# Generated by Yosys 0.9+3981 (git sha1 a3528649, clang 9.0.1-12 -fPIC -Os) autoidx 14564 attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" attribute \generator "nMigen" module \ALU_dec19 attribute \src "libresoc.v:284.3-293.6" wire width 3 $0\ALU_dec19_cr_in[2:0] attribute \src "libresoc.v:294.3-303.6" wire width 3 $0\ALU_dec19_cr_out[2:0] attribute \src "libresoc.v:324.3-333.6" wire width 2 $0\ALU_dec19_cry_in[1:0] attribute \src "libresoc.v:224.3-233.6" wire $0\ALU_dec19_cry_out[0:0] attribute \src "libresoc.v:194.3-203.6" wire width 14 $0\ALU_dec19_function_unit[13:0] attribute \src "libresoc.v:264.3-273.6" wire width 3 $0\ALU_dec19_in1_sel[2:0] attribute \src "libresoc.v:274.3-283.6" wire width 4 $0\ALU_dec19_in2_sel[3:0] attribute \src "libresoc.v:254.3-263.6" wire width 7 $0\ALU_dec19_internal_op[6:0] attribute \src "libresoc.v:204.3-213.6" wire $0\ALU_dec19_inv_a[0:0] attribute \src "libresoc.v:214.3-223.6" wire $0\ALU_dec19_inv_out[0:0] attribute \src "libresoc.v:234.3-243.6" wire $0\ALU_dec19_is_32b[0:0] attribute \src "libresoc.v:304.3-313.6" wire width 4 $0\ALU_dec19_ldst_len[3:0] attribute \src "libresoc.v:314.3-323.6" wire width 2 $0\ALU_dec19_rc_sel[1:0] attribute \src "libresoc.v:244.3-253.6" wire $0\ALU_dec19_sgn[0:0] attribute \src "libresoc.v:6.7-6.20" wire $0\initial[0:0] attribute \src "libresoc.v:284.3-293.6" wire width 3 $1\ALU_dec19_cr_in[2:0] attribute \src "libresoc.v:294.3-303.6" wire width 3 $1\ALU_dec19_cr_out[2:0] attribute \src "libresoc.v:324.3-333.6" wire width 2 $1\ALU_dec19_cry_in[1:0] attribute \src "libresoc.v:224.3-233.6" wire $1\ALU_dec19_cry_out[0:0] attribute \src "libresoc.v:194.3-203.6" wire width 14 $1\ALU_dec19_function_unit[13:0] attribute \src "libresoc.v:264.3-273.6" wire width 3 $1\ALU_dec19_in1_sel[2:0] attribute \src "libresoc.v:274.3-283.6" wire width 4 $1\ALU_dec19_in2_sel[3:0] attribute \src "libresoc.v:254.3-263.6" wire width 7 $1\ALU_dec19_internal_op[6:0] attribute \src "libresoc.v:204.3-213.6" wire $1\ALU_dec19_inv_a[0:0] attribute \src "libresoc.v:214.3-223.6" wire $1\ALU_dec19_inv_out[0:0] attribute \src "libresoc.v:234.3-243.6" wire $1\ALU_dec19_is_32b[0:0] attribute \src "libresoc.v:304.3-313.6" wire width 4 $1\ALU_dec19_ldst_len[3:0] attribute \src "libresoc.v:314.3-323.6" wire width 2 $1\ALU_dec19_rc_sel[1:0] attribute \src "libresoc.v:244.3-253.6" wire $1\ALU_dec19_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec19_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec19_sgn attribute \src "libresoc.v:6.7-6.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:194.3-203.6" process $proc$libresoc.v:194$1 assign { } { } assign { } { } assign $0\ALU_dec19_function_unit[13:0] $1\ALU_dec19_function_unit[13:0] attribute \src "libresoc.v:195.5-195.29" switch \initial attribute \src "libresoc.v:195.9-195.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_function_unit[13:0] 14'00000000000010 case assign $1\ALU_dec19_function_unit[13:0] 14'00000000000000 end sync always update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[13:0] end attribute \src "libresoc.v:204.3-213.6" process $proc$libresoc.v:204$2 assign { } { } assign { } { } assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] attribute \src "libresoc.v:205.5-205.29" switch \initial attribute \src "libresoc.v:205.9-205.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_inv_a[0:0] 1'0 case assign $1\ALU_dec19_inv_a[0:0] 1'0 end sync always update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] end attribute \src "libresoc.v:214.3-223.6" process $proc$libresoc.v:214$3 assign { } { } assign { } { } assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] attribute \src "libresoc.v:215.5-215.29" switch \initial attribute \src "libresoc.v:215.9-215.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_inv_out[0:0] 1'0 case assign $1\ALU_dec19_inv_out[0:0] 1'0 end sync always update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] end attribute \src "libresoc.v:224.3-233.6" process $proc$libresoc.v:224$4 assign { } { } assign { } { } assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] attribute \src "libresoc.v:225.5-225.29" switch \initial attribute \src "libresoc.v:225.9-225.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_cry_out[0:0] 1'0 case assign $1\ALU_dec19_cry_out[0:0] 1'0 end sync always update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] end attribute \src "libresoc.v:234.3-243.6" process $proc$libresoc.v:234$5 assign { } { } assign { } { } assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] attribute \src "libresoc.v:235.5-235.29" switch \initial attribute \src "libresoc.v:235.9-235.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_is_32b[0:0] 1'0 case assign $1\ALU_dec19_is_32b[0:0] 1'0 end sync always update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] end attribute \src "libresoc.v:244.3-253.6" process $proc$libresoc.v:244$6 assign { } { } assign { } { } assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] attribute \src "libresoc.v:245.5-245.29" switch \initial attribute \src "libresoc.v:245.9-245.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_sgn[0:0] 1'0 case assign $1\ALU_dec19_sgn[0:0] 1'0 end sync always update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] end attribute \src "libresoc.v:254.3-263.6" process $proc$libresoc.v:254$7 assign { } { } assign { } { } assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] attribute \src "libresoc.v:255.5-255.29" switch \initial attribute \src "libresoc.v:255.9-255.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_internal_op[6:0] 7'0100100 case assign $1\ALU_dec19_internal_op[6:0] 7'0000000 end sync always update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] end attribute \src "libresoc.v:264.3-273.6" process $proc$libresoc.v:264$8 assign { } { } assign { } { } assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] attribute \src "libresoc.v:265.5-265.29" switch \initial attribute \src "libresoc.v:265.9-265.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_in1_sel[2:0] 3'000 case assign $1\ALU_dec19_in1_sel[2:0] 3'000 end sync always update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] end attribute \src "libresoc.v:274.3-283.6" process $proc$libresoc.v:274$9 assign { } { } assign { } { } assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] attribute \src "libresoc.v:275.5-275.29" switch \initial attribute \src "libresoc.v:275.9-275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_in2_sel[3:0] 4'0000 case assign $1\ALU_dec19_in2_sel[3:0] 4'0000 end sync always update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] end attribute \src "libresoc.v:284.3-293.6" process $proc$libresoc.v:284$10 assign { } { } assign { } { } assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] attribute \src "libresoc.v:285.5-285.29" switch \initial attribute \src "libresoc.v:285.9-285.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_cr_in[2:0] 3'000 case assign $1\ALU_dec19_cr_in[2:0] 3'000 end sync always update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] end attribute \src "libresoc.v:294.3-303.6" process $proc$libresoc.v:294$11 assign { } { } assign { } { } assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] attribute \src "libresoc.v:295.5-295.29" switch \initial attribute \src "libresoc.v:295.9-295.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_cr_out[2:0] 3'000 case assign $1\ALU_dec19_cr_out[2:0] 3'000 end sync always update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] end attribute \src "libresoc.v:304.3-313.6" process $proc$libresoc.v:304$12 assign { } { } assign { } { } assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] attribute \src "libresoc.v:305.5-305.29" switch \initial attribute \src "libresoc.v:305.9-305.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_ldst_len[3:0] 4'0000 case assign $1\ALU_dec19_ldst_len[3:0] 4'0000 end sync always update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] end attribute \src "libresoc.v:314.3-323.6" process $proc$libresoc.v:314$13 assign { } { } assign { } { } assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] attribute \src "libresoc.v:315.5-315.29" switch \initial attribute \src "libresoc.v:315.9-315.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_rc_sel[1:0] 2'00 case assign $1\ALU_dec19_rc_sel[1:0] 2'00 end sync always update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] end attribute \src "libresoc.v:324.3-333.6" process $proc$libresoc.v:324$14 assign { } { } assign { } { } assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] attribute \src "libresoc.v:325.5-325.29" switch \initial attribute \src "libresoc.v:325.9-325.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\ALU_dec19_cry_in[1:0] 2'00 case assign $1\ALU_dec19_cry_in[1:0] 2'00 end sync always update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] end attribute \src "libresoc.v:6.7-6.20" process $proc$libresoc.v:6$15 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:339.1-1785.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" attribute \generator "nMigen" module \ALU_dec31 attribute \src "libresoc.v:1492.3-1513.6" wire width 3 $0\ALU_dec31_cr_in[2:0] attribute \src "libresoc.v:1514.3-1535.6" wire width 3 $0\ALU_dec31_cr_out[2:0] attribute \src "libresoc.v:1580.3-1601.6" wire width 2 $0\ALU_dec31_cry_in[1:0] attribute \src "libresoc.v:1646.3-1667.6" wire $0\ALU_dec31_cry_out[0:0] attribute \src "libresoc.v:1712.3-1733.6" wire width 14 $0\ALU_dec31_function_unit[13:0] attribute \src "libresoc.v:1756.3-1777.6" wire width 3 $0\ALU_dec31_in1_sel[2:0] attribute \src "libresoc.v:1470.3-1491.6" wire width 4 $0\ALU_dec31_in2_sel[3:0] attribute \src "libresoc.v:1734.3-1755.6" wire width 7 $0\ALU_dec31_internal_op[6:0] attribute \src "libresoc.v:1602.3-1623.6" wire $0\ALU_dec31_inv_a[0:0] attribute \src "libresoc.v:1624.3-1645.6" wire $0\ALU_dec31_inv_out[0:0] attribute \src "libresoc.v:1668.3-1689.6" wire $0\ALU_dec31_is_32b[0:0] attribute \src "libresoc.v:1536.3-1557.6" wire width 4 $0\ALU_dec31_ldst_len[3:0] attribute \src "libresoc.v:1558.3-1579.6" wire width 2 $0\ALU_dec31_rc_sel[1:0] attribute \src "libresoc.v:1690.3-1711.6" wire $0\ALU_dec31_sgn[0:0] attribute \src "libresoc.v:340.7-340.20" wire $0\initial[0:0] attribute \src "libresoc.v:1492.3-1513.6" wire width 3 $1\ALU_dec31_cr_in[2:0] attribute \src "libresoc.v:1514.3-1535.6" wire width 3 $1\ALU_dec31_cr_out[2:0] attribute \src "libresoc.v:1580.3-1601.6" wire width 2 $1\ALU_dec31_cry_in[1:0] attribute \src "libresoc.v:1646.3-1667.6" wire $1\ALU_dec31_cry_out[0:0] attribute \src "libresoc.v:1712.3-1733.6" wire width 14 $1\ALU_dec31_function_unit[13:0] attribute \src "libresoc.v:1756.3-1777.6" wire width 3 $1\ALU_dec31_in1_sel[2:0] attribute \src "libresoc.v:1470.3-1491.6" wire width 4 $1\ALU_dec31_in2_sel[3:0] attribute \src "libresoc.v:1734.3-1755.6" wire width 7 $1\ALU_dec31_internal_op[6:0] attribute \src "libresoc.v:1602.3-1623.6" wire $1\ALU_dec31_inv_a[0:0] attribute \src "libresoc.v:1624.3-1645.6" wire $1\ALU_dec31_inv_out[0:0] attribute \src "libresoc.v:1668.3-1689.6" wire $1\ALU_dec31_is_32b[0:0] attribute \src "libresoc.v:1536.3-1557.6" wire width 4 $1\ALU_dec31_ldst_len[3:0] attribute \src "libresoc.v:1558.3-1579.6" wire width 2 $1\ALU_dec31_rc_sel[1:0] attribute \src "libresoc.v:1690.3-1711.6" wire $1\ALU_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub10_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 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"OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_dec_sub8_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_sgn attribute \src "libresoc.v:340.7-340.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:1385.22-1401.4" cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn connect \opcode_in \ALU_dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:1402.23-1418.4" cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn connect \opcode_in \ALU_dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:1419.23-1435.4" cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn connect \opcode_in \ALU_dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:1436.23-1452.4" cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn connect \opcode_in \ALU_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:1453.22-1469.4" cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn connect \opcode_in \ALU_dec31_dec_sub8_opcode_in end attribute \src "libresoc.v:1470.3-1491.6" process $proc$libresoc.v:1470$16 assign { } { } assign { } { } assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] attribute \src "libresoc.v:1471.5-1471.29" switch \initial attribute \src "libresoc.v:1471.9-1471.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel case assign $1\ALU_dec31_in2_sel[3:0] 4'0000 end sync always update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] end attribute \src "libresoc.v:1492.3-1513.6" process $proc$libresoc.v:1492$17 assign { } { } assign { } { } assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] attribute \src "libresoc.v:1493.5-1493.29" switch \initial attribute \src "libresoc.v:1493.9-1493.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in case assign $1\ALU_dec31_cr_in[2:0] 3'000 end sync always update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] end attribute \src "libresoc.v:1514.3-1535.6" process $proc$libresoc.v:1514$18 assign { } { } assign { } { } assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] attribute \src "libresoc.v:1515.5-1515.29" switch \initial attribute \src "libresoc.v:1515.9-1515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out case assign $1\ALU_dec31_cr_out[2:0] 3'000 end sync always update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] end attribute \src "libresoc.v:1536.3-1557.6" process $proc$libresoc.v:1536$19 assign { } { } assign { } { } assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] attribute \src "libresoc.v:1537.5-1537.29" switch \initial attribute \src "libresoc.v:1537.9-1537.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len case assign $1\ALU_dec31_ldst_len[3:0] 4'0000 end sync always update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] end attribute \src "libresoc.v:1558.3-1579.6" process $proc$libresoc.v:1558$20 assign { } { } assign { } { } assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] attribute \src "libresoc.v:1559.5-1559.29" switch \initial attribute \src "libresoc.v:1559.9-1559.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel case assign $1\ALU_dec31_rc_sel[1:0] 2'00 end sync always update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] end attribute \src "libresoc.v:1580.3-1601.6" process $proc$libresoc.v:1580$21 assign { } { } assign { } { } assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] attribute \src "libresoc.v:1581.5-1581.29" switch \initial attribute \src "libresoc.v:1581.9-1581.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in case assign $1\ALU_dec31_cry_in[1:0] 2'00 end sync always update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] end attribute \src "libresoc.v:1602.3-1623.6" process $proc$libresoc.v:1602$22 assign { } { } assign { } { } assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] attribute \src "libresoc.v:1603.5-1603.29" switch \initial attribute \src "libresoc.v:1603.9-1603.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a case assign $1\ALU_dec31_inv_a[0:0] 1'0 end sync always update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] end attribute \src "libresoc.v:1624.3-1645.6" process $proc$libresoc.v:1624$23 assign { } { } assign { } { } assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] attribute \src "libresoc.v:1625.5-1625.29" switch \initial attribute \src "libresoc.v:1625.9-1625.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out case assign $1\ALU_dec31_inv_out[0:0] 1'0 end sync always update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] end attribute \src "libresoc.v:1646.3-1667.6" process $proc$libresoc.v:1646$24 assign { } { } assign { } { } assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] attribute \src "libresoc.v:1647.5-1647.29" switch \initial attribute \src "libresoc.v:1647.9-1647.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out case assign $1\ALU_dec31_cry_out[0:0] 1'0 end sync always update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] end attribute \src "libresoc.v:1668.3-1689.6" process $proc$libresoc.v:1668$25 assign { } { } assign { } { } assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] attribute \src "libresoc.v:1669.5-1669.29" switch \initial attribute \src "libresoc.v:1669.9-1669.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b case assign $1\ALU_dec31_is_32b[0:0] 1'0 end sync always update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] end attribute \src "libresoc.v:1690.3-1711.6" process $proc$libresoc.v:1690$26 assign { } { } assign { } { } assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] attribute \src "libresoc.v:1691.5-1691.29" switch \initial attribute \src "libresoc.v:1691.9-1691.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn case assign $1\ALU_dec31_sgn[0:0] 1'0 end sync always update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] end attribute \src "libresoc.v:1712.3-1733.6" process $proc$libresoc.v:1712$27 assign { } { } assign { } { } assign $0\ALU_dec31_function_unit[13:0] $1\ALU_dec31_function_unit[13:0] attribute \src "libresoc.v:1713.5-1713.29" switch \initial attribute \src "libresoc.v:1713.9-1713.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_function_unit[13:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit case assign $1\ALU_dec31_function_unit[13:0] 14'00000000000000 end sync always update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[13:0] end attribute \src "libresoc.v:1734.3-1755.6" process $proc$libresoc.v:1734$28 assign { } { } assign { } { } assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] attribute \src "libresoc.v:1735.5-1735.29" switch \initial attribute \src "libresoc.v:1735.9-1735.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op case assign $1\ALU_dec31_internal_op[6:0] 7'0000000 end sync always update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] end attribute \src "libresoc.v:1756.3-1777.6" process $proc$libresoc.v:1756$29 assign { } { } assign { } { } assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] attribute \src "libresoc.v:1757.5-1757.29" switch \initial attribute \src "libresoc.v:1757.9-1757.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel case assign $1\ALU_dec31_in1_sel[2:0] 3'000 end sync always update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] end attribute \src "libresoc.v:340.7-340.20" process $proc$libresoc.v:340$30 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end connect \ALU_dec31_dec_sub8_opcode_in \opcode_in connect \ALU_dec31_dec_sub22_opcode_in \opcode_in connect \ALU_dec31_dec_sub26_opcode_in \opcode_in connect \ALU_dec31_dec_sub0_opcode_in \opcode_in connect \ALU_dec31_dec_sub10_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:1789.1-2203.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" attribute \generator "nMigen" module \ALU_dec31_dec_sub0 attribute \src "libresoc.v:2122.3-2137.6" wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:2138.3-2153.6" wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:2186.3-2201.6" wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] attribute \src "libresoc.v:2026.3-2041.6" wire $0\ALU_dec31_dec_sub0_cry_out[0:0] attribute \src "libresoc.v:1978.3-1993.6" wire width 14 $0\ALU_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:2090.3-2105.6" wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] attribute \src "libresoc.v:2106.3-2121.6" wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] attribute \src "libresoc.v:2074.3-2089.6" wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:1994.3-2009.6" wire $0\ALU_dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:2010.3-2025.6" wire $0\ALU_dec31_dec_sub0_inv_out[0:0] attribute \src "libresoc.v:2042.3-2057.6" wire $0\ALU_dec31_dec_sub0_is_32b[0:0] attribute \src "libresoc.v:2154.3-2169.6" wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:2170.3-2185.6" wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:2058.3-2073.6" wire $0\ALU_dec31_dec_sub0_sgn[0:0] attribute \src "libresoc.v:1790.7-1790.20" wire $0\initial[0:0] attribute \src "libresoc.v:2122.3-2137.6" wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:2138.3-2153.6" wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:2186.3-2201.6" wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] attribute \src "libresoc.v:2026.3-2041.6" wire $1\ALU_dec31_dec_sub0_cry_out[0:0] attribute \src "libresoc.v:1978.3-1993.6" wire width 14 $1\ALU_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:2090.3-2105.6" wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] attribute \src "libresoc.v:2106.3-2121.6" wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] attribute \src "libresoc.v:2074.3-2089.6" wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:1994.3-2009.6" wire $1\ALU_dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:2010.3-2025.6" wire $1\ALU_dec31_dec_sub0_inv_out[0:0] attribute \src "libresoc.v:2042.3-2057.6" wire $1\ALU_dec31_dec_sub0_is_32b[0:0] attribute \src "libresoc.v:2154.3-2169.6" wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:2170.3-2185.6" wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:2058.3-2073.6" wire $1\ALU_dec31_dec_sub0_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub0_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub0_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub0_sgn attribute \src "libresoc.v:1790.7-1790.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:1790.7-1790.20" process $proc$libresoc.v:1790$45 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:1978.3-1993.6" process $proc$libresoc.v:1978$31 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_function_unit[13:0] $1\ALU_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:1979.5-1979.29" switch \initial attribute \src "libresoc.v:1979.9-1979.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000010 case assign $1\ALU_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[13:0] end attribute \src "libresoc.v:1994.3-2009.6" process $proc$libresoc.v:1994$32 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:1995.5-1995.29" switch \initial attribute \src "libresoc.v:1995.9-1995.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 case assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 end sync always update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] end attribute \src "libresoc.v:2010.3-2025.6" process $proc$libresoc.v:2010$33 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] attribute \src "libresoc.v:2011.5-2011.29" switch \initial attribute \src "libresoc.v:2011.9-2011.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] end attribute \src "libresoc.v:2026.3-2041.6" process $proc$libresoc.v:2026$34 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] attribute \src "libresoc.v:2027.5-2027.29" switch \initial attribute \src "libresoc.v:2027.9-2027.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] end attribute \src "libresoc.v:2042.3-2057.6" process $proc$libresoc.v:2042$35 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] attribute \src "libresoc.v:2043.5-2043.29" switch \initial attribute \src "libresoc.v:2043.9-2043.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 case assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 end sync always update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] end attribute \src "libresoc.v:2058.3-2073.6" process $proc$libresoc.v:2058$36 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] attribute \src "libresoc.v:2059.5-2059.29" switch \initial attribute \src "libresoc.v:2059.9-2059.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 case assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 end sync always update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] end attribute \src "libresoc.v:2074.3-2089.6" process $proc$libresoc.v:2074$37 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:2075.5-2075.29" switch \initial attribute \src "libresoc.v:2075.9-2075.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 case assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 end sync always update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] end attribute \src "libresoc.v:2090.3-2105.6" process $proc$libresoc.v:2090$38 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] attribute \src "libresoc.v:2091.5-2091.29" switch \initial attribute \src "libresoc.v:2091.9-2091.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 case assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 end sync always update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] end attribute \src "libresoc.v:2106.3-2121.6" process $proc$libresoc.v:2106$39 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] attribute \src "libresoc.v:2107.5-2107.29" switch \initial attribute \src "libresoc.v:2107.9-2107.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 case assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] end attribute \src "libresoc.v:2122.3-2137.6" process $proc$libresoc.v:2122$40 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:2123.5-2123.29" switch \initial attribute \src "libresoc.v:2123.9-2123.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 case assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 end sync always update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] end attribute \src "libresoc.v:2138.3-2153.6" process $proc$libresoc.v:2138$41 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:2139.5-2139.29" switch \initial attribute \src "libresoc.v:2139.9-2139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 case assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 end sync always update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] end attribute \src "libresoc.v:2154.3-2169.6" process $proc$libresoc.v:2154$42 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:2155.5-2155.29" switch \initial attribute \src "libresoc.v:2155.9-2155.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] end attribute \src "libresoc.v:2170.3-2185.6" process $proc$libresoc.v:2170$43 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:2171.5-2171.29" switch \initial attribute \src "libresoc.v:2171.9-2171.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 case assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 end sync always update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] end attribute \src "libresoc.v:2186.3-2201.6" process $proc$libresoc.v:2186$44 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] attribute \src "libresoc.v:2187.5-2187.29" switch \initial attribute \src "libresoc.v:2187.9-2187.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 case assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 end sync always update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:2207.1-2915.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" attribute \generator "nMigen" module \ALU_dec31_dec_sub10 attribute \src "libresoc.v:2729.3-2765.6" wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] attribute \src "libresoc.v:2766.3-2802.6" wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] attribute \src "libresoc.v:2877.3-2913.6" wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] attribute \src "libresoc.v:2507.3-2543.6" wire $0\ALU_dec31_dec_sub10_cry_out[0:0] attribute \src "libresoc.v:2396.3-2432.6" wire width 14 $0\ALU_dec31_dec_sub10_function_unit[13:0] attribute \src "libresoc.v:2655.3-2691.6" wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] attribute \src "libresoc.v:2692.3-2728.6" wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] attribute \src "libresoc.v:2618.3-2654.6" wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] attribute \src "libresoc.v:2433.3-2469.6" wire $0\ALU_dec31_dec_sub10_inv_a[0:0] attribute \src "libresoc.v:2470.3-2506.6" wire $0\ALU_dec31_dec_sub10_inv_out[0:0] attribute \src "libresoc.v:2544.3-2580.6" wire $0\ALU_dec31_dec_sub10_is_32b[0:0] attribute \src "libresoc.v:2803.3-2839.6" wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] attribute \src "libresoc.v:2840.3-2876.6" wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] attribute \src "libresoc.v:2581.3-2617.6" wire $0\ALU_dec31_dec_sub10_sgn[0:0] attribute \src "libresoc.v:2208.7-2208.20" wire $0\initial[0:0] attribute \src "libresoc.v:2729.3-2765.6" wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] attribute \src "libresoc.v:2766.3-2802.6" wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] attribute \src "libresoc.v:2877.3-2913.6" wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] attribute \src "libresoc.v:2507.3-2543.6" wire $1\ALU_dec31_dec_sub10_cry_out[0:0] attribute \src "libresoc.v:2396.3-2432.6" wire width 14 $1\ALU_dec31_dec_sub10_function_unit[13:0] attribute \src "libresoc.v:2655.3-2691.6" wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] attribute \src "libresoc.v:2692.3-2728.6" wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] attribute \src "libresoc.v:2618.3-2654.6" wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] attribute \src "libresoc.v:2433.3-2469.6" wire $1\ALU_dec31_dec_sub10_inv_a[0:0] attribute \src "libresoc.v:2470.3-2506.6" wire $1\ALU_dec31_dec_sub10_inv_out[0:0] attribute \src "libresoc.v:2544.3-2580.6" wire $1\ALU_dec31_dec_sub10_is_32b[0:0] attribute \src "libresoc.v:2803.3-2839.6" wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] attribute \src "libresoc.v:2840.3-2876.6" wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] attribute \src "libresoc.v:2581.3-2617.6" wire $1\ALU_dec31_dec_sub10_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub10_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub10_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub10_sgn attribute \src "libresoc.v:2208.7-2208.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:2208.7-2208.20" process $proc$libresoc.v:2208$60 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:2396.3-2432.6" process $proc$libresoc.v:2396$46 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_function_unit[13:0] $1\ALU_dec31_dec_sub10_function_unit[13:0] attribute \src "libresoc.v:2397.5-2397.29" switch \initial attribute \src "libresoc.v:2397.9-2397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000010 case assign $1\ALU_dec31_dec_sub10_function_unit[13:0] 14'00000000000000 end sync always update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[13:0] end attribute \src "libresoc.v:2433.3-2469.6" process $proc$libresoc.v:2433$47 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] attribute \src "libresoc.v:2434.5-2434.29" switch \initial attribute \src "libresoc.v:2434.9-2434.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 case assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 end sync always update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] end attribute \src "libresoc.v:2470.3-2506.6" process $proc$libresoc.v:2470$48 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] attribute \src "libresoc.v:2471.5-2471.29" switch \initial attribute \src "libresoc.v:2471.9-2471.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] end attribute \src "libresoc.v:2507.3-2543.6" process $proc$libresoc.v:2507$49 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] attribute \src "libresoc.v:2508.5-2508.29" switch \initial attribute \src "libresoc.v:2508.9-2508.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 case assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] end attribute \src "libresoc.v:2544.3-2580.6" process $proc$libresoc.v:2544$50 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] attribute \src "libresoc.v:2545.5-2545.29" switch \initial attribute \src "libresoc.v:2545.9-2545.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 case assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 end sync always update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] end attribute \src "libresoc.v:2581.3-2617.6" process $proc$libresoc.v:2581$51 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] attribute \src "libresoc.v:2582.5-2582.29" switch \initial attribute \src "libresoc.v:2582.9-2582.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 case assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 end sync always update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] end attribute \src "libresoc.v:2618.3-2654.6" process $proc$libresoc.v:2618$52 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] attribute \src "libresoc.v:2619.5-2619.29" switch \initial attribute \src "libresoc.v:2619.9-2619.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 case assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 end sync always update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] end attribute \src "libresoc.v:2655.3-2691.6" process $proc$libresoc.v:2655$53 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] attribute \src "libresoc.v:2656.5-2656.29" switch \initial attribute \src "libresoc.v:2656.9-2656.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 case assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 end sync always update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] end attribute \src "libresoc.v:2692.3-2728.6" process $proc$libresoc.v:2692$54 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] attribute \src "libresoc.v:2693.5-2693.29" switch \initial attribute \src "libresoc.v:2693.9-2693.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] end attribute \src "libresoc.v:2729.3-2765.6" process $proc$libresoc.v:2729$55 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] attribute \src "libresoc.v:2730.5-2730.29" switch \initial attribute \src "libresoc.v:2730.9-2730.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 case assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 end sync always update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] end attribute \src "libresoc.v:2766.3-2802.6" process $proc$libresoc.v:2766$56 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] attribute \src "libresoc.v:2767.5-2767.29" switch \initial attribute \src "libresoc.v:2767.9-2767.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 case assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 end sync always update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] end attribute \src "libresoc.v:2803.3-2839.6" process $proc$libresoc.v:2803$57 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] attribute \src "libresoc.v:2804.5-2804.29" switch \initial attribute \src "libresoc.v:2804.9-2804.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] end attribute \src "libresoc.v:2840.3-2876.6" process $proc$libresoc.v:2840$58 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] attribute \src "libresoc.v:2841.5-2841.29" switch \initial attribute \src "libresoc.v:2841.9-2841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 case assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 end sync always update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] end attribute \src "libresoc.v:2877.3-2913.6" process $proc$libresoc.v:2877$59 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] attribute \src "libresoc.v:2878.5-2878.29" switch \initial attribute \src "libresoc.v:2878.9-2878.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 case assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 end sync always update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:2919.1-3501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" attribute \generator "nMigen" module \ALU_dec31_dec_sub22 attribute \src "libresoc.v:3360.3-3387.6" wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:3388.3-3415.6" wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:3472.3-3499.6" wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] attribute \src "libresoc.v:3192.3-3219.6" wire $0\ALU_dec31_dec_sub22_cry_out[0:0] attribute \src "libresoc.v:3108.3-3135.6" wire width 14 $0\ALU_dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:3304.3-3331.6" wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:3332.3-3359.6" wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:3276.3-3303.6" wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:3136.3-3163.6" wire $0\ALU_dec31_dec_sub22_inv_a[0:0] attribute \src "libresoc.v:3164.3-3191.6" wire $0\ALU_dec31_dec_sub22_inv_out[0:0] attribute \src "libresoc.v:3220.3-3247.6" wire $0\ALU_dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:3416.3-3443.6" wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:3444.3-3471.6" wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:3248.3-3275.6" wire $0\ALU_dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:2920.7-2920.20" wire $0\initial[0:0] attribute \src "libresoc.v:3360.3-3387.6" wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:3388.3-3415.6" wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:3472.3-3499.6" wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] attribute \src "libresoc.v:3192.3-3219.6" wire $1\ALU_dec31_dec_sub22_cry_out[0:0] attribute \src "libresoc.v:3108.3-3135.6" wire width 14 $1\ALU_dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:3304.3-3331.6" wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:3332.3-3359.6" wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:3276.3-3303.6" wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:3136.3-3163.6" wire $1\ALU_dec31_dec_sub22_inv_a[0:0] attribute \src "libresoc.v:3164.3-3191.6" wire $1\ALU_dec31_dec_sub22_inv_out[0:0] attribute \src "libresoc.v:3220.3-3247.6" wire $1\ALU_dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:3416.3-3443.6" wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:3444.3-3471.6" wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:3248.3-3275.6" wire $1\ALU_dec31_dec_sub22_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub22_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub22_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub22_sgn attribute \src "libresoc.v:2920.7-2920.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:2920.7-2920.20" process $proc$libresoc.v:2920$75 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:3108.3-3135.6" process $proc$libresoc.v:3108$61 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_function_unit[13:0] $1\ALU_dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:3109.5-3109.29" switch \initial attribute \src "libresoc.v:3109.9-3109.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000010 case assign $1\ALU_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[13:0] end attribute \src "libresoc.v:3136.3-3163.6" process $proc$libresoc.v:3136$62 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] attribute \src "libresoc.v:3137.5-3137.29" switch \initial attribute \src "libresoc.v:3137.9-3137.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 case assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 end sync always update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] end attribute \src "libresoc.v:3164.3-3191.6" process $proc$libresoc.v:3164$63 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] attribute \src "libresoc.v:3165.5-3165.29" switch \initial attribute \src "libresoc.v:3165.9-3165.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] end attribute \src "libresoc.v:3192.3-3219.6" process $proc$libresoc.v:3192$64 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] attribute \src "libresoc.v:3193.5-3193.29" switch \initial attribute \src "libresoc.v:3193.9-3193.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] end attribute \src "libresoc.v:3220.3-3247.6" process $proc$libresoc.v:3220$65 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:3221.5-3221.29" switch \initial attribute \src "libresoc.v:3221.9-3221.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 case assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 end sync always update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] end attribute \src "libresoc.v:3248.3-3275.6" process $proc$libresoc.v:3248$66 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:3249.5-3249.29" switch \initial attribute \src "libresoc.v:3249.9-3249.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 case assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 end sync always update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] end attribute \src "libresoc.v:3276.3-3303.6" process $proc$libresoc.v:3276$67 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:3277.5-3277.29" switch \initial attribute \src "libresoc.v:3277.9-3277.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 case assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 end sync always update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] end attribute \src "libresoc.v:3304.3-3331.6" process $proc$libresoc.v:3304$68 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:3305.5-3305.29" switch \initial attribute \src "libresoc.v:3305.9-3305.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 case assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 end sync always update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] end attribute \src "libresoc.v:3332.3-3359.6" process $proc$libresoc.v:3332$69 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:3333.5-3333.29" switch \initial attribute \src "libresoc.v:3333.9-3333.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] end attribute \src "libresoc.v:3360.3-3387.6" process $proc$libresoc.v:3360$70 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:3361.5-3361.29" switch \initial attribute \src "libresoc.v:3361.9-3361.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 case assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 end sync always update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] end attribute \src "libresoc.v:3388.3-3415.6" process $proc$libresoc.v:3388$71 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:3389.5-3389.29" switch \initial attribute \src "libresoc.v:3389.9-3389.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 case assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 end sync always update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] end attribute \src "libresoc.v:3416.3-3443.6" process $proc$libresoc.v:3416$72 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:3417.5-3417.29" switch \initial attribute \src "libresoc.v:3417.9-3417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] end attribute \src "libresoc.v:3444.3-3471.6" process $proc$libresoc.v:3444$73 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:3445.5-3445.29" switch \initial attribute \src "libresoc.v:3445.9-3445.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 case assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 end sync always update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] end attribute \src "libresoc.v:3472.3-3499.6" process $proc$libresoc.v:3472$74 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] attribute \src "libresoc.v:3473.5-3473.29" switch \initial attribute \src "libresoc.v:3473.9-3473.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 case assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 end sync always update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:3505.1-3919.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" attribute \generator "nMigen" module \ALU_dec31_dec_sub26 attribute \src "libresoc.v:3838.3-3853.6" wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:3854.3-3869.6" wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:3902.3-3917.6" wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:3742.3-3757.6" wire $0\ALU_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:3694.3-3709.6" wire width 14 $0\ALU_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:3806.3-3821.6" wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:3822.3-3837.6" wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:3790.3-3805.6" wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:3710.3-3725.6" wire $0\ALU_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:3726.3-3741.6" wire $0\ALU_dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:3758.3-3773.6" wire $0\ALU_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:3870.3-3885.6" wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:3886.3-3901.6" wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:3774.3-3789.6" wire $0\ALU_dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:3506.7-3506.20" wire $0\initial[0:0] attribute \src "libresoc.v:3838.3-3853.6" wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:3854.3-3869.6" wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:3902.3-3917.6" wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:3742.3-3757.6" wire $1\ALU_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:3694.3-3709.6" wire width 14 $1\ALU_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:3806.3-3821.6" wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:3822.3-3837.6" wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:3790.3-3805.6" wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:3710.3-3725.6" wire $1\ALU_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:3726.3-3741.6" wire $1\ALU_dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:3758.3-3773.6" wire $1\ALU_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:3870.3-3885.6" wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:3886.3-3901.6" wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:3774.3-3789.6" wire $1\ALU_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub26_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub26_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub26_sgn attribute \src "libresoc.v:3506.7-3506.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:3506.7-3506.20" process $proc$libresoc.v:3506$90 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:3694.3-3709.6" process $proc$libresoc.v:3694$76 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_function_unit[13:0] $1\ALU_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:3695.5-3695.29" switch \initial attribute \src "libresoc.v:3695.9-3695.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000010 case assign $1\ALU_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[13:0] end attribute \src "libresoc.v:3710.3-3725.6" process $proc$libresoc.v:3710$77 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:3711.5-3711.29" switch \initial attribute \src "libresoc.v:3711.9-3711.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 case assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 end sync always update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] end attribute \src "libresoc.v:3726.3-3741.6" process $proc$libresoc.v:3726$78 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:3727.5-3727.29" switch \initial attribute \src "libresoc.v:3727.9-3727.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] end attribute \src "libresoc.v:3742.3-3757.6" process $proc$libresoc.v:3742$79 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:3743.5-3743.29" switch \initial attribute \src "libresoc.v:3743.9-3743.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] end attribute \src "libresoc.v:3758.3-3773.6" process $proc$libresoc.v:3758$80 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:3759.5-3759.29" switch \initial attribute \src "libresoc.v:3759.9-3759.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 case assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 end sync always update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] end attribute \src "libresoc.v:3774.3-3789.6" process $proc$libresoc.v:3774$81 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:3775.5-3775.29" switch \initial attribute \src "libresoc.v:3775.9-3775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 case assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 end sync always update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] end attribute \src "libresoc.v:3790.3-3805.6" process $proc$libresoc.v:3790$82 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:3791.5-3791.29" switch \initial attribute \src "libresoc.v:3791.9-3791.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 case assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] end attribute \src "libresoc.v:3806.3-3821.6" process $proc$libresoc.v:3806$83 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:3807.5-3807.29" switch \initial attribute \src "libresoc.v:3807.9-3807.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 case assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 end sync always update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] end attribute \src "libresoc.v:3822.3-3837.6" process $proc$libresoc.v:3822$84 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:3823.5-3823.29" switch \initial attribute \src "libresoc.v:3823.9-3823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] end attribute \src "libresoc.v:3838.3-3853.6" process $proc$libresoc.v:3838$85 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:3839.5-3839.29" switch \initial attribute \src "libresoc.v:3839.9-3839.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 case assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 end sync always update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] end attribute \src "libresoc.v:3854.3-3869.6" process $proc$libresoc.v:3854$86 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:3855.5-3855.29" switch \initial attribute \src "libresoc.v:3855.9-3855.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 case assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 end sync always update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] end attribute \src "libresoc.v:3870.3-3885.6" process $proc$libresoc.v:3870$87 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:3871.5-3871.29" switch \initial attribute \src "libresoc.v:3871.9-3871.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 case assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] end attribute \src "libresoc.v:3886.3-3901.6" process $proc$libresoc.v:3886$88 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:3887.5-3887.29" switch \initial attribute \src "libresoc.v:3887.9-3887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 case assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 end sync always update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] end attribute \src "libresoc.v:3902.3-3917.6" process $proc$libresoc.v:3902$89 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:3903.5-3903.29" switch \initial attribute \src "libresoc.v:3903.9-3903.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 case assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 end sync always update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:3923.1-4715.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" attribute \generator "nMigen" module \ALU_dec31_dec_sub8 attribute \src "libresoc.v:4499.3-4541.6" wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] attribute \src "libresoc.v:4542.3-4584.6" wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] attribute \src "libresoc.v:4671.3-4713.6" wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] attribute \src "libresoc.v:4241.3-4283.6" wire $0\ALU_dec31_dec_sub8_cry_out[0:0] attribute \src "libresoc.v:4112.3-4154.6" wire width 14 $0\ALU_dec31_dec_sub8_function_unit[13:0] attribute \src "libresoc.v:4413.3-4455.6" wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] attribute \src "libresoc.v:4456.3-4498.6" wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] attribute \src "libresoc.v:4370.3-4412.6" wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] attribute \src "libresoc.v:4155.3-4197.6" wire $0\ALU_dec31_dec_sub8_inv_a[0:0] attribute \src "libresoc.v:4198.3-4240.6" wire $0\ALU_dec31_dec_sub8_inv_out[0:0] attribute \src "libresoc.v:4284.3-4326.6" wire $0\ALU_dec31_dec_sub8_is_32b[0:0] attribute \src "libresoc.v:4585.3-4627.6" wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] attribute \src "libresoc.v:4628.3-4670.6" wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] attribute \src "libresoc.v:4327.3-4369.6" wire $0\ALU_dec31_dec_sub8_sgn[0:0] attribute \src "libresoc.v:3924.7-3924.20" wire $0\initial[0:0] attribute \src "libresoc.v:4499.3-4541.6" wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] attribute \src "libresoc.v:4542.3-4584.6" wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] attribute \src "libresoc.v:4671.3-4713.6" wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] attribute \src "libresoc.v:4241.3-4283.6" wire $1\ALU_dec31_dec_sub8_cry_out[0:0] attribute \src "libresoc.v:4112.3-4154.6" wire width 14 $1\ALU_dec31_dec_sub8_function_unit[13:0] attribute \src "libresoc.v:4413.3-4455.6" wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] attribute \src "libresoc.v:4456.3-4498.6" wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] attribute \src "libresoc.v:4370.3-4412.6" wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] attribute \src "libresoc.v:4155.3-4197.6" wire $1\ALU_dec31_dec_sub8_inv_a[0:0] attribute \src "libresoc.v:4198.3-4240.6" wire $1\ALU_dec31_dec_sub8_inv_out[0:0] attribute \src "libresoc.v:4284.3-4326.6" wire $1\ALU_dec31_dec_sub8_is_32b[0:0] attribute \src "libresoc.v:4585.3-4627.6" wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] attribute \src "libresoc.v:4628.3-4670.6" wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] attribute \src "libresoc.v:4327.3-4369.6" wire $1\ALU_dec31_dec_sub8_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \ALU_dec31_dec_sub8_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_dec31_dec_sub8_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_dec31_dec_sub8_sgn attribute \src "libresoc.v:3924.7-3924.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:3924.7-3924.20" process $proc$libresoc.v:3924$105 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:4112.3-4154.6" process $proc$libresoc.v:4112$91 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_function_unit[13:0] $1\ALU_dec31_dec_sub8_function_unit[13:0] attribute \src "libresoc.v:4113.5-4113.29" switch \initial attribute \src "libresoc.v:4113.9-4113.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000010 case assign $1\ALU_dec31_dec_sub8_function_unit[13:0] 14'00000000000000 end sync always update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[13:0] end attribute \src "libresoc.v:4155.3-4197.6" process $proc$libresoc.v:4155$92 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] attribute \src "libresoc.v:4156.5-4156.29" switch \initial attribute \src "libresoc.v:4156.9-4156.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 case assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 end sync always update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] end attribute \src "libresoc.v:4198.3-4240.6" process $proc$libresoc.v:4198$93 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] attribute \src "libresoc.v:4199.5-4199.29" switch \initial attribute \src "libresoc.v:4199.9-4199.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 case assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] end attribute \src "libresoc.v:4241.3-4283.6" process $proc$libresoc.v:4241$94 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] attribute \src "libresoc.v:4242.5-4242.29" switch \initial attribute \src "libresoc.v:4242.9-4242.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 case assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 end sync always update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] end attribute \src "libresoc.v:4284.3-4326.6" process $proc$libresoc.v:4284$95 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] attribute \src "libresoc.v:4285.5-4285.29" switch \initial attribute \src "libresoc.v:4285.9-4285.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 case assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 end sync always update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] end attribute \src "libresoc.v:4327.3-4369.6" process $proc$libresoc.v:4327$96 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] attribute \src "libresoc.v:4328.5-4328.29" switch \initial attribute \src "libresoc.v:4328.9-4328.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 case assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 end sync always update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] end attribute \src "libresoc.v:4370.3-4412.6" process $proc$libresoc.v:4370$97 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] attribute \src "libresoc.v:4371.5-4371.29" switch \initial attribute \src "libresoc.v:4371.9-4371.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 case assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 end sync always update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] end attribute \src "libresoc.v:4413.3-4455.6" process $proc$libresoc.v:4413$98 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] attribute \src "libresoc.v:4414.5-4414.29" switch \initial attribute \src "libresoc.v:4414.9-4414.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 case assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 end sync always update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] end attribute \src "libresoc.v:4456.3-4498.6" process $proc$libresoc.v:4456$99 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] attribute \src "libresoc.v:4457.5-4457.29" switch \initial attribute \src "libresoc.v:4457.9-4457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] end attribute \src "libresoc.v:4499.3-4541.6" process $proc$libresoc.v:4499$100 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] attribute \src "libresoc.v:4500.5-4500.29" switch \initial attribute \src "libresoc.v:4500.9-4500.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 case assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 end sync always update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] end attribute \src "libresoc.v:4542.3-4584.6" process $proc$libresoc.v:4542$101 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] attribute \src "libresoc.v:4543.5-4543.29" switch \initial attribute \src "libresoc.v:4543.9-4543.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 case assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 end sync always update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] end attribute \src "libresoc.v:4585.3-4627.6" process $proc$libresoc.v:4585$102 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] attribute \src "libresoc.v:4586.5-4586.29" switch \initial attribute \src "libresoc.v:4586.9-4586.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 case assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 end sync always update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] end attribute \src "libresoc.v:4628.3-4670.6" process $proc$libresoc.v:4628$103 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] attribute \src "libresoc.v:4629.5-4629.29" switch \initial attribute \src "libresoc.v:4629.9-4629.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 case assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 end sync always update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] end attribute \src "libresoc.v:4671.3-4713.6" process $proc$libresoc.v:4671$104 assign { } { } assign { } { } assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] attribute \src "libresoc.v:4672.5-4672.29" switch \initial attribute \src "libresoc.v:4672.9-4672.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 case assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 end sync always update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:4719.1-5003.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" attribute \generator "nMigen" module \BRANCH_dec19 attribute \src "libresoc.v:4922.3-4937.6" wire width 3 $0\BRANCH_dec19_cr_in[2:0] attribute \src "libresoc.v:4938.3-4953.6" wire width 3 $0\BRANCH_dec19_cr_out[2:0] attribute \src "libresoc.v:4874.3-4889.6" wire width 14 $0\BRANCH_dec19_function_unit[13:0] attribute \src "libresoc.v:4906.3-4921.6" wire width 4 $0\BRANCH_dec19_in2_sel[3:0] attribute \src "libresoc.v:4890.3-4905.6" wire width 7 $0\BRANCH_dec19_internal_op[6:0] attribute \src "libresoc.v:4970.3-4985.6" wire $0\BRANCH_dec19_is_32b[0:0] attribute \src "libresoc.v:4986.3-5001.6" wire $0\BRANCH_dec19_lk[0:0] attribute \src "libresoc.v:4954.3-4969.6" wire width 2 $0\BRANCH_dec19_rc_sel[1:0] attribute \src "libresoc.v:4720.7-4720.20" wire $0\initial[0:0] attribute \src "libresoc.v:4922.3-4937.6" wire width 3 $1\BRANCH_dec19_cr_in[2:0] attribute \src "libresoc.v:4938.3-4953.6" wire width 3 $1\BRANCH_dec19_cr_out[2:0] attribute \src "libresoc.v:4874.3-4889.6" wire width 14 $1\BRANCH_dec19_function_unit[13:0] attribute \src "libresoc.v:4906.3-4921.6" wire width 4 $1\BRANCH_dec19_in2_sel[3:0] attribute \src "libresoc.v:4890.3-4905.6" wire width 7 $1\BRANCH_dec19_internal_op[6:0] attribute \src "libresoc.v:4970.3-4985.6" wire $1\BRANCH_dec19_is_32b[0:0] attribute \src "libresoc.v:4986.3-5001.6" wire $1\BRANCH_dec19_lk[0:0] attribute \src "libresoc.v:4954.3-4969.6" wire width 2 $1\BRANCH_dec19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \BRANCH_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \BRANCH_dec19_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \BRANCH_dec19_rc_sel attribute \src "libresoc.v:4720.7-4720.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:4720.7-4720.20" process $proc$libresoc.v:4720$114 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:4874.3-4889.6" process $proc$libresoc.v:4874$106 assign { } { } assign { } { } assign $0\BRANCH_dec19_function_unit[13:0] $1\BRANCH_dec19_function_unit[13:0] attribute \src "libresoc.v:4875.5-4875.29" switch \initial attribute \src "libresoc.v:4875.9-4875.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000100000 case assign $1\BRANCH_dec19_function_unit[13:0] 14'00000000000000 end sync always update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[13:0] end attribute \src "libresoc.v:4890.3-4905.6" process $proc$libresoc.v:4890$107 assign { } { } assign { } { } assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] attribute \src "libresoc.v:4891.5-4891.29" switch \initial attribute \src "libresoc.v:4891.9-4891.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 case assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 end sync always update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] end attribute \src "libresoc.v:4906.3-4921.6" process $proc$libresoc.v:4906$108 assign { } { } assign { } { } assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] attribute \src "libresoc.v:4907.5-4907.29" switch \initial attribute \src "libresoc.v:4907.9-4907.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 case assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 end sync always update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] end attribute \src "libresoc.v:4922.3-4937.6" process $proc$libresoc.v:4922$109 assign { } { } assign { } { } assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] attribute \src "libresoc.v:4923.5-4923.29" switch \initial attribute \src "libresoc.v:4923.9-4923.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_cr_in[2:0] 3'010 case assign $1\BRANCH_dec19_cr_in[2:0] 3'000 end sync always update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] end attribute \src "libresoc.v:4938.3-4953.6" process $proc$libresoc.v:4938$110 assign { } { } assign { } { } assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] attribute \src "libresoc.v:4939.5-4939.29" switch \initial attribute \src "libresoc.v:4939.9-4939.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_cr_out[2:0] 3'000 case assign $1\BRANCH_dec19_cr_out[2:0] 3'000 end sync always update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] end attribute \src "libresoc.v:4954.3-4969.6" process $proc$libresoc.v:4954$111 assign { } { } assign { } { } assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] attribute \src "libresoc.v:4955.5-4955.29" switch \initial attribute \src "libresoc.v:4955.9-4955.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 case assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 end sync always update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] end attribute \src "libresoc.v:4970.3-4985.6" process $proc$libresoc.v:4970$112 assign { } { } assign { } { } assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] attribute \src "libresoc.v:4971.5-4971.29" switch \initial attribute \src "libresoc.v:4971.9-4971.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_is_32b[0:0] 1'0 case assign $1\BRANCH_dec19_is_32b[0:0] 1'0 end sync always update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] end attribute \src "libresoc.v:4986.3-5001.6" process $proc$libresoc.v:4986$113 assign { } { } assign { } { } assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] attribute \src "libresoc.v:4987.5-4987.29" switch \initial attribute \src "libresoc.v:4987.9-4987.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\BRANCH_dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\BRANCH_dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\BRANCH_dec19_lk[0:0] 1'1 case assign $1\BRANCH_dec19_lk[0:0] 1'0 end sync always update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] end connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:5007.1-5309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" attribute \generator "nMigen" module \CR_dec19 attribute \src "libresoc.v:5206.3-5239.6" wire width 3 $0\CR_dec19_cr_in[2:0] attribute \src "libresoc.v:5240.3-5273.6" wire width 3 $0\CR_dec19_cr_out[2:0] attribute \src "libresoc.v:5138.3-5171.6" wire width 14 $0\CR_dec19_function_unit[13:0] attribute \src "libresoc.v:5172.3-5205.6" wire width 7 $0\CR_dec19_internal_op[6:0] attribute \src "libresoc.v:5274.3-5307.6" wire width 2 $0\CR_dec19_rc_sel[1:0] attribute \src "libresoc.v:5008.7-5008.20" wire $0\initial[0:0] attribute \src "libresoc.v:5206.3-5239.6" wire width 3 $1\CR_dec19_cr_in[2:0] attribute \src "libresoc.v:5240.3-5273.6" wire width 3 $1\CR_dec19_cr_out[2:0] attribute \src "libresoc.v:5138.3-5171.6" wire width 14 $1\CR_dec19_function_unit[13:0] attribute \src "libresoc.v:5172.3-5205.6" wire width 7 $1\CR_dec19_internal_op[6:0] attribute \src "libresoc.v:5274.3-5307.6" wire width 2 $1\CR_dec19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec19_rc_sel attribute \src "libresoc.v:5008.7-5008.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:5008.7-5008.20" process $proc$libresoc.v:5008$120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:5138.3-5171.6" process $proc$libresoc.v:5138$115 assign { } { } assign { } { } assign $0\CR_dec19_function_unit[13:0] $1\CR_dec19_function_unit[13:0] attribute \src "libresoc.v:5139.5-5139.29" switch \initial attribute \src "libresoc.v:5139.9-5139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\CR_dec19_function_unit[13:0] 14'00000001000000 case assign $1\CR_dec19_function_unit[13:0] 14'00000000000000 end sync always update \CR_dec19_function_unit $0\CR_dec19_function_unit[13:0] end attribute \src "libresoc.v:5172.3-5205.6" process $proc$libresoc.v:5172$116 assign { } { } assign { } { } assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] attribute \src "libresoc.v:5173.5-5173.29" switch \initial attribute \src "libresoc.v:5173.9-5173.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'0101010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\CR_dec19_internal_op[6:0] 7'1000101 case assign $1\CR_dec19_internal_op[6:0] 7'0000000 end sync always update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] end attribute \src "libresoc.v:5206.3-5239.6" process $proc$libresoc.v:5206$117 assign { } { } assign { } { } assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] attribute \src "libresoc.v:5207.5-5207.29" switch \initial attribute \src "libresoc.v:5207.9-5207.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\CR_dec19_cr_in[2:0] 3'100 case assign $1\CR_dec19_cr_in[2:0] 3'000 end sync always update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] end attribute \src "libresoc.v:5240.3-5273.6" process $proc$libresoc.v:5240$118 assign { } { } assign { } { } assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] attribute \src "libresoc.v:5241.5-5241.29" switch \initial attribute \src "libresoc.v:5241.9-5241.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\CR_dec19_cr_out[2:0] 3'011 case assign $1\CR_dec19_cr_out[2:0] 3'000 end sync always update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] end attribute \src "libresoc.v:5274.3-5307.6" process $proc$libresoc.v:5274$119 assign { } { } assign { } { } assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] attribute \src "libresoc.v:5275.5-5275.29" switch \initial attribute \src "libresoc.v:5275.9-5275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\CR_dec19_rc_sel[1:0] 2'00 case assign $1\CR_dec19_rc_sel[1:0] 2'00 end sync always update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:5313.1-6067.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" attribute \generator "nMigen" module \CR_dec31 attribute \src "libresoc.v:6023.3-6041.6" wire width 3 $0\CR_dec31_cr_in[2:0] attribute \src "libresoc.v:6042.3-6060.6" wire width 3 $0\CR_dec31_cr_out[2:0] attribute \src "libresoc.v:5985.3-6003.6" wire width 14 $0\CR_dec31_function_unit[13:0] attribute \src "libresoc.v:6004.3-6022.6" wire width 7 $0\CR_dec31_internal_op[6:0] attribute \src "libresoc.v:5966.3-5984.6" wire width 2 $0\CR_dec31_rc_sel[1:0] attribute \src "libresoc.v:5314.7-5314.20" wire $0\initial[0:0] attribute \src "libresoc.v:6023.3-6041.6" wire width 3 $1\CR_dec31_cr_in[2:0] attribute \src "libresoc.v:6042.3-6060.6" wire width 3 $1\CR_dec31_cr_out[2:0] attribute \src "libresoc.v:5985.3-6003.6" wire width 14 $1\CR_dec31_function_unit[13:0] attribute \src "libresoc.v:6004.3-6022.6" wire width 7 $1\CR_dec31_internal_op[6:0] attribute \src "libresoc.v:5966.3-5984.6" wire width 2 $1\CR_dec31_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute 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"CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_rc_sel attribute \src "libresoc.v:5314.7-5314.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:5934.21-5941.4" cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out connect \CR_dec31_dec_sub0_function_unit \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit connect \CR_dec31_dec_sub0_internal_op \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op connect \CR_dec31_dec_sub0_rc_sel \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel connect \opcode_in \CR_dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:5942.22-5949.4" cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out connect \CR_dec31_dec_sub15_function_unit \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit connect \CR_dec31_dec_sub15_internal_op \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op connect \CR_dec31_dec_sub15_rc_sel \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel connect \opcode_in \CR_dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:5950.22-5957.4" cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out connect \CR_dec31_dec_sub16_function_unit \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit connect \CR_dec31_dec_sub16_internal_op \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op connect \CR_dec31_dec_sub16_rc_sel \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel connect \opcode_in \CR_dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:5958.22-5965.4" cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out connect \CR_dec31_dec_sub19_function_unit \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit connect \CR_dec31_dec_sub19_internal_op \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel connect \opcode_in \CR_dec31_dec_sub19_opcode_in end attribute \src "libresoc.v:5314.7-5314.20" process $proc$libresoc.v:5314$126 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:5966.3-5984.6" process $proc$libresoc.v:5966$121 assign { } { } assign { } { } assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] attribute \src "libresoc.v:5967.5-5967.29" switch \initial attribute \src "libresoc.v:5967.9-5967.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel case assign $1\CR_dec31_rc_sel[1:0] 2'00 end sync always update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] end attribute \src "libresoc.v:5985.3-6003.6" process $proc$libresoc.v:5985$122 assign { } { } assign { } { } assign $0\CR_dec31_function_unit[13:0] $1\CR_dec31_function_unit[13:0] attribute \src "libresoc.v:5986.5-5986.29" switch \initial attribute \src "libresoc.v:5986.9-5986.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_function_unit[13:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit case assign $1\CR_dec31_function_unit[13:0] 14'00000000000000 end sync always update \CR_dec31_function_unit $0\CR_dec31_function_unit[13:0] end attribute \src "libresoc.v:6004.3-6022.6" process $proc$libresoc.v:6004$123 assign { } { } assign { } { } assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] attribute \src "libresoc.v:6005.5-6005.29" switch \initial attribute \src "libresoc.v:6005.9-6005.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op case assign $1\CR_dec31_internal_op[6:0] 7'0000000 end sync always update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] end attribute \src "libresoc.v:6023.3-6041.6" process $proc$libresoc.v:6023$124 assign { } { } assign { } { } assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] attribute \src "libresoc.v:6024.5-6024.29" switch \initial attribute \src "libresoc.v:6024.9-6024.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in case assign $1\CR_dec31_cr_in[2:0] 3'000 end sync always update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] end attribute \src "libresoc.v:6042.3-6060.6" process $proc$libresoc.v:6042$125 assign { } { } assign { } { } assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] attribute \src "libresoc.v:6043.5-6043.29" switch \initial attribute \src "libresoc.v:6043.9-6043.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out case assign $1\CR_dec31_cr_out[2:0] 3'000 end sync always update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] end connect \CR_dec31_dec_sub16_opcode_in \opcode_in connect \CR_dec31_dec_sub15_opcode_in \opcode_in connect \CR_dec31_dec_sub19_opcode_in \opcode_in connect \CR_dec31_dec_sub0_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:6071.1-6253.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" attribute \generator "nMigen" module \CR_dec31_dec_sub0 attribute \src "libresoc.v:6222.3-6231.6" wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:6232.3-6241.6" wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:6202.3-6211.6" wire width 14 $0\CR_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:6212.3-6221.6" wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:6242.3-6251.6" wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:6072.7-6072.20" wire $0\initial[0:0] attribute \src "libresoc.v:6222.3-6231.6" wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:6232.3-6241.6" wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:6202.3-6211.6" wire width 14 $1\CR_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:6212.3-6221.6" wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:6242.3-6251.6" wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel attribute \src "libresoc.v:6072.7-6072.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6072.7-6072.20" process $proc$libresoc.v:6072$132 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:6202.3-6211.6" process $proc$libresoc.v:6202$127 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_function_unit[13:0] $1\CR_dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:6203.5-6203.29" switch \initial attribute \src "libresoc.v:6203.9-6203.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000001000000 case assign $1\CR_dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[13:0] end attribute \src "libresoc.v:6212.3-6221.6" process $proc$libresoc.v:6212$128 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:6213.5-6213.29" switch \initial attribute \src "libresoc.v:6213.9-6213.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 case assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 end sync always update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] end attribute \src "libresoc.v:6222.3-6231.6" process $proc$libresoc.v:6222$129 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:6223.5-6223.29" switch \initial attribute \src "libresoc.v:6223.9-6223.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 case assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 end sync always update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] end attribute \src "libresoc.v:6232.3-6241.6" process $proc$libresoc.v:6232$130 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:6233.5-6233.29" switch \initial attribute \src "libresoc.v:6233.9-6233.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 case assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 end sync always update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] end attribute \src "libresoc.v:6242.3-6251.6" process $proc$libresoc.v:6242$131 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:6243.5-6243.29" switch \initial attribute \src "libresoc.v:6243.9-6243.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 case assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 end sync always update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:6257.1-6904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" attribute \generator "nMigen" module \CR_dec31_dec_sub15 attribute \src "libresoc.v:6594.3-6696.6" wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] attribute \src "libresoc.v:6697.3-6799.6" wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] attribute \src "libresoc.v:6388.3-6490.6" wire width 14 $0\CR_dec31_dec_sub15_function_unit[13:0] attribute \src "libresoc.v:6491.3-6593.6" wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] attribute \src "libresoc.v:6800.3-6902.6" wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] attribute \src "libresoc.v:6258.7-6258.20" wire $0\initial[0:0] attribute \src "libresoc.v:6594.3-6696.6" wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] attribute \src "libresoc.v:6697.3-6799.6" wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] attribute \src "libresoc.v:6388.3-6490.6" wire width 14 $1\CR_dec31_dec_sub15_function_unit[13:0] attribute \src "libresoc.v:6491.3-6593.6" wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] attribute \src "libresoc.v:6800.3-6902.6" wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel attribute \src "libresoc.v:6258.7-6258.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6258.7-6258.20" process $proc$libresoc.v:6258$138 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:6388.3-6490.6" process $proc$libresoc.v:6388$133 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_function_unit[13:0] $1\CR_dec31_dec_sub15_function_unit[13:0] attribute \src "libresoc.v:6389.5-6389.29" switch \initial attribute \src "libresoc.v:6389.9-6389.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000001000000 case assign $1\CR_dec31_dec_sub15_function_unit[13:0] 14'00000000000000 end sync always update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[13:0] end attribute \src "libresoc.v:6491.3-6593.6" process $proc$libresoc.v:6491$134 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] attribute \src "libresoc.v:6492.5-6492.29" switch \initial attribute \src "libresoc.v:6492.9-6492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 case assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 end sync always update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] end attribute \src "libresoc.v:6594.3-6696.6" process $proc$libresoc.v:6594$135 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] attribute \src "libresoc.v:6595.5-6595.29" switch \initial attribute \src "libresoc.v:6595.9-6595.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 case assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 end sync always update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] end attribute \src "libresoc.v:6697.3-6799.6" process $proc$libresoc.v:6697$136 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] attribute \src "libresoc.v:6698.5-6698.29" switch \initial attribute \src "libresoc.v:6698.9-6698.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 case assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 end sync always update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] end attribute \src "libresoc.v:6800.3-6902.6" process $proc$libresoc.v:6800$137 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] attribute \src "libresoc.v:6801.5-6801.29" switch \initial attribute \src "libresoc.v:6801.9-6801.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 case assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 end sync always update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:6908.1-7090.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" attribute \generator "nMigen" module \CR_dec31_dec_sub16 attribute \src "libresoc.v:7059.3-7068.6" wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] attribute \src "libresoc.v:7069.3-7078.6" wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] attribute \src "libresoc.v:7039.3-7048.6" wire width 14 $0\CR_dec31_dec_sub16_function_unit[13:0] attribute \src "libresoc.v:7049.3-7058.6" wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] attribute \src "libresoc.v:7079.3-7088.6" wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] attribute \src "libresoc.v:6909.7-6909.20" wire $0\initial[0:0] attribute \src "libresoc.v:7059.3-7068.6" wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] attribute \src "libresoc.v:7069.3-7078.6" wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] attribute \src "libresoc.v:7039.3-7048.6" wire width 14 $1\CR_dec31_dec_sub16_function_unit[13:0] attribute \src "libresoc.v:7049.3-7058.6" wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] attribute \src "libresoc.v:7079.3-7088.6" wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel attribute \src "libresoc.v:6909.7-6909.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:6909.7-6909.20" process $proc$libresoc.v:6909$144 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:7039.3-7048.6" process $proc$libresoc.v:7039$139 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_function_unit[13:0] $1\CR_dec31_dec_sub16_function_unit[13:0] attribute \src "libresoc.v:7040.5-7040.29" switch \initial attribute \src "libresoc.v:7040.9-7040.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000001000000 case assign $1\CR_dec31_dec_sub16_function_unit[13:0] 14'00000000000000 end sync always update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[13:0] end attribute \src "libresoc.v:7049.3-7058.6" process $proc$libresoc.v:7049$140 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] attribute \src "libresoc.v:7050.5-7050.29" switch \initial attribute \src "libresoc.v:7050.9-7050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 case assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 end sync always update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] end attribute \src "libresoc.v:7059.3-7068.6" process $proc$libresoc.v:7059$141 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] attribute \src "libresoc.v:7060.5-7060.29" switch \initial attribute \src "libresoc.v:7060.9-7060.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 case assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 end sync always update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] end attribute \src "libresoc.v:7069.3-7078.6" process $proc$libresoc.v:7069$142 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] attribute \src "libresoc.v:7070.5-7070.29" switch \initial attribute \src "libresoc.v:7070.9-7070.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 case assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 end sync always update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] end attribute \src "libresoc.v:7079.3-7088.6" process $proc$libresoc.v:7079$143 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] attribute \src "libresoc.v:7080.5-7080.29" switch \initial attribute \src "libresoc.v:7080.9-7080.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 case assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 end sync always update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:7094.1-7276.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" attribute \generator "nMigen" module \CR_dec31_dec_sub19 attribute \src "libresoc.v:7245.3-7254.6" wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:7255.3-7264.6" wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:7225.3-7234.6" wire width 14 $0\CR_dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:7235.3-7244.6" wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:7265.3-7274.6" wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] attribute \src "libresoc.v:7095.7-7095.20" wire $0\initial[0:0] attribute \src "libresoc.v:7245.3-7254.6" wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:7255.3-7264.6" wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:7225.3-7234.6" wire width 14 $1\CR_dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:7235.3-7244.6" wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:7265.3-7274.6" wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:7095.7-7095.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 6 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:7095.7-7095.20" process $proc$libresoc.v:7095$150 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:7225.3-7234.6" process $proc$libresoc.v:7225$145 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_function_unit[13:0] $1\CR_dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:7226.5-7226.29" switch \initial attribute \src "libresoc.v:7226.9-7226.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000001000000 case assign $1\CR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[13:0] end attribute \src "libresoc.v:7235.3-7244.6" process $proc$libresoc.v:7235$146 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:7236.5-7236.29" switch \initial attribute \src "libresoc.v:7236.9-7236.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 case assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 end sync always update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] end attribute \src "libresoc.v:7245.3-7254.6" process $proc$libresoc.v:7245$147 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:7246.5-7246.29" switch \initial attribute \src "libresoc.v:7246.9-7246.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 case assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 end sync always update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] end attribute \src "libresoc.v:7255.3-7264.6" process $proc$libresoc.v:7255$148 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:7256.5-7256.29" switch \initial attribute \src "libresoc.v:7256.9-7256.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 case assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 end sync always update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] end attribute \src "libresoc.v:7265.3-7274.6" process $proc$libresoc.v:7265$149 assign { } { } assign { } { } assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] attribute \src "libresoc.v:7266.5-7266.29" switch \initial attribute \src "libresoc.v:7266.9-7266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 case assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 end sync always update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:7280.1-8033.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" attribute \generator "nMigen" module \DIV_dec31 attribute \src "libresoc.v:8003.3-8015.6" wire width 3 $0\DIV_dec31_cr_in[2:0] attribute \src "libresoc.v:8016.3-8028.6" wire width 3 $0\DIV_dec31_cr_out[2:0] attribute \src "libresoc.v:7873.3-7885.6" wire width 2 $0\DIV_dec31_cry_in[1:0] attribute \src "libresoc.v:7912.3-7924.6" wire $0\DIV_dec31_cry_out[0:0] attribute \src "libresoc.v:7951.3-7963.6" wire width 14 $0\DIV_dec31_function_unit[13:0] attribute \src "libresoc.v:7977.3-7989.6" wire width 3 $0\DIV_dec31_in1_sel[2:0] attribute \src "libresoc.v:7990.3-8002.6" wire width 4 $0\DIV_dec31_in2_sel[3:0] attribute \src "libresoc.v:7964.3-7976.6" wire width 7 $0\DIV_dec31_internal_op[6:0] attribute \src "libresoc.v:7886.3-7898.6" wire $0\DIV_dec31_inv_a[0:0] attribute \src "libresoc.v:7899.3-7911.6" wire $0\DIV_dec31_inv_out[0:0] attribute \src "libresoc.v:7925.3-7937.6" wire $0\DIV_dec31_is_32b[0:0] attribute \src "libresoc.v:7847.3-7859.6" wire width 4 $0\DIV_dec31_ldst_len[3:0] attribute \src "libresoc.v:7860.3-7872.6" wire width 2 $0\DIV_dec31_rc_sel[1:0] attribute \src "libresoc.v:7938.3-7950.6" wire $0\DIV_dec31_sgn[0:0] attribute \src "libresoc.v:7281.7-7281.20" wire $0\initial[0:0] attribute \src "libresoc.v:8003.3-8015.6" wire width 3 $1\DIV_dec31_cr_in[2:0] attribute \src "libresoc.v:8016.3-8028.6" wire width 3 $1\DIV_dec31_cr_out[2:0] attribute \src "libresoc.v:7873.3-7885.6" wire width 2 $1\DIV_dec31_cry_in[1:0] attribute \src "libresoc.v:7912.3-7924.6" wire $1\DIV_dec31_cry_out[0:0] attribute \src "libresoc.v:7951.3-7963.6" wire width 14 $1\DIV_dec31_function_unit[13:0] attribute \src "libresoc.v:7977.3-7989.6" wire width 3 $1\DIV_dec31_in1_sel[2:0] attribute \src "libresoc.v:7990.3-8002.6" wire width 4 $1\DIV_dec31_in2_sel[3:0] attribute \src "libresoc.v:7964.3-7976.6" wire width 7 $1\DIV_dec31_internal_op[6:0] attribute \src "libresoc.v:7886.3-7898.6" wire $1\DIV_dec31_inv_a[0:0] attribute \src "libresoc.v:7899.3-7911.6" wire $1\DIV_dec31_inv_out[0:0] attribute \src "libresoc.v:7925.3-7937.6" wire $1\DIV_dec31_is_32b[0:0] attribute \src "libresoc.v:7847.3-7859.6" wire width 4 $1\DIV_dec31_ldst_len[3:0] attribute \src "libresoc.v:7860.3-7872.6" wire width 2 $1\DIV_dec31_rc_sel[1:0] attribute \src "libresoc.v:7938.3-7950.6" wire $1\DIV_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_sgn attribute \src "libresoc.v:7281.7-7281.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:7813.23-7829.4" cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn connect \opcode_in \DIV_dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:7830.22-7846.4" cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn connect \opcode_in \DIV_dec31_dec_sub9_opcode_in end attribute \src "libresoc.v:7281.7-7281.20" process $proc$libresoc.v:7281$165 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:7847.3-7859.6" process $proc$libresoc.v:7847$151 assign { } { } assign { } { } assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] attribute \src "libresoc.v:7848.5-7848.29" switch \initial attribute \src "libresoc.v:7848.9-7848.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len case assign $1\DIV_dec31_ldst_len[3:0] 4'0000 end sync always update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] end attribute \src "libresoc.v:7860.3-7872.6" process $proc$libresoc.v:7860$152 assign { } { } assign { } { } assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] attribute \src "libresoc.v:7861.5-7861.29" switch \initial attribute \src "libresoc.v:7861.9-7861.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel case assign $1\DIV_dec31_rc_sel[1:0] 2'00 end sync always update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] end attribute \src "libresoc.v:7873.3-7885.6" process $proc$libresoc.v:7873$153 assign { } { } assign { } { } assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] attribute \src "libresoc.v:7874.5-7874.29" switch \initial attribute \src "libresoc.v:7874.9-7874.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in case assign $1\DIV_dec31_cry_in[1:0] 2'00 end sync always update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] end attribute \src "libresoc.v:7886.3-7898.6" process $proc$libresoc.v:7886$154 assign { } { } assign { } { } assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] attribute \src "libresoc.v:7887.5-7887.29" switch \initial attribute \src "libresoc.v:7887.9-7887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a case assign $1\DIV_dec31_inv_a[0:0] 1'0 end sync always update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] end attribute \src "libresoc.v:7899.3-7911.6" process $proc$libresoc.v:7899$155 assign { } { } assign { } { } assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] attribute \src "libresoc.v:7900.5-7900.29" switch \initial attribute \src "libresoc.v:7900.9-7900.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out case assign $1\DIV_dec31_inv_out[0:0] 1'0 end sync always update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] end attribute \src "libresoc.v:7912.3-7924.6" process $proc$libresoc.v:7912$156 assign { } { } assign { } { } assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] attribute \src "libresoc.v:7913.5-7913.29" switch \initial attribute \src "libresoc.v:7913.9-7913.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out case assign $1\DIV_dec31_cry_out[0:0] 1'0 end sync always update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] end attribute \src "libresoc.v:7925.3-7937.6" process $proc$libresoc.v:7925$157 assign { } { } assign { } { } assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] attribute \src "libresoc.v:7926.5-7926.29" switch \initial attribute \src "libresoc.v:7926.9-7926.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b case assign $1\DIV_dec31_is_32b[0:0] 1'0 end sync always update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] end attribute \src "libresoc.v:7938.3-7950.6" process $proc$libresoc.v:7938$158 assign { } { } assign { } { } assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] attribute \src "libresoc.v:7939.5-7939.29" switch \initial attribute \src "libresoc.v:7939.9-7939.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn case assign $1\DIV_dec31_sgn[0:0] 1'0 end sync always update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] end attribute \src "libresoc.v:7951.3-7963.6" process $proc$libresoc.v:7951$159 assign { } { } assign { } { } assign $0\DIV_dec31_function_unit[13:0] $1\DIV_dec31_function_unit[13:0] attribute \src "libresoc.v:7952.5-7952.29" switch \initial attribute \src "libresoc.v:7952.9-7952.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_function_unit[13:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit case assign $1\DIV_dec31_function_unit[13:0] 14'00000000000000 end sync always update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[13:0] end attribute \src "libresoc.v:7964.3-7976.6" process $proc$libresoc.v:7964$160 assign { } { } assign { } { } assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] attribute \src "libresoc.v:7965.5-7965.29" switch \initial attribute \src "libresoc.v:7965.9-7965.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op case assign $1\DIV_dec31_internal_op[6:0] 7'0000000 end sync always update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] end attribute \src "libresoc.v:7977.3-7989.6" process $proc$libresoc.v:7977$161 assign { } { } assign { } { } assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] attribute \src "libresoc.v:7978.5-7978.29" switch \initial attribute \src "libresoc.v:7978.9-7978.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel case assign $1\DIV_dec31_in1_sel[2:0] 3'000 end sync always update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] end attribute \src "libresoc.v:7990.3-8002.6" process $proc$libresoc.v:7990$162 assign { } { } assign { } { } assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] attribute \src "libresoc.v:7991.5-7991.29" switch \initial attribute \src "libresoc.v:7991.9-7991.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel case assign $1\DIV_dec31_in2_sel[3:0] 4'0000 end sync always update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] end attribute \src "libresoc.v:8003.3-8015.6" process $proc$libresoc.v:8003$163 assign { } { } assign { } { } assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] attribute \src "libresoc.v:8004.5-8004.29" switch \initial attribute \src "libresoc.v:8004.9-8004.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in case assign $1\DIV_dec31_cr_in[2:0] 3'000 end sync always update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] end attribute \src "libresoc.v:8016.3-8028.6" process $proc$libresoc.v:8016$164 assign { } { } assign { } { } assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] attribute \src "libresoc.v:8017.5-8017.29" switch \initial attribute \src "libresoc.v:8017.9-8017.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out case assign $1\DIV_dec31_cr_out[2:0] 3'000 end sync always update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] end connect \DIV_dec31_dec_sub11_opcode_in \opcode_in connect \DIV_dec31_dec_sub9_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:8037.1-8745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" attribute \generator "nMigen" module \DIV_dec31_dec_sub11 attribute \src "libresoc.v:8559.3-8595.6" wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:8596.3-8632.6" wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:8707.3-8743.6" wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] attribute \src "libresoc.v:8337.3-8373.6" wire $0\DIV_dec31_dec_sub11_cry_out[0:0] attribute \src "libresoc.v:8226.3-8262.6" wire width 14 $0\DIV_dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:8485.3-8521.6" wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] attribute \src "libresoc.v:8522.3-8558.6" wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:8448.3-8484.6" wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:8263.3-8299.6" wire $0\DIV_dec31_dec_sub11_inv_a[0:0] attribute \src "libresoc.v:8300.3-8336.6" wire $0\DIV_dec31_dec_sub11_inv_out[0:0] attribute \src "libresoc.v:8374.3-8410.6" wire $0\DIV_dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:8633.3-8669.6" wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] attribute \src "libresoc.v:8670.3-8706.6" wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:8411.3-8447.6" wire $0\DIV_dec31_dec_sub11_sgn[0:0] attribute \src "libresoc.v:8038.7-8038.20" wire $0\initial[0:0] attribute \src "libresoc.v:8559.3-8595.6" wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:8596.3-8632.6" wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:8707.3-8743.6" wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] attribute \src "libresoc.v:8337.3-8373.6" wire $1\DIV_dec31_dec_sub11_cry_out[0:0] attribute \src "libresoc.v:8226.3-8262.6" wire width 14 $1\DIV_dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:8485.3-8521.6" wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] attribute \src "libresoc.v:8522.3-8558.6" wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:8448.3-8484.6" wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:8263.3-8299.6" wire $1\DIV_dec31_dec_sub11_inv_a[0:0] attribute \src "libresoc.v:8300.3-8336.6" wire $1\DIV_dec31_dec_sub11_inv_out[0:0] attribute \src "libresoc.v:8374.3-8410.6" wire $1\DIV_dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:8633.3-8669.6" wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] attribute \src "libresoc.v:8670.3-8706.6" wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:8411.3-8447.6" wire $1\DIV_dec31_dec_sub11_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_dec_sub11_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_dec_sub11_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_dec_sub11_sgn attribute \src "libresoc.v:8038.7-8038.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:8038.7-8038.20" process $proc$libresoc.v:8038$180 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:8226.3-8262.6" process $proc$libresoc.v:8226$166 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_function_unit[13:0] $1\DIV_dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:8227.5-8227.29" switch \initial attribute \src "libresoc.v:8227.9-8227.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00001000000000 case assign $1\DIV_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[13:0] end attribute \src "libresoc.v:8263.3-8299.6" process $proc$libresoc.v:8263$167 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] attribute \src "libresoc.v:8264.5-8264.29" switch \initial attribute \src "libresoc.v:8264.9-8264.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 case assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 end sync always update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] end attribute \src "libresoc.v:8300.3-8336.6" process $proc$libresoc.v:8300$168 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] attribute \src "libresoc.v:8301.5-8301.29" switch \initial attribute \src "libresoc.v:8301.9-8301.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 case assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 end sync always update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] end attribute \src "libresoc.v:8337.3-8373.6" process $proc$libresoc.v:8337$169 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] attribute \src "libresoc.v:8338.5-8338.29" switch \initial attribute \src "libresoc.v:8338.9-8338.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 case assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 end sync always update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] end attribute \src "libresoc.v:8374.3-8410.6" process $proc$libresoc.v:8374$170 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:8375.5-8375.29" switch \initial attribute \src "libresoc.v:8375.9-8375.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 case assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 end sync always update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] end attribute \src "libresoc.v:8411.3-8447.6" process $proc$libresoc.v:8411$171 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] attribute \src "libresoc.v:8412.5-8412.29" switch \initial attribute \src "libresoc.v:8412.9-8412.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 case assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 end sync always update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] end attribute \src "libresoc.v:8448.3-8484.6" process $proc$libresoc.v:8448$172 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:8449.5-8449.29" switch \initial attribute \src "libresoc.v:8449.9-8449.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 case assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 end sync always update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] end attribute \src "libresoc.v:8485.3-8521.6" process $proc$libresoc.v:8485$173 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] attribute \src "libresoc.v:8486.5-8486.29" switch \initial attribute \src "libresoc.v:8486.9-8486.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 case assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 end sync always update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] end attribute \src "libresoc.v:8522.3-8558.6" process $proc$libresoc.v:8522$174 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:8523.5-8523.29" switch \initial attribute \src "libresoc.v:8523.9-8523.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 case assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 end sync always update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] end attribute \src "libresoc.v:8559.3-8595.6" process $proc$libresoc.v:8559$175 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:8560.5-8560.29" switch \initial attribute \src "libresoc.v:8560.9-8560.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 case assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 end sync always update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] end attribute \src "libresoc.v:8596.3-8632.6" process $proc$libresoc.v:8596$176 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:8597.5-8597.29" switch \initial attribute \src "libresoc.v:8597.9-8597.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 case assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 end sync always update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] end attribute \src "libresoc.v:8633.3-8669.6" process $proc$libresoc.v:8633$177 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] attribute \src "libresoc.v:8634.5-8634.29" switch \initial attribute \src "libresoc.v:8634.9-8634.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 case assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 end sync always update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] end attribute \src "libresoc.v:8670.3-8706.6" process $proc$libresoc.v:8670$178 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:8671.5-8671.29" switch \initial attribute \src "libresoc.v:8671.9-8671.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 case assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 end sync always update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] end attribute \src "libresoc.v:8707.3-8743.6" process $proc$libresoc.v:8707$179 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] attribute \src "libresoc.v:8708.5-8708.29" switch \initial attribute \src "libresoc.v:8708.9-8708.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 case assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 end sync always update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:8749.1-9457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" attribute \generator "nMigen" module \DIV_dec31_dec_sub9 attribute \src "libresoc.v:9271.3-9307.6" wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:9308.3-9344.6" wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:9419.3-9455.6" wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] attribute \src "libresoc.v:9049.3-9085.6" wire $0\DIV_dec31_dec_sub9_cry_out[0:0] attribute \src "libresoc.v:8938.3-8974.6" wire width 14 $0\DIV_dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:9197.3-9233.6" wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] attribute \src "libresoc.v:9234.3-9270.6" wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:9160.3-9196.6" wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:8975.3-9011.6" wire $0\DIV_dec31_dec_sub9_inv_a[0:0] attribute \src "libresoc.v:9012.3-9048.6" wire $0\DIV_dec31_dec_sub9_inv_out[0:0] attribute \src "libresoc.v:9086.3-9122.6" wire $0\DIV_dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:9345.3-9381.6" wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] attribute \src "libresoc.v:9382.3-9418.6" wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:9123.3-9159.6" wire $0\DIV_dec31_dec_sub9_sgn[0:0] attribute \src "libresoc.v:8750.7-8750.20" wire $0\initial[0:0] attribute \src "libresoc.v:9271.3-9307.6" wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:9308.3-9344.6" wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:9419.3-9455.6" wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] attribute \src "libresoc.v:9049.3-9085.6" wire $1\DIV_dec31_dec_sub9_cry_out[0:0] attribute \src "libresoc.v:8938.3-8974.6" wire width 14 $1\DIV_dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:9197.3-9233.6" wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] attribute \src "libresoc.v:9234.3-9270.6" wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:9160.3-9196.6" wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:8975.3-9011.6" wire $1\DIV_dec31_dec_sub9_inv_a[0:0] attribute \src "libresoc.v:9012.3-9048.6" wire $1\DIV_dec31_dec_sub9_inv_out[0:0] attribute \src "libresoc.v:9086.3-9122.6" wire $1\DIV_dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:9345.3-9381.6" wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] attribute \src "libresoc.v:9382.3-9418.6" wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:9123.3-9159.6" wire $1\DIV_dec31_dec_sub9_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \DIV_dec31_dec_sub9_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_dec31_dec_sub9_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_dec31_dec_sub9_sgn attribute \src "libresoc.v:8750.7-8750.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:8750.7-8750.20" process $proc$libresoc.v:8750$195 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:8938.3-8974.6" process $proc$libresoc.v:8938$181 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_function_unit[13:0] $1\DIV_dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:8939.5-8939.29" switch \initial attribute \src "libresoc.v:8939.9-8939.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00001000000000 case assign $1\DIV_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[13:0] end attribute \src "libresoc.v:8975.3-9011.6" process $proc$libresoc.v:8975$182 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] attribute \src "libresoc.v:8976.5-8976.29" switch \initial attribute \src "libresoc.v:8976.9-8976.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 case assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 end sync always update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] end attribute \src "libresoc.v:9012.3-9048.6" process $proc$libresoc.v:9012$183 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] attribute \src "libresoc.v:9013.5-9013.29" switch \initial attribute \src "libresoc.v:9013.9-9013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 case assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 end sync always update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] end attribute \src "libresoc.v:9049.3-9085.6" process $proc$libresoc.v:9049$184 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] attribute \src "libresoc.v:9050.5-9050.29" switch \initial attribute \src "libresoc.v:9050.9-9050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 case assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 end sync always update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] end attribute \src "libresoc.v:9086.3-9122.6" process $proc$libresoc.v:9086$185 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:9087.5-9087.29" switch \initial attribute \src "libresoc.v:9087.9-9087.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 case assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 end sync always update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] end attribute \src "libresoc.v:9123.3-9159.6" process $proc$libresoc.v:9123$186 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] attribute \src "libresoc.v:9124.5-9124.29" switch \initial attribute \src "libresoc.v:9124.9-9124.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 case assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 end sync always update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] end attribute \src "libresoc.v:9160.3-9196.6" process $proc$libresoc.v:9160$187 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:9161.5-9161.29" switch \initial attribute \src "libresoc.v:9161.9-9161.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 case assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] end attribute \src "libresoc.v:9197.3-9233.6" process $proc$libresoc.v:9197$188 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] attribute \src "libresoc.v:9198.5-9198.29" switch \initial attribute \src "libresoc.v:9198.9-9198.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 case assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 end sync always update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] end attribute \src "libresoc.v:9234.3-9270.6" process $proc$libresoc.v:9234$189 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:9235.5-9235.29" switch \initial attribute \src "libresoc.v:9235.9-9235.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 case assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 end sync always update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] end attribute \src "libresoc.v:9271.3-9307.6" process $proc$libresoc.v:9271$190 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:9272.5-9272.29" switch \initial attribute \src "libresoc.v:9272.9-9272.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 case assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 end sync always update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] end attribute \src "libresoc.v:9308.3-9344.6" process $proc$libresoc.v:9308$191 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:9309.5-9309.29" switch \initial attribute \src "libresoc.v:9309.9-9309.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 case assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 end sync always update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] end attribute \src "libresoc.v:9345.3-9381.6" process $proc$libresoc.v:9345$192 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] attribute \src "libresoc.v:9346.5-9346.29" switch \initial attribute \src "libresoc.v:9346.9-9346.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 case assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 end sync always update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] end attribute \src "libresoc.v:9382.3-9418.6" process $proc$libresoc.v:9382$193 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:9383.5-9383.29" switch \initial attribute \src "libresoc.v:9383.9-9383.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 case assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 end sync always update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] end attribute \src "libresoc.v:9419.3-9455.6" process $proc$libresoc.v:9419$194 assign { } { } assign { } { } assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] attribute \src "libresoc.v:9420.5-9420.29" switch \initial attribute \src "libresoc.v:9420.9-9420.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 case assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 end sync always update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:9461.1-10647.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" attribute \generator "nMigen" module \LDST_dec31 attribute \src "libresoc.v:10489.3-10507.6" wire $0\LDST_dec31_br[0:0] attribute \src "libresoc.v:10394.3-10412.6" wire width 3 $0\LDST_dec31_cr_in[2:0] attribute \src "libresoc.v:10413.3-10431.6" wire width 3 $0\LDST_dec31_cr_out[2:0] attribute \src "libresoc.v:10565.3-10583.6" wire width 14 $0\LDST_dec31_function_unit[13:0] attribute \src "libresoc.v:10603.3-10621.6" wire width 3 $0\LDST_dec31_in1_sel[2:0] attribute \src "libresoc.v:10622.3-10640.6" wire width 4 $0\LDST_dec31_in2_sel[3:0] attribute \src "libresoc.v:10584.3-10602.6" wire width 7 $0\LDST_dec31_internal_op[6:0] attribute \src "libresoc.v:10527.3-10545.6" wire $0\LDST_dec31_is_32b[0:0] attribute \src "libresoc.v:10432.3-10450.6" wire width 4 $0\LDST_dec31_ldst_len[3:0] attribute \src "libresoc.v:10470.3-10488.6" wire width 2 $0\LDST_dec31_rc_sel[1:0] attribute \src "libresoc.v:10546.3-10564.6" wire $0\LDST_dec31_sgn[0:0] attribute \src "libresoc.v:10508.3-10526.6" wire $0\LDST_dec31_sgn_ext[0:0] attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $0\LDST_dec31_upd[1:0] attribute \src "libresoc.v:9462.7-9462.20" wire $0\initial[0:0] attribute \src "libresoc.v:10489.3-10507.6" wire $1\LDST_dec31_br[0:0] attribute \src "libresoc.v:10394.3-10412.6" wire width 3 $1\LDST_dec31_cr_in[2:0] attribute \src "libresoc.v:10413.3-10431.6" wire width 3 $1\LDST_dec31_cr_out[2:0] attribute \src "libresoc.v:10565.3-10583.6" wire width 14 $1\LDST_dec31_function_unit[13:0] attribute \src "libresoc.v:10603.3-10621.6" wire width 3 $1\LDST_dec31_in1_sel[2:0] attribute \src "libresoc.v:10622.3-10640.6" wire width 4 $1\LDST_dec31_in2_sel[3:0] attribute \src "libresoc.v:10584.3-10602.6" wire width 7 $1\LDST_dec31_internal_op[6:0] attribute \src "libresoc.v:10527.3-10545.6" wire $1\LDST_dec31_is_32b[0:0] attribute \src "libresoc.v:10432.3-10450.6" wire width 4 $1\LDST_dec31_ldst_len[3:0] attribute \src "libresoc.v:10470.3-10488.6" wire width 2 $1\LDST_dec31_rc_sel[1:0] attribute \src "libresoc.v:10546.3-10564.6" wire $1\LDST_dec31_sgn[0:0] attribute \src "libresoc.v:10508.3-10526.6" wire $1\LDST_dec31_sgn_ext[0:0] attribute \src "libresoc.v:10451.3-10469.6" wire width 2 $1\LDST_dec31_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire 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\enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_dec_sub23_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_upd attribute \src "libresoc.v:9462.7-9462.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:10330.24-10345.4" cell \LDST_dec31_dec_sub20 \LDST_dec31_dec_sub20 connect \LDST_dec31_dec_sub20_br \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br connect \LDST_dec31_dec_sub20_cr_in \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in connect \LDST_dec31_dec_sub20_cr_out \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out connect \LDST_dec31_dec_sub20_function_unit \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit connect \LDST_dec31_dec_sub20_in1_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel connect \LDST_dec31_dec_sub20_in2_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel connect \LDST_dec31_dec_sub20_internal_op \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op connect \LDST_dec31_dec_sub20_is_32b \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b connect \LDST_dec31_dec_sub20_ldst_len \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len connect \LDST_dec31_dec_sub20_rc_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel connect \LDST_dec31_dec_sub20_sgn \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn connect \LDST_dec31_dec_sub20_sgn_ext \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext connect \LDST_dec31_dec_sub20_upd \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd connect \opcode_in \LDST_dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:10346.24-10361.4" cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in connect \LDST_dec31_dec_sub21_cr_out \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out connect \LDST_dec31_dec_sub21_function_unit \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit connect \LDST_dec31_dec_sub21_in1_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel connect \LDST_dec31_dec_sub21_in2_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel connect \LDST_dec31_dec_sub21_internal_op \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op connect \LDST_dec31_dec_sub21_is_32b \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b connect \LDST_dec31_dec_sub21_ldst_len \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len connect \LDST_dec31_dec_sub21_rc_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel connect \LDST_dec31_dec_sub21_sgn \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn connect \LDST_dec31_dec_sub21_sgn_ext \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext connect \LDST_dec31_dec_sub21_upd \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd connect \opcode_in \LDST_dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:10362.24-10377.4" cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in connect \LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd connect \opcode_in \LDST_dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:10378.24-10393.4" cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd connect \opcode_in \LDST_dec31_dec_sub23_opcode_in end attribute \src "libresoc.v:10394.3-10412.6" process $proc$libresoc.v:10394$196 assign { } { } assign { } { } assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] attribute \src "libresoc.v:10395.5-10395.29" switch \initial attribute \src "libresoc.v:10395.9-10395.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in case assign $1\LDST_dec31_cr_in[2:0] 3'000 end sync always update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] end attribute \src "libresoc.v:10413.3-10431.6" process $proc$libresoc.v:10413$197 assign { } { } assign { } { } assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] attribute \src "libresoc.v:10414.5-10414.29" switch \initial attribute \src "libresoc.v:10414.9-10414.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out case assign $1\LDST_dec31_cr_out[2:0] 3'000 end sync always update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] end attribute \src "libresoc.v:10432.3-10450.6" process $proc$libresoc.v:10432$198 assign { } { } assign { } { } assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] attribute \src "libresoc.v:10433.5-10433.29" switch \initial attribute \src "libresoc.v:10433.9-10433.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len case assign $1\LDST_dec31_ldst_len[3:0] 4'0000 end sync always update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] end attribute \src "libresoc.v:10451.3-10469.6" process $proc$libresoc.v:10451$199 assign { } { } assign { } { } assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] attribute \src "libresoc.v:10452.5-10452.29" switch \initial attribute \src "libresoc.v:10452.9-10452.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd case assign $1\LDST_dec31_upd[1:0] 2'00 end sync always update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] end attribute \src "libresoc.v:10470.3-10488.6" process $proc$libresoc.v:10470$200 assign { } { } assign { } { } assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] attribute \src "libresoc.v:10471.5-10471.29" switch \initial attribute \src "libresoc.v:10471.9-10471.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel case assign $1\LDST_dec31_rc_sel[1:0] 2'00 end sync always update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] end attribute \src "libresoc.v:10489.3-10507.6" process $proc$libresoc.v:10489$201 assign { } { } assign { } { } assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] attribute \src "libresoc.v:10490.5-10490.29" switch \initial attribute \src "libresoc.v:10490.9-10490.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br case assign $1\LDST_dec31_br[0:0] 1'0 end sync always update \LDST_dec31_br $0\LDST_dec31_br[0:0] end attribute \src "libresoc.v:10508.3-10526.6" process $proc$libresoc.v:10508$202 assign { } { } assign { } { } assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] attribute \src "libresoc.v:10509.5-10509.29" switch \initial attribute \src "libresoc.v:10509.9-10509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext case assign $1\LDST_dec31_sgn_ext[0:0] 1'0 end sync always update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] end attribute \src "libresoc.v:10527.3-10545.6" process $proc$libresoc.v:10527$203 assign { } { } assign { } { } assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] attribute \src "libresoc.v:10528.5-10528.29" switch \initial attribute \src "libresoc.v:10528.9-10528.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b case assign $1\LDST_dec31_is_32b[0:0] 1'0 end sync always update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] end attribute \src "libresoc.v:10546.3-10564.6" process $proc$libresoc.v:10546$204 assign { } { } assign { } { } assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] attribute \src "libresoc.v:10547.5-10547.29" switch \initial attribute \src "libresoc.v:10547.9-10547.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn case assign $1\LDST_dec31_sgn[0:0] 1'0 end sync always update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] end attribute \src "libresoc.v:10565.3-10583.6" process $proc$libresoc.v:10565$205 assign { } { } assign { } { } assign $0\LDST_dec31_function_unit[13:0] $1\LDST_dec31_function_unit[13:0] attribute \src "libresoc.v:10566.5-10566.29" switch \initial attribute \src "libresoc.v:10566.9-10566.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_function_unit[13:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit case assign $1\LDST_dec31_function_unit[13:0] 14'00000000000000 end sync always update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[13:0] end attribute \src "libresoc.v:10584.3-10602.6" process $proc$libresoc.v:10584$206 assign { } { } assign { } { } assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] attribute \src "libresoc.v:10585.5-10585.29" switch \initial attribute \src "libresoc.v:10585.9-10585.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op case assign $1\LDST_dec31_internal_op[6:0] 7'0000000 end sync always update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] end attribute \src "libresoc.v:10603.3-10621.6" process $proc$libresoc.v:10603$207 assign { } { } assign { } { } assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] attribute \src "libresoc.v:10604.5-10604.29" switch \initial attribute \src "libresoc.v:10604.9-10604.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel case assign $1\LDST_dec31_in1_sel[2:0] 3'000 end sync always update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] end attribute \src "libresoc.v:10622.3-10640.6" process $proc$libresoc.v:10622$208 assign { } { } assign { } { } assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] attribute \src "libresoc.v:10623.5-10623.29" switch \initial attribute \src "libresoc.v:10623.9-10623.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel case assign $1\LDST_dec31_in2_sel[3:0] 4'0000 end sync always update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] end attribute \src "libresoc.v:9462.7-9462.20" process $proc$libresoc.v:9462$209 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end connect \LDST_dec31_dec_sub23_opcode_in \opcode_in connect \LDST_dec31_dec_sub21_opcode_in \opcode_in connect \LDST_dec31_dec_sub20_opcode_in \opcode_in connect \LDST_dec31_dec_sub22_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:10651.1-11164.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" attribute \generator "nMigen" module \LDST_dec31_dec_sub20 attribute \src "libresoc.v:10863.3-10887.6" wire $0\LDST_dec31_dec_sub20_br[0:0] attribute \src "libresoc.v:11038.3-11062.6" wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] attribute \src "libresoc.v:11063.3-11087.6" wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] attribute \src "libresoc.v:10838.3-10862.6" wire width 14 $0\LDST_dec31_dec_sub20_function_unit[13:0] attribute \src "libresoc.v:10988.3-11012.6" wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] attribute \src "libresoc.v:11013.3-11037.6" wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] attribute \src "libresoc.v:10963.3-10987.6" wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] attribute \src "libresoc.v:10913.3-10937.6" wire $0\LDST_dec31_dec_sub20_is_32b[0:0] attribute \src "libresoc.v:11088.3-11112.6" wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] attribute \src "libresoc.v:11138.3-11162.6" wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] attribute \src "libresoc.v:10938.3-10962.6" wire $0\LDST_dec31_dec_sub20_sgn[0:0] attribute \src "libresoc.v:10888.3-10912.6" wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] attribute \src "libresoc.v:10652.7-10652.20" wire $0\initial[0:0] attribute \src "libresoc.v:10863.3-10887.6" wire $1\LDST_dec31_dec_sub20_br[0:0] attribute \src "libresoc.v:11038.3-11062.6" wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] attribute \src "libresoc.v:11063.3-11087.6" wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] attribute \src "libresoc.v:10838.3-10862.6" wire width 14 $1\LDST_dec31_dec_sub20_function_unit[13:0] attribute \src "libresoc.v:10988.3-11012.6" wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] attribute \src "libresoc.v:11013.3-11037.6" wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] attribute \src "libresoc.v:10963.3-10987.6" wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] attribute \src "libresoc.v:10913.3-10937.6" wire $1\LDST_dec31_dec_sub20_is_32b[0:0] attribute \src "libresoc.v:11088.3-11112.6" wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] attribute \src "libresoc.v:11138.3-11162.6" wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] attribute \src "libresoc.v:10938.3-10962.6" wire $1\LDST_dec31_dec_sub20_sgn[0:0] attribute \src "libresoc.v:10888.3-10912.6" wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:11113.3-11137.6" wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub20_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub20_upd attribute \src "libresoc.v:10652.7-10652.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:10652.7-10652.20" process $proc$libresoc.v:10652$223 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:10838.3-10862.6" process $proc$libresoc.v:10838$210 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_function_unit[13:0] $1\LDST_dec31_dec_sub20_function_unit[13:0] attribute \src "libresoc.v:10839.5-10839.29" switch \initial attribute \src "libresoc.v:10839.9-10839.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000100 case assign $1\LDST_dec31_dec_sub20_function_unit[13:0] 14'00000000000000 end sync always update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[13:0] end attribute \src "libresoc.v:10863.3-10887.6" process $proc$libresoc.v:10863$211 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] attribute \src "libresoc.v:10864.5-10864.29" switch \initial attribute \src "libresoc.v:10864.9-10864.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 case assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 end sync always update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] end attribute \src "libresoc.v:10888.3-10912.6" process $proc$libresoc.v:10888$212 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:10889.5-10889.29" switch \initial attribute \src "libresoc.v:10889.9-10889.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 case assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 end sync always update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] end attribute \src "libresoc.v:10913.3-10937.6" process $proc$libresoc.v:10913$213 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] attribute \src "libresoc.v:10914.5-10914.29" switch \initial attribute \src "libresoc.v:10914.9-10914.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 case assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 end sync always update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] end attribute \src "libresoc.v:10938.3-10962.6" process $proc$libresoc.v:10938$214 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] attribute \src "libresoc.v:10939.5-10939.29" switch \initial attribute \src "libresoc.v:10939.9-10939.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 case assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 end sync always update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] end attribute \src "libresoc.v:10963.3-10987.6" process $proc$libresoc.v:10963$215 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] attribute \src "libresoc.v:10964.5-10964.29" switch \initial attribute \src "libresoc.v:10964.9-10964.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 case assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 end sync always update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] end attribute \src "libresoc.v:10988.3-11012.6" process $proc$libresoc.v:10988$216 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] attribute \src "libresoc.v:10989.5-10989.29" switch \initial attribute \src "libresoc.v:10989.9-10989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 case assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 end sync always update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] end attribute \src "libresoc.v:11013.3-11037.6" process $proc$libresoc.v:11013$217 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] attribute \src "libresoc.v:11014.5-11014.29" switch \initial attribute \src "libresoc.v:11014.9-11014.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 case assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] end attribute \src "libresoc.v:11038.3-11062.6" process $proc$libresoc.v:11038$218 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] attribute \src "libresoc.v:11039.5-11039.29" switch \initial attribute \src "libresoc.v:11039.9-11039.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 case assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 end sync always update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] end attribute \src "libresoc.v:11063.3-11087.6" process $proc$libresoc.v:11063$219 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] attribute \src "libresoc.v:11064.5-11064.29" switch \initial attribute \src "libresoc.v:11064.9-11064.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 case assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 end sync always update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] end attribute \src "libresoc.v:11088.3-11112.6" process $proc$libresoc.v:11088$220 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] attribute \src "libresoc.v:11089.5-11089.29" switch \initial attribute \src "libresoc.v:11089.9-11089.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 case assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] end attribute \src "libresoc.v:11113.3-11137.6" process $proc$libresoc.v:11113$221 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] attribute \src "libresoc.v:11114.5-11114.29" switch \initial attribute \src "libresoc.v:11114.9-11114.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 case assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 end sync always update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] end attribute \src "libresoc.v:11138.3-11162.6" process $proc$libresoc.v:11138$222 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] attribute \src "libresoc.v:11139.5-11139.29" switch \initial attribute \src "libresoc.v:11139.9-11139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 case assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 end sync always update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:11168.1-11993.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" attribute \generator "nMigen" module \LDST_dec31_dec_sub21 attribute \src "libresoc.v:11404.3-11452.6" wire $0\LDST_dec31_dec_sub21_br[0:0] attribute \src "libresoc.v:11747.3-11795.6" wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] attribute \src "libresoc.v:11796.3-11844.6" wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] attribute \src "libresoc.v:11355.3-11403.6" wire width 14 $0\LDST_dec31_dec_sub21_function_unit[13:0] attribute \src "libresoc.v:11649.3-11697.6" wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] attribute \src "libresoc.v:11698.3-11746.6" wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] attribute \src "libresoc.v:11600.3-11648.6" wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] attribute \src "libresoc.v:11502.3-11550.6" wire $0\LDST_dec31_dec_sub21_is_32b[0:0] attribute \src "libresoc.v:11845.3-11893.6" wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] attribute \src "libresoc.v:11943.3-11991.6" wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] attribute \src "libresoc.v:11551.3-11599.6" wire $0\LDST_dec31_dec_sub21_sgn[0:0] attribute \src "libresoc.v:11453.3-11501.6" wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] attribute \src "libresoc.v:11169.7-11169.20" wire $0\initial[0:0] attribute \src "libresoc.v:11404.3-11452.6" wire $1\LDST_dec31_dec_sub21_br[0:0] attribute \src "libresoc.v:11747.3-11795.6" wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] attribute \src "libresoc.v:11796.3-11844.6" wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] attribute \src "libresoc.v:11355.3-11403.6" wire width 14 $1\LDST_dec31_dec_sub21_function_unit[13:0] attribute \src "libresoc.v:11649.3-11697.6" wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] attribute \src "libresoc.v:11698.3-11746.6" wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] attribute \src "libresoc.v:11600.3-11648.6" wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] attribute \src "libresoc.v:11502.3-11550.6" wire $1\LDST_dec31_dec_sub21_is_32b[0:0] attribute \src "libresoc.v:11845.3-11893.6" wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] attribute \src "libresoc.v:11943.3-11991.6" wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] attribute \src "libresoc.v:11551.3-11599.6" wire $1\LDST_dec31_dec_sub21_sgn[0:0] attribute \src "libresoc.v:11453.3-11501.6" wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:11894.3-11942.6" wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub21_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub21_upd attribute \src "libresoc.v:11169.7-11169.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:11169.7-11169.20" process $proc$libresoc.v:11169$237 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:11355.3-11403.6" process $proc$libresoc.v:11355$224 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_function_unit[13:0] $1\LDST_dec31_dec_sub21_function_unit[13:0] attribute \src "libresoc.v:11356.5-11356.29" switch \initial attribute \src "libresoc.v:11356.9-11356.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000100 case assign $1\LDST_dec31_dec_sub21_function_unit[13:0] 14'00000000000000 end sync always update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[13:0] end attribute \src "libresoc.v:11404.3-11452.6" process $proc$libresoc.v:11404$225 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] attribute \src "libresoc.v:11405.5-11405.29" switch \initial attribute \src "libresoc.v:11405.9-11405.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 case assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 end sync always update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] end attribute \src "libresoc.v:11453.3-11501.6" process $proc$libresoc.v:11453$226 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:11454.5-11454.29" switch \initial attribute \src "libresoc.v:11454.9-11454.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 case assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 end sync always update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] end attribute \src "libresoc.v:11502.3-11550.6" process $proc$libresoc.v:11502$227 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] attribute \src "libresoc.v:11503.5-11503.29" switch \initial attribute \src "libresoc.v:11503.9-11503.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 case assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 end sync always update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] end attribute \src "libresoc.v:11551.3-11599.6" process $proc$libresoc.v:11551$228 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] attribute \src "libresoc.v:11552.5-11552.29" switch \initial attribute \src "libresoc.v:11552.9-11552.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 case assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 end sync always update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] end attribute \src "libresoc.v:11600.3-11648.6" process $proc$libresoc.v:11600$229 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] attribute \src "libresoc.v:11601.5-11601.29" switch \initial attribute \src "libresoc.v:11601.9-11601.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 case assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 end sync always update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] end attribute \src "libresoc.v:11649.3-11697.6" process $proc$libresoc.v:11649$230 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] attribute \src "libresoc.v:11650.5-11650.29" switch \initial attribute \src "libresoc.v:11650.9-11650.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 case assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 end sync always update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] end attribute \src "libresoc.v:11698.3-11746.6" process $proc$libresoc.v:11698$231 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] attribute \src "libresoc.v:11699.5-11699.29" switch \initial attribute \src "libresoc.v:11699.9-11699.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 case assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] end attribute \src "libresoc.v:11747.3-11795.6" process $proc$libresoc.v:11747$232 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] attribute \src "libresoc.v:11748.5-11748.29" switch \initial attribute \src "libresoc.v:11748.9-11748.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 case assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 end sync always update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] end attribute \src "libresoc.v:11796.3-11844.6" process $proc$libresoc.v:11796$233 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] attribute \src "libresoc.v:11797.5-11797.29" switch \initial attribute \src "libresoc.v:11797.9-11797.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 case assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 end sync always update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] end attribute \src "libresoc.v:11845.3-11893.6" process $proc$libresoc.v:11845$234 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] attribute \src "libresoc.v:11846.5-11846.29" switch \initial attribute \src "libresoc.v:11846.9-11846.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 case assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] end attribute \src "libresoc.v:11894.3-11942.6" process $proc$libresoc.v:11894$235 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] attribute \src "libresoc.v:11895.5-11895.29" switch \initial attribute \src "libresoc.v:11895.9-11895.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 case assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 end sync always update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] end attribute \src "libresoc.v:11943.3-11991.6" process $proc$libresoc.v:11943$236 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] attribute \src "libresoc.v:11944.5-11944.29" switch \initial attribute \src "libresoc.v:11944.9-11944.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 case assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 end sync always update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:11997.1-12588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" attribute \generator "nMigen" module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:12215.3-12245.6" wire $0\LDST_dec31_dec_sub22_br[0:0] attribute \src "libresoc.v:12432.3-12462.6" wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:12463.3-12493.6" wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:12184.3-12214.6" wire width 14 $0\LDST_dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:12370.3-12400.6" wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:12401.3-12431.6" wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:12339.3-12369.6" wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:12277.3-12307.6" wire $0\LDST_dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:12494.3-12524.6" wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:12556.3-12586.6" wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:12308.3-12338.6" wire $0\LDST_dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:12246.3-12276.6" wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] attribute \src "libresoc.v:11998.7-11998.20" wire $0\initial[0:0] attribute \src "libresoc.v:12215.3-12245.6" wire $1\LDST_dec31_dec_sub22_br[0:0] attribute \src "libresoc.v:12432.3-12462.6" wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:12463.3-12493.6" wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:12184.3-12214.6" wire width 14 $1\LDST_dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:12370.3-12400.6" wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:12401.3-12431.6" wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:12339.3-12369.6" wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:12277.3-12307.6" wire $1\LDST_dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:12494.3-12524.6" wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:12556.3-12586.6" wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:12308.3-12338.6" wire $1\LDST_dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:12246.3-12276.6" wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:12525.3-12555.6" wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub22_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub22_upd attribute \src "libresoc.v:11998.7-11998.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:11998.7-11998.20" process $proc$libresoc.v:11998$251 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:12184.3-12214.6" process $proc$libresoc.v:12184$238 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_function_unit[13:0] $1\LDST_dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:12185.5-12185.29" switch \initial attribute \src "libresoc.v:12185.9-12185.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000100 case assign $1\LDST_dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[13:0] end attribute \src "libresoc.v:12215.3-12245.6" process $proc$libresoc.v:12215$239 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] attribute \src "libresoc.v:12216.5-12216.29" switch \initial attribute \src "libresoc.v:12216.9-12216.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 case assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 end sync always update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] end attribute \src "libresoc.v:12246.3-12276.6" process $proc$libresoc.v:12246$240 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:12247.5-12247.29" switch \initial attribute \src "libresoc.v:12247.9-12247.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 case assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 end sync always update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] end attribute \src "libresoc.v:12277.3-12307.6" process $proc$libresoc.v:12277$241 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:12278.5-12278.29" switch \initial attribute \src "libresoc.v:12278.9-12278.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 case assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 end sync always update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] end attribute \src "libresoc.v:12308.3-12338.6" process $proc$libresoc.v:12308$242 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:12309.5-12309.29" switch \initial attribute \src "libresoc.v:12309.9-12309.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 case assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 end sync always update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] end attribute \src "libresoc.v:12339.3-12369.6" process $proc$libresoc.v:12339$243 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:12340.5-12340.29" switch \initial attribute \src "libresoc.v:12340.9-12340.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 case assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 end sync always update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] end attribute \src "libresoc.v:12370.3-12400.6" process $proc$libresoc.v:12370$244 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:12371.5-12371.29" switch \initial attribute \src "libresoc.v:12371.9-12371.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 case assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 end sync always update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] end attribute \src "libresoc.v:12401.3-12431.6" process $proc$libresoc.v:12401$245 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:12402.5-12402.29" switch \initial attribute \src "libresoc.v:12402.9-12402.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 case assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] end attribute \src "libresoc.v:12432.3-12462.6" process $proc$libresoc.v:12432$246 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:12433.5-12433.29" switch \initial attribute \src "libresoc.v:12433.9-12433.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 case assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 end sync always update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] end attribute \src "libresoc.v:12463.3-12493.6" process $proc$libresoc.v:12463$247 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:12464.5-12464.29" switch \initial attribute \src "libresoc.v:12464.9-12464.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 case assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 end sync always update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] end attribute \src "libresoc.v:12494.3-12524.6" process $proc$libresoc.v:12494$248 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:12495.5-12495.29" switch \initial attribute \src "libresoc.v:12495.9-12495.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 case assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] end attribute \src "libresoc.v:12525.3-12555.6" process $proc$libresoc.v:12525$249 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] attribute \src "libresoc.v:12526.5-12526.29" switch \initial attribute \src "libresoc.v:12526.9-12526.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 case assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 end sync always update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] end attribute \src "libresoc.v:12556.3-12586.6" process $proc$libresoc.v:12556$250 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:12557.5-12557.29" switch \initial attribute \src "libresoc.v:12557.9-12557.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 case assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 end sync always update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:12592.1-13417.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" attribute \generator "nMigen" module \LDST_dec31_dec_sub23 attribute \src "libresoc.v:12828.3-12876.6" wire $0\LDST_dec31_dec_sub23_br[0:0] attribute \src "libresoc.v:13171.3-13219.6" wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] attribute \src "libresoc.v:13220.3-13268.6" wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] attribute \src "libresoc.v:12779.3-12827.6" wire width 14 $0\LDST_dec31_dec_sub23_function_unit[13:0] attribute \src "libresoc.v:13073.3-13121.6" wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] attribute \src "libresoc.v:13122.3-13170.6" wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] attribute \src "libresoc.v:13024.3-13072.6" wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] attribute \src "libresoc.v:12926.3-12974.6" wire $0\LDST_dec31_dec_sub23_is_32b[0:0] attribute \src "libresoc.v:13269.3-13317.6" wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] attribute \src "libresoc.v:13367.3-13415.6" wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] attribute \src "libresoc.v:12975.3-13023.6" wire $0\LDST_dec31_dec_sub23_sgn[0:0] attribute \src "libresoc.v:12877.3-12925.6" wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] attribute \src "libresoc.v:12593.7-12593.20" wire $0\initial[0:0] attribute \src "libresoc.v:12828.3-12876.6" wire $1\LDST_dec31_dec_sub23_br[0:0] attribute \src "libresoc.v:13171.3-13219.6" wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] attribute \src "libresoc.v:13220.3-13268.6" wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] attribute \src "libresoc.v:12779.3-12827.6" wire width 14 $1\LDST_dec31_dec_sub23_function_unit[13:0] attribute \src "libresoc.v:13073.3-13121.6" wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] attribute \src "libresoc.v:13122.3-13170.6" wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] attribute \src "libresoc.v:13024.3-13072.6" wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] attribute \src "libresoc.v:12926.3-12974.6" wire $1\LDST_dec31_dec_sub23_is_32b[0:0] attribute \src "libresoc.v:13269.3-13317.6" wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] attribute \src "libresoc.v:13367.3-13415.6" wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] attribute \src "libresoc.v:12975.3-13023.6" wire $1\LDST_dec31_dec_sub23_sgn[0:0] attribute \src "libresoc.v:12877.3-12925.6" wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:13318.3-13366.6" wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec31_dec_sub23_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec31_dec_sub23_upd attribute \src "libresoc.v:12593.7-12593.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:12593.7-12593.20" process $proc$libresoc.v:12593$265 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:12779.3-12827.6" process $proc$libresoc.v:12779$252 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_function_unit[13:0] $1\LDST_dec31_dec_sub23_function_unit[13:0] attribute \src "libresoc.v:12780.5-12780.29" switch \initial attribute \src "libresoc.v:12780.9-12780.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000100 case assign $1\LDST_dec31_dec_sub23_function_unit[13:0] 14'00000000000000 end sync always update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[13:0] end attribute \src "libresoc.v:12828.3-12876.6" process $proc$libresoc.v:12828$253 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] attribute \src "libresoc.v:12829.5-12829.29" switch \initial attribute \src "libresoc.v:12829.9-12829.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 case assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 end sync always update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] end attribute \src "libresoc.v:12877.3-12925.6" process $proc$libresoc.v:12877$254 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:12878.5-12878.29" switch \initial attribute \src "libresoc.v:12878.9-12878.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 case assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 end sync always update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] end attribute \src "libresoc.v:12926.3-12974.6" process $proc$libresoc.v:12926$255 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] attribute \src "libresoc.v:12927.5-12927.29" switch \initial attribute \src "libresoc.v:12927.9-12927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 case assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 end sync always update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] end attribute \src "libresoc.v:12975.3-13023.6" process $proc$libresoc.v:12975$256 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] attribute \src "libresoc.v:12976.5-12976.29" switch \initial attribute \src "libresoc.v:12976.9-12976.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 case assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 end sync always update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] end attribute \src "libresoc.v:13024.3-13072.6" process $proc$libresoc.v:13024$257 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] attribute \src "libresoc.v:13025.5-13025.29" switch \initial attribute \src "libresoc.v:13025.9-13025.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 case assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 end sync always update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] end attribute \src "libresoc.v:13073.3-13121.6" process $proc$libresoc.v:13073$258 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] attribute \src "libresoc.v:13074.5-13074.29" switch \initial attribute \src "libresoc.v:13074.9-13074.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 case assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 end sync always update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] end attribute \src "libresoc.v:13122.3-13170.6" process $proc$libresoc.v:13122$259 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] attribute \src "libresoc.v:13123.5-13123.29" switch \initial attribute \src "libresoc.v:13123.9-13123.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 case assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] end attribute \src "libresoc.v:13171.3-13219.6" process $proc$libresoc.v:13171$260 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] attribute \src "libresoc.v:13172.5-13172.29" switch \initial attribute \src "libresoc.v:13172.9-13172.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 case assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 end sync always update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] end attribute \src "libresoc.v:13220.3-13268.6" process $proc$libresoc.v:13220$261 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] attribute \src "libresoc.v:13221.5-13221.29" switch \initial attribute \src "libresoc.v:13221.9-13221.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 case assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 end sync always update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] end attribute \src "libresoc.v:13269.3-13317.6" process $proc$libresoc.v:13269$262 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] attribute \src "libresoc.v:13270.5-13270.29" switch \initial attribute \src "libresoc.v:13270.9-13270.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 case assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 end sync always update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] end attribute \src "libresoc.v:13318.3-13366.6" process $proc$libresoc.v:13318$263 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] attribute \src "libresoc.v:13319.5-13319.29" switch \initial attribute \src "libresoc.v:13319.9-13319.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 case assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 end sync always update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] end attribute \src "libresoc.v:13367.3-13415.6" process $proc$libresoc.v:13367$264 assign { } { } assign { } { } assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] attribute \src "libresoc.v:13368.5-13368.29" switch \initial attribute \src "libresoc.v:13368.9-13368.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 case assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 end sync always update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:13421.1-13817.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" attribute \generator "nMigen" module \LDST_dec58 attribute \src "libresoc.v:13624.3-13639.6" wire $0\LDST_dec58_br[0:0] attribute \src "libresoc.v:13736.3-13751.6" wire width 3 $0\LDST_dec58_cr_in[2:0] attribute \src "libresoc.v:13752.3-13767.6" wire width 3 $0\LDST_dec58_cr_out[2:0] attribute \src "libresoc.v:13608.3-13623.6" wire width 14 $0\LDST_dec58_function_unit[13:0] attribute \src "libresoc.v:13704.3-13719.6" wire width 3 $0\LDST_dec58_in1_sel[2:0] attribute \src "libresoc.v:13720.3-13735.6" wire width 4 $0\LDST_dec58_in2_sel[3:0] attribute \src "libresoc.v:13688.3-13703.6" wire width 7 $0\LDST_dec58_internal_op[6:0] attribute \src "libresoc.v:13656.3-13671.6" wire $0\LDST_dec58_is_32b[0:0] attribute \src "libresoc.v:13768.3-13783.6" wire width 4 $0\LDST_dec58_ldst_len[3:0] attribute \src "libresoc.v:13800.3-13815.6" wire width 2 $0\LDST_dec58_rc_sel[1:0] attribute \src "libresoc.v:13672.3-13687.6" wire $0\LDST_dec58_sgn[0:0] attribute \src "libresoc.v:13640.3-13655.6" wire $0\LDST_dec58_sgn_ext[0:0] attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $0\LDST_dec58_upd[1:0] attribute \src "libresoc.v:13422.7-13422.20" wire $0\initial[0:0] attribute \src "libresoc.v:13624.3-13639.6" wire $1\LDST_dec58_br[0:0] attribute \src "libresoc.v:13736.3-13751.6" wire width 3 $1\LDST_dec58_cr_in[2:0] attribute \src "libresoc.v:13752.3-13767.6" wire width 3 $1\LDST_dec58_cr_out[2:0] attribute \src "libresoc.v:13608.3-13623.6" wire width 14 $1\LDST_dec58_function_unit[13:0] attribute \src "libresoc.v:13704.3-13719.6" wire width 3 $1\LDST_dec58_in1_sel[2:0] attribute \src "libresoc.v:13720.3-13735.6" wire width 4 $1\LDST_dec58_in2_sel[3:0] attribute \src "libresoc.v:13688.3-13703.6" wire width 7 $1\LDST_dec58_internal_op[6:0] attribute \src "libresoc.v:13656.3-13671.6" wire $1\LDST_dec58_is_32b[0:0] attribute \src "libresoc.v:13768.3-13783.6" wire width 4 $1\LDST_dec58_ldst_len[3:0] attribute \src "libresoc.v:13800.3-13815.6" wire width 2 $1\LDST_dec58_rc_sel[1:0] attribute \src "libresoc.v:13672.3-13687.6" wire $1\LDST_dec58_sgn[0:0] attribute \src "libresoc.v:13640.3-13655.6" wire $1\LDST_dec58_sgn_ext[0:0] attribute \src "libresoc.v:13784.3-13799.6" wire width 2 $1\LDST_dec58_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec58_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec58_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec58_upd attribute \src "libresoc.v:13422.7-13422.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:13422.7-13422.20" process $proc$libresoc.v:13422$279 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:13608.3-13623.6" process $proc$libresoc.v:13608$266 assign { } { } assign { } { } assign $0\LDST_dec58_function_unit[13:0] $1\LDST_dec58_function_unit[13:0] attribute \src "libresoc.v:13609.5-13609.29" switch \initial attribute \src "libresoc.v:13609.9-13609.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_function_unit[13:0] 14'00000000000100 case assign $1\LDST_dec58_function_unit[13:0] 14'00000000000000 end sync always update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[13:0] end attribute \src "libresoc.v:13624.3-13639.6" process $proc$libresoc.v:13624$267 assign { } { } assign { } { } assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] attribute \src "libresoc.v:13625.5-13625.29" switch \initial attribute \src "libresoc.v:13625.9-13625.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_br[0:0] 1'0 case assign $1\LDST_dec58_br[0:0] 1'0 end sync always update \LDST_dec58_br $0\LDST_dec58_br[0:0] end attribute \src "libresoc.v:13640.3-13655.6" process $proc$libresoc.v:13640$268 assign { } { } assign { } { } assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] attribute \src "libresoc.v:13641.5-13641.29" switch \initial attribute \src "libresoc.v:13641.9-13641.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_sgn_ext[0:0] 1'1 case assign $1\LDST_dec58_sgn_ext[0:0] 1'0 end sync always update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] end attribute \src "libresoc.v:13656.3-13671.6" process $proc$libresoc.v:13656$269 assign { } { } assign { } { } assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] attribute \src "libresoc.v:13657.5-13657.29" switch \initial attribute \src "libresoc.v:13657.9-13657.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_is_32b[0:0] 1'0 case assign $1\LDST_dec58_is_32b[0:0] 1'0 end sync always update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] end attribute \src "libresoc.v:13672.3-13687.6" process $proc$libresoc.v:13672$270 assign { } { } assign { } { } assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] attribute \src "libresoc.v:13673.5-13673.29" switch \initial attribute \src "libresoc.v:13673.9-13673.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_sgn[0:0] 1'0 case assign $1\LDST_dec58_sgn[0:0] 1'0 end sync always update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] end attribute \src "libresoc.v:13688.3-13703.6" process $proc$libresoc.v:13688$271 assign { } { } assign { } { } assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] attribute \src "libresoc.v:13689.5-13689.29" switch \initial attribute \src "libresoc.v:13689.9-13689.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_internal_op[6:0] 7'0100101 case assign $1\LDST_dec58_internal_op[6:0] 7'0000000 end sync always update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] end attribute \src "libresoc.v:13704.3-13719.6" process $proc$libresoc.v:13704$272 assign { } { } assign { } { } assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] attribute \src "libresoc.v:13705.5-13705.29" switch \initial attribute \src "libresoc.v:13705.9-13705.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_in1_sel[2:0] 3'010 case assign $1\LDST_dec58_in1_sel[2:0] 3'000 end sync always update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] end attribute \src "libresoc.v:13720.3-13735.6" process $proc$libresoc.v:13720$273 assign { } { } assign { } { } assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] attribute \src "libresoc.v:13721.5-13721.29" switch \initial attribute \src "libresoc.v:13721.9-13721.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_in2_sel[3:0] 4'1000 case assign $1\LDST_dec58_in2_sel[3:0] 4'0000 end sync always update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] end attribute \src "libresoc.v:13736.3-13751.6" process $proc$libresoc.v:13736$274 assign { } { } assign { } { } assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] attribute \src "libresoc.v:13737.5-13737.29" switch \initial attribute \src "libresoc.v:13737.9-13737.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_cr_in[2:0] 3'000 case assign $1\LDST_dec58_cr_in[2:0] 3'000 end sync always update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] end attribute \src "libresoc.v:13752.3-13767.6" process $proc$libresoc.v:13752$275 assign { } { } assign { } { } assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] attribute \src "libresoc.v:13753.5-13753.29" switch \initial attribute \src "libresoc.v:13753.9-13753.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_cr_out[2:0] 3'000 case assign $1\LDST_dec58_cr_out[2:0] 3'000 end sync always update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] end attribute \src "libresoc.v:13768.3-13783.6" process $proc$libresoc.v:13768$276 assign { } { } assign { } { } assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] attribute \src "libresoc.v:13769.5-13769.29" switch \initial attribute \src "libresoc.v:13769.9-13769.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_ldst_len[3:0] 4'0100 case assign $1\LDST_dec58_ldst_len[3:0] 4'0000 end sync always update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] end attribute \src "libresoc.v:13784.3-13799.6" process $proc$libresoc.v:13784$277 assign { } { } assign { } { } assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] attribute \src "libresoc.v:13785.5-13785.29" switch \initial attribute \src "libresoc.v:13785.9-13785.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_upd[1:0] 2'00 case assign $1\LDST_dec58_upd[1:0] 2'00 end sync always update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] end attribute \src "libresoc.v:13800.3-13815.6" process $proc$libresoc.v:13800$278 assign { } { } assign { } { } assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] attribute \src "libresoc.v:13801.5-13801.29" switch \initial attribute \src "libresoc.v:13801.9-13801.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec58_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec58_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\LDST_dec58_rc_sel[1:0] 2'00 case assign $1\LDST_dec58_rc_sel[1:0] 2'00 end sync always update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] end connect \opcode_switch \opcode_in [1:0] end attribute \src "libresoc.v:13821.1-14178.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" attribute \generator "nMigen" module \LDST_dec62 attribute \src "libresoc.v:14021.3-14033.6" wire $0\LDST_dec62_br[0:0] attribute \src "libresoc.v:14112.3-14124.6" wire width 3 $0\LDST_dec62_cr_in[2:0] attribute \src "libresoc.v:14125.3-14137.6" wire width 3 $0\LDST_dec62_cr_out[2:0] attribute \src "libresoc.v:14008.3-14020.6" wire width 14 $0\LDST_dec62_function_unit[13:0] attribute \src "libresoc.v:14086.3-14098.6" wire width 3 $0\LDST_dec62_in1_sel[2:0] attribute \src "libresoc.v:14099.3-14111.6" wire width 4 $0\LDST_dec62_in2_sel[3:0] attribute \src "libresoc.v:14073.3-14085.6" wire width 7 $0\LDST_dec62_internal_op[6:0] attribute \src "libresoc.v:14047.3-14059.6" wire $0\LDST_dec62_is_32b[0:0] attribute \src "libresoc.v:14138.3-14150.6" wire width 4 $0\LDST_dec62_ldst_len[3:0] attribute \src "libresoc.v:14164.3-14176.6" wire width 2 $0\LDST_dec62_rc_sel[1:0] attribute \src "libresoc.v:14060.3-14072.6" wire $0\LDST_dec62_sgn[0:0] attribute \src "libresoc.v:14034.3-14046.6" wire $0\LDST_dec62_sgn_ext[0:0] attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $0\LDST_dec62_upd[1:0] attribute \src "libresoc.v:13822.7-13822.20" wire $0\initial[0:0] attribute \src "libresoc.v:14021.3-14033.6" wire $1\LDST_dec62_br[0:0] attribute \src "libresoc.v:14112.3-14124.6" wire width 3 $1\LDST_dec62_cr_in[2:0] attribute \src "libresoc.v:14125.3-14137.6" wire width 3 $1\LDST_dec62_cr_out[2:0] attribute \src "libresoc.v:14008.3-14020.6" wire width 14 $1\LDST_dec62_function_unit[13:0] attribute \src "libresoc.v:14086.3-14098.6" wire width 3 $1\LDST_dec62_in1_sel[2:0] attribute \src "libresoc.v:14099.3-14111.6" wire width 4 $1\LDST_dec62_in2_sel[3:0] attribute \src "libresoc.v:14073.3-14085.6" wire width 7 $1\LDST_dec62_internal_op[6:0] attribute \src "libresoc.v:14047.3-14059.6" wire $1\LDST_dec62_is_32b[0:0] attribute \src "libresoc.v:14138.3-14150.6" wire width 4 $1\LDST_dec62_ldst_len[3:0] attribute \src "libresoc.v:14164.3-14176.6" wire width 2 $1\LDST_dec62_rc_sel[1:0] attribute \src "libresoc.v:14060.3-14072.6" wire $1\LDST_dec62_sgn[0:0] attribute \src "libresoc.v:14034.3-14046.6" wire $1\LDST_dec62_sgn_ext[0:0] attribute \src "libresoc.v:14151.3-14163.6" wire width 2 $1\LDST_dec62_upd[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LDST_dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LDST_dec62_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_dec62_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LDST_dec62_upd attribute \src "libresoc.v:13822.7-13822.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 14 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:13822.7-13822.20" process $proc$libresoc.v:13822$293 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:14008.3-14020.6" process $proc$libresoc.v:14008$280 assign { } { } assign { } { } assign $0\LDST_dec62_function_unit[13:0] $1\LDST_dec62_function_unit[13:0] attribute \src "libresoc.v:14009.5-14009.29" switch \initial attribute \src "libresoc.v:14009.9-14009.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_function_unit[13:0] 14'00000000000100 case assign $1\LDST_dec62_function_unit[13:0] 14'00000000000000 end sync always update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[13:0] end attribute \src "libresoc.v:14021.3-14033.6" process $proc$libresoc.v:14021$281 assign { } { } assign { } { } assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] attribute \src "libresoc.v:14022.5-14022.29" switch \initial attribute \src "libresoc.v:14022.9-14022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_br[0:0] 1'0 case assign $1\LDST_dec62_br[0:0] 1'0 end sync always update \LDST_dec62_br $0\LDST_dec62_br[0:0] end attribute \src "libresoc.v:14034.3-14046.6" process $proc$libresoc.v:14034$282 assign { } { } assign { } { } assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] attribute \src "libresoc.v:14035.5-14035.29" switch \initial attribute \src "libresoc.v:14035.9-14035.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_sgn_ext[0:0] 1'0 case assign $1\LDST_dec62_sgn_ext[0:0] 1'0 end sync always update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] end attribute \src "libresoc.v:14047.3-14059.6" process $proc$libresoc.v:14047$283 assign { } { } assign { } { } assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] attribute \src "libresoc.v:14048.5-14048.29" switch \initial attribute \src "libresoc.v:14048.9-14048.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_is_32b[0:0] 1'0 case assign $1\LDST_dec62_is_32b[0:0] 1'0 end sync always update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] end attribute \src "libresoc.v:14060.3-14072.6" process $proc$libresoc.v:14060$284 assign { } { } assign { } { } assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] attribute \src "libresoc.v:14061.5-14061.29" switch \initial attribute \src "libresoc.v:14061.9-14061.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_sgn[0:0] 1'0 case assign $1\LDST_dec62_sgn[0:0] 1'0 end sync always update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] end attribute \src "libresoc.v:14073.3-14085.6" process $proc$libresoc.v:14073$285 assign { } { } assign { } { } assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] attribute \src "libresoc.v:14074.5-14074.29" switch \initial attribute \src "libresoc.v:14074.9-14074.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_internal_op[6:0] 7'0100110 case assign $1\LDST_dec62_internal_op[6:0] 7'0000000 end sync always update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] end attribute \src "libresoc.v:14086.3-14098.6" process $proc$libresoc.v:14086$286 assign { } { } assign { } { } assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] attribute \src "libresoc.v:14087.5-14087.29" switch \initial attribute \src "libresoc.v:14087.9-14087.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_in1_sel[2:0] 3'010 case assign $1\LDST_dec62_in1_sel[2:0] 3'000 end sync always update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] end attribute \src "libresoc.v:14099.3-14111.6" process $proc$libresoc.v:14099$287 assign { } { } assign { } { } assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] attribute \src "libresoc.v:14100.5-14100.29" switch \initial attribute \src "libresoc.v:14100.9-14100.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_in2_sel[3:0] 4'1000 case assign $1\LDST_dec62_in2_sel[3:0] 4'0000 end sync always update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] end attribute \src "libresoc.v:14112.3-14124.6" process $proc$libresoc.v:14112$288 assign { } { } assign { } { } assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] attribute \src "libresoc.v:14113.5-14113.29" switch \initial attribute \src "libresoc.v:14113.9-14113.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_cr_in[2:0] 3'000 case assign $1\LDST_dec62_cr_in[2:0] 3'000 end sync always update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] end attribute \src "libresoc.v:14125.3-14137.6" process $proc$libresoc.v:14125$289 assign { } { } assign { } { } assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] attribute \src "libresoc.v:14126.5-14126.29" switch \initial attribute \src "libresoc.v:14126.9-14126.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_cr_out[2:0] 3'000 case assign $1\LDST_dec62_cr_out[2:0] 3'000 end sync always update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] end attribute \src "libresoc.v:14138.3-14150.6" process $proc$libresoc.v:14138$290 assign { } { } assign { } { } assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] attribute \src "libresoc.v:14139.5-14139.29" switch \initial attribute \src "libresoc.v:14139.9-14139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_ldst_len[3:0] 4'1000 case assign $1\LDST_dec62_ldst_len[3:0] 4'0000 end sync always update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] end attribute \src "libresoc.v:14151.3-14163.6" process $proc$libresoc.v:14151$291 assign { } { } assign { } { } assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] attribute \src "libresoc.v:14152.5-14152.29" switch \initial attribute \src "libresoc.v:14152.9-14152.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_upd[1:0] 2'01 case assign $1\LDST_dec62_upd[1:0] 2'00 end sync always update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] end attribute \src "libresoc.v:14164.3-14176.6" process $proc$libresoc.v:14164$292 assign { } { } assign { } { } assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] attribute \src "libresoc.v:14165.5-14165.29" switch \initial attribute \src "libresoc.v:14165.9-14165.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\LDST_dec62_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\LDST_dec62_rc_sel[1:0] 2'00 case assign $1\LDST_dec62_rc_sel[1:0] 2'00 end sync always update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] end connect \opcode_switch \opcode_in [1:0] end attribute \src "libresoc.v:14182.1-14935.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" attribute \generator "nMigen" module \LOGICAL_dec31 attribute \src "libresoc.v:14905.3-14917.6" wire width 3 $0\LOGICAL_dec31_cr_in[2:0] attribute \src "libresoc.v:14918.3-14930.6" wire width 3 $0\LOGICAL_dec31_cr_out[2:0] attribute \src "libresoc.v:14775.3-14787.6" wire width 2 $0\LOGICAL_dec31_cry_in[1:0] attribute \src "libresoc.v:14814.3-14826.6" wire $0\LOGICAL_dec31_cry_out[0:0] attribute \src "libresoc.v:14853.3-14865.6" wire width 14 $0\LOGICAL_dec31_function_unit[13:0] attribute \src "libresoc.v:14879.3-14891.6" wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] attribute \src "libresoc.v:14892.3-14904.6" wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] attribute \src "libresoc.v:14866.3-14878.6" wire width 7 $0\LOGICAL_dec31_internal_op[6:0] attribute \src "libresoc.v:14788.3-14800.6" wire $0\LOGICAL_dec31_inv_a[0:0] attribute \src "libresoc.v:14801.3-14813.6" wire $0\LOGICAL_dec31_inv_out[0:0] attribute \src "libresoc.v:14827.3-14839.6" wire $0\LOGICAL_dec31_is_32b[0:0] attribute \src "libresoc.v:14749.3-14761.6" wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] attribute \src "libresoc.v:14762.3-14774.6" wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] attribute \src "libresoc.v:14840.3-14852.6" wire $0\LOGICAL_dec31_sgn[0:0] attribute \src "libresoc.v:14183.7-14183.20" wire $0\initial[0:0] attribute \src "libresoc.v:14905.3-14917.6" wire width 3 $1\LOGICAL_dec31_cr_in[2:0] attribute \src "libresoc.v:14918.3-14930.6" wire width 3 $1\LOGICAL_dec31_cr_out[2:0] attribute \src "libresoc.v:14775.3-14787.6" wire width 2 $1\LOGICAL_dec31_cry_in[1:0] attribute \src "libresoc.v:14814.3-14826.6" wire $1\LOGICAL_dec31_cry_out[0:0] attribute \src "libresoc.v:14853.3-14865.6" wire width 14 $1\LOGICAL_dec31_function_unit[13:0] attribute \src "libresoc.v:14879.3-14891.6" wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] attribute \src "libresoc.v:14892.3-14904.6" wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] attribute \src "libresoc.v:14866.3-14878.6" wire width 7 $1\LOGICAL_dec31_internal_op[6:0] attribute \src "libresoc.v:14788.3-14800.6" wire $1\LOGICAL_dec31_inv_a[0:0] attribute \src "libresoc.v:14801.3-14813.6" wire $1\LOGICAL_dec31_inv_out[0:0] attribute \src "libresoc.v:14827.3-14839.6" wire $1\LOGICAL_dec31_is_32b[0:0] attribute \src "libresoc.v:14749.3-14761.6" wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] attribute \src "libresoc.v:14762.3-14774.6" wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] attribute \src "libresoc.v:14840.3-14852.6" wire $1\LOGICAL_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_sgn attribute \src "libresoc.v:14183.7-14183.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:14715.27-14731.4" cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:14732.27-14748.4" cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in end attribute \src "libresoc.v:14183.7-14183.20" process $proc$libresoc.v:14183$308 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:14749.3-14761.6" process $proc$libresoc.v:14749$294 assign { } { } assign { } { } assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] attribute \src "libresoc.v:14750.5-14750.29" switch \initial attribute \src "libresoc.v:14750.9-14750.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len case assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 end sync always update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] end attribute \src "libresoc.v:14762.3-14774.6" process $proc$libresoc.v:14762$295 assign { } { } assign { } { } assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] attribute \src "libresoc.v:14763.5-14763.29" switch \initial attribute \src "libresoc.v:14763.9-14763.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel case assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 end sync always update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] end attribute \src "libresoc.v:14775.3-14787.6" process $proc$libresoc.v:14775$296 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] attribute \src "libresoc.v:14776.5-14776.29" switch \initial attribute \src "libresoc.v:14776.9-14776.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in case assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 end sync always update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] end attribute \src "libresoc.v:14788.3-14800.6" process $proc$libresoc.v:14788$297 assign { } { } assign { } { } assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] attribute \src "libresoc.v:14789.5-14789.29" switch \initial attribute \src "libresoc.v:14789.9-14789.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a case assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 end sync always update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] end attribute \src "libresoc.v:14801.3-14813.6" process $proc$libresoc.v:14801$298 assign { } { } assign { } { } assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] attribute \src "libresoc.v:14802.5-14802.29" switch \initial attribute \src "libresoc.v:14802.9-14802.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out case assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 end sync always update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] end attribute \src "libresoc.v:14814.3-14826.6" process $proc$libresoc.v:14814$299 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] attribute \src "libresoc.v:14815.5-14815.29" switch \initial attribute \src "libresoc.v:14815.9-14815.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out case assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 end sync always update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] end attribute \src "libresoc.v:14827.3-14839.6" process $proc$libresoc.v:14827$300 assign { } { } assign { } { } assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] attribute \src "libresoc.v:14828.5-14828.29" switch \initial attribute \src "libresoc.v:14828.9-14828.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b case assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 end sync always update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] end attribute \src "libresoc.v:14840.3-14852.6" process $proc$libresoc.v:14840$301 assign { } { } assign { } { } assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] attribute \src "libresoc.v:14841.5-14841.29" switch \initial attribute \src "libresoc.v:14841.9-14841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn case assign $1\LOGICAL_dec31_sgn[0:0] 1'0 end sync always update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] end attribute \src "libresoc.v:14853.3-14865.6" process $proc$libresoc.v:14853$302 assign { } { } assign { } { } assign $0\LOGICAL_dec31_function_unit[13:0] $1\LOGICAL_dec31_function_unit[13:0] attribute \src "libresoc.v:14854.5-14854.29" switch \initial attribute \src "libresoc.v:14854.9-14854.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_function_unit[13:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit case assign $1\LOGICAL_dec31_function_unit[13:0] 14'00000000000000 end sync always update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[13:0] end attribute \src "libresoc.v:14866.3-14878.6" process $proc$libresoc.v:14866$303 assign { } { } assign { } { } assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] attribute \src "libresoc.v:14867.5-14867.29" switch \initial attribute \src "libresoc.v:14867.9-14867.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op case assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 end sync always update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] end attribute \src "libresoc.v:14879.3-14891.6" process $proc$libresoc.v:14879$304 assign { } { } assign { } { } assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] attribute \src "libresoc.v:14880.5-14880.29" switch \initial attribute \src "libresoc.v:14880.9-14880.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel case assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 end sync always update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] end attribute \src "libresoc.v:14892.3-14904.6" process $proc$libresoc.v:14892$305 assign { } { } assign { } { } assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] attribute \src "libresoc.v:14893.5-14893.29" switch \initial attribute \src "libresoc.v:14893.9-14893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel case assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 end sync always update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] end attribute \src "libresoc.v:14905.3-14917.6" process $proc$libresoc.v:14905$306 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] attribute \src "libresoc.v:14906.5-14906.29" switch \initial attribute \src "libresoc.v:14906.9-14906.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in case assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 end sync always update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] end attribute \src "libresoc.v:14918.3-14930.6" process $proc$libresoc.v:14918$307 assign { } { } assign { } { } assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] attribute \src "libresoc.v:14919.5-14919.29" switch \initial attribute \src "libresoc.v:14919.9-14919.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out case assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 end sync always update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] end connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:14939.1-15605.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub26 attribute \src "libresoc.v:15434.3-15467.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:15468.3-15501.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:15570.3-15603.6" wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:15230.3-15263.6" wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:15128.3-15161.6" wire width 14 $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:15366.3-15399.6" wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:15400.3-15433.6" wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:15332.3-15365.6" wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:15162.3-15195.6" wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:15196.3-15229.6" wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:15264.3-15297.6" wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:15502.3-15535.6" wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:15536.3-15569.6" wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:15298.3-15331.6" wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:14940.7-14940.20" wire $0\initial[0:0] attribute \src "libresoc.v:15434.3-15467.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:15468.3-15501.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:15570.3-15603.6" wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:15230.3-15263.6" wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:15128.3-15161.6" wire width 14 $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:15366.3-15399.6" wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:15400.3-15433.6" wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:15332.3-15365.6" wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:15162.3-15195.6" wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:15196.3-15229.6" wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:15264.3-15297.6" wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:15502.3-15535.6" wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:15536.3-15569.6" wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:15298.3-15331.6" wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_dec_sub26_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_dec_sub26_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_dec_sub26_sgn attribute \src "libresoc.v:14940.7-14940.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:14940.7-14940.20" process $proc$libresoc.v:14940$323 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:15128.3-15161.6" process $proc$libresoc.v:15128$309 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:15129.5-15129.29" switch \initial attribute \src "libresoc.v:15129.9-15129.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000010000 case assign $1\LOGICAL_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[13:0] end attribute \src "libresoc.v:15162.3-15195.6" process $proc$libresoc.v:15162$310 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:15163.5-15163.29" switch \initial attribute \src "libresoc.v:15163.9-15163.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] end attribute \src "libresoc.v:15196.3-15229.6" process $proc$libresoc.v:15196$311 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:15197.5-15197.29" switch \initial attribute \src "libresoc.v:15197.9-15197.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] end attribute \src "libresoc.v:15230.3-15263.6" process $proc$libresoc.v:15230$312 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:15231.5-15231.29" switch \initial attribute \src "libresoc.v:15231.9-15231.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] end attribute \src "libresoc.v:15264.3-15297.6" process $proc$libresoc.v:15264$313 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:15265.5-15265.29" switch \initial attribute \src "libresoc.v:15265.9-15265.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] end attribute \src "libresoc.v:15298.3-15331.6" process $proc$libresoc.v:15298$314 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:15299.5-15299.29" switch \initial attribute \src "libresoc.v:15299.9-15299.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] end attribute \src "libresoc.v:15332.3-15365.6" process $proc$libresoc.v:15332$315 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:15333.5-15333.29" switch \initial attribute \src "libresoc.v:15333.9-15333.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 case assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] end attribute \src "libresoc.v:15366.3-15399.6" process $proc$libresoc.v:15366$316 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:15367.5-15367.29" switch \initial attribute \src "libresoc.v:15367.9-15367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 case assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 end sync always update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] end attribute \src "libresoc.v:15400.3-15433.6" process $proc$libresoc.v:15400$317 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:15401.5-15401.29" switch \initial attribute \src "libresoc.v:15401.9-15401.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 case assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 end sync always update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] end attribute \src "libresoc.v:15434.3-15467.6" process $proc$libresoc.v:15434$318 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:15435.5-15435.29" switch \initial attribute \src "libresoc.v:15435.9-15435.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 case assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 end sync always update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] end attribute \src "libresoc.v:15468.3-15501.6" process $proc$libresoc.v:15468$319 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:15469.5-15469.29" switch \initial attribute \src "libresoc.v:15469.9-15469.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 case assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 end sync always update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] end attribute \src "libresoc.v:15502.3-15535.6" process $proc$libresoc.v:15502$320 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:15503.5-15503.29" switch \initial attribute \src "libresoc.v:15503.9-15503.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 case assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 end sync always update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] end attribute \src "libresoc.v:15536.3-15569.6" process $proc$libresoc.v:15536$321 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:15537.5-15537.29" switch \initial attribute \src "libresoc.v:15537.9-15537.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 case assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 end sync always update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] end attribute \src "libresoc.v:15570.3-15603.6" process $proc$libresoc.v:15570$322 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:15571.5-15571.29" switch \initial attribute \src "libresoc.v:15571.9-15571.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 case assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 end sync always update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:15609.1-16317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub28 attribute \src "libresoc.v:16131.3-16167.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] attribute \src "libresoc.v:16168.3-16204.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] attribute \src "libresoc.v:16279.3-16315.6" wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] attribute \src "libresoc.v:15909.3-15945.6" wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] attribute \src "libresoc.v:15798.3-15834.6" wire width 14 $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] attribute \src "libresoc.v:16057.3-16093.6" wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] attribute \src "libresoc.v:16094.3-16130.6" wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] attribute \src "libresoc.v:16020.3-16056.6" wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] attribute \src "libresoc.v:15835.3-15871.6" wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] attribute \src "libresoc.v:15872.3-15908.6" wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] attribute \src "libresoc.v:15946.3-15982.6" wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] attribute \src "libresoc.v:16205.3-16241.6" wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] attribute \src "libresoc.v:16242.3-16278.6" wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] attribute \src "libresoc.v:15983.3-16019.6" wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] attribute \src "libresoc.v:15610.7-15610.20" wire $0\initial[0:0] attribute \src "libresoc.v:16131.3-16167.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] attribute \src "libresoc.v:16168.3-16204.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] attribute \src "libresoc.v:16279.3-16315.6" wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] attribute \src "libresoc.v:15909.3-15945.6" wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] attribute \src "libresoc.v:15798.3-15834.6" wire width 14 $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] attribute \src "libresoc.v:16057.3-16093.6" wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] attribute \src "libresoc.v:16094.3-16130.6" wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] attribute \src "libresoc.v:16020.3-16056.6" wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] attribute \src "libresoc.v:15835.3-15871.6" wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] attribute \src "libresoc.v:15872.3-15908.6" wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] attribute \src "libresoc.v:15946.3-15982.6" wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] attribute \src "libresoc.v:16205.3-16241.6" wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] attribute \src "libresoc.v:16242.3-16278.6" wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] attribute \src "libresoc.v:15983.3-16019.6" wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \LOGICAL_dec31_dec_sub28_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_dec31_dec_sub28_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_dec31_dec_sub28_sgn attribute \src "libresoc.v:15610.7-15610.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 15 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:15610.7-15610.20" process $proc$libresoc.v:15610$338 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:15798.3-15834.6" process $proc$libresoc.v:15798$324 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] attribute \src "libresoc.v:15799.5-15799.29" switch \initial attribute \src "libresoc.v:15799.9-15799.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000010000 case assign $1\LOGICAL_dec31_dec_sub28_function_unit[13:0] 14'00000000000000 end sync always update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[13:0] end attribute \src "libresoc.v:15835.3-15871.6" process $proc$libresoc.v:15835$325 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] attribute \src "libresoc.v:15836.5-15836.29" switch \initial attribute \src "libresoc.v:15836.9-15836.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] end attribute \src "libresoc.v:15872.3-15908.6" process $proc$libresoc.v:15872$326 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] attribute \src "libresoc.v:15873.5-15873.29" switch \initial attribute \src "libresoc.v:15873.9-15873.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] end attribute \src "libresoc.v:15909.3-15945.6" process $proc$libresoc.v:15909$327 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] attribute \src "libresoc.v:15910.5-15910.29" switch \initial attribute \src "libresoc.v:15910.9-15910.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] end attribute \src "libresoc.v:15946.3-15982.6" process $proc$libresoc.v:15946$328 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] attribute \src "libresoc.v:15947.5-15947.29" switch \initial attribute \src "libresoc.v:15947.9-15947.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] end attribute \src "libresoc.v:15983.3-16019.6" process $proc$libresoc.v:15983$329 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] attribute \src "libresoc.v:15984.5-15984.29" switch \initial attribute \src "libresoc.v:15984.9-15984.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 case assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 end sync always update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] end attribute \src "libresoc.v:16020.3-16056.6" process $proc$libresoc.v:16020$330 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] attribute \src "libresoc.v:16021.5-16021.29" switch \initial attribute \src "libresoc.v:16021.9-16021.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 case assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 end sync always update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] end attribute \src "libresoc.v:16057.3-16093.6" process $proc$libresoc.v:16057$331 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] attribute \src "libresoc.v:16058.5-16058.29" switch \initial attribute \src "libresoc.v:16058.9-16058.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 case assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 end sync always update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] end attribute \src "libresoc.v:16094.3-16130.6" process $proc$libresoc.v:16094$332 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] attribute \src "libresoc.v:16095.5-16095.29" switch \initial attribute \src "libresoc.v:16095.9-16095.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 case assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 end sync always update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] end attribute \src "libresoc.v:16131.3-16167.6" process $proc$libresoc.v:16131$333 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] attribute \src "libresoc.v:16132.5-16132.29" switch \initial attribute \src "libresoc.v:16132.9-16132.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 case assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 end sync always update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] end attribute \src "libresoc.v:16168.3-16204.6" process $proc$libresoc.v:16168$334 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] attribute \src "libresoc.v:16169.5-16169.29" switch \initial attribute \src "libresoc.v:16169.9-16169.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 case assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 end sync always update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] end attribute \src "libresoc.v:16205.3-16241.6" process $proc$libresoc.v:16205$335 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] attribute \src "libresoc.v:16206.5-16206.29" switch \initial attribute \src "libresoc.v:16206.9-16206.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 case assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 end sync always update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] end attribute \src "libresoc.v:16242.3-16278.6" process $proc$libresoc.v:16242$336 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] attribute \src "libresoc.v:16243.5-16243.29" switch \initial attribute \src "libresoc.v:16243.9-16243.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 case assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 end sync always update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] end attribute \src "libresoc.v:16279.3-16315.6" process $proc$libresoc.v:16279$337 assign { } { } assign { } { } assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] attribute \src "libresoc.v:16280.5-16280.29" switch \initial attribute \src "libresoc.v:16280.9-16280.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 case assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 end sync always update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:16321.1-16894.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" attribute \generator "nMigen" module \MUL_dec31 attribute \src "libresoc.v:16851.3-16863.6" wire width 3 $0\MUL_dec31_cr_in[2:0] attribute \src "libresoc.v:16864.3-16876.6" wire width 3 $0\MUL_dec31_cr_out[2:0] attribute \src "libresoc.v:16812.3-16824.6" wire width 14 $0\MUL_dec31_function_unit[13:0] attribute \src "libresoc.v:16838.3-16850.6" wire width 4 $0\MUL_dec31_in2_sel[3:0] attribute \src "libresoc.v:16825.3-16837.6" wire width 7 $0\MUL_dec31_internal_op[6:0] attribute \src "libresoc.v:16786.3-16798.6" wire $0\MUL_dec31_is_32b[0:0] attribute \src "libresoc.v:16877.3-16889.6" wire width 2 $0\MUL_dec31_rc_sel[1:0] attribute \src "libresoc.v:16799.3-16811.6" wire $0\MUL_dec31_sgn[0:0] attribute \src "libresoc.v:16322.7-16322.20" wire $0\initial[0:0] attribute \src "libresoc.v:16851.3-16863.6" wire width 3 $1\MUL_dec31_cr_in[2:0] attribute \src "libresoc.v:16864.3-16876.6" wire width 3 $1\MUL_dec31_cr_out[2:0] attribute \src "libresoc.v:16812.3-16824.6" wire width 14 $1\MUL_dec31_function_unit[13:0] attribute \src "libresoc.v:16838.3-16850.6" wire width 4 $1\MUL_dec31_in2_sel[3:0] attribute \src "libresoc.v:16825.3-16837.6" wire width 7 $1\MUL_dec31_internal_op[6:0] attribute \src "libresoc.v:16786.3-16798.6" wire $1\MUL_dec31_is_32b[0:0] attribute \src "libresoc.v:16877.3-16889.6" wire width 2 $1\MUL_dec31_rc_sel[1:0] attribute \src "libresoc.v:16799.3-16811.6" wire $1\MUL_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_sgn attribute \src "libresoc.v:16322.7-16322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:16764.23-16774.4" cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn connect \opcode_in \MUL_dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:16775.22-16785.4" cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn connect \opcode_in \MUL_dec31_dec_sub9_opcode_in end attribute \src "libresoc.v:16322.7-16322.20" process $proc$libresoc.v:16322$347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:16786.3-16798.6" process $proc$libresoc.v:16786$339 assign { } { } assign { } { } assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] attribute \src "libresoc.v:16787.5-16787.29" switch \initial attribute \src "libresoc.v:16787.9-16787.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b case assign $1\MUL_dec31_is_32b[0:0] 1'0 end sync always update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] end attribute \src "libresoc.v:16799.3-16811.6" process $proc$libresoc.v:16799$340 assign { } { } assign { } { } assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] attribute \src "libresoc.v:16800.5-16800.29" switch \initial attribute \src "libresoc.v:16800.9-16800.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn case assign $1\MUL_dec31_sgn[0:0] 1'0 end sync always update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] end attribute \src "libresoc.v:16812.3-16824.6" process $proc$libresoc.v:16812$341 assign { } { } assign { } { } assign $0\MUL_dec31_function_unit[13:0] $1\MUL_dec31_function_unit[13:0] attribute \src "libresoc.v:16813.5-16813.29" switch \initial attribute \src "libresoc.v:16813.9-16813.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_function_unit[13:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit case assign $1\MUL_dec31_function_unit[13:0] 14'00000000000000 end sync always update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[13:0] end attribute \src "libresoc.v:16825.3-16837.6" process $proc$libresoc.v:16825$342 assign { } { } assign { } { } assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] attribute \src "libresoc.v:16826.5-16826.29" switch \initial attribute \src "libresoc.v:16826.9-16826.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op case assign $1\MUL_dec31_internal_op[6:0] 7'0000000 end sync always update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] end attribute \src "libresoc.v:16838.3-16850.6" process $proc$libresoc.v:16838$343 assign { } { } assign { } { } assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] attribute \src "libresoc.v:16839.5-16839.29" switch \initial attribute \src "libresoc.v:16839.9-16839.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel case assign $1\MUL_dec31_in2_sel[3:0] 4'0000 end sync always update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] end attribute \src "libresoc.v:16851.3-16863.6" process $proc$libresoc.v:16851$344 assign { } { } assign { } { } assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] attribute \src "libresoc.v:16852.5-16852.29" switch \initial attribute \src "libresoc.v:16852.9-16852.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in case assign $1\MUL_dec31_cr_in[2:0] 3'000 end sync always update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] end attribute \src "libresoc.v:16864.3-16876.6" process $proc$libresoc.v:16864$345 assign { } { } assign { } { } assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] attribute \src "libresoc.v:16865.5-16865.29" switch \initial attribute \src "libresoc.v:16865.9-16865.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out case assign $1\MUL_dec31_cr_out[2:0] 3'000 end sync always update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] end attribute \src "libresoc.v:16877.3-16889.6" process $proc$libresoc.v:16877$346 assign { } { } assign { } { } assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] attribute \src "libresoc.v:16878.5-16878.29" switch \initial attribute \src "libresoc.v:16878.9-16878.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel case assign $1\MUL_dec31_rc_sel[1:0] 2'00 end sync always update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] end connect \MUL_dec31_dec_sub11_opcode_in \opcode_in connect \MUL_dec31_dec_sub9_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:16898.1-17254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" attribute \generator "nMigen" module \MUL_dec31_dec_sub11 attribute \src "libresoc.v:17128.3-17152.6" wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:17153.3-17177.6" wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:17053.3-17077.6" wire width 14 $0\MUL_dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:17103.3-17127.6" wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:17078.3-17102.6" wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:17203.3-17227.6" wire $0\MUL_dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:17178.3-17202.6" wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:17228.3-17252.6" wire $0\MUL_dec31_dec_sub11_sgn[0:0] attribute \src "libresoc.v:16899.7-16899.20" wire $0\initial[0:0] attribute \src "libresoc.v:17128.3-17152.6" wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:17153.3-17177.6" wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:17053.3-17077.6" wire width 14 $1\MUL_dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:17103.3-17127.6" wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:17078.3-17102.6" wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:17203.3-17227.6" wire $1\MUL_dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:17178.3-17202.6" wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:17228.3-17252.6" wire $1\MUL_dec31_dec_sub11_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_dec_sub11_sgn attribute \src "libresoc.v:16899.7-16899.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:16899.7-16899.20" process $proc$libresoc.v:16899$356 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:17053.3-17077.6" process $proc$libresoc.v:17053$348 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_function_unit[13:0] $1\MUL_dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:17054.5-17054.29" switch \initial attribute \src "libresoc.v:17054.9-17054.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000100000000 case assign $1\MUL_dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[13:0] end attribute \src "libresoc.v:17078.3-17102.6" process $proc$libresoc.v:17078$349 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:17079.5-17079.29" switch \initial attribute \src "libresoc.v:17079.9-17079.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 case assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 end sync always update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] end attribute \src "libresoc.v:17103.3-17127.6" process $proc$libresoc.v:17103$350 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:17104.5-17104.29" switch \initial attribute \src "libresoc.v:17104.9-17104.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 case assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 end sync always update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] end attribute \src "libresoc.v:17128.3-17152.6" process $proc$libresoc.v:17128$351 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:17129.5-17129.29" switch \initial attribute \src "libresoc.v:17129.9-17129.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 case assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 end sync always update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] end attribute \src "libresoc.v:17153.3-17177.6" process $proc$libresoc.v:17153$352 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:17154.5-17154.29" switch \initial attribute \src "libresoc.v:17154.9-17154.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 case assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 end sync always update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] end attribute \src "libresoc.v:17178.3-17202.6" process $proc$libresoc.v:17178$353 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:17179.5-17179.29" switch \initial attribute \src "libresoc.v:17179.9-17179.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 case assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 end sync always update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] end attribute \src "libresoc.v:17203.3-17227.6" process $proc$libresoc.v:17203$354 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:17204.5-17204.29" switch \initial attribute \src "libresoc.v:17204.9-17204.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 case assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 end sync always update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] end attribute \src "libresoc.v:17228.3-17252.6" process $proc$libresoc.v:17228$355 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] attribute \src "libresoc.v:17229.5-17229.29" switch \initial attribute \src "libresoc.v:17229.9-17229.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 case assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 end sync always update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:17258.1-17614.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" attribute \generator "nMigen" module \MUL_dec31_dec_sub9 attribute \src "libresoc.v:17488.3-17512.6" wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:17513.3-17537.6" wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:17413.3-17437.6" wire width 14 $0\MUL_dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:17463.3-17487.6" wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:17438.3-17462.6" wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:17563.3-17587.6" wire $0\MUL_dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:17538.3-17562.6" wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:17588.3-17612.6" wire $0\MUL_dec31_dec_sub9_sgn[0:0] attribute \src "libresoc.v:17259.7-17259.20" wire $0\initial[0:0] attribute \src "libresoc.v:17488.3-17512.6" wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:17513.3-17537.6" wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:17413.3-17437.6" wire width 14 $1\MUL_dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:17463.3-17487.6" wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:17438.3-17462.6" wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:17563.3-17587.6" wire $1\MUL_dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:17538.3-17562.6" wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:17588.3-17612.6" wire $1\MUL_dec31_dec_sub9_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 7 \MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \MUL_dec31_dec_sub9_sgn attribute \src "libresoc.v:17259.7-17259.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 9 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:17259.7-17259.20" process $proc$libresoc.v:17259$365 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:17413.3-17437.6" process $proc$libresoc.v:17413$357 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_function_unit[13:0] $1\MUL_dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:17414.5-17414.29" switch \initial attribute \src "libresoc.v:17414.9-17414.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000100000000 case assign $1\MUL_dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[13:0] end attribute \src "libresoc.v:17438.3-17462.6" process $proc$libresoc.v:17438$358 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:17439.5-17439.29" switch \initial attribute \src "libresoc.v:17439.9-17439.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 case assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] end attribute \src "libresoc.v:17463.3-17487.6" process $proc$libresoc.v:17463$359 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:17464.5-17464.29" switch \initial attribute \src "libresoc.v:17464.9-17464.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 case assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 end sync always update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] end attribute \src "libresoc.v:17488.3-17512.6" process $proc$libresoc.v:17488$360 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:17489.5-17489.29" switch \initial attribute \src "libresoc.v:17489.9-17489.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 case assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 end sync always update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] end attribute \src "libresoc.v:17513.3-17537.6" process $proc$libresoc.v:17513$361 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:17514.5-17514.29" switch \initial attribute \src "libresoc.v:17514.9-17514.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 case assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 end sync always update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] end attribute \src "libresoc.v:17538.3-17562.6" process $proc$libresoc.v:17538$362 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:17539.5-17539.29" switch \initial attribute \src "libresoc.v:17539.9-17539.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 case assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 end sync always update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] end attribute \src "libresoc.v:17563.3-17587.6" process $proc$libresoc.v:17563$363 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:17564.5-17564.29" switch \initial attribute \src "libresoc.v:17564.9-17564.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 case assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 end sync always update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] end attribute \src "libresoc.v:17588.3-17612.6" process $proc$libresoc.v:17588$364 assign { } { } assign { } { } assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] attribute \src "libresoc.v:17589.5-17589.29" switch \initial attribute \src "libresoc.v:17589.9-17589.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 case assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 end sync always update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:17618.1-18194.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" attribute \generator "nMigen" module \SHIFT_ROT_dec30 attribute \src "libresoc.v:17971.3-18007.6" wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] attribute \src "libresoc.v:18008.3-18044.6" wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] attribute \src "libresoc.v:18082.3-18118.6" wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] attribute \src "libresoc.v:18156.3-18192.6" wire $0\SHIFT_ROT_dec30_cry_out[0:0] attribute \src "libresoc.v:17786.3-17822.6" wire width 14 $0\SHIFT_ROT_dec30_function_unit[13:0] attribute \src "libresoc.v:17934.3-17970.6" wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] attribute \src "libresoc.v:17897.3-17933.6" wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] attribute \src "libresoc.v:18119.3-18155.6" wire $0\SHIFT_ROT_dec30_inv_a[0:0] attribute \src "libresoc.v:17823.3-17859.6" wire $0\SHIFT_ROT_dec30_is_32b[0:0] attribute \src "libresoc.v:18045.3-18081.6" wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] attribute \src "libresoc.v:17860.3-17896.6" wire $0\SHIFT_ROT_dec30_sgn[0:0] attribute \src "libresoc.v:17619.7-17619.20" wire $0\initial[0:0] attribute \src "libresoc.v:17971.3-18007.6" wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] attribute \src "libresoc.v:18008.3-18044.6" wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] attribute \src "libresoc.v:18082.3-18118.6" wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] attribute \src "libresoc.v:18156.3-18192.6" wire $1\SHIFT_ROT_dec30_cry_out[0:0] attribute \src "libresoc.v:17786.3-17822.6" wire width 14 $1\SHIFT_ROT_dec30_function_unit[13:0] attribute \src "libresoc.v:17934.3-17970.6" wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] attribute \src "libresoc.v:17897.3-17933.6" wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] attribute \src "libresoc.v:18119.3-18155.6" wire $1\SHIFT_ROT_dec30_inv_a[0:0] attribute \src "libresoc.v:17823.3-17859.6" wire $1\SHIFT_ROT_dec30_is_32b[0:0] attribute \src "libresoc.v:18045.3-18081.6" wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] attribute \src "libresoc.v:17860.3-17896.6" wire $1\SHIFT_ROT_dec30_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec30_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec30_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec30_sgn attribute \src "libresoc.v:17619.7-17619.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch attribute \src "libresoc.v:17619.7-17619.20" process $proc$libresoc.v:17619$377 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:17786.3-17822.6" process $proc$libresoc.v:17786$366 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_function_unit[13:0] $1\SHIFT_ROT_dec30_function_unit[13:0] attribute \src "libresoc.v:17787.5-17787.29" switch \initial attribute \src "libresoc.v:17787.9-17787.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000001000 case assign $1\SHIFT_ROT_dec30_function_unit[13:0] 14'00000000000000 end sync always update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[13:0] end attribute \src "libresoc.v:17823.3-17859.6" process $proc$libresoc.v:17823$367 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] attribute \src "libresoc.v:17824.5-17824.29" switch \initial attribute \src "libresoc.v:17824.9-17824.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 case assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 end sync always update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] end attribute \src "libresoc.v:17860.3-17896.6" process $proc$libresoc.v:17860$368 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] attribute \src "libresoc.v:17861.5-17861.29" switch \initial attribute \src "libresoc.v:17861.9-17861.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 case assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 end sync always update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] end attribute \src "libresoc.v:17897.3-17933.6" process $proc$libresoc.v:17897$369 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] attribute \src "libresoc.v:17898.5-17898.29" switch \initial attribute \src "libresoc.v:17898.9-17898.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 case assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 end sync always update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] end attribute \src "libresoc.v:17934.3-17970.6" process $proc$libresoc.v:17934$370 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] attribute \src "libresoc.v:17935.5-17935.29" switch \initial attribute \src "libresoc.v:17935.9-17935.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 case assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 end sync always update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] end attribute \src "libresoc.v:17971.3-18007.6" process $proc$libresoc.v:17971$371 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] attribute \src "libresoc.v:17972.5-17972.29" switch \initial attribute \src "libresoc.v:17972.9-17972.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 case assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 end sync always update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] end attribute \src "libresoc.v:18008.3-18044.6" process $proc$libresoc.v:18008$372 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] attribute \src "libresoc.v:18009.5-18009.29" switch \initial attribute \src "libresoc.v:18009.9-18009.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 case assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 end sync always update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] end attribute \src "libresoc.v:18045.3-18081.6" process $proc$libresoc.v:18045$373 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] attribute \src "libresoc.v:18046.5-18046.29" switch \initial attribute \src "libresoc.v:18046.9-18046.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 case assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 end sync always update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] end attribute \src "libresoc.v:18082.3-18118.6" process $proc$libresoc.v:18082$374 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] attribute \src "libresoc.v:18083.5-18083.29" switch \initial attribute \src "libresoc.v:18083.9-18083.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 case assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 end sync always update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] end attribute \src "libresoc.v:18119.3-18155.6" process $proc$libresoc.v:18119$375 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] attribute \src "libresoc.v:18120.5-18120.29" switch \initial attribute \src "libresoc.v:18120.9-18120.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 case assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 end sync always update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] end attribute \src "libresoc.v:18156.3-18192.6" process $proc$libresoc.v:18156$376 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] attribute \src "libresoc.v:18157.5-18157.29" switch \initial attribute \src "libresoc.v:18157.9-18157.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 case assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 end sync always update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] end connect \opcode_switch \opcode_in [4:1] end attribute \src "libresoc.v:18198.1-19050.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" attribute \generator "nMigen" module \SHIFT_ROT_dec31 attribute \src "libresoc.v:19013.3-19028.6" wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] attribute \src "libresoc.v:19029.3-19044.6" wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] attribute \src "libresoc.v:18885.3-18900.6" wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] attribute \src "libresoc.v:18917.3-18932.6" wire $0\SHIFT_ROT_dec31_cry_out[0:0] attribute \src "libresoc.v:18965.3-18980.6" wire width 14 $0\SHIFT_ROT_dec31_function_unit[13:0] attribute \src "libresoc.v:18997.3-19012.6" wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] attribute \src "libresoc.v:18981.3-18996.6" wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] attribute \src "libresoc.v:18901.3-18916.6" wire $0\SHIFT_ROT_dec31_inv_a[0:0] attribute \src "libresoc.v:18933.3-18948.6" wire $0\SHIFT_ROT_dec31_is_32b[0:0] attribute \src "libresoc.v:18869.3-18884.6" wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] attribute \src "libresoc.v:18949.3-18964.6" wire $0\SHIFT_ROT_dec31_sgn[0:0] attribute \src "libresoc.v:18199.7-18199.20" wire $0\initial[0:0] attribute \src "libresoc.v:19013.3-19028.6" wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] attribute \src "libresoc.v:19029.3-19044.6" wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] attribute \src "libresoc.v:18885.3-18900.6" wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] attribute \src "libresoc.v:18917.3-18932.6" wire $1\SHIFT_ROT_dec31_cry_out[0:0] attribute \src "libresoc.v:18965.3-18980.6" wire width 14 $1\SHIFT_ROT_dec31_function_unit[13:0] attribute \src "libresoc.v:18997.3-19012.6" wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] attribute \src "libresoc.v:18981.3-18996.6" wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] attribute \src "libresoc.v:18901.3-18916.6" wire $1\SHIFT_ROT_dec31_inv_a[0:0] attribute \src "libresoc.v:18933.3-18948.6" wire $1\SHIFT_ROT_dec31_is_32b[0:0] attribute \src "libresoc.v:18869.3-18884.6" wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] attribute \src "libresoc.v:18949.3-18964.6" wire $1\SHIFT_ROT_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_sgn attribute \src "libresoc.v:18199.7-18199.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:18827.29-18840.4" cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op connect \SHIFT_ROT_dec31_dec_sub24_inv_a \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:18841.29-18854.4" cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op connect \SHIFT_ROT_dec31_dec_sub26_inv_a \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:18855.29-18868.4" cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op connect \SHIFT_ROT_dec31_dec_sub27_inv_a \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in end attribute \src "libresoc.v:18199.7-18199.20" process $proc$libresoc.v:18199$389 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:18869.3-18884.6" process $proc$libresoc.v:18869$378 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] attribute \src "libresoc.v:18870.5-18870.29" switch \initial attribute \src "libresoc.v:18870.9-18870.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel case assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] end attribute \src "libresoc.v:18885.3-18900.6" process $proc$libresoc.v:18885$379 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] attribute \src "libresoc.v:18886.5-18886.29" switch \initial attribute \src "libresoc.v:18886.9-18886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in case assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] end attribute \src "libresoc.v:18901.3-18916.6" process $proc$libresoc.v:18901$380 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] attribute \src "libresoc.v:18902.5-18902.29" switch \initial attribute \src "libresoc.v:18902.9-18902.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a case assign $1\SHIFT_ROT_dec31_inv_a[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] end attribute \src "libresoc.v:18917.3-18932.6" process $proc$libresoc.v:18917$381 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] attribute \src "libresoc.v:18918.5-18918.29" switch \initial attribute \src "libresoc.v:18918.9-18918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out case assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] end attribute \src "libresoc.v:18933.3-18948.6" process $proc$libresoc.v:18933$382 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] attribute \src "libresoc.v:18934.5-18934.29" switch \initial attribute \src "libresoc.v:18934.9-18934.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b case assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] end attribute \src "libresoc.v:18949.3-18964.6" process $proc$libresoc.v:18949$383 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] attribute \src "libresoc.v:18950.5-18950.29" switch \initial attribute \src "libresoc.v:18950.9-18950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn case assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] end attribute \src "libresoc.v:18965.3-18980.6" process $proc$libresoc.v:18965$384 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_function_unit[13:0] $1\SHIFT_ROT_dec31_function_unit[13:0] attribute \src "libresoc.v:18966.5-18966.29" switch \initial attribute \src "libresoc.v:18966.9-18966.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_function_unit[13:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit case assign $1\SHIFT_ROT_dec31_function_unit[13:0] 14'00000000000000 end sync always update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[13:0] end attribute \src "libresoc.v:18981.3-18996.6" process $proc$libresoc.v:18981$385 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] attribute \src "libresoc.v:18982.5-18982.29" switch \initial attribute \src "libresoc.v:18982.9-18982.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op case assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 end sync always update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] end attribute \src "libresoc.v:18997.3-19012.6" process $proc$libresoc.v:18997$386 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] attribute \src "libresoc.v:18998.5-18998.29" switch \initial attribute \src "libresoc.v:18998.9-18998.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel case assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 end sync always update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] end attribute \src "libresoc.v:19013.3-19028.6" process $proc$libresoc.v:19013$387 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] attribute \src "libresoc.v:19014.5-19014.29" switch \initial attribute \src "libresoc.v:19014.9-19014.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in case assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] end attribute \src "libresoc.v:19029.3-19044.6" process $proc$libresoc.v:19029$388 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] attribute \src "libresoc.v:19030.5-19030.29" switch \initial attribute \src "libresoc.v:19030.9-19030.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out case assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] end connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:19054.1-19432.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub24 attribute \src "libresoc.v:19317.3-19335.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] attribute \src "libresoc.v:19336.3-19354.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] attribute \src "libresoc.v:19374.3-19392.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:19412.3-19430.6" wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] attribute \src "libresoc.v:19222.3-19240.6" wire width 14 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] attribute \src "libresoc.v:19298.3-19316.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] attribute \src "libresoc.v:19279.3-19297.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] attribute \src "libresoc.v:19393.3-19411.6" wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] attribute \src "libresoc.v:19241.3-19259.6" wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] attribute \src "libresoc.v:19355.3-19373.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] attribute \src "libresoc.v:19260.3-19278.6" wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] attribute \src "libresoc.v:19055.7-19055.20" wire $0\initial[0:0] attribute \src "libresoc.v:19317.3-19335.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] attribute \src "libresoc.v:19336.3-19354.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] attribute \src "libresoc.v:19374.3-19392.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:19412.3-19430.6" wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] attribute \src "libresoc.v:19222.3-19240.6" wire width 14 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] attribute \src "libresoc.v:19298.3-19316.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] attribute \src "libresoc.v:19279.3-19297.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] attribute \src "libresoc.v:19393.3-19411.6" wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] attribute \src "libresoc.v:19241.3-19259.6" wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] attribute \src "libresoc.v:19355.3-19373.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] attribute \src "libresoc.v:19260.3-19278.6" wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn attribute \src "libresoc.v:19055.7-19055.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19055.7-19055.20" process $proc$libresoc.v:19055$401 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:19222.3-19240.6" process $proc$libresoc.v:19222$390 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] attribute \src "libresoc.v:19223.5-19223.29" switch \initial attribute \src "libresoc.v:19223.9-19223.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000001000 case assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] 14'00000000000000 end sync always update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[13:0] end attribute \src "libresoc.v:19241.3-19259.6" process $proc$libresoc.v:19241$391 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] attribute \src "libresoc.v:19242.5-19242.29" switch \initial attribute \src "libresoc.v:19242.9-19242.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 case assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] end attribute \src "libresoc.v:19260.3-19278.6" process $proc$libresoc.v:19260$392 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] attribute \src "libresoc.v:19261.5-19261.29" switch \initial attribute \src "libresoc.v:19261.9-19261.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] end attribute \src "libresoc.v:19279.3-19297.6" process $proc$libresoc.v:19279$393 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] attribute \src "libresoc.v:19280.5-19280.29" switch \initial attribute \src "libresoc.v:19280.9-19280.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 case assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 end sync always update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] end attribute \src "libresoc.v:19298.3-19316.6" process $proc$libresoc.v:19298$394 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] attribute \src "libresoc.v:19299.5-19299.29" switch \initial attribute \src "libresoc.v:19299.9-19299.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 case assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 end sync always update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] end attribute \src "libresoc.v:19317.3-19335.6" process $proc$libresoc.v:19317$395 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] attribute \src "libresoc.v:19318.5-19318.29" switch \initial attribute \src "libresoc.v:19318.9-19318.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 case assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] end attribute \src "libresoc.v:19336.3-19354.6" process $proc$libresoc.v:19336$396 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] attribute \src "libresoc.v:19337.5-19337.29" switch \initial attribute \src "libresoc.v:19337.9-19337.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 case assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] end attribute \src "libresoc.v:19355.3-19373.6" process $proc$libresoc.v:19355$397 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] attribute \src "libresoc.v:19356.5-19356.29" switch \initial attribute \src "libresoc.v:19356.9-19356.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 case assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] end attribute \src "libresoc.v:19374.3-19392.6" process $proc$libresoc.v:19374$398 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:19375.5-19375.29" switch \initial attribute \src "libresoc.v:19375.9-19375.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 case assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] end attribute \src "libresoc.v:19393.3-19411.6" process $proc$libresoc.v:19393$399 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] attribute \src "libresoc.v:19394.5-19394.29" switch \initial attribute \src "libresoc.v:19394.9-19394.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] end attribute \src "libresoc.v:19412.3-19430.6" process $proc$libresoc.v:19412$400 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] attribute \src "libresoc.v:19413.5-19413.29" switch \initial attribute \src "libresoc.v:19413.9-19413.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:19436.1-19781.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub26 attribute \src "libresoc.v:19684.3-19699.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:19700.3-19715.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:19732.3-19747.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:19764.3-19779.6" wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:19604.3-19619.6" wire width 14 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:19668.3-19683.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:19652.3-19667.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:19748.3-19763.6" wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:19620.3-19635.6" wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:19716.3-19731.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:19636.3-19651.6" wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:19437.7-19437.20" wire $0\initial[0:0] attribute \src "libresoc.v:19684.3-19699.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:19700.3-19715.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:19732.3-19747.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:19764.3-19779.6" wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:19604.3-19619.6" wire width 14 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:19668.3-19683.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:19652.3-19667.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:19748.3-19763.6" wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:19620.3-19635.6" wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:19716.3-19731.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:19636.3-19651.6" wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn attribute \src "libresoc.v:19437.7-19437.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19437.7-19437.20" process $proc$libresoc.v:19437$413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:19604.3-19619.6" process $proc$libresoc.v:19604$402 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:19605.5-19605.29" switch \initial attribute \src "libresoc.v:19605.9-19605.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000001000 case assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[13:0] end attribute \src "libresoc.v:19620.3-19635.6" process $proc$libresoc.v:19620$403 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:19621.5-19621.29" switch \initial attribute \src "libresoc.v:19621.9-19621.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] end attribute \src "libresoc.v:19636.3-19651.6" process $proc$libresoc.v:19636$404 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:19637.5-19637.29" switch \initial attribute \src "libresoc.v:19637.9-19637.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 case assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] end attribute \src "libresoc.v:19652.3-19667.6" process $proc$libresoc.v:19652$405 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:19653.5-19653.29" switch \initial attribute \src "libresoc.v:19653.9-19653.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 case assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] end attribute \src "libresoc.v:19668.3-19683.6" process $proc$libresoc.v:19668$406 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:19669.5-19669.29" switch \initial attribute \src "libresoc.v:19669.9-19669.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 case assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 end sync always update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] end attribute \src "libresoc.v:19684.3-19699.6" process $proc$libresoc.v:19684$407 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:19685.5-19685.29" switch \initial attribute \src "libresoc.v:19685.9-19685.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 case assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] end attribute \src "libresoc.v:19700.3-19715.6" process $proc$libresoc.v:19700$408 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:19701.5-19701.29" switch \initial attribute \src "libresoc.v:19701.9-19701.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 case assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] end attribute \src "libresoc.v:19716.3-19731.6" process $proc$libresoc.v:19716$409 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:19717.5-19717.29" switch \initial attribute \src "libresoc.v:19717.9-19717.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 case assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] end attribute \src "libresoc.v:19732.3-19747.6" process $proc$libresoc.v:19732$410 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:19733.5-19733.29" switch \initial attribute \src "libresoc.v:19733.9-19733.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 case assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] end attribute \src "libresoc.v:19748.3-19763.6" process $proc$libresoc.v:19748$411 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:19749.5-19749.29" switch \initial attribute \src "libresoc.v:19749.9-19749.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] end attribute \src "libresoc.v:19764.3-19779.6" process $proc$libresoc.v:19764$412 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:19765.5-19765.29" switch \initial attribute \src "libresoc.v:19765.9-19765.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 case assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:19785.1-20163.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub27 attribute \src "libresoc.v:20048.3-20066.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] attribute \src "libresoc.v:20067.3-20085.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] attribute \src "libresoc.v:20105.3-20123.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:20143.3-20161.6" wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] attribute \src "libresoc.v:19953.3-19971.6" wire width 14 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] attribute \src "libresoc.v:20029.3-20047.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] attribute \src "libresoc.v:20010.3-20028.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:20124.3-20142.6" wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] attribute \src "libresoc.v:19972.3-19990.6" wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:20086.3-20104.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] attribute \src "libresoc.v:19991.3-20009.6" wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] attribute \src "libresoc.v:19786.7-19786.20" wire $0\initial[0:0] attribute \src "libresoc.v:20048.3-20066.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] attribute \src "libresoc.v:20067.3-20085.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] attribute \src "libresoc.v:20105.3-20123.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:20143.3-20161.6" wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] attribute \src "libresoc.v:19953.3-19971.6" wire width 14 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] attribute \src "libresoc.v:20029.3-20047.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] attribute \src "libresoc.v:20010.3-20028.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:20124.3-20142.6" wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] attribute \src "libresoc.v:19972.3-19990.6" wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:20086.3-20104.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] attribute \src "libresoc.v:19991.3-20009.6" wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn attribute \src "libresoc.v:19786.7-19786.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 12 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:19786.7-19786.20" process $proc$libresoc.v:19786$425 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:19953.3-19971.6" process $proc$libresoc.v:19953$414 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] attribute \src "libresoc.v:19954.5-19954.29" switch \initial attribute \src "libresoc.v:19954.9-19954.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000001000 case assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] 14'00000000000000 end sync always update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[13:0] end attribute \src "libresoc.v:19972.3-19990.6" process $proc$libresoc.v:19972$415 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:19973.5-19973.29" switch \initial attribute \src "libresoc.v:19973.9-19973.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] end attribute \src "libresoc.v:19991.3-20009.6" process $proc$libresoc.v:19991$416 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] attribute \src "libresoc.v:19992.5-19992.29" switch \initial attribute \src "libresoc.v:19992.9-19992.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] end attribute \src "libresoc.v:20010.3-20028.6" process $proc$libresoc.v:20010$417 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:20011.5-20011.29" switch \initial attribute \src "libresoc.v:20011.9-20011.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 case assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 end sync always update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] end attribute \src "libresoc.v:20029.3-20047.6" process $proc$libresoc.v:20029$418 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] attribute \src "libresoc.v:20030.5-20030.29" switch \initial attribute \src "libresoc.v:20030.9-20030.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 case assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 end sync always update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] end attribute \src "libresoc.v:20048.3-20066.6" process $proc$libresoc.v:20048$419 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] attribute \src "libresoc.v:20049.5-20049.29" switch \initial attribute \src "libresoc.v:20049.9-20049.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 case assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] end attribute \src "libresoc.v:20067.3-20085.6" process $proc$libresoc.v:20067$420 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] attribute \src "libresoc.v:20068.5-20068.29" switch \initial attribute \src "libresoc.v:20068.9-20068.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 case assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 end sync always update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] end attribute \src "libresoc.v:20086.3-20104.6" process $proc$libresoc.v:20086$421 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] attribute \src "libresoc.v:20087.5-20087.29" switch \initial attribute \src "libresoc.v:20087.9-20087.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 case assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] end attribute \src "libresoc.v:20105.3-20123.6" process $proc$libresoc.v:20105$422 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:20106.5-20106.29" switch \initial attribute \src "libresoc.v:20106.9-20106.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 case assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 end sync always update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] end attribute \src "libresoc.v:20124.3-20142.6" process $proc$libresoc.v:20124$423 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] attribute \src "libresoc.v:20125.5-20125.29" switch \initial attribute \src "libresoc.v:20125.9-20125.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] end attribute \src "libresoc.v:20143.3-20161.6" process $proc$libresoc.v:20143$424 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] attribute \src "libresoc.v:20144.5-20144.29" switch \initial attribute \src "libresoc.v:20144.9-20144.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 case assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 end sync always update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "SPBlock_512W64B8W.v:2.1-7.10" attribute \cells_not_processed 1 attribute \blackbox 1 module \SPBlock_512W64B8W attribute \src "SPBlock_512W64B8W.v:2.38-2.39" wire width 9 input 1 \a attribute \src "SPBlock_512W64B8W.v:6.11-6.14" wire input 5 \clk attribute \src "SPBlock_512W64B8W.v:3.18-3.19" wire width 64 input 2 \d attribute \src "SPBlock_512W64B8W.v:4.19-4.20" wire width 64 output 3 \q attribute \src "SPBlock_512W64B8W.v:5.17-5.19" wire width 8 input 4 \we end attribute \src "libresoc.v:20167.1-20499.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" attribute \generator "nMigen" module \SPR_dec31 attribute \src "libresoc.v:20456.3-20465.6" wire width 3 $0\SPR_dec31_cr_in[2:0] attribute \src "libresoc.v:20466.3-20475.6" wire width 3 $0\SPR_dec31_cr_out[2:0] attribute \src "libresoc.v:20436.3-20445.6" wire width 14 $0\SPR_dec31_function_unit[13:0] attribute \src "libresoc.v:20446.3-20455.6" wire width 7 $0\SPR_dec31_internal_op[6:0] attribute \src "libresoc.v:20486.3-20495.6" wire $0\SPR_dec31_is_32b[0:0] attribute \src "libresoc.v:20476.3-20485.6" wire width 2 $0\SPR_dec31_rc_sel[1:0] attribute \src "libresoc.v:20168.7-20168.20" wire $0\initial[0:0] attribute \src "libresoc.v:20456.3-20465.6" wire width 3 $1\SPR_dec31_cr_in[2:0] attribute \src "libresoc.v:20466.3-20475.6" wire width 3 $1\SPR_dec31_cr_out[2:0] attribute \src "libresoc.v:20436.3-20445.6" wire width 14 $1\SPR_dec31_function_unit[13:0] attribute \src "libresoc.v:20446.3-20455.6" wire width 7 $1\SPR_dec31_internal_op[6:0] attribute \src "libresoc.v:20486.3-20495.6" wire $1\SPR_dec31_is_32b[0:0] attribute \src "libresoc.v:20476.3-20485.6" wire width 2 $1\SPR_dec31_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SPR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SPR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SPR_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 6 \SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \SPR_dec31_rc_sel attribute \src "libresoc.v:20168.7-20168.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 7 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:20427.23-20435.4" cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel connect \opcode_in \SPR_dec31_dec_sub19_opcode_in end attribute \src "libresoc.v:20168.7-20168.20" process $proc$libresoc.v:20168$432 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:20436.3-20445.6" process $proc$libresoc.v:20436$426 assign { } { } assign { } { } assign $0\SPR_dec31_function_unit[13:0] $1\SPR_dec31_function_unit[13:0] attribute \src "libresoc.v:20437.5-20437.29" switch \initial attribute \src "libresoc.v:20437.9-20437.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\SPR_dec31_function_unit[13:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit case assign $1\SPR_dec31_function_unit[13:0] 14'00000000000000 end sync always update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[13:0] end attribute \src "libresoc.v:20446.3-20455.6" process $proc$libresoc.v:20446$427 assign { } { } assign { } { } assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] attribute \src "libresoc.v:20447.5-20447.29" switch \initial attribute \src "libresoc.v:20447.9-20447.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op case assign $1\SPR_dec31_internal_op[6:0] 7'0000000 end sync always update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] end attribute \src "libresoc.v:20456.3-20465.6" process $proc$libresoc.v:20456$428 assign { } { } assign { } { } assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] attribute \src "libresoc.v:20457.5-20457.29" switch \initial attribute \src "libresoc.v:20457.9-20457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in case assign $1\SPR_dec31_cr_in[2:0] 3'000 end sync always update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] end attribute \src "libresoc.v:20466.3-20475.6" process $proc$libresoc.v:20466$429 assign { } { } assign { } { } assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] attribute \src "libresoc.v:20467.5-20467.29" switch \initial attribute \src "libresoc.v:20467.9-20467.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out case assign $1\SPR_dec31_cr_out[2:0] 3'000 end sync always update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] end attribute \src "libresoc.v:20476.3-20485.6" process $proc$libresoc.v:20476$430 assign { } { } assign { } { } assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] attribute \src "libresoc.v:20477.5-20477.29" switch \initial attribute \src "libresoc.v:20477.9-20477.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel case assign $1\SPR_dec31_rc_sel[1:0] 2'00 end sync always update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] end attribute \src "libresoc.v:20486.3-20495.6" process $proc$libresoc.v:20486$431 assign { } { } assign { } { } assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] attribute \src "libresoc.v:20487.5-20487.29" switch \initial attribute \src "libresoc.v:20487.9-20487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b case assign $1\SPR_dec31_is_32b[0:0] 1'0 end sync always update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] end connect \SPR_dec31_dec_sub19_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:20503.1-20716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" attribute \generator "nMigen" module \SPR_dec31_dec_sub19 attribute \src "libresoc.v:20663.3-20675.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:20676.3-20688.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:20637.3-20649.6" wire width 14 $0\SPR_dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:20650.3-20662.6" wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:20702.3-20714.6" wire $0\SPR_dec31_dec_sub19_is_32b[0:0] attribute \src "libresoc.v:20689.3-20701.6" wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] attribute \src "libresoc.v:20504.7-20504.20" wire $0\initial[0:0] attribute \src "libresoc.v:20663.3-20675.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:20676.3-20688.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:20637.3-20649.6" wire width 14 $1\SPR_dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:20650.3-20662.6" wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:20702.3-20714.6" wire $1\SPR_dec31_dec_sub19_is_32b[0:0] attribute \src "libresoc.v:20689.3-20701.6" wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 6 \SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:20504.7-20504.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 7 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:20504.7-20504.20" process $proc$libresoc.v:20504$439 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:20637.3-20649.6" process $proc$libresoc.v:20637$433 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_function_unit[13:0] $1\SPR_dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:20638.5-20638.29" switch \initial attribute \src "libresoc.v:20638.9-20638.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00010000000000 case assign $1\SPR_dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[13:0] end attribute \src "libresoc.v:20650.3-20662.6" process $proc$libresoc.v:20650$434 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:20651.5-20651.29" switch \initial attribute \src "libresoc.v:20651.9-20651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 case assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 end sync always update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] end attribute \src "libresoc.v:20663.3-20675.6" process $proc$libresoc.v:20663$435 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:20664.5-20664.29" switch \initial attribute \src "libresoc.v:20664.9-20664.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 case assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 end sync always update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] end attribute \src "libresoc.v:20676.3-20688.6" process $proc$libresoc.v:20676$436 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:20677.5-20677.29" switch \initial attribute \src "libresoc.v:20677.9-20677.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 case assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 end sync always update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] end attribute \src "libresoc.v:20689.3-20701.6" process $proc$libresoc.v:20689$437 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] attribute \src "libresoc.v:20690.5-20690.29" switch \initial attribute \src "libresoc.v:20690.9-20690.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 case assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 end sync always update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] end attribute \src "libresoc.v:20702.3-20714.6" process $proc$libresoc.v:20702$438 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] attribute \src "libresoc.v:20703.5-20703.29" switch \initial attribute \src "libresoc.v:20703.9-20703.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 case assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 end sync always update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:20720.1-21040.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" attribute \generator "nMigen" module \_fsm attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $0\fsm_state$next[3:0]$464 attribute \src "libresoc.v:20806.3-20807.35" wire width 4 $0\fsm_state[3:0] attribute \src "libresoc.v:20721.7-20721.20" wire $0\initial[0:0] attribute \src "libresoc.v:20812.3-20863.6" wire $0\isdr$next[0:0]$460 attribute \src "libresoc.v:20808.3-20809.25" wire $0\isdr[0:0] attribute \src "libresoc.v:20979.3-21030.6" wire $0\isir$next[0:0]$477 attribute \src "libresoc.v:20810.3-20811.25" wire $0\isir[0:0] attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $10\fsm_state$next[3:0]$474 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $11\fsm_state$next[3:0]$475 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $1\fsm_state$next[3:0]$465 attribute \src "libresoc.v:20761.13-20761.29" wire width 4 $1\fsm_state[3:0] attribute \src "libresoc.v:20812.3-20863.6" wire $1\isdr$next[0:0]$461 attribute \src "libresoc.v:20766.7-20766.18" wire $1\isdr[0:0] attribute \src "libresoc.v:20979.3-21030.6" wire $1\isir$next[0:0]$478 attribute \src "libresoc.v:20771.7-20771.18" wire $1\isir[0:0] attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $2\fsm_state$next[3:0]$466 attribute \src "libresoc.v:20812.3-20863.6" wire $2\isdr$next[0:0]$462 attribute \src "libresoc.v:20979.3-21030.6" wire $2\isir$next[0:0]$479 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $3\fsm_state$next[3:0]$467 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $4\fsm_state$next[3:0]$468 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $5\fsm_state$next[3:0]$469 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $6\fsm_state$next[3:0]$470 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $7\fsm_state$next[3:0]$471 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $8\fsm_state$next[3:0]$472 attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $9\fsm_state$next[3:0]$473 attribute \src "libresoc.v:20790.17-20790.110" wire $eq$libresoc.v:20790$440_Y attribute \src "libresoc.v:20791.18-20791.111" wire $eq$libresoc.v:20791$441_Y attribute \src "libresoc.v:20792.18-20792.111" wire $eq$libresoc.v:20792$442_Y attribute \src "libresoc.v:20793.18-20793.111" wire $eq$libresoc.v:20793$443_Y attribute \src "libresoc.v:20794.18-20794.111" wire $eq$libresoc.v:20794$444_Y attribute \src "libresoc.v:20795.17-20795.108" wire $eq$libresoc.v:20795$445_Y attribute \src "libresoc.v:20796.18-20796.111" wire $eq$libresoc.v:20796$446_Y attribute \src "libresoc.v:20797.18-20797.111" wire $eq$libresoc.v:20797$447_Y attribute \src "libresoc.v:20798.18-20798.111" wire $eq$libresoc.v:20798$448_Y attribute \src "libresoc.v:20799.18-20799.111" wire $eq$libresoc.v:20799$449_Y attribute \src "libresoc.v:20800.18-20800.111" wire $eq$libresoc.v:20800$450_Y attribute \src "libresoc.v:20801.18-20801.111" wire $eq$libresoc.v:20801$451_Y attribute \src "libresoc.v:20802.18-20802.112" wire $eq$libresoc.v:20802$452_Y attribute \src "libresoc.v:20803.17-20803.108" wire $eq$libresoc.v:20803$453_Y attribute \src "libresoc.v:20804.17-20804.108" wire $eq$libresoc.v:20804$454_Y attribute \src "libresoc.v:20805.17-20805.108" wire $eq$libresoc.v:20805$455_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" wire \$11 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" wire \$13 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" wire \$15 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" wire \$17 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" wire \$19 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" wire \$21 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" wire \$23 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" wire \$25 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" wire \$27 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" wire \$29 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" wire \$3 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" wire \$31 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" wire \$5 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" wire \$7 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 9 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 10 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire output 1 \capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" wire width 4 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" wire width 4 \fsm_state$next attribute \src "libresoc.v:20721.7-20721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" wire output 11 \isdr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" wire \isdr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire output 4 \isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire \isir$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" wire \local_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire output 8 \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire output 6 \negjtag_rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire output 7 \posjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire output 5 \posjtag_rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" wire \rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire output 2 \shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire output 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" cell $eq $eq$libresoc.v:20790$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20790$440_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" cell $eq $eq$libresoc.v:20791$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20791$441_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" cell $eq $eq$libresoc.v:20792$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20792$442_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" cell $eq $eq$libresoc.v:20793$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 connect \Y $eq$libresoc.v:20793$443_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" cell $eq $eq$libresoc.v:20794$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20794$444_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" cell $eq $eq$libresoc.v:20795$445 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 connect \Y $eq$libresoc.v:20795$445_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" cell $eq $eq$libresoc.v:20796$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20796$446_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" cell $eq $eq$libresoc.v:20797$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20797$447_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" cell $eq $eq$libresoc.v:20798$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 connect \Y $eq$libresoc.v:20798$448_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" cell $eq $eq$libresoc.v:20799$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20799$449_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" cell $eq $eq$libresoc.v:20800$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 connect \Y $eq$libresoc.v:20800$450_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" cell $eq $eq$libresoc.v:20801$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20801$451_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" cell $eq $eq$libresoc.v:20802$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 connect \Y $eq$libresoc.v:20802$452_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" cell $eq $eq$libresoc.v:20803$453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'11 connect \Y $eq$libresoc.v:20803$453_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" cell $eq $eq$libresoc.v:20804$454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 3'101 connect \Y $eq$libresoc.v:20804$454_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" cell $eq $eq$libresoc.v:20805$455 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 4'1000 connect \Y $eq$libresoc.v:20805$455_Y end attribute \src "libresoc.v:20721.7-20721.20" process $proc$libresoc.v:20721$480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:20761.13-20761.29" process $proc$libresoc.v:20761$481 assign { } { } assign $1\fsm_state[3:0] 4'0000 sync always sync init update \fsm_state $1\fsm_state[3:0] end attribute \src "libresoc.v:20766.7-20766.18" process $proc$libresoc.v:20766$482 assign { } { } assign $1\isdr[0:0] 1'0 sync always sync init update \isdr $1\isdr[0:0] end attribute \src "libresoc.v:20771.7-20771.18" process $proc$libresoc.v:20771$483 assign { } { } assign $1\isir[0:0] 1'0 sync always sync init update \isir $1\isir[0:0] end attribute \src "libresoc.v:20806.3-20807.35" process $proc$libresoc.v:20806$456 assign { } { } assign $0\fsm_state[3:0] \fsm_state$next sync posedge \local_clk update \fsm_state $0\fsm_state[3:0] end attribute \src "libresoc.v:20808.3-20809.25" process $proc$libresoc.v:20808$457 assign { } { } assign $0\isdr[0:0] \isdr$next sync posedge \local_clk update \isdr $0\isdr[0:0] end attribute \src "libresoc.v:20810.3-20811.25" process $proc$libresoc.v:20810$458 assign { } { } assign $0\isir[0:0] \isir$next sync posedge \local_clk update \isir $0\isir[0:0] end attribute \src "libresoc.v:20812.3-20863.6" process $proc$libresoc.v:20812$459 assign { } { } assign { } { } assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 attribute \src "libresoc.v:20813.5-20813.29" switch \initial attribute \src "libresoc.v:20813.9-20813.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\isdr$next[0:0]$461 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\isdr$next[0:0]$461 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\isdr$next[0:0]$461 $2\isdr$next[0:0]$462 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\isdr$next[0:0]$462 1'1 case assign $2\isdr$next[0:0]$462 \isdr end attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\isdr$next[0:0]$461 \isdr attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\isdr$next[0:0]$461 \isdr attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\isdr$next[0:0]$461 \isdr attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\isdr$next[0:0]$461 \isdr attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\isdr$next[0:0]$461 \isdr attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign $1\isdr$next[0:0]$461 \isdr attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\isdr$next[0:0]$461 1'0 case assign $1\isdr$next[0:0]$461 \isdr end sync always update \isdr$next $0\isdr$next[0:0]$460 end attribute \src "libresoc.v:20864.3-20978.6" process $proc$libresoc.v:20864$463 assign { } { } assign { } { } assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 attribute \src "libresoc.v:20865.5-20865.29" switch \initial attribute \src "libresoc.v:20865.9-20865.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\fsm_state$next[3:0]$465 $2\fsm_state$next[3:0]$466 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fsm_state$next[3:0]$466 4'0001 case assign $2\fsm_state$next[3:0]$466 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\fsm_state$next[3:0]$465 $3\fsm_state$next[3:0]$467 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fsm_state$next[3:0]$467 4'0010 case assign $3\fsm_state$next[3:0]$467 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\fsm_state$next[3:0]$465 $4\fsm_state$next[3:0]$468 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\fsm_state$next[3:0]$468 4'0011 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $4\fsm_state$next[3:0]$468 4'0100 end attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\fsm_state$next[3:0]$465 $5\fsm_state$next[3:0]$469 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\fsm_state$next[3:0]$469 4'0011 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $5\fsm_state$next[3:0]$469 4'0000 end attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\fsm_state$next[3:0]$465 $6\fsm_state$next[3:0]$470 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\fsm_state$next[3:0]$470 4'0101 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $6\fsm_state$next[3:0]$470 4'0110 end attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\fsm_state$next[3:0]$465 $7\fsm_state$next[3:0]$471 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\fsm_state$next[3:0]$471 4'0110 case assign $7\fsm_state$next[3:0]$471 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\fsm_state$next[3:0]$465 $8\fsm_state$next[3:0]$472 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\fsm_state$next[3:0]$472 4'0111 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $8\fsm_state$next[3:0]$472 4'1000 end attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\fsm_state$next[3:0]$465 $9\fsm_state$next[3:0]$473 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\fsm_state$next[3:0]$473 4'1001 case assign $9\fsm_state$next[3:0]$473 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\fsm_state$next[3:0]$465 $10\fsm_state$next[3:0]$474 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $10\fsm_state$next[3:0]$474 4'0101 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $10\fsm_state$next[3:0]$474 4'1000 end attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\fsm_state$next[3:0]$465 $11\fsm_state$next[3:0]$475 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $11\fsm_state$next[3:0]$475 4'0001 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $11\fsm_state$next[3:0]$475 4'0010 end case assign $1\fsm_state$next[3:0]$465 \fsm_state end sync always update \fsm_state$next $0\fsm_state$next[3:0]$464 end attribute \src "libresoc.v:20979.3-21030.6" process $proc$libresoc.v:20979$476 assign { } { } assign { } { } assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 attribute \src "libresoc.v:20980.5-20980.29" switch \initial attribute \src "libresoc.v:20980.9-20980.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\isir$next[0:0]$478 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\isir$next[0:0]$478 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\isir$next[0:0]$478 \isir attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\isir$next[0:0]$479 1'1 case assign $2\isir$next[0:0]$479 \isir end attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\isir$next[0:0]$478 \isir attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\isir$next[0:0]$478 \isir attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\isir$next[0:0]$478 \isir attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\isir$next[0:0]$478 \isir attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign $1\isir$next[0:0]$478 \isir attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\isir$next[0:0]$478 1'0 case assign $1\isir$next[0:0]$478 \isir end sync always update \isir$next $0\isir$next[0:0]$477 end connect \$9 $eq$libresoc.v:20790$440_Y connect \$11 $eq$libresoc.v:20791$441_Y connect \$13 $eq$libresoc.v:20792$442_Y connect \$15 $eq$libresoc.v:20793$443_Y connect \$17 $eq$libresoc.v:20794$444_Y connect \$1 $eq$libresoc.v:20795$445_Y connect \$19 $eq$libresoc.v:20796$446_Y connect \$21 $eq$libresoc.v:20797$447_Y connect \$23 $eq$libresoc.v:20798$448_Y connect \$25 $eq$libresoc.v:20799$449_Y connect \$27 $eq$libresoc.v:20800$450_Y connect \$29 $eq$libresoc.v:20801$451_Y connect \$31 $eq$libresoc.v:20802$452_Y connect \$3 $eq$libresoc.v:20803$453_Y connect \$5 $eq$libresoc.v:20804$454_Y connect \$7 $eq$libresoc.v:20805$455_Y connect \update \$7 connect \shift \$5 connect \capture \$3 connect \rst \$1 connect \local_clk \TAP_bus__tck connect \negjtag_rst \rst connect \negjtag_clk \TAP_bus__tck connect \posjtag_rst \rst connect \posjtag_clk \TAP_bus__tck end attribute \src "libresoc.v:21044.1-21116.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" attribute \generator "nMigen" module \_idblock attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $0\TAP_id_sr$next[31:0]$489 attribute \src "libresoc.v:21087.3-21088.35" wire width 32 $0\TAP_id_sr[31:0] attribute \src "libresoc.v:21045.7-21045.20" wire $0\initial[0:0] attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $1\TAP_id_sr$next[31:0]$490 attribute \src "libresoc.v:21055.14-21055.31" wire width 32 $1\TAP_id_sr[31:0] attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $2\TAP_id_sr$next[31:0]$491 attribute \src "libresoc.v:21084.17-21084.110" wire $and$libresoc.v:21084$484_Y attribute \src "libresoc.v:21085.17-21085.108" wire $and$libresoc.v:21085$485_Y attribute \src "libresoc.v:21086.17-21086.109" wire $and$libresoc.v:21086$486_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" wire \$3 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 5 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" wire width 32 \TAP_id_sr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" wire width 32 \TAP_id_sr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" wire output 6 \TAP_id_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" wire \_bypass attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" wire \_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" wire \_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" wire \_tdi attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" wire \_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire input 2 \capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" wire input 1 \id_bypass attribute \src "libresoc.v:21045.7-21045.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 7 \posjtag_rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" wire input 9 \select_id attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire input 3 \shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 4 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" cell $and $and$libresoc.v:21084$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \select_id connect \B \capture connect \Y $and$libresoc.v:21084$484_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" cell $and $and$libresoc.v:21085$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \select_id connect \B \shift connect \Y $and$libresoc.v:21085$485_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" cell $and $and$libresoc.v:21086$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \select_id connect \B \update connect \Y $and$libresoc.v:21086$486_Y end attribute \src "libresoc.v:21045.7-21045.20" process $proc$libresoc.v:21045$492 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:21055.14-21055.31" process $proc$libresoc.v:21055$493 assign { } { } assign $1\TAP_id_sr[31:0] 0 sync always sync init update \TAP_id_sr $1\TAP_id_sr[31:0] end attribute \src "libresoc.v:21087.3-21088.35" process $proc$libresoc.v:21087$487 assign { } { } assign $0\TAP_id_sr[31:0] \TAP_id_sr$next sync posedge \posjtag_clk update \TAP_id_sr $0\TAP_id_sr[31:0] end attribute \src "libresoc.v:21089.3-21109.6" process $proc$libresoc.v:21089$488 assign { } { } assign { } { } assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 attribute \src "libresoc.v:21090.5-21090.29" switch \initial attribute \src "libresoc.v:21090.9-21090.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" switch { \_shift \_capture } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\TAP_id_sr$next[31:0]$490 6399 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\TAP_id_sr$next[31:0]$490 $2\TAP_id_sr$next[31:0]$491 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" switch \_bypass attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\TAP_id_sr$next[31:0]$491 [31:1] \TAP_id_sr [31:1] assign $2\TAP_id_sr$next[31:0]$491 [0] \_tdi attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\TAP_id_sr$next[31:0]$491 { \_tdi \TAP_id_sr [31:1] } end case assign $1\TAP_id_sr$next[31:0]$490 \TAP_id_sr end sync always update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 end connect \$1 $and$libresoc.v:21084$484_Y connect \$3 $and$libresoc.v:21085$485_Y connect \$5 $and$libresoc.v:21086$486_Y connect \TAP_id_tdo \TAP_id_sr [0] connect \_bypass \id_bypass connect \_update \$5 connect \_shift \$3 connect \_capture \$1 connect \_tdi \TAP_bus__tdi end attribute \src "libresoc.v:21120.1-21204.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" attribute \generator "nMigen" module \_irblock attribute \src "libresoc.v:21121.7-21121.20" wire $0\initial[0:0] attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $0\ir$next[3:0]$506 attribute \src "libresoc.v:21165.3-21166.21" wire width 4 $0\ir[3:0] attribute \src "libresoc.v:21169.3-21181.6" wire width 4 $0\shift_ir$next[3:0]$503 attribute \src "libresoc.v:21167.3-21168.33" wire width 4 $0\shift_ir[3:0] attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $1\ir$next[3:0]$507 attribute \src "libresoc.v:21140.13-21140.22" wire width 4 $1\ir[3:0] attribute \src "libresoc.v:21169.3-21181.6" wire width 4 $1\shift_ir$next[3:0]$504 attribute \src "libresoc.v:21152.13-21152.28" wire width 4 $1\shift_ir[3:0] attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $2\ir$next[3:0]$508 attribute \src "libresoc.v:21159.17-21159.103" wire $and$libresoc.v:21159$494_Y attribute \src "libresoc.v:21160.18-21160.105" wire $and$libresoc.v:21160$495_Y attribute \src "libresoc.v:21161.17-21161.105" wire $and$libresoc.v:21161$496_Y attribute \src "libresoc.v:21162.17-21162.103" wire $and$libresoc.v:21162$497_Y attribute \src "libresoc.v:21163.17-21163.104" wire $and$libresoc.v:21163$498_Y attribute \src "libresoc.v:21164.17-21164.105" wire $and$libresoc.v:21164$499_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" wire \$11 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" wire \$3 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" wire \$5 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$7 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 4 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire input 1 \capture attribute \src "libresoc.v:21121.7-21121.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 output 9 \ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 \ir$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire input 5 \isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 7 \posjtag_rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire input 2 \shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" wire width 4 \shift_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" wire width 4 \shift_ir$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire output 6 \tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" cell $and $and$libresoc.v:21159$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \isir connect \B \shift connect \Y $and$libresoc.v:21159$494_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" cell $and $and$libresoc.v:21160$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \isir connect \B \update connect \Y $and$libresoc.v:21160$495_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" cell $and $and$libresoc.v:21161$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \isir connect \B \capture connect \Y $and$libresoc.v:21161$496_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" cell $and $and$libresoc.v:21162$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \isir connect \B \shift connect \Y $and$libresoc.v:21162$497_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" cell $and $and$libresoc.v:21163$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \isir connect \B \update connect \Y $and$libresoc.v:21163$498_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" cell $and $and$libresoc.v:21164$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \isir connect \B \capture connect \Y $and$libresoc.v:21164$499_Y end attribute \src "libresoc.v:21121.7-21121.20" process $proc$libresoc.v:21121$509 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:21140.13-21140.22" process $proc$libresoc.v:21140$510 assign { } { } assign $1\ir[3:0] 4'0001 sync always sync init update \ir $1\ir[3:0] end attribute \src "libresoc.v:21152.13-21152.28" process $proc$libresoc.v:21152$511 assign { } { } assign $1\shift_ir[3:0] 4'0000 sync always sync init update \shift_ir $1\shift_ir[3:0] end attribute \src "libresoc.v:21165.3-21166.21" process $proc$libresoc.v:21165$500 assign { } { } assign $0\ir[3:0] \ir$next sync posedge \posjtag_clk update \ir $0\ir[3:0] end attribute \src "libresoc.v:21167.3-21168.33" process $proc$libresoc.v:21167$501 assign { } { } assign $0\shift_ir[3:0] \shift_ir$next sync posedge \posjtag_clk update \shift_ir $0\shift_ir[3:0] end attribute \src "libresoc.v:21169.3-21181.6" process $proc$libresoc.v:21169$502 assign { } { } assign { } { } assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 attribute \src "libresoc.v:21170.5-21170.29" switch \initial attribute \src "libresoc.v:21170.9-21170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" switch { \$5 \$3 \$1 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\shift_ir$next[3:0]$504 \ir attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $1\shift_ir$next[3:0]$504 { \TAP_bus__tdi \shift_ir [3:1] } case assign $1\shift_ir$next[3:0]$504 \shift_ir end sync always update \shift_ir$next $0\shift_ir$next[3:0]$503 end attribute \src "libresoc.v:21182.3-21202.6" process $proc$libresoc.v:21182$505 assign { } { } assign { } { } assign { } { } assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 attribute \src "libresoc.v:21183.5-21183.29" switch \initial attribute \src "libresoc.v:21183.9-21183.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" switch { \$11 \$9 \$7 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign $1\ir$next[3:0]$507 \ir attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign $1\ir$next[3:0]$507 \ir attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $1\ir$next[3:0]$507 \shift_ir case assign $1\ir$next[3:0]$507 \ir end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ir$next[3:0]$508 4'0001 case assign $2\ir$next[3:0]$508 $1\ir$next[3:0]$507 end sync always update \ir$next $0\ir$next[3:0]$506 end connect \$9 $and$libresoc.v:21159$494_Y connect \$11 $and$libresoc.v:21160$495_Y connect \$1 $and$libresoc.v:21161$496_Y connect \$3 $and$libresoc.v:21162$497_Y connect \$5 $and$libresoc.v:21163$498_Y connect \$7 $and$libresoc.v:21164$499_Y connect \tdo \ir [0] end attribute \src "libresoc.v:21208.1-21266.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" attribute \generator "nMigen" module \adr_l attribute \src "libresoc.v:21209.7-21209.20" wire $0\initial[0:0] attribute \src "libresoc.v:21254.3-21262.6" wire $0\q_int$next[0:0]$522 attribute \src "libresoc.v:21252.3-21253.27" wire $0\q_int[0:0] attribute \src "libresoc.v:21254.3-21262.6" wire $1\q_int$next[0:0]$523 attribute \src "libresoc.v:21233.7-21233.19" wire $1\q_int[0:0] attribute \src "libresoc.v:21244.17-21244.96" wire $and$libresoc.v:21244$512_Y attribute \src "libresoc.v:21249.17-21249.96" wire $and$libresoc.v:21249$517_Y attribute \src "libresoc.v:21246.18-21246.93" wire $not$libresoc.v:21246$514_Y attribute \src "libresoc.v:21248.17-21248.92" wire $not$libresoc.v:21248$516_Y attribute \src "libresoc.v:21251.17-21251.92" wire $not$libresoc.v:21251$519_Y attribute \src "libresoc.v:21245.18-21245.98" wire $or$libresoc.v:21245$513_Y attribute \src "libresoc.v:21247.18-21247.99" wire $or$libresoc.v:21247$515_Y attribute \src "libresoc.v:21250.17-21250.97" wire $or$libresoc.v:21250$518_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:21209.7-21209.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:21244$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:21244$512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:21249$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:21249$517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:21246$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_adr connect \Y $not$libresoc.v:21246$514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:21248$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr connect \Y $not$libresoc.v:21248$516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:21251$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr connect \Y $not$libresoc.v:21251$519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:21245$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_adr connect \Y $or$libresoc.v:21245$513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:21247$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_adr connect \B \q_int connect \Y $or$libresoc.v:21247$515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:21250$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_adr connect \Y $or$libresoc.v:21250$518_Y end attribute \src "libresoc.v:21209.7-21209.20" process $proc$libresoc.v:21209$524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:21233.7-21233.19" process $proc$libresoc.v:21233$525 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:21252.3-21253.27" process $proc$libresoc.v:21252$520 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:21254.3-21262.6" process $proc$libresoc.v:21254$521 assign { } { } assign { } { } assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 attribute \src "libresoc.v:21255.5-21255.29" switch \initial attribute \src "libresoc.v:21255.9-21255.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$523 1'0 case assign $1\q_int$next[0:0]$523 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$522 end connect \$9 $and$libresoc.v:21244$512_Y connect \$11 $or$libresoc.v:21245$513_Y connect \$13 $not$libresoc.v:21246$514_Y connect \$15 $or$libresoc.v:21247$515_Y connect \$1 $not$libresoc.v:21248$516_Y connect \$3 $and$libresoc.v:21249$517_Y connect \$5 $or$libresoc.v:21250$518_Y connect \$7 $not$libresoc.v:21251$519_Y connect \qlq_adr \$15 connect \qn_adr \$13 connect \q_adr \$11 end attribute \src "libresoc.v:21270.1-21328.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" attribute \generator "nMigen" module \adrok_l attribute \src "libresoc.v:21271.7-21271.20" wire $0\initial[0:0] attribute \src "libresoc.v:21316.3-21324.6" wire $0\q_int$next[0:0]$536 attribute \src "libresoc.v:21314.3-21315.27" wire $0\q_int[0:0] attribute \src "libresoc.v:21316.3-21324.6" wire $1\q_int$next[0:0]$537 attribute \src "libresoc.v:21295.7-21295.19" wire $1\q_int[0:0] attribute \src "libresoc.v:21306.17-21306.96" wire $and$libresoc.v:21306$526_Y attribute \src "libresoc.v:21311.17-21311.96" wire $and$libresoc.v:21311$531_Y attribute \src "libresoc.v:21308.18-21308.100" wire $not$libresoc.v:21308$528_Y attribute \src "libresoc.v:21310.17-21310.99" wire $not$libresoc.v:21310$530_Y attribute \src "libresoc.v:21313.17-21313.99" wire $not$libresoc.v:21313$533_Y attribute \src "libresoc.v:21307.18-21307.105" wire $or$libresoc.v:21307$527_Y attribute \src "libresoc.v:21309.18-21309.106" wire $or$libresoc.v:21309$529_Y attribute \src "libresoc.v:21312.17-21312.104" wire $or$libresoc.v:21312$532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 6 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:21271.7-21271.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 5 \q_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire output 4 \qn_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:21306$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:21306$526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:21311$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:21311$531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:21308$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_addr_acked connect \Y $not$libresoc.v:21308$528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:21310$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked connect \Y $not$libresoc.v:21310$530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:21313$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked connect \Y $not$libresoc.v:21313$533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:21307$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_addr_acked connect \Y $or$libresoc.v:21307$527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:21309$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_addr_acked connect \B \q_int connect \Y $or$libresoc.v:21309$529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:21312$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_addr_acked connect \Y $or$libresoc.v:21312$532_Y end attribute \src "libresoc.v:21271.7-21271.20" process $proc$libresoc.v:21271$538 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:21295.7-21295.19" process $proc$libresoc.v:21295$539 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:21314.3-21315.27" process $proc$libresoc.v:21314$534 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:21316.3-21324.6" process $proc$libresoc.v:21316$535 assign { } { } assign { } { } assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 attribute \src "libresoc.v:21317.5-21317.29" switch \initial attribute \src "libresoc.v:21317.9-21317.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$537 1'0 case assign $1\q_int$next[0:0]$537 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$536 end connect \$9 $and$libresoc.v:21306$526_Y connect \$11 $or$libresoc.v:21307$527_Y connect \$13 $not$libresoc.v:21308$528_Y connect \$15 $or$libresoc.v:21309$529_Y connect \$1 $not$libresoc.v:21310$530_Y connect \$3 $and$libresoc.v:21311$531_Y connect \$5 $or$libresoc.v:21312$532_Y connect \$7 $not$libresoc.v:21313$533_Y connect \qlq_addr_acked \$15 connect \qn_addr_acked \$13 connect \q_addr_acked \$11 end attribute \src "libresoc.v:21332.1-22663.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" attribute \generator "nMigen" module \alu0 attribute \src "libresoc.v:22174.3-22175.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 attribute \src "libresoc.v:22146.3-22147.67" wire width 4 $0\alu_alu0_alu_op__data_len[3:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 14 $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 attribute \src "libresoc.v:22116.3-22117.65" wire width 14 $0\alu_alu0_alu_op__fn_unit[13:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 attribute \src "libresoc.v:22118.3-22119.79" wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 attribute \src "libresoc.v:22120.3-22121.75" wire $0\alu_alu0_alu_op__imm_data__ok[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 attribute \src "libresoc.v:22138.3-22139.73" wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 attribute \src "libresoc.v:22148.3-22149.59" wire width 32 $0\alu_alu0_alu_op__insn[31:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 attribute \src "libresoc.v:22114.3-22115.69" wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 attribute \src "libresoc.v:22130.3-22131.69" wire $0\alu_alu0_alu_op__invert_in[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 attribute \src "libresoc.v:22134.3-22135.71" wire $0\alu_alu0_alu_op__invert_out[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 attribute \src "libresoc.v:22142.3-22143.67" wire $0\alu_alu0_alu_op__is_32bit[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 attribute \src "libresoc.v:22144.3-22145.69" wire $0\alu_alu0_alu_op__is_signed[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 attribute \src "libresoc.v:22126.3-22127.63" wire $0\alu_alu0_alu_op__oe__oe[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 attribute \src "libresoc.v:22128.3-22129.63" wire $0\alu_alu0_alu_op__oe__ok[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 attribute \src "libresoc.v:22140.3-22141.75" wire $0\alu_alu0_alu_op__output_carry[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 attribute \src "libresoc.v:22124.3-22125.63" wire $0\alu_alu0_alu_op__rc__ok[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 attribute \src "libresoc.v:22122.3-22123.63" wire $0\alu_alu0_alu_op__rc__rc[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 attribute \src "libresoc.v:22136.3-22137.69" wire $0\alu_alu0_alu_op__write_cr0[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 attribute \src "libresoc.v:22132.3-22133.63" wire $0\alu_alu0_alu_op__zero_a[0:0] attribute \src "libresoc.v:22172.3-22173.40" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:22562.3-22570.6" wire $0\alu_l_r_alu$next[0:0]$784 attribute \src "libresoc.v:22082.3-22083.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:22553.3-22561.6" wire $0\alui_l_r_alui$next[0:0]$781 attribute \src "libresoc.v:22084.3-22085.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $0\data_r0__o$next[63:0]$729 attribute \src "libresoc.v:22110.3-22111.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:22403.3-22424.6" wire $0\data_r0__o_ok$next[0:0]$730 attribute \src "libresoc.v:22112.3-22113.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $0\data_r1__cr_a$next[3:0]$737 attribute \src "libresoc.v:22106.3-22107.43" wire width 4 $0\data_r1__cr_a[3:0] attribute \src "libresoc.v:22425.3-22446.6" wire $0\data_r1__cr_a_ok$next[0:0]$738 attribute \src "libresoc.v:22108.3-22109.49" wire $0\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $0\data_r2__xer_ca$next[1:0]$745 attribute \src "libresoc.v:22102.3-22103.47" wire width 2 $0\data_r2__xer_ca[1:0] attribute \src "libresoc.v:22447.3-22468.6" wire $0\data_r2__xer_ca_ok$next[0:0]$746 attribute \src "libresoc.v:22104.3-22105.53" wire $0\data_r2__xer_ca_ok[0:0] attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $0\data_r3__xer_ov$next[1:0]$753 attribute \src "libresoc.v:22098.3-22099.47" wire width 2 $0\data_r3__xer_ov[1:0] attribute \src "libresoc.v:22469.3-22490.6" wire $0\data_r3__xer_ov_ok$next[0:0]$754 attribute \src "libresoc.v:22100.3-22101.53" wire $0\data_r3__xer_ov_ok[0:0] attribute \src "libresoc.v:22491.3-22512.6" wire $0\data_r4__xer_so$next[0:0]$761 attribute \src "libresoc.v:22094.3-22095.47" wire $0\data_r4__xer_so[0:0] attribute \src "libresoc.v:22491.3-22512.6" wire $0\data_r4__xer_so_ok$next[0:0]$762 attribute \src "libresoc.v:22096.3-22097.53" wire $0\data_r4__xer_so_ok[0:0] attribute \src "libresoc.v:22571.3-22580.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:22581.3-22590.6" wire width 4 $0\dest2_o[3:0] attribute \src "libresoc.v:22591.3-22600.6" wire width 2 $0\dest3_o[1:0] attribute \src "libresoc.v:22601.3-22610.6" wire width 2 $0\dest4_o[1:0] attribute \src "libresoc.v:22611.3-22620.6" wire $0\dest5_o[0:0] attribute \src "libresoc.v:21333.7-21333.20" wire $0\initial[0:0] attribute \src "libresoc.v:22319.3-22327.6" wire $0\opc_l_r_opc$next[0:0]$671 attribute \src "libresoc.v:22158.3-22159.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:22310.3-22318.6" wire $0\opc_l_s_opc$next[0:0]$668 attribute \src "libresoc.v:22160.3-22161.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:22621.3-22629.6" wire width 5 $0\prev_wr_go$next[4:0]$792 attribute \src "libresoc.v:22170.3-22171.37" wire width 5 $0\prev_wr_go[4:0] attribute \src "libresoc.v:22264.3-22273.6" wire $0\req_done[0:0] attribute \src "libresoc.v:22355.3-22363.6" wire width 5 $0\req_l_r_req$next[4:0]$683 attribute \src "libresoc.v:22150.3-22151.39" wire width 5 $0\req_l_r_req[4:0] attribute \src "libresoc.v:22346.3-22354.6" wire width 5 $0\req_l_s_req$next[4:0]$680 attribute \src "libresoc.v:22152.3-22153.39" wire width 5 $0\req_l_s_req[4:0] attribute \src "libresoc.v:22283.3-22291.6" wire $0\rok_l_r_rdok$next[0:0]$659 attribute \src "libresoc.v:22166.3-22167.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:22274.3-22282.6" wire $0\rok_l_s_rdok$next[0:0]$656 attribute \src "libresoc.v:22168.3-22169.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:22301.3-22309.6" wire $0\rst_l_r_rst$next[0:0]$665 attribute \src "libresoc.v:22162.3-22163.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:22292.3-22300.6" wire $0\rst_l_s_rst$next[0:0]$662 attribute \src "libresoc.v:22164.3-22165.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:22337.3-22345.6" wire width 4 $0\src_l_r_src$next[3:0]$677 attribute \src "libresoc.v:22154.3-22155.39" wire width 4 $0\src_l_r_src[3:0] attribute \src "libresoc.v:22328.3-22336.6" wire width 4 $0\src_l_s_src$next[3:0]$674 attribute \src "libresoc.v:22156.3-22157.39" wire width 4 $0\src_l_s_src[3:0] attribute \src "libresoc.v:22513.3-22522.6" wire width 64 $0\src_r0$next[63:0]$769 attribute \src "libresoc.v:22092.3-22093.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $0\src_r1$next[63:0]$772 attribute \src "libresoc.v:22090.3-22091.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:22533.3-22542.6" wire $0\src_r2$next[0:0]$775 attribute \src "libresoc.v:22088.3-22089.29" wire $0\src_r2[0:0] attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $0\src_r3$next[1:0]$778 attribute \src "libresoc.v:22086.3-22087.29" wire width 2 $0\src_r3[1:0] attribute \src "libresoc.v:21471.7-21471.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 attribute \src "libresoc.v:21479.13-21479.45" wire width 4 $1\alu_alu0_alu_op__data_len[3:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 14 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 attribute \src "libresoc.v:21498.14-21498.49" wire width 14 $1\alu_alu0_alu_op__fn_unit[13:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 attribute \src "libresoc.v:21502.14-21502.68" wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 attribute \src "libresoc.v:21506.7-21506.43" wire $1\alu_alu0_alu_op__imm_data__ok[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 attribute \src "libresoc.v:21514.13-21514.48" wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 attribute \src "libresoc.v:21518.14-21518.43" wire width 32 $1\alu_alu0_alu_op__insn[31:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 attribute \src "libresoc.v:21597.13-21597.47" wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 attribute \src "libresoc.v:21601.7-21601.40" wire $1\alu_alu0_alu_op__invert_in[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 attribute \src "libresoc.v:21605.7-21605.41" wire $1\alu_alu0_alu_op__invert_out[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 attribute \src "libresoc.v:21609.7-21609.39" wire $1\alu_alu0_alu_op__is_32bit[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 attribute \src "libresoc.v:21613.7-21613.40" wire $1\alu_alu0_alu_op__is_signed[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 attribute \src "libresoc.v:21617.7-21617.37" wire $1\alu_alu0_alu_op__oe__oe[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 attribute \src "libresoc.v:21621.7-21621.37" wire $1\alu_alu0_alu_op__oe__ok[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 attribute \src "libresoc.v:21625.7-21625.43" wire $1\alu_alu0_alu_op__output_carry[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 attribute \src "libresoc.v:21629.7-21629.37" wire $1\alu_alu0_alu_op__rc__ok[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 attribute \src "libresoc.v:21633.7-21633.37" wire $1\alu_alu0_alu_op__rc__rc[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 attribute \src "libresoc.v:21637.7-21637.40" wire $1\alu_alu0_alu_op__write_cr0[0:0] attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 attribute \src "libresoc.v:21641.7-21641.37" wire $1\alu_alu0_alu_op__zero_a[0:0] attribute \src "libresoc.v:21673.7-21673.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:22562.3-22570.6" wire $1\alu_l_r_alu$next[0:0]$785 attribute \src "libresoc.v:21681.7-21681.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:22553.3-22561.6" wire $1\alui_l_r_alui$next[0:0]$782 attribute \src "libresoc.v:21693.7-21693.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $1\data_r0__o$next[63:0]$731 attribute \src "libresoc.v:21727.14-21727.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:22403.3-22424.6" wire $1\data_r0__o_ok$next[0:0]$732 attribute \src "libresoc.v:21731.7-21731.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $1\data_r1__cr_a$next[3:0]$739 attribute \src "libresoc.v:21735.13-21735.33" wire width 4 $1\data_r1__cr_a[3:0] attribute \src "libresoc.v:22425.3-22446.6" wire $1\data_r1__cr_a_ok$next[0:0]$740 attribute \src "libresoc.v:21739.7-21739.30" wire $1\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $1\data_r2__xer_ca$next[1:0]$747 attribute \src "libresoc.v:21743.13-21743.35" wire width 2 $1\data_r2__xer_ca[1:0] attribute \src "libresoc.v:22447.3-22468.6" wire $1\data_r2__xer_ca_ok$next[0:0]$748 attribute \src "libresoc.v:21747.7-21747.32" wire $1\data_r2__xer_ca_ok[0:0] attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $1\data_r3__xer_ov$next[1:0]$755 attribute \src "libresoc.v:21751.13-21751.35" wire width 2 $1\data_r3__xer_ov[1:0] attribute \src "libresoc.v:22469.3-22490.6" wire $1\data_r3__xer_ov_ok$next[0:0]$756 attribute \src "libresoc.v:21755.7-21755.32" wire $1\data_r3__xer_ov_ok[0:0] attribute \src "libresoc.v:22491.3-22512.6" wire $1\data_r4__xer_so$next[0:0]$763 attribute \src "libresoc.v:21759.7-21759.29" wire $1\data_r4__xer_so[0:0] attribute \src "libresoc.v:22491.3-22512.6" wire $1\data_r4__xer_so_ok$next[0:0]$764 attribute \src "libresoc.v:21763.7-21763.32" wire $1\data_r4__xer_so_ok[0:0] attribute \src "libresoc.v:22571.3-22580.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:22581.3-22590.6" wire width 4 $1\dest2_o[3:0] attribute \src "libresoc.v:22591.3-22600.6" wire width 2 $1\dest3_o[1:0] attribute \src "libresoc.v:22601.3-22610.6" wire width 2 $1\dest4_o[1:0] attribute \src "libresoc.v:22611.3-22620.6" wire $1\dest5_o[0:0] attribute \src "libresoc.v:22319.3-22327.6" wire $1\opc_l_r_opc$next[0:0]$672 attribute \src "libresoc.v:21786.7-21786.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:22310.3-22318.6" wire $1\opc_l_s_opc$next[0:0]$669 attribute \src "libresoc.v:21790.7-21790.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:22621.3-22629.6" wire width 5 $1\prev_wr_go$next[4:0]$793 attribute \src "libresoc.v:21924.13-21924.31" wire width 5 $1\prev_wr_go[4:0] attribute \src "libresoc.v:22264.3-22273.6" wire $1\req_done[0:0] attribute \src "libresoc.v:22355.3-22363.6" wire width 5 $1\req_l_r_req$next[4:0]$684 attribute \src "libresoc.v:21932.13-21932.32" wire width 5 $1\req_l_r_req[4:0] attribute \src "libresoc.v:22346.3-22354.6" wire width 5 $1\req_l_s_req$next[4:0]$681 attribute \src "libresoc.v:21936.13-21936.32" wire width 5 $1\req_l_s_req[4:0] attribute \src "libresoc.v:22283.3-22291.6" wire $1\rok_l_r_rdok$next[0:0]$660 attribute \src "libresoc.v:21948.7-21948.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:22274.3-22282.6" wire $1\rok_l_s_rdok$next[0:0]$657 attribute \src "libresoc.v:21952.7-21952.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:22301.3-22309.6" wire $1\rst_l_r_rst$next[0:0]$666 attribute \src "libresoc.v:21956.7-21956.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:22292.3-22300.6" wire $1\rst_l_s_rst$next[0:0]$663 attribute \src "libresoc.v:21960.7-21960.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:22337.3-22345.6" wire width 4 $1\src_l_r_src$next[3:0]$678 attribute \src "libresoc.v:21976.13-21976.31" wire width 4 $1\src_l_r_src[3:0] attribute \src "libresoc.v:22328.3-22336.6" wire width 4 $1\src_l_s_src$next[3:0]$675 attribute \src "libresoc.v:21980.13-21980.31" wire width 4 $1\src_l_s_src[3:0] attribute \src "libresoc.v:22513.3-22522.6" wire width 64 $1\src_r0$next[63:0]$770 attribute \src "libresoc.v:21988.14-21988.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $1\src_r1$next[63:0]$773 attribute \src "libresoc.v:21992.14-21992.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:22533.3-22542.6" wire $1\src_r2$next[0:0]$776 attribute \src "libresoc.v:21996.7-21996.20" wire $1\src_r2[0:0] attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $1\src_r3$next[1:0]$779 attribute \src "libresoc.v:22000.13-22000.26" wire width 2 $1\src_r3[1:0] attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $2\data_r0__o$next[63:0]$733 attribute \src "libresoc.v:22403.3-22424.6" wire $2\data_r0__o_ok$next[0:0]$734 attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $2\data_r1__cr_a$next[3:0]$741 attribute \src "libresoc.v:22425.3-22446.6" wire $2\data_r1__cr_a_ok$next[0:0]$742 attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $2\data_r2__xer_ca$next[1:0]$749 attribute \src "libresoc.v:22447.3-22468.6" wire $2\data_r2__xer_ca_ok$next[0:0]$750 attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $2\data_r3__xer_ov$next[1:0]$757 attribute \src "libresoc.v:22469.3-22490.6" wire $2\data_r3__xer_ov_ok$next[0:0]$758 attribute \src "libresoc.v:22491.3-22512.6" wire $2\data_r4__xer_so$next[0:0]$765 attribute \src "libresoc.v:22491.3-22512.6" wire $2\data_r4__xer_so_ok$next[0:0]$766 attribute \src "libresoc.v:22403.3-22424.6" wire $3\data_r0__o_ok$next[0:0]$735 attribute \src "libresoc.v:22425.3-22446.6" wire $3\data_r1__cr_a_ok$next[0:0]$743 attribute \src "libresoc.v:22447.3-22468.6" wire $3\data_r2__xer_ca_ok$next[0:0]$751 attribute \src "libresoc.v:22469.3-22490.6" wire $3\data_r3__xer_ov_ok$next[0:0]$759 attribute \src "libresoc.v:22491.3-22512.6" wire $3\data_r4__xer_so_ok$next[0:0]$767 attribute \src "libresoc.v:22016.18-22016.134" wire $and$libresoc.v:22016$541_Y attribute \src "libresoc.v:22017.19-22017.133" wire $and$libresoc.v:22017$542_Y attribute \src "libresoc.v:22018.19-22018.161" wire width 4 $and$libresoc.v:22018$543_Y attribute \src "libresoc.v:22021.19-22021.134" wire width 4 $and$libresoc.v:22021$546_Y attribute \src "libresoc.v:22023.19-22023.115" wire width 4 $and$libresoc.v:22023$548_Y attribute \src "libresoc.v:22024.19-22024.125" wire $and$libresoc.v:22024$549_Y attribute \src "libresoc.v:22025.19-22025.125" wire $and$libresoc.v:22025$550_Y attribute \src "libresoc.v:22026.18-22026.110" wire $and$libresoc.v:22026$551_Y attribute \src "libresoc.v:22027.19-22027.125" wire $and$libresoc.v:22027$552_Y attribute \src "libresoc.v:22028.19-22028.125" wire $and$libresoc.v:22028$553_Y attribute \src "libresoc.v:22029.19-22029.125" wire $and$libresoc.v:22029$554_Y attribute \src "libresoc.v:22030.19-22030.157" wire width 5 $and$libresoc.v:22030$555_Y attribute \src "libresoc.v:22031.19-22031.121" wire width 5 $and$libresoc.v:22031$556_Y attribute \src "libresoc.v:22032.19-22032.127" wire $and$libresoc.v:22032$557_Y attribute \src "libresoc.v:22033.19-22033.127" wire $and$libresoc.v:22033$558_Y attribute \src "libresoc.v:22034.19-22034.127" wire $and$libresoc.v:22034$559_Y attribute \src "libresoc.v:22035.19-22035.127" wire $and$libresoc.v:22035$560_Y attribute \src "libresoc.v:22036.19-22036.127" wire $and$libresoc.v:22036$561_Y attribute \src "libresoc.v:22038.18-22038.98" wire $and$libresoc.v:22038$563_Y attribute \src "libresoc.v:22040.18-22040.100" wire $and$libresoc.v:22040$565_Y attribute \src "libresoc.v:22041.18-22041.171" wire width 5 $and$libresoc.v:22041$566_Y attribute \src "libresoc.v:22043.18-22043.119" wire width 5 $and$libresoc.v:22043$568_Y attribute \src "libresoc.v:22046.18-22046.116" wire $and$libresoc.v:22046$571_Y attribute \src "libresoc.v:22050.17-22050.123" wire $and$libresoc.v:22050$575_Y attribute \src "libresoc.v:22052.18-22052.113" wire $and$libresoc.v:22052$577_Y attribute \src "libresoc.v:22053.18-22053.125" wire width 5 $and$libresoc.v:22053$578_Y attribute \src "libresoc.v:22055.18-22055.112" wire $and$libresoc.v:22055$580_Y attribute \src "libresoc.v:22057.18-22057.126" wire $and$libresoc.v:22057$582_Y attribute \src "libresoc.v:22058.18-22058.126" wire $and$libresoc.v:22058$583_Y attribute \src "libresoc.v:22059.18-22059.117" wire $and$libresoc.v:22059$584_Y attribute \src "libresoc.v:22064.18-22064.130" wire $and$libresoc.v:22064$589_Y attribute \src "libresoc.v:22065.18-22065.124" wire width 5 $and$libresoc.v:22065$590_Y attribute \src "libresoc.v:22068.18-22068.116" wire $and$libresoc.v:22068$593_Y attribute \src "libresoc.v:22069.18-22069.119" wire $and$libresoc.v:22069$594_Y attribute \src "libresoc.v:22070.18-22070.121" wire $and$libresoc.v:22070$595_Y attribute \src "libresoc.v:22071.18-22071.121" wire $and$libresoc.v:22071$596_Y attribute \src "libresoc.v:22072.18-22072.121" wire $and$libresoc.v:22072$597_Y attribute \src "libresoc.v:22054.18-22054.113" wire $eq$libresoc.v:22054$579_Y attribute \src "libresoc.v:22056.18-22056.119" wire $eq$libresoc.v:22056$581_Y attribute \src "libresoc.v:22019.19-22019.126" wire $not$libresoc.v:22019$544_Y attribute \src "libresoc.v:22020.19-22020.132" wire $not$libresoc.v:22020$545_Y attribute \src "libresoc.v:22022.19-22022.115" wire width 4 $not$libresoc.v:22022$547_Y attribute \src "libresoc.v:22037.18-22037.97" wire $not$libresoc.v:22037$562_Y attribute \src "libresoc.v:22039.18-22039.99" wire $not$libresoc.v:22039$564_Y attribute \src "libresoc.v:22042.18-22042.113" wire width 5 $not$libresoc.v:22042$567_Y attribute \src "libresoc.v:22045.18-22045.106" wire $not$libresoc.v:22045$570_Y attribute \src "libresoc.v:22051.18-22051.120" wire $not$libresoc.v:22051$576_Y attribute \src "libresoc.v:22066.17-22066.113" wire width 4 $not$libresoc.v:22066$591_Y attribute \src "libresoc.v:22049.18-22049.112" wire $or$libresoc.v:22049$574_Y attribute \src "libresoc.v:22060.18-22060.122" wire $or$libresoc.v:22060$585_Y attribute \src "libresoc.v:22061.18-22061.124" wire $or$libresoc.v:22061$586_Y attribute \src "libresoc.v:22062.18-22062.181" wire width 5 $or$libresoc.v:22062$587_Y attribute \src "libresoc.v:22063.18-22063.168" wire width 4 $or$libresoc.v:22063$588_Y attribute \src "libresoc.v:22067.18-22067.120" wire width 5 $or$libresoc.v:22067$592_Y attribute \src "libresoc.v:22076.17-22076.117" wire width 4 $or$libresoc.v:22076$601_Y attribute \src "libresoc.v:22015.17-22015.104" wire $reduce_and$libresoc.v:22015$540_Y attribute \src "libresoc.v:22044.18-22044.106" wire $reduce_or$libresoc.v:22044$569_Y attribute \src "libresoc.v:22047.18-22047.113" wire $reduce_or$libresoc.v:22047$572_Y attribute \src "libresoc.v:22048.18-22048.112" wire $reduce_or$libresoc.v:22048$573_Y attribute \src "libresoc.v:22073.18-22073.154" wire $ternary$libresoc.v:22073$598_Y attribute \src "libresoc.v:22074.18-22074.155" wire width 64 $ternary$libresoc.v:22074$599_Y attribute \src "libresoc.v:22075.18-22075.160" wire $ternary$libresoc.v:22075$600_Y attribute \src "libresoc.v:22077.18-22077.172" wire width 64 $ternary$libresoc.v:22077$602_Y attribute \src "libresoc.v:22078.18-22078.115" wire width 64 $ternary$libresoc.v:22078$603_Y attribute \src "libresoc.v:22079.18-22079.125" wire width 64 $ternary$libresoc.v:22079$604_Y attribute \src "libresoc.v:22080.18-22080.118" wire $ternary$libresoc.v:22080$605_Y attribute \src "libresoc.v:22081.18-22081.118" wire width 2 $ternary$libresoc.v:22081$606_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 5 \$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 5 \$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$137 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 5 \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 5 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 5 \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 5 \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 4 \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 5 \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 4 \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 5 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 5 \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 4 \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$95 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_alu0_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_alu0_alu_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_alu0_alu_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_alu0_alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_alu0_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_alu0_alu_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_alu0_alu_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_alu0_alu_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_alu0_alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_alu0_alu_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_alu0_alu_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_alu0_alu_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__zero_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_alu0_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_alu0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_alu0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_alu0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_alu0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_alu0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_alu0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_alu0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_alu0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_alu0_xer_ca$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_alu0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_alu0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_alu0_xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 5 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 41 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 21 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 20 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 24 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 23 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 input 22 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 input 31 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 output 30 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 5 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r3__xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r3__xer_ov$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 32 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 38 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 40 \dest5_o attribute \src "libresoc.v:21333.7-21333.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \oper_i_alu_alu0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 14 \oper_i_alu_alu0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 19 \oper_i_alu_alu0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \oper_i_alu_alu0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \oper_i_alu_alu0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \oper_i_alu_alu0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \oper_i_alu_alu0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \oper_i_alu_alu0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_alu_alu0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \oper_i_alu_alu0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \oper_i_alu_alu0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \oper_i_alu_alu0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \oper_i_alu_alu0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \oper_i_alu_alu0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 5 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 5 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 4 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 5 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 28 \src4_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:22016$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:22016$541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:22017$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:22017$542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:22018$543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:22018$543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:22021$546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$103 connect \B { 2'11 \$107 \$105 } connect \Y $and$libresoc.v:22021$546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:22023$548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$109 connect \B \$111 connect \Y $and$libresoc.v:22023$548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:22024$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:22024$549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:22025$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:22025$550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:22026$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 connect \Y $and$libresoc.v:22026$551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:22027$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:22027$552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:22028$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:22028$553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:22029$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:22029$554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:22030$555 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$115 \$117 \$119 \$121 \$123 } connect \Y $and$libresoc.v:22030$555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:22031$556 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$125 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:22031$556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:22032$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:22032$557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:22033$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:22033$558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:22034$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:22034$559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:22035$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o connect \Y $and$libresoc.v:22035$560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:22036$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o connect \Y $and$libresoc.v:22036$561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:22038$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 connect \Y $and$libresoc.v:22038$563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:22040$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 connect \Y $and$libresoc.v:22040$565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:22041$566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:22041$566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:22043$568 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 connect \Y $and$libresoc.v:22043$568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:22046$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 connect \Y $and$libresoc.v:22046$571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:22050$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:22050$575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:22052$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 connect \Y $and$libresoc.v:22052$577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:22053$578 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:22053$578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:22055$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 connect \Y $and$libresoc.v:22055$580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:22057$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_alu0_n_ready_i connect \Y $and$libresoc.v:22057$582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:22058$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_alu0_n_valid_o connect \Y $and$libresoc.v:22058$583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:22059$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o connect \Y $and$libresoc.v:22059$584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:22064$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:22064$589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:22065$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:22065$590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:22068$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:22068$593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:22069$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:22069$594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:22070$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:22070$595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:22071$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:22071$596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:22072$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:22072$597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:22054$579 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 connect \Y $eq$libresoc.v:22054$579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:22056$581 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:22056$581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:22019$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__zero_a connect \Y $not$libresoc.v:22019$544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:22020$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__imm_data__ok connect \Y $not$libresoc.v:22020$545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:22022$547 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:22022$547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:22037$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:22037$562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:22039$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:22039$564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:22042$567 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:22042$567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:22045$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:22045$570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:22051$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_ready_i connect \Y $not$libresoc.v:22051$576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:22066$591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:22066$591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:22049$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 connect \Y $or$libresoc.v:22049$574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:22060$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:22060$585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:22061$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:22061$586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:22062$587 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:22062$587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:22063$588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:22063$588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:22067$592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:22067$592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:22076$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:22076$601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:22015$540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $reduce_and$libresoc.v:22015$540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:22044$569 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 connect \Y $reduce_or$libresoc.v:22044$569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:22047$572 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:22047$572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:22048$573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:22048$573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:22073$598 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__zero_a connect \Y $ternary$libresoc.v:22073$598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:22074$599 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_alu0_alu_op__zero_a connect \Y $ternary$libresoc.v:22074$599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:22075$600 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__imm_data__ok connect \Y $ternary$libresoc.v:22075$600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:22077$602 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_alu0_alu_op__imm_data__data connect \S \alu_alu0_alu_op__imm_data__ok connect \Y $ternary$libresoc.v:22077$602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:22078$603 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel connect \Y $ternary$libresoc.v:22078$603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:22079$604 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$88 connect \S \src_sel$85 connect \Y $ternary$libresoc.v:22079$604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:22080$605 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:22080$605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:22081$606 parameter \WIDTH 2 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] connect \Y $ternary$libresoc.v:22081$606_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:22176.12-22215.4" cell \alu_alu0 \alu_alu0 connect \alu_op__data_len \alu_alu0_alu_op__data_len connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok connect \alu_op__input_carry \alu_alu0_alu_op__input_carry connect \alu_op__insn \alu_alu0_alu_op__insn connect \alu_op__insn_type \alu_alu0_alu_op__insn_type connect \alu_op__invert_in \alu_alu0_alu_op__invert_in connect \alu_op__invert_out \alu_alu0_alu_op__invert_out connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit connect \alu_op__is_signed \alu_alu0_alu_op__is_signed connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok connect \alu_op__output_carry \alu_alu0_alu_op__output_carry connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 connect \alu_op__zero_a \alu_alu0_alu_op__zero_a connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \alu_alu0_cr_a connect \cr_a_ok \cr_a_ok connect \n_ready_i \alu_alu0_n_ready_i connect \n_valid_o \alu_alu0_n_valid_o connect \o \alu_alu0_o connect \o_ok \o_ok connect \p_ready_o \alu_alu0_p_ready_o connect \p_valid_i \alu_alu0_p_valid_i connect \ra \alu_alu0_ra connect \rb \alu_alu0_rb connect \xer_ca \alu_alu0_xer_ca connect \xer_ca$2 \alu_alu0_xer_ca$2 connect \xer_ca_ok \xer_ca_ok connect \xer_ov \alu_alu0_xer_ov connect \xer_ov_ok \xer_ov_ok connect \xer_so \alu_alu0_xer_so connect \xer_so$1 \alu_alu0_xer_so$1 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:22216.9-22222.4" cell \alu_l \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:22223.10-22229.4" cell \alui_l \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:22230.9-22236.4" cell \opc_l \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:22237.9-22243.4" cell \req_l \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:22244.9-22250.4" cell \rok_l \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:22251.9-22256.4" cell \rst_l \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:22257.9-22263.4" cell \src_l \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:21333.7-21333.20" process $proc$libresoc.v:21333$794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:21471.7-21471.24" process $proc$libresoc.v:21471$795 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:21479.13-21479.45" process $proc$libresoc.v:21479$796 assign { } { } assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] end attribute \src "libresoc.v:21498.14-21498.49" process $proc$libresoc.v:21498$797 assign { } { } assign $1\alu_alu0_alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[13:0] end attribute \src "libresoc.v:21502.14-21502.68" process $proc$libresoc.v:21502$798 assign { } { } assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] end attribute \src "libresoc.v:21506.7-21506.43" process $proc$libresoc.v:21506$799 assign { } { } assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] end attribute \src "libresoc.v:21514.13-21514.48" process $proc$libresoc.v:21514$800 assign { } { } assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] end attribute \src "libresoc.v:21518.14-21518.43" process $proc$libresoc.v:21518$801 assign { } { } assign $1\alu_alu0_alu_op__insn[31:0] 0 sync always sync init update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] end attribute \src "libresoc.v:21597.13-21597.47" process $proc$libresoc.v:21597$802 assign { } { } assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] end attribute \src "libresoc.v:21601.7-21601.40" process $proc$libresoc.v:21601$803 assign { } { } assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] end attribute \src "libresoc.v:21605.7-21605.41" process $proc$libresoc.v:21605$804 assign { } { } assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] end attribute \src "libresoc.v:21609.7-21609.39" process $proc$libresoc.v:21609$805 assign { } { } assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] end attribute \src "libresoc.v:21613.7-21613.40" process $proc$libresoc.v:21613$806 assign { } { } assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] end attribute \src "libresoc.v:21617.7-21617.37" process $proc$libresoc.v:21617$807 assign { } { } assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] end attribute \src "libresoc.v:21621.7-21621.37" process $proc$libresoc.v:21621$808 assign { } { } assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] end attribute \src "libresoc.v:21625.7-21625.43" process $proc$libresoc.v:21625$809 assign { } { } assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] end attribute \src "libresoc.v:21629.7-21629.37" process $proc$libresoc.v:21629$810 assign { } { } assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] end attribute \src "libresoc.v:21633.7-21633.37" process $proc$libresoc.v:21633$811 assign { } { } assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] end attribute \src "libresoc.v:21637.7-21637.40" process $proc$libresoc.v:21637$812 assign { } { } assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] end attribute \src "libresoc.v:21641.7-21641.37" process $proc$libresoc.v:21641$813 assign { } { } assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] end attribute \src "libresoc.v:21673.7-21673.26" process $proc$libresoc.v:21673$814 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:21681.7-21681.25" process $proc$libresoc.v:21681$815 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:21693.7-21693.27" process $proc$libresoc.v:21693$816 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:21727.14-21727.47" process $proc$libresoc.v:21727$817 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:21731.7-21731.27" process $proc$libresoc.v:21731$818 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:21735.13-21735.33" process $proc$libresoc.v:21735$819 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end attribute \src "libresoc.v:21739.7-21739.30" process $proc$libresoc.v:21739$820 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:21743.13-21743.35" process $proc$libresoc.v:21743$821 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end attribute \src "libresoc.v:21747.7-21747.32" process $proc$libresoc.v:21747$822 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end attribute \src "libresoc.v:21751.13-21751.35" process $proc$libresoc.v:21751$823 assign { } { } assign $1\data_r3__xer_ov[1:0] 2'00 sync always sync init update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] end attribute \src "libresoc.v:21755.7-21755.32" process $proc$libresoc.v:21755$824 assign { } { } assign $1\data_r3__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] end attribute \src "libresoc.v:21759.7-21759.29" process $proc$libresoc.v:21759$825 assign { } { } assign $1\data_r4__xer_so[0:0] 1'0 sync always sync init update \data_r4__xer_so $1\data_r4__xer_so[0:0] end attribute \src "libresoc.v:21763.7-21763.32" process $proc$libresoc.v:21763$826 assign { } { } assign $1\data_r4__xer_so_ok[0:0] 1'0 sync always sync init update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] end attribute \src "libresoc.v:21786.7-21786.25" process $proc$libresoc.v:21786$827 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:21790.7-21790.25" process $proc$libresoc.v:21790$828 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:21924.13-21924.31" process $proc$libresoc.v:21924$829 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end attribute \src "libresoc.v:21932.13-21932.32" process $proc$libresoc.v:21932$830 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end attribute \src "libresoc.v:21936.13-21936.32" process $proc$libresoc.v:21936$831 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end attribute \src "libresoc.v:21948.7-21948.26" process $proc$libresoc.v:21948$832 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:21952.7-21952.26" process $proc$libresoc.v:21952$833 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:21956.7-21956.25" process $proc$libresoc.v:21956$834 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:21960.7-21960.25" process $proc$libresoc.v:21960$835 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:21976.13-21976.31" process $proc$libresoc.v:21976$836 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end attribute \src "libresoc.v:21980.13-21980.31" process $proc$libresoc.v:21980$837 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end attribute \src "libresoc.v:21988.14-21988.43" process $proc$libresoc.v:21988$838 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:21992.14-21992.43" process $proc$libresoc.v:21992$839 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:21996.7-21996.20" process $proc$libresoc.v:21996$840 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end attribute \src "libresoc.v:22000.13-22000.26" process $proc$libresoc.v:22000$841 assign { } { } assign $1\src_r3[1:0] 2'00 sync always sync init update \src_r3 $1\src_r3[1:0] end attribute \src "libresoc.v:22082.3-22083.39" process $proc$libresoc.v:22082$607 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:22084.3-22085.43" process $proc$libresoc.v:22084$608 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:22086.3-22087.29" process $proc$libresoc.v:22086$609 assign { } { } assign $0\src_r3[1:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[1:0] end attribute \src "libresoc.v:22088.3-22089.29" process $proc$libresoc.v:22088$610 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end attribute \src "libresoc.v:22090.3-22091.29" process $proc$libresoc.v:22090$611 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:22092.3-22093.29" process $proc$libresoc.v:22092$612 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:22094.3-22095.47" process $proc$libresoc.v:22094$613 assign { } { } assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next sync posedge \coresync_clk update \data_r4__xer_so $0\data_r4__xer_so[0:0] end attribute \src "libresoc.v:22096.3-22097.53" process $proc$libresoc.v:22096$614 assign { } { } assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next sync posedge \coresync_clk update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] end attribute \src "libresoc.v:22098.3-22099.47" process $proc$libresoc.v:22098$615 assign { } { } assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next sync posedge \coresync_clk update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] end attribute \src "libresoc.v:22100.3-22101.53" process $proc$libresoc.v:22100$616 assign { } { } assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next sync posedge \coresync_clk update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] end attribute \src "libresoc.v:22102.3-22103.47" process $proc$libresoc.v:22102$617 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end attribute \src "libresoc.v:22104.3-22105.53" process $proc$libresoc.v:22104$618 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end attribute \src "libresoc.v:22106.3-22107.43" process $proc$libresoc.v:22106$619 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end attribute \src "libresoc.v:22108.3-22109.49" process $proc$libresoc.v:22108$620 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:22110.3-22111.37" process $proc$libresoc.v:22110$621 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:22112.3-22113.43" process $proc$libresoc.v:22112$622 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:22114.3-22115.69" process $proc$libresoc.v:22114$623 assign { } { } assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] end attribute \src "libresoc.v:22116.3-22117.65" process $proc$libresoc.v:22116$624 assign { } { } assign $0\alu_alu0_alu_op__fn_unit[13:0] \alu_alu0_alu_op__fn_unit$next sync posedge \coresync_clk update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[13:0] end attribute \src "libresoc.v:22118.3-22119.79" process $proc$libresoc.v:22118$625 assign { } { } assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] end attribute \src "libresoc.v:22120.3-22121.75" process $proc$libresoc.v:22120$626 assign { } { } assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] end attribute \src "libresoc.v:22122.3-22123.63" process $proc$libresoc.v:22122$627 assign { } { } assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] end attribute \src "libresoc.v:22124.3-22125.63" process $proc$libresoc.v:22124$628 assign { } { } assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] end attribute \src "libresoc.v:22126.3-22127.63" process $proc$libresoc.v:22126$629 assign { } { } assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] end attribute \src "libresoc.v:22128.3-22129.63" process $proc$libresoc.v:22128$630 assign { } { } assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] end attribute \src "libresoc.v:22130.3-22131.69" process $proc$libresoc.v:22130$631 assign { } { } assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] end attribute \src "libresoc.v:22132.3-22133.63" process $proc$libresoc.v:22132$632 assign { } { } assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next sync posedge \coresync_clk update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] end attribute \src "libresoc.v:22134.3-22135.71" process $proc$libresoc.v:22134$633 assign { } { } assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] end attribute \src "libresoc.v:22136.3-22137.69" process $proc$libresoc.v:22136$634 assign { } { } assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next sync posedge \coresync_clk update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] end attribute \src "libresoc.v:22138.3-22139.73" process $proc$libresoc.v:22138$635 assign { } { } assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] end attribute \src "libresoc.v:22140.3-22141.75" process $proc$libresoc.v:22140$636 assign { } { } assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] end attribute \src "libresoc.v:22142.3-22143.67" process $proc$libresoc.v:22142$637 assign { } { } assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] end attribute \src "libresoc.v:22144.3-22145.69" process $proc$libresoc.v:22144$638 assign { } { } assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] end attribute \src "libresoc.v:22146.3-22147.67" process $proc$libresoc.v:22146$639 assign { } { } assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next sync posedge \coresync_clk update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] end attribute \src "libresoc.v:22148.3-22149.59" process $proc$libresoc.v:22148$640 assign { } { } assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] end attribute \src "libresoc.v:22150.3-22151.39" process $proc$libresoc.v:22150$641 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end attribute \src "libresoc.v:22152.3-22153.39" process $proc$libresoc.v:22152$642 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end attribute \src "libresoc.v:22154.3-22155.39" process $proc$libresoc.v:22154$643 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end attribute \src "libresoc.v:22156.3-22157.39" process $proc$libresoc.v:22156$644 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end attribute \src "libresoc.v:22158.3-22159.39" process $proc$libresoc.v:22158$645 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:22160.3-22161.39" process $proc$libresoc.v:22160$646 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:22162.3-22163.39" process $proc$libresoc.v:22162$647 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:22164.3-22165.39" process $proc$libresoc.v:22164$648 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:22166.3-22167.41" process $proc$libresoc.v:22166$649 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:22168.3-22169.41" process $proc$libresoc.v:22168$650 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:22170.3-22171.37" process $proc$libresoc.v:22170$651 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end attribute \src "libresoc.v:22172.3-22173.40" process $proc$libresoc.v:22172$652 assign { } { } assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:22174.3-22175.25" process $proc$libresoc.v:22174$653 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:22264.3-22273.6" process $proc$libresoc.v:22264$654 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:22265.5-22265.29" switch \initial attribute \src "libresoc.v:22265.9-22265.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$47 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:22274.3-22282.6" process $proc$libresoc.v:22274$655 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 attribute \src "libresoc.v:22275.5-22275.29" switch \initial attribute \src "libresoc.v:22275.9-22275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$657 1'0 case assign $1\rok_l_s_rdok$next[0:0]$657 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 end attribute \src "libresoc.v:22283.3-22291.6" process $proc$libresoc.v:22283$658 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 attribute \src "libresoc.v:22284.5-22284.29" switch \initial attribute \src "libresoc.v:22284.9-22284.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$660 1'1 case assign $1\rok_l_r_rdok$next[0:0]$660 \$65 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 end attribute \src "libresoc.v:22292.3-22300.6" process $proc$libresoc.v:22292$661 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 attribute \src "libresoc.v:22293.5-22293.29" switch \initial attribute \src "libresoc.v:22293.9-22293.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$663 1'0 case assign $1\rst_l_s_rst$next[0:0]$663 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 end attribute \src "libresoc.v:22301.3-22309.6" process $proc$libresoc.v:22301$664 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 attribute \src "libresoc.v:22302.5-22302.29" switch \initial attribute \src "libresoc.v:22302.9-22302.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$666 1'1 case assign $1\rst_l_r_rst$next[0:0]$666 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 end attribute \src "libresoc.v:22310.3-22318.6" process $proc$libresoc.v:22310$667 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 attribute \src "libresoc.v:22311.5-22311.29" switch \initial attribute \src "libresoc.v:22311.9-22311.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$669 1'0 case assign $1\opc_l_s_opc$next[0:0]$669 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 end attribute \src "libresoc.v:22319.3-22327.6" process $proc$libresoc.v:22319$670 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 attribute \src "libresoc.v:22320.5-22320.29" switch \initial attribute \src "libresoc.v:22320.9-22320.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$672 1'1 case assign $1\opc_l_r_opc$next[0:0]$672 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 end attribute \src "libresoc.v:22328.3-22336.6" process $proc$libresoc.v:22328$673 assign { } { } assign { } { } assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 attribute \src "libresoc.v:22329.5-22329.29" switch \initial attribute \src "libresoc.v:22329.9-22329.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[3:0]$675 4'0000 case assign $1\src_l_s_src$next[3:0]$675 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 end attribute \src "libresoc.v:22337.3-22345.6" process $proc$libresoc.v:22337$676 assign { } { } assign { } { } assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 attribute \src "libresoc.v:22338.5-22338.29" switch \initial attribute \src "libresoc.v:22338.9-22338.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[3:0]$678 4'1111 case assign $1\src_l_r_src$next[3:0]$678 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 end attribute \src "libresoc.v:22346.3-22354.6" process $proc$libresoc.v:22346$679 assign { } { } assign { } { } assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 attribute \src "libresoc.v:22347.5-22347.29" switch \initial attribute \src "libresoc.v:22347.9-22347.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[4:0]$681 5'00000 case assign $1\req_l_s_req$next[4:0]$681 \$67 end sync always update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 end attribute \src "libresoc.v:22355.3-22363.6" process $proc$libresoc.v:22355$682 assign { } { } assign { } { } assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 attribute \src "libresoc.v:22356.5-22356.29" switch \initial attribute \src "libresoc.v:22356.9-22356.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[4:0]$684 5'11111 case assign $1\req_l_r_req$next[4:0]$684 \$69 end sync always update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 end attribute \src "libresoc.v:22364.3-22402.6" process $proc$libresoc.v:22364$685 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 assign $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 assign { } { } assign { } { } assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 assign $0\alu_alu0_alu_op__insn$next[31:0]$691 $1\alu_alu0_alu_op__insn$next[31:0]$709 assign $0\alu_alu0_alu_op__insn_type$next[6:0]$692 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 assign $0\alu_alu0_alu_op__invert_in$next[0:0]$693 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 assign $0\alu_alu0_alu_op__invert_out$next[0:0]$694 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 assign $0\alu_alu0_alu_op__is_signed$next[0:0]$696 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 assign { } { } assign { } { } assign $0\alu_alu0_alu_op__output_carry$next[0:0]$699 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 assign { } { } assign { } { } assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 assign $0\alu_alu0_alu_op__zero_a$next[0:0]$703 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 attribute \src "libresoc.v:22365.5-22365.29" switch \initial attribute \src "libresoc.v:22365.9-22365.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } case assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len assign $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 \alu_alu0_alu_op__fn_unit assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry assign $1\alu_alu0_alu_op__insn$next[31:0]$709 \alu_alu0_alu_op__insn assign $1\alu_alu0_alu_op__insn_type$next[6:0]$710 \alu_alu0_alu_op__insn_type assign $1\alu_alu0_alu_op__invert_in$next[0:0]$711 \alu_alu0_alu_op__invert_in assign $1\alu_alu0_alu_op__invert_out$next[0:0]$712 \alu_alu0_alu_op__invert_out assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 \alu_alu0_alu_op__is_32bit assign $1\alu_alu0_alu_op__is_signed$next[0:0]$714 \alu_alu0_alu_op__is_signed assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 \alu_alu0_alu_op__oe__oe assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 \alu_alu0_alu_op__oe__ok assign $1\alu_alu0_alu_op__output_carry$next[0:0]$717 \alu_alu0_alu_op__output_carry assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 \alu_alu0_alu_op__rc__ok assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 \alu_alu0_alu_op__rc__rc assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 \alu_alu0_alu_op__write_cr0 assign $1\alu_alu0_alu_op__zero_a$next[0:0]$721 \alu_alu0_alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 1'0 assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 1'0 assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 1'0 assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 1'0 assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 1'0 case assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 end sync always update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$691 update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$692 update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$693 update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$694 update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$696 update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$699 update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 end attribute \src "libresoc.v:22403.3-22424.6" process $proc$libresoc.v:22403$728 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 assign { } { } assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 attribute \src "libresoc.v:22404.5-22404.29" switch \initial attribute \src "libresoc.v:22404.9-22404.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$732 $1\data_r0__o$next[63:0]$731 } { \o_ok \alu_alu0_o } case assign $1\data_r0__o$next[63:0]$731 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$732 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$734 $2\data_r0__o$next[63:0]$733 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$733 $1\data_r0__o$next[63:0]$731 assign $2\data_r0__o_ok$next[0:0]$734 $1\data_r0__o_ok$next[0:0]$732 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$735 1'0 case assign $3\data_r0__o_ok$next[0:0]$735 $2\data_r0__o_ok$next[0:0]$734 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$729 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 end attribute \src "libresoc.v:22425.3-22446.6" process $proc$libresoc.v:22425$736 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 attribute \src "libresoc.v:22426.5-22426.29" switch \initial attribute \src "libresoc.v:22426.9-22426.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__cr_a_ok$next[0:0]$740 $1\data_r1__cr_a$next[3:0]$739 } { \cr_a_ok \alu_alu0_cr_a } case assign $1\data_r1__cr_a$next[3:0]$739 \data_r1__cr_a assign $1\data_r1__cr_a_ok$next[0:0]$740 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__cr_a_ok$next[0:0]$742 $2\data_r1__cr_a$next[3:0]$741 } 5'00000 case assign $2\data_r1__cr_a$next[3:0]$741 $1\data_r1__cr_a$next[3:0]$739 assign $2\data_r1__cr_a_ok$next[0:0]$742 $1\data_r1__cr_a_ok$next[0:0]$740 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__cr_a_ok$next[0:0]$743 1'0 case assign $3\data_r1__cr_a_ok$next[0:0]$743 $2\data_r1__cr_a_ok$next[0:0]$742 end sync always update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 end attribute \src "libresoc.v:22447.3-22468.6" process $proc$libresoc.v:22447$744 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 assign { } { } assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 attribute \src "libresoc.v:22448.5-22448.29" switch \initial attribute \src "libresoc.v:22448.9-22448.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__xer_ca_ok$next[0:0]$748 $1\data_r2__xer_ca$next[1:0]$747 } { \xer_ca_ok \alu_alu0_xer_ca } case assign $1\data_r2__xer_ca$next[1:0]$747 \data_r2__xer_ca assign $1\data_r2__xer_ca_ok$next[0:0]$748 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__xer_ca_ok$next[0:0]$750 $2\data_r2__xer_ca$next[1:0]$749 } 3'000 case assign $2\data_r2__xer_ca$next[1:0]$749 $1\data_r2__xer_ca$next[1:0]$747 assign $2\data_r2__xer_ca_ok$next[0:0]$750 $1\data_r2__xer_ca_ok$next[0:0]$748 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__xer_ca_ok$next[0:0]$751 1'0 case assign $3\data_r2__xer_ca_ok$next[0:0]$751 $2\data_r2__xer_ca_ok$next[0:0]$750 end sync always update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 end attribute \src "libresoc.v:22469.3-22490.6" process $proc$libresoc.v:22469$752 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 assign { } { } assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 attribute \src "libresoc.v:22470.5-22470.29" switch \initial attribute \src "libresoc.v:22470.9-22470.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r3__xer_ov_ok$next[0:0]$756 $1\data_r3__xer_ov$next[1:0]$755 } { \xer_ov_ok \alu_alu0_xer_ov } case assign $1\data_r3__xer_ov$next[1:0]$755 \data_r3__xer_ov assign $1\data_r3__xer_ov_ok$next[0:0]$756 \data_r3__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r3__xer_ov_ok$next[0:0]$758 $2\data_r3__xer_ov$next[1:0]$757 } 3'000 case assign $2\data_r3__xer_ov$next[1:0]$757 $1\data_r3__xer_ov$next[1:0]$755 assign $2\data_r3__xer_ov_ok$next[0:0]$758 $1\data_r3__xer_ov_ok$next[0:0]$756 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r3__xer_ov_ok$next[0:0]$759 1'0 case assign $3\data_r3__xer_ov_ok$next[0:0]$759 $2\data_r3__xer_ov_ok$next[0:0]$758 end sync always update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 end attribute \src "libresoc.v:22491.3-22512.6" process $proc$libresoc.v:22491$760 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 assign { } { } assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 attribute \src "libresoc.v:22492.5-22492.29" switch \initial attribute \src "libresoc.v:22492.9-22492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r4__xer_so_ok$next[0:0]$764 $1\data_r4__xer_so$next[0:0]$763 } { \xer_so_ok \alu_alu0_xer_so } case assign $1\data_r4__xer_so$next[0:0]$763 \data_r4__xer_so assign $1\data_r4__xer_so_ok$next[0:0]$764 \data_r4__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r4__xer_so_ok$next[0:0]$766 $2\data_r4__xer_so$next[0:0]$765 } 2'00 case assign $2\data_r4__xer_so$next[0:0]$765 $1\data_r4__xer_so$next[0:0]$763 assign $2\data_r4__xer_so_ok$next[0:0]$766 $1\data_r4__xer_so_ok$next[0:0]$764 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r4__xer_so_ok$next[0:0]$767 1'0 case assign $3\data_r4__xer_so_ok$next[0:0]$767 $2\data_r4__xer_so_ok$next[0:0]$766 end sync always update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 end attribute \src "libresoc.v:22513.3-22522.6" process $proc$libresoc.v:22513$768 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 attribute \src "libresoc.v:22514.5-22514.29" switch \initial attribute \src "libresoc.v:22514.9-22514.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$770 \src_or_imm case assign $1\src_r0$next[63:0]$770 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$769 end attribute \src "libresoc.v:22523.3-22532.6" process $proc$libresoc.v:22523$771 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 attribute \src "libresoc.v:22524.5-22524.29" switch \initial attribute \src "libresoc.v:22524.9-22524.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$773 \src_or_imm$88 case assign $1\src_r1$next[63:0]$773 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$772 end attribute \src "libresoc.v:22533.3-22542.6" process $proc$libresoc.v:22533$774 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 attribute \src "libresoc.v:22534.5-22534.29" switch \initial attribute \src "libresoc.v:22534.9-22534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[0:0]$776 \src3_i case assign $1\src_r2$next[0:0]$776 \src_r2 end sync always update \src_r2$next $0\src_r2$next[0:0]$775 end attribute \src "libresoc.v:22543.3-22552.6" process $proc$libresoc.v:22543$777 assign { } { } assign { } { } assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 attribute \src "libresoc.v:22544.5-22544.29" switch \initial attribute \src "libresoc.v:22544.9-22544.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r3$next[1:0]$779 \src4_i case assign $1\src_r3$next[1:0]$779 \src_r3 end sync always update \src_r3$next $0\src_r3$next[1:0]$778 end attribute \src "libresoc.v:22553.3-22561.6" process $proc$libresoc.v:22553$780 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 attribute \src "libresoc.v:22554.5-22554.29" switch \initial attribute \src "libresoc.v:22554.9-22554.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$782 1'1 case assign $1\alui_l_r_alui$next[0:0]$782 \$99 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 end attribute \src "libresoc.v:22562.3-22570.6" process $proc$libresoc.v:22562$783 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 attribute \src "libresoc.v:22563.5-22563.29" switch \initial attribute \src "libresoc.v:22563.9-22563.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$785 1'1 case assign $1\alu_l_r_alu$next[0:0]$785 \$101 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 end attribute \src "libresoc.v:22571.3-22580.6" process $proc$libresoc.v:22571$786 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:22572.5-22572.29" switch \initial attribute \src "libresoc.v:22572.9-22572.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:22581.3-22590.6" process $proc$libresoc.v:22581$787 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] attribute \src "libresoc.v:22582.5-22582.29" switch \initial attribute \src "libresoc.v:22582.9-22582.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[3:0] \data_r1__cr_a case assign $1\dest2_o[3:0] 4'0000 end sync always update \dest2_o $0\dest2_o[3:0] end attribute \src "libresoc.v:22591.3-22600.6" process $proc$libresoc.v:22591$788 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] attribute \src "libresoc.v:22592.5-22592.29" switch \initial attribute \src "libresoc.v:22592.9-22592.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[1:0] \data_r2__xer_ca case assign $1\dest3_o[1:0] 2'00 end sync always update \dest3_o $0\dest3_o[1:0] end attribute \src "libresoc.v:22601.3-22610.6" process $proc$libresoc.v:22601$789 assign { } { } assign { } { } assign $0\dest4_o[1:0] $1\dest4_o[1:0] attribute \src "libresoc.v:22602.5-22602.29" switch \initial attribute \src "libresoc.v:22602.9-22602.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest4_o[1:0] \data_r3__xer_ov case assign $1\dest4_o[1:0] 2'00 end sync always update \dest4_o $0\dest4_o[1:0] end attribute \src "libresoc.v:22611.3-22620.6" process $proc$libresoc.v:22611$790 assign { } { } assign { } { } assign $0\dest5_o[0:0] $1\dest5_o[0:0] attribute \src "libresoc.v:22612.5-22612.29" switch \initial attribute \src "libresoc.v:22612.9-22612.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest5_o[0:0] \data_r4__xer_so case assign $1\dest5_o[0:0] 1'0 end sync always update \dest5_o $0\dest5_o[0:0] end attribute \src "libresoc.v:22621.3-22629.6" process $proc$libresoc.v:22621$791 assign { } { } assign { } { } assign $0\prev_wr_go$next[4:0]$792 $1\prev_wr_go$next[4:0]$793 attribute \src "libresoc.v:22622.5-22622.29" switch \initial attribute \src "libresoc.v:22622.9-22622.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[4:0]$793 5'00000 case assign $1\prev_wr_go$next[4:0]$793 \$21 end sync always update \prev_wr_go$next $0\prev_wr_go$next[4:0]$792 end connect \$5 $reduce_and$libresoc.v:22015$540_Y connect \$99 $and$libresoc.v:22016$541_Y connect \$101 $and$libresoc.v:22017$542_Y connect \$103 $and$libresoc.v:22018$543_Y connect \$105 $not$libresoc.v:22019$544_Y connect \$107 $not$libresoc.v:22020$545_Y connect \$109 $and$libresoc.v:22021$546_Y connect \$111 $not$libresoc.v:22022$547_Y connect \$113 $and$libresoc.v:22023$548_Y connect \$115 $and$libresoc.v:22024$549_Y connect \$117 $and$libresoc.v:22025$550_Y connect \$11 $and$libresoc.v:22026$551_Y connect \$119 $and$libresoc.v:22027$552_Y connect \$121 $and$libresoc.v:22028$553_Y connect \$123 $and$libresoc.v:22029$554_Y connect \$125 $and$libresoc.v:22030$555_Y connect \$127 $and$libresoc.v:22031$556_Y connect \$129 $and$libresoc.v:22032$557_Y connect \$131 $and$libresoc.v:22033$558_Y connect \$133 $and$libresoc.v:22034$559_Y connect \$135 $and$libresoc.v:22035$560_Y connect \$137 $and$libresoc.v:22036$561_Y connect \$13 $not$libresoc.v:22037$562_Y connect \$15 $and$libresoc.v:22038$563_Y connect \$17 $not$libresoc.v:22039$564_Y connect \$19 $and$libresoc.v:22040$565_Y connect \$21 $and$libresoc.v:22041$566_Y connect \$25 $not$libresoc.v:22042$567_Y connect \$27 $and$libresoc.v:22043$568_Y connect \$24 $reduce_or$libresoc.v:22044$569_Y connect \$23 $not$libresoc.v:22045$570_Y connect \$31 $and$libresoc.v:22046$571_Y connect \$33 $reduce_or$libresoc.v:22047$572_Y connect \$35 $reduce_or$libresoc.v:22048$573_Y connect \$37 $or$libresoc.v:22049$574_Y connect \$3 $and$libresoc.v:22050$575_Y connect \$39 $not$libresoc.v:22051$576_Y connect \$41 $and$libresoc.v:22052$577_Y connect \$43 $and$libresoc.v:22053$578_Y connect \$45 $eq$libresoc.v:22054$579_Y connect \$47 $and$libresoc.v:22055$580_Y connect \$49 $eq$libresoc.v:22056$581_Y connect \$51 $and$libresoc.v:22057$582_Y connect \$53 $and$libresoc.v:22058$583_Y connect \$55 $and$libresoc.v:22059$584_Y connect \$57 $or$libresoc.v:22060$585_Y connect \$59 $or$libresoc.v:22061$586_Y connect \$61 $or$libresoc.v:22062$587_Y connect \$63 $or$libresoc.v:22063$588_Y connect \$65 $and$libresoc.v:22064$589_Y connect \$67 $and$libresoc.v:22065$590_Y connect \$6 $not$libresoc.v:22066$591_Y connect \$69 $or$libresoc.v:22067$592_Y connect \$71 $and$libresoc.v:22068$593_Y connect \$73 $and$libresoc.v:22069$594_Y connect \$75 $and$libresoc.v:22070$595_Y connect \$77 $and$libresoc.v:22071$596_Y connect \$79 $and$libresoc.v:22072$597_Y connect \$81 $ternary$libresoc.v:22073$598_Y connect \$83 $ternary$libresoc.v:22074$599_Y connect \$86 $ternary$libresoc.v:22075$600_Y connect \$8 $or$libresoc.v:22076$601_Y connect \$89 $ternary$libresoc.v:22077$602_Y connect \$91 $ternary$libresoc.v:22078$603_Y connect \$93 $ternary$libresoc.v:22079$604_Y connect \$95 $ternary$libresoc.v:22080$605_Y connect \$97 $ternary$libresoc.v:22081$606_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$127 connect \cu_rd__rel_o \$113 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_alu0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_alu0_p_valid_i \alui_l_q_alui connect \alu_alu0_xer_ca$2 \$97 connect \alu_alu0_xer_so$1 \$95 connect \alu_alu0_rb \$93 connect \alu_alu0_ra \$91 connect \src_or_imm$88 \$89 connect \src_sel$85 \$86 connect \src_or_imm \$83 connect \src_sel \$81 connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } connect \reset_r \$63 connect \reset_w \$61 connect \rst_r \$59 connect \reset \$57 connect \wr_any \$37 connect \cu_done_o \$31 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$19 connect \alu_done_dly$next \alu_done connect \alu_done \alu_alu0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$15 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end attribute \src "libresoc.v:22667.1-23745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0" attribute \generator "nMigen" module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 25 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$70 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 10 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 11 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_op__imm_data__data$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__imm_data__ok$57 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 21 \alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_op__input_carry$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 26 \alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_op__insn$71 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 9 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_in$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_out$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 23 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 24 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__oe$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 22 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__output_carry$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__rc$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__write_cr0$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 38 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 28 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 8 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 7 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 27 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 37 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 36 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe1_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe1_alu_op__data_len$20 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe1_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe1_alu_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_alu_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__imm_data__ok$7 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe1_alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe1_alu_op__input_carry$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_alu_op__insn$21 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_alu_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__invert_in$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__invert_out$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__is_32bit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__is_signed$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__oe__oe$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__oe__ok$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__output_carry$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__rc__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__rc__rc$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__write_cr0$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__zero_a$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe1_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe1_xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe1_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe1_xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe2_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe2_alu_op__data_len$41 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe2_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe2_alu_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_alu_op__imm_data__data$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__imm_data__ok$28 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe2_alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe2_alu_op__input_carry$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe2_alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe2_alu_op__insn$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_alu_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__invert_in$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__invert_out$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__is_32bit$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__is_signed$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__oe__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__output_carry$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__rc__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__write_cr0$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__zero_a$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ov$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ov_ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so_ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 32 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 33 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 29 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 35 \xer_ca$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 30 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 34 \xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \xer_so_ok attribute \module_not_derived 1 attribute \src "libresoc.v:23584.5-23587.4" cell \n \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:23588.5-23591.4" cell \p \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:23592.9-23651.4" cell \pipe1 \pipe1 connect \alu_op__data_len \pipe1_alu_op__data_len connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 connect \alu_op__fn_unit \pipe1_alu_op__fn_unit connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 connect \alu_op__input_carry \pipe1_alu_op__input_carry connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 connect \alu_op__insn \pipe1_alu_op__insn connect \alu_op__insn$19 \pipe1_alu_op__insn$21 connect \alu_op__insn_type \pipe1_alu_op__insn_type connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 connect \alu_op__invert_in \pipe1_alu_op__invert_in connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 connect \alu_op__invert_out \pipe1_alu_op__invert_out connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 connect \alu_op__is_32bit \pipe1_alu_op__is_32bit connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 connect \alu_op__is_signed \pipe1_alu_op__is_signed connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 connect \alu_op__oe__oe \pipe1_alu_op__oe__oe connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 connect \alu_op__oe__ok \pipe1_alu_op__oe__ok connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 connect \alu_op__output_carry \pipe1_alu_op__output_carry connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 connect \alu_op__rc__ok \pipe1_alu_op__rc__ok connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 connect \alu_op__rc__rc \pipe1_alu_op__rc__rc connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 connect \alu_op__zero_a \pipe1_alu_op__zero_a connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe1_cr_a connect \cr_a_ok \pipe1_cr_a_ok connect \muxid \pipe1_muxid connect \muxid$1 \pipe1_muxid$3 connect \n_ready_i \pipe1_n_ready_i connect \n_valid_o \pipe1_n_valid_o connect \o \pipe1_o connect \o_ok \pipe1_o_ok connect \p_ready_o \pipe1_p_ready_o connect \p_valid_i \pipe1_p_valid_i connect \ra \pipe1_ra connect \rb \pipe1_rb connect \xer_ca \pipe1_xer_ca connect \xer_ca$21 \pipe1_xer_ca$23 connect \xer_ca_ok \pipe1_xer_ca_ok connect \xer_ov \pipe1_xer_ov connect \xer_ov_ok \pipe1_xer_ov_ok connect \xer_so \pipe1_xer_so connect \xer_so$20 \pipe1_xer_so$22 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:23652.9-23717.4" cell \pipe2 \pipe2 connect \alu_op__data_len \pipe2_alu_op__data_len connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 connect \alu_op__fn_unit \pipe2_alu_op__fn_unit connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 connect \alu_op__input_carry \pipe2_alu_op__input_carry connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 connect \alu_op__insn \pipe2_alu_op__insn connect \alu_op__insn$19 \pipe2_alu_op__insn$42 connect \alu_op__insn_type \pipe2_alu_op__insn_type connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 connect \alu_op__invert_in \pipe2_alu_op__invert_in connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 connect \alu_op__invert_out \pipe2_alu_op__invert_out connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 connect \alu_op__is_32bit \pipe2_alu_op__is_32bit connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 connect \alu_op__is_signed \pipe2_alu_op__is_signed connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 connect \alu_op__oe__oe \pipe2_alu_op__oe__oe connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 connect \alu_op__oe__ok \pipe2_alu_op__oe__ok connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 connect \alu_op__output_carry \pipe2_alu_op__output_carry connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 connect \alu_op__rc__ok \pipe2_alu_op__rc__ok connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 connect \alu_op__rc__rc \pipe2_alu_op__rc__rc connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 connect \alu_op__zero_a \pipe2_alu_op__zero_a connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe2_cr_a connect \cr_a$22 \pipe2_cr_a$45 connect \cr_a_ok \pipe2_cr_a_ok connect \cr_a_ok$23 \pipe2_cr_a_ok$46 connect \muxid \pipe2_muxid connect \muxid$1 \pipe2_muxid$24 connect \n_ready_i \pipe2_n_ready_i connect \n_valid_o \pipe2_n_valid_o connect \o \pipe2_o connect \o$20 \pipe2_o$43 connect \o_ok \pipe2_o_ok connect \o_ok$21 \pipe2_o_ok$44 connect \p_ready_o \pipe2_p_ready_o connect \p_valid_i \pipe2_p_valid_i connect \xer_ca \pipe2_xer_ca connect \xer_ca$24 \pipe2_xer_ca$47 connect \xer_ca_ok \pipe2_xer_ca_ok connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 connect \xer_ov \pipe2_xer_ov connect \xer_ov$26 \pipe2_xer_ov$49 connect \xer_ov_ok \pipe2_xer_ov_ok connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 connect \xer_so \pipe2_xer_so connect \xer_so$28 \pipe2_xer_so$51 connect \xer_so_ok \pipe2_xer_so_ok connect \xer_so_ok$29 \pipe2_xer_so_ok$52 end connect \muxid 2'00 connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } connect \muxid$53 \pipe2_muxid$24 connect \pipe2_n_ready_i \n_ready_i connect \n_valid_o \pipe2_n_valid_o connect \pipe1_xer_ca$23 \xer_ca$2 connect \pipe1_xer_so$22 \xer_so$1 connect \pipe1_rb \rb connect \pipe1_ra \ra connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \pipe1_muxid$3 2'00 connect \p_ready_o \pipe1_p_ready_o connect \pipe1_p_valid_i \p_valid_i connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } connect \pipe2_muxid \pipe1_muxid connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end attribute \src "libresoc.v:23749.1-24296.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" attribute \generator "nMigen" module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__cia$15 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 9 \br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \br_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 11 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__imm_data__data$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__imm_data__ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 10 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \br_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \br_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__is_32bit$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 23 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 15 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \fast1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 16 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \fast2$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 17 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 22 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 21 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__cia$4 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_br_op__fn_unit$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_br_op__imm_data__data$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_br_op__imm_data__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_br_op__insn$7 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_br_op__insn_type$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_br_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_br_op__lk$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_fast1$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_fast2$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \module_not_derived 1 attribute \src "libresoc.v:24238.10-24241.4" cell \n$18 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:24242.10-24245.4" cell \p$17 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:24246.13-24280.4" cell \pipe$19 \pipe connect \br_op__cia \pipe_br_op__cia connect \br_op__cia$2 \pipe_br_op__cia$4 connect \br_op__fn_unit \pipe_br_op__fn_unit connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 connect \br_op__imm_data__data \pipe_br_op__imm_data__data connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 connect \br_op__insn \pipe_br_op__insn connect \br_op__insn$5 \pipe_br_op__insn$7 connect \br_op__insn_type \pipe_br_op__insn_type connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 connect \br_op__is_32bit \pipe_br_op__is_32bit connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 connect \br_op__lk \pipe_br_op__lk connect \br_op__lk$8 \pipe_br_op__lk$10 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe_cr_a connect \fast1 \pipe_fast1 connect \fast1$10 \pipe_fast1$12 connect \fast1_ok \pipe_fast1_ok connect \fast2 \pipe_fast2 connect \fast2$11 \pipe_fast2$13 connect \fast2_ok \pipe_fast2_ok connect \muxid \pipe_muxid connect \muxid$1 \pipe_muxid$3 connect \n_ready_i \pipe_n_ready_i connect \n_valid_o \pipe_n_valid_o connect \nia \pipe_nia connect \nia_ok \pipe_nia_ok connect \p_ready_o \pipe_p_ready_o connect \p_valid_i \pipe_p_valid_i end connect \muxid 2'00 connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } connect \muxid$14 \pipe_muxid$3 connect \pipe_n_ready_i \n_ready_i connect \n_valid_o \pipe_n_valid_o connect \pipe_cr_a \cr_a connect \pipe_fast2 \fast2$2 connect \pipe_fast1 \fast1$1 connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \pipe_muxid 2'00 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end attribute \src "libresoc.v:24300.1-24815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 21 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 12 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 16 \cr_a$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 17 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 18 \cr_c attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 8 \cr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \cr_op__fn_unit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 9 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \cr_op__insn$12 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 7 \cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 output 11 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 15 \full_cr$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 10 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 20 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 19 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe_cr_a$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_c attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_cr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_cr_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_cr_op__insn$6 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_cr_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \pipe_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \pipe_full_cr$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \module_not_derived 1 attribute \src "libresoc.v:24761.9-24764.4" cell \n$6 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:24765.9-24768.4" cell \p$5 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:24769.8-24796.4" cell \pipe \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe_cr_a connect \cr_a$6 \pipe_cr_a$8 connect \cr_a_ok \pipe_cr_a_ok connect \cr_b \pipe_cr_b connect \cr_c \pipe_cr_c connect \cr_op__fn_unit \pipe_cr_op__fn_unit connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 connect \cr_op__insn \pipe_cr_op__insn connect \cr_op__insn$4 \pipe_cr_op__insn$6 connect \cr_op__insn_type \pipe_cr_op__insn_type connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 connect \full_cr \pipe_full_cr connect \full_cr$5 \pipe_full_cr$7 connect \full_cr_ok \pipe_full_cr_ok connect \muxid \pipe_muxid connect \muxid$1 \pipe_muxid$3 connect \n_ready_i \pipe_n_ready_i connect \n_valid_o \pipe_n_valid_o connect \o \pipe_o connect \o_ok \pipe_o_ok connect \p_ready_o \pipe_p_ready_o connect \p_valid_i \pipe_p_valid_i connect \ra \pipe_ra connect \rb \pipe_rb end connect \muxid 2'00 connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } connect { \o_ok \o } { \pipe_o_ok \pipe_o } connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } connect \muxid$9 \pipe_muxid$3 connect \pipe_n_ready_i \n_ready_i connect \n_valid_o \pipe_n_valid_o connect \pipe_cr_c \cr_c connect \pipe_cr_b \cr_b connect \pipe_cr_a \cr_a$2 connect \pipe_full_cr \full_cr$1 connect \pipe_rb \rb connect \pipe_ra \ra connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \pipe_muxid 2'00 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end attribute \src "libresoc.v:24819.1-26284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 35 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 27 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 24 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$88 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 9 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 10 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$75 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 18 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 25 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 22 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 23 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 21 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 7 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 6 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 26 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 34 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 33 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe_end_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_end_div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \pipe_end_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \pipe_end_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \pipe_end_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \pipe_end_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_end_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_end_logical_op__data_len$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_end_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_end_logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_end_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_end_logical_op__imm_data__data$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__imm_data__ok$55 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe_end_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe_end_logical_op__input_carry$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_end_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_end_logical_op__insn$69 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_end_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_end_logical_op__insn_type$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__invert_in$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__invert_out$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__is_32bit$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__is_signed$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__oe__oe$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__oe__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__output_carry$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__rc__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__rc__rc$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__write_cr0$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_end_logical_op__zero_a$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_end_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_end_muxid$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_end_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_end_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_end_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_end_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_end_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \pipe_end_quotient_root attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_end_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_end_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 \pipe_end_remainder attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe_end_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_end_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_xer_so$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_end_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_middle_0_div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_middle_0_div_by_zero$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \pipe_middle_0_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \pipe_middle_0_dive_abs_ov32$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \pipe_middle_0_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \pipe_middle_0_dive_abs_ov64$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \pipe_middle_0_dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \pipe_middle_0_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \pipe_middle_0_dividend_neg$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \pipe_middle_0_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \pipe_middle_0_divisor_neg$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \pipe_middle_0_divisor_radicand attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_middle_0_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_middle_0_logical_op__data_len$41 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_middle_0_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_middle_0_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_middle_0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_middle_0_logical_op__imm_data__data$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__imm_data__ok$28 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe_middle_0_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe_middle_0_logical_op__input_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_middle_0_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_middle_0_logical_op__insn$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_middle_0_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_middle_0_logical_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__invert_in$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__invert_out$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__is_32bit$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__is_signed$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__oe__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__output_carry$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__rc__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__write_cr0$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_middle_0_logical_op__zero_a$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_middle_0_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_middle_0_muxid$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_middle_0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_middle_0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \pipe_middle_0_operation attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_middle_0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_middle_0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \pipe_middle_0_quotient_root attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_middle_0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_middle_0_ra$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_middle_0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_middle_0_rb$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 \pipe_middle_0_remainder attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_middle_0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_middle_0_xer_so$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_start_div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \pipe_start_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \pipe_start_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \pipe_start_dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \pipe_start_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \pipe_start_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \pipe_start_divisor_radicand attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_start_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe_start_logical_op__data_len$19 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_start_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_start_logical_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_start_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe_start_logical_op__imm_data__data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__imm_data__ok$6 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe_start_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe_start_logical_op__input_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_start_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_start_logical_op__insn$20 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_start_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_start_logical_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__invert_out$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__is_32bit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__is_signed$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__oe__oe$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__oe__ok$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__output_carry$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__rc__ok$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__rc__rc$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__write_cr0$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_start_logical_op__zero_a$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_start_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_start_muxid$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_start_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_start_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \pipe_start_operation attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_start_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_start_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_start_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_start_ra$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_start_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_start_rb$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_start_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_start_xer_so$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 30 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 31 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 28 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 32 \xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_so_ok attribute \module_not_derived 1 attribute \src "libresoc.v:26040.10-26043.4" cell \n$75 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:26044.10-26047.4" cell \p$74 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:26048.12-26111.4" cell \pipe_end \pipe_end connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe_end_cr_a connect \cr_a_ok \pipe_end_cr_a_ok connect \div_by_zero \pipe_end_div_by_zero connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 connect \dividend_neg \pipe_end_dividend_neg connect \divisor_neg \pipe_end_divisor_neg connect \logical_op__data_len \pipe_end_logical_op__data_len connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 connect \logical_op__input_carry \pipe_end_logical_op__input_carry connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 connect \logical_op__insn \pipe_end_logical_op__insn connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 connect \logical_op__insn_type \pipe_end_logical_op__insn_type connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 connect \logical_op__invert_in \pipe_end_logical_op__invert_in connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 connect \logical_op__invert_out \pipe_end_logical_op__invert_out connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 connect \logical_op__is_signed \pipe_end_logical_op__is_signed connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 connect \logical_op__output_carry \pipe_end_logical_op__output_carry connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 connect \logical_op__zero_a \pipe_end_logical_op__zero_a connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 connect \muxid \pipe_end_muxid connect \muxid$1 \pipe_end_muxid$51 connect \n_ready_i \pipe_end_n_ready_i connect \n_valid_o \pipe_end_n_valid_o connect \o \pipe_end_o connect \o_ok \pipe_end_o_ok connect \p_ready_o \pipe_end_p_ready_o connect \p_valid_i \pipe_end_p_valid_i connect \quotient_root \pipe_end_quotient_root connect \ra \pipe_end_ra connect \rb \pipe_end_rb connect \remainder \pipe_end_remainder connect \xer_ov \pipe_end_xer_ov connect \xer_ov_ok \pipe_end_xer_ov_ok connect \xer_so \pipe_end_xer_so connect \xer_so$20 \pipe_end_xer_so$70 connect \xer_so_ok \pipe_end_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:26112.17-26178.4" cell \pipe_middle_0 \pipe_middle_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \div_by_zero \pipe_middle_0_div_by_zero connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 connect \dividend \pipe_middle_0_dividend connect \dividend_neg \pipe_middle_0_dividend_neg connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 connect \divisor_neg \pipe_middle_0_divisor_neg connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 connect \divisor_radicand \pipe_middle_0_divisor_radicand connect \logical_op__data_len \pipe_middle_0_logical_op__data_len connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 connect \logical_op__insn \pipe_middle_0_logical_op__insn connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 connect \muxid \pipe_middle_0_muxid connect \muxid$1 \pipe_middle_0_muxid$24 connect \n_ready_i \pipe_middle_0_n_ready_i connect \n_valid_o \pipe_middle_0_n_valid_o connect \operation \pipe_middle_0_operation connect \p_ready_o \pipe_middle_0_p_ready_o connect \p_valid_i \pipe_middle_0_p_valid_i connect \quotient_root \pipe_middle_0_quotient_root connect \ra \pipe_middle_0_ra connect \ra$20 \pipe_middle_0_ra$43 connect \rb \pipe_middle_0_rb connect \rb$21 \pipe_middle_0_rb$44 connect \remainder \pipe_middle_0_remainder connect \xer_so \pipe_middle_0_xer_so connect \xer_so$22 \pipe_middle_0_xer_so$45 end attribute \module_not_derived 1 attribute \src "libresoc.v:26179.14-26238.4" cell \pipe_start \pipe_start connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \div_by_zero \pipe_start_div_by_zero connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 connect \dividend \pipe_start_dividend connect \dividend_neg \pipe_start_dividend_neg connect \divisor_neg \pipe_start_divisor_neg connect \divisor_radicand \pipe_start_divisor_radicand connect \logical_op__data_len \pipe_start_logical_op__data_len connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 connect \logical_op__input_carry \pipe_start_logical_op__input_carry connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 connect \logical_op__insn \pipe_start_logical_op__insn connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 connect \logical_op__insn_type \pipe_start_logical_op__insn_type connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 connect \logical_op__invert_in \pipe_start_logical_op__invert_in connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 connect \logical_op__invert_out \pipe_start_logical_op__invert_out connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 connect \logical_op__is_signed \pipe_start_logical_op__is_signed connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 connect \logical_op__output_carry \pipe_start_logical_op__output_carry connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 connect \logical_op__zero_a \pipe_start_logical_op__zero_a connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 connect \muxid \pipe_start_muxid connect \muxid$1 \pipe_start_muxid$2 connect \n_ready_i \pipe_start_n_ready_i connect \n_valid_o \pipe_start_n_valid_o connect \operation \pipe_start_operation connect \p_ready_o \pipe_start_p_ready_o connect \p_valid_i \pipe_start_p_valid_i connect \ra \pipe_start_ra connect \ra$20 \pipe_start_ra$21 connect \rb \pipe_start_rb connect \rb$21 \pipe_start_rb$22 connect \xer_so \pipe_start_xer_so connect \xer_so$22 \pipe_start_xer_so$23 end connect \muxid 2'00 connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } connect \muxid$71 \pipe_end_muxid$51 connect \pipe_end_n_ready_i \n_ready_i connect \n_valid_o \pipe_end_n_valid_o connect \pipe_start_xer_so$23 \xer_so$1 connect \pipe_start_rb$22 \rb connect \pipe_start_ra$21 \ra connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \pipe_start_muxid$2 2'00 connect \p_ready_o \pipe_start_p_ready_o connect \pipe_start_p_valid_i \p_valid_i connect \pipe_end_remainder \pipe_middle_0_remainder connect \pipe_end_quotient_root \pipe_middle_0_quotient_root connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 connect \pipe_end_rb \pipe_middle_0_rb$44 connect \pipe_end_ra \pipe_middle_0_ra$43 connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } connect \pipe_end_muxid \pipe_middle_0_muxid$24 connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o connect \pipe_middle_0_operation \pipe_start_operation connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand connect \pipe_middle_0_dividend \pipe_start_dividend connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg connect \pipe_middle_0_xer_so \pipe_start_xer_so connect \pipe_middle_0_rb \pipe_start_rb connect \pipe_middle_0_ra \pipe_start_ra connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } connect \pipe_middle_0_muxid \pipe_start_muxid connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o end attribute \src "libresoc.v:26288.1-26346.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" attribute \generator "nMigen" module \alu_l attribute \src "libresoc.v:26289.7-26289.20" wire $0\initial[0:0] attribute \src "libresoc.v:26334.3-26342.6" wire $0\q_int$next[0:0]$852 attribute \src "libresoc.v:26332.3-26333.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26334.3-26342.6" wire $1\q_int$next[0:0]$853 attribute \src "libresoc.v:26313.7-26313.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26324.17-26324.96" wire $and$libresoc.v:26324$842_Y attribute \src "libresoc.v:26329.17-26329.96" wire $and$libresoc.v:26329$847_Y attribute \src "libresoc.v:26326.18-26326.93" wire $not$libresoc.v:26326$844_Y attribute \src "libresoc.v:26328.17-26328.92" wire $not$libresoc.v:26328$846_Y attribute \src "libresoc.v:26331.17-26331.92" wire $not$libresoc.v:26331$849_Y attribute \src "libresoc.v:26325.18-26325.98" wire $or$libresoc.v:26325$843_Y attribute \src "libresoc.v:26327.18-26327.99" wire $or$libresoc.v:26327$845_Y attribute \src "libresoc.v:26330.17-26330.97" wire $or$libresoc.v:26330$848_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26289.7-26289.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26324$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26324$842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26329$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26329$847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26326$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26326$844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26328$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26328$846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26331$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26331$849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26325$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26325$843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26327$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26327$845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26330$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26330$848_Y end attribute \src "libresoc.v:26289.7-26289.20" process $proc$libresoc.v:26289$854 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26313.7-26313.19" process $proc$libresoc.v:26313$855 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26332.3-26333.27" process $proc$libresoc.v:26332$850 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26334.3-26342.6" process $proc$libresoc.v:26334$851 assign { } { } assign { } { } assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 attribute \src "libresoc.v:26335.5-26335.29" switch \initial attribute \src "libresoc.v:26335.9-26335.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$853 1'0 case assign $1\q_int$next[0:0]$853 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$852 end connect \$9 $and$libresoc.v:26324$842_Y connect \$11 $or$libresoc.v:26325$843_Y connect \$13 $not$libresoc.v:26326$844_Y connect \$15 $or$libresoc.v:26327$845_Y connect \$1 $not$libresoc.v:26328$846_Y connect \$3 $and$libresoc.v:26329$847_Y connect \$5 $or$libresoc.v:26330$848_Y connect \$7 $not$libresoc.v:26331$849_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26350.1-26408.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" attribute \generator "nMigen" module \alu_l$107 attribute \src "libresoc.v:26351.7-26351.20" wire $0\initial[0:0] attribute \src "libresoc.v:26396.3-26404.6" wire $0\q_int$next[0:0]$866 attribute \src "libresoc.v:26394.3-26395.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26396.3-26404.6" wire $1\q_int$next[0:0]$867 attribute \src "libresoc.v:26375.7-26375.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26386.17-26386.96" wire $and$libresoc.v:26386$856_Y attribute \src "libresoc.v:26391.17-26391.96" wire $and$libresoc.v:26391$861_Y attribute \src "libresoc.v:26388.18-26388.93" wire $not$libresoc.v:26388$858_Y attribute \src "libresoc.v:26390.17-26390.92" wire $not$libresoc.v:26390$860_Y attribute \src "libresoc.v:26393.17-26393.92" wire $not$libresoc.v:26393$863_Y attribute \src "libresoc.v:26387.18-26387.98" wire $or$libresoc.v:26387$857_Y attribute \src "libresoc.v:26389.18-26389.99" wire $or$libresoc.v:26389$859_Y attribute \src "libresoc.v:26392.17-26392.97" wire $or$libresoc.v:26392$862_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26351.7-26351.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26386$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26386$856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26391$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26391$861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26388$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26388$858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26390$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26390$860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26393$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26393$863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26387$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26387$857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26389$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26389$859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26392$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26392$862_Y end attribute \src "libresoc.v:26351.7-26351.20" process $proc$libresoc.v:26351$868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26375.7-26375.19" process $proc$libresoc.v:26375$869 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26394.3-26395.27" process $proc$libresoc.v:26394$864 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26396.3-26404.6" process $proc$libresoc.v:26396$865 assign { } { } assign { } { } assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 attribute \src "libresoc.v:26397.5-26397.29" switch \initial attribute \src "libresoc.v:26397.9-26397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$867 1'0 case assign $1\q_int$next[0:0]$867 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$866 end connect \$9 $and$libresoc.v:26386$856_Y connect \$11 $or$libresoc.v:26387$857_Y connect \$13 $not$libresoc.v:26388$858_Y connect \$15 $or$libresoc.v:26389$859_Y connect \$1 $not$libresoc.v:26390$860_Y connect \$3 $and$libresoc.v:26391$861_Y connect \$5 $or$libresoc.v:26392$862_Y connect \$7 $not$libresoc.v:26393$863_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26412.1-26470.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" attribute \generator "nMigen" module \alu_l$125 attribute \src "libresoc.v:26413.7-26413.20" wire $0\initial[0:0] attribute \src "libresoc.v:26458.3-26466.6" wire $0\q_int$next[0:0]$880 attribute \src "libresoc.v:26456.3-26457.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26458.3-26466.6" wire $1\q_int$next[0:0]$881 attribute \src "libresoc.v:26437.7-26437.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26448.17-26448.96" wire $and$libresoc.v:26448$870_Y attribute \src "libresoc.v:26453.17-26453.96" wire $and$libresoc.v:26453$875_Y attribute \src "libresoc.v:26450.18-26450.93" wire $not$libresoc.v:26450$872_Y attribute \src "libresoc.v:26452.17-26452.92" wire $not$libresoc.v:26452$874_Y attribute \src "libresoc.v:26455.17-26455.92" wire $not$libresoc.v:26455$877_Y attribute \src "libresoc.v:26449.18-26449.98" wire $or$libresoc.v:26449$871_Y attribute \src "libresoc.v:26451.18-26451.99" wire $or$libresoc.v:26451$873_Y attribute \src "libresoc.v:26454.17-26454.97" wire $or$libresoc.v:26454$876_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26413.7-26413.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26448$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26448$870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26453$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26453$875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26450$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26450$872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26452$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26452$874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26455$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26455$877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26449$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26449$871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26451$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26451$873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26454$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26454$876_Y end attribute \src "libresoc.v:26413.7-26413.20" process $proc$libresoc.v:26413$882 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26437.7-26437.19" process $proc$libresoc.v:26437$883 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26456.3-26457.27" process $proc$libresoc.v:26456$878 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26458.3-26466.6" process $proc$libresoc.v:26458$879 assign { } { } assign { } { } assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 attribute \src "libresoc.v:26459.5-26459.29" switch \initial attribute \src "libresoc.v:26459.9-26459.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$881 1'0 case assign $1\q_int$next[0:0]$881 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$880 end connect \$9 $and$libresoc.v:26448$870_Y connect \$11 $or$libresoc.v:26449$871_Y connect \$13 $not$libresoc.v:26450$872_Y connect \$15 $or$libresoc.v:26451$873_Y connect \$1 $not$libresoc.v:26452$874_Y connect \$3 $and$libresoc.v:26453$875_Y connect \$5 $or$libresoc.v:26454$876_Y connect \$7 $not$libresoc.v:26455$877_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26474.1-26532.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" attribute \generator "nMigen" module \alu_l$128 attribute \src "libresoc.v:26475.7-26475.20" wire $0\initial[0:0] attribute \src "libresoc.v:26520.3-26528.6" wire $0\q_int$next[0:0]$894 attribute \src "libresoc.v:26518.3-26519.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26520.3-26528.6" wire $1\q_int$next[0:0]$895 attribute \src "libresoc.v:26499.7-26499.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26510.17-26510.96" wire $and$libresoc.v:26510$884_Y attribute \src "libresoc.v:26515.17-26515.96" wire $and$libresoc.v:26515$889_Y attribute \src "libresoc.v:26512.18-26512.93" wire $not$libresoc.v:26512$886_Y attribute \src "libresoc.v:26514.17-26514.92" wire $not$libresoc.v:26514$888_Y attribute \src "libresoc.v:26517.17-26517.92" wire $not$libresoc.v:26517$891_Y attribute \src "libresoc.v:26511.18-26511.98" wire $or$libresoc.v:26511$885_Y attribute \src "libresoc.v:26513.18-26513.99" wire $or$libresoc.v:26513$887_Y attribute \src "libresoc.v:26516.17-26516.97" wire $or$libresoc.v:26516$890_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26475.7-26475.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26510$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26510$884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26515$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26515$889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26512$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26512$886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26514$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26514$888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26517$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26517$891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26511$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26511$885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26513$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26513$887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26516$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26516$890_Y end attribute \src "libresoc.v:26475.7-26475.20" process $proc$libresoc.v:26475$896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26499.7-26499.19" process $proc$libresoc.v:26499$897 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26518.3-26519.27" process $proc$libresoc.v:26518$892 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26520.3-26528.6" process $proc$libresoc.v:26520$893 assign { } { } assign { } { } assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 attribute \src "libresoc.v:26521.5-26521.29" switch \initial attribute \src "libresoc.v:26521.9-26521.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$895 1'0 case assign $1\q_int$next[0:0]$895 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$894 end connect \$9 $and$libresoc.v:26510$884_Y connect \$11 $or$libresoc.v:26511$885_Y connect \$13 $not$libresoc.v:26512$886_Y connect \$15 $or$libresoc.v:26513$887_Y connect \$1 $not$libresoc.v:26514$888_Y connect \$3 $and$libresoc.v:26515$889_Y connect \$5 $or$libresoc.v:26516$890_Y connect \$7 $not$libresoc.v:26517$891_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26536.1-26594.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" attribute \generator "nMigen" module \alu_l$16 attribute \src "libresoc.v:26537.7-26537.20" wire $0\initial[0:0] attribute \src "libresoc.v:26582.3-26590.6" wire $0\q_int$next[0:0]$908 attribute \src "libresoc.v:26580.3-26581.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26582.3-26590.6" wire $1\q_int$next[0:0]$909 attribute \src "libresoc.v:26561.7-26561.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26572.17-26572.96" wire $and$libresoc.v:26572$898_Y attribute \src "libresoc.v:26577.17-26577.96" wire $and$libresoc.v:26577$903_Y attribute \src "libresoc.v:26574.18-26574.93" wire $not$libresoc.v:26574$900_Y attribute \src "libresoc.v:26576.17-26576.92" wire $not$libresoc.v:26576$902_Y attribute \src "libresoc.v:26579.17-26579.92" wire $not$libresoc.v:26579$905_Y attribute \src "libresoc.v:26573.18-26573.98" wire $or$libresoc.v:26573$899_Y attribute \src "libresoc.v:26575.18-26575.99" wire $or$libresoc.v:26575$901_Y attribute \src "libresoc.v:26578.17-26578.97" wire $or$libresoc.v:26578$904_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26537.7-26537.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26572$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26572$898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26577$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26577$903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26574$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26574$900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26576$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26576$902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26579$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26579$905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26573$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26573$899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26575$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26575$901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26578$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26578$904_Y end attribute \src "libresoc.v:26537.7-26537.20" process $proc$libresoc.v:26537$910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26561.7-26561.19" process $proc$libresoc.v:26561$911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26580.3-26581.27" process $proc$libresoc.v:26580$906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26582.3-26590.6" process $proc$libresoc.v:26582$907 assign { } { } assign { } { } assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 attribute \src "libresoc.v:26583.5-26583.29" switch \initial attribute \src "libresoc.v:26583.9-26583.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$909 1'0 case assign $1\q_int$next[0:0]$909 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$908 end connect \$9 $and$libresoc.v:26572$898_Y connect \$11 $or$libresoc.v:26573$899_Y connect \$13 $not$libresoc.v:26574$900_Y connect \$15 $or$libresoc.v:26575$901_Y connect \$1 $not$libresoc.v:26576$902_Y connect \$3 $and$libresoc.v:26577$903_Y connect \$5 $or$libresoc.v:26578$904_Y connect \$7 $not$libresoc.v:26579$905_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26598.1-26656.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" attribute \generator "nMigen" module \alu_l$29 attribute \src "libresoc.v:26599.7-26599.20" wire $0\initial[0:0] attribute \src "libresoc.v:26644.3-26652.6" wire $0\q_int$next[0:0]$922 attribute \src "libresoc.v:26642.3-26643.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26644.3-26652.6" wire $1\q_int$next[0:0]$923 attribute \src "libresoc.v:26623.7-26623.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26634.17-26634.96" wire $and$libresoc.v:26634$912_Y attribute \src "libresoc.v:26639.17-26639.96" wire $and$libresoc.v:26639$917_Y attribute \src "libresoc.v:26636.18-26636.93" wire $not$libresoc.v:26636$914_Y attribute \src "libresoc.v:26638.17-26638.92" wire $not$libresoc.v:26638$916_Y attribute \src "libresoc.v:26641.17-26641.92" wire $not$libresoc.v:26641$919_Y attribute \src "libresoc.v:26635.18-26635.98" wire $or$libresoc.v:26635$913_Y attribute \src "libresoc.v:26637.18-26637.99" wire $or$libresoc.v:26637$915_Y attribute \src "libresoc.v:26640.17-26640.97" wire $or$libresoc.v:26640$918_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26599.7-26599.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26634$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26634$912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26639$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26639$917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26636$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26636$914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26638$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26638$916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26641$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26641$919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26635$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26635$913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26637$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26637$915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26640$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26640$918_Y end attribute \src "libresoc.v:26599.7-26599.20" process $proc$libresoc.v:26599$924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26623.7-26623.19" process $proc$libresoc.v:26623$925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26642.3-26643.27" process $proc$libresoc.v:26642$920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26644.3-26652.6" process $proc$libresoc.v:26644$921 assign { } { } assign { } { } assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 attribute \src "libresoc.v:26645.5-26645.29" switch \initial attribute \src "libresoc.v:26645.9-26645.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$923 1'0 case assign $1\q_int$next[0:0]$923 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$922 end connect \$9 $and$libresoc.v:26634$912_Y connect \$11 $or$libresoc.v:26635$913_Y connect \$13 $not$libresoc.v:26636$914_Y connect \$15 $or$libresoc.v:26637$915_Y connect \$1 $not$libresoc.v:26638$916_Y connect \$3 $and$libresoc.v:26639$917_Y connect \$5 $or$libresoc.v:26640$918_Y connect \$7 $not$libresoc.v:26641$919_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26660.1-26718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" attribute \generator "nMigen" module \alu_l$45 attribute \src "libresoc.v:26661.7-26661.20" wire $0\initial[0:0] attribute \src "libresoc.v:26706.3-26714.6" wire $0\q_int$next[0:0]$936 attribute \src "libresoc.v:26704.3-26705.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26706.3-26714.6" wire $1\q_int$next[0:0]$937 attribute \src "libresoc.v:26685.7-26685.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26696.17-26696.96" wire $and$libresoc.v:26696$926_Y attribute \src "libresoc.v:26701.17-26701.96" wire $and$libresoc.v:26701$931_Y attribute \src "libresoc.v:26698.18-26698.93" wire $not$libresoc.v:26698$928_Y attribute \src "libresoc.v:26700.17-26700.92" wire $not$libresoc.v:26700$930_Y attribute \src "libresoc.v:26703.17-26703.92" wire $not$libresoc.v:26703$933_Y attribute \src "libresoc.v:26697.18-26697.98" wire $or$libresoc.v:26697$927_Y attribute \src "libresoc.v:26699.18-26699.99" wire $or$libresoc.v:26699$929_Y attribute \src "libresoc.v:26702.17-26702.97" wire $or$libresoc.v:26702$932_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26661.7-26661.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26696$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26696$926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26701$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26701$931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26698$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26698$928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26700$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26700$930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26703$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26703$933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26697$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26697$927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26699$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26699$929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26702$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26702$932_Y end attribute \src "libresoc.v:26661.7-26661.20" process $proc$libresoc.v:26661$938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26685.7-26685.19" process $proc$libresoc.v:26685$939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26704.3-26705.27" process $proc$libresoc.v:26704$934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26706.3-26714.6" process $proc$libresoc.v:26706$935 assign { } { } assign { } { } assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 attribute \src "libresoc.v:26707.5-26707.29" switch \initial attribute \src "libresoc.v:26707.9-26707.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$937 1'0 case assign $1\q_int$next[0:0]$937 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$936 end connect \$9 $and$libresoc.v:26696$926_Y connect \$11 $or$libresoc.v:26697$927_Y connect \$13 $not$libresoc.v:26698$928_Y connect \$15 $or$libresoc.v:26699$929_Y connect \$1 $not$libresoc.v:26700$930_Y connect \$3 $and$libresoc.v:26701$931_Y connect \$5 $or$libresoc.v:26702$932_Y connect \$7 $not$libresoc.v:26703$933_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26722.1-26780.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" attribute \generator "nMigen" module \alu_l$61 attribute \src "libresoc.v:26723.7-26723.20" wire $0\initial[0:0] attribute \src "libresoc.v:26768.3-26776.6" wire $0\q_int$next[0:0]$950 attribute \src "libresoc.v:26766.3-26767.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26768.3-26776.6" wire $1\q_int$next[0:0]$951 attribute \src "libresoc.v:26747.7-26747.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26758.17-26758.96" wire $and$libresoc.v:26758$940_Y attribute \src "libresoc.v:26763.17-26763.96" wire $and$libresoc.v:26763$945_Y attribute \src "libresoc.v:26760.18-26760.93" wire $not$libresoc.v:26760$942_Y attribute \src "libresoc.v:26762.17-26762.92" wire $not$libresoc.v:26762$944_Y attribute \src "libresoc.v:26765.17-26765.92" wire $not$libresoc.v:26765$947_Y attribute \src "libresoc.v:26759.18-26759.98" wire $or$libresoc.v:26759$941_Y attribute \src "libresoc.v:26761.18-26761.99" wire $or$libresoc.v:26761$943_Y attribute \src "libresoc.v:26764.17-26764.97" wire $or$libresoc.v:26764$946_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26723.7-26723.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26758$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26758$940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26763$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26763$945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26760$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26760$942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26762$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26762$944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26765$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26765$947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26759$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26759$941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26761$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26761$943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26764$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26764$946_Y end attribute \src "libresoc.v:26723.7-26723.20" process $proc$libresoc.v:26723$952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26747.7-26747.19" process $proc$libresoc.v:26747$953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26766.3-26767.27" process $proc$libresoc.v:26766$948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26768.3-26776.6" process $proc$libresoc.v:26768$949 assign { } { } assign { } { } assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 attribute \src "libresoc.v:26769.5-26769.29" switch \initial attribute \src "libresoc.v:26769.9-26769.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$951 1'0 case assign $1\q_int$next[0:0]$951 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$950 end connect \$9 $and$libresoc.v:26758$940_Y connect \$11 $or$libresoc.v:26759$941_Y connect \$13 $not$libresoc.v:26760$942_Y connect \$15 $or$libresoc.v:26761$943_Y connect \$1 $not$libresoc.v:26762$944_Y connect \$3 $and$libresoc.v:26763$945_Y connect \$5 $or$libresoc.v:26764$946_Y connect \$7 $not$libresoc.v:26765$947_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26784.1-26842.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" attribute \generator "nMigen" module \alu_l$73 attribute \src "libresoc.v:26785.7-26785.20" wire $0\initial[0:0] attribute \src "libresoc.v:26830.3-26838.6" wire $0\q_int$next[0:0]$964 attribute \src "libresoc.v:26828.3-26829.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26830.3-26838.6" wire $1\q_int$next[0:0]$965 attribute \src "libresoc.v:26809.7-26809.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26820.17-26820.96" wire $and$libresoc.v:26820$954_Y attribute \src "libresoc.v:26825.17-26825.96" wire $and$libresoc.v:26825$959_Y attribute \src "libresoc.v:26822.18-26822.93" wire $not$libresoc.v:26822$956_Y attribute \src "libresoc.v:26824.17-26824.92" wire $not$libresoc.v:26824$958_Y attribute \src "libresoc.v:26827.17-26827.92" wire $not$libresoc.v:26827$961_Y attribute \src "libresoc.v:26821.18-26821.98" wire $or$libresoc.v:26821$955_Y attribute \src "libresoc.v:26823.18-26823.99" wire $or$libresoc.v:26823$957_Y attribute \src "libresoc.v:26826.17-26826.97" wire $or$libresoc.v:26826$960_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26785.7-26785.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26820$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26820$954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26825$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26825$959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26822$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26822$956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26824$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26824$958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26827$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26827$961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26821$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26821$955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26823$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26823$957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26826$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26826$960_Y end attribute \src "libresoc.v:26785.7-26785.20" process $proc$libresoc.v:26785$966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26809.7-26809.19" process $proc$libresoc.v:26809$967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26828.3-26829.27" process $proc$libresoc.v:26828$962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26830.3-26838.6" process $proc$libresoc.v:26830$963 assign { } { } assign { } { } assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 attribute \src "libresoc.v:26831.5-26831.29" switch \initial attribute \src "libresoc.v:26831.9-26831.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$965 1'0 case assign $1\q_int$next[0:0]$965 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$964 end connect \$9 $and$libresoc.v:26820$954_Y connect \$11 $or$libresoc.v:26821$955_Y connect \$13 $not$libresoc.v:26822$956_Y connect \$15 $or$libresoc.v:26823$957_Y connect \$1 $not$libresoc.v:26824$958_Y connect \$3 $and$libresoc.v:26825$959_Y connect \$5 $or$libresoc.v:26826$960_Y connect \$7 $not$libresoc.v:26827$961_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26846.1-26904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_l" attribute \generator "nMigen" module \alu_l$90 attribute \src "libresoc.v:26847.7-26847.20" wire $0\initial[0:0] attribute \src "libresoc.v:26892.3-26900.6" wire $0\q_int$next[0:0]$978 attribute \src "libresoc.v:26890.3-26891.27" wire $0\q_int[0:0] attribute \src "libresoc.v:26892.3-26900.6" wire $1\q_int$next[0:0]$979 attribute \src "libresoc.v:26871.7-26871.19" wire $1\q_int[0:0] attribute \src "libresoc.v:26882.17-26882.96" wire $and$libresoc.v:26882$968_Y attribute \src "libresoc.v:26887.17-26887.96" wire $and$libresoc.v:26887$973_Y attribute \src "libresoc.v:26884.18-26884.93" wire $not$libresoc.v:26884$970_Y attribute \src "libresoc.v:26886.17-26886.92" wire $not$libresoc.v:26886$972_Y attribute \src "libresoc.v:26889.17-26889.92" wire $not$libresoc.v:26889$975_Y attribute \src "libresoc.v:26883.18-26883.98" wire $or$libresoc.v:26883$969_Y attribute \src "libresoc.v:26885.18-26885.99" wire $or$libresoc.v:26885$971_Y attribute \src "libresoc.v:26888.17-26888.97" wire $or$libresoc.v:26888$974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:26847.7-26847.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:26882$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:26882$968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:26887$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:26887$973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:26884$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \Y $not$libresoc.v:26884$970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:26886$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26886$972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:26889$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu connect \Y $not$libresoc.v:26889$975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:26883$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu connect \Y $or$libresoc.v:26883$969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:26885$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int connect \Y $or$libresoc.v:26885$971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:26888$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu connect \Y $or$libresoc.v:26888$974_Y end attribute \src "libresoc.v:26847.7-26847.20" process $proc$libresoc.v:26847$980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:26871.7-26871.19" process $proc$libresoc.v:26871$981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:26890.3-26891.27" process $proc$libresoc.v:26890$976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:26892.3-26900.6" process $proc$libresoc.v:26892$977 assign { } { } assign { } { } assign $0\q_int$next[0:0]$978 $1\q_int$next[0:0]$979 attribute \src "libresoc.v:26893.5-26893.29" switch \initial attribute \src "libresoc.v:26893.9-26893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$979 1'0 case assign $1\q_int$next[0:0]$979 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$978 end connect \$9 $and$libresoc.v:26882$968_Y connect \$11 $or$libresoc.v:26883$969_Y connect \$13 $not$libresoc.v:26884$970_Y connect \$15 $or$libresoc.v:26885$971_Y connect \$1 $not$libresoc.v:26886$972_Y connect \$3 $and$libresoc.v:26887$973_Y connect \$5 $or$libresoc.v:26888$974_Y connect \$7 $not$libresoc.v:26889$975_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end attribute \src "libresoc.v:26908.1-27921.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 31 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 22 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$61 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 7 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$48 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 16 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 23 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$62 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 21 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \logical_pipe1_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe1_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe1_logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_pipe1_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_pipe1_logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe1_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe1_logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_pipe1_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_pipe1_logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_pipe1_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_pipe1_logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe1_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe1_logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe1_logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe1_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe1_muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \logical_pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \logical_pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \logical_pipe1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \logical_pipe1_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \logical_pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \logical_pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \logical_pipe1_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \logical_pipe1_xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe1_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \logical_pipe2_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \logical_pipe2_cr_a$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_cr_a_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe2_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe2_logical_op__data_len$38 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_pipe2_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_pipe2_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe2_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_pipe2_logical_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__imm_data__ok$25 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_pipe2_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_pipe2_logical_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_pipe2_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_pipe2_logical_op__insn$39 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe2_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_pipe2_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_pipe2_logical_op__zero_a$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe2_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \logical_pipe2_muxid$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \logical_pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \logical_pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \logical_pipe2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \logical_pipe2_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_o_ok$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \logical_pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \logical_pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \logical_pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 5 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 4 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 30 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 29 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 26 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 27 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 28 \xer_so attribute \module_not_derived 1 attribute \src "libresoc.v:27781.17-27835.4" cell \logical_pipe1 \logical_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \logical_pipe1_cr_a connect \cr_a_ok \logical_pipe1_cr_a_ok connect \logical_op__data_len \logical_pipe1_logical_op__data_len connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 connect \logical_op__insn \logical_pipe1_logical_op__insn connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 connect \muxid \logical_pipe1_muxid connect \muxid$1 \logical_pipe1_muxid$1 connect \n_ready_i \logical_pipe1_n_ready_i connect \n_valid_o \logical_pipe1_n_valid_o connect \o \logical_pipe1_o connect \o_ok \logical_pipe1_o_ok connect \p_ready_o \logical_pipe1_p_ready_o connect \p_valid_i \logical_pipe1_p_valid_i connect \ra \logical_pipe1_ra connect \rb \logical_pipe1_rb connect \xer_so \logical_pipe1_xer_so connect \xer_so$20 \logical_pipe1_xer_so$20 connect \xer_so_ok \logical_pipe1_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:27836.17-27891.4" cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \logical_pipe2_cr_a connect \cr_a$22 \logical_pipe2_cr_a$42 connect \cr_a_ok \logical_pipe2_cr_a_ok connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 connect \logical_op__data_len \logical_pipe2_logical_op__data_len connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 connect \logical_op__insn \logical_pipe2_logical_op__insn connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 connect \muxid \logical_pipe2_muxid connect \muxid$1 \logical_pipe2_muxid$21 connect \n_ready_i \logical_pipe2_n_ready_i connect \n_valid_o \logical_pipe2_n_valid_o connect \o \logical_pipe2_o connect \o$20 \logical_pipe2_o$40 connect \o_ok \logical_pipe2_o_ok connect \o_ok$21 \logical_pipe2_o_ok$41 connect \p_ready_o \logical_pipe2_p_ready_o connect \p_valid_i \logical_pipe2_p_valid_i connect \xer_so \logical_pipe2_xer_so connect \xer_so_ok \logical_pipe2_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:27892.10-27895.4" cell \n$47 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:27896.10-27899.4" cell \p$46 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end connect \muxid 2'00 connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } connect \muxid$44 \logical_pipe2_muxid$21 connect \logical_pipe2_n_ready_i \n_ready_i connect \n_valid_o \logical_pipe2_n_valid_o connect \logical_pipe1_xer_so$20 \xer_so connect \logical_pipe1_rb \rb connect \logical_pipe1_ra \ra connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \logical_pipe1_muxid$1 2'00 connect \p_ready_o \logical_pipe1_p_ready_o connect \logical_pipe1_p_valid_i \p_valid_i connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } connect \logical_pipe2_muxid \logical_pipe1_muxid connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o end attribute \src "libresoc.v:27925.1-29142.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 29 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 9 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_op__fn_unit$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 10 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_op__imm_data__data$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__imm_data__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 19 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_op__insn$61 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 8 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_32bit$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_signed$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__oe$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__rc$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$58 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_pipe1_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_pipe1_mul_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe1_mul_op__imm_data__data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__imm_data__ok$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_pipe1_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_pipe1_mul_op__insn$14 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe1_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe1_mul_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__is_32bit$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__is_signed$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__oe__oe$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__oe__ok$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__rc__ok$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__rc__rc$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe1_mul_op__write_cr0$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe1_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe1_muxid$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \mul_pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \mul_pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul_pipe1_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \mul_pipe1_neg_res32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \mul_pipe1_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \mul_pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe1_ra$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe1_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe1_rb$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe1_xer_so$17 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_pipe2_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_pipe2_mul_op__fn_unit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe2_mul_op__imm_data__data$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__imm_data__ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_pipe2_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_pipe2_mul_op__insn$30 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe2_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe2_mul_op__insn_type$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__is_32bit$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__is_signed$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__oe__oe$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__oe__ok$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__rc__ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__rc__rc$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe2_mul_op__write_cr0$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe2_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe2_muxid$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \mul_pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \mul_pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul_pipe2_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \mul_pipe2_neg_res$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \mul_pipe2_neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire \mul_pipe2_neg_res32$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul_pipe2_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \mul_pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \mul_pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe2_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul_pipe2_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe2_xer_so$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \mul_pipe3_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_pipe3_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_pipe3_mul_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_pipe3_mul_op__imm_data__data$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__imm_data__ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_pipe3_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_pipe3_mul_op__insn$46 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe3_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_pipe3_mul_op__insn_type$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__is_32bit$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__is_signed$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__oe__ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__rc__ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_pipe3_mul_op__write_cr0$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe3_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul_pipe3_muxid$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \mul_pipe3_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \mul_pipe3_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \mul_pipe3_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire \mul_pipe3_neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul_pipe3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \mul_pipe3_o$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \mul_pipe3_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \mul_pipe3_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \mul_pipe3_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe3_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_xer_so$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul_pipe3_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 7 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 6 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 28 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 27 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 24 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 25 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 22 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 26 \xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_so_ok attribute \module_not_derived 1 attribute \src "libresoc.v:28970.13-29011.4" cell \mul_pipe1 \mul_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 connect \mul_op__insn \mul_pipe1_mul_op__insn connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 connect \muxid \mul_pipe1_muxid connect \muxid$1 \mul_pipe1_muxid$2 connect \n_ready_i \mul_pipe1_n_ready_i connect \n_valid_o \mul_pipe1_n_valid_o connect \neg_res \mul_pipe1_neg_res connect \neg_res32 \mul_pipe1_neg_res32 connect \p_ready_o \mul_pipe1_p_ready_o connect \p_valid_i \mul_pipe1_p_valid_i connect \ra \mul_pipe1_ra connect \ra$14 \mul_pipe1_ra$15 connect \rb \mul_pipe1_rb connect \rb$15 \mul_pipe1_rb$16 connect \xer_so \mul_pipe1_xer_so connect \xer_so$16 \mul_pipe1_xer_so$17 end attribute \module_not_derived 1 attribute \src "libresoc.v:29012.13-29054.4" cell \mul_pipe2 \mul_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 connect \mul_op__insn \mul_pipe2_mul_op__insn connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 connect \muxid \mul_pipe2_muxid connect \muxid$1 \mul_pipe2_muxid$18 connect \n_ready_i \mul_pipe2_n_ready_i connect \n_valid_o \mul_pipe2_n_valid_o connect \neg_res \mul_pipe2_neg_res connect \neg_res$15 \mul_pipe2_neg_res$32 connect \neg_res32 \mul_pipe2_neg_res32 connect \neg_res32$16 \mul_pipe2_neg_res32$33 connect \o \mul_pipe2_o connect \p_ready_o \mul_pipe2_p_ready_o connect \p_valid_i \mul_pipe2_p_valid_i connect \ra \mul_pipe2_ra connect \rb \mul_pipe2_rb connect \xer_so \mul_pipe2_xer_so connect \xer_so$14 \mul_pipe2_xer_so$31 end attribute \module_not_derived 1 attribute \src "libresoc.v:29055.13-29100.4" cell \mul_pipe3 \mul_pipe3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \mul_pipe3_cr_a connect \cr_a_ok \mul_pipe3_cr_a_ok connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 connect \mul_op__insn \mul_pipe3_mul_op__insn connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 connect \muxid \mul_pipe3_muxid connect \muxid$1 \mul_pipe3_muxid$34 connect \n_ready_i \mul_pipe3_n_ready_i connect \n_valid_o \mul_pipe3_n_valid_o connect \neg_res \mul_pipe3_neg_res connect \neg_res32 \mul_pipe3_neg_res32 connect \o \mul_pipe3_o connect \o$14 \mul_pipe3_o$47 connect \o_ok \mul_pipe3_o_ok connect \p_ready_o \mul_pipe3_p_ready_o connect \p_valid_i \mul_pipe3_p_valid_i connect \xer_ov \mul_pipe3_xer_ov connect \xer_ov_ok \mul_pipe3_xer_ov_ok connect \xer_so \mul_pipe3_xer_so connect \xer_so$15 \mul_pipe3_xer_so$48 connect \xer_so_ok \mul_pipe3_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:29101.10-29104.4" cell \n$92 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:29105.10-29108.4" cell \p$91 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end connect \muxid 2'00 connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } connect \muxid$49 \mul_pipe3_muxid$34 connect \mul_pipe3_n_ready_i \n_ready_i connect \n_valid_o \mul_pipe3_n_valid_o connect \mul_pipe1_xer_so$17 \xer_so$1 connect \mul_pipe1_rb$16 \rb connect \mul_pipe1_ra$15 \ra connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul_pipe1_muxid$2 2'00 connect \p_ready_o \mul_pipe1_p_ready_o connect \mul_pipe1_p_valid_i \p_valid_i connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 connect \mul_pipe3_o \mul_pipe2_o connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } connect \mul_pipe3_muxid \mul_pipe2_muxid$18 connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 connect \mul_pipe2_neg_res \mul_pipe1_neg_res connect \mul_pipe2_xer_so \mul_pipe1_xer_so connect \mul_pipe2_rb \mul_pipe1_rb connect \mul_pipe2_ra \mul_pipe1_ra connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } connect \mul_pipe2_muxid \mul_pipe1_muxid connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o end attribute \src "libresoc.v:29146.1-30179.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 5 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 33 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 32 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe1_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rc attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe1_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe1_sr_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_sr_op__imm_data__data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__imm_data__ok$6 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe1_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe1_sr_op__input_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__input_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_sr_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_sr_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__invert_in$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__is_32bit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__is_signed$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__oe__oe$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__oe__ok$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__output_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__output_cr$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__rc__ok$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__rc__rc$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__write_cr0$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe1_xer_ca$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe1_xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe1_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \pipe2_cr_a$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_cr_a_ok$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe2_muxid$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_o_ok$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe2_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe2_sr_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_sr_op__imm_data__data$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__imm_data__ok$26 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe2_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \pipe2_sr_op__input_carry$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__input_cr$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe2_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe2_sr_op__insn$39 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe2_sr_op__insn_type$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__invert_in$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__is_32bit$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__is_signed$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__oe__oe$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__oe__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__output_carry$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__output_cr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__rc__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__rc__rc$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__write_cr0$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe2_xer_ca$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_ca_ok$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 27 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 28 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 29 \rc attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 8 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \sr_op__fn_unit$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 9 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \sr_op__imm_data__data$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__imm_data__ok$50 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 17 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \sr_op__input_carry$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__input_cr$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 23 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \sr_op__insn$63 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 7 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__invert_in$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 21 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_32bit$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 22 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_signed$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__oe$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__ok$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_carry$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_cr$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__rc$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 26 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 31 \xer_ca$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 30 \xer_so attribute \module_not_derived 1 attribute \src "libresoc.v:30031.11-30034.4" cell \n$109 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:30035.11-30038.4" cell \p$108 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:30039.15-30095.4" cell \pipe1$110 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe1_cr_a connect \cr_a_ok \pipe1_cr_a_ok connect \muxid \pipe1_muxid connect \muxid$1 \pipe1_muxid$2 connect \n_ready_i \pipe1_n_ready_i connect \n_valid_o \pipe1_n_valid_o connect \o \pipe1_o connect \o_ok \pipe1_o_ok connect \p_ready_o \pipe1_p_ready_o connect \p_valid_i \pipe1_p_valid_i connect \ra \pipe1_ra connect \rb \pipe1_rb connect \rc \pipe1_rc connect \sr_op__fn_unit \pipe1_sr_op__fn_unit connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 connect \sr_op__input_carry \pipe1_sr_op__input_carry connect \sr_op__input_carry$12 \pipe1_sr_op__input_carry$13 connect \sr_op__input_cr \pipe1_sr_op__input_cr connect \sr_op__input_cr$14 \pipe1_sr_op__input_cr$15 connect \sr_op__insn \pipe1_sr_op__insn connect \sr_op__insn$18 \pipe1_sr_op__insn$19 connect \sr_op__insn_type \pipe1_sr_op__insn_type connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 connect \sr_op__invert_in \pipe1_sr_op__invert_in connect \sr_op__invert_in$11 \pipe1_sr_op__invert_in$12 connect \sr_op__is_32bit \pipe1_sr_op__is_32bit connect \sr_op__is_32bit$16 \pipe1_sr_op__is_32bit$17 connect \sr_op__is_signed \pipe1_sr_op__is_signed connect \sr_op__is_signed$17 \pipe1_sr_op__is_signed$18 connect \sr_op__oe__oe \pipe1_sr_op__oe__oe connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 connect \sr_op__oe__ok \pipe1_sr_op__oe__ok connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 connect \sr_op__output_carry \pipe1_sr_op__output_carry connect \sr_op__output_carry$13 \pipe1_sr_op__output_carry$14 connect \sr_op__output_cr \pipe1_sr_op__output_cr connect \sr_op__output_cr$15 \pipe1_sr_op__output_cr$16 connect \sr_op__rc__ok \pipe1_sr_op__rc__ok connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 connect \sr_op__rc__rc \pipe1_sr_op__rc__rc connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 connect \xer_ca \pipe1_xer_ca connect \xer_ca$20 \pipe1_xer_ca$21 connect \xer_ca_ok \pipe1_xer_ca_ok connect \xer_so \pipe1_xer_so connect \xer_so$19 \pipe1_xer_so$20 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:30096.15-30153.4" cell \pipe2$115 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe2_cr_a connect \cr_a$21 \pipe2_cr_a$42 connect \cr_a_ok \pipe2_cr_a_ok connect \cr_a_ok$22 \pipe2_cr_a_ok$43 connect \muxid \pipe2_muxid connect \muxid$1 \pipe2_muxid$22 connect \n_ready_i \pipe2_n_ready_i connect \n_valid_o \pipe2_n_valid_o connect \o \pipe2_o connect \o$19 \pipe2_o$40 connect \o_ok \pipe2_o_ok connect \o_ok$20 \pipe2_o_ok$41 connect \p_ready_o \pipe2_p_ready_o connect \p_valid_i \pipe2_p_valid_i connect \sr_op__fn_unit \pipe2_sr_op__fn_unit connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$24 connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$25 connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$26 connect \sr_op__input_carry \pipe2_sr_op__input_carry connect \sr_op__input_carry$12 \pipe2_sr_op__input_carry$33 connect \sr_op__input_cr \pipe2_sr_op__input_cr connect \sr_op__input_cr$14 \pipe2_sr_op__input_cr$35 connect \sr_op__insn \pipe2_sr_op__insn connect \sr_op__insn$18 \pipe2_sr_op__insn$39 connect \sr_op__insn_type \pipe2_sr_op__insn_type connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$23 connect \sr_op__invert_in \pipe2_sr_op__invert_in connect \sr_op__invert_in$11 \pipe2_sr_op__invert_in$32 connect \sr_op__is_32bit \pipe2_sr_op__is_32bit connect \sr_op__is_32bit$16 \pipe2_sr_op__is_32bit$37 connect \sr_op__is_signed \pipe2_sr_op__is_signed connect \sr_op__is_signed$17 \pipe2_sr_op__is_signed$38 connect \sr_op__oe__oe \pipe2_sr_op__oe__oe connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$29 connect \sr_op__oe__ok \pipe2_sr_op__oe__ok connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$30 connect \sr_op__output_carry \pipe2_sr_op__output_carry connect \sr_op__output_carry$13 \pipe2_sr_op__output_carry$34 connect \sr_op__output_cr \pipe2_sr_op__output_cr connect \sr_op__output_cr$15 \pipe2_sr_op__output_cr$36 connect \sr_op__rc__ok \pipe2_sr_op__rc__ok connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$28 connect \sr_op__rc__rc \pipe2_sr_op__rc__rc connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$27 connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$31 connect \xer_ca \pipe2_xer_ca connect \xer_ca$23 \pipe2_xer_ca$44 connect \xer_ca_ok \pipe2_xer_ca_ok connect \xer_ca_ok$24 \pipe2_xer_ca_ok$45 connect \xer_so \pipe2_xer_so connect \xer_so_ok \pipe2_xer_so_ok end connect \muxid 2'00 connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$45 \pipe2_xer_ca$44 } connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$43 \pipe2_cr_a$42 } connect { \o_ok \o } { \pipe2_o_ok$41 \pipe2_o$40 } connect { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 \sr_op__invert_in$56 \sr_op__write_cr0$55 \sr_op__oe__ok$54 \sr_op__oe__oe$53 \sr_op__rc__ok$52 \sr_op__rc__rc$51 \sr_op__imm_data__ok$50 \sr_op__imm_data__data$49 \sr_op__fn_unit$48 \sr_op__insn_type$47 } { \pipe2_sr_op__insn$39 \pipe2_sr_op__is_signed$38 \pipe2_sr_op__is_32bit$37 \pipe2_sr_op__output_cr$36 \pipe2_sr_op__input_cr$35 \pipe2_sr_op__output_carry$34 \pipe2_sr_op__input_carry$33 \pipe2_sr_op__invert_in$32 \pipe2_sr_op__write_cr0$31 \pipe2_sr_op__oe__ok$30 \pipe2_sr_op__oe__oe$29 \pipe2_sr_op__rc__ok$28 \pipe2_sr_op__rc__rc$27 \pipe2_sr_op__imm_data__ok$26 \pipe2_sr_op__imm_data__data$25 \pipe2_sr_op__fn_unit$24 \pipe2_sr_op__insn_type$23 } connect \muxid$46 \pipe2_muxid$22 connect \pipe2_n_ready_i \n_ready_i connect \n_valid_o \pipe2_n_valid_o connect \pipe1_xer_ca$21 \xer_ca$1 connect \pipe1_xer_so$20 \xer_so connect \pipe1_rc \rc connect \pipe1_rb \rb connect \pipe1_ra \ra connect { \pipe1_sr_op__insn$19 \pipe1_sr_op__is_signed$18 \pipe1_sr_op__is_32bit$17 \pipe1_sr_op__output_cr$16 \pipe1_sr_op__input_cr$15 \pipe1_sr_op__output_carry$14 \pipe1_sr_op__input_carry$13 \pipe1_sr_op__invert_in$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \pipe1_muxid$2 2'00 connect \p_ready_o \pipe1_p_ready_o connect \pipe1_p_valid_i \p_valid_i connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__invert_in \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__invert_in \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } connect \pipe2_muxid \pipe1_muxid connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end attribute \src "libresoc.v:30183.1-30741.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 28 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 16 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 22 \fast1$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 9 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 8 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 14 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 27 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 26 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_fast1$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe_muxid$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe_spr1$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe_spr_op__fn_unit$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe_spr_op__insn$9 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe_spr_op__insn_type$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe_spr_op__is_32bit$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe_xer_ca$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \pipe_xer_ov$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_so$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 15 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 21 \spr1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 11 \spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \spr_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \spr_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 10 \spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_op__insn_type$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \spr_op__is_32bit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 19 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 25 \xer_ca$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 18 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 24 \xer_ov$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 23 \xer_so$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \xer_so_ok attribute \module_not_derived 1 attribute \src "libresoc.v:30676.10-30679.4" cell \n$63 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:30680.10-30683.4" cell \p$62 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:30684.13-30719.4" cell \pipe$64 \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \fast1 \pipe_fast1 connect \fast1$7 \pipe_fast1$12 connect \fast1_ok \pipe_fast1_ok connect \muxid \pipe_muxid connect \muxid$1 \pipe_muxid$6 connect \n_ready_i \pipe_n_ready_i connect \n_valid_o \pipe_n_valid_o connect \o \pipe_o connect \o_ok \pipe_o_ok connect \p_ready_o \pipe_p_ready_o connect \p_valid_i \pipe_p_valid_i connect \ra \pipe_ra connect \spr1 \pipe_spr1 connect \spr1$6 \pipe_spr1$11 connect \spr1_ok \pipe_spr1_ok connect \spr_op__fn_unit \pipe_spr_op__fn_unit connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 connect \spr_op__insn \pipe_spr_op__insn connect \spr_op__insn$4 \pipe_spr_op__insn$9 connect \spr_op__insn_type \pipe_spr_op__insn_type connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 connect \spr_op__is_32bit \pipe_spr_op__is_32bit connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 connect \xer_ca \pipe_xer_ca connect \xer_ca$10 \pipe_xer_ca$15 connect \xer_ca_ok \pipe_xer_ca_ok connect \xer_ov \pipe_xer_ov connect \xer_ov$9 \pipe_xer_ov$14 connect \xer_ov_ok \pipe_xer_ov_ok connect \xer_so \pipe_xer_so connect \xer_so$8 \pipe_xer_so$13 connect \xer_so_ok \pipe_xer_so_ok end connect \muxid 2'00 connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } connect { \o_ok \o } { \pipe_o_ok \pipe_o } connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } connect \muxid$16 \pipe_muxid$6 connect \pipe_n_ready_i \n_ready_i connect \n_valid_o \pipe_n_valid_o connect \pipe_xer_ca \xer_ca$5 connect \pipe_xer_ov \xer_ov$4 connect \pipe_xer_so \xer_so$3 connect \pipe_fast1 \fast1$2 connect \pipe_spr1 \spr1$1 connect \pipe_ra \ra connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \pipe_muxid 2'00 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end attribute \src "libresoc.v:30745.1-31618.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 29 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 19 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 25 \fast1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 26 \fast2$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 22 \msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 8 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 7 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 21 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 18 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 28 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 27 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_fast1$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_fast2$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \pipe1_muxid$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe1_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_ra$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rb$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe1_trap_op__cia$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe1_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe1_trap_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_trap_op__insn$6 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute 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width 13 \pipe1_trap_op__trapaddr$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \pipe1_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \pipe1_trap_op__traptype$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe2_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_fast1$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe2_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pipe2_fast2$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pipe2_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe2_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe2_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_trap_op__cia$22 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \pipe2_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute 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attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute 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"OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 9 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \trap_op__is_32bit$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 17 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__ldst_exc$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 12 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__msr$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 16 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \trap_op__trapaddr$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 15 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$36 attribute \module_not_derived 1 attribute \src "libresoc.v:31506.10-31509.4" cell \n$31 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:31510.10-31513.4" cell \p$30 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:31514.14-31549.4" cell \pipe1$32 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \fast1 \pipe1_fast1 connect \fast1$13 \pipe1_fast1$15 connect \fast2 \pipe1_fast2 connect \fast2$14 \pipe1_fast2$16 connect \muxid \pipe1_muxid connect \muxid$1 \pipe1_muxid$3 connect \n_ready_i \pipe1_n_ready_i connect \n_valid_o \pipe1_n_valid_o connect \p_ready_o \pipe1_p_ready_o connect \p_valid_i \pipe1_p_valid_i connect \ra \pipe1_ra connect \ra$11 \pipe1_ra$13 connect \rb \pipe1_rb connect \rb$12 \pipe1_rb$14 connect \trap_op__cia \pipe1_trap_op__cia connect \trap_op__cia$6 \pipe1_trap_op__cia$8 connect \trap_op__fn_unit \pipe1_trap_op__fn_unit connect \trap_op__fn_unit$3 \pipe1_trap_op__fn_unit$5 connect \trap_op__insn \pipe1_trap_op__insn connect \trap_op__insn$4 \pipe1_trap_op__insn$6 connect \trap_op__insn_type \pipe1_trap_op__insn_type connect \trap_op__insn_type$2 \pipe1_trap_op__insn_type$4 connect \trap_op__is_32bit \pipe1_trap_op__is_32bit connect \trap_op__is_32bit$7 \pipe1_trap_op__is_32bit$9 connect \trap_op__ldst_exc \pipe1_trap_op__ldst_exc connect \trap_op__ldst_exc$10 \pipe1_trap_op__ldst_exc$12 connect \trap_op__msr \pipe1_trap_op__msr connect \trap_op__msr$5 \pipe1_trap_op__msr$7 connect \trap_op__trapaddr \pipe1_trap_op__trapaddr connect \trap_op__trapaddr$9 \pipe1_trap_op__trapaddr$11 connect \trap_op__traptype \pipe1_trap_op__traptype connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 end attribute \module_not_derived 1 attribute \src "libresoc.v:31550.14-31591.4" cell \pipe2$35 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \fast1 \pipe2_fast1 connect \fast1$11 \pipe2_fast1$27 connect \fast1_ok \pipe2_fast1_ok connect \fast2 \pipe2_fast2 connect \fast2$12 \pipe2_fast2$28 connect \fast2_ok \pipe2_fast2_ok connect \msr \pipe2_msr connect \msr_ok \pipe2_msr_ok connect \muxid \pipe2_muxid connect \muxid$1 \pipe2_muxid$17 connect \n_ready_i \pipe2_n_ready_i connect \n_valid_o \pipe2_n_valid_o connect \nia \pipe2_nia connect \nia_ok \pipe2_nia_ok connect \o \pipe2_o connect \o_ok \pipe2_o_ok connect \p_ready_o \pipe2_p_ready_o connect \p_valid_i \pipe2_p_valid_i connect \ra \pipe2_ra connect \rb \pipe2_rb connect \trap_op__cia \pipe2_trap_op__cia connect \trap_op__cia$6 \pipe2_trap_op__cia$22 connect \trap_op__fn_unit \pipe2_trap_op__fn_unit connect \trap_op__fn_unit$3 \pipe2_trap_op__fn_unit$19 connect \trap_op__insn \pipe2_trap_op__insn connect \trap_op__insn$4 \pipe2_trap_op__insn$20 connect \trap_op__insn_type \pipe2_trap_op__insn_type connect \trap_op__insn_type$2 \pipe2_trap_op__insn_type$18 connect \trap_op__is_32bit \pipe2_trap_op__is_32bit connect \trap_op__is_32bit$7 \pipe2_trap_op__is_32bit$23 connect \trap_op__ldst_exc \pipe2_trap_op__ldst_exc connect \trap_op__ldst_exc$10 \pipe2_trap_op__ldst_exc$26 connect \trap_op__msr \pipe2_trap_op__msr connect \trap_op__msr$5 \pipe2_trap_op__msr$21 connect \trap_op__trapaddr \pipe2_trap_op__trapaddr connect \trap_op__trapaddr$9 \pipe2_trap_op__trapaddr$25 connect \trap_op__traptype \pipe2_trap_op__traptype connect \trap_op__traptype$8 \pipe2_trap_op__traptype$24 end connect \muxid 2'00 connect { \msr_ok \msr } { \pipe2_msr_ok \pipe2_msr } connect { \nia_ok \nia } { \pipe2_nia_ok \pipe2_nia } connect { \fast2_ok \fast2 } { \pipe2_fast2_ok \pipe2_fast2$28 } connect { \fast1_ok \fast1 } { \pipe2_fast1_ok \pipe2_fast1$27 } connect { \o_ok \o } { \pipe2_o_ok \pipe2_o } connect { \trap_op__ldst_exc$38 \trap_op__trapaddr$37 \trap_op__traptype$36 \trap_op__is_32bit$35 \trap_op__cia$34 \trap_op__msr$33 \trap_op__insn$32 \trap_op__fn_unit$31 \trap_op__insn_type$30 } { \pipe2_trap_op__ldst_exc$26 \pipe2_trap_op__trapaddr$25 \pipe2_trap_op__traptype$24 \pipe2_trap_op__is_32bit$23 \pipe2_trap_op__cia$22 \pipe2_trap_op__msr$21 \pipe2_trap_op__insn$20 \pipe2_trap_op__fn_unit$19 \pipe2_trap_op__insn_type$18 } connect \muxid$29 \pipe2_muxid$17 connect \pipe2_n_ready_i \n_ready_i connect \n_valid_o \pipe2_n_valid_o connect \pipe1_fast2$16 \fast2$2 connect \pipe1_fast1$15 \fast1$1 connect \pipe1_rb$14 \rb connect \pipe1_ra$13 \ra connect { \pipe1_trap_op__ldst_exc$12 \pipe1_trap_op__trapaddr$11 \pipe1_trap_op__traptype$10 \pipe1_trap_op__is_32bit$9 \pipe1_trap_op__cia$8 \pipe1_trap_op__msr$7 \pipe1_trap_op__insn$6 \pipe1_trap_op__fn_unit$5 \pipe1_trap_op__insn_type$4 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \pipe1_muxid$3 2'00 connect \p_ready_o \pipe1_p_ready_o connect \pipe1_p_valid_i \p_valid_i connect \pipe2_fast2 \pipe1_fast2 connect \pipe2_fast1 \pipe1_fast1 connect \pipe2_rb \pipe1_rb connect \pipe2_ra \pipe1_ra connect { \pipe2_trap_op__ldst_exc \pipe2_trap_op__trapaddr \pipe2_trap_op__traptype \pipe2_trap_op__is_32bit \pipe2_trap_op__cia \pipe2_trap_op__msr \pipe2_trap_op__insn \pipe2_trap_op__fn_unit \pipe2_trap_op__insn_type } { \pipe1_trap_op__ldst_exc \pipe1_trap_op__trapaddr \pipe1_trap_op__traptype \pipe1_trap_op__is_32bit \pipe1_trap_op__cia \pipe1_trap_op__msr \pipe1_trap_op__insn \pipe1_trap_op__fn_unit \pipe1_trap_op__insn_type } connect \pipe2_muxid \pipe1_muxid connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end attribute \src "libresoc.v:31622.1-31680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" attribute \generator "nMigen" module \alui_l attribute \src "libresoc.v:31623.7-31623.20" wire $0\initial[0:0] attribute \src "libresoc.v:31668.3-31676.6" wire $0\q_int$next[0:0]$992 attribute \src "libresoc.v:31666.3-31667.27" wire $0\q_int[0:0] attribute \src "libresoc.v:31668.3-31676.6" wire $1\q_int$next[0:0]$993 attribute \src "libresoc.v:31647.7-31647.19" wire $1\q_int[0:0] attribute \src "libresoc.v:31658.17-31658.96" wire $and$libresoc.v:31658$982_Y attribute \src "libresoc.v:31663.17-31663.96" wire $and$libresoc.v:31663$987_Y attribute \src "libresoc.v:31660.18-31660.94" wire $not$libresoc.v:31660$984_Y attribute \src "libresoc.v:31662.17-31662.93" wire $not$libresoc.v:31662$986_Y attribute \src "libresoc.v:31665.17-31665.93" wire $not$libresoc.v:31665$989_Y attribute \src "libresoc.v:31659.18-31659.99" wire $or$libresoc.v:31659$983_Y attribute \src "libresoc.v:31661.18-31661.100" wire $or$libresoc.v:31661$985_Y attribute \src "libresoc.v:31664.17-31664.98" wire $or$libresoc.v:31664$988_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31623.7-31623.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:31658$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:31658$982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:31663$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:31663$987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:31660$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:31660$984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:31662$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31662$986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:31665$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31665$989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:31659$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:31659$983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:31661$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:31661$985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:31664$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:31664$988_Y end attribute \src "libresoc.v:31623.7-31623.20" process $proc$libresoc.v:31623$994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:31647.7-31647.19" process $proc$libresoc.v:31647$995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:31666.3-31667.27" process $proc$libresoc.v:31666$990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:31668.3-31676.6" process $proc$libresoc.v:31668$991 assign { } { } assign { } { } assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 attribute \src "libresoc.v:31669.5-31669.29" switch \initial attribute \src "libresoc.v:31669.9-31669.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$993 1'0 case assign $1\q_int$next[0:0]$993 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$992 end connect \$9 $and$libresoc.v:31658$982_Y connect \$11 $or$libresoc.v:31659$983_Y connect \$13 $not$libresoc.v:31660$984_Y connect \$15 $or$libresoc.v:31661$985_Y connect \$1 $not$libresoc.v:31662$986_Y connect \$3 $and$libresoc.v:31663$987_Y connect \$5 $or$libresoc.v:31664$988_Y connect \$7 $not$libresoc.v:31665$989_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:31684.1-31742.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" attribute \generator "nMigen" module \alui_l$106 attribute \src "libresoc.v:31685.7-31685.20" wire $0\initial[0:0] attribute \src "libresoc.v:31730.3-31738.6" wire $0\q_int$next[0:0]$1006 attribute \src "libresoc.v:31728.3-31729.27" wire $0\q_int[0:0] attribute \src "libresoc.v:31730.3-31738.6" wire $1\q_int$next[0:0]$1007 attribute \src "libresoc.v:31709.7-31709.19" wire $1\q_int[0:0] attribute \src "libresoc.v:31720.17-31720.96" wire $and$libresoc.v:31720$996_Y attribute \src "libresoc.v:31725.17-31725.96" wire $and$libresoc.v:31725$1001_Y attribute \src "libresoc.v:31722.18-31722.94" wire $not$libresoc.v:31722$998_Y attribute \src "libresoc.v:31724.17-31724.93" wire $not$libresoc.v:31724$1000_Y attribute \src "libresoc.v:31727.17-31727.93" wire $not$libresoc.v:31727$1003_Y attribute \src "libresoc.v:31721.18-31721.99" wire $or$libresoc.v:31721$997_Y attribute \src "libresoc.v:31723.18-31723.100" wire $or$libresoc.v:31723$999_Y attribute \src "libresoc.v:31726.17-31726.98" wire $or$libresoc.v:31726$1002_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31685.7-31685.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:31720$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:31720$996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:31725$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:31725$1001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:31722$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:31722$998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:31724$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31724$1000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:31727$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31727$1003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:31721$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:31721$997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:31723$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:31723$999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:31726$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:31726$1002_Y end attribute \src "libresoc.v:31685.7-31685.20" process $proc$libresoc.v:31685$1008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:31709.7-31709.19" process $proc$libresoc.v:31709$1009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:31728.3-31729.27" process $proc$libresoc.v:31728$1004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:31730.3-31738.6" process $proc$libresoc.v:31730$1005 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 attribute \src "libresoc.v:31731.5-31731.29" switch \initial attribute \src "libresoc.v:31731.9-31731.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1007 1'0 case assign $1\q_int$next[0:0]$1007 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1006 end connect \$9 $and$libresoc.v:31720$996_Y connect \$11 $or$libresoc.v:31721$997_Y connect \$13 $not$libresoc.v:31722$998_Y connect \$15 $or$libresoc.v:31723$999_Y connect \$1 $not$libresoc.v:31724$1000_Y connect \$3 $and$libresoc.v:31725$1001_Y connect \$5 $or$libresoc.v:31726$1002_Y connect \$7 $not$libresoc.v:31727$1003_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:31746.1-31804.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" attribute \generator "nMigen" module \alui_l$124 attribute \src "libresoc.v:31747.7-31747.20" wire $0\initial[0:0] attribute \src "libresoc.v:31792.3-31800.6" wire $0\q_int$next[0:0]$1020 attribute \src "libresoc.v:31790.3-31791.27" wire $0\q_int[0:0] attribute \src "libresoc.v:31792.3-31800.6" wire $1\q_int$next[0:0]$1021 attribute \src "libresoc.v:31771.7-31771.19" wire $1\q_int[0:0] attribute \src "libresoc.v:31782.17-31782.96" wire $and$libresoc.v:31782$1010_Y attribute \src "libresoc.v:31787.17-31787.96" wire $and$libresoc.v:31787$1015_Y attribute \src "libresoc.v:31784.18-31784.94" wire $not$libresoc.v:31784$1012_Y attribute \src "libresoc.v:31786.17-31786.93" wire $not$libresoc.v:31786$1014_Y attribute \src "libresoc.v:31789.17-31789.93" wire $not$libresoc.v:31789$1017_Y attribute \src "libresoc.v:31783.18-31783.99" wire $or$libresoc.v:31783$1011_Y attribute \src "libresoc.v:31785.18-31785.100" wire $or$libresoc.v:31785$1013_Y attribute \src "libresoc.v:31788.17-31788.98" wire $or$libresoc.v:31788$1016_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31747.7-31747.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:31782$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:31782$1010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:31787$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:31787$1015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:31784$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:31784$1012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:31786$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31786$1014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:31789$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31789$1017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:31783$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:31783$1011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:31785$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:31785$1013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:31788$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:31788$1016_Y end attribute \src "libresoc.v:31747.7-31747.20" process $proc$libresoc.v:31747$1022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:31771.7-31771.19" process $proc$libresoc.v:31771$1023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:31790.3-31791.27" process $proc$libresoc.v:31790$1018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:31792.3-31800.6" process $proc$libresoc.v:31792$1019 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 attribute \src "libresoc.v:31793.5-31793.29" switch \initial attribute \src "libresoc.v:31793.9-31793.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1021 1'0 case assign $1\q_int$next[0:0]$1021 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1020 end connect \$9 $and$libresoc.v:31782$1010_Y connect \$11 $or$libresoc.v:31783$1011_Y connect \$13 $not$libresoc.v:31784$1012_Y connect \$15 $or$libresoc.v:31785$1013_Y connect \$1 $not$libresoc.v:31786$1014_Y connect \$3 $and$libresoc.v:31787$1015_Y connect \$5 $or$libresoc.v:31788$1016_Y connect \$7 $not$libresoc.v:31789$1017_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:31808.1-31866.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" attribute \generator "nMigen" module \alui_l$15 attribute \src "libresoc.v:31809.7-31809.20" wire $0\initial[0:0] attribute \src "libresoc.v:31854.3-31862.6" wire $0\q_int$next[0:0]$1034 attribute \src "libresoc.v:31852.3-31853.27" wire $0\q_int[0:0] attribute \src "libresoc.v:31854.3-31862.6" wire $1\q_int$next[0:0]$1035 attribute \src "libresoc.v:31833.7-31833.19" wire $1\q_int[0:0] attribute \src "libresoc.v:31844.17-31844.96" wire $and$libresoc.v:31844$1024_Y attribute \src "libresoc.v:31849.17-31849.96" wire $and$libresoc.v:31849$1029_Y attribute \src "libresoc.v:31846.18-31846.94" wire $not$libresoc.v:31846$1026_Y attribute \src "libresoc.v:31848.17-31848.93" wire $not$libresoc.v:31848$1028_Y attribute \src "libresoc.v:31851.17-31851.93" wire $not$libresoc.v:31851$1031_Y attribute \src "libresoc.v:31845.18-31845.99" wire $or$libresoc.v:31845$1025_Y attribute \src "libresoc.v:31847.18-31847.100" wire $or$libresoc.v:31847$1027_Y attribute \src "libresoc.v:31850.17-31850.98" wire $or$libresoc.v:31850$1030_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31809.7-31809.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:31844$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:31844$1024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:31849$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:31849$1029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:31846$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:31846$1026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:31848$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31848$1028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:31851$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31851$1031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:31845$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:31845$1025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:31847$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:31847$1027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:31850$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:31850$1030_Y end attribute \src "libresoc.v:31809.7-31809.20" process $proc$libresoc.v:31809$1036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:31833.7-31833.19" process $proc$libresoc.v:31833$1037 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:31852.3-31853.27" process $proc$libresoc.v:31852$1032 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:31854.3-31862.6" process $proc$libresoc.v:31854$1033 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 attribute \src "libresoc.v:31855.5-31855.29" switch \initial attribute \src "libresoc.v:31855.9-31855.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1035 1'0 case assign $1\q_int$next[0:0]$1035 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1034 end connect \$9 $and$libresoc.v:31844$1024_Y connect \$11 $or$libresoc.v:31845$1025_Y connect \$13 $not$libresoc.v:31846$1026_Y connect \$15 $or$libresoc.v:31847$1027_Y connect \$1 $not$libresoc.v:31848$1028_Y connect \$3 $and$libresoc.v:31849$1029_Y connect \$5 $or$libresoc.v:31850$1030_Y connect \$7 $not$libresoc.v:31851$1031_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:31870.1-31928.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" attribute \generator "nMigen" module \alui_l$28 attribute \src "libresoc.v:31871.7-31871.20" wire $0\initial[0:0] attribute \src "libresoc.v:31916.3-31924.6" wire $0\q_int$next[0:0]$1048 attribute \src "libresoc.v:31914.3-31915.27" wire $0\q_int[0:0] attribute \src "libresoc.v:31916.3-31924.6" wire $1\q_int$next[0:0]$1049 attribute \src "libresoc.v:31895.7-31895.19" wire $1\q_int[0:0] attribute \src "libresoc.v:31906.17-31906.96" wire $and$libresoc.v:31906$1038_Y attribute \src "libresoc.v:31911.17-31911.96" wire $and$libresoc.v:31911$1043_Y attribute \src "libresoc.v:31908.18-31908.94" wire $not$libresoc.v:31908$1040_Y attribute \src "libresoc.v:31910.17-31910.93" wire $not$libresoc.v:31910$1042_Y attribute \src "libresoc.v:31913.17-31913.93" wire $not$libresoc.v:31913$1045_Y attribute \src "libresoc.v:31907.18-31907.99" wire $or$libresoc.v:31907$1039_Y attribute \src "libresoc.v:31909.18-31909.100" wire $or$libresoc.v:31909$1041_Y attribute \src "libresoc.v:31912.17-31912.98" wire $or$libresoc.v:31912$1044_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31871.7-31871.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:31906$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:31906$1038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:31911$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:31911$1043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:31908$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:31908$1040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:31910$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31910$1042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:31913$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31913$1045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:31907$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:31907$1039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:31909$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:31909$1041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:31912$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:31912$1044_Y end attribute \src "libresoc.v:31871.7-31871.20" process $proc$libresoc.v:31871$1050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:31895.7-31895.19" process $proc$libresoc.v:31895$1051 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:31914.3-31915.27" process $proc$libresoc.v:31914$1046 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:31916.3-31924.6" process $proc$libresoc.v:31916$1047 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 attribute \src "libresoc.v:31917.5-31917.29" switch \initial attribute \src "libresoc.v:31917.9-31917.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1049 1'0 case assign $1\q_int$next[0:0]$1049 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1048 end connect \$9 $and$libresoc.v:31906$1038_Y connect \$11 $or$libresoc.v:31907$1039_Y connect \$13 $not$libresoc.v:31908$1040_Y connect \$15 $or$libresoc.v:31909$1041_Y connect \$1 $not$libresoc.v:31910$1042_Y connect \$3 $and$libresoc.v:31911$1043_Y connect \$5 $or$libresoc.v:31912$1044_Y connect \$7 $not$libresoc.v:31913$1045_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:31932.1-31990.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" attribute \generator "nMigen" module \alui_l$44 attribute \src "libresoc.v:31933.7-31933.20" wire $0\initial[0:0] attribute \src "libresoc.v:31978.3-31986.6" wire $0\q_int$next[0:0]$1062 attribute \src "libresoc.v:31976.3-31977.27" wire $0\q_int[0:0] attribute \src "libresoc.v:31978.3-31986.6" wire $1\q_int$next[0:0]$1063 attribute \src "libresoc.v:31957.7-31957.19" wire $1\q_int[0:0] attribute \src "libresoc.v:31968.17-31968.96" wire $and$libresoc.v:31968$1052_Y attribute \src "libresoc.v:31973.17-31973.96" wire $and$libresoc.v:31973$1057_Y attribute \src "libresoc.v:31970.18-31970.94" wire $not$libresoc.v:31970$1054_Y attribute \src "libresoc.v:31972.17-31972.93" wire $not$libresoc.v:31972$1056_Y attribute \src "libresoc.v:31975.17-31975.93" wire $not$libresoc.v:31975$1059_Y attribute \src "libresoc.v:31969.18-31969.99" wire $or$libresoc.v:31969$1053_Y attribute \src "libresoc.v:31971.18-31971.100" wire $or$libresoc.v:31971$1055_Y attribute \src "libresoc.v:31974.17-31974.98" wire $or$libresoc.v:31974$1058_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31933.7-31933.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:31968$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:31968$1052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:31973$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:31973$1057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:31970$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:31970$1054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:31972$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31972$1056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:31975$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:31975$1059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:31969$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:31969$1053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:31971$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:31971$1055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:31974$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:31974$1058_Y end attribute \src "libresoc.v:31933.7-31933.20" process $proc$libresoc.v:31933$1064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:31957.7-31957.19" process $proc$libresoc.v:31957$1065 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:31976.3-31977.27" process $proc$libresoc.v:31976$1060 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:31978.3-31986.6" process $proc$libresoc.v:31978$1061 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 attribute \src "libresoc.v:31979.5-31979.29" switch \initial attribute \src "libresoc.v:31979.9-31979.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1063 1'0 case assign $1\q_int$next[0:0]$1063 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1062 end connect \$9 $and$libresoc.v:31968$1052_Y connect \$11 $or$libresoc.v:31969$1053_Y connect \$13 $not$libresoc.v:31970$1054_Y connect \$15 $or$libresoc.v:31971$1055_Y connect \$1 $not$libresoc.v:31972$1056_Y connect \$3 $and$libresoc.v:31973$1057_Y connect \$5 $or$libresoc.v:31974$1058_Y connect \$7 $not$libresoc.v:31975$1059_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:31994.1-32052.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" attribute \generator "nMigen" module \alui_l$60 attribute \src "libresoc.v:31995.7-31995.20" wire $0\initial[0:0] attribute \src "libresoc.v:32040.3-32048.6" wire $0\q_int$next[0:0]$1076 attribute \src "libresoc.v:32038.3-32039.27" wire $0\q_int[0:0] attribute \src "libresoc.v:32040.3-32048.6" wire $1\q_int$next[0:0]$1077 attribute \src "libresoc.v:32019.7-32019.19" wire $1\q_int[0:0] attribute \src "libresoc.v:32030.17-32030.96" wire $and$libresoc.v:32030$1066_Y attribute \src "libresoc.v:32035.17-32035.96" wire $and$libresoc.v:32035$1071_Y attribute \src "libresoc.v:32032.18-32032.94" wire $not$libresoc.v:32032$1068_Y attribute \src "libresoc.v:32034.17-32034.93" wire $not$libresoc.v:32034$1070_Y attribute \src "libresoc.v:32037.17-32037.93" wire $not$libresoc.v:32037$1073_Y attribute \src "libresoc.v:32031.18-32031.99" wire $or$libresoc.v:32031$1067_Y attribute \src "libresoc.v:32033.18-32033.100" wire $or$libresoc.v:32033$1069_Y attribute \src "libresoc.v:32036.17-32036.98" wire $or$libresoc.v:32036$1072_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:31995.7-31995.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:32030$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:32030$1066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:32035$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:32035$1071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:32032$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:32032$1068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:32034$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:32034$1070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:32037$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:32037$1073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:32031$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:32031$1067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:32033$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:32033$1069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:32036$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:32036$1072_Y end attribute \src "libresoc.v:31995.7-31995.20" process $proc$libresoc.v:31995$1078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:32019.7-32019.19" process $proc$libresoc.v:32019$1079 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:32038.3-32039.27" process $proc$libresoc.v:32038$1074 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:32040.3-32048.6" process $proc$libresoc.v:32040$1075 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 attribute \src "libresoc.v:32041.5-32041.29" switch \initial attribute \src "libresoc.v:32041.9-32041.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1077 1'0 case assign $1\q_int$next[0:0]$1077 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1076 end connect \$9 $and$libresoc.v:32030$1066_Y connect \$11 $or$libresoc.v:32031$1067_Y connect \$13 $not$libresoc.v:32032$1068_Y connect \$15 $or$libresoc.v:32033$1069_Y connect \$1 $not$libresoc.v:32034$1070_Y connect \$3 $and$libresoc.v:32035$1071_Y connect \$5 $or$libresoc.v:32036$1072_Y connect \$7 $not$libresoc.v:32037$1073_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:32056.1-32114.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" attribute \generator "nMigen" module \alui_l$72 attribute \src "libresoc.v:32057.7-32057.20" wire $0\initial[0:0] attribute \src "libresoc.v:32102.3-32110.6" wire $0\q_int$next[0:0]$1090 attribute \src "libresoc.v:32100.3-32101.27" wire $0\q_int[0:0] attribute \src "libresoc.v:32102.3-32110.6" wire $1\q_int$next[0:0]$1091 attribute \src "libresoc.v:32081.7-32081.19" wire $1\q_int[0:0] attribute \src "libresoc.v:32092.17-32092.96" wire $and$libresoc.v:32092$1080_Y attribute \src "libresoc.v:32097.17-32097.96" wire $and$libresoc.v:32097$1085_Y attribute \src "libresoc.v:32094.18-32094.94" wire $not$libresoc.v:32094$1082_Y attribute \src "libresoc.v:32096.17-32096.93" wire $not$libresoc.v:32096$1084_Y attribute \src "libresoc.v:32099.17-32099.93" wire $not$libresoc.v:32099$1087_Y attribute \src "libresoc.v:32093.18-32093.99" wire $or$libresoc.v:32093$1081_Y attribute \src "libresoc.v:32095.18-32095.100" wire $or$libresoc.v:32095$1083_Y attribute \src "libresoc.v:32098.17-32098.98" wire $or$libresoc.v:32098$1086_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:32057.7-32057.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:32092$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:32092$1080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:32097$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:32097$1085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:32094$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:32094$1082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:32096$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:32096$1084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:32099$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:32099$1087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:32093$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:32093$1081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:32095$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:32095$1083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:32098$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:32098$1086_Y end attribute \src "libresoc.v:32057.7-32057.20" process $proc$libresoc.v:32057$1092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:32081.7-32081.19" process $proc$libresoc.v:32081$1093 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:32100.3-32101.27" process $proc$libresoc.v:32100$1088 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:32102.3-32110.6" process $proc$libresoc.v:32102$1089 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 attribute \src "libresoc.v:32103.5-32103.29" switch \initial attribute \src "libresoc.v:32103.9-32103.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1091 1'0 case assign $1\q_int$next[0:0]$1091 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1090 end connect \$9 $and$libresoc.v:32092$1080_Y connect \$11 $or$libresoc.v:32093$1081_Y connect \$13 $not$libresoc.v:32094$1082_Y connect \$15 $or$libresoc.v:32095$1083_Y connect \$1 $not$libresoc.v:32096$1084_Y connect \$3 $and$libresoc.v:32097$1085_Y connect \$5 $or$libresoc.v:32098$1086_Y connect \$7 $not$libresoc.v:32099$1087_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:32118.1-32176.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" attribute \generator "nMigen" module \alui_l$89 attribute \src "libresoc.v:32119.7-32119.20" wire $0\initial[0:0] attribute \src "libresoc.v:32164.3-32172.6" wire $0\q_int$next[0:0]$1104 attribute \src "libresoc.v:32162.3-32163.27" wire $0\q_int[0:0] attribute \src "libresoc.v:32164.3-32172.6" wire $1\q_int$next[0:0]$1105 attribute \src "libresoc.v:32143.7-32143.19" wire $1\q_int[0:0] attribute \src "libresoc.v:32154.17-32154.96" wire $and$libresoc.v:32154$1094_Y attribute \src "libresoc.v:32159.17-32159.96" wire $and$libresoc.v:32159$1099_Y attribute \src "libresoc.v:32156.18-32156.94" wire $not$libresoc.v:32156$1096_Y attribute \src "libresoc.v:32158.17-32158.93" wire $not$libresoc.v:32158$1098_Y attribute \src "libresoc.v:32161.17-32161.93" wire $not$libresoc.v:32161$1101_Y attribute \src "libresoc.v:32155.18-32155.99" wire $or$libresoc.v:32155$1095_Y attribute \src "libresoc.v:32157.18-32157.100" wire $or$libresoc.v:32157$1097_Y attribute \src "libresoc.v:32160.17-32160.98" wire $or$libresoc.v:32160$1100_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:32119.7-32119.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:32154$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:32154$1094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:32159$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:32159$1099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:32156$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \Y $not$libresoc.v:32156$1096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:32158$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:32158$1098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:32161$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui connect \Y $not$libresoc.v:32161$1101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:32155$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui connect \Y $or$libresoc.v:32155$1095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:32157$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int connect \Y $or$libresoc.v:32157$1097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:32160$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui connect \Y $or$libresoc.v:32160$1100_Y end attribute \src "libresoc.v:32119.7-32119.20" process $proc$libresoc.v:32119$1106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:32143.7-32143.19" process $proc$libresoc.v:32143$1107 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:32162.3-32163.27" process $proc$libresoc.v:32162$1102 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:32164.3-32172.6" process $proc$libresoc.v:32164$1103 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 attribute \src "libresoc.v:32165.5-32165.29" switch \initial attribute \src "libresoc.v:32165.9-32165.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1105 1'0 case assign $1\q_int$next[0:0]$1105 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1104 end connect \$9 $and$libresoc.v:32154$1094_Y connect \$11 $or$libresoc.v:32155$1095_Y connect \$13 $not$libresoc.v:32156$1096_Y connect \$15 $or$libresoc.v:32157$1097_Y connect \$1 $not$libresoc.v:32158$1098_Y connect \$3 $and$libresoc.v:32159$1099_Y connect \$5 $or$libresoc.v:32160$1100_Y connect \$7 $not$libresoc.v:32161$1101_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end attribute \src "libresoc.v:32180.1-33524.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" attribute \generator "nMigen" module \bpermd attribute \src "libresoc.v:32181.7-32181.20" wire $0\initial[0:0] attribute \src "libresoc.v:32358.3-33449.6" wire width 64 $0\perm[63:0] attribute \src "libresoc.v:32358.3-33449.6" wire $10\perm[4:4] attribute \src "libresoc.v:32358.3-33449.6" wire $11\perm[5:5] attribute \src "libresoc.v:32358.3-33449.6" wire $12\perm[5:5] attribute \src "libresoc.v:32358.3-33449.6" wire $13\perm[6:6] attribute \src "libresoc.v:32358.3-33449.6" wire $14\perm[6:6] attribute \src "libresoc.v:32358.3-33449.6" wire $15\perm[7:7] attribute \src "libresoc.v:32358.3-33449.6" wire $16\perm[7:7] attribute \src "libresoc.v:32358.3-33449.6" wire $1\perm[0:0] attribute \src "libresoc.v:32358.3-33449.6" wire $2\perm[0:0] attribute \src "libresoc.v:32358.3-33449.6" wire $3\perm[1:1] attribute \src "libresoc.v:32358.3-33449.6" wire $4\perm[1:1] attribute \src "libresoc.v:32358.3-33449.6" wire $5\perm[2:2] attribute \src "libresoc.v:32358.3-33449.6" wire $6\perm[2:2] attribute \src "libresoc.v:32358.3-33449.6" wire $7\perm[3:3] attribute \src "libresoc.v:32358.3-33449.6" wire $8\perm[3:3] attribute \src "libresoc.v:32358.3-33449.6" wire $9\perm[4:4] attribute \src "libresoc.v:32350.17-32350.104" wire $lt$libresoc.v:32350$1108_Y attribute \src "libresoc.v:32351.18-32351.105" wire $lt$libresoc.v:32351$1109_Y attribute \src "libresoc.v:32352.18-32352.105" wire $lt$libresoc.v:32352$1110_Y attribute \src "libresoc.v:32353.18-32353.105" wire $lt$libresoc.v:32353$1111_Y attribute \src "libresoc.v:32354.17-32354.104" wire $lt$libresoc.v:32354$1112_Y attribute \src "libresoc.v:32355.17-32355.104" wire $lt$libresoc.v:32355$1113_Y attribute \src "libresoc.v:32356.17-32356.104" wire $lt$libresoc.v:32356$1114_Y attribute \src "libresoc.v:32357.17-32357.104" wire $lt$libresoc.v:32357$1115_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_7 attribute \src "libresoc.v:32181.7-32181.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" wire width 64 \perm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" wire width 64 output 2 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" wire width 64 input 1 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" wire \rb64_9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 input 3 \rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32350$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_4 connect \B 7'1000000 connect \Y $lt$libresoc.v:32350$1108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32351$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_5 connect \B 7'1000000 connect \Y $lt$libresoc.v:32351$1109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32352$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_6 connect \B 7'1000000 connect \Y $lt$libresoc.v:32352$1110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32353$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_7 connect \B 7'1000000 connect \Y $lt$libresoc.v:32353$1111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32354$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_0 connect \B 7'1000000 connect \Y $lt$libresoc.v:32354$1112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32355$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_1 connect \B 7'1000000 connect \Y $lt$libresoc.v:32355$1113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32356$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_2 connect \B 7'1000000 connect \Y $lt$libresoc.v:32356$1114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" cell $lt $lt$libresoc.v:32357$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \idx_3 connect \B 7'1000000 connect \Y $lt$libresoc.v:32357$1115_Y end attribute \src "libresoc.v:32181.7-32181.20" process $proc$libresoc.v:32181$1117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:32358.3-33449.6" process $proc$libresoc.v:32358$1116 assign { } { } assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 assign $0\perm[63:0] [0] $1\perm[0:0] assign $0\perm[63:0] [1] $3\perm[1:1] assign $0\perm[63:0] [2] $5\perm[2:2] assign $0\perm[63:0] [3] $7\perm[3:3] assign $0\perm[63:0] [4] $9\perm[4:4] assign $0\perm[63:0] [5] $11\perm[5:5] assign $0\perm[63:0] [6] $13\perm[6:6] assign $0\perm[63:0] [7] $15\perm[7:7] attribute \src "libresoc.v:32359.5-32359.29" switch \initial attribute \src "libresoc.v:32359.9-32359.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\perm[0:0] $2\perm[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $2\perm[0:0] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $2\perm[0:0] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $2\perm[0:0] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $2\perm[0:0] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $2\perm[0:0] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $2\perm[0:0] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $2\perm[0:0] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $2\perm[0:0] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $2\perm[0:0] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $2\perm[0:0] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $2\perm[0:0] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $2\perm[0:0] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $2\perm[0:0] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $2\perm[0:0] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $2\perm[0:0] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $2\perm[0:0] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $2\perm[0:0] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $2\perm[0:0] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $2\perm[0:0] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $2\perm[0:0] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $2\perm[0:0] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $2\perm[0:0] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $2\perm[0:0] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $2\perm[0:0] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $2\perm[0:0] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $2\perm[0:0] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $2\perm[0:0] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $2\perm[0:0] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $2\perm[0:0] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $2\perm[0:0] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $2\perm[0:0] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $2\perm[0:0] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $2\perm[0:0] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $2\perm[0:0] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $2\perm[0:0] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $2\perm[0:0] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $2\perm[0:0] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $2\perm[0:0] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $2\perm[0:0] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $2\perm[0:0] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $2\perm[0:0] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $2\perm[0:0] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $2\perm[0:0] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $2\perm[0:0] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $2\perm[0:0] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $2\perm[0:0] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $2\perm[0:0] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $2\perm[0:0] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $2\perm[0:0] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $2\perm[0:0] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $2\perm[0:0] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $2\perm[0:0] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $2\perm[0:0] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $2\perm[0:0] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $2\perm[0:0] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $2\perm[0:0] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $2\perm[0:0] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $2\perm[0:0] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $2\perm[0:0] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $2\perm[0:0] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $2\perm[0:0] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $2\perm[0:0] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $2\perm[0:0] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $2\perm[0:0] \rb64_63 case assign $2\perm[0:0] 1'0 end case assign $1\perm[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\perm[1:1] $4\perm[1:1] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $4\perm[1:1] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $4\perm[1:1] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $4\perm[1:1] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $4\perm[1:1] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $4\perm[1:1] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $4\perm[1:1] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $4\perm[1:1] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $4\perm[1:1] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $4\perm[1:1] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $4\perm[1:1] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $4\perm[1:1] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $4\perm[1:1] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $4\perm[1:1] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $4\perm[1:1] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $4\perm[1:1] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $4\perm[1:1] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $4\perm[1:1] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $4\perm[1:1] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $4\perm[1:1] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $4\perm[1:1] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $4\perm[1:1] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $4\perm[1:1] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $4\perm[1:1] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $4\perm[1:1] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $4\perm[1:1] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $4\perm[1:1] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $4\perm[1:1] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $4\perm[1:1] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $4\perm[1:1] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $4\perm[1:1] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $4\perm[1:1] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $4\perm[1:1] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $4\perm[1:1] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $4\perm[1:1] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $4\perm[1:1] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $4\perm[1:1] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $4\perm[1:1] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $4\perm[1:1] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $4\perm[1:1] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $4\perm[1:1] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $4\perm[1:1] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $4\perm[1:1] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $4\perm[1:1] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $4\perm[1:1] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $4\perm[1:1] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $4\perm[1:1] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $4\perm[1:1] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $4\perm[1:1] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $4\perm[1:1] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $4\perm[1:1] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $4\perm[1:1] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $4\perm[1:1] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $4\perm[1:1] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $4\perm[1:1] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $4\perm[1:1] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $4\perm[1:1] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $4\perm[1:1] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $4\perm[1:1] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $4\perm[1:1] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $4\perm[1:1] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $4\perm[1:1] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $4\perm[1:1] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $4\perm[1:1] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $4\perm[1:1] \rb64_63 case assign $4\perm[1:1] 1'0 end case assign $3\perm[1:1] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\perm[2:2] $6\perm[2:2] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $6\perm[2:2] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $6\perm[2:2] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $6\perm[2:2] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $6\perm[2:2] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $6\perm[2:2] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $6\perm[2:2] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $6\perm[2:2] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $6\perm[2:2] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $6\perm[2:2] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $6\perm[2:2] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $6\perm[2:2] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $6\perm[2:2] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $6\perm[2:2] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $6\perm[2:2] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $6\perm[2:2] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $6\perm[2:2] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $6\perm[2:2] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $6\perm[2:2] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $6\perm[2:2] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $6\perm[2:2] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $6\perm[2:2] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $6\perm[2:2] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $6\perm[2:2] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $6\perm[2:2] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $6\perm[2:2] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $6\perm[2:2] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $6\perm[2:2] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $6\perm[2:2] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $6\perm[2:2] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $6\perm[2:2] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $6\perm[2:2] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $6\perm[2:2] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $6\perm[2:2] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $6\perm[2:2] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $6\perm[2:2] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $6\perm[2:2] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $6\perm[2:2] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $6\perm[2:2] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $6\perm[2:2] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $6\perm[2:2] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $6\perm[2:2] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $6\perm[2:2] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $6\perm[2:2] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $6\perm[2:2] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $6\perm[2:2] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $6\perm[2:2] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $6\perm[2:2] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $6\perm[2:2] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $6\perm[2:2] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $6\perm[2:2] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $6\perm[2:2] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $6\perm[2:2] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $6\perm[2:2] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $6\perm[2:2] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $6\perm[2:2] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $6\perm[2:2] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $6\perm[2:2] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $6\perm[2:2] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $6\perm[2:2] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $6\perm[2:2] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $6\perm[2:2] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $6\perm[2:2] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $6\perm[2:2] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $6\perm[2:2] \rb64_63 case assign $6\perm[2:2] 1'0 end case assign $5\perm[2:2] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\perm[3:3] $8\perm[3:3] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $8\perm[3:3] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $8\perm[3:3] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $8\perm[3:3] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $8\perm[3:3] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $8\perm[3:3] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $8\perm[3:3] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $8\perm[3:3] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $8\perm[3:3] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $8\perm[3:3] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $8\perm[3:3] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $8\perm[3:3] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $8\perm[3:3] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $8\perm[3:3] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $8\perm[3:3] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $8\perm[3:3] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $8\perm[3:3] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $8\perm[3:3] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $8\perm[3:3] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $8\perm[3:3] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $8\perm[3:3] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $8\perm[3:3] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $8\perm[3:3] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $8\perm[3:3] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $8\perm[3:3] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $8\perm[3:3] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $8\perm[3:3] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $8\perm[3:3] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $8\perm[3:3] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $8\perm[3:3] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $8\perm[3:3] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $8\perm[3:3] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $8\perm[3:3] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $8\perm[3:3] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $8\perm[3:3] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $8\perm[3:3] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $8\perm[3:3] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $8\perm[3:3] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $8\perm[3:3] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $8\perm[3:3] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $8\perm[3:3] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $8\perm[3:3] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $8\perm[3:3] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $8\perm[3:3] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $8\perm[3:3] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $8\perm[3:3] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $8\perm[3:3] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $8\perm[3:3] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $8\perm[3:3] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $8\perm[3:3] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $8\perm[3:3] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $8\perm[3:3] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $8\perm[3:3] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $8\perm[3:3] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $8\perm[3:3] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $8\perm[3:3] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $8\perm[3:3] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $8\perm[3:3] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $8\perm[3:3] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $8\perm[3:3] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $8\perm[3:3] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $8\perm[3:3] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $8\perm[3:3] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $8\perm[3:3] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $8\perm[3:3] \rb64_63 case assign $8\perm[3:3] 1'0 end case assign $7\perm[3:3] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\perm[4:4] $10\perm[4:4] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $10\perm[4:4] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $10\perm[4:4] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $10\perm[4:4] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $10\perm[4:4] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $10\perm[4:4] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $10\perm[4:4] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $10\perm[4:4] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $10\perm[4:4] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $10\perm[4:4] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $10\perm[4:4] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $10\perm[4:4] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $10\perm[4:4] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $10\perm[4:4] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $10\perm[4:4] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $10\perm[4:4] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $10\perm[4:4] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $10\perm[4:4] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $10\perm[4:4] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $10\perm[4:4] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $10\perm[4:4] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $10\perm[4:4] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $10\perm[4:4] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $10\perm[4:4] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $10\perm[4:4] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $10\perm[4:4] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $10\perm[4:4] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $10\perm[4:4] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $10\perm[4:4] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $10\perm[4:4] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $10\perm[4:4] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $10\perm[4:4] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $10\perm[4:4] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $10\perm[4:4] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $10\perm[4:4] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $10\perm[4:4] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $10\perm[4:4] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $10\perm[4:4] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $10\perm[4:4] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $10\perm[4:4] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $10\perm[4:4] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $10\perm[4:4] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $10\perm[4:4] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $10\perm[4:4] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $10\perm[4:4] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $10\perm[4:4] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $10\perm[4:4] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $10\perm[4:4] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $10\perm[4:4] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $10\perm[4:4] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $10\perm[4:4] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $10\perm[4:4] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $10\perm[4:4] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $10\perm[4:4] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $10\perm[4:4] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $10\perm[4:4] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $10\perm[4:4] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $10\perm[4:4] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $10\perm[4:4] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $10\perm[4:4] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $10\perm[4:4] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $10\perm[4:4] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $10\perm[4:4] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $10\perm[4:4] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $10\perm[4:4] \rb64_63 case assign $10\perm[4:4] 1'0 end case assign $9\perm[4:4] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $11\perm[5:5] $12\perm[5:5] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $12\perm[5:5] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $12\perm[5:5] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $12\perm[5:5] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $12\perm[5:5] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $12\perm[5:5] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $12\perm[5:5] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $12\perm[5:5] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $12\perm[5:5] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $12\perm[5:5] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $12\perm[5:5] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $12\perm[5:5] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $12\perm[5:5] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $12\perm[5:5] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $12\perm[5:5] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $12\perm[5:5] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $12\perm[5:5] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $12\perm[5:5] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $12\perm[5:5] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $12\perm[5:5] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $12\perm[5:5] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $12\perm[5:5] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $12\perm[5:5] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $12\perm[5:5] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $12\perm[5:5] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $12\perm[5:5] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $12\perm[5:5] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $12\perm[5:5] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $12\perm[5:5] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $12\perm[5:5] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $12\perm[5:5] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $12\perm[5:5] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $12\perm[5:5] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $12\perm[5:5] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $12\perm[5:5] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $12\perm[5:5] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $12\perm[5:5] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $12\perm[5:5] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $12\perm[5:5] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $12\perm[5:5] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $12\perm[5:5] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $12\perm[5:5] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $12\perm[5:5] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $12\perm[5:5] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $12\perm[5:5] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $12\perm[5:5] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $12\perm[5:5] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $12\perm[5:5] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $12\perm[5:5] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $12\perm[5:5] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $12\perm[5:5] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $12\perm[5:5] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $12\perm[5:5] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $12\perm[5:5] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $12\perm[5:5] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $12\perm[5:5] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $12\perm[5:5] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $12\perm[5:5] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $12\perm[5:5] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $12\perm[5:5] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $12\perm[5:5] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $12\perm[5:5] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $12\perm[5:5] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $12\perm[5:5] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $12\perm[5:5] \rb64_63 case assign $12\perm[5:5] 1'0 end case assign $11\perm[5:5] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $13\perm[6:6] $14\perm[6:6] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $14\perm[6:6] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $14\perm[6:6] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $14\perm[6:6] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $14\perm[6:6] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $14\perm[6:6] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $14\perm[6:6] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $14\perm[6:6] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $14\perm[6:6] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $14\perm[6:6] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $14\perm[6:6] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $14\perm[6:6] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $14\perm[6:6] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $14\perm[6:6] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $14\perm[6:6] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $14\perm[6:6] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $14\perm[6:6] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $14\perm[6:6] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $14\perm[6:6] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $14\perm[6:6] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $14\perm[6:6] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $14\perm[6:6] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $14\perm[6:6] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $14\perm[6:6] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $14\perm[6:6] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $14\perm[6:6] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $14\perm[6:6] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $14\perm[6:6] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $14\perm[6:6] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $14\perm[6:6] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $14\perm[6:6] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $14\perm[6:6] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $14\perm[6:6] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $14\perm[6:6] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $14\perm[6:6] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $14\perm[6:6] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $14\perm[6:6] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $14\perm[6:6] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $14\perm[6:6] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $14\perm[6:6] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $14\perm[6:6] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $14\perm[6:6] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $14\perm[6:6] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $14\perm[6:6] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $14\perm[6:6] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $14\perm[6:6] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $14\perm[6:6] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $14\perm[6:6] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $14\perm[6:6] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $14\perm[6:6] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $14\perm[6:6] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $14\perm[6:6] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $14\perm[6:6] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $14\perm[6:6] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $14\perm[6:6] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $14\perm[6:6] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $14\perm[6:6] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $14\perm[6:6] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $14\perm[6:6] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $14\perm[6:6] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $14\perm[6:6] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $14\perm[6:6] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $14\perm[6:6] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $14\perm[6:6] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $14\perm[6:6] \rb64_63 case assign $14\perm[6:6] 1'0 end case assign $13\perm[6:6] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $15\perm[7:7] $16\perm[7:7] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" switch \idx_7 attribute \src "libresoc.v:0.0-0.0" case 8'00000000 assign { } { } assign $16\perm[7:7] \rb64_0 attribute \src "libresoc.v:0.0-0.0" case 8'00000001 assign { } { } assign $16\perm[7:7] \rb64_1 attribute \src "libresoc.v:0.0-0.0" case 8'00000010 assign { } { } assign $16\perm[7:7] \rb64_2 attribute \src "libresoc.v:0.0-0.0" case 8'00000011 assign { } { } assign $16\perm[7:7] \rb64_3 attribute \src "libresoc.v:0.0-0.0" case 8'00000100 assign { } { } assign $16\perm[7:7] \rb64_4 attribute \src "libresoc.v:0.0-0.0" case 8'00000101 assign { } { } assign $16\perm[7:7] \rb64_5 attribute \src "libresoc.v:0.0-0.0" case 8'00000110 assign { } { } assign $16\perm[7:7] \rb64_6 attribute \src "libresoc.v:0.0-0.0" case 8'00000111 assign { } { } assign $16\perm[7:7] \rb64_7 attribute \src "libresoc.v:0.0-0.0" case 8'00001000 assign { } { } assign $16\perm[7:7] \rb64_8 attribute \src "libresoc.v:0.0-0.0" case 8'00001001 assign { } { } assign $16\perm[7:7] \rb64_9 attribute \src "libresoc.v:0.0-0.0" case 8'00001010 assign { } { } assign $16\perm[7:7] \rb64_10 attribute \src "libresoc.v:0.0-0.0" case 8'00001011 assign { } { } assign $16\perm[7:7] \rb64_11 attribute \src "libresoc.v:0.0-0.0" case 8'00001100 assign { } { } assign $16\perm[7:7] \rb64_12 attribute \src "libresoc.v:0.0-0.0" case 8'00001101 assign { } { } assign $16\perm[7:7] \rb64_13 attribute \src "libresoc.v:0.0-0.0" case 8'00001110 assign { } { } assign $16\perm[7:7] \rb64_14 attribute \src "libresoc.v:0.0-0.0" case 8'00001111 assign { } { } assign $16\perm[7:7] \rb64_15 attribute \src "libresoc.v:0.0-0.0" case 8'00010000 assign { } { } assign $16\perm[7:7] \rb64_16 attribute \src "libresoc.v:0.0-0.0" case 8'00010001 assign { } { } assign $16\perm[7:7] \rb64_17 attribute \src "libresoc.v:0.0-0.0" case 8'00010010 assign { } { } assign $16\perm[7:7] \rb64_18 attribute \src "libresoc.v:0.0-0.0" case 8'00010011 assign { } { } assign $16\perm[7:7] \rb64_19 attribute \src "libresoc.v:0.0-0.0" case 8'00010100 assign { } { } assign $16\perm[7:7] \rb64_20 attribute \src "libresoc.v:0.0-0.0" case 8'00010101 assign { } { } assign $16\perm[7:7] \rb64_21 attribute \src "libresoc.v:0.0-0.0" case 8'00010110 assign { } { } assign $16\perm[7:7] \rb64_22 attribute \src "libresoc.v:0.0-0.0" case 8'00010111 assign { } { } assign $16\perm[7:7] \rb64_23 attribute \src "libresoc.v:0.0-0.0" case 8'00011000 assign { } { } assign $16\perm[7:7] \rb64_24 attribute \src "libresoc.v:0.0-0.0" case 8'00011001 assign { } { } assign $16\perm[7:7] \rb64_25 attribute \src "libresoc.v:0.0-0.0" case 8'00011010 assign { } { } assign $16\perm[7:7] \rb64_26 attribute \src "libresoc.v:0.0-0.0" case 8'00011011 assign { } { } assign $16\perm[7:7] \rb64_27 attribute \src "libresoc.v:0.0-0.0" case 8'00011100 assign { } { } assign $16\perm[7:7] \rb64_28 attribute \src "libresoc.v:0.0-0.0" case 8'00011101 assign { } { } assign $16\perm[7:7] \rb64_29 attribute \src "libresoc.v:0.0-0.0" case 8'00011110 assign { } { } assign $16\perm[7:7] \rb64_30 attribute \src "libresoc.v:0.0-0.0" case 8'00011111 assign { } { } assign $16\perm[7:7] \rb64_31 attribute \src "libresoc.v:0.0-0.0" case 8'00100000 assign { } { } assign $16\perm[7:7] \rb64_32 attribute \src "libresoc.v:0.0-0.0" case 8'00100001 assign { } { } assign $16\perm[7:7] \rb64_33 attribute \src "libresoc.v:0.0-0.0" case 8'00100010 assign { } { } assign $16\perm[7:7] \rb64_34 attribute \src "libresoc.v:0.0-0.0" case 8'00100011 assign { } { } assign $16\perm[7:7] \rb64_35 attribute \src "libresoc.v:0.0-0.0" case 8'00100100 assign { } { } assign $16\perm[7:7] \rb64_36 attribute \src "libresoc.v:0.0-0.0" case 8'00100101 assign { } { } assign $16\perm[7:7] \rb64_37 attribute \src "libresoc.v:0.0-0.0" case 8'00100110 assign { } { } assign $16\perm[7:7] \rb64_38 attribute \src "libresoc.v:0.0-0.0" case 8'00100111 assign { } { } assign $16\perm[7:7] \rb64_39 attribute \src "libresoc.v:0.0-0.0" case 8'00101000 assign { } { } assign $16\perm[7:7] \rb64_40 attribute \src "libresoc.v:0.0-0.0" case 8'00101001 assign { } { } assign $16\perm[7:7] \rb64_41 attribute \src "libresoc.v:0.0-0.0" case 8'00101010 assign { } { } assign $16\perm[7:7] \rb64_42 attribute \src "libresoc.v:0.0-0.0" case 8'00101011 assign { } { } assign $16\perm[7:7] \rb64_43 attribute \src "libresoc.v:0.0-0.0" case 8'00101100 assign { } { } assign $16\perm[7:7] \rb64_44 attribute \src "libresoc.v:0.0-0.0" case 8'00101101 assign { } { } assign $16\perm[7:7] \rb64_45 attribute \src "libresoc.v:0.0-0.0" case 8'00101110 assign { } { } assign $16\perm[7:7] \rb64_46 attribute \src "libresoc.v:0.0-0.0" case 8'00101111 assign { } { } assign $16\perm[7:7] \rb64_47 attribute \src "libresoc.v:0.0-0.0" case 8'00110000 assign { } { } assign $16\perm[7:7] \rb64_48 attribute \src "libresoc.v:0.0-0.0" case 8'00110001 assign { } { } assign $16\perm[7:7] \rb64_49 attribute \src "libresoc.v:0.0-0.0" case 8'00110010 assign { } { } assign $16\perm[7:7] \rb64_50 attribute \src "libresoc.v:0.0-0.0" case 8'00110011 assign { } { } assign $16\perm[7:7] \rb64_51 attribute \src "libresoc.v:0.0-0.0" case 8'00110100 assign { } { } assign $16\perm[7:7] \rb64_52 attribute \src "libresoc.v:0.0-0.0" case 8'00110101 assign { } { } assign $16\perm[7:7] \rb64_53 attribute \src "libresoc.v:0.0-0.0" case 8'00110110 assign { } { } assign $16\perm[7:7] \rb64_54 attribute \src "libresoc.v:0.0-0.0" case 8'00110111 assign { } { } assign $16\perm[7:7] \rb64_55 attribute \src "libresoc.v:0.0-0.0" case 8'00111000 assign { } { } assign $16\perm[7:7] \rb64_56 attribute \src "libresoc.v:0.0-0.0" case 8'00111001 assign { } { } assign $16\perm[7:7] \rb64_57 attribute \src "libresoc.v:0.0-0.0" case 8'00111010 assign { } { } assign $16\perm[7:7] \rb64_58 attribute \src "libresoc.v:0.0-0.0" case 8'00111011 assign { } { } assign $16\perm[7:7] \rb64_59 attribute \src "libresoc.v:0.0-0.0" case 8'00111100 assign { } { } assign $16\perm[7:7] \rb64_60 attribute \src "libresoc.v:0.0-0.0" case 8'00111101 assign { } { } assign $16\perm[7:7] \rb64_61 attribute \src "libresoc.v:0.0-0.0" case 8'00111110 assign { } { } assign $16\perm[7:7] \rb64_62 attribute \src "libresoc.v:0.0-0.0" case 8'-------- assign { } { } assign $16\perm[7:7] \rb64_63 case assign $16\perm[7:7] 1'0 end case assign $15\perm[7:7] 1'0 end sync always update \perm $0\perm[63:0] end connect \$9 $lt$libresoc.v:32350$1108_Y connect \$11 $lt$libresoc.v:32351$1109_Y connect \$13 $lt$libresoc.v:32352$1110_Y connect \$15 $lt$libresoc.v:32353$1111_Y connect \$1 $lt$libresoc.v:32354$1112_Y connect \$3 $lt$libresoc.v:32355$1113_Y connect \$5 $lt$libresoc.v:32356$1114_Y connect \$7 $lt$libresoc.v:32357$1115_Y connect \ra [7:0] \perm [7:0] connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 connect \idx_7 \rs [63:56] connect \idx_6 \rs [55:48] connect \idx_5 \rs [47:40] connect \idx_4 \rs [39:32] connect \idx_3 \rs [31:24] connect \idx_2 \rs [23:16] connect \idx_1 \rs [15:8] connect \idx_0 \rs [7:0] connect \rb64_63 \rb [0] connect \rb64_62 \rb [1] connect \rb64_61 \rb [2] connect \rb64_60 \rb [3] connect \rb64_59 \rb [4] connect \rb64_58 \rb [5] connect \rb64_57 \rb [6] connect \rb64_56 \rb [7] connect \rb64_55 \rb [8] connect \rb64_54 \rb [9] connect \rb64_53 \rb [10] connect \rb64_52 \rb [11] connect \rb64_51 \rb [12] connect \rb64_50 \rb [13] connect \rb64_49 \rb [14] connect \rb64_48 \rb [15] connect \rb64_47 \rb [16] connect \rb64_46 \rb [17] connect \rb64_45 \rb [18] connect \rb64_44 \rb [19] connect \rb64_43 \rb [20] connect \rb64_42 \rb [21] connect \rb64_41 \rb [22] connect \rb64_40 \rb [23] connect \rb64_39 \rb [24] connect \rb64_38 \rb [25] connect \rb64_37 \rb [26] connect \rb64_36 \rb [27] connect \rb64_35 \rb [28] connect \rb64_34 \rb [29] connect \rb64_33 \rb [30] connect \rb64_32 \rb [31] connect \rb64_31 \rb [32] connect \rb64_30 \rb [33] connect \rb64_29 \rb [34] connect \rb64_28 \rb [35] connect \rb64_27 \rb [36] connect \rb64_26 \rb [37] connect \rb64_25 \rb [38] connect \rb64_24 \rb [39] connect \rb64_23 \rb [40] connect \rb64_22 \rb [41] connect \rb64_21 \rb [42] connect \rb64_20 \rb [43] connect \rb64_19 \rb [44] connect \rb64_18 \rb [45] connect \rb64_17 \rb [46] connect \rb64_16 \rb [47] connect \rb64_15 \rb [48] connect \rb64_14 \rb [49] connect \rb64_13 \rb [50] connect \rb64_12 \rb [51] connect \rb64_11 \rb [52] connect \rb64_10 \rb [53] connect \rb64_9 \rb [54] connect \rb64_8 \rb [55] connect \rb64_7 \rb [56] connect \rb64_6 \rb [57] connect \rb64_5 \rb [58] connect \rb64_4 \rb [59] connect \rb64_3 \rb [60] connect \rb64_2 \rb [61] connect \rb64_1 \rb [62] connect \rb64_0 \rb [63] end attribute \src "libresoc.v:33528.1-34583.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" attribute \generator "nMigen" module \branch0 attribute \src "libresoc.v:34200.3-34201.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 attribute \src "libresoc.v:34160.3-34161.61" wire width 64 $0\alu_branch0_br_op__cia[63:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 14 $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 attribute \src "libresoc.v:34164.3-34165.69" wire width 14 $0\alu_branch0_br_op__fn_unit[13:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 attribute \src "libresoc.v:34168.3-34169.83" wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 attribute \src "libresoc.v:34170.3-34171.79" wire $0\alu_branch0_br_op__imm_data__ok[0:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 attribute \src "libresoc.v:34166.3-34167.63" wire width 32 $0\alu_branch0_br_op__insn[31:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 attribute \src "libresoc.v:34162.3-34163.73" wire width 7 $0\alu_branch0_br_op__insn_type[6:0] attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 attribute \src "libresoc.v:34174.3-34175.71" wire $0\alu_branch0_br_op__is_32bit[0:0] attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__lk$next[0:0]$1246 attribute \src "libresoc.v:34172.3-34173.59" wire $0\alu_branch0_br_op__lk[0:0] attribute \src "libresoc.v:34198.3-34199.43" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:34505.3-34513.6" wire $0\alu_l_r_alu$next[0:0]$1294 attribute \src "libresoc.v:34138.3-34139.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:34496.3-34504.6" wire $0\alui_l_r_alui$next[0:0]$1291 attribute \src "libresoc.v:34140.3-34141.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $0\data_r0__fast1$next[63:0]$1258 attribute \src "libresoc.v:34156.3-34157.45" wire width 64 $0\data_r0__fast1[63:0] attribute \src "libresoc.v:34400.3-34421.6" wire $0\data_r0__fast1_ok$next[0:0]$1259 attribute \src "libresoc.v:34158.3-34159.51" wire $0\data_r0__fast1_ok[0:0] attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $0\data_r1__fast2$next[63:0]$1266 attribute \src "libresoc.v:34152.3-34153.45" wire width 64 $0\data_r1__fast2[63:0] attribute \src "libresoc.v:34422.3-34443.6" wire $0\data_r1__fast2_ok$next[0:0]$1267 attribute \src "libresoc.v:34154.3-34155.51" wire $0\data_r1__fast2_ok[0:0] attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $0\data_r2__nia$next[63:0]$1274 attribute \src "libresoc.v:34148.3-34149.41" wire width 64 $0\data_r2__nia[63:0] attribute \src "libresoc.v:34444.3-34465.6" wire $0\data_r2__nia_ok$next[0:0]$1275 attribute \src "libresoc.v:34150.3-34151.47" wire $0\data_r2__nia_ok[0:0] attribute \src "libresoc.v:34514.3-34523.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:34524.3-34533.6" wire width 64 $0\dest2_o[63:0] attribute \src "libresoc.v:34534.3-34543.6" wire width 64 $0\dest3_o[63:0] attribute \src "libresoc.v:33529.7-33529.20" wire $0\initial[0:0] attribute \src "libresoc.v:34330.3-34338.6" wire $0\opc_l_r_opc$next[0:0]$1224 attribute \src "libresoc.v:34184.3-34185.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:34321.3-34329.6" wire $0\opc_l_s_opc$next[0:0]$1221 attribute \src "libresoc.v:34186.3-34187.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:34544.3-34552.6" wire width 3 $0\prev_wr_go$next[2:0]$1300 attribute \src "libresoc.v:34196.3-34197.37" wire width 3 $0\prev_wr_go[2:0] attribute \src "libresoc.v:34275.3-34284.6" wire $0\req_done[0:0] attribute \src "libresoc.v:34366.3-34374.6" wire width 3 $0\req_l_r_req$next[2:0]$1236 attribute \src "libresoc.v:34176.3-34177.39" wire width 3 $0\req_l_r_req[2:0] attribute \src "libresoc.v:34357.3-34365.6" wire width 3 $0\req_l_s_req$next[2:0]$1233 attribute \src "libresoc.v:34178.3-34179.39" wire width 3 $0\req_l_s_req[2:0] attribute \src "libresoc.v:34294.3-34302.6" wire $0\rok_l_r_rdok$next[0:0]$1212 attribute \src "libresoc.v:34192.3-34193.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:34285.3-34293.6" wire $0\rok_l_s_rdok$next[0:0]$1209 attribute \src "libresoc.v:34194.3-34195.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:34312.3-34320.6" wire $0\rst_l_r_rst$next[0:0]$1218 attribute \src "libresoc.v:34188.3-34189.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:34303.3-34311.6" wire $0\rst_l_s_rst$next[0:0]$1215 attribute \src "libresoc.v:34190.3-34191.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:34348.3-34356.6" wire width 3 $0\src_l_r_src$next[2:0]$1230 attribute \src "libresoc.v:34180.3-34181.39" wire width 3 $0\src_l_r_src[2:0] attribute \src "libresoc.v:34339.3-34347.6" wire width 3 $0\src_l_s_src$next[2:0]$1227 attribute \src "libresoc.v:34182.3-34183.39" wire width 3 $0\src_l_s_src[2:0] attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $0\src_r0$next[63:0]$1282 attribute \src "libresoc.v:34146.3-34147.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $0\src_r1$next[63:0]$1285 attribute \src "libresoc.v:34144.3-34145.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:34486.3-34495.6" wire width 4 $0\src_r2$next[3:0]$1288 attribute \src "libresoc.v:34142.3-34143.29" wire width 4 $0\src_r2[3:0] attribute \src "libresoc.v:33647.7-33647.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 attribute \src "libresoc.v:33655.14-33655.59" wire width 64 $1\alu_branch0_br_op__cia[63:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 14 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 attribute \src "libresoc.v:33674.14-33674.51" wire width 14 $1\alu_branch0_br_op__fn_unit[13:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 attribute \src "libresoc.v:33678.14-33678.70" wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 attribute \src "libresoc.v:33682.7-33682.45" wire $1\alu_branch0_br_op__imm_data__ok[0:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 attribute \src "libresoc.v:33686.14-33686.45" wire width 32 $1\alu_branch0_br_op__insn[31:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 attribute \src "libresoc.v:33765.13-33765.49" wire width 7 $1\alu_branch0_br_op__insn_type[6:0] attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 attribute \src "libresoc.v:33769.7-33769.41" wire $1\alu_branch0_br_op__is_32bit[0:0] attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__lk$next[0:0]$1254 attribute \src "libresoc.v:33773.7-33773.35" wire $1\alu_branch0_br_op__lk[0:0] attribute \src "libresoc.v:33799.7-33799.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:34505.3-34513.6" wire $1\alu_l_r_alu$next[0:0]$1295 attribute \src "libresoc.v:33807.7-33807.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:34496.3-34504.6" wire $1\alui_l_r_alui$next[0:0]$1292 attribute \src "libresoc.v:33819.7-33819.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $1\data_r0__fast1$next[63:0]$1260 attribute \src "libresoc.v:33851.14-33851.51" wire width 64 $1\data_r0__fast1[63:0] attribute \src "libresoc.v:34400.3-34421.6" wire $1\data_r0__fast1_ok$next[0:0]$1261 attribute \src "libresoc.v:33855.7-33855.31" wire $1\data_r0__fast1_ok[0:0] attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $1\data_r1__fast2$next[63:0]$1268 attribute \src "libresoc.v:33859.14-33859.51" wire width 64 $1\data_r1__fast2[63:0] attribute \src "libresoc.v:34422.3-34443.6" wire $1\data_r1__fast2_ok$next[0:0]$1269 attribute \src "libresoc.v:33863.7-33863.31" wire $1\data_r1__fast2_ok[0:0] attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $1\data_r2__nia$next[63:0]$1276 attribute \src "libresoc.v:33867.14-33867.49" wire width 64 $1\data_r2__nia[63:0] attribute \src "libresoc.v:34444.3-34465.6" wire $1\data_r2__nia_ok$next[0:0]$1277 attribute \src "libresoc.v:33871.7-33871.29" wire $1\data_r2__nia_ok[0:0] attribute \src "libresoc.v:34514.3-34523.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:34524.3-34533.6" wire width 64 $1\dest2_o[63:0] attribute \src "libresoc.v:34534.3-34543.6" wire width 64 $1\dest3_o[63:0] attribute \src "libresoc.v:34330.3-34338.6" wire $1\opc_l_r_opc$next[0:0]$1225 attribute \src "libresoc.v:33892.7-33892.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:34321.3-34329.6" wire $1\opc_l_s_opc$next[0:0]$1222 attribute \src "libresoc.v:33896.7-33896.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:34544.3-34552.6" wire width 3 $1\prev_wr_go$next[2:0]$1301 attribute \src "libresoc.v:34006.13-34006.30" wire width 3 $1\prev_wr_go[2:0] attribute \src "libresoc.v:34275.3-34284.6" wire $1\req_done[0:0] attribute \src "libresoc.v:34366.3-34374.6" wire width 3 $1\req_l_r_req$next[2:0]$1237 attribute \src "libresoc.v:34014.13-34014.31" wire width 3 $1\req_l_r_req[2:0] attribute \src "libresoc.v:34357.3-34365.6" wire width 3 $1\req_l_s_req$next[2:0]$1234 attribute \src "libresoc.v:34018.13-34018.31" wire width 3 $1\req_l_s_req[2:0] attribute \src "libresoc.v:34294.3-34302.6" wire $1\rok_l_r_rdok$next[0:0]$1213 attribute \src "libresoc.v:34030.7-34030.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:34285.3-34293.6" wire $1\rok_l_s_rdok$next[0:0]$1210 attribute \src "libresoc.v:34034.7-34034.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:34312.3-34320.6" wire $1\rst_l_r_rst$next[0:0]$1219 attribute \src "libresoc.v:34038.7-34038.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:34303.3-34311.6" wire $1\rst_l_s_rst$next[0:0]$1216 attribute \src "libresoc.v:34042.7-34042.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:34348.3-34356.6" wire width 3 $1\src_l_r_src$next[2:0]$1231 attribute \src "libresoc.v:34056.13-34056.31" wire width 3 $1\src_l_r_src[2:0] attribute \src "libresoc.v:34339.3-34347.6" wire width 3 $1\src_l_s_src$next[2:0]$1228 attribute \src "libresoc.v:34060.13-34060.31" wire width 3 $1\src_l_s_src[2:0] attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $1\src_r0$next[63:0]$1283 attribute \src "libresoc.v:34066.14-34066.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $1\src_r1$next[63:0]$1286 attribute \src "libresoc.v:34070.14-34070.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:34486.3-34495.6" wire width 4 $1\src_r2$next[3:0]$1289 attribute \src "libresoc.v:34074.13-34074.26" wire width 4 $1\src_r2[3:0] attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 attribute \src "libresoc.v:34375.3-34399.6" wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $2\data_r0__fast1$next[63:0]$1262 attribute \src "libresoc.v:34400.3-34421.6" wire $2\data_r0__fast1_ok$next[0:0]$1263 attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $2\data_r1__fast2$next[63:0]$1270 attribute \src "libresoc.v:34422.3-34443.6" wire $2\data_r1__fast2_ok$next[0:0]$1271 attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $2\data_r2__nia$next[63:0]$1278 attribute \src "libresoc.v:34444.3-34465.6" wire $2\data_r2__nia_ok$next[0:0]$1279 attribute \src "libresoc.v:34400.3-34421.6" wire $3\data_r0__fast1_ok$next[0:0]$1264 attribute \src "libresoc.v:34422.3-34443.6" wire $3\data_r1__fast2_ok$next[0:0]$1272 attribute \src "libresoc.v:34444.3-34465.6" wire $3\data_r2__nia_ok$next[0:0]$1280 attribute \src "libresoc.v:34082.18-34082.112" wire width 3 $and$libresoc.v:34082$1119_Y attribute \src "libresoc.v:34083.19-34083.125" wire $and$libresoc.v:34083$1120_Y attribute \src "libresoc.v:34084.19-34084.125" wire $and$libresoc.v:34084$1121_Y attribute \src "libresoc.v:34085.19-34085.125" wire $and$libresoc.v:34085$1122_Y attribute \src "libresoc.v:34086.19-34086.141" wire width 3 $and$libresoc.v:34086$1123_Y attribute \src "libresoc.v:34087.19-34087.121" wire width 3 $and$libresoc.v:34087$1124_Y attribute \src "libresoc.v:34088.19-34088.127" wire $and$libresoc.v:34088$1125_Y attribute \src "libresoc.v:34089.19-34089.127" wire $and$libresoc.v:34089$1126_Y attribute \src "libresoc.v:34090.19-34090.127" wire $and$libresoc.v:34090$1127_Y attribute \src "libresoc.v:34091.18-34091.110" wire $and$libresoc.v:34091$1128_Y attribute \src "libresoc.v:34093.18-34093.98" wire $and$libresoc.v:34093$1130_Y attribute \src "libresoc.v:34095.18-34095.100" wire $and$libresoc.v:34095$1132_Y attribute \src "libresoc.v:34096.18-34096.149" wire width 3 $and$libresoc.v:34096$1133_Y attribute \src "libresoc.v:34098.18-34098.119" wire width 3 $and$libresoc.v:34098$1135_Y attribute \src "libresoc.v:34101.18-34101.116" wire $and$libresoc.v:34101$1138_Y attribute \src "libresoc.v:34105.17-34105.123" wire $and$libresoc.v:34105$1142_Y attribute \src "libresoc.v:34107.18-34107.113" wire $and$libresoc.v:34107$1144_Y attribute \src "libresoc.v:34108.18-34108.125" wire width 3 $and$libresoc.v:34108$1145_Y attribute \src "libresoc.v:34110.18-34110.112" wire $and$libresoc.v:34110$1147_Y attribute \src "libresoc.v:34112.18-34112.129" wire $and$libresoc.v:34112$1149_Y attribute \src "libresoc.v:34113.18-34113.129" wire $and$libresoc.v:34113$1150_Y attribute \src "libresoc.v:34114.18-34114.117" wire $and$libresoc.v:34114$1151_Y attribute \src "libresoc.v:34119.18-34119.133" wire $and$libresoc.v:34119$1156_Y attribute \src "libresoc.v:34120.18-34120.124" wire width 3 $and$libresoc.v:34120$1157_Y attribute \src "libresoc.v:34123.18-34123.120" wire $and$libresoc.v:34123$1160_Y attribute \src "libresoc.v:34124.18-34124.120" wire $and$libresoc.v:34124$1161_Y attribute \src "libresoc.v:34125.18-34125.118" wire $and$libresoc.v:34125$1162_Y attribute \src "libresoc.v:34131.18-34131.137" wire $and$libresoc.v:34131$1168_Y attribute \src "libresoc.v:34133.18-34133.135" wire $and$libresoc.v:34133$1170_Y attribute \src "libresoc.v:34134.18-34134.149" wire width 3 $and$libresoc.v:34134$1171_Y attribute \src "libresoc.v:34136.18-34136.129" wire width 3 $and$libresoc.v:34136$1173_Y attribute \src "libresoc.v:34109.18-34109.113" wire $eq$libresoc.v:34109$1146_Y attribute \src "libresoc.v:34111.18-34111.119" wire $eq$libresoc.v:34111$1148_Y attribute \src "libresoc.v:34092.18-34092.97" wire $not$libresoc.v:34092$1129_Y attribute \src "libresoc.v:34094.18-34094.99" wire $not$libresoc.v:34094$1131_Y attribute \src "libresoc.v:34097.18-34097.113" wire width 3 $not$libresoc.v:34097$1134_Y attribute \src "libresoc.v:34100.18-34100.106" wire $not$libresoc.v:34100$1137_Y attribute \src "libresoc.v:34106.18-34106.123" wire $not$libresoc.v:34106$1143_Y attribute \src "libresoc.v:34121.17-34121.113" wire width 3 $not$libresoc.v:34121$1158_Y attribute \src "libresoc.v:34135.18-34135.133" wire $not$libresoc.v:34135$1172_Y attribute \src "libresoc.v:34137.18-34137.114" wire width 3 $not$libresoc.v:34137$1174_Y attribute \src "libresoc.v:34104.18-34104.112" wire $or$libresoc.v:34104$1141_Y attribute \src "libresoc.v:34115.18-34115.122" wire $or$libresoc.v:34115$1152_Y attribute \src "libresoc.v:34116.18-34116.124" wire $or$libresoc.v:34116$1153_Y attribute \src "libresoc.v:34117.18-34117.155" wire width 3 $or$libresoc.v:34117$1154_Y attribute \src "libresoc.v:34118.18-34118.155" wire width 3 $or$libresoc.v:34118$1155_Y attribute \src "libresoc.v:34122.18-34122.120" wire width 3 $or$libresoc.v:34122$1159_Y attribute \src "libresoc.v:34132.17-34132.117" wire width 3 $or$libresoc.v:34132$1169_Y attribute \src "libresoc.v:34081.17-34081.104" wire $reduce_and$libresoc.v:34081$1118_Y attribute \src "libresoc.v:34099.18-34099.106" wire $reduce_or$libresoc.v:34099$1136_Y attribute \src "libresoc.v:34102.18-34102.113" wire $reduce_or$libresoc.v:34102$1139_Y attribute \src "libresoc.v:34103.18-34103.112" wire $reduce_or$libresoc.v:34103$1140_Y attribute \src "libresoc.v:34126.18-34126.162" wire $ternary$libresoc.v:34126$1163_Y attribute \src "libresoc.v:34127.18-34127.176" wire width 64 $ternary$libresoc.v:34127$1164_Y attribute \src "libresoc.v:34128.18-34128.118" wire width 64 $ternary$libresoc.v:34128$1165_Y attribute \src "libresoc.v:34129.18-34129.115" wire width 64 $ternary$libresoc.v:34129$1166_Y attribute \src "libresoc.v:34130.18-34130.118" wire width 4 $ternary$libresoc.v:34130$1167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 3 \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 3 \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 3 \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 3 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 3 \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 3 \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 3 \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 3 \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 3 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 3 \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__cia$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_branch0_br_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_branch0_br_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_branch0_br_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_branch0_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_branch0_br_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_branch0_br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_branch0_br_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_branch0_br_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_branch0_br_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_branch0_br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_branch0_br_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_branch0_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_branch0_br_op__lk$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_branch0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_branch0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_branch0_fast1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_branch0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_branch0_fast2$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_branch0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_branch0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_branch0_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_branch0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_branch0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 26 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 10 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 14 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 13 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 12 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 20 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 19 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 3 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__fast1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r1__fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r1__fast2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__fast2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r2__nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r2__nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__nia_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 22 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 23 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 25 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 18 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \fast2_ok attribute \src "libresoc.v:33529.7-33529.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 2 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 4 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 6 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \oper_i_alu_branch0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 5 \oper_i_alu_branch0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 3 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_alu_branch0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \oper_i_alu_branch0__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 3 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 16 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 17 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 15 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:34082$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$95 connect \B \$97 connect \Y $and$libresoc.v:34082$1119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:34083$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:34083$1120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:34084$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:34084$1121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:34085$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:34085$1122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:34086$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } connect \Y $and$libresoc.v:34086$1123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:34087$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:34087$1124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:34088$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:34088$1125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:34089$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:34089$1126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:34090$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:34090$1127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:34091$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 connect \Y $and$libresoc.v:34091$1128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:34093$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 connect \Y $and$libresoc.v:34093$1130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:34095$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 connect \Y $and$libresoc.v:34095$1132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:34096$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:34096$1133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:34098$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 connect \Y $and$libresoc.v:34098$1135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:34101$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 connect \Y $and$libresoc.v:34101$1138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:34105$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:34105$1142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:34107$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 connect \Y $and$libresoc.v:34107$1144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:34108$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:34108$1145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:34110$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 connect \Y $and$libresoc.v:34110$1147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:34112$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_branch0_n_ready_i connect \Y $and$libresoc.v:34112$1149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:34113$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_branch0_n_valid_o connect \Y $and$libresoc.v:34113$1150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:34114$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o connect \Y $and$libresoc.v:34114$1151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:34119$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:34119$1156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:34120$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:34120$1157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:34123$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:34123$1160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:34124$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:34124$1161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:34125$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:34125$1162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:34131$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:34131$1168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:34133$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:34133$1170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:34134$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:34134$1171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:34136$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$91 connect \B { 1'1 \$93 1'1 } connect \Y $and$libresoc.v:34136$1173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:34109$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 connect \Y $eq$libresoc.v:34109$1146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:34111$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:34111$1148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:34092$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:34092$1129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:34094$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:34094$1131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:34097$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:34097$1134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:34100$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:34100$1137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:34106$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_ready_i connect \Y $not$libresoc.v:34106$1143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:34121$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:34121$1158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:34135$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_br_op__imm_data__ok connect \Y $not$libresoc.v:34135$1172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:34137$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:34137$1174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:34104$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 connect \Y $or$libresoc.v:34104$1141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:34115$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:34115$1152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:34116$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:34116$1153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:34117$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:34117$1154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:34118$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:34118$1155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:34122$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:34122$1159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:34132$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$6 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:34132$1169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:34081$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $reduce_and$libresoc.v:34081$1118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:34099$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 connect \Y $reduce_or$libresoc.v:34099$1136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:34102$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:34102$1139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:34103$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:34103$1140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:34126$1163 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_branch0_br_op__imm_data__ok connect \Y $ternary$libresoc.v:34126$1163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:34127$1164 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_branch0_br_op__imm_data__data connect \S \alu_branch0_br_op__imm_data__ok connect \Y $ternary$libresoc.v:34127$1164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:34128$1165 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] connect \Y $ternary$libresoc.v:34128$1165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:34129$1166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel connect \Y $ternary$libresoc.v:34129$1166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:34130$1167 parameter \WIDTH 4 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:34130$1167_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:34202.15-34226.4" cell \alu_branch0 \alu_branch0 connect \br_op__cia \alu_branch0_br_op__cia connect \br_op__fn_unit \alu_branch0_br_op__fn_unit connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok connect \br_op__insn \alu_branch0_br_op__insn connect \br_op__insn_type \alu_branch0_br_op__insn_type connect \br_op__is_32bit \alu_branch0_br_op__is_32bit connect \br_op__lk \alu_branch0_br_op__lk connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \alu_branch0_cr_a connect \fast1 \alu_branch0_fast1 connect \fast1$1 \alu_branch0_fast1$1 connect \fast1_ok \fast1_ok connect \fast2 \alu_branch0_fast2 connect \fast2$2 \alu_branch0_fast2$2 connect \fast2_ok \fast2_ok connect \n_ready_i \alu_branch0_n_ready_i connect \n_valid_o \alu_branch0_n_valid_o connect \nia \alu_branch0_nia connect \nia_ok \nia_ok connect \p_ready_o \alu_branch0_p_ready_o connect \p_valid_i \alu_branch0_p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:34227.14-34233.4" cell \alu_l$29 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:34234.15-34240.4" cell \alui_l$28 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:34241.14-34247.4" cell \opc_l$24 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:34248.14-34254.4" cell \req_l$25 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:34255.14-34261.4" cell \rok_l$27 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:34262.14-34267.4" cell \rst_l$26 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:34268.14-34274.4" cell \src_l$23 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:33529.7-33529.20" process $proc$libresoc.v:33529$1302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:33647.7-33647.24" process $proc$libresoc.v:33647$1303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:33655.14-33655.59" process $proc$libresoc.v:33655$1304 assign { } { } assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] end attribute \src "libresoc.v:33674.14-33674.51" process $proc$libresoc.v:33674$1305 assign { } { } assign $1\alu_branch0_br_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[13:0] end attribute \src "libresoc.v:33678.14-33678.70" process $proc$libresoc.v:33678$1306 assign { } { } assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] end attribute \src "libresoc.v:33682.7-33682.45" process $proc$libresoc.v:33682$1307 assign { } { } assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] end attribute \src "libresoc.v:33686.14-33686.45" process $proc$libresoc.v:33686$1308 assign { } { } assign $1\alu_branch0_br_op__insn[31:0] 0 sync always sync init update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] end attribute \src "libresoc.v:33765.13-33765.49" process $proc$libresoc.v:33765$1309 assign { } { } assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] end attribute \src "libresoc.v:33769.7-33769.41" process $proc$libresoc.v:33769$1310 assign { } { } assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 sync always sync init update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] end attribute \src "libresoc.v:33773.7-33773.35" process $proc$libresoc.v:33773$1311 assign { } { } assign $1\alu_branch0_br_op__lk[0:0] 1'0 sync always sync init update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] end attribute \src "libresoc.v:33799.7-33799.26" process $proc$libresoc.v:33799$1312 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:33807.7-33807.25" process $proc$libresoc.v:33807$1313 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:33819.7-33819.27" process $proc$libresoc.v:33819$1314 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:33851.14-33851.51" process $proc$libresoc.v:33851$1315 assign { } { } assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__fast1 $1\data_r0__fast1[63:0] end attribute \src "libresoc.v:33855.7-33855.31" process $proc$libresoc.v:33855$1316 assign { } { } assign $1\data_r0__fast1_ok[0:0] 1'0 sync always sync init update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] end attribute \src "libresoc.v:33859.14-33859.51" process $proc$libresoc.v:33859$1317 assign { } { } assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast2 $1\data_r1__fast2[63:0] end attribute \src "libresoc.v:33863.7-33863.31" process $proc$libresoc.v:33863$1318 assign { } { } assign $1\data_r1__fast2_ok[0:0] 1'0 sync always sync init update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] end attribute \src "libresoc.v:33867.14-33867.49" process $proc$libresoc.v:33867$1319 assign { } { } assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__nia $1\data_r2__nia[63:0] end attribute \src "libresoc.v:33871.7-33871.29" process $proc$libresoc.v:33871$1320 assign { } { } assign $1\data_r2__nia_ok[0:0] 1'0 sync always sync init update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] end attribute \src "libresoc.v:33892.7-33892.25" process $proc$libresoc.v:33892$1321 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:33896.7-33896.25" process $proc$libresoc.v:33896$1322 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:34006.13-34006.30" process $proc$libresoc.v:34006$1323 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end attribute \src "libresoc.v:34014.13-34014.31" process $proc$libresoc.v:34014$1324 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end attribute \src "libresoc.v:34018.13-34018.31" process $proc$libresoc.v:34018$1325 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end attribute \src "libresoc.v:34030.7-34030.26" process $proc$libresoc.v:34030$1326 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:34034.7-34034.26" process $proc$libresoc.v:34034$1327 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:34038.7-34038.25" process $proc$libresoc.v:34038$1328 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:34042.7-34042.25" process $proc$libresoc.v:34042$1329 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:34056.13-34056.31" process $proc$libresoc.v:34056$1330 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end attribute \src "libresoc.v:34060.13-34060.31" process $proc$libresoc.v:34060$1331 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end attribute \src "libresoc.v:34066.14-34066.43" process $proc$libresoc.v:34066$1332 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:34070.14-34070.43" process $proc$libresoc.v:34070$1333 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:34074.13-34074.26" process $proc$libresoc.v:34074$1334 assign { } { } assign $1\src_r2[3:0] 4'0000 sync always sync init update \src_r2 $1\src_r2[3:0] end attribute \src "libresoc.v:34138.3-34139.39" process $proc$libresoc.v:34138$1175 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:34140.3-34141.43" process $proc$libresoc.v:34140$1176 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:34142.3-34143.29" process $proc$libresoc.v:34142$1177 assign { } { } assign $0\src_r2[3:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[3:0] end attribute \src "libresoc.v:34144.3-34145.29" process $proc$libresoc.v:34144$1178 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:34146.3-34147.29" process $proc$libresoc.v:34146$1179 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:34148.3-34149.41" process $proc$libresoc.v:34148$1180 assign { } { } assign $0\data_r2__nia[63:0] \data_r2__nia$next sync posedge \coresync_clk update \data_r2__nia $0\data_r2__nia[63:0] end attribute \src "libresoc.v:34150.3-34151.47" process $proc$libresoc.v:34150$1181 assign { } { } assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next sync posedge \coresync_clk update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] end attribute \src "libresoc.v:34152.3-34153.45" process $proc$libresoc.v:34152$1182 assign { } { } assign $0\data_r1__fast2[63:0] \data_r1__fast2$next sync posedge \coresync_clk update \data_r1__fast2 $0\data_r1__fast2[63:0] end attribute \src "libresoc.v:34154.3-34155.51" process $proc$libresoc.v:34154$1183 assign { } { } assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next sync posedge \coresync_clk update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] end attribute \src "libresoc.v:34156.3-34157.45" process $proc$libresoc.v:34156$1184 assign { } { } assign $0\data_r0__fast1[63:0] \data_r0__fast1$next sync posedge \coresync_clk update \data_r0__fast1 $0\data_r0__fast1[63:0] end attribute \src "libresoc.v:34158.3-34159.51" process $proc$libresoc.v:34158$1185 assign { } { } assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next sync posedge \coresync_clk update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] end attribute \src "libresoc.v:34160.3-34161.61" process $proc$libresoc.v:34160$1186 assign { } { } assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next sync posedge \coresync_clk update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] end attribute \src "libresoc.v:34162.3-34163.73" process $proc$libresoc.v:34162$1187 assign { } { } assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next sync posedge \coresync_clk update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] end attribute \src "libresoc.v:34164.3-34165.69" process $proc$libresoc.v:34164$1188 assign { } { } assign $0\alu_branch0_br_op__fn_unit[13:0] \alu_branch0_br_op__fn_unit$next sync posedge \coresync_clk update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[13:0] end attribute \src "libresoc.v:34166.3-34167.63" process $proc$libresoc.v:34166$1189 assign { } { } assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next sync posedge \coresync_clk update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] end attribute \src "libresoc.v:34168.3-34169.83" process $proc$libresoc.v:34168$1190 assign { } { } assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] end attribute \src "libresoc.v:34170.3-34171.79" process $proc$libresoc.v:34170$1191 assign { } { } assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] end attribute \src "libresoc.v:34172.3-34173.59" process $proc$libresoc.v:34172$1192 assign { } { } assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next sync posedge \coresync_clk update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] end attribute \src "libresoc.v:34174.3-34175.71" process $proc$libresoc.v:34174$1193 assign { } { } assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next sync posedge \coresync_clk update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] end attribute \src "libresoc.v:34176.3-34177.39" process $proc$libresoc.v:34176$1194 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end attribute \src "libresoc.v:34178.3-34179.39" process $proc$libresoc.v:34178$1195 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end attribute \src "libresoc.v:34180.3-34181.39" process $proc$libresoc.v:34180$1196 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end attribute \src "libresoc.v:34182.3-34183.39" process $proc$libresoc.v:34182$1197 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end attribute \src "libresoc.v:34184.3-34185.39" process $proc$libresoc.v:34184$1198 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:34186.3-34187.39" process $proc$libresoc.v:34186$1199 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:34188.3-34189.39" process $proc$libresoc.v:34188$1200 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:34190.3-34191.39" process $proc$libresoc.v:34190$1201 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:34192.3-34193.41" process $proc$libresoc.v:34192$1202 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:34194.3-34195.41" process $proc$libresoc.v:34194$1203 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:34196.3-34197.37" process $proc$libresoc.v:34196$1204 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end attribute \src "libresoc.v:34198.3-34199.43" process $proc$libresoc.v:34198$1205 assign { } { } assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:34200.3-34201.25" process $proc$libresoc.v:34200$1206 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:34275.3-34284.6" process $proc$libresoc.v:34275$1207 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:34276.5-34276.29" switch \initial attribute \src "libresoc.v:34276.9-34276.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$47 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:34285.3-34293.6" process $proc$libresoc.v:34285$1208 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 attribute \src "libresoc.v:34286.5-34286.29" switch \initial attribute \src "libresoc.v:34286.9-34286.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$1210 1'0 case assign $1\rok_l_s_rdok$next[0:0]$1210 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 end attribute \src "libresoc.v:34294.3-34302.6" process $proc$libresoc.v:34294$1211 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 attribute \src "libresoc.v:34295.5-34295.29" switch \initial attribute \src "libresoc.v:34295.9-34295.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$1213 1'1 case assign $1\rok_l_r_rdok$next[0:0]$1213 \$65 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 end attribute \src "libresoc.v:34303.3-34311.6" process $proc$libresoc.v:34303$1214 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 attribute \src "libresoc.v:34304.5-34304.29" switch \initial attribute \src "libresoc.v:34304.9-34304.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$1216 1'0 case assign $1\rst_l_s_rst$next[0:0]$1216 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 end attribute \src "libresoc.v:34312.3-34320.6" process $proc$libresoc.v:34312$1217 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 attribute \src "libresoc.v:34313.5-34313.29" switch \initial attribute \src "libresoc.v:34313.9-34313.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$1219 1'1 case assign $1\rst_l_r_rst$next[0:0]$1219 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 end attribute \src "libresoc.v:34321.3-34329.6" process $proc$libresoc.v:34321$1220 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 attribute \src "libresoc.v:34322.5-34322.29" switch \initial attribute \src "libresoc.v:34322.9-34322.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$1222 1'0 case assign $1\opc_l_s_opc$next[0:0]$1222 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 end attribute \src "libresoc.v:34330.3-34338.6" process $proc$libresoc.v:34330$1223 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 attribute \src "libresoc.v:34331.5-34331.29" switch \initial attribute \src "libresoc.v:34331.9-34331.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$1225 1'1 case assign $1\opc_l_r_opc$next[0:0]$1225 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 end attribute \src "libresoc.v:34339.3-34347.6" process $proc$libresoc.v:34339$1226 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 attribute \src "libresoc.v:34340.5-34340.29" switch \initial attribute \src "libresoc.v:34340.9-34340.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[2:0]$1228 3'000 case assign $1\src_l_s_src$next[2:0]$1228 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 end attribute \src "libresoc.v:34348.3-34356.6" process $proc$libresoc.v:34348$1229 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 attribute \src "libresoc.v:34349.5-34349.29" switch \initial attribute \src "libresoc.v:34349.9-34349.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[2:0]$1231 3'111 case assign $1\src_l_r_src$next[2:0]$1231 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 end attribute \src "libresoc.v:34357.3-34365.6" process $proc$libresoc.v:34357$1232 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 attribute \src "libresoc.v:34358.5-34358.29" switch \initial attribute \src "libresoc.v:34358.9-34358.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[2:0]$1234 3'000 case assign $1\req_l_s_req$next[2:0]$1234 \$67 end sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 end attribute \src "libresoc.v:34366.3-34374.6" process $proc$libresoc.v:34366$1235 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 attribute \src "libresoc.v:34367.5-34367.29" switch \initial attribute \src "libresoc.v:34367.9-34367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[2:0]$1237 3'111 case assign $1\req_l_r_req$next[2:0]$1237 \$69 end sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 end attribute \src "libresoc.v:34375.3-34399.6" process $proc$libresoc.v:34375$1238 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 assign $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 assign { } { } assign { } { } assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 assign $0\alu_branch0_br_op__insn_type$next[6:0]$1244 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 attribute \src "libresoc.v:34376.5-34376.29" switch \initial attribute \src "libresoc.v:34376.9-34376.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } case assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia assign $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 \alu_branch0_br_op__fn_unit assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn assign $1\alu_branch0_br_op__insn_type$next[6:0]$1252 \alu_branch0_br_op__insn_type assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 \alu_branch0_br_op__is_32bit assign $1\alu_branch0_br_op__lk$next[0:0]$1254 \alu_branch0_br_op__lk end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 1'0 case assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 end sync always update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1244 update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 end attribute \src "libresoc.v:34400.3-34421.6" process $proc$libresoc.v:34400$1257 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 assign { } { } assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 attribute \src "libresoc.v:34401.5-34401.29" switch \initial attribute \src "libresoc.v:34401.9-34401.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__fast1_ok$next[0:0]$1261 $1\data_r0__fast1$next[63:0]$1260 } { \fast1_ok \alu_branch0_fast1 } case assign $1\data_r0__fast1$next[63:0]$1260 \data_r0__fast1 assign $1\data_r0__fast1_ok$next[0:0]$1261 \data_r0__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__fast1_ok$next[0:0]$1263 $2\data_r0__fast1$next[63:0]$1262 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__fast1$next[63:0]$1262 $1\data_r0__fast1$next[63:0]$1260 assign $2\data_r0__fast1_ok$next[0:0]$1263 $1\data_r0__fast1_ok$next[0:0]$1261 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__fast1_ok$next[0:0]$1264 1'0 case assign $3\data_r0__fast1_ok$next[0:0]$1264 $2\data_r0__fast1_ok$next[0:0]$1263 end sync always update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 end attribute \src "libresoc.v:34422.3-34443.6" process $proc$libresoc.v:34422$1265 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 assign { } { } assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 attribute \src "libresoc.v:34423.5-34423.29" switch \initial attribute \src "libresoc.v:34423.9-34423.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__fast2_ok$next[0:0]$1269 $1\data_r1__fast2$next[63:0]$1268 } { \fast2_ok \alu_branch0_fast2 } case assign $1\data_r1__fast2$next[63:0]$1268 \data_r1__fast2 assign $1\data_r1__fast2_ok$next[0:0]$1269 \data_r1__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__fast2_ok$next[0:0]$1271 $2\data_r1__fast2$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r1__fast2$next[63:0]$1270 $1\data_r1__fast2$next[63:0]$1268 assign $2\data_r1__fast2_ok$next[0:0]$1271 $1\data_r1__fast2_ok$next[0:0]$1269 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__fast2_ok$next[0:0]$1272 1'0 case assign $3\data_r1__fast2_ok$next[0:0]$1272 $2\data_r1__fast2_ok$next[0:0]$1271 end sync always update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 end attribute \src "libresoc.v:34444.3-34465.6" process $proc$libresoc.v:34444$1273 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 assign { } { } assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 attribute \src "libresoc.v:34445.5-34445.29" switch \initial attribute \src "libresoc.v:34445.9-34445.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__nia_ok$next[0:0]$1277 $1\data_r2__nia$next[63:0]$1276 } { \nia_ok \alu_branch0_nia } case assign $1\data_r2__nia$next[63:0]$1276 \data_r2__nia assign $1\data_r2__nia_ok$next[0:0]$1277 \data_r2__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__nia_ok$next[0:0]$1279 $2\data_r2__nia$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r2__nia$next[63:0]$1278 $1\data_r2__nia$next[63:0]$1276 assign $2\data_r2__nia_ok$next[0:0]$1279 $1\data_r2__nia_ok$next[0:0]$1277 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__nia_ok$next[0:0]$1280 1'0 case assign $3\data_r2__nia_ok$next[0:0]$1280 $2\data_r2__nia_ok$next[0:0]$1279 end sync always update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 end attribute \src "libresoc.v:34466.3-34475.6" process $proc$libresoc.v:34466$1281 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 attribute \src "libresoc.v:34467.5-34467.29" switch \initial attribute \src "libresoc.v:34467.9-34467.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$1283 \src1_i case assign $1\src_r0$next[63:0]$1283 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$1282 end attribute \src "libresoc.v:34476.3-34485.6" process $proc$libresoc.v:34476$1284 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 attribute \src "libresoc.v:34477.5-34477.29" switch \initial attribute \src "libresoc.v:34477.9-34477.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$1286 \src_or_imm case assign $1\src_r1$next[63:0]$1286 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$1285 end attribute \src "libresoc.v:34486.3-34495.6" process $proc$libresoc.v:34486$1287 assign { } { } assign { } { } assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 attribute \src "libresoc.v:34487.5-34487.29" switch \initial attribute \src "libresoc.v:34487.9-34487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[3:0]$1289 \src3_i case assign $1\src_r2$next[3:0]$1289 \src_r2 end sync always update \src_r2$next $0\src_r2$next[3:0]$1288 end attribute \src "libresoc.v:34496.3-34504.6" process $proc$libresoc.v:34496$1290 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 attribute \src "libresoc.v:34497.5-34497.29" switch \initial attribute \src "libresoc.v:34497.9-34497.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$1292 1'1 case assign $1\alui_l_r_alui$next[0:0]$1292 \$87 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 end attribute \src "libresoc.v:34505.3-34513.6" process $proc$libresoc.v:34505$1293 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 attribute \src "libresoc.v:34506.5-34506.29" switch \initial attribute \src "libresoc.v:34506.9-34506.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$1295 1'1 case assign $1\alu_l_r_alu$next[0:0]$1295 \$89 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 end attribute \src "libresoc.v:34514.3-34523.6" process $proc$libresoc.v:34514$1296 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:34515.5-34515.29" switch \initial attribute \src "libresoc.v:34515.9-34515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__fast1 case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:34524.3-34533.6" process $proc$libresoc.v:34524$1297 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] attribute \src "libresoc.v:34525.5-34525.29" switch \initial attribute \src "libresoc.v:34525.9-34525.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[63:0] \data_r1__fast2 case assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest2_o $0\dest2_o[63:0] end attribute \src "libresoc.v:34534.3-34543.6" process $proc$libresoc.v:34534$1298 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] attribute \src "libresoc.v:34535.5-34535.29" switch \initial attribute \src "libresoc.v:34535.9-34535.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[63:0] \data_r2__nia case assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest3_o $0\dest3_o[63:0] end attribute \src "libresoc.v:34544.3-34552.6" process $proc$libresoc.v:34544$1299 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 attribute \src "libresoc.v:34545.5-34545.29" switch \initial attribute \src "libresoc.v:34545.9-34545.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[2:0]$1301 3'000 case assign $1\prev_wr_go$next[2:0]$1301 \$21 end sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 end connect \$5 $reduce_and$libresoc.v:34081$1118_Y connect \$99 $and$libresoc.v:34082$1119_Y connect \$101 $and$libresoc.v:34083$1120_Y connect \$103 $and$libresoc.v:34084$1121_Y connect \$105 $and$libresoc.v:34085$1122_Y connect \$107 $and$libresoc.v:34086$1123_Y connect \$109 $and$libresoc.v:34087$1124_Y connect \$111 $and$libresoc.v:34088$1125_Y connect \$113 $and$libresoc.v:34089$1126_Y connect \$115 $and$libresoc.v:34090$1127_Y connect \$11 $and$libresoc.v:34091$1128_Y connect \$13 $not$libresoc.v:34092$1129_Y connect \$15 $and$libresoc.v:34093$1130_Y connect \$17 $not$libresoc.v:34094$1131_Y connect \$19 $and$libresoc.v:34095$1132_Y connect \$21 $and$libresoc.v:34096$1133_Y connect \$25 $not$libresoc.v:34097$1134_Y connect \$27 $and$libresoc.v:34098$1135_Y connect \$24 $reduce_or$libresoc.v:34099$1136_Y connect \$23 $not$libresoc.v:34100$1137_Y connect \$31 $and$libresoc.v:34101$1138_Y connect \$33 $reduce_or$libresoc.v:34102$1139_Y connect \$35 $reduce_or$libresoc.v:34103$1140_Y connect \$37 $or$libresoc.v:34104$1141_Y connect \$3 $and$libresoc.v:34105$1142_Y connect \$39 $not$libresoc.v:34106$1143_Y connect \$41 $and$libresoc.v:34107$1144_Y connect \$43 $and$libresoc.v:34108$1145_Y connect \$45 $eq$libresoc.v:34109$1146_Y connect \$47 $and$libresoc.v:34110$1147_Y connect \$49 $eq$libresoc.v:34111$1148_Y connect \$51 $and$libresoc.v:34112$1149_Y connect \$53 $and$libresoc.v:34113$1150_Y connect \$55 $and$libresoc.v:34114$1151_Y connect \$57 $or$libresoc.v:34115$1152_Y connect \$59 $or$libresoc.v:34116$1153_Y connect \$61 $or$libresoc.v:34117$1154_Y connect \$63 $or$libresoc.v:34118$1155_Y connect \$65 $and$libresoc.v:34119$1156_Y connect \$67 $and$libresoc.v:34120$1157_Y connect \$6 $not$libresoc.v:34121$1158_Y connect \$69 $or$libresoc.v:34122$1159_Y connect \$71 $and$libresoc.v:34123$1160_Y connect \$73 $and$libresoc.v:34124$1161_Y connect \$75 $and$libresoc.v:34125$1162_Y connect \$77 $ternary$libresoc.v:34126$1163_Y connect \$79 $ternary$libresoc.v:34127$1164_Y connect \$81 $ternary$libresoc.v:34128$1165_Y connect \$83 $ternary$libresoc.v:34129$1166_Y connect \$85 $ternary$libresoc.v:34130$1167_Y connect \$87 $and$libresoc.v:34131$1168_Y connect \$8 $or$libresoc.v:34132$1169_Y connect \$89 $and$libresoc.v:34133$1170_Y connect \$91 $and$libresoc.v:34134$1171_Y connect \$93 $not$libresoc.v:34135$1172_Y connect \$95 $and$libresoc.v:34136$1173_Y connect \$97 $not$libresoc.v:34137$1174_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 connect \cu_rd__rel_o \$99 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_branch0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_branch0_p_valid_i \alui_l_q_alui connect \alu_branch0_cr_a \$85 connect \alu_branch0_fast2$2 \$83 connect \alu_branch0_fast1$1 \$81 connect \src_or_imm \$79 connect \src_sel \$77 connect \cu_wrmask_o { \$75 \$73 \$71 } connect \reset_r \$63 connect \reset_w \$61 connect \rst_r \$59 connect \reset \$57 connect \wr_any \$37 connect \cu_done_o \$31 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$19 connect \alu_done_dly$next \alu_done connect \alu_done \alu_branch0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$15 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end attribute \src "libresoc.v:34587.1-34645.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" attribute \generator "nMigen" module \busy_l attribute \src "libresoc.v:34588.7-34588.20" wire $0\initial[0:0] attribute \src "libresoc.v:34633.3-34641.6" wire $0\q_int$next[0:0]$1345 attribute \src "libresoc.v:34631.3-34632.27" wire $0\q_int[0:0] attribute \src "libresoc.v:34633.3-34641.6" wire $1\q_int$next[0:0]$1346 attribute \src "libresoc.v:34612.7-34612.19" wire $1\q_int[0:0] attribute \src "libresoc.v:34623.17-34623.96" wire $and$libresoc.v:34623$1335_Y attribute \src "libresoc.v:34628.17-34628.96" wire $and$libresoc.v:34628$1340_Y attribute \src "libresoc.v:34625.18-34625.94" wire $not$libresoc.v:34625$1337_Y attribute \src "libresoc.v:34627.17-34627.93" wire $not$libresoc.v:34627$1339_Y attribute \src "libresoc.v:34630.17-34630.93" wire $not$libresoc.v:34630$1342_Y attribute \src "libresoc.v:34624.18-34624.99" wire $or$libresoc.v:34624$1336_Y attribute \src "libresoc.v:34626.18-34626.100" wire $or$libresoc.v:34626$1338_Y attribute \src "libresoc.v:34629.17-34629.98" wire $or$libresoc.v:34629$1341_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:34588.7-34588.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:34623$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:34623$1335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:34628$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:34628$1340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:34625$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_busy connect \Y $not$libresoc.v:34625$1337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:34627$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy connect \Y $not$libresoc.v:34627$1339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:34630$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy connect \Y $not$libresoc.v:34630$1342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:34624$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_busy connect \Y $or$libresoc.v:34624$1336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:34626$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_busy connect \B \q_int connect \Y $or$libresoc.v:34626$1338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:34629$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_busy connect \Y $or$libresoc.v:34629$1341_Y end attribute \src "libresoc.v:34588.7-34588.20" process $proc$libresoc.v:34588$1347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:34612.7-34612.19" process $proc$libresoc.v:34612$1348 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:34631.3-34632.27" process $proc$libresoc.v:34631$1343 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:34633.3-34641.6" process $proc$libresoc.v:34633$1344 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 attribute \src "libresoc.v:34634.5-34634.29" switch \initial attribute \src "libresoc.v:34634.9-34634.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$1346 1'0 case assign $1\q_int$next[0:0]$1346 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$1345 end connect \$9 $and$libresoc.v:34623$1335_Y connect \$11 $or$libresoc.v:34624$1336_Y connect \$13 $not$libresoc.v:34625$1337_Y connect \$15 $or$libresoc.v:34626$1338_Y connect \$1 $not$libresoc.v:34627$1339_Y connect \$3 $and$libresoc.v:34628$1340_Y connect \$5 $or$libresoc.v:34629$1341_Y connect \$7 $not$libresoc.v:34630$1342_Y connect \qlq_busy \$15 connect \qn_busy \$13 connect \q_busy \$11 end attribute \src "libresoc.v:34649.1-36257.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" attribute \generator "nMigen" module \clz attribute \src "libresoc.v:35124.3-35138.6" wire width 2 $0\cnt_1_0[1:0] attribute \src "libresoc.v:35214.3-35228.6" wire width 2 $0\cnt_1_10[1:0] attribute \src "libresoc.v:35229.3-35243.6" wire width 2 $0\cnt_1_11[1:0] attribute \src "libresoc.v:35244.3-35258.6" wire width 2 $0\cnt_1_12[1:0] attribute \src "libresoc.v:35259.3-35273.6" wire width 2 $0\cnt_1_13[1:0] attribute \src "libresoc.v:35274.3-35288.6" wire width 2 $0\cnt_1_14[1:0] attribute \src "libresoc.v:35304.3-35318.6" wire width 2 $0\cnt_1_15[1:0] attribute \src "libresoc.v:35319.3-35333.6" wire width 2 $0\cnt_1_16[1:0] attribute \src "libresoc.v:35334.3-35348.6" wire width 2 $0\cnt_1_17[1:0] attribute \src "libresoc.v:35349.3-35363.6" wire width 2 $0\cnt_1_18[1:0] attribute \src "libresoc.v:35364.3-35378.6" wire width 2 $0\cnt_1_19[1:0] attribute \src "libresoc.v:35289.3-35303.6" wire width 2 $0\cnt_1_1[1:0] attribute \src "libresoc.v:35379.3-35393.6" wire width 2 $0\cnt_1_20[1:0] attribute \src "libresoc.v:35394.3-35408.6" wire width 2 $0\cnt_1_21[1:0] attribute \src "libresoc.v:35409.3-35423.6" wire width 2 $0\cnt_1_22[1:0] attribute \src "libresoc.v:35424.3-35438.6" wire width 2 $0\cnt_1_23[1:0] attribute \src "libresoc.v:35439.3-35453.6" wire width 2 $0\cnt_1_24[1:0] attribute \src "libresoc.v:35469.3-35483.6" wire width 2 $0\cnt_1_25[1:0] attribute \src "libresoc.v:35484.3-35498.6" wire width 2 $0\cnt_1_26[1:0] attribute \src "libresoc.v:35499.3-35513.6" wire width 2 $0\cnt_1_27[1:0] attribute \src "libresoc.v:35514.3-35528.6" wire width 2 $0\cnt_1_28[1:0] attribute \src "libresoc.v:35529.3-35543.6" wire width 2 $0\cnt_1_29[1:0] attribute \src "libresoc.v:35454.3-35468.6" wire width 2 $0\cnt_1_2[1:0] attribute \src "libresoc.v:35544.3-35558.6" wire width 2 $0\cnt_1_30[1:0] attribute \src "libresoc.v:35559.3-35573.6" wire width 2 $0\cnt_1_31[1:0] attribute \src "libresoc.v:35694.3-35708.6" wire width 2 $0\cnt_1_3[1:0] attribute \src "libresoc.v:36109.3-36123.6" wire width 2 $0\cnt_1_4[1:0] attribute \src "libresoc.v:35139.3-35153.6" wire width 2 $0\cnt_1_5[1:0] attribute \src "libresoc.v:35154.3-35168.6" wire width 2 $0\cnt_1_6[1:0] attribute \src "libresoc.v:35169.3-35183.6" wire width 2 $0\cnt_1_7[1:0] attribute \src "libresoc.v:35184.3-35198.6" wire width 2 $0\cnt_1_8[1:0] attribute \src "libresoc.v:35199.3-35213.6" wire width 2 $0\cnt_1_9[1:0] attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $0\cnt_2_0[2:0] attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $0\cnt_2_10[2:0] attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $0\cnt_2_12[2:0] attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $0\cnt_2_14[2:0] attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $0\cnt_2_16[2:0] attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $0\cnt_2_18[2:0] attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $0\cnt_2_20[2:0] attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $0\cnt_2_22[2:0] attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $0\cnt_2_24[2:0] attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $0\cnt_2_26[2:0] attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $0\cnt_2_28[2:0] attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $0\cnt_2_2[2:0] attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $0\cnt_2_30[2:0] attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $0\cnt_2_4[2:0] attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $0\cnt_2_6[2:0] attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $0\cnt_2_8[2:0] attribute \src "libresoc.v:35909.3-35928.6" wire width 4 $0\cnt_3_0[3:0] attribute \src "libresoc.v:36009.3-36028.6" wire width 4 $0\cnt_3_10[3:0] attribute \src "libresoc.v:36029.3-36048.6" wire width 4 $0\cnt_3_12[3:0] attribute \src "libresoc.v:36049.3-36068.6" wire width 4 $0\cnt_3_14[3:0] attribute \src "libresoc.v:35929.3-35948.6" wire width 4 $0\cnt_3_2[3:0] attribute \src "libresoc.v:35949.3-35968.6" wire width 4 $0\cnt_3_4[3:0] attribute \src "libresoc.v:35969.3-35988.6" wire width 4 $0\cnt_3_6[3:0] attribute \src "libresoc.v:35989.3-36008.6" wire width 4 $0\cnt_3_8[3:0] attribute \src "libresoc.v:36069.3-36088.6" wire width 5 $0\cnt_4_0[4:0] attribute \src "libresoc.v:36089.3-36108.6" wire width 5 $0\cnt_4_2[4:0] attribute \src "libresoc.v:36124.3-36143.6" wire width 5 $0\cnt_4_4[4:0] attribute \src "libresoc.v:36144.3-36163.6" wire width 5 $0\cnt_4_6[4:0] attribute \src "libresoc.v:36164.3-36183.6" wire width 6 $0\cnt_5_0[5:0] attribute \src "libresoc.v:36184.3-36203.6" wire width 6 $0\cnt_5_2[5:0] attribute \src "libresoc.v:36204.3-36223.6" wire width 7 $0\cnt_6_0[6:0] attribute \src "libresoc.v:34650.7-34650.20" wire $0\initial[0:0] attribute \src "libresoc.v:35124.3-35138.6" wire width 2 $1\cnt_1_0[1:0] attribute \src "libresoc.v:35214.3-35228.6" wire width 2 $1\cnt_1_10[1:0] attribute \src "libresoc.v:35229.3-35243.6" wire width 2 $1\cnt_1_11[1:0] attribute \src "libresoc.v:35244.3-35258.6" wire width 2 $1\cnt_1_12[1:0] attribute \src "libresoc.v:35259.3-35273.6" wire width 2 $1\cnt_1_13[1:0] attribute \src "libresoc.v:35274.3-35288.6" wire width 2 $1\cnt_1_14[1:0] attribute \src "libresoc.v:35304.3-35318.6" wire width 2 $1\cnt_1_15[1:0] attribute \src "libresoc.v:35319.3-35333.6" wire width 2 $1\cnt_1_16[1:0] attribute \src "libresoc.v:35334.3-35348.6" wire width 2 $1\cnt_1_17[1:0] attribute \src "libresoc.v:35349.3-35363.6" wire width 2 $1\cnt_1_18[1:0] attribute \src "libresoc.v:35364.3-35378.6" wire width 2 $1\cnt_1_19[1:0] attribute \src "libresoc.v:35289.3-35303.6" wire width 2 $1\cnt_1_1[1:0] attribute \src "libresoc.v:35379.3-35393.6" wire width 2 $1\cnt_1_20[1:0] attribute \src "libresoc.v:35394.3-35408.6" wire width 2 $1\cnt_1_21[1:0] attribute \src "libresoc.v:35409.3-35423.6" wire width 2 $1\cnt_1_22[1:0] attribute \src "libresoc.v:35424.3-35438.6" wire width 2 $1\cnt_1_23[1:0] attribute \src "libresoc.v:35439.3-35453.6" wire width 2 $1\cnt_1_24[1:0] attribute \src "libresoc.v:35469.3-35483.6" wire width 2 $1\cnt_1_25[1:0] attribute \src "libresoc.v:35484.3-35498.6" wire width 2 $1\cnt_1_26[1:0] attribute \src "libresoc.v:35499.3-35513.6" wire width 2 $1\cnt_1_27[1:0] attribute \src "libresoc.v:35514.3-35528.6" wire width 2 $1\cnt_1_28[1:0] attribute \src "libresoc.v:35529.3-35543.6" wire width 2 $1\cnt_1_29[1:0] attribute \src "libresoc.v:35454.3-35468.6" wire width 2 $1\cnt_1_2[1:0] attribute \src "libresoc.v:35544.3-35558.6" wire width 2 $1\cnt_1_30[1:0] attribute \src "libresoc.v:35559.3-35573.6" wire width 2 $1\cnt_1_31[1:0] attribute \src "libresoc.v:35694.3-35708.6" wire width 2 $1\cnt_1_3[1:0] attribute \src "libresoc.v:36109.3-36123.6" wire width 2 $1\cnt_1_4[1:0] attribute \src "libresoc.v:35139.3-35153.6" wire width 2 $1\cnt_1_5[1:0] attribute \src "libresoc.v:35154.3-35168.6" wire width 2 $1\cnt_1_6[1:0] attribute \src "libresoc.v:35169.3-35183.6" wire width 2 $1\cnt_1_7[1:0] attribute \src "libresoc.v:35184.3-35198.6" wire width 2 $1\cnt_1_8[1:0] attribute \src "libresoc.v:35199.3-35213.6" wire width 2 $1\cnt_1_9[1:0] attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $1\cnt_2_0[2:0] attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $1\cnt_2_10[2:0] attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $1\cnt_2_12[2:0] attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $1\cnt_2_14[2:0] attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $1\cnt_2_16[2:0] attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $1\cnt_2_18[2:0] attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $1\cnt_2_20[2:0] attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $1\cnt_2_22[2:0] attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $1\cnt_2_24[2:0] attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $1\cnt_2_26[2:0] attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $1\cnt_2_28[2:0] attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $1\cnt_2_2[2:0] attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $1\cnt_2_30[2:0] attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $1\cnt_2_4[2:0] attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $1\cnt_2_6[2:0] attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $1\cnt_2_8[2:0] attribute \src "libresoc.v:35909.3-35928.6" wire width 4 $1\cnt_3_0[3:0] attribute \src "libresoc.v:36009.3-36028.6" wire width 4 $1\cnt_3_10[3:0] attribute \src "libresoc.v:36029.3-36048.6" wire width 4 $1\cnt_3_12[3:0] attribute \src "libresoc.v:36049.3-36068.6" wire width 4 $1\cnt_3_14[3:0] attribute \src "libresoc.v:35929.3-35948.6" wire width 4 $1\cnt_3_2[3:0] attribute \src "libresoc.v:35949.3-35968.6" wire width 4 $1\cnt_3_4[3:0] attribute \src "libresoc.v:35969.3-35988.6" wire width 4 $1\cnt_3_6[3:0] attribute \src "libresoc.v:35989.3-36008.6" wire width 4 $1\cnt_3_8[3:0] attribute \src "libresoc.v:36069.3-36088.6" wire width 5 $1\cnt_4_0[4:0] attribute \src "libresoc.v:36089.3-36108.6" wire width 5 $1\cnt_4_2[4:0] attribute \src "libresoc.v:36124.3-36143.6" wire width 5 $1\cnt_4_4[4:0] attribute \src "libresoc.v:36144.3-36163.6" wire width 5 $1\cnt_4_6[4:0] attribute \src "libresoc.v:36164.3-36183.6" wire width 6 $1\cnt_5_0[5:0] attribute \src "libresoc.v:36184.3-36203.6" wire width 6 $1\cnt_5_2[5:0] attribute \src "libresoc.v:36204.3-36223.6" wire width 7 $1\cnt_6_0[6:0] attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $2\cnt_2_0[2:0] attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $2\cnt_2_10[2:0] attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $2\cnt_2_12[2:0] attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $2\cnt_2_14[2:0] attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $2\cnt_2_16[2:0] attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $2\cnt_2_18[2:0] attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $2\cnt_2_20[2:0] attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $2\cnt_2_22[2:0] attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $2\cnt_2_24[2:0] attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $2\cnt_2_26[2:0] attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $2\cnt_2_28[2:0] attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $2\cnt_2_2[2:0] attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $2\cnt_2_30[2:0] attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $2\cnt_2_4[2:0] attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $2\cnt_2_6[2:0] attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $2\cnt_2_8[2:0] attribute \src "libresoc.v:35909.3-35928.6" wire width 4 $2\cnt_3_0[3:0] attribute \src "libresoc.v:36009.3-36028.6" wire width 4 $2\cnt_3_10[3:0] attribute \src "libresoc.v:36029.3-36048.6" wire width 4 $2\cnt_3_12[3:0] attribute \src "libresoc.v:36049.3-36068.6" wire width 4 $2\cnt_3_14[3:0] attribute \src "libresoc.v:35929.3-35948.6" wire width 4 $2\cnt_3_2[3:0] attribute \src "libresoc.v:35949.3-35968.6" wire width 4 $2\cnt_3_4[3:0] attribute \src "libresoc.v:35969.3-35988.6" wire width 4 $2\cnt_3_6[3:0] attribute \src "libresoc.v:35989.3-36008.6" wire width 4 $2\cnt_3_8[3:0] attribute \src "libresoc.v:36069.3-36088.6" wire width 5 $2\cnt_4_0[4:0] attribute \src "libresoc.v:36089.3-36108.6" wire width 5 $2\cnt_4_2[4:0] attribute \src "libresoc.v:36124.3-36143.6" wire width 5 $2\cnt_4_4[4:0] attribute \src "libresoc.v:36144.3-36163.6" wire width 5 $2\cnt_4_6[4:0] attribute \src "libresoc.v:36164.3-36183.6" wire width 6 $2\cnt_5_0[5:0] attribute \src "libresoc.v:36184.3-36203.6" wire width 6 $2\cnt_5_2[5:0] attribute \src "libresoc.v:36204.3-36223.6" wire width 7 $2\cnt_6_0[6:0] attribute \src "libresoc.v:35031.17-35031.101" wire $eq$libresoc.v:35031$1349_Y attribute \src "libresoc.v:35032.18-35032.102" wire $eq$libresoc.v:35032$1350_Y attribute \src "libresoc.v:35034.19-35034.103" wire $eq$libresoc.v:35034$1352_Y attribute \src "libresoc.v:35035.19-35035.103" wire $eq$libresoc.v:35035$1353_Y attribute \src "libresoc.v:35037.19-35037.104" wire $eq$libresoc.v:35037$1355_Y attribute \src "libresoc.v:35038.19-35038.103" wire $eq$libresoc.v:35038$1356_Y attribute \src "libresoc.v:35040.19-35040.104" wire $eq$libresoc.v:35040$1358_Y attribute \src "libresoc.v:35041.19-35041.104" wire $eq$libresoc.v:35041$1359_Y attribute \src "libresoc.v:35044.19-35044.104" wire $eq$libresoc.v:35044$1362_Y attribute \src "libresoc.v:35045.19-35045.104" wire $eq$libresoc.v:35045$1363_Y attribute \src "libresoc.v:35047.19-35047.104" wire $eq$libresoc.v:35047$1365_Y attribute \src "libresoc.v:35048.19-35048.104" wire $eq$libresoc.v:35048$1366_Y attribute \src "libresoc.v:35050.19-35050.104" wire $eq$libresoc.v:35050$1368_Y attribute \src "libresoc.v:35051.19-35051.104" wire $eq$libresoc.v:35051$1369_Y attribute \src "libresoc.v:35053.18-35053.102" wire $eq$libresoc.v:35053$1371_Y attribute \src "libresoc.v:35054.19-35054.104" wire $eq$libresoc.v:35054$1372_Y attribute \src "libresoc.v:35055.19-35055.104" wire $eq$libresoc.v:35055$1373_Y attribute \src "libresoc.v:35057.19-35057.103" wire $eq$libresoc.v:35057$1375_Y attribute \src "libresoc.v:35058.19-35058.103" wire $eq$libresoc.v:35058$1376_Y attribute \src "libresoc.v:35060.19-35060.103" wire $eq$libresoc.v:35060$1378_Y attribute \src "libresoc.v:35061.19-35061.103" wire $eq$libresoc.v:35061$1379_Y attribute \src "libresoc.v:35063.19-35063.104" wire $eq$libresoc.v:35063$1381_Y attribute \src "libresoc.v:35064.18-35064.102" wire $eq$libresoc.v:35064$1382_Y attribute \src "libresoc.v:35065.19-35065.103" wire $eq$libresoc.v:35065$1383_Y attribute \src "libresoc.v:35067.19-35067.104" wire $eq$libresoc.v:35067$1385_Y attribute \src "libresoc.v:35068.19-35068.104" wire $eq$libresoc.v:35068$1386_Y attribute \src "libresoc.v:35070.19-35070.103" wire $eq$libresoc.v:35070$1388_Y attribute \src "libresoc.v:35071.19-35071.103" wire $eq$libresoc.v:35071$1389_Y attribute \src "libresoc.v:35073.19-35073.103" wire $eq$libresoc.v:35073$1391_Y attribute \src "libresoc.v:35074.19-35074.103" wire $eq$libresoc.v:35074$1392_Y attribute \src "libresoc.v:35077.19-35077.103" wire $eq$libresoc.v:35077$1395_Y attribute \src "libresoc.v:35078.19-35078.103" wire $eq$libresoc.v:35078$1396_Y attribute \src "libresoc.v:35080.17-35080.101" wire $eq$libresoc.v:35080$1398_Y attribute \src "libresoc.v:35081.18-35081.102" wire $eq$libresoc.v:35081$1399_Y attribute \src "libresoc.v:35082.18-35082.102" wire $eq$libresoc.v:35082$1400_Y attribute \src "libresoc.v:35084.18-35084.102" wire $eq$libresoc.v:35084$1402_Y attribute \src "libresoc.v:35085.18-35085.102" wire $eq$libresoc.v:35085$1403_Y attribute \src "libresoc.v:35087.18-35087.103" wire $eq$libresoc.v:35087$1405_Y attribute \src "libresoc.v:35088.18-35088.103" wire $eq$libresoc.v:35088$1406_Y attribute \src "libresoc.v:35090.18-35090.103" wire $eq$libresoc.v:35090$1408_Y attribute \src "libresoc.v:35091.17-35091.101" wire $eq$libresoc.v:35091$1409_Y attribute \src "libresoc.v:35092.18-35092.103" wire $eq$libresoc.v:35092$1410_Y attribute \src "libresoc.v:35094.18-35094.103" wire $eq$libresoc.v:35094$1412_Y attribute \src "libresoc.v:35095.18-35095.103" wire $eq$libresoc.v:35095$1413_Y attribute \src "libresoc.v:35097.18-35097.103" wire $eq$libresoc.v:35097$1415_Y attribute \src "libresoc.v:35098.18-35098.103" wire $eq$libresoc.v:35098$1416_Y attribute \src "libresoc.v:35100.18-35100.103" wire $eq$libresoc.v:35100$1418_Y attribute \src "libresoc.v:35101.18-35101.103" wire $eq$libresoc.v:35101$1419_Y attribute \src "libresoc.v:35104.18-35104.103" wire $eq$libresoc.v:35104$1422_Y attribute \src "libresoc.v:35105.18-35105.103" wire $eq$libresoc.v:35105$1423_Y attribute \src "libresoc.v:35107.18-35107.103" wire $eq$libresoc.v:35107$1425_Y attribute \src "libresoc.v:35108.18-35108.103" wire $eq$libresoc.v:35108$1426_Y attribute \src "libresoc.v:35110.18-35110.103" wire $eq$libresoc.v:35110$1428_Y attribute \src "libresoc.v:35111.18-35111.103" wire $eq$libresoc.v:35111$1429_Y attribute \src "libresoc.v:35113.17-35113.101" wire $eq$libresoc.v:35113$1431_Y attribute \src "libresoc.v:35114.18-35114.103" wire $eq$libresoc.v:35114$1432_Y attribute \src "libresoc.v:35115.18-35115.103" wire $eq$libresoc.v:35115$1433_Y attribute \src "libresoc.v:35117.18-35117.103" wire $eq$libresoc.v:35117$1435_Y attribute \src "libresoc.v:35118.18-35118.103" wire $eq$libresoc.v:35118$1436_Y attribute \src "libresoc.v:35120.18-35120.103" wire $eq$libresoc.v:35120$1438_Y attribute \src "libresoc.v:35121.18-35121.103" wire $eq$libresoc.v:35121$1439_Y attribute \src "libresoc.v:35123.18-35123.102" wire $eq$libresoc.v:35123$1441_Y attribute \src "libresoc.v:35033.19-35033.109" wire width 4 $pos$libresoc.v:35033$1351_Y attribute \src "libresoc.v:35036.19-35036.109" wire width 4 $pos$libresoc.v:35036$1354_Y attribute \src "libresoc.v:35039.19-35039.109" wire width 4 $pos$libresoc.v:35039$1357_Y attribute \src "libresoc.v:35042.18-35042.106" wire width 3 $pos$libresoc.v:35042$1360_Y attribute \src "libresoc.v:35043.19-35043.110" wire width 4 $pos$libresoc.v:35043$1361_Y attribute \src "libresoc.v:35046.19-35046.110" wire width 4 $pos$libresoc.v:35046$1364_Y attribute \src "libresoc.v:35049.19-35049.110" wire width 4 $pos$libresoc.v:35049$1367_Y attribute \src "libresoc.v:35052.19-35052.110" wire width 4 $pos$libresoc.v:35052$1370_Y attribute \src "libresoc.v:35056.19-35056.110" wire width 4 $pos$libresoc.v:35056$1374_Y attribute \src "libresoc.v:35059.19-35059.109" wire width 5 $pos$libresoc.v:35059$1377_Y attribute \src "libresoc.v:35062.19-35062.109" wire width 5 $pos$libresoc.v:35062$1380_Y attribute \src "libresoc.v:35066.19-35066.109" wire width 5 $pos$libresoc.v:35066$1384_Y attribute \src "libresoc.v:35069.19-35069.110" wire width 5 $pos$libresoc.v:35069$1387_Y attribute \src "libresoc.v:35072.19-35072.109" wire width 6 $pos$libresoc.v:35072$1390_Y attribute \src "libresoc.v:35075.18-35075.106" wire width 3 $pos$libresoc.v:35075$1393_Y attribute \src "libresoc.v:35076.19-35076.109" wire width 6 $pos$libresoc.v:35076$1394_Y attribute \src "libresoc.v:35079.19-35079.109" wire width 7 $pos$libresoc.v:35079$1397_Y attribute \src "libresoc.v:35083.18-35083.106" wire width 3 $pos$libresoc.v:35083$1401_Y attribute \src "libresoc.v:35086.18-35086.106" wire width 3 $pos$libresoc.v:35086$1404_Y attribute \src "libresoc.v:35089.18-35089.107" wire width 3 $pos$libresoc.v:35089$1407_Y attribute \src "libresoc.v:35093.18-35093.107" wire width 3 $pos$libresoc.v:35093$1411_Y attribute \src "libresoc.v:35096.18-35096.107" wire width 3 $pos$libresoc.v:35096$1414_Y attribute \src "libresoc.v:35099.18-35099.107" wire width 3 $pos$libresoc.v:35099$1417_Y attribute \src "libresoc.v:35102.17-35102.105" wire width 3 $pos$libresoc.v:35102$1420_Y attribute \src "libresoc.v:35103.18-35103.107" wire width 3 $pos$libresoc.v:35103$1421_Y attribute \src "libresoc.v:35106.18-35106.107" wire width 3 $pos$libresoc.v:35106$1424_Y attribute \src "libresoc.v:35109.18-35109.107" wire width 3 $pos$libresoc.v:35109$1427_Y attribute \src "libresoc.v:35112.18-35112.107" wire width 3 $pos$libresoc.v:35112$1430_Y attribute \src "libresoc.v:35116.18-35116.107" wire width 3 $pos$libresoc.v:35116$1434_Y attribute \src "libresoc.v:35119.18-35119.107" wire width 3 $pos$libresoc.v:35119$1437_Y attribute \src "libresoc.v:35122.18-35122.107" wire width 3 $pos$libresoc.v:35122$1440_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$113 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$133 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$135 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$137 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$139 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$141 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 4 \$143 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$145 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$147 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$149 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$151 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$153 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$155 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$157 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$159 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$161 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$163 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$165 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 5 \$167 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$169 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$171 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 6 \$173 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$177 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 6 \$179 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$181 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 7 \$185 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$35 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" wire width 3 \$95 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" wire \$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" wire width 2 \cnt_1_9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 3 \cnt_2_8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 4 \cnt_3_8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 5 \cnt_4_6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 6 \cnt_5_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 6 \cnt_5_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 7 \cnt_6_0 attribute \src "libresoc.v:34650.7-34650.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 7 output 1 \lz attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair38 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair54 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" wire width 2 \pair8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" wire width 64 input 2 \sig_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35031$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_2 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35031$1349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35032$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_0 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35032$1350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35034$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_6 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35034$1352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35035$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_4 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35035$1353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35037$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_10 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35037$1355_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35038$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_8 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35038$1356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35040$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_14 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35040$1358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35041$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_12 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35041$1359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35044$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_18 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35044$1362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35045$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_16 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35045$1363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35047$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_22 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35047$1365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35048$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_20 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35048$1366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35050$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_26 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35050$1368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35051$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_24 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35051$1369_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35053$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_5 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35053$1371_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35054$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_30 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35054$1372_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35055$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_28 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35055$1373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35057$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_2 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35057$1375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35058$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_0 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35058$1376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35060$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_6 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35060$1378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35061$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_4 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35061$1379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35063$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_10 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35063$1381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35064$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_4 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35064$1382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35065$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_8 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35065$1383_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35067$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_14 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35067$1385_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35068$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_3_12 [3] connect \B 1'1 connect \Y $eq$libresoc.v:35068$1386_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35070$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_4_2 [4] connect \B 1'1 connect \Y $eq$libresoc.v:35070$1388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35071$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_4_0 [4] connect \B 1'1 connect \Y $eq$libresoc.v:35071$1389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35073$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_4_6 [4] connect \B 1'1 connect \Y $eq$libresoc.v:35073$1391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35074$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_4_4 [4] connect \B 1'1 connect \Y $eq$libresoc.v:35074$1392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35077$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_5_2 [5] connect \B 1'1 connect \Y $eq$libresoc.v:35077$1395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35078$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_5_0 [5] connect \B 1'1 connect \Y $eq$libresoc.v:35078$1396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35080$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_1 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35080$1398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35081$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_7 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35081$1399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35082$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_6 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35082$1400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35084$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_9 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35084$1402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35085$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_8 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35085$1403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35087$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_11 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35087$1405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35088$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_10 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35088$1406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35090$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_13 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35090$1408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35091$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_0 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35091$1409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35092$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_12 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35092$1410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35094$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_15 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35094$1412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35095$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_14 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35095$1413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35097$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_17 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35097$1415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35098$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_16 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35098$1416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35100$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_19 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35100$1418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35101$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_18 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35101$1419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35104$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_21 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35104$1422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35105$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_20 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35105$1423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35107$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_23 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35107$1425_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35108$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_22 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35108$1426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35110$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_25 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35110$1428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35111$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_24 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35111$1429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35113$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_3 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35113$1431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35114$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_27 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35114$1432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35115$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_26 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35115$1433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35117$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_29 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35117$1435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35118$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_28 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35118$1436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35120$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_31 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35120$1438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" cell $eq $eq$libresoc.v:35121$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_1_30 [1] connect \B 1'1 connect \Y $eq$libresoc.v:35121$1439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" cell $eq $eq$libresoc.v:35123$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cnt_2_2 [2] connect \B 1'1 connect \Y $eq$libresoc.v:35123$1441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35033$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_0 [1:0] } connect \Y $pos$libresoc.v:35033$1351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35036$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_4 [1:0] } connect \Y $pos$libresoc.v:35036$1354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35039$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_8 [1:0] } connect \Y $pos$libresoc.v:35039$1357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35042$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_2 [0] } connect \Y $pos$libresoc.v:35042$1360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35043$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_12 [1:0] } connect \Y $pos$libresoc.v:35043$1361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35046$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_16 [1:0] } connect \Y $pos$libresoc.v:35046$1364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35049$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_20 [1:0] } connect \Y $pos$libresoc.v:35049$1367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35052$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_24 [1:0] } connect \Y $pos$libresoc.v:35052$1370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35056$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_28 [1:0] } connect \Y $pos$libresoc.v:35056$1374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35059$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_0 [2:0] } connect \Y $pos$libresoc.v:35059$1377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35062$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_4 [2:0] } connect \Y $pos$libresoc.v:35062$1380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35066$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_8 [2:0] } connect \Y $pos$libresoc.v:35066$1384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35069$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_12 [2:0] } connect \Y $pos$libresoc.v:35069$1387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35072$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_0 [3:0] } connect \Y $pos$libresoc.v:35072$1390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35075$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_4 [0] } connect \Y $pos$libresoc.v:35075$1393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35076$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_4 [3:0] } connect \Y $pos$libresoc.v:35076$1394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35079$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'01 \cnt_5_0 [4:0] } connect \Y $pos$libresoc.v:35079$1397_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35083$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_6 [0] } connect \Y $pos$libresoc.v:35083$1401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35086$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_8 [0] } connect \Y $pos$libresoc.v:35086$1404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35089$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_10 [0] } connect \Y $pos$libresoc.v:35089$1407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35093$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_12 [0] } connect \Y $pos$libresoc.v:35093$1411_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35096$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_14 [0] } connect \Y $pos$libresoc.v:35096$1414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35099$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_16 [0] } connect \Y $pos$libresoc.v:35099$1417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35102$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_0 [0] } connect \Y $pos$libresoc.v:35102$1420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35103$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_18 [0] } connect \Y $pos$libresoc.v:35103$1421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35106$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_20 [0] } connect \Y $pos$libresoc.v:35106$1424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35109$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_22 [0] } connect \Y $pos$libresoc.v:35109$1427_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35112$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_24 [0] } connect \Y $pos$libresoc.v:35112$1430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35116$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_26 [0] } connect \Y $pos$libresoc.v:35116$1434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35119$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_28 [0] } connect \Y $pos$libresoc.v:35119$1437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" cell $pos $pos$libresoc.v:35122$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_30 [0] } connect \Y $pos$libresoc.v:35122$1440_Y end attribute \src "libresoc.v:34650.7-34650.20" process $proc$libresoc.v:34650$1505 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:35124.3-35138.6" process $proc$libresoc.v:35124$1442 assign { } { } assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] attribute \src "libresoc.v:35125.5-35125.29" switch \initial attribute \src "libresoc.v:35125.9-35125.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair0 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_0[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_0[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_0[1:0] 2'00 end sync always update \cnt_1_0 $0\cnt_1_0[1:0] end attribute \src "libresoc.v:35139.3-35153.6" process $proc$libresoc.v:35139$1443 assign { } { } assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] attribute \src "libresoc.v:35140.5-35140.29" switch \initial attribute \src "libresoc.v:35140.9-35140.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair10 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_5[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_5[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_5[1:0] 2'00 end sync always update \cnt_1_5 $0\cnt_1_5[1:0] end attribute \src "libresoc.v:35154.3-35168.6" process $proc$libresoc.v:35154$1444 assign { } { } assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] attribute \src "libresoc.v:35155.5-35155.29" switch \initial attribute \src "libresoc.v:35155.9-35155.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair12 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_6[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_6[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_6[1:0] 2'00 end sync always update \cnt_1_6 $0\cnt_1_6[1:0] end attribute \src "libresoc.v:35169.3-35183.6" process $proc$libresoc.v:35169$1445 assign { } { } assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] attribute \src "libresoc.v:35170.5-35170.29" switch \initial attribute \src "libresoc.v:35170.9-35170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair14 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_7[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_7[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_7[1:0] 2'00 end sync always update \cnt_1_7 $0\cnt_1_7[1:0] end attribute \src "libresoc.v:35184.3-35198.6" process $proc$libresoc.v:35184$1446 assign { } { } assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] attribute \src "libresoc.v:35185.5-35185.29" switch \initial attribute \src "libresoc.v:35185.9-35185.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair16 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_8[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_8[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_8[1:0] 2'00 end sync always update \cnt_1_8 $0\cnt_1_8[1:0] end attribute \src "libresoc.v:35199.3-35213.6" process $proc$libresoc.v:35199$1447 assign { } { } assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] attribute \src "libresoc.v:35200.5-35200.29" switch \initial attribute \src "libresoc.v:35200.9-35200.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair18 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_9[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_9[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_9[1:0] 2'00 end sync always update \cnt_1_9 $0\cnt_1_9[1:0] end attribute \src "libresoc.v:35214.3-35228.6" process $proc$libresoc.v:35214$1448 assign { } { } assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] attribute \src "libresoc.v:35215.5-35215.29" switch \initial attribute \src "libresoc.v:35215.9-35215.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair20 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_10[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_10[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_10[1:0] 2'00 end sync always update \cnt_1_10 $0\cnt_1_10[1:0] end attribute \src "libresoc.v:35229.3-35243.6" process $proc$libresoc.v:35229$1449 assign { } { } assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] attribute \src "libresoc.v:35230.5-35230.29" switch \initial attribute \src "libresoc.v:35230.9-35230.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair22 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_11[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_11[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_11[1:0] 2'00 end sync always update \cnt_1_11 $0\cnt_1_11[1:0] end attribute \src "libresoc.v:35244.3-35258.6" process $proc$libresoc.v:35244$1450 assign { } { } assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] attribute \src "libresoc.v:35245.5-35245.29" switch \initial attribute \src "libresoc.v:35245.9-35245.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair24 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_12[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_12[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_12[1:0] 2'00 end sync always update \cnt_1_12 $0\cnt_1_12[1:0] end attribute \src "libresoc.v:35259.3-35273.6" process $proc$libresoc.v:35259$1451 assign { } { } assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] attribute \src "libresoc.v:35260.5-35260.29" switch \initial attribute \src "libresoc.v:35260.9-35260.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair26 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_13[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_13[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_13[1:0] 2'00 end sync always update \cnt_1_13 $0\cnt_1_13[1:0] end attribute \src "libresoc.v:35274.3-35288.6" process $proc$libresoc.v:35274$1452 assign { } { } assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] attribute \src "libresoc.v:35275.5-35275.29" switch \initial attribute \src "libresoc.v:35275.9-35275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair28 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_14[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_14[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_14[1:0] 2'00 end sync always update \cnt_1_14 $0\cnt_1_14[1:0] end attribute \src "libresoc.v:35289.3-35303.6" process $proc$libresoc.v:35289$1453 assign { } { } assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] attribute \src "libresoc.v:35290.5-35290.29" switch \initial attribute \src "libresoc.v:35290.9-35290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair2 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_1[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_1[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_1[1:0] 2'00 end sync always update \cnt_1_1 $0\cnt_1_1[1:0] end attribute \src "libresoc.v:35304.3-35318.6" process $proc$libresoc.v:35304$1454 assign { } { } assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] attribute \src "libresoc.v:35305.5-35305.29" switch \initial attribute \src "libresoc.v:35305.9-35305.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair30 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_15[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_15[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_15[1:0] 2'00 end sync always update \cnt_1_15 $0\cnt_1_15[1:0] end attribute \src "libresoc.v:35319.3-35333.6" process $proc$libresoc.v:35319$1455 assign { } { } assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] attribute \src "libresoc.v:35320.5-35320.29" switch \initial attribute \src "libresoc.v:35320.9-35320.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair32 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_16[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_16[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_16[1:0] 2'00 end sync always update \cnt_1_16 $0\cnt_1_16[1:0] end attribute \src "libresoc.v:35334.3-35348.6" process $proc$libresoc.v:35334$1456 assign { } { } assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] attribute \src "libresoc.v:35335.5-35335.29" switch \initial attribute \src "libresoc.v:35335.9-35335.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair34 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_17[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_17[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_17[1:0] 2'00 end sync always update \cnt_1_17 $0\cnt_1_17[1:0] end attribute \src "libresoc.v:35349.3-35363.6" process $proc$libresoc.v:35349$1457 assign { } { } assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] attribute \src "libresoc.v:35350.5-35350.29" switch \initial attribute \src "libresoc.v:35350.9-35350.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair36 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_18[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_18[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_18[1:0] 2'00 end sync always update \cnt_1_18 $0\cnt_1_18[1:0] end attribute \src "libresoc.v:35364.3-35378.6" process $proc$libresoc.v:35364$1458 assign { } { } assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] attribute \src "libresoc.v:35365.5-35365.29" switch \initial attribute \src "libresoc.v:35365.9-35365.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair38 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_19[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_19[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_19[1:0] 2'00 end sync always update \cnt_1_19 $0\cnt_1_19[1:0] end attribute \src "libresoc.v:35379.3-35393.6" process $proc$libresoc.v:35379$1459 assign { } { } assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] attribute \src "libresoc.v:35380.5-35380.29" switch \initial attribute \src "libresoc.v:35380.9-35380.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair40 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_20[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_20[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_20[1:0] 2'00 end sync always update \cnt_1_20 $0\cnt_1_20[1:0] end attribute \src "libresoc.v:35394.3-35408.6" process $proc$libresoc.v:35394$1460 assign { } { } assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] attribute \src "libresoc.v:35395.5-35395.29" switch \initial attribute \src "libresoc.v:35395.9-35395.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair42 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_21[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_21[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_21[1:0] 2'00 end sync always update \cnt_1_21 $0\cnt_1_21[1:0] end attribute \src "libresoc.v:35409.3-35423.6" process $proc$libresoc.v:35409$1461 assign { } { } assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] attribute \src "libresoc.v:35410.5-35410.29" switch \initial attribute \src "libresoc.v:35410.9-35410.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair44 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_22[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_22[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_22[1:0] 2'00 end sync always update \cnt_1_22 $0\cnt_1_22[1:0] end attribute \src "libresoc.v:35424.3-35438.6" process $proc$libresoc.v:35424$1462 assign { } { } assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] attribute \src "libresoc.v:35425.5-35425.29" switch \initial attribute \src "libresoc.v:35425.9-35425.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair46 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_23[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_23[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_23[1:0] 2'00 end sync always update \cnt_1_23 $0\cnt_1_23[1:0] end attribute \src "libresoc.v:35439.3-35453.6" process $proc$libresoc.v:35439$1463 assign { } { } assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] attribute \src "libresoc.v:35440.5-35440.29" switch \initial attribute \src "libresoc.v:35440.9-35440.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair48 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_24[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_24[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_24[1:0] 2'00 end sync always update \cnt_1_24 $0\cnt_1_24[1:0] end attribute \src "libresoc.v:35454.3-35468.6" process $proc$libresoc.v:35454$1464 assign { } { } assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] attribute \src "libresoc.v:35455.5-35455.29" switch \initial attribute \src "libresoc.v:35455.9-35455.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair4 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_2[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_2[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_2[1:0] 2'00 end sync always update \cnt_1_2 $0\cnt_1_2[1:0] end attribute \src "libresoc.v:35469.3-35483.6" process $proc$libresoc.v:35469$1465 assign { } { } assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] attribute \src "libresoc.v:35470.5-35470.29" switch \initial attribute \src "libresoc.v:35470.9-35470.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair50 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_25[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_25[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_25[1:0] 2'00 end sync always update \cnt_1_25 $0\cnt_1_25[1:0] end attribute \src "libresoc.v:35484.3-35498.6" process $proc$libresoc.v:35484$1466 assign { } { } assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] attribute \src "libresoc.v:35485.5-35485.29" switch \initial attribute \src "libresoc.v:35485.9-35485.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair52 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_26[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_26[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_26[1:0] 2'00 end sync always update \cnt_1_26 $0\cnt_1_26[1:0] end attribute \src "libresoc.v:35499.3-35513.6" process $proc$libresoc.v:35499$1467 assign { } { } assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] attribute \src "libresoc.v:35500.5-35500.29" switch \initial attribute \src "libresoc.v:35500.9-35500.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair54 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_27[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_27[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_27[1:0] 2'00 end sync always update \cnt_1_27 $0\cnt_1_27[1:0] end attribute \src "libresoc.v:35514.3-35528.6" process $proc$libresoc.v:35514$1468 assign { } { } assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] attribute \src "libresoc.v:35515.5-35515.29" switch \initial attribute \src "libresoc.v:35515.9-35515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair56 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_28[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_28[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_28[1:0] 2'00 end sync always update \cnt_1_28 $0\cnt_1_28[1:0] end attribute \src "libresoc.v:35529.3-35543.6" process $proc$libresoc.v:35529$1469 assign { } { } assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] attribute \src "libresoc.v:35530.5-35530.29" switch \initial attribute \src "libresoc.v:35530.9-35530.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair58 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_29[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_29[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_29[1:0] 2'00 end sync always update \cnt_1_29 $0\cnt_1_29[1:0] end attribute \src "libresoc.v:35544.3-35558.6" process $proc$libresoc.v:35544$1470 assign { } { } assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] attribute \src "libresoc.v:35545.5-35545.29" switch \initial attribute \src "libresoc.v:35545.9-35545.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair60 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_30[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_30[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_30[1:0] 2'00 end sync always update \cnt_1_30 $0\cnt_1_30[1:0] end attribute \src "libresoc.v:35559.3-35573.6" process $proc$libresoc.v:35559$1471 assign { } { } assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] attribute \src "libresoc.v:35560.5-35560.29" switch \initial attribute \src "libresoc.v:35560.9-35560.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair62 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_31[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_31[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_31[1:0] 2'00 end sync always update \cnt_1_31 $0\cnt_1_31[1:0] end attribute \src "libresoc.v:35574.3-35593.6" process $proc$libresoc.v:35574$1472 assign { } { } assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] attribute \src "libresoc.v:35575.5-35575.29" switch \initial attribute \src "libresoc.v:35575.9-35575.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_0[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_0[2:0] \$5 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } end sync always update \cnt_2_0 $0\cnt_2_0[2:0] end attribute \src "libresoc.v:35594.3-35613.6" process $proc$libresoc.v:35594$1473 assign { } { } assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] attribute \src "libresoc.v:35595.5-35595.29" switch \initial attribute \src "libresoc.v:35595.9-35595.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_2[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_2[2:0] \$11 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } end sync always update \cnt_2_2 $0\cnt_2_2[2:0] end attribute \src "libresoc.v:35614.3-35633.6" process $proc$libresoc.v:35614$1474 assign { } { } assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] attribute \src "libresoc.v:35615.5-35615.29" switch \initial attribute \src "libresoc.v:35615.9-35615.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_4[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_4[2:0] \$17 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } end sync always update \cnt_2_4 $0\cnt_2_4[2:0] end attribute \src "libresoc.v:35634.3-35653.6" process $proc$libresoc.v:35634$1475 assign { } { } assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] attribute \src "libresoc.v:35635.5-35635.29" switch \initial attribute \src "libresoc.v:35635.9-35635.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_6[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_6[2:0] \$23 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } end sync always update \cnt_2_6 $0\cnt_2_6[2:0] end attribute \src "libresoc.v:35654.3-35673.6" process $proc$libresoc.v:35654$1476 assign { } { } assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] attribute \src "libresoc.v:35655.5-35655.29" switch \initial attribute \src "libresoc.v:35655.9-35655.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_8[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_8[2:0] \$29 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } end sync always update \cnt_2_8 $0\cnt_2_8[2:0] end attribute \src "libresoc.v:35674.3-35693.6" process $proc$libresoc.v:35674$1477 assign { } { } assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] attribute \src "libresoc.v:35675.5-35675.29" switch \initial attribute \src "libresoc.v:35675.9-35675.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_10[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_10[2:0] \$35 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } end sync always update \cnt_2_10 $0\cnt_2_10[2:0] end attribute \src "libresoc.v:35694.3-35708.6" process $proc$libresoc.v:35694$1478 assign { } { } assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] attribute \src "libresoc.v:35695.5-35695.29" switch \initial attribute \src "libresoc.v:35695.9-35695.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair6 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_3[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_3[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_3[1:0] 2'00 end sync always update \cnt_1_3 $0\cnt_1_3[1:0] end attribute \src "libresoc.v:35709.3-35728.6" process $proc$libresoc.v:35709$1479 assign { } { } assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] attribute \src "libresoc.v:35710.5-35710.29" switch \initial attribute \src "libresoc.v:35710.9-35710.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_12[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_12[2:0] \$41 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } end sync always update \cnt_2_12 $0\cnt_2_12[2:0] end attribute \src "libresoc.v:35729.3-35748.6" process $proc$libresoc.v:35729$1480 assign { } { } assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] attribute \src "libresoc.v:35730.5-35730.29" switch \initial attribute \src "libresoc.v:35730.9-35730.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_14[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_14[2:0] \$47 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } end sync always update \cnt_2_14 $0\cnt_2_14[2:0] end attribute \src "libresoc.v:35749.3-35768.6" process $proc$libresoc.v:35749$1481 assign { } { } assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] attribute \src "libresoc.v:35750.5-35750.29" switch \initial attribute \src "libresoc.v:35750.9-35750.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$51 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_16[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_16[2:0] \$53 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } end sync always update \cnt_2_16 $0\cnt_2_16[2:0] end attribute \src "libresoc.v:35769.3-35788.6" process $proc$libresoc.v:35769$1482 assign { } { } assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] attribute \src "libresoc.v:35770.5-35770.29" switch \initial attribute \src "libresoc.v:35770.9-35770.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_18[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_18[2:0] \$59 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } end sync always update \cnt_2_18 $0\cnt_2_18[2:0] end attribute \src "libresoc.v:35789.3-35808.6" process $proc$libresoc.v:35789$1483 assign { } { } assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] attribute \src "libresoc.v:35790.5-35790.29" switch \initial attribute \src "libresoc.v:35790.9-35790.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_20[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_20[2:0] \$65 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } end sync always update \cnt_2_20 $0\cnt_2_20[2:0] end attribute \src "libresoc.v:35809.3-35828.6" process $proc$libresoc.v:35809$1484 assign { } { } assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] attribute \src "libresoc.v:35810.5-35810.29" switch \initial attribute \src "libresoc.v:35810.9-35810.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_22[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_22[2:0] \$71 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } end sync always update \cnt_2_22 $0\cnt_2_22[2:0] end attribute \src "libresoc.v:35829.3-35848.6" process $proc$libresoc.v:35829$1485 assign { } { } assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] attribute \src "libresoc.v:35830.5-35830.29" switch \initial attribute \src "libresoc.v:35830.9-35830.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$75 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_24[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_24[2:0] \$77 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } end sync always update \cnt_2_24 $0\cnt_2_24[2:0] end attribute \src "libresoc.v:35849.3-35868.6" process $proc$libresoc.v:35849$1486 assign { } { } assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] attribute \src "libresoc.v:35850.5-35850.29" switch \initial attribute \src "libresoc.v:35850.9-35850.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$79 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_26[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_26[2:0] \$83 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } end sync always update \cnt_2_26 $0\cnt_2_26[2:0] end attribute \src "libresoc.v:35869.3-35888.6" process $proc$libresoc.v:35869$1487 assign { } { } assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] attribute \src "libresoc.v:35870.5-35870.29" switch \initial attribute \src "libresoc.v:35870.9-35870.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_28[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_28[2:0] \$89 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } end sync always update \cnt_2_28 $0\cnt_2_28[2:0] end attribute \src "libresoc.v:35889.3-35908.6" process $proc$libresoc.v:35889$1488 assign { } { } assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] attribute \src "libresoc.v:35890.5-35890.29" switch \initial attribute \src "libresoc.v:35890.9-35890.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$91 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_2_30[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_2_30[2:0] \$95 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } end sync always update \cnt_2_30 $0\cnt_2_30[2:0] end attribute \src "libresoc.v:35909.3-35928.6" process $proc$libresoc.v:35909$1489 assign { } { } assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] attribute \src "libresoc.v:35910.5-35910.29" switch \initial attribute \src "libresoc.v:35910.9-35910.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$97 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$99 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_0[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_0[3:0] \$101 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } end sync always update \cnt_3_0 $0\cnt_3_0[3:0] end attribute \src "libresoc.v:35929.3-35948.6" process $proc$libresoc.v:35929$1490 assign { } { } assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] attribute \src "libresoc.v:35930.5-35930.29" switch \initial attribute \src "libresoc.v:35930.9-35930.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_2[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_2[3:0] \$107 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } end sync always update \cnt_3_2 $0\cnt_3_2[3:0] end attribute \src "libresoc.v:35949.3-35968.6" process $proc$libresoc.v:35949$1491 assign { } { } assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] attribute \src "libresoc.v:35950.5-35950.29" switch \initial attribute \src "libresoc.v:35950.9-35950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_4[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_4[3:0] \$113 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } end sync always update \cnt_3_4 $0\cnt_3_4[3:0] end attribute \src "libresoc.v:35969.3-35988.6" process $proc$libresoc.v:35969$1492 assign { } { } assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] attribute \src "libresoc.v:35970.5-35970.29" switch \initial attribute \src "libresoc.v:35970.9-35970.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_6[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_6[3:0] \$119 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } end sync always update \cnt_3_6 $0\cnt_3_6[3:0] end attribute \src "libresoc.v:35989.3-36008.6" process $proc$libresoc.v:35989$1493 assign { } { } assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] attribute \src "libresoc.v:35990.5-35990.29" switch \initial attribute \src "libresoc.v:35990.9-35990.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_8[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_8[3:0] \$125 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } end sync always update \cnt_3_8 $0\cnt_3_8[3:0] end attribute \src "libresoc.v:36009.3-36028.6" process $proc$libresoc.v:36009$1494 assign { } { } assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] attribute \src "libresoc.v:36010.5-36010.29" switch \initial attribute \src "libresoc.v:36010.9-36010.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_10[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_10[3:0] \$131 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } end sync always update \cnt_3_10 $0\cnt_3_10[3:0] end attribute \src "libresoc.v:36029.3-36048.6" process $proc$libresoc.v:36029$1495 assign { } { } assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] attribute \src "libresoc.v:36030.5-36030.29" switch \initial attribute \src "libresoc.v:36030.9-36030.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_12[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_12[3:0] \$137 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } end sync always update \cnt_3_12 $0\cnt_3_12[3:0] end attribute \src "libresoc.v:36049.3-36068.6" process $proc$libresoc.v:36049$1496 assign { } { } assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] attribute \src "libresoc.v:36050.5-36050.29" switch \initial attribute \src "libresoc.v:36050.9-36050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$139 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$141 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_3_14[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_3_14[3:0] \$143 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } end sync always update \cnt_3_14 $0\cnt_3_14[3:0] end attribute \src "libresoc.v:36069.3-36088.6" process $proc$libresoc.v:36069$1497 assign { } { } assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] attribute \src "libresoc.v:36070.5-36070.29" switch \initial attribute \src "libresoc.v:36070.9-36070.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$145 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$147 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_4_0[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_4_0[4:0] \$149 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } end sync always update \cnt_4_0 $0\cnt_4_0[4:0] end attribute \src "libresoc.v:36089.3-36108.6" process $proc$libresoc.v:36089$1498 assign { } { } assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] attribute \src "libresoc.v:36090.5-36090.29" switch \initial attribute \src "libresoc.v:36090.9-36090.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$151 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$153 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_4_2[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_4_2[4:0] \$155 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } end sync always update \cnt_4_2 $0\cnt_4_2[4:0] end attribute \src "libresoc.v:36109.3-36123.6" process $proc$libresoc.v:36109$1499 assign { } { } assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] attribute \src "libresoc.v:36110.5-36110.29" switch \initial attribute \src "libresoc.v:36110.9-36110.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" switch \pair8 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cnt_1_4[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cnt_1_4[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_1_4[1:0] 2'00 end sync always update \cnt_1_4 $0\cnt_1_4[1:0] end attribute \src "libresoc.v:36124.3-36143.6" process $proc$libresoc.v:36124$1500 assign { } { } assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] attribute \src "libresoc.v:36125.5-36125.29" switch \initial attribute \src "libresoc.v:36125.9-36125.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$157 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$159 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_4_4[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_4_4[4:0] \$161 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } end sync always update \cnt_4_4 $0\cnt_4_4[4:0] end attribute \src "libresoc.v:36144.3-36163.6" process $proc$libresoc.v:36144$1501 assign { } { } assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] attribute \src "libresoc.v:36145.5-36145.29" switch \initial attribute \src "libresoc.v:36145.9-36145.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$163 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$165 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_4_6[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_4_6[4:0] \$167 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } end sync always update \cnt_4_6 $0\cnt_4_6[4:0] end attribute \src "libresoc.v:36164.3-36183.6" process $proc$libresoc.v:36164$1502 assign { } { } assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] attribute \src "libresoc.v:36165.5-36165.29" switch \initial attribute \src "libresoc.v:36165.9-36165.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$169 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$171 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_5_0[5:0] 6'100000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_5_0[5:0] \$173 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } end sync always update \cnt_5_0 $0\cnt_5_0[5:0] end attribute \src "libresoc.v:36184.3-36203.6" process $proc$libresoc.v:36184$1503 assign { } { } assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] attribute \src "libresoc.v:36185.5-36185.29" switch \initial attribute \src "libresoc.v:36185.9-36185.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$175 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$177 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_5_2[5:0] 6'100000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_5_2[5:0] \$179 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } end sync always update \cnt_5_2 $0\cnt_5_2[5:0] end attribute \src "libresoc.v:36204.3-36223.6" process $proc$libresoc.v:36204$1504 assign { } { } assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] attribute \src "libresoc.v:36205.5-36205.29" switch \initial attribute \src "libresoc.v:36205.9-36205.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" switch \$181 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" switch \$183 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cnt_6_0[6:0] 7'1000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cnt_6_0[6:0] \$185 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } end sync always update \cnt_6_0 $0\cnt_6_0[6:0] end connect \$9 $eq$libresoc.v:35031$1349_Y connect \$99 $eq$libresoc.v:35032$1350_Y connect \$101 $pos$libresoc.v:35033$1351_Y connect \$103 $eq$libresoc.v:35034$1352_Y connect \$105 $eq$libresoc.v:35035$1353_Y connect \$107 $pos$libresoc.v:35036$1354_Y connect \$109 $eq$libresoc.v:35037$1355_Y connect \$111 $eq$libresoc.v:35038$1356_Y connect \$113 $pos$libresoc.v:35039$1357_Y connect \$115 $eq$libresoc.v:35040$1358_Y connect \$117 $eq$libresoc.v:35041$1359_Y connect \$11 $pos$libresoc.v:35042$1360_Y connect \$119 $pos$libresoc.v:35043$1361_Y connect \$121 $eq$libresoc.v:35044$1362_Y connect \$123 $eq$libresoc.v:35045$1363_Y connect \$125 $pos$libresoc.v:35046$1364_Y connect \$127 $eq$libresoc.v:35047$1365_Y connect \$129 $eq$libresoc.v:35048$1366_Y connect \$131 $pos$libresoc.v:35049$1367_Y connect \$133 $eq$libresoc.v:35050$1368_Y connect \$135 $eq$libresoc.v:35051$1369_Y connect \$137 $pos$libresoc.v:35052$1370_Y connect \$13 $eq$libresoc.v:35053$1371_Y connect \$139 $eq$libresoc.v:35054$1372_Y connect \$141 $eq$libresoc.v:35055$1373_Y connect \$143 $pos$libresoc.v:35056$1374_Y connect \$145 $eq$libresoc.v:35057$1375_Y connect \$147 $eq$libresoc.v:35058$1376_Y connect \$149 $pos$libresoc.v:35059$1377_Y connect \$151 $eq$libresoc.v:35060$1378_Y connect \$153 $eq$libresoc.v:35061$1379_Y connect \$155 $pos$libresoc.v:35062$1380_Y connect \$157 $eq$libresoc.v:35063$1381_Y connect \$15 $eq$libresoc.v:35064$1382_Y connect \$159 $eq$libresoc.v:35065$1383_Y connect \$161 $pos$libresoc.v:35066$1384_Y connect \$163 $eq$libresoc.v:35067$1385_Y connect \$165 $eq$libresoc.v:35068$1386_Y connect \$167 $pos$libresoc.v:35069$1387_Y connect \$169 $eq$libresoc.v:35070$1388_Y connect \$171 $eq$libresoc.v:35071$1389_Y connect \$173 $pos$libresoc.v:35072$1390_Y connect \$175 $eq$libresoc.v:35073$1391_Y connect \$177 $eq$libresoc.v:35074$1392_Y connect \$17 $pos$libresoc.v:35075$1393_Y connect \$179 $pos$libresoc.v:35076$1394_Y connect \$181 $eq$libresoc.v:35077$1395_Y connect \$183 $eq$libresoc.v:35078$1396_Y connect \$185 $pos$libresoc.v:35079$1397_Y connect \$1 $eq$libresoc.v:35080$1398_Y connect \$19 $eq$libresoc.v:35081$1399_Y connect \$21 $eq$libresoc.v:35082$1400_Y connect \$23 $pos$libresoc.v:35083$1401_Y connect \$25 $eq$libresoc.v:35084$1402_Y connect \$27 $eq$libresoc.v:35085$1403_Y connect \$29 $pos$libresoc.v:35086$1404_Y connect \$31 $eq$libresoc.v:35087$1405_Y connect \$33 $eq$libresoc.v:35088$1406_Y connect \$35 $pos$libresoc.v:35089$1407_Y connect \$37 $eq$libresoc.v:35090$1408_Y connect \$3 $eq$libresoc.v:35091$1409_Y connect \$39 $eq$libresoc.v:35092$1410_Y connect \$41 $pos$libresoc.v:35093$1411_Y connect \$43 $eq$libresoc.v:35094$1412_Y connect \$45 $eq$libresoc.v:35095$1413_Y connect \$47 $pos$libresoc.v:35096$1414_Y connect \$49 $eq$libresoc.v:35097$1415_Y connect \$51 $eq$libresoc.v:35098$1416_Y connect \$53 $pos$libresoc.v:35099$1417_Y connect \$55 $eq$libresoc.v:35100$1418_Y connect \$57 $eq$libresoc.v:35101$1419_Y connect \$5 $pos$libresoc.v:35102$1420_Y connect \$59 $pos$libresoc.v:35103$1421_Y connect \$61 $eq$libresoc.v:35104$1422_Y connect \$63 $eq$libresoc.v:35105$1423_Y connect \$65 $pos$libresoc.v:35106$1424_Y connect \$67 $eq$libresoc.v:35107$1425_Y connect \$69 $eq$libresoc.v:35108$1426_Y connect \$71 $pos$libresoc.v:35109$1427_Y connect \$73 $eq$libresoc.v:35110$1428_Y connect \$75 $eq$libresoc.v:35111$1429_Y connect \$77 $pos$libresoc.v:35112$1430_Y connect \$7 $eq$libresoc.v:35113$1431_Y connect \$79 $eq$libresoc.v:35114$1432_Y connect \$81 $eq$libresoc.v:35115$1433_Y connect \$83 $pos$libresoc.v:35116$1434_Y connect \$85 $eq$libresoc.v:35117$1435_Y connect \$87 $eq$libresoc.v:35118$1436_Y connect \$89 $pos$libresoc.v:35119$1437_Y connect \$91 $eq$libresoc.v:35120$1438_Y connect \$93 $eq$libresoc.v:35121$1439_Y connect \$95 $pos$libresoc.v:35122$1440_Y connect \$97 $eq$libresoc.v:35123$1441_Y connect \lz \cnt_6_0 connect \pair62 \sig_in [63:62] connect \pair60 \sig_in [61:60] connect \pair58 \sig_in [59:58] connect \pair56 \sig_in [57:56] connect \pair54 \sig_in [55:54] connect \pair52 \sig_in [53:52] connect \pair50 \sig_in [51:50] connect \pair48 \sig_in [49:48] connect \pair46 \sig_in [47:46] connect \pair44 \sig_in [45:44] connect \pair42 \sig_in [43:42] connect \pair40 \sig_in [41:40] connect \pair38 \sig_in [39:38] connect \pair36 \sig_in [37:36] connect \pair34 \sig_in [35:34] connect \pair32 \sig_in [33:32] connect \pair30 \sig_in [31:30] connect \pair28 \sig_in [29:28] connect \pair26 \sig_in [27:26] connect \pair24 \sig_in [25:24] connect \pair22 \sig_in [23:22] connect \pair20 \sig_in [21:20] connect \pair18 \sig_in [19:18] connect \pair16 \sig_in [17:16] connect \pair14 \sig_in [15:14] connect \pair12 \sig_in [13:12] connect \pair10 \sig_in [11:10] connect \pair8 \sig_in [9:8] connect \pair6 \sig_in [7:6] connect \pair4 \sig_in [5:4] connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end attribute \src "libresoc.v:36261.1-48917.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core attribute \src "libresoc.v:46390.3-46410.6" wire $0\core_terminate_o$next[0:0]$2679 attribute \src "libresoc.v:42786.3-42787.49" wire $0\core_terminate_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $0\corebusy_o[0:0] attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $0\counter$next[1:0]$2657 attribute \src "libresoc.v:42788.3-42789.31" wire width 2 $0\counter[1:0] attribute \src "libresoc.v:46192.3-46200.6" wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 attribute \src "libresoc.v:42722.3-42723.57" wire $0\dp_CR_cr_a_branch0_1[0:0] attribute \src "libresoc.v:46173.3-46181.6" wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 attribute \src "libresoc.v:42724.3-42725.49" wire $0\dp_CR_cr_a_cr0_0[0:0] attribute \src "libresoc.v:46211.3-46219.6" wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 attribute \src "libresoc.v:42720.3-42721.49" wire $0\dp_CR_cr_b_cr0_0[0:0] attribute \src "libresoc.v:46261.3-46269.6" wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 attribute \src "libresoc.v:42718.3-42719.49" wire $0\dp_CR_cr_c_cr0_0[0:0] attribute \src "libresoc.v:46154.3-46162.6" wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 attribute \src "libresoc.v:42726.3-42727.55" wire $0\dp_CR_full_cr_cr0_0[0:0] attribute \src "libresoc.v:46371.3-46379.6" wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 attribute \src "libresoc.v:42716.3-42717.63" wire $0\dp_FAST_fast1_branch0_0[0:0] attribute \src "libresoc.v:46478.3-46486.6" wire $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 attribute \src "libresoc.v:42710.3-42711.63" wire $0\dp_FAST_fast1_branch0_3[0:0] attribute \src "libresoc.v:46430.3-46438.6" wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 attribute \src "libresoc.v:42712.3-42713.57" wire $0\dp_FAST_fast1_spr0_2[0:0] attribute \src "libresoc.v:46411.3-46419.6" wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 attribute \src "libresoc.v:42714.3-42715.59" wire $0\dp_FAST_fast1_trap0_1[0:0] attribute \src "libresoc.v:46497.3-46505.6" wire $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 attribute \src "libresoc.v:42708.3-42709.59" wire $0\dp_FAST_fast1_trap0_4[0:0] attribute \src "libresoc.v:45603.3-45611.6" wire $0\dp_INT_rabc_alu0_0$next[0:0]$2474 attribute \src "libresoc.v:42784.3-42785.53" wire $0\dp_INT_rabc_alu0_0[0:0] attribute \src "libresoc.v:45793.3-45801.6" wire $0\dp_INT_rabc_alu0_10$next[0:0]$2530 attribute \src "libresoc.v:42764.3-42765.55" wire $0\dp_INT_rabc_alu0_10[0:0] attribute \src "libresoc.v:45622.3-45630.6" wire $0\dp_INT_rabc_cr0_1$next[0:0]$2478 attribute \src "libresoc.v:45812.3-45820.6" wire $0\dp_INT_rabc_cr0_11$next[0:0]$2534 attribute \src "libresoc.v:42762.3-42763.53" wire $0\dp_INT_rabc_cr0_11[0:0] attribute \src "libresoc.v:42782.3-42783.51" wire $0\dp_INT_rabc_cr0_1[0:0] attribute \src "libresoc.v:45888.3-45896.6" wire $0\dp_INT_rabc_div0_15$next[0:0]$2558 attribute \src "libresoc.v:42754.3-42755.55" wire $0\dp_INT_rabc_div0_15[0:0] attribute \src "libresoc.v:45679.3-45687.6" wire $0\dp_INT_rabc_div0_4$next[0:0]$2496 attribute \src "libresoc.v:42776.3-42777.53" wire $0\dp_INT_rabc_div0_4[0:0] attribute \src "libresoc.v:45945.3-45953.6" wire $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 attribute \src "libresoc.v:42748.3-42749.57" wire $0\dp_INT_rabc_ldst0_18[0:0] attribute \src "libresoc.v:45736.3-45744.6" wire $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 attribute \src "libresoc.v:42770.3-42771.55" wire $0\dp_INT_rabc_ldst0_7[0:0] attribute \src "libresoc.v:45774.3-45782.6" wire $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 attribute \src "libresoc.v:42766.3-42767.55" wire $0\dp_INT_rabc_ldst0_9[0:0] attribute \src "libresoc.v:45850.3-45858.6" wire $0\dp_INT_rabc_logical0_13$next[0:0]$2546 attribute \src "libresoc.v:42758.3-42759.63" wire $0\dp_INT_rabc_logical0_13[0:0] attribute \src "libresoc.v:45660.3-45668.6" wire $0\dp_INT_rabc_logical0_3$next[0:0]$2490 attribute \src "libresoc.v:42778.3-42779.61" wire $0\dp_INT_rabc_logical0_3[0:0] attribute \src "libresoc.v:45907.3-45915.6" wire $0\dp_INT_rabc_mul0_16$next[0:0]$2564 attribute \src "libresoc.v:42752.3-42753.55" wire $0\dp_INT_rabc_mul0_16[0:0] attribute \src "libresoc.v:45698.3-45706.6" wire $0\dp_INT_rabc_mul0_5$next[0:0]$2502 attribute \src "libresoc.v:42774.3-42775.53" wire $0\dp_INT_rabc_mul0_5[0:0] attribute \src "libresoc.v:45926.3-45934.6" wire $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 attribute \src "libresoc.v:42750.3-42751.65" wire $0\dp_INT_rabc_shiftrot0_17[0:0] attribute \src "libresoc.v:45717.3-45725.6" wire $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 attribute \src "libresoc.v:42772.3-42773.63" wire $0\dp_INT_rabc_shiftrot0_6[0:0] attribute \src "libresoc.v:45755.3-45763.6" wire $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 attribute \src "libresoc.v:42768.3-42769.63" wire $0\dp_INT_rabc_shiftrot0_8[0:0] attribute \src "libresoc.v:45869.3-45877.6" wire $0\dp_INT_rabc_spr0_14$next[0:0]$2552 attribute \src "libresoc.v:42756.3-42757.55" wire $0\dp_INT_rabc_spr0_14[0:0] attribute \src "libresoc.v:45831.3-45839.6" wire $0\dp_INT_rabc_trap0_12$next[0:0]$2540 attribute \src "libresoc.v:42760.3-42761.57" wire $0\dp_INT_rabc_trap0_12[0:0] attribute \src "libresoc.v:45641.3-45649.6" wire $0\dp_INT_rabc_trap0_2$next[0:0]$2484 attribute \src "libresoc.v:42780.3-42781.55" wire $0\dp_INT_rabc_trap0_2[0:0] attribute \src "libresoc.v:46545.3-46553.6" wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 attribute \src "libresoc.v:42706.3-42707.53" wire $0\dp_SPR_spr1_spr0_0[0:0] attribute \src "libresoc.v:46078.3-46086.6" wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 attribute \src "libresoc.v:42734.3-42735.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] attribute \src "libresoc.v:46116.3-46124.6" wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 attribute \src "libresoc.v:42730.3-42731.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] attribute \src "libresoc.v:46097.3-46105.6" wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 attribute \src "libresoc.v:42732.3-42733.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] attribute \src "libresoc.v:46135.3-46143.6" wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 attribute \src "libresoc.v:42728.3-42729.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] attribute \src "libresoc.v:45964.3-45972.6" wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 attribute \src "libresoc.v:42746.3-42747.57" wire $0\dp_XER_xer_so_alu0_0[0:0] attribute \src "libresoc.v:46021.3-46029.6" wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598 attribute \src "libresoc.v:42740.3-42741.57" wire $0\dp_XER_xer_so_div0_3[0:0] attribute \src "libresoc.v:45983.3-45991.6" wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 attribute \src "libresoc.v:42744.3-42745.65" wire $0\dp_XER_xer_so_logical0_1[0:0] attribute \src "libresoc.v:46040.3-46048.6" wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 attribute \src "libresoc.v:42738.3-42739.57" wire $0\dp_XER_xer_so_mul0_4[0:0] attribute \src "libresoc.v:46059.3-46067.6" wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 attribute \src "libresoc.v:42736.3-42737.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] attribute \src "libresoc.v:46002.3-46010.6" wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 attribute \src "libresoc.v:42742.3-42743.57" wire $0\dp_XER_xer_so_spr0_2[0:0] attribute \src "libresoc.v:47359.3-47387.6" wire $0\fus_cu_issue_i$13[0:0]$2824 attribute \src "libresoc.v:47684.3-47712.6" wire $0\fus_cu_issue_i$16[0:0]$2862 attribute \src "libresoc.v:48003.3-48031.6" wire $0\fus_cu_issue_i$19[0:0]$2881 attribute \src "libresoc.v:43648.3-43676.6" wire $0\fus_cu_issue_i$22[0:0]$2359 attribute \src "libresoc.v:43822.3-43850.6" wire $0\fus_cu_issue_i$25[0:0]$2373 attribute \src "libresoc.v:44318.3-44346.6" wire $0\fus_cu_issue_i$28[0:0]$2398 attribute \src "libresoc.v:44640.3-44668.6" wire $0\fus_cu_issue_i$31[0:0]$2417 attribute \src "libresoc.v:45107.3-45135.6" wire $0\fus_cu_issue_i$34[0:0]$2441 attribute \src "libresoc.v:45545.3-45573.6" wire $0\fus_cu_issue_i$37[0:0]$2464 attribute \src "libresoc.v:47151.3-47179.6" wire $0\fus_cu_issue_i[0:0] attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2835 attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867 attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886 attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364 attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378 attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403 attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422 attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446 attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469 attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0] attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] attribute \src "libresoc.v:46564.3-46593.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] attribute \src "libresoc.v:46735.3-46763.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] attribute \src "libresoc.v:46811.3-46839.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] attribute \src "libresoc.v:46981.3-47009.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] attribute \src "libresoc.v:47019.3-47047.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] attribute \src "libresoc.v:46943.3-46971.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] attribute \src "libresoc.v:46849.3-46877.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] attribute \src "libresoc.v:46773.3-46801.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0] attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] attribute \src "libresoc.v:47596.3-47625.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] attribute \src "libresoc.v:47655.3-47683.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] attribute \src "libresoc.v:47626.3-47654.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0] attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0] attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] attribute \src "libresoc.v:43938.3-43967.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] attribute \src "libresoc.v:44028.3-44056.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] attribute \src "libresoc.v:44115.3-44143.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] attribute \src "libresoc.v:44202.3-44230.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] attribute \src "libresoc.v:44231.3-44259.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] attribute \src "libresoc.v:44173.3-44201.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] attribute \src "libresoc.v:44144.3-44172.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] attribute \src "libresoc.v:44057.3-44085.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0] attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] attribute \src "libresoc.v:48119.3-48148.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] attribute \src "libresoc.v:48209.3-48237.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] attribute \src "libresoc.v:48296.3-48324.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] attribute \src "libresoc.v:43532.3-43560.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] attribute \src "libresoc.v:43561.3-43589.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] attribute \src "libresoc.v:43503.3-43531.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] attribute \src "libresoc.v:48325.3-48353.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] attribute \src "libresoc.v:48238.3-48266.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0] attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] attribute \src "libresoc.v:44434.3-44463.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] attribute \src "libresoc.v:44553.3-44581.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] attribute \src "libresoc.v:44582.3-44610.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] attribute \src "libresoc.v:44524.3-44552.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] attribute \src "libresoc.v:44756.3-44785.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] attribute \src "libresoc.v:44962.3-44990.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] attribute \src "libresoc.v:44875.3-44903.6" wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] attribute \src "libresoc.v:45020.3-45048.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] attribute \src "libresoc.v:45049.3-45077.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] attribute \src "libresoc.v:44933.3-44961.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] attribute \src "libresoc.v:44991.3-45019.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] attribute \src "libresoc.v:44846.3-44874.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0] attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] attribute \src "libresoc.v:43793.3-43821.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0] attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] attribute \src "libresoc.v:47887.3-47915.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] attribute \src "libresoc.v:45429.3-45457.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] attribute \src "libresoc.v:45223.3-45252.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] attribute \src "libresoc.v:45342.3-45370.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] attribute \src "libresoc.v:45371.3-45399.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] attribute \src "libresoc.v:45312.3-45341.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] attribute \src "libresoc.v:45312.3-45341.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] attribute \src "libresoc.v:45458.3-45486.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] attribute \src "libresoc.v:45253.3-45281.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] attribute \src "libresoc.v:45821.3-45830.6" wire width 64 $0\fus_src1_i$62[63:0]$2537 attribute \src "libresoc.v:45840.3-45849.6" wire width 64 $0\fus_src1_i$63[63:0]$2543 attribute \src "libresoc.v:45859.3-45868.6" wire width 64 $0\fus_src1_i$64[63:0]$2549 attribute \src "libresoc.v:45878.3-45887.6" wire width 64 $0\fus_src1_i$67[63:0]$2555 attribute \src "libresoc.v:45897.3-45906.6" wire width 64 $0\fus_src1_i$68[63:0]$2561 attribute \src "libresoc.v:45916.3-45925.6" wire width 64 $0\fus_src1_i$69[63:0]$2567 attribute \src "libresoc.v:45935.3-45944.6" wire width 64 $0\fus_src1_i$70[63:0]$2573 attribute \src "libresoc.v:45954.3-45963.6" wire width 64 $0\fus_src1_i$71[63:0]$2579 attribute \src "libresoc.v:46380.3-46389.6" wire width 64 $0\fus_src1_i$86[63:0]$2676 attribute \src "libresoc.v:45802.3-45811.6" wire width 64 $0\fus_src1_i[63:0] attribute \src "libresoc.v:45631.3-45640.6" wire width 64 $0\fus_src2_i$42[63:0]$2481 attribute \src "libresoc.v:45650.3-45659.6" wire width 64 $0\fus_src2_i$45[63:0]$2487 attribute \src "libresoc.v:45669.3-45678.6" wire width 64 $0\fus_src2_i$48[63:0]$2493 attribute \src "libresoc.v:45688.3-45697.6" wire width 64 $0\fus_src2_i$51[63:0]$2499 attribute \src "libresoc.v:45707.3-45716.6" wire width 64 $0\fus_src2_i$54[63:0]$2505 attribute \src "libresoc.v:45726.3-45735.6" wire width 64 $0\fus_src2_i$57[63:0]$2511 attribute \src "libresoc.v:45745.3-45754.6" wire width 64 $0\fus_src2_i$60[63:0]$2517 attribute \src "libresoc.v:46487.3-46496.6" wire width 64 $0\fus_src2_i$89[63:0]$2700 attribute \src "libresoc.v:46554.3-46563.6" wire width 64 $0\fus_src2_i$91[63:0]$2713 attribute \src "libresoc.v:45612.3-45621.6" wire width 64 $0\fus_src2_i[63:0] attribute \src "libresoc.v:45783.3-45792.6" wire width 64 $0\fus_src3_i$61[63:0]$2527 attribute \src "libresoc.v:45973.3-45982.6" wire $0\fus_src3_i$72[0:0]$2585 attribute \src "libresoc.v:45992.3-46001.6" wire $0\fus_src3_i$73[0:0]$2591 attribute \src "libresoc.v:46030.3-46039.6" wire $0\fus_src3_i$74[0:0]$2601 attribute \src "libresoc.v:46049.3-46058.6" wire $0\fus_src3_i$75[0:0]$2607 attribute \src "libresoc.v:46163.3-46172.6" wire width 32 $0\fus_src3_i$79[31:0]$2639 attribute \src "libresoc.v:46201.3-46210.6" wire width 4 $0\fus_src3_i$83[3:0]$2651 attribute \src "libresoc.v:46420.3-46429.6" wire width 64 $0\fus_src3_i$87[63:0]$2687 attribute \src "libresoc.v:46439.3-46448.6" wire width 64 $0\fus_src3_i$88[63:0]$2693 attribute \src "libresoc.v:45764.3-45773.6" wire width 64 $0\fus_src3_i[63:0] attribute \src "libresoc.v:46068.3-46077.6" wire $0\fus_src4_i$76[0:0]$2613 attribute \src "libresoc.v:46087.3-46096.6" wire width 2 $0\fus_src4_i$77[1:0]$2619 attribute \src "libresoc.v:46182.3-46191.6" wire width 4 $0\fus_src4_i$80[3:0]$2645 attribute \src "libresoc.v:46506.3-46515.6" wire width 64 $0\fus_src4_i$90[63:0]$2706 attribute \src "libresoc.v:46011.3-46020.6" wire $0\fus_src4_i[0:0] attribute \src "libresoc.v:46144.3-46153.6" wire width 2 $0\fus_src5_i$78[1:0]$2633 attribute \src "libresoc.v:46251.3-46260.6" wire width 4 $0\fus_src5_i$84[3:0]$2663 attribute \src "libresoc.v:46125.3-46134.6" wire width 2 $0\fus_src5_i[1:0] attribute \src "libresoc.v:46270.3-46279.6" wire width 4 $0\fus_src6_i$85[3:0]$2669 attribute \src "libresoc.v:46106.3-46115.6" wire width 2 $0\fus_src6_i[1:0] attribute \src "libresoc.v:36262.7-36262.20" wire $0\initial[0:0] attribute \src "libresoc.v:46612.3-46620.6" wire $0\wr_pick_dly$1008$next[0:0]$2723 attribute \src "libresoc.v:42700.3-42701.51" wire $0\wr_pick_dly$1008[0:0]$2307 attribute \src "libresoc.v:41530.7-41530.32" wire $0\wr_pick_dly$1008[0:0]$2945 attribute \src "libresoc.v:46651.3-46659.6" wire $0\wr_pick_dly$1029$next[0:0]$2727 attribute \src "libresoc.v:42698.3-42699.51" wire $0\wr_pick_dly$1029[0:0]$2305 attribute \src "libresoc.v:41534.7-41534.32" wire $0\wr_pick_dly$1029[0:0]$2947 attribute \src "libresoc.v:46660.3-46668.6" wire $0\wr_pick_dly$1047$next[0:0]$2730 attribute \src "libresoc.v:42696.3-42697.51" wire $0\wr_pick_dly$1047[0:0]$2303 attribute \src "libresoc.v:41538.7-41538.32" wire $0\wr_pick_dly$1047[0:0]$2949 attribute \src "libresoc.v:46669.3-46677.6" wire $0\wr_pick_dly$1069$next[0:0]$2733 attribute \src "libresoc.v:42694.3-42695.51" wire $0\wr_pick_dly$1069[0:0]$2301 attribute \src "libresoc.v:41542.7-41542.32" wire $0\wr_pick_dly$1069[0:0]$2951 attribute \src "libresoc.v:46708.3-46716.6" wire $0\wr_pick_dly$1089$next[0:0]$2737 attribute \src "libresoc.v:42692.3-42693.51" wire $0\wr_pick_dly$1089[0:0]$2299 attribute \src "libresoc.v:41546.7-41546.32" wire $0\wr_pick_dly$1089[0:0]$2953 attribute \src "libresoc.v:46717.3-46725.6" wire $0\wr_pick_dly$1109$next[0:0]$2740 attribute \src "libresoc.v:42690.3-42691.51" wire $0\wr_pick_dly$1109[0:0]$2297 attribute \src "libresoc.v:41550.7-41550.32" wire $0\wr_pick_dly$1109[0:0]$2955 attribute \src "libresoc.v:46726.3-46734.6" wire $0\wr_pick_dly$1128$next[0:0]$2743 attribute \src "libresoc.v:42688.3-42689.51" wire $0\wr_pick_dly$1128[0:0]$2295 attribute \src "libresoc.v:41554.7-41554.32" wire $0\wr_pick_dly$1128[0:0]$2957 attribute \src "libresoc.v:46764.3-46772.6" wire $0\wr_pick_dly$1146$next[0:0]$2747 attribute \src "libresoc.v:42686.3-42687.51" wire $0\wr_pick_dly$1146[0:0]$2293 attribute \src "libresoc.v:41558.7-41558.32" wire $0\wr_pick_dly$1146[0:0]$2959 attribute \src "libresoc.v:46802.3-46810.6" wire $0\wr_pick_dly$1220$next[0:0]$2751 attribute \src "libresoc.v:42684.3-42685.51" wire $0\wr_pick_dly$1220[0:0]$2291 attribute \src "libresoc.v:41562.7-41562.32" wire $0\wr_pick_dly$1220[0:0]$2961 attribute \src "libresoc.v:46840.3-46848.6" wire $0\wr_pick_dly$1248$next[0:0]$2755 attribute \src "libresoc.v:42682.3-42683.51" wire $0\wr_pick_dly$1248[0:0]$2289 attribute \src "libresoc.v:41566.7-41566.32" wire $0\wr_pick_dly$1248[0:0]$2963 attribute \src "libresoc.v:46878.3-46886.6" wire $0\wr_pick_dly$1268$next[0:0]$2759 attribute \src "libresoc.v:42680.3-42681.51" wire $0\wr_pick_dly$1268[0:0]$2287 attribute \src "libresoc.v:41570.7-41570.32" wire $0\wr_pick_dly$1268[0:0]$2965 attribute \src "libresoc.v:46887.3-46895.6" wire $0\wr_pick_dly$1288$next[0:0]$2762 attribute \src "libresoc.v:42678.3-42679.51" wire $0\wr_pick_dly$1288[0:0]$2285 attribute \src "libresoc.v:41574.7-41574.32" wire $0\wr_pick_dly$1288[0:0]$2967 attribute \src "libresoc.v:46925.3-46933.6" wire $0\wr_pick_dly$1308$next[0:0]$2766 attribute \src "libresoc.v:42676.3-42677.51" wire $0\wr_pick_dly$1308[0:0]$2283 attribute \src "libresoc.v:41578.7-41578.32" wire $0\wr_pick_dly$1308[0:0]$2969 attribute \src "libresoc.v:46934.3-46942.6" wire $0\wr_pick_dly$1328$next[0:0]$2769 attribute \src "libresoc.v:42674.3-42675.51" wire $0\wr_pick_dly$1328[0:0]$2281 attribute \src "libresoc.v:41582.7-41582.32" wire $0\wr_pick_dly$1328[0:0]$2971 attribute \src "libresoc.v:46972.3-46980.6" wire $0\wr_pick_dly$1348$next[0:0]$2773 attribute \src "libresoc.v:42672.3-42673.51" wire $0\wr_pick_dly$1348[0:0]$2279 attribute \src "libresoc.v:41586.7-41586.32" wire $0\wr_pick_dly$1348[0:0]$2973 attribute \src "libresoc.v:47010.3-47018.6" wire $0\wr_pick_dly$1395$next[0:0]$2777 attribute \src "libresoc.v:42670.3-42671.51" wire $0\wr_pick_dly$1395[0:0]$2277 attribute \src "libresoc.v:41590.7-41590.32" wire $0\wr_pick_dly$1395[0:0]$2975 attribute \src "libresoc.v:47048.3-47056.6" wire $0\wr_pick_dly$1411$next[0:0]$2781 attribute \src "libresoc.v:42668.3-42669.51" wire $0\wr_pick_dly$1411[0:0]$2275 attribute \src "libresoc.v:41594.7-41594.32" wire $0\wr_pick_dly$1411[0:0]$2977 attribute \src "libresoc.v:47057.3-47065.6" wire $0\wr_pick_dly$1427$next[0:0]$2784 attribute \src "libresoc.v:42666.3-42667.51" wire $0\wr_pick_dly$1427[0:0]$2273 attribute \src "libresoc.v:41598.7-41598.32" wire $0\wr_pick_dly$1427[0:0]$2979 attribute \src "libresoc.v:47095.3-47103.6" wire $0\wr_pick_dly$1461$next[0:0]$2788 attribute \src "libresoc.v:42664.3-42665.51" wire $0\wr_pick_dly$1461[0:0]$2271 attribute \src "libresoc.v:41602.7-41602.32" wire $0\wr_pick_dly$1461[0:0]$2981 attribute \src "libresoc.v:47133.3-47141.6" wire $0\wr_pick_dly$1477$next[0:0]$2792 attribute \src "libresoc.v:42662.3-42663.51" wire $0\wr_pick_dly$1477[0:0]$2269 attribute \src "libresoc.v:41606.7-41606.32" wire $0\wr_pick_dly$1477[0:0]$2983 attribute \src "libresoc.v:47142.3-47150.6" wire $0\wr_pick_dly$1493$next[0:0]$2795 attribute \src "libresoc.v:42660.3-42661.51" wire $0\wr_pick_dly$1493[0:0]$2267 attribute \src "libresoc.v:41610.7-41610.32" wire $0\wr_pick_dly$1493[0:0]$2985 attribute \src "libresoc.v:47180.3-47188.6" wire $0\wr_pick_dly$1509$next[0:0]$2799 attribute \src "libresoc.v:42658.3-42659.51" wire $0\wr_pick_dly$1509[0:0]$2265 attribute \src "libresoc.v:41614.7-41614.32" wire $0\wr_pick_dly$1509[0:0]$2987 attribute \src "libresoc.v:47218.3-47226.6" wire $0\wr_pick_dly$1545$next[0:0]$2803 attribute \src "libresoc.v:42656.3-42657.51" wire $0\wr_pick_dly$1545[0:0]$2263 attribute \src "libresoc.v:41618.7-41618.32" wire $0\wr_pick_dly$1545[0:0]$2989 attribute \src "libresoc.v:47227.3-47235.6" wire $0\wr_pick_dly$1561$next[0:0]$2806 attribute \src "libresoc.v:42654.3-42655.51" wire $0\wr_pick_dly$1561[0:0]$2261 attribute \src "libresoc.v:41622.7-41622.32" wire $0\wr_pick_dly$1561[0:0]$2991 attribute \src "libresoc.v:47265.3-47273.6" wire $0\wr_pick_dly$1577$next[0:0]$2810 attribute \src "libresoc.v:42652.3-42653.51" wire $0\wr_pick_dly$1577[0:0]$2259 attribute \src "libresoc.v:41626.7-41626.32" wire $0\wr_pick_dly$1577[0:0]$2993 attribute \src "libresoc.v:47303.3-47311.6" wire $0\wr_pick_dly$1593$next[0:0]$2814 attribute \src "libresoc.v:42650.3-42651.51" wire $0\wr_pick_dly$1593[0:0]$2257 attribute \src "libresoc.v:41630.7-41630.32" wire $0\wr_pick_dly$1593[0:0]$2995 attribute \src "libresoc.v:47312.3-47320.6" wire $0\wr_pick_dly$1635$next[0:0]$2817 attribute \src "libresoc.v:42648.3-42649.51" wire $0\wr_pick_dly$1635[0:0]$2255 attribute \src "libresoc.v:41634.7-41634.32" wire $0\wr_pick_dly$1635[0:0]$2997 attribute \src "libresoc.v:47350.3-47358.6" wire $0\wr_pick_dly$1654$next[0:0]$2821 attribute \src "libresoc.v:42646.3-42647.51" wire $0\wr_pick_dly$1654[0:0]$2253 attribute \src "libresoc.v:41638.7-41638.32" wire $0\wr_pick_dly$1654[0:0]$2999 attribute \src "libresoc.v:47388.3-47396.6" wire $0\wr_pick_dly$1670$next[0:0]$2829 attribute \src "libresoc.v:42644.3-42645.51" wire $0\wr_pick_dly$1670[0:0]$2251 attribute \src "libresoc.v:41642.7-41642.32" wire $0\wr_pick_dly$1670[0:0]$3001 attribute \src "libresoc.v:47397.3-47405.6" wire $0\wr_pick_dly$1686$next[0:0]$2832 attribute \src "libresoc.v:42642.3-42643.51" wire $0\wr_pick_dly$1686[0:0]$2249 attribute \src "libresoc.v:41646.7-41646.32" wire $0\wr_pick_dly$1686[0:0]$3003 attribute \src "libresoc.v:47435.3-47443.6" wire $0\wr_pick_dly$1702$next[0:0]$2840 attribute \src "libresoc.v:42640.3-42641.51" wire $0\wr_pick_dly$1702[0:0]$2247 attribute \src "libresoc.v:41650.7-41650.32" wire $0\wr_pick_dly$1702[0:0]$3005 attribute \src "libresoc.v:47473.3-47481.6" wire $0\wr_pick_dly$1746$next[0:0]$2844 attribute \src "libresoc.v:42638.3-42639.51" wire $0\wr_pick_dly$1746[0:0]$2245 attribute \src "libresoc.v:41654.7-41654.32" wire $0\wr_pick_dly$1746[0:0]$3007 attribute \src "libresoc.v:47511.3-47519.6" wire $0\wr_pick_dly$1762$next[0:0]$2848 attribute \src "libresoc.v:42636.3-42637.51" wire $0\wr_pick_dly$1762[0:0]$2243 attribute \src "libresoc.v:41658.7-41658.32" wire $0\wr_pick_dly$1762[0:0]$3009 attribute \src "libresoc.v:47520.3-47528.6" wire $0\wr_pick_dly$1786$next[0:0]$2851 attribute \src "libresoc.v:42634.3-42635.51" wire $0\wr_pick_dly$1786[0:0]$2241 attribute \src "libresoc.v:41662.7-41662.32" wire $0\wr_pick_dly$1786[0:0]$3011 attribute \src "libresoc.v:47558.3-47566.6" wire $0\wr_pick_dly$1806$next[0:0]$2855 attribute \src "libresoc.v:42632.3-42633.51" wire $0\wr_pick_dly$1806[0:0]$2239 attribute \src "libresoc.v:41666.7-41666.32" wire $0\wr_pick_dly$1806[0:0]$3013 attribute \src "libresoc.v:46603.3-46611.6" wire $0\wr_pick_dly$989$next[0:0]$2720 attribute \src "libresoc.v:42702.3-42703.49" wire $0\wr_pick_dly$989[0:0]$2309 attribute \src "libresoc.v:41670.7-41670.31" wire $0\wr_pick_dly$989[0:0]$3015 attribute \src "libresoc.v:46594.3-46602.6" wire $0\wr_pick_dly$next[0:0]$2717 attribute \src "libresoc.v:42704.3-42705.39" wire $0\wr_pick_dly[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $10\corebusy_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $11\corebusy_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $12\corebusy_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $13\corebusy_o[0:0] attribute \src "libresoc.v:46390.3-46410.6" wire $1\core_terminate_o$next[0:0]$2680 attribute \src "libresoc.v:38103.7-38103.30" wire $1\core_terminate_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $1\corebusy_o[0:0] attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $1\counter$next[1:0]$2658 attribute \src "libresoc.v:38116.13-38116.27" wire width 2 $1\counter[1:0] attribute \src "libresoc.v:46192.3-46200.6" wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 attribute \src "libresoc.v:39283.7-39283.34" wire $1\dp_CR_cr_a_branch0_1[0:0] attribute \src "libresoc.v:46173.3-46181.6" wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 attribute \src "libresoc.v:39287.7-39287.30" wire $1\dp_CR_cr_a_cr0_0[0:0] attribute \src "libresoc.v:46211.3-46219.6" wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 attribute \src "libresoc.v:39291.7-39291.30" wire $1\dp_CR_cr_b_cr0_0[0:0] attribute \src "libresoc.v:46261.3-46269.6" wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 attribute \src "libresoc.v:39295.7-39295.30" wire $1\dp_CR_cr_c_cr0_0[0:0] attribute \src "libresoc.v:46154.3-46162.6" wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 attribute \src "libresoc.v:39299.7-39299.33" wire $1\dp_CR_full_cr_cr0_0[0:0] attribute \src "libresoc.v:46371.3-46379.6" wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 attribute \src "libresoc.v:39303.7-39303.37" wire $1\dp_FAST_fast1_branch0_0[0:0] attribute \src "libresoc.v:46478.3-46486.6" wire $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 attribute \src "libresoc.v:39307.7-39307.37" wire $1\dp_FAST_fast1_branch0_3[0:0] attribute \src "libresoc.v:46430.3-46438.6" wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 attribute \src "libresoc.v:39311.7-39311.34" wire $1\dp_FAST_fast1_spr0_2[0:0] attribute \src "libresoc.v:46411.3-46419.6" wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 attribute \src "libresoc.v:39315.7-39315.35" wire $1\dp_FAST_fast1_trap0_1[0:0] attribute \src "libresoc.v:46497.3-46505.6" wire $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 attribute \src "libresoc.v:39319.7-39319.35" wire $1\dp_FAST_fast1_trap0_4[0:0] attribute \src "libresoc.v:45603.3-45611.6" wire $1\dp_INT_rabc_alu0_0$next[0:0]$2475 attribute \src "libresoc.v:39323.7-39323.32" wire $1\dp_INT_rabc_alu0_0[0:0] attribute \src "libresoc.v:45793.3-45801.6" wire $1\dp_INT_rabc_alu0_10$next[0:0]$2531 attribute \src "libresoc.v:39327.7-39327.33" wire $1\dp_INT_rabc_alu0_10[0:0] attribute \src "libresoc.v:45622.3-45630.6" wire $1\dp_INT_rabc_cr0_1$next[0:0]$2479 attribute \src "libresoc.v:45812.3-45820.6" wire $1\dp_INT_rabc_cr0_11$next[0:0]$2535 attribute \src "libresoc.v:39335.7-39335.32" wire $1\dp_INT_rabc_cr0_11[0:0] attribute \src "libresoc.v:39331.7-39331.31" wire $1\dp_INT_rabc_cr0_1[0:0] attribute \src "libresoc.v:45888.3-45896.6" wire $1\dp_INT_rabc_div0_15$next[0:0]$2559 attribute \src "libresoc.v:39339.7-39339.33" wire $1\dp_INT_rabc_div0_15[0:0] attribute \src "libresoc.v:45679.3-45687.6" wire $1\dp_INT_rabc_div0_4$next[0:0]$2497 attribute \src "libresoc.v:39343.7-39343.32" wire $1\dp_INT_rabc_div0_4[0:0] attribute \src "libresoc.v:45945.3-45953.6" wire $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 attribute \src "libresoc.v:39347.7-39347.34" wire $1\dp_INT_rabc_ldst0_18[0:0] attribute \src "libresoc.v:45736.3-45744.6" wire $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 attribute \src "libresoc.v:39351.7-39351.33" wire $1\dp_INT_rabc_ldst0_7[0:0] attribute \src "libresoc.v:45774.3-45782.6" wire $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 attribute \src "libresoc.v:39355.7-39355.33" wire $1\dp_INT_rabc_ldst0_9[0:0] attribute \src "libresoc.v:45850.3-45858.6" wire $1\dp_INT_rabc_logical0_13$next[0:0]$2547 attribute \src "libresoc.v:39359.7-39359.37" wire $1\dp_INT_rabc_logical0_13[0:0] attribute \src "libresoc.v:45660.3-45668.6" wire $1\dp_INT_rabc_logical0_3$next[0:0]$2491 attribute \src "libresoc.v:39363.7-39363.36" wire $1\dp_INT_rabc_logical0_3[0:0] attribute \src "libresoc.v:45907.3-45915.6" wire $1\dp_INT_rabc_mul0_16$next[0:0]$2565 attribute \src "libresoc.v:39367.7-39367.33" wire $1\dp_INT_rabc_mul0_16[0:0] attribute \src "libresoc.v:45698.3-45706.6" wire $1\dp_INT_rabc_mul0_5$next[0:0]$2503 attribute \src "libresoc.v:39371.7-39371.32" wire $1\dp_INT_rabc_mul0_5[0:0] attribute \src "libresoc.v:45926.3-45934.6" wire $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 attribute \src "libresoc.v:39375.7-39375.38" wire $1\dp_INT_rabc_shiftrot0_17[0:0] attribute \src "libresoc.v:45717.3-45725.6" wire $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 attribute \src "libresoc.v:39379.7-39379.37" wire $1\dp_INT_rabc_shiftrot0_6[0:0] attribute \src "libresoc.v:45755.3-45763.6" wire $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 attribute \src "libresoc.v:39383.7-39383.37" wire $1\dp_INT_rabc_shiftrot0_8[0:0] attribute \src "libresoc.v:45869.3-45877.6" wire $1\dp_INT_rabc_spr0_14$next[0:0]$2553 attribute \src "libresoc.v:39387.7-39387.33" wire $1\dp_INT_rabc_spr0_14[0:0] attribute \src "libresoc.v:45831.3-45839.6" wire $1\dp_INT_rabc_trap0_12$next[0:0]$2541 attribute \src "libresoc.v:39391.7-39391.34" wire $1\dp_INT_rabc_trap0_12[0:0] attribute \src "libresoc.v:45641.3-45649.6" wire $1\dp_INT_rabc_trap0_2$next[0:0]$2485 attribute \src "libresoc.v:39395.7-39395.33" wire $1\dp_INT_rabc_trap0_2[0:0] attribute \src "libresoc.v:46545.3-46553.6" wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 attribute \src "libresoc.v:39399.7-39399.32" wire $1\dp_SPR_spr1_spr0_0[0:0] attribute \src "libresoc.v:46078.3-46086.6" wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 attribute \src "libresoc.v:39403.7-39403.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] attribute \src "libresoc.v:46116.3-46124.6" wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 attribute \src "libresoc.v:39407.7-39407.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] attribute \src "libresoc.v:46097.3-46105.6" wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 attribute \src "libresoc.v:39411.7-39411.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] attribute \src "libresoc.v:46135.3-46143.6" wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 attribute \src "libresoc.v:39415.7-39415.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] attribute \src "libresoc.v:45964.3-45972.6" wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 attribute \src "libresoc.v:39419.7-39419.34" wire $1\dp_XER_xer_so_alu0_0[0:0] attribute \src "libresoc.v:46021.3-46029.6" wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599 attribute \src "libresoc.v:39423.7-39423.34" wire $1\dp_XER_xer_so_div0_3[0:0] attribute \src "libresoc.v:45983.3-45991.6" wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 attribute \src "libresoc.v:39427.7-39427.38" wire $1\dp_XER_xer_so_logical0_1[0:0] attribute \src "libresoc.v:46040.3-46048.6" wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 attribute \src "libresoc.v:39431.7-39431.34" wire $1\dp_XER_xer_so_mul0_4[0:0] attribute \src "libresoc.v:46059.3-46067.6" wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 attribute \src "libresoc.v:39435.7-39435.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] attribute \src "libresoc.v:46002.3-46010.6" wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 attribute \src "libresoc.v:39439.7-39439.34" wire $1\dp_XER_xer_so_spr0_2[0:0] attribute \src "libresoc.v:47359.3-47387.6" wire $1\fus_cu_issue_i$13[0:0]$2825 attribute \src "libresoc.v:47684.3-47712.6" wire $1\fus_cu_issue_i$16[0:0]$2863 attribute \src "libresoc.v:48003.3-48031.6" wire $1\fus_cu_issue_i$19[0:0]$2882 attribute \src "libresoc.v:43648.3-43676.6" wire $1\fus_cu_issue_i$22[0:0]$2360 attribute \src "libresoc.v:43822.3-43850.6" wire $1\fus_cu_issue_i$25[0:0]$2374 attribute \src "libresoc.v:44318.3-44346.6" wire $1\fus_cu_issue_i$28[0:0]$2399 attribute \src "libresoc.v:44640.3-44668.6" wire $1\fus_cu_issue_i$31[0:0]$2418 attribute \src "libresoc.v:45107.3-45135.6" wire $1\fus_cu_issue_i$34[0:0]$2442 attribute \src "libresoc.v:45545.3-45573.6" wire $1\fus_cu_issue_i$37[0:0]$2465 attribute \src "libresoc.v:47151.3-47179.6" wire $1\fus_cu_issue_i[0:0] attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2836 attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868 attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887 attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365 attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379 attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404 attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423 attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447 attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470 attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0] attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] attribute \src "libresoc.v:46564.3-46593.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] attribute \src "libresoc.v:46735.3-46763.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] attribute \src "libresoc.v:46811.3-46839.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] attribute \src "libresoc.v:46981.3-47009.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] attribute \src "libresoc.v:47019.3-47047.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] attribute \src "libresoc.v:46943.3-46971.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] attribute \src "libresoc.v:46849.3-46877.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] attribute \src "libresoc.v:46773.3-46801.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0] attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] attribute \src "libresoc.v:47596.3-47625.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] attribute \src "libresoc.v:47655.3-47683.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] attribute \src "libresoc.v:47626.3-47654.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0] attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0] attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] attribute \src "libresoc.v:43938.3-43967.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] attribute \src "libresoc.v:44028.3-44056.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] attribute \src "libresoc.v:44115.3-44143.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] attribute \src "libresoc.v:44202.3-44230.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] attribute \src "libresoc.v:44231.3-44259.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] attribute \src "libresoc.v:44173.3-44201.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] attribute \src "libresoc.v:44144.3-44172.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] attribute \src "libresoc.v:44057.3-44085.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0] attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] attribute \src "libresoc.v:48119.3-48148.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] attribute \src "libresoc.v:48209.3-48237.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] attribute \src "libresoc.v:48296.3-48324.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] attribute \src "libresoc.v:43532.3-43560.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] attribute \src "libresoc.v:43561.3-43589.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] attribute \src "libresoc.v:43503.3-43531.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] attribute \src "libresoc.v:48325.3-48353.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] attribute \src "libresoc.v:48238.3-48266.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0] attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] attribute \src "libresoc.v:44434.3-44463.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] attribute \src "libresoc.v:44553.3-44581.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] attribute \src "libresoc.v:44582.3-44610.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] attribute \src "libresoc.v:44524.3-44552.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] attribute \src "libresoc.v:44756.3-44785.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] attribute \src "libresoc.v:44962.3-44990.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] attribute \src "libresoc.v:44875.3-44903.6" wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] attribute \src "libresoc.v:45020.3-45048.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] attribute \src "libresoc.v:45049.3-45077.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] attribute \src "libresoc.v:44933.3-44961.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] attribute \src "libresoc.v:44991.3-45019.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] attribute \src "libresoc.v:44846.3-44874.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0] attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] attribute \src "libresoc.v:43793.3-43821.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0] attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] attribute \src "libresoc.v:47887.3-47915.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] attribute \src "libresoc.v:45429.3-45457.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] attribute \src "libresoc.v:45223.3-45252.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] attribute \src "libresoc.v:45342.3-45370.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] attribute \src "libresoc.v:45371.3-45399.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] attribute \src "libresoc.v:45312.3-45341.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] attribute \src "libresoc.v:45312.3-45341.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] attribute \src "libresoc.v:45458.3-45486.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] attribute \src "libresoc.v:45253.3-45281.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] attribute \src "libresoc.v:45821.3-45830.6" wire width 64 $1\fus_src1_i$62[63:0]$2538 attribute \src "libresoc.v:45840.3-45849.6" wire width 64 $1\fus_src1_i$63[63:0]$2544 attribute \src "libresoc.v:45859.3-45868.6" wire width 64 $1\fus_src1_i$64[63:0]$2550 attribute \src "libresoc.v:45878.3-45887.6" wire width 64 $1\fus_src1_i$67[63:0]$2556 attribute \src "libresoc.v:45897.3-45906.6" wire width 64 $1\fus_src1_i$68[63:0]$2562 attribute \src "libresoc.v:45916.3-45925.6" wire width 64 $1\fus_src1_i$69[63:0]$2568 attribute \src "libresoc.v:45935.3-45944.6" wire width 64 $1\fus_src1_i$70[63:0]$2574 attribute \src "libresoc.v:45954.3-45963.6" wire width 64 $1\fus_src1_i$71[63:0]$2580 attribute \src "libresoc.v:46380.3-46389.6" wire width 64 $1\fus_src1_i$86[63:0]$2677 attribute \src "libresoc.v:45802.3-45811.6" wire width 64 $1\fus_src1_i[63:0] attribute \src "libresoc.v:45631.3-45640.6" wire width 64 $1\fus_src2_i$42[63:0]$2482 attribute \src "libresoc.v:45650.3-45659.6" wire width 64 $1\fus_src2_i$45[63:0]$2488 attribute \src "libresoc.v:45669.3-45678.6" wire width 64 $1\fus_src2_i$48[63:0]$2494 attribute \src "libresoc.v:45688.3-45697.6" wire width 64 $1\fus_src2_i$51[63:0]$2500 attribute \src "libresoc.v:45707.3-45716.6" wire width 64 $1\fus_src2_i$54[63:0]$2506 attribute \src "libresoc.v:45726.3-45735.6" wire width 64 $1\fus_src2_i$57[63:0]$2512 attribute \src "libresoc.v:45745.3-45754.6" wire width 64 $1\fus_src2_i$60[63:0]$2518 attribute \src "libresoc.v:46487.3-46496.6" wire width 64 $1\fus_src2_i$89[63:0]$2701 attribute \src "libresoc.v:46554.3-46563.6" wire width 64 $1\fus_src2_i$91[63:0]$2714 attribute \src "libresoc.v:45612.3-45621.6" wire width 64 $1\fus_src2_i[63:0] attribute \src "libresoc.v:45783.3-45792.6" wire width 64 $1\fus_src3_i$61[63:0]$2528 attribute \src "libresoc.v:45973.3-45982.6" wire $1\fus_src3_i$72[0:0]$2586 attribute \src "libresoc.v:45992.3-46001.6" wire $1\fus_src3_i$73[0:0]$2592 attribute \src "libresoc.v:46030.3-46039.6" wire $1\fus_src3_i$74[0:0]$2602 attribute \src "libresoc.v:46049.3-46058.6" wire $1\fus_src3_i$75[0:0]$2608 attribute \src "libresoc.v:46163.3-46172.6" wire width 32 $1\fus_src3_i$79[31:0]$2640 attribute \src "libresoc.v:46201.3-46210.6" wire width 4 $1\fus_src3_i$83[3:0]$2652 attribute \src "libresoc.v:46420.3-46429.6" wire width 64 $1\fus_src3_i$87[63:0]$2688 attribute \src "libresoc.v:46439.3-46448.6" wire width 64 $1\fus_src3_i$88[63:0]$2694 attribute \src "libresoc.v:45764.3-45773.6" wire width 64 $1\fus_src3_i[63:0] attribute \src "libresoc.v:46068.3-46077.6" wire $1\fus_src4_i$76[0:0]$2614 attribute \src "libresoc.v:46087.3-46096.6" wire width 2 $1\fus_src4_i$77[1:0]$2620 attribute \src "libresoc.v:46182.3-46191.6" wire width 4 $1\fus_src4_i$80[3:0]$2646 attribute \src "libresoc.v:46506.3-46515.6" wire width 64 $1\fus_src4_i$90[63:0]$2707 attribute \src "libresoc.v:46011.3-46020.6" wire $1\fus_src4_i[0:0] attribute \src "libresoc.v:46144.3-46153.6" wire width 2 $1\fus_src5_i$78[1:0]$2634 attribute \src "libresoc.v:46251.3-46260.6" wire width 4 $1\fus_src5_i$84[3:0]$2664 attribute \src "libresoc.v:46125.3-46134.6" wire width 2 $1\fus_src5_i[1:0] attribute \src "libresoc.v:46270.3-46279.6" wire width 4 $1\fus_src6_i$85[3:0]$2670 attribute \src "libresoc.v:46106.3-46115.6" wire width 2 $1\fus_src6_i[1:0] attribute \src "libresoc.v:46612.3-46620.6" wire $1\wr_pick_dly$1008$next[0:0]$2724 attribute \src "libresoc.v:46651.3-46659.6" wire $1\wr_pick_dly$1029$next[0:0]$2728 attribute \src "libresoc.v:46660.3-46668.6" wire $1\wr_pick_dly$1047$next[0:0]$2731 attribute \src "libresoc.v:46669.3-46677.6" wire $1\wr_pick_dly$1069$next[0:0]$2734 attribute \src "libresoc.v:46708.3-46716.6" wire $1\wr_pick_dly$1089$next[0:0]$2738 attribute \src "libresoc.v:46717.3-46725.6" wire $1\wr_pick_dly$1109$next[0:0]$2741 attribute \src "libresoc.v:46726.3-46734.6" wire $1\wr_pick_dly$1128$next[0:0]$2744 attribute \src "libresoc.v:46764.3-46772.6" wire $1\wr_pick_dly$1146$next[0:0]$2748 attribute \src "libresoc.v:46802.3-46810.6" wire $1\wr_pick_dly$1220$next[0:0]$2752 attribute \src "libresoc.v:46840.3-46848.6" wire $1\wr_pick_dly$1248$next[0:0]$2756 attribute \src "libresoc.v:46878.3-46886.6" wire $1\wr_pick_dly$1268$next[0:0]$2760 attribute \src "libresoc.v:46887.3-46895.6" wire $1\wr_pick_dly$1288$next[0:0]$2763 attribute \src "libresoc.v:46925.3-46933.6" wire $1\wr_pick_dly$1308$next[0:0]$2767 attribute \src "libresoc.v:46934.3-46942.6" wire $1\wr_pick_dly$1328$next[0:0]$2770 attribute \src "libresoc.v:46972.3-46980.6" wire $1\wr_pick_dly$1348$next[0:0]$2774 attribute \src "libresoc.v:47010.3-47018.6" wire $1\wr_pick_dly$1395$next[0:0]$2778 attribute \src "libresoc.v:47048.3-47056.6" wire $1\wr_pick_dly$1411$next[0:0]$2782 attribute \src "libresoc.v:47057.3-47065.6" wire $1\wr_pick_dly$1427$next[0:0]$2785 attribute \src "libresoc.v:47095.3-47103.6" wire $1\wr_pick_dly$1461$next[0:0]$2789 attribute \src "libresoc.v:47133.3-47141.6" wire $1\wr_pick_dly$1477$next[0:0]$2793 attribute \src "libresoc.v:47142.3-47150.6" wire $1\wr_pick_dly$1493$next[0:0]$2796 attribute \src "libresoc.v:47180.3-47188.6" wire $1\wr_pick_dly$1509$next[0:0]$2800 attribute \src "libresoc.v:47218.3-47226.6" wire $1\wr_pick_dly$1545$next[0:0]$2804 attribute \src "libresoc.v:47227.3-47235.6" wire $1\wr_pick_dly$1561$next[0:0]$2807 attribute \src "libresoc.v:47265.3-47273.6" wire $1\wr_pick_dly$1577$next[0:0]$2811 attribute \src "libresoc.v:47303.3-47311.6" wire $1\wr_pick_dly$1593$next[0:0]$2815 attribute \src "libresoc.v:47312.3-47320.6" wire $1\wr_pick_dly$1635$next[0:0]$2818 attribute \src "libresoc.v:47350.3-47358.6" wire $1\wr_pick_dly$1654$next[0:0]$2822 attribute \src "libresoc.v:47388.3-47396.6" wire $1\wr_pick_dly$1670$next[0:0]$2830 attribute \src "libresoc.v:47397.3-47405.6" wire $1\wr_pick_dly$1686$next[0:0]$2833 attribute \src "libresoc.v:47435.3-47443.6" wire $1\wr_pick_dly$1702$next[0:0]$2841 attribute \src "libresoc.v:47473.3-47481.6" wire $1\wr_pick_dly$1746$next[0:0]$2845 attribute \src "libresoc.v:47511.3-47519.6" wire $1\wr_pick_dly$1762$next[0:0]$2849 attribute \src "libresoc.v:47520.3-47528.6" wire $1\wr_pick_dly$1786$next[0:0]$2852 attribute \src "libresoc.v:47558.3-47566.6" wire $1\wr_pick_dly$1806$next[0:0]$2856 attribute \src "libresoc.v:46603.3-46611.6" wire $1\wr_pick_dly$989$next[0:0]$2721 attribute \src "libresoc.v:46594.3-46602.6" wire $1\wr_pick_dly$next[0:0]$2718 attribute \src "libresoc.v:41528.7-41528.25" wire $1\wr_pick_dly[0:0] attribute \src "libresoc.v:46390.3-46410.6" wire $2\core_terminate_o$next[0:0]$2681 attribute \src "libresoc.v:46280.3-46370.6" wire $2\corebusy_o[0:0] attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $2\counter$next[1:0]$2659 attribute \src "libresoc.v:47359.3-47387.6" wire $2\fus_cu_issue_i$13[0:0]$2826 attribute \src "libresoc.v:47684.3-47712.6" wire $2\fus_cu_issue_i$16[0:0]$2864 attribute \src "libresoc.v:48003.3-48031.6" wire $2\fus_cu_issue_i$19[0:0]$2883 attribute \src "libresoc.v:43648.3-43676.6" wire $2\fus_cu_issue_i$22[0:0]$2361 attribute \src "libresoc.v:43822.3-43850.6" wire $2\fus_cu_issue_i$25[0:0]$2375 attribute \src "libresoc.v:44318.3-44346.6" wire $2\fus_cu_issue_i$28[0:0]$2400 attribute \src "libresoc.v:44640.3-44668.6" wire $2\fus_cu_issue_i$31[0:0]$2419 attribute \src "libresoc.v:45107.3-45135.6" wire $2\fus_cu_issue_i$34[0:0]$2443 attribute \src "libresoc.v:45545.3-45573.6" wire $2\fus_cu_issue_i$37[0:0]$2466 attribute \src "libresoc.v:47151.3-47179.6" wire $2\fus_cu_issue_i[0:0] attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2837 attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869 attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888 attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366 attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380 attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405 attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424 attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448 attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471 attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0] attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] attribute \src "libresoc.v:46564.3-46593.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] attribute \src "libresoc.v:46735.3-46763.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] attribute \src "libresoc.v:46811.3-46839.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] attribute \src "libresoc.v:46981.3-47009.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] attribute \src "libresoc.v:47019.3-47047.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] attribute \src "libresoc.v:46943.3-46971.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] attribute \src "libresoc.v:46849.3-46877.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] attribute \src "libresoc.v:46773.3-46801.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0] attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] attribute \src "libresoc.v:47596.3-47625.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] attribute \src "libresoc.v:47655.3-47683.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] attribute \src "libresoc.v:47626.3-47654.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0] attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0] attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] attribute \src "libresoc.v:43938.3-43967.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] attribute \src "libresoc.v:44028.3-44056.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] attribute \src "libresoc.v:44115.3-44143.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] attribute \src "libresoc.v:44202.3-44230.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] attribute \src "libresoc.v:44231.3-44259.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] attribute \src "libresoc.v:44173.3-44201.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] attribute \src "libresoc.v:44144.3-44172.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] attribute \src "libresoc.v:44057.3-44085.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0] attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] attribute \src "libresoc.v:48119.3-48148.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] attribute \src "libresoc.v:48209.3-48237.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] attribute \src "libresoc.v:48296.3-48324.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] attribute \src "libresoc.v:43532.3-43560.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] attribute \src "libresoc.v:43561.3-43589.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] attribute \src "libresoc.v:43503.3-43531.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] attribute \src "libresoc.v:48325.3-48353.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] attribute \src "libresoc.v:48238.3-48266.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0] attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] attribute \src "libresoc.v:44434.3-44463.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] attribute \src "libresoc.v:44553.3-44581.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] attribute \src "libresoc.v:44582.3-44610.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] attribute \src "libresoc.v:44524.3-44552.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] attribute \src "libresoc.v:44756.3-44785.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] attribute \src "libresoc.v:44962.3-44990.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] attribute \src "libresoc.v:44875.3-44903.6" wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] attribute \src "libresoc.v:45020.3-45048.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] attribute \src "libresoc.v:45049.3-45077.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] attribute \src "libresoc.v:44933.3-44961.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] attribute \src "libresoc.v:44991.3-45019.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] attribute \src "libresoc.v:44846.3-44874.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0] attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] attribute \src "libresoc.v:43793.3-43821.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0] attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] attribute \src "libresoc.v:47887.3-47915.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] attribute \src "libresoc.v:45429.3-45457.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] attribute \src "libresoc.v:45223.3-45252.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] attribute \src "libresoc.v:45342.3-45370.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] attribute \src "libresoc.v:45371.3-45399.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] attribute \src "libresoc.v:45312.3-45341.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] attribute \src "libresoc.v:45312.3-45341.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] attribute \src "libresoc.v:45458.3-45486.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] attribute \src "libresoc.v:45253.3-45281.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] attribute \src "libresoc.v:46390.3-46410.6" wire $3\core_terminate_o$next[0:0]$2682 attribute \src "libresoc.v:46280.3-46370.6" wire $3\corebusy_o[0:0] attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $3\counter$next[1:0]$2660 attribute \src "libresoc.v:47359.3-47387.6" wire $3\fus_cu_issue_i$13[0:0]$2827 attribute \src "libresoc.v:47684.3-47712.6" wire $3\fus_cu_issue_i$16[0:0]$2865 attribute \src "libresoc.v:48003.3-48031.6" wire $3\fus_cu_issue_i$19[0:0]$2884 attribute \src "libresoc.v:43648.3-43676.6" wire $3\fus_cu_issue_i$22[0:0]$2362 attribute \src "libresoc.v:43822.3-43850.6" wire $3\fus_cu_issue_i$25[0:0]$2376 attribute \src "libresoc.v:44318.3-44346.6" wire $3\fus_cu_issue_i$28[0:0]$2401 attribute \src "libresoc.v:44640.3-44668.6" wire $3\fus_cu_issue_i$31[0:0]$2420 attribute \src "libresoc.v:45107.3-45135.6" wire $3\fus_cu_issue_i$34[0:0]$2444 attribute \src "libresoc.v:45545.3-45573.6" wire $3\fus_cu_issue_i$37[0:0]$2467 attribute \src "libresoc.v:47151.3-47179.6" wire $3\fus_cu_issue_i[0:0] attribute \src "libresoc.v:47406.3-47434.6" wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2838 attribute \src "libresoc.v:47713.3-47741.6" wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870 attribute \src "libresoc.v:48032.3-48060.6" wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889 attribute \src "libresoc.v:43677.3-43705.6" wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367 attribute \src "libresoc.v:43851.3-43879.6" wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381 attribute \src "libresoc.v:44347.3-44375.6" wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406 attribute \src "libresoc.v:44669.3-44697.6" wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425 attribute \src "libresoc.v:45136.3-45164.6" wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449 attribute \src "libresoc.v:45574.3-45602.6" wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472 attribute \src "libresoc.v:47189.3-47217.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] attribute \src "libresoc.v:47066.3-47094.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] attribute \src "libresoc.v:46516.3-46544.6" wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0] attribute \src "libresoc.v:46564.3-46593.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] attribute \src "libresoc.v:46564.3-46593.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] attribute \src "libresoc.v:46896.3-46924.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] attribute \src "libresoc.v:47104.3-47132.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] attribute \src "libresoc.v:46449.3-46477.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] attribute \src "libresoc.v:46735.3-46763.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] attribute \src "libresoc.v:46811.3-46839.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] attribute \src "libresoc.v:46981.3-47009.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] attribute \src "libresoc.v:47019.3-47047.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] attribute \src "libresoc.v:46678.3-46707.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] attribute \src "libresoc.v:46943.3-46971.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] attribute \src "libresoc.v:46621.3-46650.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] attribute \src "libresoc.v:46849.3-46877.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] attribute \src "libresoc.v:46773.3-46801.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] attribute \src "libresoc.v:47444.3-47472.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] attribute \src "libresoc.v:47529.3-47557.6" wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0] attribute \src "libresoc.v:47596.3-47625.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] attribute \src "libresoc.v:47596.3-47625.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] attribute \src "libresoc.v:47567.3-47595.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] attribute \src "libresoc.v:47482.3-47510.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] attribute \src "libresoc.v:47655.3-47683.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] attribute \src "libresoc.v:47626.3-47654.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] attribute \src "libresoc.v:47274.3-47302.6" wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0] attribute \src "libresoc.v:47321.3-47349.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] attribute \src "libresoc.v:47236.3-47264.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] attribute \src "libresoc.v:44260.3-44288.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] attribute \src "libresoc.v:43909.3-43937.6" wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0] attribute \src "libresoc.v:43938.3-43967.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] attribute \src "libresoc.v:43938.3-43967.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] attribute \src "libresoc.v:44086.3-44114.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] attribute \src "libresoc.v:44289.3-44317.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] attribute \src "libresoc.v:43880.3-43908.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] attribute \src "libresoc.v:44028.3-44056.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] attribute \src "libresoc.v:44115.3-44143.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] attribute \src "libresoc.v:44202.3-44230.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] attribute \src "libresoc.v:44231.3-44259.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] attribute \src "libresoc.v:43998.3-44027.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] attribute \src "libresoc.v:44173.3-44201.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] attribute \src "libresoc.v:43968.3-43997.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] attribute \src "libresoc.v:44144.3-44172.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] attribute \src "libresoc.v:44057.3-44085.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] attribute \src "libresoc.v:43590.3-43618.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] attribute \src "libresoc.v:48090.3-48118.6" wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0] attribute \src "libresoc.v:48119.3-48148.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] attribute \src "libresoc.v:48119.3-48148.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] attribute \src "libresoc.v:48267.3-48295.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] attribute \src "libresoc.v:43619.3-43647.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] attribute \src "libresoc.v:48061.3-48089.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] attribute \src "libresoc.v:48209.3-48237.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] attribute \src "libresoc.v:48296.3-48324.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] attribute \src "libresoc.v:43532.3-43560.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] attribute \src "libresoc.v:43561.3-43589.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] attribute \src "libresoc.v:48179.3-48208.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] attribute \src "libresoc.v:43503.3-43531.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] attribute \src "libresoc.v:48149.3-48178.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] attribute \src "libresoc.v:48325.3-48353.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] attribute \src "libresoc.v:48238.3-48266.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] attribute \src "libresoc.v:44405.3-44433.6" wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0] attribute \src "libresoc.v:44434.3-44463.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] attribute \src "libresoc.v:44434.3-44463.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] attribute \src "libresoc.v:44611.3-44639.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] attribute \src "libresoc.v:44376.3-44404.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] attribute \src "libresoc.v:44553.3-44581.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] attribute \src "libresoc.v:44582.3-44610.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] attribute \src "libresoc.v:44494.3-44523.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] attribute \src "libresoc.v:44464.3-44493.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] attribute \src "libresoc.v:44524.3-44552.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] attribute \src "libresoc.v:44727.3-44755.6" wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] attribute \src "libresoc.v:44756.3-44785.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] attribute \src "libresoc.v:44756.3-44785.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] attribute \src "libresoc.v:44904.3-44932.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] attribute \src "libresoc.v:44962.3-44990.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] attribute \src "libresoc.v:45078.3-45106.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] attribute \src "libresoc.v:44698.3-44726.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] attribute \src "libresoc.v:44875.3-44903.6" wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] attribute \src "libresoc.v:45020.3-45048.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] attribute \src "libresoc.v:45049.3-45077.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] attribute \src "libresoc.v:44816.3-44845.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] attribute \src "libresoc.v:44933.3-44961.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] attribute \src "libresoc.v:44991.3-45019.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] attribute \src "libresoc.v:44786.3-44815.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] attribute \src "libresoc.v:44846.3-44874.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] attribute \src "libresoc.v:43735.3-43763.6" wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0] attribute \src "libresoc.v:43764.3-43792.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] attribute \src "libresoc.v:43706.3-43734.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] attribute \src "libresoc.v:43793.3-43821.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] attribute \src "libresoc.v:47858.3-47886.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] attribute \src "libresoc.v:47771.3-47799.6" wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0] attribute \src "libresoc.v:47800.3-47828.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] attribute \src "libresoc.v:47742.3-47770.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] attribute \src "libresoc.v:47887.3-47915.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] attribute \src "libresoc.v:47974.3-48002.6" wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] attribute \src "libresoc.v:47829.3-47857.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] attribute \src "libresoc.v:47945.3-47973.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] attribute \src "libresoc.v:47916.3-47944.6" wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] attribute \src "libresoc.v:45429.3-45457.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] attribute \src "libresoc.v:45400.3-45428.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] attribute \src "libresoc.v:45194.3-45222.6" wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] attribute \src "libresoc.v:45223.3-45252.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] attribute \src "libresoc.v:45223.3-45252.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] attribute \src "libresoc.v:45516.3-45544.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] attribute \src "libresoc.v:45165.3-45193.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] attribute \src "libresoc.v:45342.3-45370.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] attribute \src "libresoc.v:45371.3-45399.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] attribute \src "libresoc.v:45487.3-45515.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] attribute \src "libresoc.v:45312.3-45341.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] attribute \src "libresoc.v:45312.3-45341.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] attribute \src "libresoc.v:45282.3-45311.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] attribute \src "libresoc.v:45458.3-45486.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] attribute \src "libresoc.v:45253.3-45281.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $4\corebusy_o[0:0] attribute \src "libresoc.v:46220.3-46250.6" wire width 2 $4\counter$next[1:0]$2661 attribute \src "libresoc.v:46280.3-46370.6" wire $5\corebusy_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $6\corebusy_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $7\corebusy_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $8\corebusy_o[0:0] attribute \src "libresoc.v:46280.3-46370.6" wire $9\corebusy_o[0:0] attribute \src "libresoc.v:41908.20-41908.122" wire $and$libresoc.v:41908$1507_Y attribute \src "libresoc.v:41909.20-41909.126" wire $and$libresoc.v:41909$1508_Y attribute \src "libresoc.v:41911.20-41911.110" wire $and$libresoc.v:41911$1510_Y attribute \src "libresoc.v:41912.20-41912.123" wire $and$libresoc.v:41912$1511_Y attribute \src "libresoc.v:41914.20-41914.122" wire $and$libresoc.v:41914$1513_Y attribute \src "libresoc.v:41915.20-41915.126" wire $and$libresoc.v:41915$1514_Y attribute \src "libresoc.v:41917.20-41917.110" wire $and$libresoc.v:41917$1516_Y attribute \src "libresoc.v:41918.20-41918.123" wire $and$libresoc.v:41918$1517_Y attribute \src "libresoc.v:41920.20-41920.123" wire $and$libresoc.v:41920$1519_Y attribute \src "libresoc.v:41921.20-41921.126" wire $and$libresoc.v:41921$1520_Y attribute \src "libresoc.v:41923.20-41923.110" wire $and$libresoc.v:41923$1522_Y attribute \src "libresoc.v:41924.20-41924.123" wire $and$libresoc.v:41924$1523_Y attribute \src "libresoc.v:41926.20-41926.123" wire $and$libresoc.v:41926$1525_Y attribute \src "libresoc.v:41927.20-41927.126" wire $and$libresoc.v:41927$1526_Y attribute \src "libresoc.v:41929.20-41929.110" wire $and$libresoc.v:41929$1528_Y attribute \src "libresoc.v:41930.20-41930.123" wire $and$libresoc.v:41930$1529_Y attribute \src "libresoc.v:41932.20-41932.123" wire $and$libresoc.v:41932$1531_Y attribute \src "libresoc.v:41933.20-41933.126" wire $and$libresoc.v:41933$1532_Y attribute \src "libresoc.v:41935.20-41935.110" wire $and$libresoc.v:41935$1534_Y attribute \src "libresoc.v:41936.20-41936.123" wire $and$libresoc.v:41936$1535_Y attribute \src "libresoc.v:41938.20-41938.123" wire $and$libresoc.v:41938$1537_Y attribute \src "libresoc.v:41939.20-41939.126" wire $and$libresoc.v:41939$1538_Y attribute \src "libresoc.v:41941.20-41941.110" wire $and$libresoc.v:41941$1540_Y attribute \src "libresoc.v:41942.20-41942.123" wire $and$libresoc.v:41942$1541_Y attribute \src "libresoc.v:41944.20-41944.113" wire $and$libresoc.v:41944$1543_Y attribute \src "libresoc.v:41945.20-41945.126" wire $and$libresoc.v:41945$1544_Y attribute \src "libresoc.v:41947.20-41947.110" wire $and$libresoc.v:41947$1546_Y attribute \src "libresoc.v:41948.20-41948.123" wire $and$libresoc.v:41948$1547_Y attribute \src "libresoc.v:41950.20-41950.114" wire $and$libresoc.v:41950$1549_Y attribute \src "libresoc.v:41951.20-41951.126" wire $and$libresoc.v:41951$1550_Y attribute \src "libresoc.v:41953.20-41953.110" wire $and$libresoc.v:41953$1552_Y attribute \src "libresoc.v:41954.20-41954.123" wire $and$libresoc.v:41954$1553_Y attribute \src "libresoc.v:41983.20-41983.123" wire $and$libresoc.v:41983$1582_Y attribute \src "libresoc.v:41984.20-41984.128" wire $and$libresoc.v:41984$1583_Y attribute \src "libresoc.v:41985.20-41985.133" wire $and$libresoc.v:41985$1584_Y attribute \src "libresoc.v:41987.20-41987.110" wire $and$libresoc.v:41987$1586_Y attribute \src "libresoc.v:41988.20-41988.128" wire $and$libresoc.v:41988$1587_Y attribute \src "libresoc.v:41990.20-41990.116" wire $and$libresoc.v:41990$1589_Y attribute \src "libresoc.v:41991.20-41991.123" wire $and$libresoc.v:41991$1590_Y attribute \src "libresoc.v:41992.20-41992.128" wire $and$libresoc.v:41992$1591_Y attribute \src "libresoc.v:41993.20-41993.128" wire $and$libresoc.v:41993$1592_Y attribute \src "libresoc.v:41994.20-41994.129" wire $and$libresoc.v:41994$1593_Y attribute \src "libresoc.v:41995.20-41995.129" wire $and$libresoc.v:41995$1594_Y attribute \src "libresoc.v:41996.20-41996.129" wire $and$libresoc.v:41996$1595_Y attribute \src "libresoc.v:41997.20-41997.130" wire $and$libresoc.v:41997$1596_Y attribute \src "libresoc.v:41999.20-41999.110" wire $and$libresoc.v:41999$1598_Y attribute \src "libresoc.v:42000.20-42000.125" wire $and$libresoc.v:42000$1599_Y attribute \src "libresoc.v:42004.20-42004.126" wire $and$libresoc.v:42004$1603_Y attribute \src "libresoc.v:42005.20-42005.130" wire $and$libresoc.v:42005$1604_Y attribute \src "libresoc.v:42007.20-42007.110" wire $and$libresoc.v:42007$1606_Y attribute \src "libresoc.v:42008.20-42008.125" wire $and$libresoc.v:42008$1607_Y attribute \src "libresoc.v:42012.20-42012.126" wire $and$libresoc.v:42012$1611_Y attribute \src "libresoc.v:42013.20-42013.130" wire $and$libresoc.v:42013$1612_Y attribute \src "libresoc.v:42015.20-42015.110" wire $and$libresoc.v:42015$1614_Y attribute \src "libresoc.v:42016.20-42016.125" wire $and$libresoc.v:42016$1615_Y attribute \src "libresoc.v:42020.20-42020.126" wire $and$libresoc.v:42020$1619_Y attribute \src "libresoc.v:42021.20-42021.130" wire $and$libresoc.v:42021$1620_Y attribute \src "libresoc.v:42023.20-42023.110" wire $and$libresoc.v:42023$1622_Y attribute \src "libresoc.v:42024.20-42024.125" wire $and$libresoc.v:42024$1623_Y attribute \src "libresoc.v:42028.20-42028.126" wire $and$libresoc.v:42028$1627_Y attribute \src "libresoc.v:42029.20-42029.130" wire $and$libresoc.v:42029$1628_Y attribute \src "libresoc.v:42031.20-42031.110" wire $and$libresoc.v:42031$1630_Y attribute \src "libresoc.v:42032.20-42032.125" wire $and$libresoc.v:42032$1631_Y attribute \src "libresoc.v:42036.20-42036.126" wire $and$libresoc.v:42036$1635_Y attribute \src "libresoc.v:42037.20-42037.130" wire $and$libresoc.v:42037$1636_Y attribute \src "libresoc.v:42039.20-42039.110" wire $and$libresoc.v:42039$1638_Y attribute \src "libresoc.v:42040.20-42040.125" wire $and$libresoc.v:42040$1639_Y attribute \src "libresoc.v:42054.20-42054.118" wire $and$libresoc.v:42054$1653_Y attribute \src "libresoc.v:42055.20-42055.123" wire $and$libresoc.v:42055$1654_Y attribute \src "libresoc.v:42056.20-42056.129" wire $and$libresoc.v:42056$1655_Y attribute \src "libresoc.v:42057.20-42057.129" wire $and$libresoc.v:42057$1656_Y attribute \src "libresoc.v:42058.20-42058.136" wire $and$libresoc.v:42058$1657_Y attribute \src "libresoc.v:42060.20-42060.110" wire $and$libresoc.v:42060$1659_Y attribute \src "libresoc.v:42061.20-42061.128" wire $and$libresoc.v:42061$1660_Y attribute \src "libresoc.v:42063.20-42063.128" wire $and$libresoc.v:42063$1662_Y attribute \src "libresoc.v:42064.20-42064.136" wire $and$libresoc.v:42064$1663_Y attribute \src "libresoc.v:42066.20-42066.110" wire $and$libresoc.v:42066$1665_Y attribute \src "libresoc.v:42067.20-42067.128" wire $and$libresoc.v:42067$1666_Y attribute \src "libresoc.v:42069.20-42069.128" wire $and$libresoc.v:42069$1668_Y attribute \src "libresoc.v:42070.20-42070.136" wire $and$libresoc.v:42070$1669_Y attribute \src "libresoc.v:42072.20-42072.110" wire $and$libresoc.v:42072$1671_Y attribute \src "libresoc.v:42073.20-42073.128" wire $and$libresoc.v:42073$1672_Y attribute \src "libresoc.v:42080.20-42080.118" wire $and$libresoc.v:42080$1680_Y attribute \src "libresoc.v:42081.20-42081.123" wire $and$libresoc.v:42081$1681_Y attribute \src "libresoc.v:42082.20-42082.129" wire $and$libresoc.v:42082$1682_Y attribute \src "libresoc.v:42083.20-42083.129" wire $and$libresoc.v:42083$1683_Y attribute \src "libresoc.v:42084.20-42084.129" wire $and$libresoc.v:42084$1684_Y attribute \src "libresoc.v:42085.20-42085.136" wire $and$libresoc.v:42085$1685_Y attribute \src "libresoc.v:42087.20-42087.110" wire $and$libresoc.v:42087$1687_Y attribute \src "libresoc.v:42088.20-42088.128" wire $and$libresoc.v:42088$1688_Y attribute \src "libresoc.v:42090.20-42090.128" wire $and$libresoc.v:42090$1690_Y attribute \src "libresoc.v:42091.20-42091.136" wire $and$libresoc.v:42091$1691_Y attribute \src "libresoc.v:42093.20-42093.110" wire $and$libresoc.v:42093$1693_Y attribute \src "libresoc.v:42094.20-42094.128" wire $and$libresoc.v:42094$1694_Y attribute \src "libresoc.v:42096.20-42096.128" wire $and$libresoc.v:42096$1696_Y attribute \src "libresoc.v:42097.20-42097.136" wire $and$libresoc.v:42097$1697_Y attribute \src "libresoc.v:42099.20-42099.110" wire $and$libresoc.v:42099$1699_Y attribute \src "libresoc.v:42100.20-42100.128" wire $and$libresoc.v:42100$1700_Y attribute \src "libresoc.v:42102.20-42102.128" wire $and$libresoc.v:42102$1702_Y attribute \src "libresoc.v:42103.20-42103.136" wire $and$libresoc.v:42103$1703_Y attribute \src "libresoc.v:42105.20-42105.110" wire $and$libresoc.v:42105$1705_Y attribute \src "libresoc.v:42106.20-42106.128" wire $and$libresoc.v:42106$1706_Y attribute \src "libresoc.v:42114.20-42114.118" wire $and$libresoc.v:42114$1714_Y attribute \src "libresoc.v:42115.20-42115.123" wire $and$libresoc.v:42115$1715_Y attribute \src "libresoc.v:42116.20-42116.129" wire $and$libresoc.v:42116$1716_Y attribute \src "libresoc.v:42117.20-42117.129" wire $and$libresoc.v:42117$1717_Y attribute \src "libresoc.v:42118.20-42118.129" wire $and$libresoc.v:42118$1718_Y attribute \src "libresoc.v:42119.20-42119.136" wire $and$libresoc.v:42119$1719_Y attribute \src "libresoc.v:42121.20-42121.110" wire $and$libresoc.v:42121$1721_Y attribute \src "libresoc.v:42122.20-42122.128" wire $and$libresoc.v:42122$1722_Y attribute \src "libresoc.v:42124.20-42124.128" wire $and$libresoc.v:42124$1724_Y attribute \src "libresoc.v:42125.20-42125.136" wire $and$libresoc.v:42125$1725_Y attribute \src "libresoc.v:42127.20-42127.110" wire $and$libresoc.v:42127$1727_Y attribute \src "libresoc.v:42128.20-42128.128" wire $and$libresoc.v:42128$1728_Y attribute \src "libresoc.v:42130.20-42130.128" wire $and$libresoc.v:42130$1730_Y attribute \src "libresoc.v:42131.20-42131.136" wire $and$libresoc.v:42131$1731_Y attribute \src "libresoc.v:42133.20-42133.110" wire $and$libresoc.v:42133$1733_Y attribute \src "libresoc.v:42134.20-42134.128" wire $and$libresoc.v:42134$1734_Y attribute \src "libresoc.v:42136.20-42136.128" wire $and$libresoc.v:42136$1736_Y attribute \src "libresoc.v:42137.20-42137.136" wire $and$libresoc.v:42137$1737_Y attribute \src "libresoc.v:42139.20-42139.110" wire $and$libresoc.v:42139$1739_Y attribute \src "libresoc.v:42140.20-42140.128" wire $and$libresoc.v:42140$1740_Y attribute \src "libresoc.v:42150.20-42150.121" wire $and$libresoc.v:42150$1752_Y attribute \src "libresoc.v:42151.20-42151.129" wire $and$libresoc.v:42151$1753_Y attribute \src "libresoc.v:42152.20-42152.128" wire $and$libresoc.v:42152$1754_Y attribute \src "libresoc.v:42153.20-42153.129" wire $and$libresoc.v:42153$1755_Y attribute \src "libresoc.v:42154.20-42154.129" wire $and$libresoc.v:42154$1756_Y attribute \src "libresoc.v:42155.20-42155.128" wire $and$libresoc.v:42155$1757_Y attribute \src "libresoc.v:42156.20-42156.136" wire $and$libresoc.v:42156$1758_Y attribute \src "libresoc.v:42158.20-42158.110" wire $and$libresoc.v:42158$1760_Y attribute \src "libresoc.v:42159.20-42159.128" wire $and$libresoc.v:42159$1761_Y attribute \src "libresoc.v:42161.20-42161.127" wire $and$libresoc.v:42161$1763_Y attribute \src "libresoc.v:42162.20-42162.136" wire $and$libresoc.v:42162$1764_Y attribute \src "libresoc.v:42164.20-42164.110" wire $and$libresoc.v:42164$1766_Y attribute \src "libresoc.v:42165.20-42165.128" wire $and$libresoc.v:42165$1767_Y attribute \src "libresoc.v:42167.20-42167.127" wire $and$libresoc.v:42167$1769_Y attribute \src "libresoc.v:42168.20-42168.136" wire $and$libresoc.v:42168$1770_Y attribute \src "libresoc.v:42170.20-42170.110" wire $and$libresoc.v:42170$1772_Y attribute \src "libresoc.v:42171.20-42171.128" wire $and$libresoc.v:42171$1773_Y attribute \src "libresoc.v:42173.20-42173.121" wire $and$libresoc.v:42173$1775_Y attribute \src "libresoc.v:42174.20-42174.136" wire $and$libresoc.v:42174$1776_Y attribute \src "libresoc.v:42176.20-42176.110" wire $and$libresoc.v:42176$1778_Y attribute \src "libresoc.v:42177.20-42177.128" wire $and$libresoc.v:42177$1779_Y attribute \src "libresoc.v:42179.20-42179.127" wire $and$libresoc.v:42179$1781_Y attribute \src "libresoc.v:42180.20-42180.136" wire $and$libresoc.v:42180$1782_Y attribute \src "libresoc.v:42182.20-42182.110" wire $and$libresoc.v:42182$1784_Y attribute \src "libresoc.v:42183.20-42183.128" wire $and$libresoc.v:42183$1785_Y attribute \src "libresoc.v:42197.20-42197.119" wire $and$libresoc.v:42197$1799_Y attribute \src "libresoc.v:42198.20-42198.129" wire $and$libresoc.v:42198$1800_Y attribute \src "libresoc.v:42199.20-42199.128" wire $and$libresoc.v:42199$1801_Y attribute \src "libresoc.v:42200.20-42200.134" wire $and$libresoc.v:42200$1802_Y attribute \src "libresoc.v:42202.20-42202.110" wire $and$libresoc.v:42202$1804_Y attribute \src "libresoc.v:42203.20-42203.127" wire $and$libresoc.v:42203$1805_Y attribute \src "libresoc.v:42205.20-42205.125" wire $and$libresoc.v:42205$1807_Y attribute \src "libresoc.v:42206.20-42206.134" wire $and$libresoc.v:42206$1808_Y attribute \src "libresoc.v:42208.20-42208.110" wire $and$libresoc.v:42208$1810_Y attribute \src "libresoc.v:42209.20-42209.127" wire $and$libresoc.v:42209$1811_Y attribute \src "libresoc.v:42214.20-42214.119" wire $and$libresoc.v:42214$1817_Y attribute \src "libresoc.v:42215.20-42215.128" wire $and$libresoc.v:42215$1818_Y attribute \src "libresoc.v:42216.20-42216.131" wire $and$libresoc.v:42216$1819_Y attribute \src "libresoc.v:42218.20-42218.110" wire $and$libresoc.v:42218$1821_Y attribute \src "libresoc.v:42219.20-42219.127" wire $and$libresoc.v:42219$1822_Y attribute \src "libresoc.v:42222.20-42222.120" wire $and$libresoc.v:42222$1826_Y attribute \src "libresoc.v:42223.20-42223.129" wire $and$libresoc.v:42223$1827_Y attribute \src "libresoc.v:42224.20-42224.129" wire $and$libresoc.v:42224$1828_Y attribute \src "libresoc.v:42226.20-42226.110" wire $and$libresoc.v:42226$1830_Y attribute \src "libresoc.v:42227.20-42227.126" wire $and$libresoc.v:42227$1831_Y attribute \src "libresoc.v:42229.19-42229.112" wire width 14 $and$libresoc.v:42229$1833_Y attribute \src "libresoc.v:42231.19-42231.113" wire width 14 $and$libresoc.v:42231$1835_Y attribute \src "libresoc.v:42233.19-42233.113" wire width 14 $and$libresoc.v:42233$1837_Y attribute \src "libresoc.v:42235.19-42235.113" wire width 14 $and$libresoc.v:42235$1839_Y attribute \src "libresoc.v:42237.19-42237.113" wire width 14 $and$libresoc.v:42237$1841_Y attribute \src "libresoc.v:42239.19-42239.115" wire width 14 $and$libresoc.v:42239$1843_Y attribute \src "libresoc.v:42241.19-42241.115" wire width 14 $and$libresoc.v:42241$1845_Y attribute \src "libresoc.v:42243.19-42243.114" wire width 14 $and$libresoc.v:42243$1847_Y attribute \src "libresoc.v:42245.19-42245.112" wire width 14 $and$libresoc.v:42245$1849_Y attribute \src "libresoc.v:42247.19-42247.112" wire width 14 $and$libresoc.v:42247$1851_Y attribute \src "libresoc.v:42252.19-42252.131" wire $and$libresoc.v:42252$1856_Y attribute \src "libresoc.v:42253.19-42253.119" wire width 3 $and$libresoc.v:42253$1857_Y attribute \src "libresoc.v:42256.19-42256.131" wire $and$libresoc.v:42256$1860_Y attribute \src "libresoc.v:42259.19-42259.119" wire width 3 $and$libresoc.v:42259$1863_Y attribute \src "libresoc.v:42266.19-42266.131" wire $and$libresoc.v:42266$1870_Y attribute \src "libresoc.v:42267.19-42267.119" wire width 3 $and$libresoc.v:42267$1871_Y attribute \src "libresoc.v:42270.19-42270.131" wire $and$libresoc.v:42270$1874_Y attribute \src "libresoc.v:42273.19-42273.131" wire $and$libresoc.v:42273$1877_Y attribute \src "libresoc.v:42274.19-42274.119" wire width 3 $and$libresoc.v:42274$1878_Y attribute \src "libresoc.v:42277.19-42277.131" wire $and$libresoc.v:42277$1881_Y attribute \src "libresoc.v:42279.19-42279.131" wire $and$libresoc.v:42279$1883_Y attribute \src "libresoc.v:42280.19-42280.119" wire width 3 $and$libresoc.v:42280$1884_Y attribute \src "libresoc.v:42284.19-42284.119" wire width 3 $and$libresoc.v:42284$1888_Y attribute \src "libresoc.v:42288.19-42288.131" wire $and$libresoc.v:42288$1892_Y attribute \src "libresoc.v:42289.19-42289.119" wire width 3 $and$libresoc.v:42289$1893_Y attribute \src "libresoc.v:42292.19-42292.131" wire $and$libresoc.v:42292$1896_Y attribute \src "libresoc.v:42295.19-42295.131" wire $and$libresoc.v:42295$1899_Y attribute \src "libresoc.v:42296.19-42296.119" wire width 3 $and$libresoc.v:42296$1900_Y attribute \src "libresoc.v:42299.19-42299.131" wire $and$libresoc.v:42299$1903_Y attribute \src "libresoc.v:42302.19-42302.131" wire $and$libresoc.v:42302$1906_Y attribute \src "libresoc.v:42303.19-42303.119" wire width 3 $and$libresoc.v:42303$1907_Y attribute \src "libresoc.v:42306.19-42306.131" wire $and$libresoc.v:42306$1910_Y attribute \src "libresoc.v:42309.19-42309.119" wire width 3 $and$libresoc.v:42309$1913_Y attribute \src "libresoc.v:42314.19-42314.122" wire $and$libresoc.v:42314$1918_Y attribute \src "libresoc.v:42315.19-42315.114" wire $and$libresoc.v:42315$1919_Y attribute \src "libresoc.v:42317.19-42317.102" wire $and$libresoc.v:42317$1921_Y attribute \src "libresoc.v:42318.19-42318.131" wire $and$libresoc.v:42318$1922_Y attribute \src "libresoc.v:42320.19-42320.127" wire $and$libresoc.v:42320$1924_Y attribute \src "libresoc.v:42321.19-42321.114" wire $and$libresoc.v:42321$1925_Y attribute \src "libresoc.v:42323.19-42323.102" wire $and$libresoc.v:42323$1927_Y attribute \src "libresoc.v:42324.19-42324.131" wire $and$libresoc.v:42324$1928_Y attribute \src "libresoc.v:42326.19-42326.127" wire $and$libresoc.v:42326$1930_Y attribute \src "libresoc.v:42327.19-42327.114" wire $and$libresoc.v:42327$1931_Y attribute \src "libresoc.v:42329.19-42329.102" wire $and$libresoc.v:42329$1933_Y attribute \src "libresoc.v:42330.19-42330.131" wire $and$libresoc.v:42330$1934_Y attribute \src "libresoc.v:42332.19-42332.127" wire $and$libresoc.v:42332$1936_Y attribute \src "libresoc.v:42333.19-42333.114" wire $and$libresoc.v:42333$1937_Y attribute \src "libresoc.v:42335.19-42335.102" wire $and$libresoc.v:42335$1939_Y attribute \src "libresoc.v:42336.19-42336.131" wire $and$libresoc.v:42336$1940_Y attribute \src "libresoc.v:42338.19-42338.127" wire $and$libresoc.v:42338$1942_Y attribute \src "libresoc.v:42339.19-42339.114" wire $and$libresoc.v:42339$1943_Y attribute \src "libresoc.v:42341.19-42341.102" wire $and$libresoc.v:42341$1945_Y attribute \src "libresoc.v:42342.19-42342.131" wire $and$libresoc.v:42342$1946_Y attribute \src "libresoc.v:42344.19-42344.127" wire $and$libresoc.v:42344$1948_Y attribute \src "libresoc.v:42345.19-42345.114" wire $and$libresoc.v:42345$1949_Y attribute \src "libresoc.v:42347.19-42347.102" wire $and$libresoc.v:42347$1951_Y attribute \src "libresoc.v:42348.19-42348.131" wire $and$libresoc.v:42348$1952_Y attribute \src "libresoc.v:42350.19-42350.127" wire $and$libresoc.v:42350$1954_Y attribute \src "libresoc.v:42351.19-42351.114" wire $and$libresoc.v:42351$1955_Y attribute \src "libresoc.v:42353.19-42353.102" wire $and$libresoc.v:42353$1957_Y attribute \src "libresoc.v:42354.19-42354.131" wire $and$libresoc.v:42354$1958_Y attribute \src "libresoc.v:42356.19-42356.127" wire $and$libresoc.v:42356$1960_Y attribute \src "libresoc.v:42357.19-42357.114" wire $and$libresoc.v:42357$1961_Y attribute \src "libresoc.v:42359.19-42359.102" wire $and$libresoc.v:42359$1963_Y attribute \src "libresoc.v:42360.19-42360.131" wire $and$libresoc.v:42360$1964_Y attribute \src "libresoc.v:42362.19-42362.127" wire $and$libresoc.v:42362$1966_Y attribute \src "libresoc.v:42363.19-42363.114" wire $and$libresoc.v:42363$1967_Y attribute \src "libresoc.v:42365.19-42365.102" wire $and$libresoc.v:42365$1969_Y attribute \src "libresoc.v:42366.19-42366.131" wire $and$libresoc.v:42366$1970_Y attribute \src "libresoc.v:42368.19-42368.127" wire $and$libresoc.v:42368$1972_Y attribute \src "libresoc.v:42369.19-42369.114" wire $and$libresoc.v:42369$1973_Y attribute \src "libresoc.v:42371.19-42371.102" wire $and$libresoc.v:42371$1975_Y attribute \src "libresoc.v:42372.19-42372.131" wire $and$libresoc.v:42372$1976_Y attribute \src "libresoc.v:42374.19-42374.122" wire $and$libresoc.v:42374$1978_Y attribute \src "libresoc.v:42375.19-42375.114" wire $and$libresoc.v:42375$1979_Y attribute \src "libresoc.v:42377.19-42377.102" wire $and$libresoc.v:42377$1981_Y attribute \src "libresoc.v:42378.19-42378.132" wire $and$libresoc.v:42378$1982_Y attribute \src "libresoc.v:42380.19-42380.127" wire $and$libresoc.v:42380$1984_Y attribute \src "libresoc.v:42381.19-42381.114" wire $and$libresoc.v:42381$1985_Y attribute \src "libresoc.v:42383.19-42383.102" wire $and$libresoc.v:42383$1987_Y attribute \src "libresoc.v:42384.19-42384.132" wire $and$libresoc.v:42384$1988_Y attribute \src "libresoc.v:42386.19-42386.127" wire $and$libresoc.v:42386$1990_Y attribute \src "libresoc.v:42387.19-42387.114" wire $and$libresoc.v:42387$1991_Y attribute \src "libresoc.v:42389.19-42389.102" wire $and$libresoc.v:42389$1993_Y attribute \src "libresoc.v:42390.19-42390.132" wire $and$libresoc.v:42390$1994_Y attribute \src "libresoc.v:42392.19-42392.127" wire $and$libresoc.v:42392$1996_Y attribute \src "libresoc.v:42393.19-42393.114" wire $and$libresoc.v:42393$1997_Y attribute \src "libresoc.v:42395.19-42395.102" wire $and$libresoc.v:42395$1999_Y attribute \src "libresoc.v:42396.19-42396.132" wire $and$libresoc.v:42396$2000_Y attribute \src "libresoc.v:42398.19-42398.127" wire $and$libresoc.v:42398$2002_Y attribute \src "libresoc.v:42399.19-42399.114" wire $and$libresoc.v:42399$2003_Y attribute \src "libresoc.v:42401.19-42401.102" wire $and$libresoc.v:42401$2005_Y attribute \src "libresoc.v:42402.19-42402.132" wire $and$libresoc.v:42402$2006_Y attribute \src "libresoc.v:42404.19-42404.127" wire $and$libresoc.v:42404$2008_Y attribute \src "libresoc.v:42405.19-42405.114" wire $and$libresoc.v:42405$2009_Y attribute \src "libresoc.v:42407.19-42407.102" wire $and$libresoc.v:42407$2011_Y attribute \src "libresoc.v:42408.19-42408.132" wire $and$libresoc.v:42408$2012_Y attribute \src "libresoc.v:42410.19-42410.127" wire $and$libresoc.v:42410$2014_Y attribute \src "libresoc.v:42411.19-42411.114" wire $and$libresoc.v:42411$2015_Y attribute \src "libresoc.v:42413.19-42413.102" wire $and$libresoc.v:42413$2017_Y attribute \src "libresoc.v:42414.19-42414.132" wire $and$libresoc.v:42414$2018_Y attribute \src "libresoc.v:42416.19-42416.127" wire $and$libresoc.v:42416$2020_Y attribute \src "libresoc.v:42417.19-42417.114" wire $and$libresoc.v:42417$2021_Y attribute \src "libresoc.v:42419.19-42419.102" wire $and$libresoc.v:42419$2023_Y attribute \src "libresoc.v:42420.19-42420.132" wire $and$libresoc.v:42420$2024_Y attribute \src "libresoc.v:42422.19-42422.127" wire $and$libresoc.v:42422$2026_Y attribute \src "libresoc.v:42423.19-42423.114" wire $and$libresoc.v:42423$2027_Y attribute \src "libresoc.v:42425.19-42425.102" wire $and$libresoc.v:42425$2029_Y attribute \src "libresoc.v:42426.19-42426.132" wire $and$libresoc.v:42426$2030_Y attribute \src "libresoc.v:42447.19-42447.131" wire $and$libresoc.v:42447$2051_Y attribute \src "libresoc.v:42448.19-42448.119" wire width 3 $and$libresoc.v:42448$2052_Y attribute \src "libresoc.v:42451.19-42451.131" wire $and$libresoc.v:42451$2055_Y attribute \src "libresoc.v:42453.19-42453.122" wire $and$libresoc.v:42453$2057_Y attribute \src "libresoc.v:42454.19-42454.116" wire $and$libresoc.v:42454$2058_Y attribute \src "libresoc.v:42456.19-42456.102" wire $and$libresoc.v:42456$2060_Y attribute \src "libresoc.v:42457.19-42457.135" wire $and$libresoc.v:42457$2061_Y attribute \src "libresoc.v:42459.19-42459.127" wire $and$libresoc.v:42459$2063_Y attribute \src "libresoc.v:42460.19-42460.116" wire $and$libresoc.v:42460$2064_Y attribute \src "libresoc.v:42462.19-42462.102" wire $and$libresoc.v:42462$2066_Y attribute \src "libresoc.v:42463.19-42463.135" wire $and$libresoc.v:42463$2067_Y attribute \src "libresoc.v:42465.19-42465.127" wire $and$libresoc.v:42465$2069_Y attribute \src "libresoc.v:42466.19-42466.116" wire $and$libresoc.v:42466$2070_Y attribute \src "libresoc.v:42468.19-42468.102" wire $and$libresoc.v:42468$2072_Y attribute \src "libresoc.v:42469.19-42469.135" wire $and$libresoc.v:42469$2073_Y attribute \src "libresoc.v:42471.19-42471.127" wire $and$libresoc.v:42471$2075_Y attribute \src "libresoc.v:42472.19-42472.116" wire $and$libresoc.v:42472$2076_Y attribute \src "libresoc.v:42474.19-42474.102" wire $and$libresoc.v:42474$2078_Y attribute \src "libresoc.v:42475.19-42475.135" wire $and$libresoc.v:42475$2079_Y attribute \src "libresoc.v:42477.19-42477.127" wire $and$libresoc.v:42477$2081_Y attribute \src "libresoc.v:42478.19-42478.116" wire $and$libresoc.v:42478$2082_Y attribute \src "libresoc.v:42480.19-42480.102" wire $and$libresoc.v:42480$2084_Y attribute \src "libresoc.v:42481.19-42481.135" wire $and$libresoc.v:42481$2085_Y attribute \src "libresoc.v:42483.19-42483.127" wire $and$libresoc.v:42483$2087_Y attribute \src "libresoc.v:42484.19-42484.116" wire $and$libresoc.v:42484$2088_Y attribute \src "libresoc.v:42486.19-42486.102" wire $and$libresoc.v:42486$2090_Y attribute \src "libresoc.v:42487.19-42487.135" wire $and$libresoc.v:42487$2091_Y attribute \src "libresoc.v:42496.19-42496.119" wire width 3 $and$libresoc.v:42496$2101_Y attribute \src "libresoc.v:42499.19-42499.122" wire $and$libresoc.v:42499$2104_Y attribute \src "libresoc.v:42500.19-42500.116" wire $and$libresoc.v:42500$2105_Y attribute \src "libresoc.v:42502.19-42502.102" wire $and$libresoc.v:42502$2107_Y attribute \src "libresoc.v:42503.19-42503.135" wire $and$libresoc.v:42503$2108_Y attribute \src "libresoc.v:42505.19-42505.127" wire $and$libresoc.v:42505$2110_Y attribute \src "libresoc.v:42506.19-42506.116" wire $and$libresoc.v:42506$2111_Y attribute \src "libresoc.v:42508.19-42508.102" wire $and$libresoc.v:42508$2113_Y attribute \src "libresoc.v:42509.19-42509.135" wire $and$libresoc.v:42509$2114_Y attribute \src "libresoc.v:42511.19-42511.127" wire $and$libresoc.v:42511$2116_Y attribute \src "libresoc.v:42512.19-42512.116" wire $and$libresoc.v:42512$2117_Y attribute \src "libresoc.v:42514.19-42514.102" wire $and$libresoc.v:42514$2119_Y attribute \src "libresoc.v:42515.19-42515.135" wire $and$libresoc.v:42515$2120_Y attribute \src "libresoc.v:42520.19-42520.131" wire $and$libresoc.v:42520$2126_Y attribute \src "libresoc.v:42521.19-42521.119" wire width 3 $and$libresoc.v:42521$2127_Y attribute \src "libresoc.v:42524.19-42524.127" wire $and$libresoc.v:42524$2130_Y attribute \src "libresoc.v:42525.19-42525.116" wire $and$libresoc.v:42525$2131_Y attribute \src "libresoc.v:42527.19-42527.102" wire $and$libresoc.v:42527$2133_Y attribute \src "libresoc.v:42528.19-42528.132" wire $and$libresoc.v:42528$2134_Y attribute \src "libresoc.v:42530.19-42530.127" wire $and$libresoc.v:42530$2136_Y attribute \src "libresoc.v:42531.19-42531.116" wire $and$libresoc.v:42531$2137_Y attribute \src "libresoc.v:42533.19-42533.102" wire $and$libresoc.v:42533$2139_Y attribute \src "libresoc.v:42534.19-42534.132" wire $and$libresoc.v:42534$2140_Y attribute \src "libresoc.v:42536.19-42536.127" wire $and$libresoc.v:42536$2142_Y attribute \src "libresoc.v:42537.19-42537.113" wire $and$libresoc.v:42537$2143_Y attribute \src "libresoc.v:42539.19-42539.102" wire $and$libresoc.v:42539$2145_Y attribute \src "libresoc.v:42540.19-42540.129" wire $and$libresoc.v:42540$2146_Y attribute \src "libresoc.v:42544.19-42544.127" wire $and$libresoc.v:42544$2150_Y attribute \src "libresoc.v:42545.19-42545.113" wire $and$libresoc.v:42545$2151_Y attribute \src "libresoc.v:42547.19-42547.102" wire $and$libresoc.v:42547$2153_Y attribute \src "libresoc.v:42548.19-42548.129" wire $and$libresoc.v:42548$2154_Y attribute \src "libresoc.v:42553.19-42553.127" wire $and$libresoc.v:42553$2159_Y attribute \src "libresoc.v:42554.19-42554.113" wire $and$libresoc.v:42554$2160_Y attribute \src "libresoc.v:42556.19-42556.102" wire $and$libresoc.v:42556$2162_Y attribute \src "libresoc.v:42557.19-42557.126" wire $and$libresoc.v:42557$2163_Y attribute \src "libresoc.v:42561.19-42561.127" wire $and$libresoc.v:42561$2167_Y attribute \src "libresoc.v:42562.19-42562.113" wire $and$libresoc.v:42562$2168_Y attribute \src "libresoc.v:42564.19-42564.102" wire $and$libresoc.v:42564$2170_Y attribute \src "libresoc.v:42565.19-42565.126" wire $and$libresoc.v:42565$2171_Y attribute \src "libresoc.v:42569.19-42569.127" wire $and$libresoc.v:42569$2175_Y attribute \src "libresoc.v:42570.19-42570.116" wire $and$libresoc.v:42570$2176_Y attribute \src "libresoc.v:42572.19-42572.102" wire $and$libresoc.v:42572$2178_Y attribute \src "libresoc.v:42573.19-42573.135" wire $and$libresoc.v:42573$2179_Y attribute \src "libresoc.v:42575.19-42575.127" wire $and$libresoc.v:42575$2181_Y attribute \src "libresoc.v:42576.19-42576.116" wire $and$libresoc.v:42576$2182_Y attribute \src "libresoc.v:42578.19-42578.102" wire $and$libresoc.v:42578$2184_Y attribute \src "libresoc.v:42579.19-42579.135" wire $and$libresoc.v:42579$2185_Y attribute \src "libresoc.v:42581.19-42581.127" wire $and$libresoc.v:42581$2187_Y attribute \src "libresoc.v:42582.19-42582.116" wire $and$libresoc.v:42582$2188_Y attribute \src "libresoc.v:42584.19-42584.102" wire $and$libresoc.v:42584$2190_Y attribute \src "libresoc.v:42585.19-42585.135" wire $and$libresoc.v:42585$2191_Y attribute \src "libresoc.v:42587.19-42587.127" wire $and$libresoc.v:42587$2193_Y attribute \src "libresoc.v:42588.19-42588.116" wire $and$libresoc.v:42588$2194_Y attribute \src "libresoc.v:42590.19-42590.102" wire $and$libresoc.v:42590$2196_Y attribute \src "libresoc.v:42591.19-42591.135" wire $and$libresoc.v:42591$2197_Y attribute \src "libresoc.v:42593.19-42593.127" wire $and$libresoc.v:42593$2199_Y attribute \src "libresoc.v:42594.19-42594.116" wire $and$libresoc.v:42594$2200_Y attribute \src "libresoc.v:42596.19-42596.102" wire $and$libresoc.v:42596$2202_Y attribute \src "libresoc.v:42597.19-42597.135" wire $and$libresoc.v:42597$2203_Y attribute \src "libresoc.v:42604.19-42604.127" wire $and$libresoc.v:42604$2210_Y attribute \src "libresoc.v:42605.19-42605.114" wire $and$libresoc.v:42605$2211_Y attribute \src "libresoc.v:42607.19-42607.102" wire $and$libresoc.v:42607$2213_Y attribute \src "libresoc.v:42608.19-42608.128" wire $and$libresoc.v:42608$2214_Y attribute \src "libresoc.v:42611.19-42611.112" wire $and$libresoc.v:42611$2217_Y attribute \src "libresoc.v:42612.19-42612.122" wire $and$libresoc.v:42612$2218_Y attribute \src "libresoc.v:42613.19-42613.127" wire $and$libresoc.v:42613$2219_Y attribute \src "libresoc.v:42614.19-42614.127" wire $and$libresoc.v:42614$2220_Y attribute \src "libresoc.v:42615.19-42615.127" wire $and$libresoc.v:42615$2221_Y attribute \src "libresoc.v:42616.19-42616.128" wire $and$libresoc.v:42616$2222_Y attribute \src "libresoc.v:42617.19-42617.128" wire $and$libresoc.v:42617$2223_Y attribute \src "libresoc.v:42618.19-42618.128" wire $and$libresoc.v:42618$2224_Y attribute \src "libresoc.v:42619.19-42619.128" wire $and$libresoc.v:42619$2225_Y attribute \src "libresoc.v:42620.19-42620.128" wire $and$libresoc.v:42620$2226_Y attribute \src "libresoc.v:42621.19-42621.128" wire $and$libresoc.v:42621$2227_Y attribute \src "libresoc.v:42622.19-42622.125" wire $and$libresoc.v:42622$2228_Y attribute \src "libresoc.v:42624.19-42624.101" wire $and$libresoc.v:42624$2230_Y attribute \src "libresoc.v:42625.19-42625.115" wire $and$libresoc.v:42625$2231_Y attribute \src "libresoc.v:42627.19-42627.121" wire $and$libresoc.v:42627$2233_Y attribute \src "libresoc.v:42628.19-42628.125" wire $and$libresoc.v:42628$2234_Y attribute \src "libresoc.v:42630.19-42630.107" wire $and$libresoc.v:42630$2236_Y attribute \src "libresoc.v:42631.19-42631.121" wire $and$libresoc.v:42631$2237_Y attribute \src "libresoc.v:42254.19-42254.115" wire $eq$libresoc.v:42254$1858_Y attribute \src "libresoc.v:42258.19-42258.130" wire $eq$libresoc.v:42258$1862_Y attribute \src "libresoc.v:42260.19-42260.115" wire $eq$libresoc.v:42260$1864_Y attribute \src "libresoc.v:42268.19-42268.115" wire $eq$libresoc.v:42268$1872_Y attribute \src "libresoc.v:42275.19-42275.115" wire $eq$libresoc.v:42275$1879_Y attribute \src "libresoc.v:42281.19-42281.115" wire $eq$libresoc.v:42281$1885_Y attribute \src "libresoc.v:42283.19-42283.130" wire $eq$libresoc.v:42283$1887_Y attribute \src "libresoc.v:42285.19-42285.115" wire $eq$libresoc.v:42285$1889_Y attribute \src "libresoc.v:42290.19-42290.115" wire $eq$libresoc.v:42290$1894_Y attribute \src "libresoc.v:42297.19-42297.115" wire $eq$libresoc.v:42297$1901_Y attribute \src "libresoc.v:42304.19-42304.115" wire $eq$libresoc.v:42304$1908_Y attribute \src "libresoc.v:42308.19-42308.130" wire $eq$libresoc.v:42308$1912_Y attribute \src "libresoc.v:42310.19-42310.115" wire $eq$libresoc.v:42310$1914_Y attribute \src "libresoc.v:42449.19-42449.115" wire $eq$libresoc.v:42449$2053_Y attribute \src "libresoc.v:42495.19-42495.130" wire $eq$libresoc.v:42495$2100_Y attribute \src "libresoc.v:42497.19-42497.115" wire $eq$libresoc.v:42497$2102_Y attribute \src "libresoc.v:42522.19-42522.115" wire $eq$libresoc.v:42522$2128_Y attribute \src "libresoc.v:42079.20-42079.95" wire width 3 $extend$libresoc.v:42079$1678_Y attribute \src "libresoc.v:42145.20-42145.95" wire width 2 $extend$libresoc.v:42145$1745_Y attribute \src "libresoc.v:42149.20-42149.95" wire width 3 $extend$libresoc.v:42149$1750_Y attribute \src "libresoc.v:42213.20-42213.95" wire width 3 $extend$libresoc.v:42213$1815_Y attribute \src "libresoc.v:42221.20-42221.104" wire width 3 $extend$libresoc.v:42221$1824_Y attribute \src "libresoc.v:42494.19-42494.93" wire width 3 $extend$libresoc.v:42494$2098_Y attribute \src "libresoc.v:42519.19-42519.93" wire width 3 $extend$libresoc.v:42519$2124_Y attribute \src "libresoc.v:42249.19-42249.103" wire $ne$libresoc.v:42249$1853_Y attribute \src "libresoc.v:42251.19-42251.103" wire $ne$libresoc.v:42251$1855_Y attribute \src "libresoc.v:41910.20-41910.106" wire $not$libresoc.v:41910$1509_Y attribute \src "libresoc.v:41916.20-41916.106" wire $not$libresoc.v:41916$1515_Y attribute \src "libresoc.v:41922.20-41922.106" wire $not$libresoc.v:41922$1521_Y attribute \src "libresoc.v:41928.20-41928.106" wire $not$libresoc.v:41928$1527_Y attribute \src "libresoc.v:41934.20-41934.106" wire $not$libresoc.v:41934$1533_Y attribute \src "libresoc.v:41940.20-41940.106" wire $not$libresoc.v:41940$1539_Y attribute \src "libresoc.v:41946.20-41946.106" wire $not$libresoc.v:41946$1545_Y attribute \src "libresoc.v:41952.20-41952.106" wire $not$libresoc.v:41952$1551_Y attribute \src "libresoc.v:41986.20-41986.106" wire $not$libresoc.v:41986$1585_Y attribute \src "libresoc.v:41998.20-41998.106" wire $not$libresoc.v:41998$1597_Y attribute \src "libresoc.v:42006.20-42006.106" wire $not$libresoc.v:42006$1605_Y attribute \src "libresoc.v:42014.20-42014.106" wire $not$libresoc.v:42014$1613_Y attribute \src "libresoc.v:42022.20-42022.106" wire $not$libresoc.v:42022$1621_Y attribute \src "libresoc.v:42030.20-42030.106" wire $not$libresoc.v:42030$1629_Y attribute \src "libresoc.v:42038.20-42038.106" wire $not$libresoc.v:42038$1637_Y attribute \src "libresoc.v:42059.20-42059.106" wire $not$libresoc.v:42059$1658_Y attribute \src "libresoc.v:42065.20-42065.106" wire $not$libresoc.v:42065$1664_Y attribute \src "libresoc.v:42071.20-42071.106" wire $not$libresoc.v:42071$1670_Y attribute \src "libresoc.v:42086.20-42086.106" wire $not$libresoc.v:42086$1686_Y attribute \src "libresoc.v:42092.20-42092.106" wire $not$libresoc.v:42092$1692_Y attribute \src "libresoc.v:42098.20-42098.106" wire $not$libresoc.v:42098$1698_Y attribute \src "libresoc.v:42104.20-42104.106" wire $not$libresoc.v:42104$1704_Y attribute \src "libresoc.v:42120.20-42120.106" wire $not$libresoc.v:42120$1720_Y attribute \src "libresoc.v:42126.20-42126.106" wire $not$libresoc.v:42126$1726_Y attribute \src "libresoc.v:42132.20-42132.106" wire $not$libresoc.v:42132$1732_Y attribute \src "libresoc.v:42138.20-42138.106" wire $not$libresoc.v:42138$1738_Y attribute \src "libresoc.v:42157.20-42157.106" wire $not$libresoc.v:42157$1759_Y attribute \src "libresoc.v:42163.20-42163.106" wire $not$libresoc.v:42163$1765_Y attribute \src "libresoc.v:42169.20-42169.106" wire $not$libresoc.v:42169$1771_Y attribute \src "libresoc.v:42175.20-42175.106" wire $not$libresoc.v:42175$1777_Y attribute \src "libresoc.v:42181.20-42181.106" wire $not$libresoc.v:42181$1783_Y attribute \src "libresoc.v:42201.20-42201.106" wire $not$libresoc.v:42201$1803_Y attribute \src "libresoc.v:42207.20-42207.106" wire $not$libresoc.v:42207$1809_Y attribute \src "libresoc.v:42217.20-42217.106" wire $not$libresoc.v:42217$1820_Y attribute \src "libresoc.v:42225.20-42225.106" wire $not$libresoc.v:42225$1829_Y attribute \src "libresoc.v:42262.19-42262.136" wire width 4 $not$libresoc.v:42262$1866_Y attribute \src "libresoc.v:42263.19-42263.192" wire width 6 $not$libresoc.v:42263$1867_Y attribute \src "libresoc.v:42264.19-42264.138" wire width 3 $not$libresoc.v:42264$1868_Y attribute \src "libresoc.v:42265.19-42265.150" wire width 4 $not$libresoc.v:42265$1869_Y attribute \src "libresoc.v:42272.19-42272.128" wire width 3 $not$libresoc.v:42272$1876_Y attribute \src "libresoc.v:42287.19-42287.159" wire width 6 $not$libresoc.v:42287$1891_Y attribute \src "libresoc.v:42294.19-42294.128" wire width 3 $not$libresoc.v:42294$1898_Y attribute \src "libresoc.v:42301.19-42301.128" wire width 3 $not$libresoc.v:42301$1905_Y attribute \src "libresoc.v:42312.19-42312.150" wire width 5 $not$libresoc.v:42312$1916_Y attribute \src "libresoc.v:42313.19-42313.134" wire width 3 $not$libresoc.v:42313$1917_Y attribute \src "libresoc.v:42316.19-42316.108" wire $not$libresoc.v:42316$1920_Y attribute \src "libresoc.v:42322.19-42322.107" wire $not$libresoc.v:42322$1926_Y attribute \src "libresoc.v:42328.19-42328.109" wire $not$libresoc.v:42328$1932_Y attribute \src "libresoc.v:42334.19-42334.112" wire $not$libresoc.v:42334$1938_Y attribute \src "libresoc.v:42340.19-42340.108" wire $not$libresoc.v:42340$1944_Y attribute \src "libresoc.v:42346.19-42346.108" wire $not$libresoc.v:42346$1950_Y attribute \src "libresoc.v:42352.19-42352.113" wire $not$libresoc.v:42352$1956_Y attribute \src "libresoc.v:42358.19-42358.109" wire $not$libresoc.v:42358$1962_Y attribute \src "libresoc.v:42364.19-42364.113" wire $not$libresoc.v:42364$1968_Y attribute \src "libresoc.v:42370.19-42370.109" wire $not$libresoc.v:42370$1974_Y attribute \src "libresoc.v:42376.19-42376.109" wire $not$libresoc.v:42376$1980_Y attribute \src "libresoc.v:42382.19-42382.108" wire $not$libresoc.v:42382$1986_Y attribute \src "libresoc.v:42388.19-42388.110" wire $not$libresoc.v:42388$1992_Y attribute \src "libresoc.v:42394.19-42394.113" wire $not$libresoc.v:42394$1998_Y attribute \src "libresoc.v:42400.19-42400.109" wire $not$libresoc.v:42400$2004_Y attribute \src "libresoc.v:42406.19-42406.109" wire $not$libresoc.v:42406$2010_Y attribute \src "libresoc.v:42412.19-42412.109" wire $not$libresoc.v:42412$2016_Y attribute \src "libresoc.v:42418.19-42418.114" wire $not$libresoc.v:42418$2022_Y attribute \src "libresoc.v:42424.19-42424.110" wire $not$libresoc.v:42424$2028_Y attribute \src "libresoc.v:42455.19-42455.110" wire $not$libresoc.v:42455$2059_Y attribute \src "libresoc.v:42461.19-42461.114" wire $not$libresoc.v:42461$2065_Y attribute \src "libresoc.v:42467.19-42467.110" wire $not$libresoc.v:42467$2071_Y attribute \src "libresoc.v:42473.19-42473.110" wire $not$libresoc.v:42473$2077_Y attribute \src "libresoc.v:42479.19-42479.110" wire $not$libresoc.v:42479$2083_Y attribute \src "libresoc.v:42485.19-42485.115" wire $not$libresoc.v:42485$2089_Y attribute \src "libresoc.v:42501.19-42501.110" wire $not$libresoc.v:42501$2106_Y attribute \src "libresoc.v:42507.19-42507.110" wire $not$libresoc.v:42507$2112_Y attribute \src "libresoc.v:42513.19-42513.115" wire $not$libresoc.v:42513$2118_Y attribute \src "libresoc.v:42526.19-42526.110" wire $not$libresoc.v:42526$2132_Y attribute \src "libresoc.v:42532.19-42532.109" wire $not$libresoc.v:42532$2138_Y attribute \src "libresoc.v:42538.19-42538.106" wire $not$libresoc.v:42538$2144_Y attribute \src "libresoc.v:42546.19-42546.110" wire $not$libresoc.v:42546$2152_Y attribute \src "libresoc.v:42555.19-42555.106" wire $not$libresoc.v:42555$2161_Y attribute \src "libresoc.v:42563.19-42563.106" wire $not$libresoc.v:42563$2169_Y attribute \src "libresoc.v:42571.19-42571.113" wire $not$libresoc.v:42571$2177_Y attribute \src "libresoc.v:42577.19-42577.111" wire $not$libresoc.v:42577$2183_Y attribute \src "libresoc.v:42583.19-42583.110" wire $not$libresoc.v:42583$2189_Y attribute \src "libresoc.v:42589.19-42589.113" wire $not$libresoc.v:42589$2195_Y attribute \src "libresoc.v:42595.19-42595.111" wire $not$libresoc.v:42595$2201_Y attribute \src "libresoc.v:42606.19-42606.108" wire $not$libresoc.v:42606$2212_Y attribute \src "libresoc.v:42623.19-42623.99" wire $not$libresoc.v:42623$2229_Y attribute \src "libresoc.v:42629.19-42629.104" wire $not$libresoc.v:42629$2235_Y attribute \src "libresoc.v:41956.20-41956.117" wire width 64 $or$libresoc.v:41956$1555_Y attribute \src "libresoc.v:41957.20-41957.123" wire width 64 $or$libresoc.v:41957$1556_Y attribute \src "libresoc.v:41958.20-41958.113" wire width 64 $or$libresoc.v:41958$1557_Y attribute \src "libresoc.v:41959.20-41959.103" wire width 64 $or$libresoc.v:41959$1558_Y attribute \src "libresoc.v:41960.20-41960.123" wire width 64 $or$libresoc.v:41960$1559_Y attribute \src "libresoc.v:41961.20-41961.122" wire width 65 $or$libresoc.v:41961$1560_Y attribute \src "libresoc.v:41962.20-41962.113" wire width 65 $or$libresoc.v:41962$1561_Y attribute \src "libresoc.v:41963.20-41963.103" wire width 65 $or$libresoc.v:41963$1562_Y attribute \src "libresoc.v:41964.20-41964.103" wire width 65 $or$libresoc.v:41964$1563_Y attribute \src "libresoc.v:41965.20-41965.110" wire width 7 $or$libresoc.v:41965$1564_Y attribute \src "libresoc.v:41966.20-41966.117" wire width 7 $or$libresoc.v:41966$1565_Y attribute \src "libresoc.v:41967.20-41967.110" wire width 7 $or$libresoc.v:41967$1566_Y attribute \src "libresoc.v:41968.20-41968.103" wire width 7 $or$libresoc.v:41968$1567_Y attribute \src "libresoc.v:41969.20-41969.117" wire width 7 $or$libresoc.v:41969$1568_Y attribute \src "libresoc.v:41970.20-41970.117" wire width 7 $or$libresoc.v:41970$1569_Y attribute \src "libresoc.v:41971.20-41971.110" wire width 7 $or$libresoc.v:41971$1570_Y attribute \src "libresoc.v:41972.20-41972.103" wire width 7 $or$libresoc.v:41972$1571_Y attribute \src "libresoc.v:41973.20-41973.103" wire width 7 $or$libresoc.v:41973$1572_Y attribute \src "libresoc.v:41974.20-41974.99" wire $or$libresoc.v:41974$1573_Y attribute \src "libresoc.v:41975.20-41975.107" wire $or$libresoc.v:41975$1574_Y attribute \src "libresoc.v:41976.20-41976.105" wire $or$libresoc.v:41976$1575_Y attribute \src "libresoc.v:41977.20-41977.103" wire $or$libresoc.v:41977$1576_Y attribute \src "libresoc.v:41978.20-41978.107" wire $or$libresoc.v:41978$1577_Y attribute \src "libresoc.v:41979.20-41979.107" wire $or$libresoc.v:41979$1578_Y attribute \src "libresoc.v:41980.20-41980.105" wire $or$libresoc.v:41980$1579_Y attribute \src "libresoc.v:41981.20-41981.103" wire $or$libresoc.v:41981$1580_Y attribute \src "libresoc.v:41982.20-41982.103" wire $or$libresoc.v:41982$1581_Y attribute \src "libresoc.v:42044.20-42044.117" wire width 4 $or$libresoc.v:42044$1643_Y attribute \src "libresoc.v:42045.20-42045.113" wire width 4 $or$libresoc.v:42045$1644_Y attribute \src "libresoc.v:42046.20-42046.123" wire width 4 $or$libresoc.v:42046$1645_Y attribute \src "libresoc.v:42047.20-42047.113" wire width 4 $or$libresoc.v:42047$1646_Y attribute \src "libresoc.v:42048.20-42048.103" wire width 4 $or$libresoc.v:42048$1647_Y attribute \src "libresoc.v:42049.20-42049.117" wire width 256 $or$libresoc.v:42049$1648_Y attribute \src "libresoc.v:42050.20-42050.110" wire width 256 $or$libresoc.v:42050$1649_Y attribute \src "libresoc.v:42051.20-42051.117" wire width 256 $or$libresoc.v:42051$1650_Y attribute \src "libresoc.v:42052.20-42052.110" wire width 256 $or$libresoc.v:42052$1651_Y attribute \src "libresoc.v:42053.20-42053.103" wire width 256 $or$libresoc.v:42053$1652_Y attribute \src "libresoc.v:42075.20-42075.117" wire width 2 $or$libresoc.v:42075$1674_Y attribute \src "libresoc.v:42076.20-42076.113" wire width 2 $or$libresoc.v:42076$1675_Y attribute \src "libresoc.v:42077.20-42077.117" wire width 2 $or$libresoc.v:42077$1676_Y attribute \src "libresoc.v:42078.20-42078.110" wire width 2 $or$libresoc.v:42078$1677_Y attribute \src "libresoc.v:42108.20-42108.112" wire width 2 $or$libresoc.v:42108$1708_Y attribute \src "libresoc.v:42109.20-42109.123" wire width 2 $or$libresoc.v:42109$1709_Y attribute \src "libresoc.v:42110.20-42110.103" wire width 2 $or$libresoc.v:42110$1710_Y attribute \src "libresoc.v:42111.20-42111.117" wire width 3 $or$libresoc.v:42111$1711_Y attribute \src "libresoc.v:42112.20-42112.117" wire width 3 $or$libresoc.v:42112$1712_Y attribute \src "libresoc.v:42113.20-42113.103" wire width 3 $or$libresoc.v:42113$1713_Y attribute \src "libresoc.v:42142.20-42142.123" wire $or$libresoc.v:42142$1742_Y attribute \src "libresoc.v:42143.20-42143.123" wire $or$libresoc.v:42143$1743_Y attribute \src "libresoc.v:42144.20-42144.103" wire $or$libresoc.v:42144$1744_Y attribute \src "libresoc.v:42146.20-42146.117" wire $or$libresoc.v:42146$1747_Y attribute \src "libresoc.v:42147.20-42147.117" wire $or$libresoc.v:42147$1748_Y attribute \src "libresoc.v:42148.20-42148.103" wire $or$libresoc.v:42148$1749_Y attribute \src "libresoc.v:42185.20-42185.123" wire width 64 $or$libresoc.v:42185$1787_Y attribute \src "libresoc.v:42186.20-42186.123" wire width 64 $or$libresoc.v:42186$1788_Y attribute \src "libresoc.v:42187.20-42187.113" wire width 64 $or$libresoc.v:42187$1789_Y attribute \src "libresoc.v:42188.20-42188.103" wire width 64 $or$libresoc.v:42188$1790_Y attribute \src "libresoc.v:42189.20-42189.117" wire width 3 $or$libresoc.v:42189$1791_Y attribute \src "libresoc.v:42190.20-42190.117" wire width 3 $or$libresoc.v:42190$1792_Y attribute \src "libresoc.v:42191.20-42191.110" wire width 3 $or$libresoc.v:42191$1793_Y attribute \src "libresoc.v:42192.20-42192.103" wire width 3 $or$libresoc.v:42192$1794_Y attribute \src "libresoc.v:42193.20-42193.107" wire $or$libresoc.v:42193$1795_Y attribute \src "libresoc.v:42194.20-42194.107" wire $or$libresoc.v:42194$1796_Y attribute \src "libresoc.v:42195.20-42195.105" wire $or$libresoc.v:42195$1797_Y attribute \src "libresoc.v:42196.20-42196.103" wire $or$libresoc.v:42196$1798_Y attribute \src "libresoc.v:42211.20-42211.123" wire width 64 $or$libresoc.v:42211$1813_Y attribute \src "libresoc.v:42212.20-42212.117" wire $or$libresoc.v:42212$1814_Y attribute \src "libresoc.v:42255.19-42255.115" wire $or$libresoc.v:42255$1859_Y attribute \src "libresoc.v:42257.19-42257.115" wire $or$libresoc.v:42257$1861_Y attribute \src "libresoc.v:42261.19-42261.115" wire $or$libresoc.v:42261$1865_Y attribute \src "libresoc.v:42269.19-42269.115" wire $or$libresoc.v:42269$1873_Y attribute \src "libresoc.v:42271.19-42271.115" wire $or$libresoc.v:42271$1875_Y attribute \src "libresoc.v:42276.19-42276.115" wire $or$libresoc.v:42276$1880_Y attribute \src "libresoc.v:42278.19-42278.115" wire $or$libresoc.v:42278$1882_Y attribute \src "libresoc.v:42282.19-42282.115" wire $or$libresoc.v:42282$1886_Y attribute \src "libresoc.v:42286.19-42286.115" wire $or$libresoc.v:42286$1890_Y attribute \src "libresoc.v:42291.19-42291.115" wire $or$libresoc.v:42291$1895_Y attribute \src "libresoc.v:42293.19-42293.115" wire $or$libresoc.v:42293$1897_Y attribute \src "libresoc.v:42298.19-42298.115" wire $or$libresoc.v:42298$1902_Y attribute \src "libresoc.v:42300.19-42300.115" wire $or$libresoc.v:42300$1904_Y attribute \src "libresoc.v:42305.19-42305.115" wire $or$libresoc.v:42305$1909_Y attribute \src "libresoc.v:42307.19-42307.115" wire $or$libresoc.v:42307$1911_Y attribute \src "libresoc.v:42311.19-42311.115" wire $or$libresoc.v:42311$1915_Y attribute \src "libresoc.v:42428.19-42428.134" wire width 7 $or$libresoc.v:42428$2032_Y attribute \src "libresoc.v:42429.19-42429.140" wire width 7 $or$libresoc.v:42429$2033_Y attribute \src "libresoc.v:42430.19-42430.100" wire width 7 $or$libresoc.v:42430$2034_Y attribute \src "libresoc.v:42431.19-42431.135" wire width 7 $or$libresoc.v:42431$2035_Y attribute \src "libresoc.v:42432.19-42432.141" wire width 7 $or$libresoc.v:42432$2036_Y attribute \src "libresoc.v:42433.19-42433.122" wire width 7 $or$libresoc.v:42433$2037_Y attribute \src "libresoc.v:42434.19-42434.100" wire width 7 $or$libresoc.v:42434$2038_Y attribute \src "libresoc.v:42435.19-42435.100" wire width 7 $or$libresoc.v:42435$2039_Y attribute \src "libresoc.v:42436.19-42436.137" wire width 7 $or$libresoc.v:42436$2040_Y attribute \src "libresoc.v:42437.19-42437.142" wire width 7 $or$libresoc.v:42437$2041_Y attribute \src "libresoc.v:42438.19-42438.117" wire width 7 $or$libresoc.v:42438$2042_Y attribute \src "libresoc.v:42439.19-42439.100" wire width 7 $or$libresoc.v:42439$2043_Y attribute \src "libresoc.v:42440.19-42440.137" wire width 7 $or$libresoc.v:42440$2044_Y attribute \src "libresoc.v:42441.19-42441.143" wire width 7 $or$libresoc.v:42441$2045_Y attribute \src "libresoc.v:42442.19-42442.118" wire width 7 $or$libresoc.v:42442$2046_Y attribute \src "libresoc.v:42443.19-42443.100" wire width 7 $or$libresoc.v:42443$2047_Y attribute \src "libresoc.v:42444.19-42444.100" wire width 7 $or$libresoc.v:42444$2048_Y attribute \src "libresoc.v:42445.19-42445.100" wire width 7 $or$libresoc.v:42445$2049_Y attribute \src "libresoc.v:42450.19-42450.115" wire $or$libresoc.v:42450$2054_Y attribute \src "libresoc.v:42452.19-42452.115" wire $or$libresoc.v:42452$2056_Y attribute \src "libresoc.v:42489.19-42489.143" wire $or$libresoc.v:42489$2093_Y attribute \src "libresoc.v:42490.19-42490.119" wire $or$libresoc.v:42490$2094_Y attribute \src "libresoc.v:42491.19-42491.144" wire $or$libresoc.v:42491$2095_Y attribute \src "libresoc.v:42492.19-42492.119" wire $or$libresoc.v:42492$2096_Y attribute \src "libresoc.v:42493.19-42493.100" wire $or$libresoc.v:42493$2097_Y attribute \src "libresoc.v:42498.19-42498.115" wire $or$libresoc.v:42498$2103_Y attribute \src "libresoc.v:42517.19-42517.144" wire width 2 $or$libresoc.v:42517$2122_Y attribute \src "libresoc.v:42518.19-42518.119" wire width 2 $or$libresoc.v:42518$2123_Y attribute \src "libresoc.v:42523.19-42523.115" wire $or$libresoc.v:42523$2129_Y attribute \src "libresoc.v:42552.19-42552.135" wire width 256 $or$libresoc.v:42552$2158_Y attribute \src "libresoc.v:42599.19-42599.143" wire width 3 $or$libresoc.v:42599$2205_Y attribute \src "libresoc.v:42600.19-42600.143" wire width 3 $or$libresoc.v:42600$2206_Y attribute \src "libresoc.v:42601.19-42601.119" wire width 3 $or$libresoc.v:42601$2207_Y attribute \src "libresoc.v:42602.19-42602.100" wire width 3 $or$libresoc.v:42602$2208_Y attribute \src "libresoc.v:42079.20-42079.95" wire width 3 $pos$libresoc.v:42079$1679_Y attribute \src "libresoc.v:42145.20-42145.95" wire width 2 $pos$libresoc.v:42145$1746_Y attribute \src "libresoc.v:42149.20-42149.95" wire width 3 $pos$libresoc.v:42149$1751_Y attribute \src "libresoc.v:42213.20-42213.95" wire width 3 $pos$libresoc.v:42213$1816_Y attribute \src "libresoc.v:42221.20-42221.104" wire width 3 $pos$libresoc.v:42221$1825_Y attribute \src "libresoc.v:42494.19-42494.93" wire width 3 $pos$libresoc.v:42494$2099_Y attribute \src "libresoc.v:42519.19-42519.93" wire width 3 $pos$libresoc.v:42519$2125_Y attribute \src "libresoc.v:42230.19-42230.95" wire $reduce_or$libresoc.v:42230$1834_Y attribute \src "libresoc.v:42232.19-42232.95" wire $reduce_or$libresoc.v:42232$1836_Y attribute \src "libresoc.v:42234.19-42234.95" wire $reduce_or$libresoc.v:42234$1838_Y attribute \src "libresoc.v:42236.19-42236.95" wire $reduce_or$libresoc.v:42236$1840_Y attribute \src "libresoc.v:42238.19-42238.95" wire $reduce_or$libresoc.v:42238$1842_Y attribute \src "libresoc.v:42240.19-42240.95" wire $reduce_or$libresoc.v:42240$1844_Y attribute \src "libresoc.v:42242.19-42242.95" wire $reduce_or$libresoc.v:42242$1846_Y attribute \src "libresoc.v:42244.19-42244.95" wire $reduce_or$libresoc.v:42244$1848_Y attribute \src "libresoc.v:42246.19-42246.95" wire $reduce_or$libresoc.v:42246$1850_Y attribute \src "libresoc.v:42248.19-42248.95" wire $reduce_or$libresoc.v:42248$1852_Y attribute \src "libresoc.v:42446.19-42446.507" wire $reduce_or$libresoc.v:42446$2050_Y attribute \src "libresoc.v:42603.19-42603.210" wire $reduce_or$libresoc.v:42603$2209_Y attribute \src "libresoc.v:42610.19-42610.108" wire $reduce_or$libresoc.v:42610$2216_Y attribute \src "libresoc.v:42002.20-42002.118" wire width 256 $sshl$libresoc.v:42002$1601_Y attribute \src "libresoc.v:42010.20-42010.118" wire width 256 $sshl$libresoc.v:42010$1609_Y attribute \src "libresoc.v:42018.20-42018.118" wire width 256 $sshl$libresoc.v:42018$1617_Y attribute \src "libresoc.v:42026.20-42026.118" wire width 256 $sshl$libresoc.v:42026$1625_Y attribute \src "libresoc.v:42034.20-42034.118" wire width 256 $sshl$libresoc.v:42034$1633_Y attribute \src "libresoc.v:42042.20-42042.118" wire width 256 $sshl$libresoc.v:42042$1641_Y attribute \src "libresoc.v:42542.19-42542.115" wire width 256 $sshl$libresoc.v:42542$2148_Y attribute \src "libresoc.v:42550.19-42550.115" wire width 256 $sshl$libresoc.v:42550$2156_Y attribute \src "libresoc.v:42559.19-42559.115" wire width 256 $sshl$libresoc.v:42559$2165_Y attribute \src "libresoc.v:42567.19-42567.115" wire width 256 $sshl$libresoc.v:42567$2173_Y attribute \src "libresoc.v:42001.20-42001.121" wire width 8 $sub$libresoc.v:42001$1600_Y attribute \src "libresoc.v:42009.20-42009.121" wire width 8 $sub$libresoc.v:42009$1608_Y attribute \src "libresoc.v:42017.20-42017.121" wire width 8 $sub$libresoc.v:42017$1616_Y attribute \src "libresoc.v:42025.20-42025.121" wire width 8 $sub$libresoc.v:42025$1624_Y attribute \src "libresoc.v:42033.20-42033.121" wire width 8 $sub$libresoc.v:42033$1632_Y attribute \src "libresoc.v:42041.20-42041.121" wire width 8 $sub$libresoc.v:42041$1640_Y attribute \src "libresoc.v:42250.19-42250.102" wire width 3 $sub$libresoc.v:42250$1854_Y attribute \src "libresoc.v:42541.19-42541.119" wire width 8 $sub$libresoc.v:42541$2147_Y attribute \src "libresoc.v:42549.19-42549.119" wire width 8 $sub$libresoc.v:42549$2155_Y attribute \src "libresoc.v:42558.19-42558.119" wire width 8 $sub$libresoc.v:42558$2164_Y attribute \src "libresoc.v:42566.19-42566.122" wire width 8 $sub$libresoc.v:42566$2172_Y attribute \src "libresoc.v:41907.20-41907.117" wire width 7 $ternary$libresoc.v:41907$1506_Y attribute \src "libresoc.v:41913.20-41913.118" wire width 7 $ternary$libresoc.v:41913$1512_Y attribute \src "libresoc.v:41919.20-41919.118" wire width 7 $ternary$libresoc.v:41919$1518_Y attribute \src "libresoc.v:41925.20-41925.118" wire width 7 $ternary$libresoc.v:41925$1524_Y attribute \src "libresoc.v:41931.20-41931.118" wire width 7 $ternary$libresoc.v:41931$1530_Y attribute \src "libresoc.v:41937.20-41937.118" wire width 7 $ternary$libresoc.v:41937$1536_Y attribute \src "libresoc.v:41943.20-41943.118" wire width 7 $ternary$libresoc.v:41943$1542_Y attribute \src "libresoc.v:41949.20-41949.118" wire width 7 $ternary$libresoc.v:41949$1548_Y attribute \src "libresoc.v:41955.20-41955.116" wire width 7 $ternary$libresoc.v:41955$1554_Y attribute \src "libresoc.v:41989.20-41989.124" wire width 8 $ternary$libresoc.v:41989$1588_Y attribute \src "libresoc.v:42003.20-42003.180" wire width 256 $ternary$libresoc.v:42003$1602_Y attribute \src "libresoc.v:42011.20-42011.180" wire width 256 $ternary$libresoc.v:42011$1610_Y attribute \src "libresoc.v:42019.20-42019.180" wire width 256 $ternary$libresoc.v:42019$1618_Y attribute \src "libresoc.v:42027.20-42027.180" wire width 256 $ternary$libresoc.v:42027$1626_Y attribute \src "libresoc.v:42035.20-42035.180" wire width 256 $ternary$libresoc.v:42035$1634_Y attribute \src "libresoc.v:42043.20-42043.180" wire width 256 $ternary$libresoc.v:42043$1642_Y attribute \src "libresoc.v:42062.20-42062.112" wire width 2 $ternary$libresoc.v:42062$1661_Y attribute \src "libresoc.v:42068.20-42068.112" wire width 2 $ternary$libresoc.v:42068$1667_Y attribute \src "libresoc.v:42074.20-42074.112" wire width 2 $ternary$libresoc.v:42074$1673_Y attribute \src "libresoc.v:42089.20-42089.112" wire width 3 $ternary$libresoc.v:42089$1689_Y attribute \src "libresoc.v:42095.20-42095.112" wire width 3 $ternary$libresoc.v:42095$1695_Y attribute \src "libresoc.v:42101.20-42101.112" wire width 3 $ternary$libresoc.v:42101$1701_Y attribute \src "libresoc.v:42107.20-42107.112" wire width 3 $ternary$libresoc.v:42107$1707_Y attribute \src "libresoc.v:42123.20-42123.112" wire $ternary$libresoc.v:42123$1723_Y attribute \src "libresoc.v:42129.20-42129.112" wire $ternary$libresoc.v:42129$1729_Y attribute \src "libresoc.v:42135.20-42135.112" wire $ternary$libresoc.v:42135$1735_Y attribute \src "libresoc.v:42141.20-42141.112" wire $ternary$libresoc.v:42141$1741_Y attribute \src "libresoc.v:42160.20-42160.119" wire width 3 $ternary$libresoc.v:42160$1762_Y attribute \src "libresoc.v:42166.20-42166.119" wire width 3 $ternary$libresoc.v:42166$1768_Y attribute \src "libresoc.v:42172.20-42172.119" wire width 3 $ternary$libresoc.v:42172$1774_Y attribute \src "libresoc.v:42178.20-42178.119" wire width 3 $ternary$libresoc.v:42178$1780_Y attribute \src "libresoc.v:42184.20-42184.119" wire width 3 $ternary$libresoc.v:42184$1786_Y attribute \src "libresoc.v:42204.20-42204.112" wire $ternary$libresoc.v:42204$1806_Y attribute \src "libresoc.v:42210.20-42210.112" wire $ternary$libresoc.v:42210$1812_Y attribute \src "libresoc.v:42220.20-42220.112" wire width 2 $ternary$libresoc.v:42220$1823_Y attribute \src "libresoc.v:42228.20-42228.120" wire width 10 $ternary$libresoc.v:42228$1832_Y attribute \src "libresoc.v:42319.19-42319.126" wire width 7 $ternary$libresoc.v:42319$1923_Y attribute \src "libresoc.v:42325.19-42325.125" wire width 7 $ternary$libresoc.v:42325$1929_Y attribute \src "libresoc.v:42331.19-42331.127" wire width 7 $ternary$libresoc.v:42331$1935_Y attribute \src "libresoc.v:42337.19-42337.130" wire width 7 $ternary$libresoc.v:42337$1941_Y attribute \src "libresoc.v:42343.19-42343.126" wire width 7 $ternary$libresoc.v:42343$1947_Y attribute \src "libresoc.v:42349.19-42349.126" wire width 7 $ternary$libresoc.v:42349$1953_Y attribute \src "libresoc.v:42355.19-42355.131" wire width 7 $ternary$libresoc.v:42355$1959_Y attribute \src "libresoc.v:42361.19-42361.127" wire width 7 $ternary$libresoc.v:42361$1965_Y attribute \src "libresoc.v:42367.19-42367.131" wire width 7 $ternary$libresoc.v:42367$1971_Y attribute \src "libresoc.v:42373.19-42373.127" wire width 7 $ternary$libresoc.v:42373$1977_Y attribute \src "libresoc.v:42379.19-42379.127" wire width 7 $ternary$libresoc.v:42379$1983_Y attribute \src "libresoc.v:42385.19-42385.126" wire width 7 $ternary$libresoc.v:42385$1989_Y attribute \src "libresoc.v:42391.19-42391.128" wire width 7 $ternary$libresoc.v:42391$1995_Y attribute \src "libresoc.v:42397.19-42397.131" wire width 7 $ternary$libresoc.v:42397$2001_Y attribute \src "libresoc.v:42403.19-42403.127" wire width 7 $ternary$libresoc.v:42403$2007_Y attribute \src "libresoc.v:42409.19-42409.127" wire width 7 $ternary$libresoc.v:42409$2013_Y attribute \src "libresoc.v:42415.19-42415.127" wire width 7 $ternary$libresoc.v:42415$2019_Y attribute \src "libresoc.v:42421.19-42421.132" wire width 7 $ternary$libresoc.v:42421$2025_Y attribute \src "libresoc.v:42427.19-42427.128" wire width 7 $ternary$libresoc.v:42427$2031_Y attribute \src "libresoc.v:42458.19-42458.122" wire $ternary$libresoc.v:42458$2062_Y attribute \src "libresoc.v:42464.19-42464.126" wire $ternary$libresoc.v:42464$2068_Y attribute \src "libresoc.v:42470.19-42470.122" wire $ternary$libresoc.v:42470$2074_Y attribute \src "libresoc.v:42476.19-42476.122" wire $ternary$libresoc.v:42476$2080_Y attribute \src "libresoc.v:42482.19-42482.122" wire $ternary$libresoc.v:42482$2086_Y attribute \src "libresoc.v:42488.19-42488.127" wire $ternary$libresoc.v:42488$2092_Y attribute \src "libresoc.v:42504.19-42504.122" wire width 2 $ternary$libresoc.v:42504$2109_Y attribute \src "libresoc.v:42510.19-42510.122" wire width 2 $ternary$libresoc.v:42510$2115_Y attribute \src "libresoc.v:42516.19-42516.127" wire width 2 $ternary$libresoc.v:42516$2121_Y attribute \src "libresoc.v:42529.19-42529.122" wire width 3 $ternary$libresoc.v:42529$2135_Y attribute \src "libresoc.v:42535.19-42535.133" wire width 8 $ternary$libresoc.v:42535$2141_Y attribute \src "libresoc.v:42543.19-42543.185" wire width 256 $ternary$libresoc.v:42543$2149_Y attribute \src "libresoc.v:42551.19-42551.189" wire width 256 $ternary$libresoc.v:42551$2157_Y attribute \src "libresoc.v:42560.19-42560.185" wire width 256 $ternary$libresoc.v:42560$2166_Y attribute \src "libresoc.v:42568.19-42568.185" wire width 256 $ternary$libresoc.v:42568$2174_Y attribute \src "libresoc.v:42574.19-42574.131" wire width 3 $ternary$libresoc.v:42574$2180_Y attribute \src "libresoc.v:42580.19-42580.129" wire width 3 $ternary$libresoc.v:42580$2186_Y attribute \src "libresoc.v:42586.19-42586.128" wire width 3 $ternary$libresoc.v:42586$2192_Y attribute \src "libresoc.v:42592.19-42592.131" wire width 3 $ternary$libresoc.v:42592$2198_Y attribute \src "libresoc.v:42598.19-42598.129" wire width 3 $ternary$libresoc.v:42598$2204_Y attribute \src "libresoc.v:42609.19-42609.128" wire width 10 $ternary$libresoc.v:42609$2215_Y attribute \src "libresoc.v:42626.19-42626.110" wire width 7 $ternary$libresoc.v:42626$2232_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1003 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1006 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1010 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1012 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1019 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1022 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1024 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1027 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1031 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1033 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1037 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1040 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1042 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1045 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1049 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1051 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1059 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1062 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1064 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1067 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1071 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1073 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1079 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1082 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1084 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1087 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1091 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1093 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1099 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1144 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1147 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 7 \$1155 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 65 \$1157 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1158 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1160 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$1162 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$1164 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1166 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 65 \$1168 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 65 \$1170 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 65 \$1172 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 65 \$1174 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$1176 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$1177 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$1179 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$1181 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$1183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$1185 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$1187 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$1189 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$1191 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$1193 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1195 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1197 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1199 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1201 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1203 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1205 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1207 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1209 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1211 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1213 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1215 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1218 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1221 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1223 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1226 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 8 \$1229 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1231 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1233 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1237 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1239 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1241 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1243 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1246 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1249 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1251 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1254 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1259 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1261 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1263 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1266 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1269 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1271 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1274 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1277 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1279 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1281 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1283 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1286 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1289 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1291 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1294 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1297 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1299 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1301 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1303 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1306 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1309 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1311 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1314 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1317 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1319 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1321 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1323 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1326 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1329 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1331 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1334 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1337 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1339 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1341 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1343 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1346 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1349 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1351 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1354 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 8 \$1357 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" wire width 256 \$1359 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 256 \$1361 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$1363 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$1365 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$1367 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$1369 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$1371 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 256 \$1373 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 256 \$1374 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 256 \$1376 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 256 \$1378 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 256 \$1380 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 256 \$1382 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1384 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1390 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1393 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1396 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1398 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1409 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1412 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1417 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1425 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1428 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1433 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1436 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$1438 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$1440 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1442 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$1443 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$1445 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1450 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1452 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1459 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1462 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1464 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1467 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1470 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1472 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1475 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1478 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1480 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1483 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1486 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1488 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1491 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1494 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1496 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1499 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1504 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1507 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1510 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1515 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1518 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$1520 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$1522 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$1524 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 3 \$1526 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 3 \$1528 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1532 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1534 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1536 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1538 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1540 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1543 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1546 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1548 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1551 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1554 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1556 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1559 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1562 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1564 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1567 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1570 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1572 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1575 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1578 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1580 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1583 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1586 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1588 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1591 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1594 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1596 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1599 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1602 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$1604 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1605 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1607 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1609 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1612 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1613 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1615 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1617 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1620 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1624 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1626 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1630 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1633 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1637 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1639 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1644 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1647 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1649 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1652 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1655 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1657 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1660 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1663 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1665 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1668 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1671 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1673 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1676 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1679 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1681 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1684 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1687 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1689 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1692 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1695 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1697 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1700 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1703 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1705 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1708 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 3 \$1711 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1713 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1715 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$1717 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$1719 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 3 \$1721 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 3 \$1723 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1725 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$1727 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1729 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1731 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1733 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$1735 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1737 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1739 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1741 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1744 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1747 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1749 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1752 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1755 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1757 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1760 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1763 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1765 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1768 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire \$1771 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$1773 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 3 \$1775 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$1776 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1779 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1781 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1784 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1787 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1789 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1792 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 2 \$1795 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" wire width 3 \$1797 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" wire \$1799 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" wire \$1801 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" wire \$1804 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1807 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$1809 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" wire \$1812 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" wire width 10 \$1815 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$189 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$194 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$201 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$202 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$205 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$206 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$209 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$210 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$213 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire \$217 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" wire width 14 \$218 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" wire \$221 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" wire width 3 \$223 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" wire width 3 \$224 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" wire \$226 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 4 \$228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$229 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire width 3 \$231 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$233 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$237 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$239 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" wire \$241 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire width 3 \$243 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$245 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$247 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 6 \$250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$252 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 4 \$254 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire width 3 \$259 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$261 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$263 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$267 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 6 \$270 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$271 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire width 3 \$273 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$275 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$277 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$279 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$281 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" wire \$283 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" wire width 3 \$285 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" wire \$287 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" wire \$289 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" wire \$291 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire width 3 \$293 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$295 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$297 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$300 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$301 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire width 3 \$303 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$305 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$307 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$309 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$311 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$314 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$315 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire width 3 \$317 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$319 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$321 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$323 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$325 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 5 \$328 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$329 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire width 3 \$331 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$333 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$335 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$337 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$339 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" wire \$341 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire width 3 \$343 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$347 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" wire width 3 \$350 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$352 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$354 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$356 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$358 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$360 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$362 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$364 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$368 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$370 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$372 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$374 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$376 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$378 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$380 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$382 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$384 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$390 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$392 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$394 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$396 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$398 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$410 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$418 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$432 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$434 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$436 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$438 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$442 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$446 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$450 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$452 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$458 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$460 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$462 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$464 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$468 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$470 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$472 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$476 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$478 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$480 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$484 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$486 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$488 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$492 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$494 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$496 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$498 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$500 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$504 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$506 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$508 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$514 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$516 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$518 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$520 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$522 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$524 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$526 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$528 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$532 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$534 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$536 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$538 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$540 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$542 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$544 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$546 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$548 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$552 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$554 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$556 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$558 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$560 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$562 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$564 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$568 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$570 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$572 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$574 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$576 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire width 7 \$578 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$580 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$581 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$583 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$585 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$587 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$589 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$591 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$593 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$595 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$597 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$599 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$601 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$603 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$605 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 7 \$607 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$609 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$611 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$613 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 7 \$615 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" wire \$617 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$619 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire width 3 \$621 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$623 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$625 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$627 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$629 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$631 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$633 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$635 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$637 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$639 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$641 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$643 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$645 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$647 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$649 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$651 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$653 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$655 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$657 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$659 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$661 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$663 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$665 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$667 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$669 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$671 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$673 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$675 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$677 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$679 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$681 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$683 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$685 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$687 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$689 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$691 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$693 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$695 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" wire \$697 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" wire \$699 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" wire \$701 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 3 \$703 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$704 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$706 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire \$708 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$710 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire \$712 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" wire \$715 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire width 3 \$717 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$719 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$721 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$723 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" wire \$725 attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_trap0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_FAST_fast1_trap0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_alu0_10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_cr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_cr0_11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_div0_15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_div0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_ldst0_18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_ldst0_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_ldst0_9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_logical0_13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_logical0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_mul0_16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_mul0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_shiftrot0_17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_shiftrot0_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_shiftrot0_8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_spr0_14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_trap0_12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 7 \addr_en_INT_rabc_trap0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 10 \addr_en_SPR_spr1_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 2 \addr_en_XER_xer_ca_spr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire width 3 \addr_en_XER_xer_ov_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_div0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_logical0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_mul0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_shiftrot0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" wire \addr_en_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire input 67 \bigendian_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 7 \cia__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 input 42 \core_core_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 input 61 \core_core_cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 62 \core_core_cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 input 63 \core_core_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 52 \core_core_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 53 \core_core_exc_$signal$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 54 \core_core_exc_$signal$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 55 \core_core_exc_$signal$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 56 \core_core_exc_$signal$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 57 \core_core_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 58 \core_core_exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 59 \core_core_exc_$signal$9 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 input 45 \core_core_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 input 50 \core_core_input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 input 43 \core_core_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 input 44 \core_core_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire input 64 \core_core_is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 input 41 \core_core_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 48 \core_core_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 49 \core_core_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 46 \core_core_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 47 \core_core_rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 input 60 \core_core_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 input 51 \core_core_traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 34 \core_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 35 \core_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 36 \core_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 38 \core_cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 37 \core_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 39 \core_cr_in2_ok$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 40 \core_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 17 \core_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 28 \core_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 29 \core_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 30 \core_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 31 \core_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 32 \core_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 input 33 \core_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 65 \core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 18 \core_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 19 \core_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 20 \core_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 21 \core_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 22 \core_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 23 \core_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 input 16 \core_rego attribute \enum_base_type "SPR" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 input 25 \core_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \core_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 input 24 \core_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire output 14 \core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire \core_terminate_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 input 27 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" wire output 2 \corebusy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 97 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" wire width 2 \counter attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" wire width 2 \counter$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 \cr_full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 \cr_full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_full_wr__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \cr_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 4 \cu_ad__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 5 \cu_ad__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 6 \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 3 \cu_st__rel_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 12 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 70 \data_i$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 89 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 45 output 94 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 88 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 input 93 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 output 96 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 90 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 8 output 92 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 91 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 95 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_ALU_ALU__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_ALU_ALU__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_ALU_ALU__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \dec_ALU_ALU__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_ALU_ALU__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_ALU_ALU__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_ALU_ALU__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_ALU_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_ALU_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_ALU_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_BRANCH_BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_BRANCH_BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_BRANCH_BRANCH__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_BRANCH_BRANCH__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_BRANCH_BRANCH__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_BRANCH_BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_BRANCH_BRANCH__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_BRANCH_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_BRANCH_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_CR_CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_CR_CR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_CR_CR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_CR_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_CR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_DIV_DIV__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_DIV_DIV__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_DIV_DIV__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \dec_DIV_DIV__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_DIV_DIV__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_DIV_DIV__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_DIV_DIV__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_DIV_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_DIV_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_DIV_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LDST_LDST__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_LDST_LDST__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_LDST_LDST__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_LDST_LDST__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_LDST_LDST__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \dec_LDST_LDST__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LDST_LDST__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_LDST_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LDST_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_LDST_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \dec_LOGICAL_LOGICAL__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_LOGICAL_LOGICAL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_LOGICAL_LOGICAL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \dec_LOGICAL_LOGICAL__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_LOGICAL_LOGICAL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_LOGICAL_LOGICAL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_LOGICAL_LOGICAL__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_LOGICAL_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_LOGICAL_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec_LOGICAL_sv_a_nz attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_MUL_MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_MUL_MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_MUL_MUL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_MUL_MUL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_MUL_MUL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_MUL_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_MUL_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \dec_SHIFT_ROT_SHIFT_ROT__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_SHIFT_ROT_SHIFT_ROT__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_SHIFT_ROT_SHIFT_ROT__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_SHIFT_ROT_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_SHIFT_ROT_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dec_SPR_SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dec_SPR_SPR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dec_SPR_SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dec_SPR_SPR__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec_SPR_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec_SPR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 74 \dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 76 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 75 \dmi__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_branch0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_branch0_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_a_cr0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_b_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_b_cr0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_c_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_cr_c_cr0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_full_cr_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_CR_full_cr_cr0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_branch0_3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_spr0_2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_FAST_fast1_trap0_4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_alu0_10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_cr0_11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_div0_4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_ldst0_9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_logical0_3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_mul0_5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_shiftrot0_8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_spr0_14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_spr0_14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_INT_rabc_trap0_2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_SPR_spr1_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_SPR_spr1_spr0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_alu0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_shiftrot0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_shiftrot0_2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_spr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ca_spr0_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ov_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_ov_spr0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_alu0_0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_div0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_div0_3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_logical0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_logical0_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_mul0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_mul0_4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_shiftrot0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_shiftrot0_5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" wire \dp_XER_xer_so_spr0_2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_ldst0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" wire \en_trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \fast_dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_dest1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \fast_src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \fast_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \fast_src1__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire width 10 \fu_enable attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 78 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 77 \full_rd2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 6 output 80 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 79 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_cr_a_ok$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 \fus_cu_rd__go_i$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__go_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_rd__go_i$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 \fus_cu_rd__go_i$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__go_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 \fus_cu_rd__rel_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__rel_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_rd__rel_o$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 \fus_cu_rd__rel_o$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_rd__rel_o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 \fus_cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 6 \fus_cu_rdmaskn_i$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 \fus_cu_rdmaskn_i$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 \fus_cu_rdmaskn_i$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 \fus_cu_rdmaskn_i$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 6 \fus_cu_rdmaskn_i$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 \fus_cu_rdmaskn_i$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 \fus_cu_rdmaskn_i$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 5 \fus_cu_rdmaskn_i$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 \fus_cu_rdmaskn_i$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 \fus_cu_wr__go_i$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 \fus_cu_wr__go_i$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_wr__go_i$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_wr__go_i$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_wr__go_i$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 \fus_cu_wr__go_i$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_wr__go_i$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_wr__go_i$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__go_i$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 \fus_cu_wr__rel_o$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_wr__rel_o$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_wr__rel_o$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_wr__rel_o$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 \fus_cu_wr__rel_o$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_wr__rel_o$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 \fus_cu_wr__rel_o$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__rel_o$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 \fus_cu_wr__rel_o$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 32 \fus_dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest2_o$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest2_o$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest2_o$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest2_o$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest2_o$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest2_o$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest2_o$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest2_o$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest3_o$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest3_o$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest3_o$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest3_o$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest3_o$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest3_o$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest3_o$159 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire \fus_dest4_o$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire \fus_dest4_o$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire \fus_dest4_o$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest4_o$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire \fus_dest5_o$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest5_o$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast1_ok$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast1_ok$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_fast2_ok$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 \fus_ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire \fus_ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire \fus_ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 \fus_ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \fus_ldst_port0_exc_$signal$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire \fus_ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire \fus_ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_nia_ok$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fus_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_o_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_alu0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \fus_oper_i_alu_alu0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_alu0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_alu0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_branch0__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_branch0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_branch0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_branch0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_branch0__lk attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_div0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \fus_oper_i_alu_div0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_div0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_logical0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \fus_oper_i_alu_logical0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_logical0__zero_a attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_mul0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_mul0__write_cr0 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \fus_oper_i_alu_shift_rot0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_shift_rot0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_spr0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_trap0__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \fus_oper_i_alu_trap0__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_trap0__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \fus_oper_i_alu_trap0__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \fus_oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \fus_oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \fus_oper_i_ldst_ldst0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src3_i$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src3_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src3_i$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src3_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src3_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 32 \fus_src3_i$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 \fus_src3_i$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src3_i$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src3_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src4_i$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src4_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 \fus_src4_i$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src4_i$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src5_i$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 \fus_src5_i$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 \fus_src6_i$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ca_ok$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ca_ok$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_ov_ok$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fus_xer_so_ok$143 attribute \src "libresoc.v:36262.7-36262.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \int_dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_dest1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \int_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \int_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 81 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 84 \issue__addr$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 86 \issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 83 \issue__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 82 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 85 \issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" wire input 72 \issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" wire input 71 \ivalid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 15 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 13 \msr__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_a_branch0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_a_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_b_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_cr_c_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_CR_full_cr_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_branch0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_branch0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_trap0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_FAST_fast1_trap0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_alu0_10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_cr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_cr0_11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_div0_15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_div0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_ldst0_18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_ldst0_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_ldst0_9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_logical0_13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_logical0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_mul0_16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_mul0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_shiftrot0_17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_shiftrot0_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_shiftrot0_8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_spr0_14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_trap0_12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_INT_rabc_trap0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_SPR_spr1_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_shiftrot0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ca_spr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_ov_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_div0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_logical0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_mul0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_shiftrot0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire \pick_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 input 66 \raw_insn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_a_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_b_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_cr_c_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_CR_full_cr_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_FAST_fast1_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_FAST_fast1_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_INT_rabc_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_INT_rabc_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_INT_rabc_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_SPR_spr1_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_ca_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_ov_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" wire \rdflag_XER_xer_so_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_a_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 \rdpick_CR_cr_a_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 \rdpick_CR_cr_a_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_b_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_CR_cr_b_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_CR_cr_b_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_cr_c_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_CR_cr_c_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_CR_cr_c_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_CR_full_cr_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_CR_full_cr_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_CR_full_cr_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_FAST_fast1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 5 \rdpick_FAST_fast1_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 5 \rdpick_FAST_fast1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_INT_rabc_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 19 \rdpick_INT_rabc_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 19 \rdpick_INT_rabc_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_SPR_spr1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_SPR_spr1_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_SPR_spr1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_XER_xer_ca_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 \rdpick_XER_xer_ca_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 \rdpick_XER_xer_ca_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_XER_xer_ov_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \rdpick_XER_xer_ov_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \rdpick_XER_xer_ov_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \rdpick_XER_xer_so_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 \rdpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 \rdpick_XER_xer_so_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_a_branch0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_a_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_b_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_cr_c_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_CR_full_cr_cr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_branch0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_branch0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_trap0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_FAST_fast1_trap0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_alu0_10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_cr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_cr0_11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_div0_15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_div0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_ldst0_18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_ldst0_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_ldst0_9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_logical0_13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_logical0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_mul0_16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_mul0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_shiftrot0_17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_shiftrot0_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_shiftrot0_8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_spr0_14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_trap0_12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_INT_rabc_trap0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_SPR_spr1_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_shiftrot0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ca_spr0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_ov_spr0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_alu0_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_div0_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_logical0_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_mul0_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_shiftrot0_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" wire \rp_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \spr_spr1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \spr_spr1__addr$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \spr_spr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \spr_spr1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \spr_spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \spr_spr1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \state_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \state_data_i$174 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 output 73 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \state_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 10 \sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \sv__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire input 68 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \sv_a_nz$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 87 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 11 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 69 \wen$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1018 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1036 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1058 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1078 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1098 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1225 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1253 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1273 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1293 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1313 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1333 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1353 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1432 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1498 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1514 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1582 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1598 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1643 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1659 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1675 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1691 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1707 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1751 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1767 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1791 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$1811 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" wire \wp$997 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1005 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1044 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1066 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1086 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1217 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1245 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1285 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1305 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1325 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1392 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1458 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1506 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1542 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1558 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1574 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1590 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1632 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1651 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1667 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1683 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1699 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1743 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1759 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1783 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$1803 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" wire \wr_pick$986 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1008 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1008$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1029 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1029$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1047 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1047$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1069 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1069$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1089 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1089$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1109$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1128$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1146 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1146$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1220 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1220$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1248 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1248$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1268 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1268$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1288 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1288$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1308 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1308$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1328 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1328$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1348 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1348$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1395 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1395$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1411 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1411$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1427 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1427$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1461 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1461$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1477 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1477$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1493 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1493$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1509 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1509$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1545 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1545$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1561 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1561$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1577 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1577$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1593 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1593$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1635 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1635$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1654 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1654$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1670 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1670$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1686 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1686$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1702 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1702$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1746 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1746$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1762 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1762$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1786 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1786$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1806 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$1806$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$989 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$989$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \wr_pick_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1009 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1014 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1015 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1016 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1017 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1030 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1035 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1048 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1053 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1054 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1055 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1056 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1057 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1070 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1075 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1076 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1077 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1090 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1095 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1096 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1097 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1110 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1134 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1636 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1641 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$1642 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$976 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$977 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$978 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$979 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$990 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$995 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \wr_pick_rise$996 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_cr_a_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_ca_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_ov_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_alu0_xer_so_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_fast1_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_fast1_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_branch0_nia_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_cr_a_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_full_cr_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_cr0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_cr_a_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_xer_ov_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_div0_xer_so_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_ldst0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_ldst0_o_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_logical0_cr_a_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_logical0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_cr_a_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_xer_ov_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_mul0_xer_so_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_cr_a_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_shiftrot0_xer_ca_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_fast1_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_o_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_spr1_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_ca_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_ov_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_spr0_xer_so_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_fast1_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_fast1_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_msr_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_nia_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wrflag_trap0_o_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_CR_cr_a_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 \wrpick_CR_cr_a_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 \wrpick_CR_cr_a_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_CR_full_cr_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \wrpick_CR_full_cr_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \wrpick_CR_full_cr_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_FAST_fast1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 5 \wrpick_FAST_fast1_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 5 \wrpick_FAST_fast1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_INT_o_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 10 \wrpick_INT_o_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 10 \wrpick_INT_o_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_SPR_spr1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \wrpick_SPR_spr1_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \wrpick_SPR_spr1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_STATE_msr_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire \wrpick_STATE_msr_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire \wrpick_STATE_msr_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_STATE_nia_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 \wrpick_STATE_nia_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 \wrpick_STATE_nia_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_XER_xer_ca_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 \wrpick_XER_xer_ca_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 \wrpick_XER_xer_ca_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_XER_xer_ov_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 \wrpick_XER_xer_ov_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 \wrpick_XER_xer_ov_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \wrpick_XER_xer_so_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 \wrpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 \wrpick_XER_xer_so_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_data_i$170 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_data_i$172 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \xer_src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$171 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41908$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok$95 connect \B \fus_cu_busy_o$20 connect \Y $and$libresoc.v:41908$1507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41909$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41909$1508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41911$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1005 connect \B \$1010 connect \Y $and$libresoc.v:41911$1510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41912$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1005 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41912$1511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41914$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok$98 connect \B \fus_cu_busy_o$23 connect \Y $and$libresoc.v:41914$1513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41915$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41915$1514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41917$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1026 connect \B \$1031 connect \Y $and$libresoc.v:41917$1516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41918$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1026 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41918$1517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41920$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok$101 connect \B \fus_cu_busy_o$26 connect \Y $and$libresoc.v:41920$1519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41921$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41921$1520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41923$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1044 connect \B \$1049 connect \Y $and$libresoc.v:41923$1522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41924$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1044 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41924$1523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41926$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok$104 connect \B \fus_cu_busy_o$29 connect \Y $and$libresoc.v:41926$1525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41927$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41927$1526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41929$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1066 connect \B \$1071 connect \Y $and$libresoc.v:41929$1528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41930$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1066 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41930$1529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41932$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok$107 connect \B \fus_cu_busy_o$32 connect \Y $and$libresoc.v:41932$1531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41933$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41933$1532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41935$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1086 connect \B \$1091 connect \Y $and$libresoc.v:41935$1534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41936$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1086 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41936$1535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41938$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok$110 connect \B \fus_cu_busy_o$35 connect \Y $and$libresoc.v:41938$1537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41939$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41939$1538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41941$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1106 connect \B \$1111 connect \Y $and$libresoc.v:41941$1540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41942$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1106 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41942$1541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41944$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \fus_cu_busy_o$38 connect \Y $and$libresoc.v:41944$1543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41945$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41945$1544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41947$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1125 connect \B \$1130 connect \Y $and$libresoc.v:41947$1546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41948$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1125 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41948$1547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41950$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ea_ok connect \B \fus_cu_busy_o$38 connect \Y $and$libresoc.v:41950$1549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41951$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41951$1550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41953$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1143 connect \B \$1147 connect \Y $and$libresoc.v:41953$1552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41954$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1143 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:41954$1553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41983$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok connect \B \fus_cu_busy_o$14 connect \Y $and$libresoc.v:41983$1582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:41984$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [1] connect \Y $and$libresoc.v:41984$1583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41985$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o connect \Y $and$libresoc.v:41985$1584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41987$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1217 connect \B \$1221 connect \Y $and$libresoc.v:41987$1586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:41988$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1217 connect \B \wrpick_CR_full_cr_en_o connect \Y $and$libresoc.v:41988$1587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:41990$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o connect \Y $and$libresoc.v:41990$1589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:41991$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] connect \Y $and$libresoc.v:41991$1590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:41992$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [1] connect \Y $and$libresoc.v:41992$1591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:41993$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [4] connect \Y $and$libresoc.v:41993$1592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:41994$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [1] connect \B \fu_enable [6] connect \Y $and$libresoc.v:41994$1593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:41995$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [1] connect \B \fu_enable [7] connect \Y $and$libresoc.v:41995$1594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:41996$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [8] connect \Y $and$libresoc.v:41996$1595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:41997$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:41997$1596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:41999$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1245 connect \B \$1249 connect \Y $and$libresoc.v:41999$1598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42000$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1245 connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42000$1599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42004$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$122 connect \B \fus_cu_busy_o$14 connect \Y $and$libresoc.v:42004$1603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42005$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42005$1604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42007$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1265 connect \B \$1269 connect \Y $and$libresoc.v:42007$1606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42008$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1265 connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42008$1607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42012$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$123 connect \B \fus_cu_busy_o$23 connect \Y $and$libresoc.v:42012$1611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42013$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42013$1612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42015$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1285 connect \B \$1289 connect \Y $and$libresoc.v:42015$1614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42016$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1285 connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42016$1615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42020$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$124 connect \B \fus_cu_busy_o$29 connect \Y $and$libresoc.v:42020$1619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42021$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42021$1620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42023$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1305 connect \B \$1309 connect \Y $and$libresoc.v:42023$1622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42024$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1305 connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42024$1623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42028$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$125 connect \B \fus_cu_busy_o$32 connect \Y $and$libresoc.v:42028$1627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42029$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42029$1628_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42031$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1325 connect \B \$1329 connect \Y $and$libresoc.v:42031$1630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42032$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1325 connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42032$1631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42036$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$126 connect \B \fus_cu_busy_o$35 connect \Y $and$libresoc.v:42036$1635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42037$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42037$1636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42039$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1345 connect \B \$1349 connect \Y $and$libresoc.v:42039$1638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42040$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1345 connect \B \wrpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42040$1639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42054$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o connect \Y $and$libresoc.v:42054$1653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42055$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42055$1654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42056$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [5] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42056$1655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42057$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [2] connect \B \fu_enable [8] connect \Y $and$libresoc.v:42057$1656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42058$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42058$1657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42060$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1392 connect \B \$1396 connect \Y $and$libresoc.v:42060$1659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42061$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1392 connect \B \wrpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42061$1660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42063$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$132 connect \B \fus_cu_busy_o$26 connect \Y $and$libresoc.v:42063$1662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42064$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42064$1663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42066$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1408 connect \B \$1412 connect \Y $and$libresoc.v:42066$1665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42067$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1408 connect \B \wrpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42067$1666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42069$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$133 connect \B \fus_cu_busy_o$35 connect \Y $and$libresoc.v:42069$1668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42070$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42070$1669_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42072$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1424 connect \B \$1428 connect \Y $and$libresoc.v:42072$1671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42073$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1424 connect \B \wrpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42073$1672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42080$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o connect \Y $and$libresoc.v:42080$1680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42081$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42081$1681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42082$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [4] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42082$1682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42083$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [2] connect \B \fu_enable [6] connect \Y $and$libresoc.v:42083$1683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42084$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [2] connect \B \fu_enable [7] connect \Y $and$libresoc.v:42084$1684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42085$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42085$1685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42087$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1458 connect \B \$1462 connect \Y $and$libresoc.v:42087$1687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42088$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1458 connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42088$1688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42090$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$136 connect \B \fus_cu_busy_o$26 connect \Y $and$libresoc.v:42090$1690_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42091$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42091$1691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42093$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1474 connect \B \$1478 connect \Y $and$libresoc.v:42093$1693_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42094$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1474 connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42094$1694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42096$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$137 connect \B \fus_cu_busy_o$29 connect \Y $and$libresoc.v:42096$1696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42097$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42097$1697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42099$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1490 connect \B \$1494 connect \Y $and$libresoc.v:42099$1699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42100$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1490 connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42100$1700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42102$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$138 connect \B \fus_cu_busy_o$32 connect \Y $and$libresoc.v:42102$1702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42103$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42103$1703_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42105$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1506 connect \B \$1510 connect \Y $and$libresoc.v:42105$1705_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42106$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1506 connect \B \wrpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42106$1706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42114$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o connect \Y $and$libresoc.v:42114$1714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42115$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42115$1715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42116$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [3] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42116$1716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42117$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [3] connect \B \fu_enable [6] connect \Y $and$libresoc.v:42117$1717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42118$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [3] connect \B \fu_enable [7] connect \Y $and$libresoc.v:42118$1718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42119$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42119$1719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42121$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1542 connect \B \$1546 connect \Y $and$libresoc.v:42121$1721_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42122$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1542 connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42122$1722_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42124$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$141 connect \B \fus_cu_busy_o$26 connect \Y $and$libresoc.v:42124$1724_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42125$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42125$1725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42127$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1558 connect \B \$1562 connect \Y $and$libresoc.v:42127$1727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42128$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1558 connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42128$1728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42130$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$142 connect \B \fus_cu_busy_o$29 connect \Y $and$libresoc.v:42130$1730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42131$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42131$1731_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42133$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1574 connect \B \$1578 connect \Y $and$libresoc.v:42133$1733_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42134$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1574 connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42134$1734_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42136$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$143 connect \B \fus_cu_busy_o$32 connect \Y $and$libresoc.v:42136$1736_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42137$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42137$1737_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42139$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1590 connect \B \$1594 connect \Y $and$libresoc.v:42139$1739_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42140$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1590 connect \B \wrpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42140$1740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42150$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast1_ok connect \B \fus_cu_busy_o$17 connect \Y $and$libresoc.v:42150$1752_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42151$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [0] connect \B \fu_enable [2] connect \Y $and$libresoc.v:42151$1753_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42152$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42152$1754_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42153$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42153$1755_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42154$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [1] connect \B \fu_enable [2] connect \Y $and$libresoc.v:42154$1756_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42155$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42155$1757_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42156$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42156$1758_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42158$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1632 connect \B \$1637 connect \Y $and$libresoc.v:42158$1760_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42159$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1632 connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42159$1761_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42161$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$150 connect \B \fus_cu_busy_o$20 connect \Y $and$libresoc.v:42161$1763_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42162$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42162$1764_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42164$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1651 connect \B \$1655 connect \Y $and$libresoc.v:42164$1766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42165$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1651 connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42165$1767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42167$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$151 connect \B \fus_cu_busy_o$26 connect \Y $and$libresoc.v:42167$1769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42168$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42168$1770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42170$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1667 connect \B \$1671 connect \Y $and$libresoc.v:42170$1772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42171$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1667 connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42171$1773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42173$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast2_ok connect \B \fus_cu_busy_o$17 connect \Y $and$libresoc.v:42173$1775_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42174$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42174$1776_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42176$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1683 connect \B \$1687 connect \Y $and$libresoc.v:42176$1778_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42177$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1683 connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42177$1779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42179$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast2_ok$152 connect \B \fus_cu_busy_o$20 connect \Y $and$libresoc.v:42179$1781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42180$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42180$1782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42182$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1699 connect \B \$1703 connect \Y $and$libresoc.v:42182$1784_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42183$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1699 connect \B \wrpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42183$1785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42197$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_nia_ok connect \B \fus_cu_busy_o$17 connect \Y $and$libresoc.v:42197$1799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42198$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [2] connect \B \fu_enable [2] connect \Y $and$libresoc.v:42198$1800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42199$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42199$1801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42200$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o connect \Y $and$libresoc.v:42200$1802_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42202$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1743 connect \B \$1747 connect \Y $and$libresoc.v:42202$1804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42203$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1743 connect \B \wrpick_STATE_nia_en_o connect \Y $and$libresoc.v:42203$1805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42205$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_nia_ok$158 connect \B \fus_cu_busy_o$20 connect \Y $and$libresoc.v:42205$1807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42206$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o connect \Y $and$libresoc.v:42206$1808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42208$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1759 connect \B \$1763 connect \Y $and$libresoc.v:42208$1810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42209$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1759 connect \B \wrpick_STATE_nia_en_o connect \Y $and$libresoc.v:42209$1811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42214$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_msr_ok connect \B \fus_cu_busy_o$20 connect \Y $and$libresoc.v:42214$1817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42215$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [4] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42215$1818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42216$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o connect \Y $and$libresoc.v:42216$1819_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42218$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1783 connect \B \$1787 connect \Y $and$libresoc.v:42218$1821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42219$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1783 connect \B \wrpick_STATE_msr_en_o connect \Y $and$libresoc.v:42219$1822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42222$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_spr1_ok connect \B \fus_cu_busy_o$26 connect \Y $and$libresoc.v:42222$1826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42223$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42223$1827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42224$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o connect \Y $and$libresoc.v:42224$1828_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42226$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1803 connect \B \$1807 connect \Y $and$libresoc.v:42226$1830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42227$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$1803 connect \B \wrpick_SPR_spr1_en_o connect \Y $and$libresoc.v:42227$1831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42229$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 2'10 connect \Y $and$libresoc.v:42229$1833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42231$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 7'1000000 connect \Y $and$libresoc.v:42231$1835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42233$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 6'100000 connect \Y $and$libresoc.v:42233$1837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42235$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 8'10000000 connect \Y $and$libresoc.v:42235$1839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42237$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 5'10000 connect \Y $and$libresoc.v:42237$1841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42239$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 11 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 11'10000000000 connect \Y $and$libresoc.v:42239$1843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42241$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 10'1000000000 connect \Y $and$libresoc.v:42241$1845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42243$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 9 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 9'100000000 connect \Y $and$libresoc.v:42243$1847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42245$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 4'1000 connect \Y $and$libresoc.v:42245$1849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $and $and$libresoc.v:42247$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 3'100 connect \Y $and$libresoc.v:42247$1851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42252$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42252$1856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42253$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 connect \Y $and$libresoc.v:42253$1857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $and $and$libresoc.v:42256$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok connect \Y $and$libresoc.v:42256$1860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $and $and$libresoc.v:42259$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 connect \Y $and$libresoc.v:42259$1863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42266$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42266$1870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42267$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 connect \Y $and$libresoc.v:42267$1871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $and $and$libresoc.v:42270$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok connect \Y $and$libresoc.v:42270$1874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42273$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42273$1877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42274$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 connect \Y $and$libresoc.v:42274$1878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $and $and$libresoc.v:42277$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok connect \Y $and$libresoc.v:42277$1881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" cell $and $and$libresoc.v:42279$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42279$1883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" cell $and $and$libresoc.v:42280$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 connect \Y $and$libresoc.v:42280$1884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $and $and$libresoc.v:42284$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 connect \Y $and$libresoc.v:42284$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42288$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42288$1892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42289$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 connect \Y $and$libresoc.v:42289$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $and $and$libresoc.v:42292$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok connect \Y $and$libresoc.v:42292$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42295$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42295$1899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42296$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 connect \Y $and$libresoc.v:42296$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $and $and$libresoc.v:42299$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok connect \Y $and$libresoc.v:42299$1903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42302$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42302$1906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42303$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 connect \Y $and$libresoc.v:42303$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $and $and$libresoc.v:42306$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok connect \Y $and$libresoc.v:42306$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $and $and$libresoc.v:42309$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 connect \Y $and$libresoc.v:42309$1913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42314$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42314$1918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42315$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$352 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42315$1919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42317$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$354 connect \B \$356 connect \Y $and$libresoc.v:42317$1921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42318$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [0] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42318$1922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42320$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [1] connect \Y $and$libresoc.v:42320$1924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42321$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$364 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42321$1925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42323$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$366 connect \B \$368 connect \Y $and$libresoc.v:42323$1927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42324$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [1] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42324$1928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42326$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42326$1930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42327$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$376 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42327$1931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42329$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$378 connect \B \$380 connect \Y $and$libresoc.v:42329$1933_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42330$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [2] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42330$1934_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42332$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [4] connect \Y $and$libresoc.v:42332$1936_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42333$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$388 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42333$1937_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42335$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$390 connect \B \$392 connect \Y $and$libresoc.v:42335$1939_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42336$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [3] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42336$1940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42338$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [1] connect \B \fu_enable [6] connect \Y $and$libresoc.v:42338$1942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42339$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$400 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42339$1943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42341$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$402 connect \B \$404 connect \Y $and$libresoc.v:42341$1945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42342$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [4] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42342$1946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42344$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [1] connect \B \fu_enable [7] connect \Y $and$libresoc.v:42344$1948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42345$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$412 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42345$1949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42347$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$414 connect \B \$416 connect \Y $and$libresoc.v:42347$1951_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42348$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [5] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42348$1952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42350$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [1] connect \B \fu_enable [8] connect \Y $and$libresoc.v:42350$1954_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42351$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$424 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42351$1955_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42353$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$426 connect \B \$428 connect \Y $and$libresoc.v:42353$1957_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42354$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [6] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42354$1958_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42356$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [1] connect \B \fu_enable [9] connect \Y $and$libresoc.v:42356$1960_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42357$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$436 connect \B \rdflag_INT_rabc_0 connect \Y $and$libresoc.v:42357$1961_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42359$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$438 connect \B \$440 connect \Y $and$libresoc.v:42359$1963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42360$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [7] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42360$1964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42362$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [2] connect \B \fu_enable [8] connect \Y $and$libresoc.v:42362$1966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42363$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$448 connect \B \rdflag_INT_rabc_1 connect \Y $and$libresoc.v:42363$1967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42365$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$450 connect \B \$452 connect \Y $and$libresoc.v:42365$1969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42366$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [8] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42366$1970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42368$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [2] connect \B \fu_enable [9] connect \Y $and$libresoc.v:42368$1972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42369$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$460 connect \B \rdflag_INT_rabc_1 connect \Y $and$libresoc.v:42369$1973_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42371$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$462 connect \B \$464 connect \Y $and$libresoc.v:42371$1975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42372$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [9] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42372$1976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42374$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42374$1978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42375$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$472 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42375$1979_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42377$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$474 connect \B \$476 connect \Y $and$libresoc.v:42377$1981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42378$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [10] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42378$1982_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42380$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [0] connect \B \fu_enable [1] connect \Y $and$libresoc.v:42380$1984_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42381$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$484 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42381$1985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42383$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$486 connect \B \$488 connect \Y $and$libresoc.v:42383$1987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42384$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [11] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42384$1988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42386$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [0] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42386$1990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42387$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$496 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42387$1991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42389$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$498 connect \B \$500 connect \Y $and$libresoc.v:42389$1993_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42390$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [12] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42390$1994_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42392$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [0] connect \B \fu_enable [4] connect \Y $and$libresoc.v:42392$1996_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42393$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$508 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42393$1997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42395$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$510 connect \B \$512 connect \Y $and$libresoc.v:42395$1999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42396$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [13] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42396$2000_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42398$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [0] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42398$2002_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42399$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$520 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42399$2003_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42401$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$522 connect \B \$524 connect \Y $and$libresoc.v:42401$2005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42402$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [14] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42402$2006_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42404$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [0] connect \B \fu_enable [6] connect \Y $and$libresoc.v:42404$2008_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42405$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$532 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42405$2009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42407$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$534 connect \B \$536 connect \Y $and$libresoc.v:42407$2011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42408$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [15] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42408$2012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42410$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [0] connect \B \fu_enable [7] connect \Y $and$libresoc.v:42410$2014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42411$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$544 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42411$2015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42413$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$546 connect \B \$548 connect \Y $and$libresoc.v:42413$2017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42414$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [16] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42414$2018_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42416$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [0] connect \B \fu_enable [8] connect \Y $and$libresoc.v:42416$2020_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42417$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$556 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42417$2021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42419$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$558 connect \B \$560 connect \Y $and$libresoc.v:42419$2023_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42420$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [17] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42420$2024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42422$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [0] connect \B \fu_enable [9] connect \Y $and$libresoc.v:42422$2026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42423$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$568 connect \B \rdflag_INT_rabc_2 connect \Y $and$libresoc.v:42423$2027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42425$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$570 connect \B \$572 connect \Y $and$libresoc.v:42425$2029_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42426$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_INT_rabc_o [18] connect \B \rdpick_INT_rabc_en_o connect \Y $and$libresoc.v:42426$2030_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42447$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42447$2051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $and $and$libresoc.v:42448$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 connect \Y $and$libresoc.v:42448$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $and $and$libresoc.v:42451$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok connect \Y $and$libresoc.v:42451$2055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42453$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42453$2057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42454$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$631 connect \B \rdflag_XER_xer_so_0 connect \Y $and$libresoc.v:42454$2058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42456$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$633 connect \B \$635 connect \Y $and$libresoc.v:42456$2060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42457$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42457$2061_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42459$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [4] connect \Y $and$libresoc.v:42459$2063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42460$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$643 connect \B \rdflag_XER_xer_so_0 connect \Y $and$libresoc.v:42460$2064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42462$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$645 connect \B \$647 connect \Y $and$libresoc.v:42462$2066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42463$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42463$2067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42465$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [3] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42465$2069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42466$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$655 connect \B \rdflag_XER_xer_so_0 connect \Y $and$libresoc.v:42466$2070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42468$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$657 connect \B \$659 connect \Y $and$libresoc.v:42468$2072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42469$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42469$2073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42471$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [6] connect \Y $and$libresoc.v:42471$2075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42472$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$667 connect \B \rdflag_XER_xer_so_0 connect \Y $and$libresoc.v:42472$2076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42474$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$669 connect \B \$671 connect \Y $and$libresoc.v:42474$2078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42475$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42475$2079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42477$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [7] connect \Y $and$libresoc.v:42477$2081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42478$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$679 connect \B \rdflag_XER_xer_so_0 connect \Y $and$libresoc.v:42478$2082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42480$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$681 connect \B \$683 connect \Y $and$libresoc.v:42480$2084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42481$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42481$2085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42483$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [3] connect \B \fu_enable [8] connect \Y $and$libresoc.v:42483$2087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42484$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$691 connect \B \rdflag_XER_xer_so_0 connect \Y $and$libresoc.v:42484$2088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42486$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$693 connect \B \$695 connect \Y $and$libresoc.v:42486$2090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42487$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o connect \Y $and$libresoc.v:42487$2091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $and $and$libresoc.v:42496$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 connect \Y $and$libresoc.v:42496$2101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42499$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42499$2104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42500$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$723 connect \B \rdflag_XER_xer_ca_0 connect \Y $and$libresoc.v:42500$2105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42502$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$725 connect \B \$727 connect \Y $and$libresoc.v:42502$2107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42503$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42503$2108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42505$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [5] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42505$2110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42506$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$735 connect \B \rdflag_XER_xer_ca_0 connect \Y $and$libresoc.v:42506$2111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42508$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$737 connect \B \$739 connect \Y $and$libresoc.v:42508$2113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42509$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42509$2114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42511$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [4] connect \B \fu_enable [8] connect \Y $and$libresoc.v:42511$2116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42512$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$747 connect \B \rdflag_XER_xer_ca_0 connect \Y $and$libresoc.v:42512$2117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42514$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$749 connect \B \$751 connect \Y $and$libresoc.v:42514$2119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42515$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o connect \Y $and$libresoc.v:42515$2120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" cell $and $and$libresoc.v:42520$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok connect \Y $and$libresoc.v:42520$2126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" cell $and $and$libresoc.v:42521$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 connect \Y $and$libresoc.v:42521$2127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42524$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [4] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42524$2130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42525$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$773 connect \B \rdflag_XER_xer_ov_0 connect \Y $and$libresoc.v:42525$2131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42527$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$775 connect \B \$777 connect \Y $and$libresoc.v:42527$2133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42528$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o connect \Y $and$libresoc.v:42528$2134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42530$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [1] connect \Y $and$libresoc.v:42530$2136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42531$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$785 connect \B \rdflag_CR_full_cr_0 connect \Y $and$libresoc.v:42531$2137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42533$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$787 connect \B \$789 connect \Y $and$libresoc.v:42533$2139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42534$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o connect \Y $and$libresoc.v:42534$2140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42536$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [3] connect \B \fu_enable [1] connect \Y $and$libresoc.v:42536$2142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42537$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$797 connect \B \rdflag_CR_cr_a_0 connect \Y $and$libresoc.v:42537$2143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42539$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$799 connect \B \$801 connect \Y $and$libresoc.v:42539$2145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42540$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42540$2146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42544$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [2] connect \B \fu_enable [2] connect \Y $and$libresoc.v:42544$2150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42545$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$813 connect \B \rdflag_CR_cr_a_0 connect \Y $and$libresoc.v:42545$2151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42547$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$815 connect \B \$817 connect \Y $and$libresoc.v:42547$2153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42548$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o connect \Y $and$libresoc.v:42548$2154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42553$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [1] connect \Y $and$libresoc.v:42553$2159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42554$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$832 connect \B \rdflag_CR_cr_b_0 connect \Y $and$libresoc.v:42554$2160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42556$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$834 connect \B \$836 connect \Y $and$libresoc.v:42556$2162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42557$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o connect \Y $and$libresoc.v:42557$2163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42561$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [1] connect \Y $and$libresoc.v:42561$2167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42562$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$848 connect \B \rdflag_CR_cr_c_0 connect \Y $and$libresoc.v:42562$2168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42564$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$850 connect \B \$852 connect \Y $and$libresoc.v:42564$2170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42565$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o connect \Y $and$libresoc.v:42565$2171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42569$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [0] connect \B \fu_enable [2] connect \Y $and$libresoc.v:42569$2175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42570$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$864 connect \B \rdflag_FAST_fast1_0 connect \Y $and$libresoc.v:42570$2176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42572$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$866 connect \B \$868 connect \Y $and$libresoc.v:42572$2178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42573$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42573$2179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42575$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42575$2181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42576$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$876 connect \B \rdflag_FAST_fast1_0 connect \Y $and$libresoc.v:42576$2182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42578$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$878 connect \B \$880 connect \Y $and$libresoc.v:42578$2184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42579$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42579$2185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42581$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [2] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42581$2187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42582$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$888 connect \B \rdflag_FAST_fast1_0 connect \Y $and$libresoc.v:42582$2188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42584$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$890 connect \B \$892 connect \Y $and$libresoc.v:42584$2190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42585$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42585$2191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42587$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [1] connect \B \fu_enable [2] connect \Y $and$libresoc.v:42587$2193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42588$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$900 connect \B \rdflag_FAST_fast1_1 connect \Y $and$libresoc.v:42588$2194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42590$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$902 connect \B \$904 connect \Y $and$libresoc.v:42590$2196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42591$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [3] connect \B \rdpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42591$2197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42593$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [3] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42593$2199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42594$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$912 connect \B \rdflag_FAST_fast1_1 connect \Y $and$libresoc.v:42594$2200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42596$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$914 connect \B \$916 connect \Y $and$libresoc.v:42596$2202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42597$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [4] connect \B \rdpick_FAST_fast1_en_o connect \Y $and$libresoc.v:42597$2203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42604$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$65 [1] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42604$2210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" cell $and $and$libresoc.v:42605$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$934 connect \B \rdflag_SPR_spr1_0 connect \Y $and$libresoc.v:42605$2211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $and $and$libresoc.v:42607$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$936 connect \B \$938 connect \Y $and$libresoc.v:42607$2213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" cell $and $and$libresoc.v:42608$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o connect \Y $and$libresoc.v:42608$2214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42611$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o connect \Y $and$libresoc.v:42611$2217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42612$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] connect \Y $and$libresoc.v:42612$2218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42613$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [1] connect \Y $and$libresoc.v:42613$2219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42614$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [3] connect \Y $and$libresoc.v:42614$2220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42615$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [4] connect \Y $and$libresoc.v:42615$2221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42616$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [5] connect \Y $and$libresoc.v:42616$2222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42617$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [0] connect \B \fu_enable [6] connect \Y $and$libresoc.v:42617$2223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42618$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [0] connect \B \fu_enable [7] connect \Y $and$libresoc.v:42618$2224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42619$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [8] connect \Y $and$libresoc.v:42619$2225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42620$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [0] connect \B \fu_enable [9] connect \Y $and$libresoc.v:42620$2226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" cell $and $and$libresoc.v:42621$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [1] connect \B \fu_enable [9] connect \Y $and$libresoc.v:42621$2227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42622$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:42622$2228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42624$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \$972 connect \Y $and$libresoc.v:42624$2230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42625$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:42625$2231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" cell $and $and$libresoc.v:42627$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_o_ok$92 connect \B \fus_cu_busy_o$14 connect \Y $and$libresoc.v:42627$2233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" cell $and $and$libresoc.v:42628$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:42628$2234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:42630$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$986 connect \B \$991 connect \Y $and$libresoc.v:42630$2236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" cell $and $and$libresoc.v:42631$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick$986 connect \B \wrpick_INT_o_en_o connect \Y $and$libresoc.v:42631$2237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $eq $eq$libresoc.v:42254$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$231 connect \B 1'1 connect \Y $eq$libresoc.v:42254$1858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" cell $eq $eq$libresoc.v:42258$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 connect \Y $eq$libresoc.v:42258$1862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $eq $eq$libresoc.v:42260$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$243 connect \B 3'100 connect \Y $eq$libresoc.v:42260$1864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $eq $eq$libresoc.v:42268$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$259 connect \B 1'1 connect \Y $eq$libresoc.v:42268$1872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $eq $eq$libresoc.v:42275$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$273 connect \B 1'1 connect \Y $eq$libresoc.v:42275$1879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" cell $eq $eq$libresoc.v:42281$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$285 connect \B 2'10 connect \Y $eq$libresoc.v:42281$1885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" cell $eq $eq$libresoc.v:42283$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 connect \Y $eq$libresoc.v:42283$1887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $eq $eq$libresoc.v:42285$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$293 connect \B 3'100 connect \Y $eq$libresoc.v:42285$1889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $eq $eq$libresoc.v:42290$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$303 connect \B 1'1 connect \Y $eq$libresoc.v:42290$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $eq $eq$libresoc.v:42297$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$317 connect \B 1'1 connect \Y $eq$libresoc.v:42297$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $eq $eq$libresoc.v:42304$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$331 connect \B 1'1 connect \Y $eq$libresoc.v:42304$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" cell $eq $eq$libresoc.v:42308$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 connect \Y $eq$libresoc.v:42308$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $eq $eq$libresoc.v:42310$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$343 connect \B 3'100 connect \Y $eq$libresoc.v:42310$1914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $eq $eq$libresoc.v:42449$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$621 connect \B 1'1 connect \Y $eq$libresoc.v:42449$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" cell $eq $eq$libresoc.v:42495$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 connect \Y $eq$libresoc.v:42495$2100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $eq $eq$libresoc.v:42497$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$717 connect \B 3'100 connect \Y $eq$libresoc.v:42497$2102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" cell $eq $eq$libresoc.v:42522$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$767 connect \B 2'10 connect \Y $eq$libresoc.v:42522$2128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $extend$libresoc.v:42079$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$1445 connect \Y $extend$libresoc.v:42079$1678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $extend$libresoc.v:42145$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \$1609 connect \Y $extend$libresoc.v:42145$1745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $extend$libresoc.v:42149$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1617 connect \Y $extend$libresoc.v:42149$1750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $pos $extend$libresoc.v:42213$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1776 connect \Y $extend$libresoc.v:42213$1815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" cell $pos $extend$libresoc.v:42221$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \addr_en$1794 connect \Y $extend$libresoc.v:42221$1824_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $extend$libresoc.v:42494$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$712 connect \Y $extend$libresoc.v:42494$2098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $extend$libresoc.v:42519$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$762 connect \Y $extend$libresoc.v:42519$2124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" cell $ne $ne$libresoc.v:42249$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 connect \Y $ne$libresoc.v:42249$1853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" cell $ne $ne$libresoc.v:42251$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 connect \Y $ne$libresoc.v:42251$1855_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41910$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1008 connect \Y $not$libresoc.v:41910$1509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41916$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1029 connect \Y $not$libresoc.v:41916$1515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41922$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1047 connect \Y $not$libresoc.v:41922$1521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41928$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1069 connect \Y $not$libresoc.v:41928$1527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41934$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1089 connect \Y $not$libresoc.v:41934$1533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41940$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1109 connect \Y $not$libresoc.v:41940$1539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41946$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1128 connect \Y $not$libresoc.v:41946$1545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41952$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1146 connect \Y $not$libresoc.v:41952$1551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41986$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1220 connect \Y $not$libresoc.v:41986$1585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:41998$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1248 connect \Y $not$libresoc.v:41998$1597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42006$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1268 connect \Y $not$libresoc.v:42006$1605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42014$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1288 connect \Y $not$libresoc.v:42014$1613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42022$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1308 connect \Y $not$libresoc.v:42022$1621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42030$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1328 connect \Y $not$libresoc.v:42030$1629_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42038$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1348 connect \Y $not$libresoc.v:42038$1637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42059$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1395 connect \Y $not$libresoc.v:42059$1658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42065$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1411 connect \Y $not$libresoc.v:42065$1664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42071$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1427 connect \Y $not$libresoc.v:42071$1670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42086$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1461 connect \Y $not$libresoc.v:42086$1686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42092$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1477 connect \Y $not$libresoc.v:42092$1692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42098$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1493 connect \Y $not$libresoc.v:42098$1698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42104$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1509 connect \Y $not$libresoc.v:42104$1704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42120$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1545 connect \Y $not$libresoc.v:42120$1720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42126$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1561 connect \Y $not$libresoc.v:42126$1726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42132$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1577 connect \Y $not$libresoc.v:42132$1732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42138$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1593 connect \Y $not$libresoc.v:42138$1738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42157$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1635 connect \Y $not$libresoc.v:42157$1759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42163$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1654 connect \Y $not$libresoc.v:42163$1765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42169$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1670 connect \Y $not$libresoc.v:42169$1771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42175$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1686 connect \Y $not$libresoc.v:42175$1777_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42181$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1702 connect \Y $not$libresoc.v:42181$1783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42201$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1746 connect \Y $not$libresoc.v:42201$1803_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42207$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1762 connect \Y $not$libresoc.v:42207$1809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42217$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1786 connect \Y $not$libresoc.v:42217$1820_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42225$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1806 connect \Y $not$libresoc.v:42225$1829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42262$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { \$247 \$239 \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42262$1866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42263$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { \core_cr_in2_ok$2 \core_cr_in2_ok \core_cr_in1_ok \core_core_cr_rd_ok \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42263$1867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42264$1868 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \core_cr_in1_ok \core_fast2_ok \core_fast1_ok } connect \Y $not$libresoc.v:42264$1868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42265$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { \core_fast2_ok \core_fast1_ok \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42265$1869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42272$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \$267 \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42272$1876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42287$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { \$297 \$289 \$281 \core_fast1_ok \core_spr1_ok \core_reg1_ok } connect \Y $not$libresoc.v:42287$1891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42294$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \$311 \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42294$1898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42301$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \$325 \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42301$1905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42312$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { \$347 \$339 \core_reg3_ok \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42312$1916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" cell $not $not$libresoc.v:42313$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \core_reg3_ok \core_reg2_ok \core_reg1_ok } connect \Y $not$libresoc.v:42313$1917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42316$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_alu0_0 connect \Y $not$libresoc.v:42316$1920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42322$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_cr0_1 connect \Y $not$libresoc.v:42322$1926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42328$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_trap0_2 connect \Y $not$libresoc.v:42328$1932_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42334$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_logical0_3 connect \Y $not$libresoc.v:42334$1938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42340$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_div0_4 connect \Y $not$libresoc.v:42340$1944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42346$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_mul0_5 connect \Y $not$libresoc.v:42346$1950_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42352$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_shiftrot0_6 connect \Y $not$libresoc.v:42352$1956_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42358$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_ldst0_7 connect \Y $not$libresoc.v:42358$1962_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42364$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_shiftrot0_8 connect \Y $not$libresoc.v:42364$1968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42370$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_ldst0_9 connect \Y $not$libresoc.v:42370$1974_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42376$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_alu0_10 connect \Y $not$libresoc.v:42376$1980_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42382$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_cr0_11 connect \Y $not$libresoc.v:42382$1986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42388$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_trap0_12 connect \Y $not$libresoc.v:42388$1992_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42394$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_logical0_13 connect \Y $not$libresoc.v:42394$1998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42400$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_spr0_14 connect \Y $not$libresoc.v:42400$2004_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42406$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_div0_15 connect \Y $not$libresoc.v:42406$2010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42412$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_mul0_16 connect \Y $not$libresoc.v:42412$2016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42418$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_shiftrot0_17 connect \Y $not$libresoc.v:42418$2022_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42424$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_INT_rabc_ldst0_18 connect \Y $not$libresoc.v:42424$2028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42455$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_alu0_0 connect \Y $not$libresoc.v:42455$2059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42461$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_logical0_1 connect \Y $not$libresoc.v:42461$2065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42467$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_spr0_2 connect \Y $not$libresoc.v:42467$2071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42473$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_div0_3 connect \Y $not$libresoc.v:42473$2077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42479$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_mul0_4 connect \Y $not$libresoc.v:42479$2083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42485$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_so_shiftrot0_5 connect \Y $not$libresoc.v:42485$2089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42501$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_alu0_0 connect \Y $not$libresoc.v:42501$2106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42507$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_spr0_1 connect \Y $not$libresoc.v:42507$2112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42513$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ca_shiftrot0_2 connect \Y $not$libresoc.v:42513$2118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42526$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ov_spr0_0 connect \Y $not$libresoc.v:42526$2132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42532$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 connect \Y $not$libresoc.v:42532$2138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42538$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 connect \Y $not$libresoc.v:42538$2144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42546$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 connect \Y $not$libresoc.v:42546$2152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42555$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 connect \Y $not$libresoc.v:42555$2161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42563$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 connect \Y $not$libresoc.v:42563$2169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42571$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 connect \Y $not$libresoc.v:42571$2177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42577$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 connect \Y $not$libresoc.v:42577$2183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42583$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 connect \Y $not$libresoc.v:42583$2189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42589$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_3 connect \Y $not$libresoc.v:42589$2195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42595$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_4 connect \Y $not$libresoc.v:42595$2201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" cell $not $not$libresoc.v:42606$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 connect \Y $not$libresoc.v:42606$2212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42623$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly connect \Y $not$libresoc.v:42623$2229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:42629$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$989 connect \Y $not$libresoc.v:42629$2235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41956$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o connect \B \fus_dest1_o$115 connect \Y $or$libresoc.v:41956$1555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41957$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o$117 connect \B \fus_dest1_o$118 connect \Y $or$libresoc.v:41957$1556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41958$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o$116 connect \B \$1160 connect \Y $or$libresoc.v:41958$1557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41959$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$1158 connect \B \$1162 connect \Y $or$libresoc.v:41959$1558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41960$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o$119 connect \B \fus_dest1_o$120 connect \Y $or$libresoc.v:41960$1559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41961$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } connect \Y $or$libresoc.v:41961$1560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41962$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 connect \A \fus_dest1_o$121 connect \B \$1168 connect \Y $or$libresoc.v:41962$1561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41963$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 connect \A \$1166 connect \B \$1170 connect \Y $or$libresoc.v:41963$1562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41964$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 connect \A \$1164 connect \B \$1172 connect \Y $or$libresoc.v:41964$1563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41965$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en connect \B \addr_en$1000 connect \Y $or$libresoc.v:41965$1564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41966$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en$1039 connect \B \addr_en$1061 connect \Y $or$libresoc.v:41966$1565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41967$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en$1021 connect \B \$1179 connect \Y $or$libresoc.v:41967$1566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41968$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$1177 connect \B \$1181 connect \Y $or$libresoc.v:41968$1567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41969$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en$1081 connect \B \addr_en$1101 connect \Y $or$libresoc.v:41969$1568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41970$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en$1138 connect \B \addr_en$1154 connect \Y $or$libresoc.v:41970$1569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41971$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en$1120 connect \B \$1187 connect \Y $or$libresoc.v:41971$1570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41972$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$1185 connect \B \$1189 connect \Y $or$libresoc.v:41972$1571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41973$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$1183 connect \B \$1191 connect \Y $or$libresoc.v:41973$1572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41974$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp connect \B \wp$997 connect \Y $or$libresoc.v:41974$1573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41975$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1036 connect \B \wp$1058 connect \Y $or$libresoc.v:41975$1574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41976$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1018 connect \B \$1197 connect \Y $or$libresoc.v:41976$1575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41977$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1195 connect \B \$1199 connect \Y $or$libresoc.v:41977$1576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41978$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1078 connect \B \wp$1098 connect \Y $or$libresoc.v:41978$1577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:41979$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1135 connect \B \wp$1151 connect \Y $or$libresoc.v:41979$1578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41980$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1117 connect \B \$1205 connect \Y $or$libresoc.v:41980$1579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41981$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1203 connect \B \$1207 connect \Y $or$libresoc.v:41981$1580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:41982$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1201 connect \B \$1209 connect \Y $or$libresoc.v:41982$1581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42044$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest3_o connect \B \fus_dest2_o$128 connect \Y $or$libresoc.v:42044$1643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42045$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$127 connect \B \$1363 connect \Y $or$libresoc.v:42045$1644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42046$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$130 connect \B \fus_dest2_o$131 connect \Y $or$libresoc.v:42046$1645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42047$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest2_o$129 connect \B \$1367 connect \Y $or$libresoc.v:42047$1646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42048$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$1365 connect \B \$1369 connect \Y $or$libresoc.v:42048$1647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42049$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 connect \A \addr_en$1276 connect \B \addr_en$1296 connect \Y $or$libresoc.v:42049$1648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42050$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 connect \A \addr_en$1256 connect \B \$1374 connect \Y $or$libresoc.v:42050$1649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42051$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 connect \A \addr_en$1336 connect \B \addr_en$1356 connect \Y $or$libresoc.v:42051$1650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42052$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 connect \A \addr_en$1316 connect \B \$1378 connect \Y $or$libresoc.v:42052$1651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42053$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 connect \A \$1376 connect \B \$1380 connect \Y $or$libresoc.v:42053$1652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42075$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest6_o connect \B \fus_dest3_o$135 connect \Y $or$libresoc.v:42075$1674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42076$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest3_o$134 connect \B \$1438 connect \Y $or$libresoc.v:42076$1675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42077$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en$1419 connect \B \addr_en$1435 connect \Y $or$libresoc.v:42077$1676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42078$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en$1403 connect \B \$1443 connect \Y $or$libresoc.v:42078$1677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42108$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o connect \Y $or$libresoc.v:42108$1708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42109$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest3_o$139 connect \B \fus_dest3_o$140 connect \Y $or$libresoc.v:42109$1709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42110$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \$1520 connect \B \$1522 connect \Y $or$libresoc.v:42110$1710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42111$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en$1469 connect \B \addr_en$1485 connect \Y $or$libresoc.v:42111$1711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42112$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en$1501 connect \B \addr_en$1517 connect \Y $or$libresoc.v:42112$1712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42113$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$1526 connect \B \$1528 connect \Y $or$libresoc.v:42113$1713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42142$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_dest5_o$144 connect \B \fus_dest4_o$145 connect \Y $or$libresoc.v:42142$1742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42143$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_dest4_o$146 connect \B \fus_dest4_o$147 connect \Y $or$libresoc.v:42143$1743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42144$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1605 connect \B \$1607 connect \Y $or$libresoc.v:42144$1744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42146$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en$1553 connect \B \addr_en$1569 connect \Y $or$libresoc.v:42146$1747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42147$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en$1585 connect \B \addr_en$1601 connect \Y $or$libresoc.v:42147$1748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42148$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1613 connect \B \$1615 connect \Y $or$libresoc.v:42148$1749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42185$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o$153 connect \B \fus_dest2_o$154 connect \Y $or$libresoc.v:42185$1787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42186$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest2_o$156 connect \B \fus_dest3_o$157 connect \Y $or$libresoc.v:42186$1788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42187$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest3_o$155 connect \B \$1715 connect \Y $or$libresoc.v:42187$1789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42188$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$1713 connect \B \$1717 connect \Y $or$libresoc.v:42188$1790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42189$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en$1646 connect \B \addr_en$1662 connect \Y $or$libresoc.v:42189$1791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42190$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en$1694 connect \B \addr_en$1710 connect \Y $or$libresoc.v:42190$1792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42191$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en$1678 connect \B \$1723 connect \Y $or$libresoc.v:42191$1793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42192$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$1721 connect \B \$1725 connect \Y $or$libresoc.v:42192$1794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42193$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1643 connect \B \wp$1659 connect \Y $or$libresoc.v:42193$1795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42194$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1691 connect \B \wp$1707 connect \Y $or$libresoc.v:42194$1796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42195$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp$1675 connect \B \$1731 connect \Y $or$libresoc.v:42195$1797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42196$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1729 connect \B \$1733 connect \Y $or$libresoc.v:42196$1798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42211$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest3_o$159 connect \B \fus_dest4_o$160 connect \Y $or$libresoc.v:42211$1813_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42212$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en$1754 connect \B \addr_en$1770 connect \Y $or$libresoc.v:42212$1814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $or $or$libresoc.v:42255$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$229 connect \B \$233 connect \Y $or$libresoc.v:42255$1859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $or $or$libresoc.v:42257$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$235 connect \B \$237 connect \Y $or$libresoc.v:42257$1861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $or $or$libresoc.v:42261$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$241 connect \B \$245 connect \Y $or$libresoc.v:42261$1865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $or $or$libresoc.v:42269$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$257 connect \B \$261 connect \Y $or$libresoc.v:42269$1873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $or $or$libresoc.v:42271$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$263 connect \B \$265 connect \Y $or$libresoc.v:42271$1875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $or $or$libresoc.v:42276$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$271 connect \B \$275 connect \Y $or$libresoc.v:42276$1880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $or $or$libresoc.v:42278$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$277 connect \B \$279 connect \Y $or$libresoc.v:42278$1882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" cell $or $or$libresoc.v:42282$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$283 connect \B \$287 connect \Y $or$libresoc.v:42282$1886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $or $or$libresoc.v:42286$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$291 connect \B \$295 connect \Y $or$libresoc.v:42286$1890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $or $or$libresoc.v:42291$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$301 connect \B \$305 connect \Y $or$libresoc.v:42291$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $or $or$libresoc.v:42293$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$307 connect \B \$309 connect \Y $or$libresoc.v:42293$1897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $or $or$libresoc.v:42298$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$315 connect \B \$319 connect \Y $or$libresoc.v:42298$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $or $or$libresoc.v:42300$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$321 connect \B \$323 connect \Y $or$libresoc.v:42300$1904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $or $or$libresoc.v:42305$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$329 connect \B \$333 connect \Y $or$libresoc.v:42305$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $or $or$libresoc.v:42307$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$335 connect \B \$337 connect \Y $or$libresoc.v:42307$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $or $or$libresoc.v:42311$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$341 connect \B \$345 connect \Y $or$libresoc.v:42311$1915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42428$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_alu0_0 connect \B \addr_en_INT_rabc_cr0_1 connect \Y $or$libresoc.v:42428$2032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42429$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_trap0_2 connect \B \addr_en_INT_rabc_logical0_3 connect \Y $or$libresoc.v:42429$2033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42430$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$581 connect \B \$583 connect \Y $or$libresoc.v:42430$2034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42431$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_div0_4 connect \B \addr_en_INT_rabc_mul0_5 connect \Y $or$libresoc.v:42431$2035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42432$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_ldst0_7 connect \B \addr_en_INT_rabc_shiftrot0_8 connect \Y $or$libresoc.v:42432$2036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42433$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_shiftrot0_6 connect \B \$589 connect \Y $or$libresoc.v:42433$2037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42434$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$587 connect \B \$591 connect \Y $or$libresoc.v:42434$2038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42435$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$585 connect \B \$593 connect \Y $or$libresoc.v:42435$2039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42436$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_ldst0_9 connect \B \addr_en_INT_rabc_alu0_10 connect \Y $or$libresoc.v:42436$2040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42437$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_trap0_12 connect \B \addr_en_INT_rabc_logical0_13 connect \Y $or$libresoc.v:42437$2041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42438$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_cr0_11 connect \B \$599 connect \Y $or$libresoc.v:42438$2042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42439$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$597 connect \B \$601 connect \Y $or$libresoc.v:42439$2043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42440$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_spr0_14 connect \B \addr_en_INT_rabc_div0_15 connect \Y $or$libresoc.v:42440$2044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42441$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_shiftrot0_17 connect \B \addr_en_INT_rabc_ldst0_18 connect \Y $or$libresoc.v:42441$2045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42442$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \addr_en_INT_rabc_mul0_16 connect \B \$607 connect \Y $or$libresoc.v:42442$2046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42443$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$605 connect \B \$609 connect \Y $or$libresoc.v:42443$2047_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42444$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$603 connect \B \$611 connect \Y $or$libresoc.v:42444$2048_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42445$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A \$595 connect \B \$613 connect \Y $or$libresoc.v:42445$2049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" cell $or $or$libresoc.v:42450$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$619 connect \B \$623 connect \Y $or$libresoc.v:42450$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" cell $or $or$libresoc.v:42452$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$625 connect \B \$627 connect \Y $or$libresoc.v:42452$2056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42489$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 connect \Y $or$libresoc.v:42489$2093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42490$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 connect \B \$704 connect \Y $or$libresoc.v:42490$2094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42491$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 connect \Y $or$libresoc.v:42491$2095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42492$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 connect \B \$708 connect \Y $or$libresoc.v:42492$2096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42493$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$706 connect \B \$710 connect \Y $or$libresoc.v:42493$2097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" cell $or $or$libresoc.v:42498$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$715 connect \B \$719 connect \Y $or$libresoc.v:42498$2103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42517$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 connect \Y $or$libresoc.v:42517$2122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42518$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 connect \B \$760 connect \Y $or$libresoc.v:42518$2123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" cell $or $or$libresoc.v:42523$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$765 connect \B \$769 connect \Y $or$libresoc.v:42523$2129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42552$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 parameter \B_WIDTH 256 parameter \Y_WIDTH 256 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 connect \Y $or$libresoc.v:42552$2158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42599$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 connect \B \addr_en_FAST_fast1_trap0_1 connect \Y $or$libresoc.v:42599$2205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:42600$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_3 connect \B \addr_en_FAST_fast1_trap0_4 connect \Y $or$libresoc.v:42600$2206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42601$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_spr0_2 connect \B \$926 connect \Y $or$libresoc.v:42601$2207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:42602$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$924 connect \B \$928 connect \Y $or$libresoc.v:42602$2208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $pos$libresoc.v:42079$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A $extend$libresoc.v:42079$1678_Y connect \Y $pos$libresoc.v:42079$1679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $pos$libresoc.v:42145$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A $extend$libresoc.v:42145$1745_Y connect \Y $pos$libresoc.v:42145$1746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $pos$libresoc.v:42149$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A $extend$libresoc.v:42149$1750_Y connect \Y $pos$libresoc.v:42149$1751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $pos $pos$libresoc.v:42213$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A $extend$libresoc.v:42213$1815_Y connect \Y $pos$libresoc.v:42213$1816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" cell $pos $pos$libresoc.v:42221$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A $extend$libresoc.v:42221$1824_Y connect \Y $pos$libresoc.v:42221$1825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $pos$libresoc.v:42494$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A $extend$libresoc.v:42494$2098_Y connect \Y $pos$libresoc.v:42494$2099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $pos $pos$libresoc.v:42519$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A $extend$libresoc.v:42519$2124_Y connect \Y $pos$libresoc.v:42519$2125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42230$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$182 connect \Y $reduce_or$libresoc.v:42230$1834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42232$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$186 connect \Y $reduce_or$libresoc.v:42232$1836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42234$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$190 connect \Y $reduce_or$libresoc.v:42234$1838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42236$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$194 connect \Y $reduce_or$libresoc.v:42236$1840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42238$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$198 connect \Y $reduce_or$libresoc.v:42238$1842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42240$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$202 connect \Y $reduce_or$libresoc.v:42240$1844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42242$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$206 connect \Y $reduce_or$libresoc.v:42242$1846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42244$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$210 connect \Y $reduce_or$libresoc.v:42244$1848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42246$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$214 connect \Y $reduce_or$libresoc.v:42246$1850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" cell $reduce_or $reduce_or$libresoc.v:42248$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$218 connect \Y $reduce_or$libresoc.v:42248$1852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" cell $reduce_or $reduce_or$libresoc.v:42446$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 1 connect \A { \rp_INT_rabc_ldst0_18 \rp_INT_rabc_shiftrot0_17 \rp_INT_rabc_mul0_16 \rp_INT_rabc_div0_15 \rp_INT_rabc_spr0_14 \rp_INT_rabc_logical0_13 \rp_INT_rabc_trap0_12 \rp_INT_rabc_cr0_11 \rp_INT_rabc_alu0_10 \rp_INT_rabc_ldst0_9 \rp_INT_rabc_shiftrot0_8 \rp_INT_rabc_ldst0_7 \rp_INT_rabc_shiftrot0_6 \rp_INT_rabc_mul0_5 \rp_INT_rabc_div0_4 \rp_INT_rabc_logical0_3 \rp_INT_rabc_trap0_2 \rp_INT_rabc_cr0_1 \rp_INT_rabc_alu0_0 } connect \Y $reduce_or$libresoc.v:42446$2050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" cell $reduce_or $reduce_or$libresoc.v:42603$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_trap0_4 \rp_FAST_fast1_branch0_3 \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } connect \Y $reduce_or$libresoc.v:42603$2209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" cell $reduce_or $reduce_or$libresoc.v:42610$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 connect \Y $reduce_or$libresoc.v:42610$2216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sshl $sshl$libresoc.v:42002$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1257 connect \Y $sshl$libresoc.v:42002$1601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sshl $sshl$libresoc.v:42010$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1277 connect \Y $sshl$libresoc.v:42010$1609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sshl $sshl$libresoc.v:42018$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1297 connect \Y $sshl$libresoc.v:42018$1617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sshl $sshl$libresoc.v:42026$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1317 connect \Y $sshl$libresoc.v:42026$1625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sshl $sshl$libresoc.v:42034$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1337 connect \Y $sshl$libresoc.v:42034$1633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sshl $sshl$libresoc.v:42042$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1357 connect \Y $sshl$libresoc.v:42042$1641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" cell $sshl $sshl$libresoc.v:42542$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$807 connect \Y $sshl$libresoc.v:42542$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" cell $sshl $sshl$libresoc.v:42550$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$823 connect \Y $sshl$libresoc.v:42550$2156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" cell $sshl $sshl$libresoc.v:42559$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$842 connect \Y $sshl$libresoc.v:42559$2165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" cell $sshl $sshl$libresoc.v:42567$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$858 connect \Y $sshl$libresoc.v:42567$2173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sub $sub$libresoc.v:42001$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out connect \Y $sub$libresoc.v:42001$1600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sub $sub$libresoc.v:42009$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out connect \Y $sub$libresoc.v:42009$1608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sub $sub$libresoc.v:42017$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out connect \Y $sub$libresoc.v:42017$1616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sub $sub$libresoc.v:42025$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out connect \Y $sub$libresoc.v:42025$1624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sub $sub$libresoc.v:42033$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out connect \Y $sub$libresoc.v:42033$1632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" cell $sub $sub$libresoc.v:42041$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out connect \Y $sub$libresoc.v:42041$1640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" cell $sub $sub$libresoc.v:42250$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 connect \Y $sub$libresoc.v:42250$1854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" cell $sub $sub$libresoc.v:42541$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 connect \Y $sub$libresoc.v:42541$2147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" cell $sub $sub$libresoc.v:42549$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 connect \Y $sub$libresoc.v:42549$2155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" cell $sub $sub$libresoc.v:42558$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2 connect \Y $sub$libresoc.v:42558$2164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" cell $sub $sub$libresoc.v:42566$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2$1 connect \Y $sub$libresoc.v:42566$2172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41907$1506 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$997 connect \Y $ternary$libresoc.v:41907$1506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41913$1512 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1018 connect \Y $ternary$libresoc.v:41913$1512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41919$1518 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1036 connect \Y $ternary$libresoc.v:41919$1518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41925$1524 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1058 connect \Y $ternary$libresoc.v:41925$1524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41931$1530 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1078 connect \Y $ternary$libresoc.v:41931$1530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41937$1536 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1098 connect \Y $ternary$libresoc.v:41937$1536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41943$1542 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1117 connect \Y $ternary$libresoc.v:41943$1542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41949$1548 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1135 connect \Y $ternary$libresoc.v:41949$1548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41955$1554 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_ea connect \S \wp$1151 connect \Y $ternary$libresoc.v:41955$1554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:41989$1588 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr connect \S \wp$1225 connect \Y $ternary$libresoc.v:41989$1588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42003$1602 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1259 connect \S \wp$1253 connect \Y $ternary$libresoc.v:42003$1602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42011$1610 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1279 connect \S \wp$1273 connect \Y $ternary$libresoc.v:42011$1610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42019$1618 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1299 connect \S \wp$1293 connect \Y $ternary$libresoc.v:42019$1618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42027$1626 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1319 connect \S \wp$1313 connect \Y $ternary$libresoc.v:42027$1626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42035$1634 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1339 connect \S \wp$1333 connect \Y $ternary$libresoc.v:42035$1634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42043$1642 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1359 connect \S \wp$1353 connect \Y $ternary$libresoc.v:42043$1642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42062$1661 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1400 connect \Y $ternary$libresoc.v:42062$1661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42068$1667 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1416 connect \Y $ternary$libresoc.v:42068$1667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42074$1673 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1432 connect \Y $ternary$libresoc.v:42074$1673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42089$1689 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1466 connect \Y $ternary$libresoc.v:42089$1689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42095$1695 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1482 connect \Y $ternary$libresoc.v:42095$1695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42101$1701 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1498 connect \Y $ternary$libresoc.v:42101$1701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42107$1707 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1514 connect \Y $ternary$libresoc.v:42107$1707_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42123$1723 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1550 connect \Y $ternary$libresoc.v:42123$1723_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42129$1729 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1566 connect \Y $ternary$libresoc.v:42129$1729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42135$1735 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1582 connect \Y $ternary$libresoc.v:42135$1735_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42141$1741 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1598 connect \Y $ternary$libresoc.v:42141$1741_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42160$1762 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1643 connect \Y $ternary$libresoc.v:42160$1762_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42166$1768 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1659 connect \Y $ternary$libresoc.v:42166$1768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42172$1774 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1675 connect \Y $ternary$libresoc.v:42172$1774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42178$1780 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1691 connect \Y $ternary$libresoc.v:42178$1780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42184$1786 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1707 connect \Y $ternary$libresoc.v:42184$1786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42204$1806 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1751 connect \Y $ternary$libresoc.v:42204$1806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42210$1812 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1767 connect \Y $ternary$libresoc.v:42210$1812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42220$1823 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1791 connect \Y $ternary$libresoc.v:42220$1823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42228$1832 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro connect \S \wp$1811 connect \Y $ternary$libresoc.v:42228$1832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42319$1923 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_alu0_0 connect \Y $ternary$libresoc.v:42319$1923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42325$1929 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_cr0_1 connect \Y $ternary$libresoc.v:42325$1929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42331$1935 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_trap0_2 connect \Y $ternary$libresoc.v:42331$1935_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42337$1941 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_logical0_3 connect \Y $ternary$libresoc.v:42337$1941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42343$1947 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_div0_4 connect \Y $ternary$libresoc.v:42343$1947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42349$1953 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_mul0_5 connect \Y $ternary$libresoc.v:42349$1953_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42355$1959 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_shiftrot0_6 connect \Y $ternary$libresoc.v:42355$1959_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42361$1965 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rabc_ldst0_7 connect \Y $ternary$libresoc.v:42361$1965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42367$1971 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rabc_shiftrot0_8 connect \Y $ternary$libresoc.v:42367$1971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42373$1977 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rabc_ldst0_9 connect \Y $ternary$libresoc.v:42373$1977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42379$1983 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_alu0_10 connect \Y $ternary$libresoc.v:42379$1983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42385$1989 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_cr0_11 connect \Y $ternary$libresoc.v:42385$1989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42391$1995 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_trap0_12 connect \Y $ternary$libresoc.v:42391$1995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42397$2001 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_logical0_13 connect \Y $ternary$libresoc.v:42397$2001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42403$2007 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_spr0_14 connect \Y $ternary$libresoc.v:42403$2007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42409$2013 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_div0_15 connect \Y $ternary$libresoc.v:42409$2013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42415$2019 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_mul0_16 connect \Y $ternary$libresoc.v:42415$2019_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42421$2025 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_shiftrot0_17 connect \Y $ternary$libresoc.v:42421$2025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42427$2031 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_rabc_ldst0_18 connect \Y $ternary$libresoc.v:42427$2031_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42458$2062 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 connect \Y $ternary$libresoc.v:42458$2062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42464$2068 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 connect \Y $ternary$libresoc.v:42464$2068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42470$2074 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 connect \Y $ternary$libresoc.v:42470$2074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42476$2080 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 connect \Y $ternary$libresoc.v:42476$2080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42482$2086 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 connect \Y $ternary$libresoc.v:42482$2086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42488$2092 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 connect \Y $ternary$libresoc.v:42488$2092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42504$2109 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 connect \Y $ternary$libresoc.v:42504$2109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42510$2115 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 connect \Y $ternary$libresoc.v:42510$2115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42516$2121 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 connect \Y $ternary$libresoc.v:42516$2121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42529$2135 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 connect \Y $ternary$libresoc.v:42529$2135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42535$2141 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 connect \Y $ternary$libresoc.v:42535$2141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42543$2149 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$809 connect \S \rp_CR_cr_a_cr0_0 connect \Y $ternary$libresoc.v:42543$2149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42551$2157 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$825 connect \S \rp_CR_cr_a_branch0_1 connect \Y $ternary$libresoc.v:42551$2157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42560$2166 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$844 connect \S \rp_CR_cr_b_cr0_0 connect \Y $ternary$libresoc.v:42560$2166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42568$2174 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$860 connect \S \rp_CR_cr_c_cr0_0 connect \Y $ternary$libresoc.v:42568$2174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42574$2180 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 connect \Y $ternary$libresoc.v:42574$2180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42580$2186 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 connect \Y $ternary$libresoc.v:42580$2186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42586$2192 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 connect \Y $ternary$libresoc.v:42586$2192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42592$2198 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast1_branch0_3 connect \Y $ternary$libresoc.v:42592$2198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42598$2204 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast1_trap0_4 connect \Y $ternary$libresoc.v:42598$2204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" cell $mux $ternary$libresoc.v:42609$2215 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 connect \Y $ternary$libresoc.v:42609$2215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" cell $mux $ternary$libresoc.v:42626$2232 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp connect \Y $ternary$libresoc.v:42626$2232_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:42790.6-42807.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \data_i \cr_data_i connect \full_rd2__data_o \full_rd2__data_o connect \full_rd2__ren \full_rd2__ren connect \full_rd__data_o \cr_full_rd__data_o connect \full_rd__ren \cr_full_rd__ren connect \full_wr__data_i \cr_full_wr__data_i connect \full_wr__wen \cr_full_wr__wen connect \src1__data_o \cr_src1__data_o connect \src1__ren \cr_src1__ren connect \src2__data_o \cr_src2__data_o connect \src2__ren \cr_src2__ren connect \src3__data_o \cr_src3__data_o connect \src3__ren \cr_src3__ren connect \wen \cr_wen end attribute \module_not_derived 1 attribute \src "libresoc.v:42808.11-42830.4" cell \dec_ALU \dec_ALU connect \ALU__data_len \dec_ALU_ALU__data_len connect \ALU__fn_unit \dec_ALU_ALU__fn_unit connect \ALU__imm_data__data \dec_ALU_ALU__imm_data__data connect \ALU__imm_data__ok \dec_ALU_ALU__imm_data__ok connect \ALU__input_carry \dec_ALU_ALU__input_carry connect \ALU__insn \dec_ALU_ALU__insn connect \ALU__insn_type \dec_ALU_ALU__insn_type connect \ALU__invert_in \dec_ALU_ALU__invert_in connect \ALU__invert_out \dec_ALU_ALU__invert_out connect \ALU__is_32bit \dec_ALU_ALU__is_32bit connect \ALU__is_signed \dec_ALU_ALU__is_signed connect \ALU__oe__oe \dec_ALU_ALU__oe__oe connect \ALU__oe__ok \dec_ALU_ALU__oe__ok connect \ALU__output_carry \dec_ALU_ALU__output_carry connect \ALU__rc__ok \dec_ALU_ALU__rc__ok connect \ALU__rc__rc \dec_ALU_ALU__rc__rc connect \ALU__write_cr0 \dec_ALU_ALU__write_cr0 connect \ALU__zero_a \dec_ALU_ALU__zero_a connect \bigendian \dec_ALU_bigendian connect \raw_opcode_in \dec_ALU_raw_opcode_in connect \sv_a_nz \dec_ALU_sv_a_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:42831.14-42843.4" cell \dec_BRANCH \dec_BRANCH connect \BRANCH__cia \dec_BRANCH_BRANCH__cia connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit connect \BRANCH__imm_data__data \dec_BRANCH_BRANCH__imm_data__data connect \BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__ok connect \BRANCH__insn \dec_BRANCH_BRANCH__insn connect \BRANCH__insn_type \dec_BRANCH_BRANCH__insn_type connect \BRANCH__is_32bit \dec_BRANCH_BRANCH__is_32bit connect \BRANCH__lk \dec_BRANCH_BRANCH__lk connect \bigendian \dec_BRANCH_bigendian connect \core_pc \core_pc connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:42844.10-42850.4" cell \dec_CR \dec_CR connect \CR__fn_unit \dec_CR_CR__fn_unit connect \CR__insn \dec_CR_CR__insn connect \CR__insn_type \dec_CR_CR__insn_type connect \bigendian \dec_CR_bigendian connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:42851.11-42873.4" cell \dec_DIV \dec_DIV connect \DIV__data_len \dec_DIV_DIV__data_len connect \DIV__fn_unit \dec_DIV_DIV__fn_unit connect \DIV__imm_data__data \dec_DIV_DIV__imm_data__data connect \DIV__imm_data__ok \dec_DIV_DIV__imm_data__ok connect \DIV__input_carry \dec_DIV_DIV__input_carry connect \DIV__insn \dec_DIV_DIV__insn connect \DIV__insn_type \dec_DIV_DIV__insn_type connect \DIV__invert_in \dec_DIV_DIV__invert_in connect \DIV__invert_out \dec_DIV_DIV__invert_out connect \DIV__is_32bit \dec_DIV_DIV__is_32bit connect \DIV__is_signed \dec_DIV_DIV__is_signed connect \DIV__oe__oe \dec_DIV_DIV__oe__oe connect \DIV__oe__ok \dec_DIV_DIV__oe__ok connect \DIV__output_carry \dec_DIV_DIV__output_carry connect \DIV__rc__ok \dec_DIV_DIV__rc__ok connect \DIV__rc__rc \dec_DIV_DIV__rc__rc connect \DIV__write_cr0 \dec_DIV_DIV__write_cr0 connect \DIV__zero_a \dec_DIV_DIV__zero_a connect \bigendian \dec_DIV_bigendian connect \raw_opcode_in \dec_DIV_raw_opcode_in connect \sv_a_nz \dec_DIV_sv_a_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:42874.12-42894.4" cell \dec_LDST \dec_LDST connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse connect \LDST__data_len \dec_LDST_LDST__data_len connect \LDST__fn_unit \dec_LDST_LDST__fn_unit connect \LDST__imm_data__data \dec_LDST_LDST__imm_data__data connect \LDST__imm_data__ok \dec_LDST_LDST__imm_data__ok connect \LDST__insn \dec_LDST_LDST__insn connect \LDST__insn_type \dec_LDST_LDST__insn_type connect \LDST__is_32bit \dec_LDST_LDST__is_32bit connect \LDST__is_signed \dec_LDST_LDST__is_signed connect \LDST__ldst_mode \dec_LDST_LDST__ldst_mode connect \LDST__oe__oe \dec_LDST_LDST__oe__oe connect \LDST__oe__ok \dec_LDST_LDST__oe__ok connect \LDST__rc__ok \dec_LDST_LDST__rc__ok connect \LDST__rc__rc \dec_LDST_LDST__rc__rc connect \LDST__sign_extend \dec_LDST_LDST__sign_extend connect \LDST__zero_a \dec_LDST_LDST__zero_a connect \bigendian \dec_LDST_bigendian connect \raw_opcode_in \dec_LDST_raw_opcode_in connect \sv_a_nz \dec_LDST_sv_a_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:42895.15-42917.4" cell \dec_LOGICAL \dec_LOGICAL connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit connect \LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL__imm_data__data connect \LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__ok connect \LOGICAL__input_carry \dec_LOGICAL_LOGICAL__input_carry connect \LOGICAL__insn \dec_LOGICAL_LOGICAL__insn connect \LOGICAL__insn_type \dec_LOGICAL_LOGICAL__insn_type connect \LOGICAL__invert_in \dec_LOGICAL_LOGICAL__invert_in connect \LOGICAL__invert_out \dec_LOGICAL_LOGICAL__invert_out connect \LOGICAL__is_32bit \dec_LOGICAL_LOGICAL__is_32bit connect \LOGICAL__is_signed \dec_LOGICAL_LOGICAL__is_signed connect \LOGICAL__oe__oe \dec_LOGICAL_LOGICAL__oe__oe connect \LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__ok connect \LOGICAL__output_carry \dec_LOGICAL_LOGICAL__output_carry connect \LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__ok connect \LOGICAL__rc__rc \dec_LOGICAL_LOGICAL__rc__rc connect \LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL__write_cr0 connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a connect \bigendian \dec_LOGICAL_bigendian connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in connect \sv_a_nz \dec_LOGICAL_sv_a_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:42918.11-42933.4" cell \dec_MUL \dec_MUL connect \MUL__fn_unit \dec_MUL_MUL__fn_unit connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data connect \MUL__imm_data__ok \dec_MUL_MUL__imm_data__ok connect \MUL__insn \dec_MUL_MUL__insn connect \MUL__insn_type \dec_MUL_MUL__insn_type connect \MUL__is_32bit \dec_MUL_MUL__is_32bit connect \MUL__is_signed \dec_MUL_MUL__is_signed connect \MUL__oe__oe \dec_MUL_MUL__oe__oe connect \MUL__oe__ok \dec_MUL_MUL__oe__ok connect \MUL__rc__ok \dec_MUL_MUL__rc__ok connect \MUL__rc__rc \dec_MUL_MUL__rc__rc connect \MUL__write_cr0 \dec_MUL_MUL__write_cr0 connect \bigendian \dec_MUL_bigendian connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:42934.17-42954.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data connect \SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT__input_carry connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT__input_cr connect \SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT__insn connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT__insn_type connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_SHIFT_ROT__invert_in connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT__is_32bit connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT__is_signed connect \SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT__oe__oe connect \SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__ok connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT__output_carry connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT__output_cr connect \SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__ok connect \SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT__rc__rc connect \SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 connect \bigendian \dec_SHIFT_ROT_bigendian connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:42955.11-42962.4" cell \dec_SPR \dec_SPR connect \SPR__fn_unit \dec_SPR_SPR__fn_unit connect \SPR__insn \dec_SPR_SPR__insn connect \SPR__insn_type \dec_SPR_SPR__insn_type connect \SPR__is_32bit \dec_SPR_SPR__is_32bit connect \bigendian \dec_SPR_bigendian connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:42963.8-42978.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest1__addr \fast_dest1__addr connect \dest1__data_i \fast_dest1__data_i connect \dest1__wen \fast_dest1__wen connect \issue__addr \issue__addr connect \issue__addr$1 \issue__addr$12 connect \issue__data_i \issue__data_i connect \issue__data_o \issue__data_o connect \issue__ren \issue__ren connect \issue__wen \issue__wen connect \src1__addr \fast_src1__addr connect \src1__data_o \fast_src1__data_o connect \src1__ren \fast_src1__ren end attribute \module_not_derived 1 attribute \src "libresoc.v:42979.7-43310.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \fus_cr_a_ok connect \cr_a_ok$110 \fus_cr_a_ok$122 connect \cr_a_ok$111 \fus_cr_a_ok$123 connect \cr_a_ok$112 \fus_cr_a_ok$124 connect \cr_a_ok$113 \fus_cr_a_ok$125 connect \cr_a_ok$114 \fus_cr_a_ok$126 connect \cu_ad__go_i \cu_ad__go_i connect \cu_ad__rel_o \cu_ad__rel_o connect \cu_busy_o \fus_cu_busy_o connect \cu_busy_o$11 \fus_cu_busy_o$23 connect \cu_busy_o$14 \fus_cu_busy_o$26 connect \cu_busy_o$17 \fus_cu_busy_o$29 connect \cu_busy_o$2 \fus_cu_busy_o$14 connect \cu_busy_o$20 \fus_cu_busy_o$32 connect \cu_busy_o$23 \fus_cu_busy_o$35 connect \cu_busy_o$26 \fus_cu_busy_o$38 connect \cu_busy_o$5 \fus_cu_busy_o$17 connect \cu_busy_o$8 \fus_cu_busy_o$20 connect \cu_issue_i \fus_cu_issue_i connect \cu_issue_i$1 \fus_cu_issue_i$13 connect \cu_issue_i$10 \fus_cu_issue_i$22 connect \cu_issue_i$13 \fus_cu_issue_i$25 connect \cu_issue_i$16 \fus_cu_issue_i$28 connect \cu_issue_i$19 \fus_cu_issue_i$31 connect \cu_issue_i$22 \fus_cu_issue_i$34 connect \cu_issue_i$25 \fus_cu_issue_i$37 connect \cu_issue_i$4 \fus_cu_issue_i$16 connect \cu_issue_i$7 \fus_cu_issue_i$19 connect \cu_rd__go_i \fus_cu_rd__go_i connect \cu_rd__go_i$29 \fus_cu_rd__go_i$41 connect \cu_rd__go_i$32 \fus_cu_rd__go_i$44 connect \cu_rd__go_i$35 \fus_cu_rd__go_i$47 connect \cu_rd__go_i$38 \fus_cu_rd__go_i$50 connect \cu_rd__go_i$41 \fus_cu_rd__go_i$53 connect \cu_rd__go_i$44 \fus_cu_rd__go_i$56 connect \cu_rd__go_i$47 \fus_cu_rd__go_i$59 connect \cu_rd__go_i$54 \fus_cu_rd__go_i$66 connect \cu_rd__go_i$70 \fus_cu_rd__go_i$82 connect \cu_rd__rel_o \fus_cu_rd__rel_o connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$40 connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$43 connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$46 connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$49 connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$52 connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$55 connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$58 connect \cu_rd__rel_o$53 \fus_cu_rd__rel_o$65 connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$81 connect \cu_rdmaskn_i \fus_cu_rdmaskn_i connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$24 connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$27 connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$30 connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$33 connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$36 connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$39 connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$15 connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$18 connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$21 connect \cu_st__go_i \cu_st__go_i connect \cu_st__rel_o \cu_st__rel_o connect \cu_wr__go_i \fus_cu_wr__go_i connect \cu_wr__go_i$100 \fus_cu_wr__go_i$112 connect \cu_wr__go_i$102 \fus_cu_wr__go_i$114 connect \cu_wr__go_i$137 \fus_cu_wr__go_i$149 connect \cu_wr__go_i$82 \fus_cu_wr__go_i$94 connect \cu_wr__go_i$85 \fus_cu_wr__go_i$97 connect \cu_wr__go_i$88 \fus_cu_wr__go_i$100 connect \cu_wr__go_i$91 \fus_cu_wr__go_i$103 connect \cu_wr__go_i$94 \fus_cu_wr__go_i$106 connect \cu_wr__go_i$97 \fus_cu_wr__go_i$109 connect \cu_wr__rel_o \fus_cu_wr__rel_o connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$113 connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$148 connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$93 connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$96 connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$99 connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$102 connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$105 connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$108 connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$111 connect \dest1_o \fus_dest1_o connect \dest1_o$103 \fus_dest1_o$115 connect \dest1_o$104 \fus_dest1_o$116 connect \dest1_o$105 \fus_dest1_o$117 connect \dest1_o$106 \fus_dest1_o$118 connect \dest1_o$107 \fus_dest1_o$119 connect \dest1_o$108 \fus_dest1_o$120 connect \dest1_o$109 \fus_dest1_o$121 connect \dest1_o$141 \fus_dest1_o$153 connect \dest2_o \fus_dest2_o connect \dest2_o$115 \fus_dest2_o$127 connect \dest2_o$116 \fus_dest2_o$128 connect \dest2_o$117 \fus_dest2_o$129 connect \dest2_o$118 \fus_dest2_o$130 connect \dest2_o$119 \fus_dest2_o$131 connect \dest2_o$142 \fus_dest2_o$154 connect \dest2_o$144 \fus_dest2_o$156 connect \dest2_o$150 \fus_dest2_o$162 connect \dest3_o \fus_dest3_o connect \dest3_o$122 \fus_dest3_o$134 connect \dest3_o$123 \fus_dest3_o$135 connect \dest3_o$127 \fus_dest3_o$139 connect \dest3_o$128 \fus_dest3_o$140 connect \dest3_o$143 \fus_dest3_o$155 connect \dest3_o$145 \fus_dest3_o$157 connect \dest3_o$147 \fus_dest3_o$159 connect \dest4_o \fus_dest4_o connect \dest4_o$133 \fus_dest4_o$145 connect \dest4_o$134 \fus_dest4_o$146 connect \dest4_o$135 \fus_dest4_o$147 connect \dest4_o$148 \fus_dest4_o$160 connect \dest5_o \fus_dest5_o connect \dest5_o$132 \fus_dest5_o$144 connect \dest5_o$149 \fus_dest5_o$161 connect \dest6_o \fus_dest6_o connect \ea \fus_ea connect \fast1_ok \fus_fast1_ok connect \fast1_ok$138 \fus_fast1_ok$150 connect \fast1_ok$139 \fus_fast1_ok$151 connect \fast2_ok \fus_fast2_ok connect \fast2_ok$140 \fus_fast2_ok$152 connect \full_cr_ok \fus_full_cr_ok connect \ldst_port0_addr_i \fus_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \fus_ldst_port0_busy_o connect \ldst_port0_data_len \fus_ldst_port0_data_len connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$163 connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$164 connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$165 connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$166 connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$167 connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$168 connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$169 connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok connect \msr_ok \fus_msr_ok connect \nia_ok \fus_nia_ok connect \nia_ok$146 \fus_nia_ok$158 connect \o \fus_o connect \o_ok \fus_o_ok connect \o_ok$80 \fus_o_ok$92 connect \o_ok$83 \fus_o_ok$95 connect \o_ok$86 \fus_o_ok$98 connect \o_ok$89 \fus_o_ok$101 connect \o_ok$92 \fus_o_ok$104 connect \o_ok$95 \fus_o_ok$107 connect \o_ok$98 \fus_o_ok$110 connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type connect \oper_i_alu_shift_rot0__invert_in \fus_oper_i_alu_shift_rot0__invert_in connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit connect \oper_i_alu_trap0__ldst_exc \fus_oper_i_alu_trap0__ldst_exc connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a connect \spr1_ok \fus_spr1_ok connect \src1_i \fus_src1_i connect \src1_i$50 \fus_src1_i$62 connect \src1_i$51 \fus_src1_i$63 connect \src1_i$52 \fus_src1_i$64 connect \src1_i$55 \fus_src1_i$67 connect \src1_i$56 \fus_src1_i$68 connect \src1_i$57 \fus_src1_i$69 connect \src1_i$58 \fus_src1_i$70 connect \src1_i$59 \fus_src1_i$71 connect \src1_i$74 \fus_src1_i$86 connect \src2_i \fus_src2_i connect \src2_i$30 \fus_src2_i$42 connect \src2_i$33 \fus_src2_i$45 connect \src2_i$36 \fus_src2_i$48 connect \src2_i$39 \fus_src2_i$51 connect \src2_i$42 \fus_src2_i$54 connect \src2_i$45 \fus_src2_i$57 connect \src2_i$48 \fus_src2_i$60 connect \src2_i$77 \fus_src2_i$89 connect \src2_i$79 \fus_src2_i$91 connect \src3_i \fus_src3_i connect \src3_i$49 \fus_src3_i$61 connect \src3_i$60 \fus_src3_i$72 connect \src3_i$61 \fus_src3_i$73 connect \src3_i$62 \fus_src3_i$74 connect \src3_i$63 \fus_src3_i$75 connect \src3_i$67 \fus_src3_i$79 connect \src3_i$71 \fus_src3_i$83 connect \src3_i$75 \fus_src3_i$87 connect \src3_i$76 \fus_src3_i$88 connect \src4_i \fus_src4_i connect \src4_i$64 \fus_src4_i$76 connect \src4_i$65 \fus_src4_i$77 connect \src4_i$68 \fus_src4_i$80 connect \src4_i$78 \fus_src4_i$90 connect \src5_i \fus_src5_i connect \src5_i$66 \fus_src5_i$78 connect \src5_i$72 \fus_src5_i$84 connect \src6_i \fus_src6_i connect \src6_i$73 \fus_src6_i$85 connect \xer_ca_ok \fus_xer_ca_ok connect \xer_ca_ok$120 \fus_xer_ca_ok$132 connect \xer_ca_ok$121 \fus_xer_ca_ok$133 connect \xer_ov_ok \fus_xer_ov_ok connect \xer_ov_ok$124 \fus_xer_ov_ok$136 connect \xer_ov_ok$125 \fus_xer_ov_ok$137 connect \xer_ov_ok$126 \fus_xer_ov_ok$138 connect \xer_so_ok \fus_xer_so_ok connect \xer_so_ok$129 \fus_xer_so_ok$141 connect \xer_so_ok$130 \fus_xer_so_ok$142 connect \xer_so_ok$131 \fus_xer_so_ok$143 end attribute \module_not_derived 1 attribute \src "libresoc.v:43311.9-43323.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest1__addr \int_dest1__addr connect \dest1__data_i \int_dest1__data_i connect \dest1__wen \int_dest1__wen connect \dmi__addr \dmi__addr connect \dmi__data_o \dmi__data_o connect \dmi__ren \dmi__ren connect \src1__addr \int_src1__addr connect \src1__data_o \int_src1__data_o connect \src1__ren \int_src1__ren end attribute \module_not_derived 1 attribute \src "libresoc.v:43324.6-43356.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dbus__ack \dbus__ack connect \dbus__adr \dbus__adr connect \dbus__cyc \dbus__cyc connect \dbus__dat_r \dbus__dat_r connect \dbus__dat_w \dbus__dat_w connect \dbus__err \dbus__err connect \dbus__sel \dbus__sel connect \dbus__stb \dbus__stb connect \dbus__we \dbus__we connect \ldst_port0_addr_i \fus_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \fus_ldst_port0_busy_o connect \ldst_port0_data_len \fus_ldst_port0_data_len connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$163 connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$164 connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$165 connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$166 connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$167 connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$168 connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$169 connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 attribute \src "libresoc.v:43357.18-43361.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43362.18-43366.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43367.18-43371.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43372.21-43376.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43377.21-43381.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43382.19-43386.4" cell \rdpick_INT_rabc \rdpick_INT_rabc connect \en_o \rdpick_INT_rabc_en_o connect \i \rdpick_INT_rabc_i connect \o \rdpick_INT_rabc_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43387.19-43391.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43392.21-43396.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43397.21-43401.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43402.21-43406.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43407.7-43416.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \spr1__addr \spr_spr1__addr connect \spr1__addr$1 \spr_spr1__addr$175 connect \spr1__data_i \spr_spr1__data_i connect \spr1__data_o \spr_spr1__data_o connect \spr1__ren \spr_spr1__ren connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:43417.9-43434.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \data_i \data_i connect \data_i$2 \data_i$11 connect \data_i$3 \state_data_i connect \data_i$4 \state_data_i$174 connect \msr__data_o \msr__data_o connect \msr__ren \msr__ren connect \state_nia_wen \state_nia_wen connect \sv__data_o \sv__data_o connect \sv__ren \sv__ren connect \wen \wen connect \wen$1 \wen$10 connect \wen$5 \state_wen end attribute \module_not_derived 1 attribute \src "libresoc.v:43435.18-43439.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43440.21-43444.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43445.21-43449.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43450.16-43454.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43455.19-43459.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43460.20-43464.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43465.20-43469.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43470.21-43474.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43475.21-43479.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43480.21-43484.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 attribute \src "libresoc.v:43485.7-43502.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \data_i \xer_data_i connect \data_i$1 \xer_data_i$170 connect \data_i$3 \xer_data_i$172 connect \full_rd__data_o \full_rd__data_o connect \full_rd__ren \full_rd__ren connect \src1__data_o \xer_src1__data_o connect \src1__ren \xer_src1__ren connect \src2__data_o \xer_src2__data_o connect \src2__ren \xer_src2__ren connect \src3__data_o \xer_src3__data_o connect \src3__ren \xer_src3__ren connect \wen \xer_wen connect \wen$2 \xer_wen$171 connect \wen$4 \xer_wen$173 end attribute \src "libresoc.v:36262.7-36262.20" process $proc$libresoc.v:36262$2900 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:38103.7-38103.30" process $proc$libresoc.v:38103$2901 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end attribute \src "libresoc.v:38116.13-38116.27" process $proc$libresoc.v:38116$2902 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end attribute \src "libresoc.v:39283.7-39283.34" process $proc$libresoc.v:39283$2903 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end attribute \src "libresoc.v:39287.7-39287.30" process $proc$libresoc.v:39287$2904 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end attribute \src "libresoc.v:39291.7-39291.30" process $proc$libresoc.v:39291$2905 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end attribute \src "libresoc.v:39295.7-39295.30" process $proc$libresoc.v:39295$2906 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end attribute \src "libresoc.v:39299.7-39299.33" process $proc$libresoc.v:39299$2907 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end attribute \src "libresoc.v:39303.7-39303.37" process $proc$libresoc.v:39303$2908 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end attribute \src "libresoc.v:39307.7-39307.37" process $proc$libresoc.v:39307$2909 assign { } { } assign $1\dp_FAST_fast1_branch0_3[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_3 $1\dp_FAST_fast1_branch0_3[0:0] end attribute \src "libresoc.v:39311.7-39311.34" process $proc$libresoc.v:39311$2910 assign { } { } assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end attribute \src "libresoc.v:39315.7-39315.35" process $proc$libresoc.v:39315$2911 assign { } { } assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end attribute \src "libresoc.v:39319.7-39319.35" process $proc$libresoc.v:39319$2912 assign { } { } assign $1\dp_FAST_fast1_trap0_4[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_4 $1\dp_FAST_fast1_trap0_4[0:0] end attribute \src "libresoc.v:39323.7-39323.32" process $proc$libresoc.v:39323$2913 assign { } { } assign $1\dp_INT_rabc_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_rabc_alu0_0 $1\dp_INT_rabc_alu0_0[0:0] end attribute \src "libresoc.v:39327.7-39327.33" process $proc$libresoc.v:39327$2914 assign { } { } assign $1\dp_INT_rabc_alu0_10[0:0] 1'0 sync always sync init update \dp_INT_rabc_alu0_10 $1\dp_INT_rabc_alu0_10[0:0] end attribute \src "libresoc.v:39331.7-39331.31" process $proc$libresoc.v:39331$2915 assign { } { } assign $1\dp_INT_rabc_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_rabc_cr0_1 $1\dp_INT_rabc_cr0_1[0:0] end attribute \src "libresoc.v:39335.7-39335.32" process $proc$libresoc.v:39335$2916 assign { } { } assign $1\dp_INT_rabc_cr0_11[0:0] 1'0 sync always sync init update \dp_INT_rabc_cr0_11 $1\dp_INT_rabc_cr0_11[0:0] end attribute \src "libresoc.v:39339.7-39339.33" process $proc$libresoc.v:39339$2917 assign { } { } assign $1\dp_INT_rabc_div0_15[0:0] 1'0 sync always sync init update \dp_INT_rabc_div0_15 $1\dp_INT_rabc_div0_15[0:0] end attribute \src "libresoc.v:39343.7-39343.32" process $proc$libresoc.v:39343$2918 assign { } { } assign $1\dp_INT_rabc_div0_4[0:0] 1'0 sync always sync init update \dp_INT_rabc_div0_4 $1\dp_INT_rabc_div0_4[0:0] end attribute \src "libresoc.v:39347.7-39347.34" process $proc$libresoc.v:39347$2919 assign { } { } assign $1\dp_INT_rabc_ldst0_18[0:0] 1'0 sync always sync init update \dp_INT_rabc_ldst0_18 $1\dp_INT_rabc_ldst0_18[0:0] end attribute \src "libresoc.v:39351.7-39351.33" process $proc$libresoc.v:39351$2920 assign { } { } assign $1\dp_INT_rabc_ldst0_7[0:0] 1'0 sync always sync init update \dp_INT_rabc_ldst0_7 $1\dp_INT_rabc_ldst0_7[0:0] end attribute \src "libresoc.v:39355.7-39355.33" process $proc$libresoc.v:39355$2921 assign { } { } assign $1\dp_INT_rabc_ldst0_9[0:0] 1'0 sync always sync init update \dp_INT_rabc_ldst0_9 $1\dp_INT_rabc_ldst0_9[0:0] end attribute \src "libresoc.v:39359.7-39359.37" process $proc$libresoc.v:39359$2922 assign { } { } assign $1\dp_INT_rabc_logical0_13[0:0] 1'0 sync always sync init update \dp_INT_rabc_logical0_13 $1\dp_INT_rabc_logical0_13[0:0] end attribute \src "libresoc.v:39363.7-39363.36" process $proc$libresoc.v:39363$2923 assign { } { } assign $1\dp_INT_rabc_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_rabc_logical0_3 $1\dp_INT_rabc_logical0_3[0:0] end attribute \src "libresoc.v:39367.7-39367.33" process $proc$libresoc.v:39367$2924 assign { } { } assign $1\dp_INT_rabc_mul0_16[0:0] 1'0 sync always sync init update \dp_INT_rabc_mul0_16 $1\dp_INT_rabc_mul0_16[0:0] end attribute \src "libresoc.v:39371.7-39371.32" process $proc$libresoc.v:39371$2925 assign { } { } assign $1\dp_INT_rabc_mul0_5[0:0] 1'0 sync always sync init update \dp_INT_rabc_mul0_5 $1\dp_INT_rabc_mul0_5[0:0] end attribute \src "libresoc.v:39375.7-39375.38" process $proc$libresoc.v:39375$2926 assign { } { } assign $1\dp_INT_rabc_shiftrot0_17[0:0] 1'0 sync always sync init update \dp_INT_rabc_shiftrot0_17 $1\dp_INT_rabc_shiftrot0_17[0:0] end attribute \src "libresoc.v:39379.7-39379.37" process $proc$libresoc.v:39379$2927 assign { } { } assign $1\dp_INT_rabc_shiftrot0_6[0:0] 1'0 sync always sync init update \dp_INT_rabc_shiftrot0_6 $1\dp_INT_rabc_shiftrot0_6[0:0] end attribute \src "libresoc.v:39383.7-39383.37" process $proc$libresoc.v:39383$2928 assign { } { } assign $1\dp_INT_rabc_shiftrot0_8[0:0] 1'0 sync always sync init update \dp_INT_rabc_shiftrot0_8 $1\dp_INT_rabc_shiftrot0_8[0:0] end attribute \src "libresoc.v:39387.7-39387.33" process $proc$libresoc.v:39387$2929 assign { } { } assign $1\dp_INT_rabc_spr0_14[0:0] 1'0 sync always sync init update \dp_INT_rabc_spr0_14 $1\dp_INT_rabc_spr0_14[0:0] end attribute \src "libresoc.v:39391.7-39391.34" process $proc$libresoc.v:39391$2930 assign { } { } assign $1\dp_INT_rabc_trap0_12[0:0] 1'0 sync always sync init update \dp_INT_rabc_trap0_12 $1\dp_INT_rabc_trap0_12[0:0] end attribute \src "libresoc.v:39395.7-39395.33" process $proc$libresoc.v:39395$2931 assign { } { } assign $1\dp_INT_rabc_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_rabc_trap0_2 $1\dp_INT_rabc_trap0_2[0:0] end attribute \src "libresoc.v:39399.7-39399.32" process $proc$libresoc.v:39399$2932 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end attribute \src "libresoc.v:39403.7-39403.34" process $proc$libresoc.v:39403$2933 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end attribute \src "libresoc.v:39407.7-39407.39" process $proc$libresoc.v:39407$2934 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end attribute \src "libresoc.v:39411.7-39411.34" process $proc$libresoc.v:39411$2935 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end attribute \src "libresoc.v:39415.7-39415.34" process $proc$libresoc.v:39415$2936 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end attribute \src "libresoc.v:39419.7-39419.34" process $proc$libresoc.v:39419$2937 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end attribute \src "libresoc.v:39423.7-39423.34" process $proc$libresoc.v:39423$2938 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end attribute \src "libresoc.v:39427.7-39427.38" process $proc$libresoc.v:39427$2939 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end attribute \src "libresoc.v:39431.7-39431.34" process $proc$libresoc.v:39431$2940 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end attribute \src "libresoc.v:39435.7-39435.39" process $proc$libresoc.v:39435$2941 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end attribute \src "libresoc.v:39439.7-39439.34" process $proc$libresoc.v:39439$2942 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end attribute \src "libresoc.v:41528.7-41528.25" process $proc$libresoc.v:41528$2943 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end attribute \src "libresoc.v:41530.7-41530.32" process $proc$libresoc.v:41530$2944 assign { } { } assign $0\wr_pick_dly$1008[0:0]$2945 1'0 sync always sync init update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2945 end attribute \src "libresoc.v:41534.7-41534.32" process $proc$libresoc.v:41534$2946 assign { } { } assign $0\wr_pick_dly$1029[0:0]$2947 1'0 sync always sync init update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2947 end attribute \src "libresoc.v:41538.7-41538.32" process $proc$libresoc.v:41538$2948 assign { } { } assign $0\wr_pick_dly$1047[0:0]$2949 1'0 sync always sync init update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2949 end attribute \src "libresoc.v:41542.7-41542.32" process $proc$libresoc.v:41542$2950 assign { } { } assign $0\wr_pick_dly$1069[0:0]$2951 1'0 sync always sync init update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2951 end attribute \src "libresoc.v:41546.7-41546.32" process $proc$libresoc.v:41546$2952 assign { } { } assign $0\wr_pick_dly$1089[0:0]$2953 1'0 sync always sync init update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2953 end attribute \src "libresoc.v:41550.7-41550.32" process $proc$libresoc.v:41550$2954 assign { } { } assign $0\wr_pick_dly$1109[0:0]$2955 1'0 sync always sync init update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2955 end attribute \src "libresoc.v:41554.7-41554.32" process $proc$libresoc.v:41554$2956 assign { } { } assign $0\wr_pick_dly$1128[0:0]$2957 1'0 sync always sync init update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2957 end attribute \src "libresoc.v:41558.7-41558.32" process $proc$libresoc.v:41558$2958 assign { } { } assign $0\wr_pick_dly$1146[0:0]$2959 1'0 sync always sync init update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2959 end attribute \src "libresoc.v:41562.7-41562.32" process $proc$libresoc.v:41562$2960 assign { } { } assign $0\wr_pick_dly$1220[0:0]$2961 1'0 sync always sync init update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2961 end attribute \src "libresoc.v:41566.7-41566.32" process $proc$libresoc.v:41566$2962 assign { } { } assign $0\wr_pick_dly$1248[0:0]$2963 1'0 sync always sync init update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2963 end attribute \src "libresoc.v:41570.7-41570.32" process $proc$libresoc.v:41570$2964 assign { } { } assign $0\wr_pick_dly$1268[0:0]$2965 1'0 sync always sync init update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2965 end attribute \src "libresoc.v:41574.7-41574.32" process $proc$libresoc.v:41574$2966 assign { } { } assign $0\wr_pick_dly$1288[0:0]$2967 1'0 sync always sync init update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2967 end attribute \src "libresoc.v:41578.7-41578.32" process $proc$libresoc.v:41578$2968 assign { } { } assign $0\wr_pick_dly$1308[0:0]$2969 1'0 sync always sync init update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2969 end attribute \src "libresoc.v:41582.7-41582.32" process $proc$libresoc.v:41582$2970 assign { } { } assign $0\wr_pick_dly$1328[0:0]$2971 1'0 sync always sync init update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2971 end attribute \src "libresoc.v:41586.7-41586.32" process $proc$libresoc.v:41586$2972 assign { } { } assign $0\wr_pick_dly$1348[0:0]$2973 1'0 sync always sync init update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2973 end attribute \src "libresoc.v:41590.7-41590.32" process $proc$libresoc.v:41590$2974 assign { } { } assign $0\wr_pick_dly$1395[0:0]$2975 1'0 sync always sync init update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2975 end attribute \src "libresoc.v:41594.7-41594.32" process $proc$libresoc.v:41594$2976 assign { } { } assign $0\wr_pick_dly$1411[0:0]$2977 1'0 sync always sync init update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2977 end attribute \src "libresoc.v:41598.7-41598.32" process $proc$libresoc.v:41598$2978 assign { } { } assign $0\wr_pick_dly$1427[0:0]$2979 1'0 sync always sync init update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2979 end attribute \src "libresoc.v:41602.7-41602.32" process $proc$libresoc.v:41602$2980 assign { } { } assign $0\wr_pick_dly$1461[0:0]$2981 1'0 sync always sync init update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2981 end attribute \src "libresoc.v:41606.7-41606.32" process $proc$libresoc.v:41606$2982 assign { } { } assign $0\wr_pick_dly$1477[0:0]$2983 1'0 sync always sync init update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2983 end attribute \src "libresoc.v:41610.7-41610.32" process $proc$libresoc.v:41610$2984 assign { } { } assign $0\wr_pick_dly$1493[0:0]$2985 1'0 sync always sync init update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2985 end attribute \src "libresoc.v:41614.7-41614.32" process $proc$libresoc.v:41614$2986 assign { } { } assign $0\wr_pick_dly$1509[0:0]$2987 1'0 sync always sync init update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2987 end attribute \src "libresoc.v:41618.7-41618.32" process $proc$libresoc.v:41618$2988 assign { } { } assign $0\wr_pick_dly$1545[0:0]$2989 1'0 sync always sync init update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2989 end attribute \src "libresoc.v:41622.7-41622.32" process $proc$libresoc.v:41622$2990 assign { } { } assign $0\wr_pick_dly$1561[0:0]$2991 1'0 sync always sync init update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2991 end attribute \src "libresoc.v:41626.7-41626.32" process $proc$libresoc.v:41626$2992 assign { } { } assign $0\wr_pick_dly$1577[0:0]$2993 1'0 sync always sync init update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2993 end attribute \src "libresoc.v:41630.7-41630.32" process $proc$libresoc.v:41630$2994 assign { } { } assign $0\wr_pick_dly$1593[0:0]$2995 1'0 sync always sync init update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2995 end attribute \src "libresoc.v:41634.7-41634.32" process $proc$libresoc.v:41634$2996 assign { } { } assign $0\wr_pick_dly$1635[0:0]$2997 1'0 sync always sync init update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2997 end attribute \src "libresoc.v:41638.7-41638.32" process $proc$libresoc.v:41638$2998 assign { } { } assign $0\wr_pick_dly$1654[0:0]$2999 1'0 sync always sync init update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2999 end attribute \src "libresoc.v:41642.7-41642.32" process $proc$libresoc.v:41642$3000 assign { } { } assign $0\wr_pick_dly$1670[0:0]$3001 1'0 sync always sync init update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$3001 end attribute \src "libresoc.v:41646.7-41646.32" process $proc$libresoc.v:41646$3002 assign { } { } assign $0\wr_pick_dly$1686[0:0]$3003 1'0 sync always sync init update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$3003 end attribute \src "libresoc.v:41650.7-41650.32" process $proc$libresoc.v:41650$3004 assign { } { } assign $0\wr_pick_dly$1702[0:0]$3005 1'0 sync always sync init update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$3005 end attribute \src "libresoc.v:41654.7-41654.32" process $proc$libresoc.v:41654$3006 assign { } { } assign $0\wr_pick_dly$1746[0:0]$3007 1'0 sync always sync init update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$3007 end attribute \src "libresoc.v:41658.7-41658.32" process $proc$libresoc.v:41658$3008 assign { } { } assign $0\wr_pick_dly$1762[0:0]$3009 1'0 sync always sync init update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$3009 end attribute \src "libresoc.v:41662.7-41662.32" process $proc$libresoc.v:41662$3010 assign { } { } assign $0\wr_pick_dly$1786[0:0]$3011 1'0 sync always sync init update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$3011 end attribute \src "libresoc.v:41666.7-41666.32" process $proc$libresoc.v:41666$3012 assign { } { } assign $0\wr_pick_dly$1806[0:0]$3013 1'0 sync always sync init update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$3013 end attribute \src "libresoc.v:41670.7-41670.31" process $proc$libresoc.v:41670$3014 assign { } { } assign $0\wr_pick_dly$989[0:0]$3015 1'0 sync always sync init update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$3015 end attribute \src "libresoc.v:42632.3-42633.51" process $proc$libresoc.v:42632$2238 assign { } { } assign $0\wr_pick_dly$1806[0:0]$2239 \wr_pick_dly$1806$next sync posedge \coresync_clk update \wr_pick_dly$1806 $0\wr_pick_dly$1806[0:0]$2239 end attribute \src "libresoc.v:42634.3-42635.51" process $proc$libresoc.v:42634$2240 assign { } { } assign $0\wr_pick_dly$1786[0:0]$2241 \wr_pick_dly$1786$next sync posedge \coresync_clk update \wr_pick_dly$1786 $0\wr_pick_dly$1786[0:0]$2241 end attribute \src "libresoc.v:42636.3-42637.51" process $proc$libresoc.v:42636$2242 assign { } { } assign $0\wr_pick_dly$1762[0:0]$2243 \wr_pick_dly$1762$next sync posedge \coresync_clk update \wr_pick_dly$1762 $0\wr_pick_dly$1762[0:0]$2243 end attribute \src "libresoc.v:42638.3-42639.51" process $proc$libresoc.v:42638$2244 assign { } { } assign $0\wr_pick_dly$1746[0:0]$2245 \wr_pick_dly$1746$next sync posedge \coresync_clk update \wr_pick_dly$1746 $0\wr_pick_dly$1746[0:0]$2245 end attribute \src "libresoc.v:42640.3-42641.51" process $proc$libresoc.v:42640$2246 assign { } { } assign $0\wr_pick_dly$1702[0:0]$2247 \wr_pick_dly$1702$next sync posedge \coresync_clk update \wr_pick_dly$1702 $0\wr_pick_dly$1702[0:0]$2247 end attribute \src "libresoc.v:42642.3-42643.51" process $proc$libresoc.v:42642$2248 assign { } { } assign $0\wr_pick_dly$1686[0:0]$2249 \wr_pick_dly$1686$next sync posedge \coresync_clk update \wr_pick_dly$1686 $0\wr_pick_dly$1686[0:0]$2249 end attribute \src "libresoc.v:42644.3-42645.51" process $proc$libresoc.v:42644$2250 assign { } { } assign $0\wr_pick_dly$1670[0:0]$2251 \wr_pick_dly$1670$next sync posedge \coresync_clk update \wr_pick_dly$1670 $0\wr_pick_dly$1670[0:0]$2251 end attribute \src "libresoc.v:42646.3-42647.51" process $proc$libresoc.v:42646$2252 assign { } { } assign $0\wr_pick_dly$1654[0:0]$2253 \wr_pick_dly$1654$next sync posedge \coresync_clk update \wr_pick_dly$1654 $0\wr_pick_dly$1654[0:0]$2253 end attribute \src "libresoc.v:42648.3-42649.51" process $proc$libresoc.v:42648$2254 assign { } { } assign $0\wr_pick_dly$1635[0:0]$2255 \wr_pick_dly$1635$next sync posedge \coresync_clk update \wr_pick_dly$1635 $0\wr_pick_dly$1635[0:0]$2255 end attribute \src "libresoc.v:42650.3-42651.51" process $proc$libresoc.v:42650$2256 assign { } { } assign $0\wr_pick_dly$1593[0:0]$2257 \wr_pick_dly$1593$next sync posedge \coresync_clk update \wr_pick_dly$1593 $0\wr_pick_dly$1593[0:0]$2257 end attribute \src "libresoc.v:42652.3-42653.51" process $proc$libresoc.v:42652$2258 assign { } { } assign $0\wr_pick_dly$1577[0:0]$2259 \wr_pick_dly$1577$next sync posedge \coresync_clk update \wr_pick_dly$1577 $0\wr_pick_dly$1577[0:0]$2259 end attribute \src "libresoc.v:42654.3-42655.51" process $proc$libresoc.v:42654$2260 assign { } { } assign $0\wr_pick_dly$1561[0:0]$2261 \wr_pick_dly$1561$next sync posedge \coresync_clk update \wr_pick_dly$1561 $0\wr_pick_dly$1561[0:0]$2261 end attribute \src "libresoc.v:42656.3-42657.51" process $proc$libresoc.v:42656$2262 assign { } { } assign $0\wr_pick_dly$1545[0:0]$2263 \wr_pick_dly$1545$next sync posedge \coresync_clk update \wr_pick_dly$1545 $0\wr_pick_dly$1545[0:0]$2263 end attribute \src "libresoc.v:42658.3-42659.51" process $proc$libresoc.v:42658$2264 assign { } { } assign $0\wr_pick_dly$1509[0:0]$2265 \wr_pick_dly$1509$next sync posedge \coresync_clk update \wr_pick_dly$1509 $0\wr_pick_dly$1509[0:0]$2265 end attribute \src "libresoc.v:42660.3-42661.51" process $proc$libresoc.v:42660$2266 assign { } { } assign $0\wr_pick_dly$1493[0:0]$2267 \wr_pick_dly$1493$next sync posedge \coresync_clk update \wr_pick_dly$1493 $0\wr_pick_dly$1493[0:0]$2267 end attribute \src "libresoc.v:42662.3-42663.51" process $proc$libresoc.v:42662$2268 assign { } { } assign $0\wr_pick_dly$1477[0:0]$2269 \wr_pick_dly$1477$next sync posedge \coresync_clk update \wr_pick_dly$1477 $0\wr_pick_dly$1477[0:0]$2269 end attribute \src "libresoc.v:42664.3-42665.51" process $proc$libresoc.v:42664$2270 assign { } { } assign $0\wr_pick_dly$1461[0:0]$2271 \wr_pick_dly$1461$next sync posedge \coresync_clk update \wr_pick_dly$1461 $0\wr_pick_dly$1461[0:0]$2271 end attribute \src "libresoc.v:42666.3-42667.51" process $proc$libresoc.v:42666$2272 assign { } { } assign $0\wr_pick_dly$1427[0:0]$2273 \wr_pick_dly$1427$next sync posedge \coresync_clk update \wr_pick_dly$1427 $0\wr_pick_dly$1427[0:0]$2273 end attribute \src "libresoc.v:42668.3-42669.51" process $proc$libresoc.v:42668$2274 assign { } { } assign $0\wr_pick_dly$1411[0:0]$2275 \wr_pick_dly$1411$next sync posedge \coresync_clk update \wr_pick_dly$1411 $0\wr_pick_dly$1411[0:0]$2275 end attribute \src "libresoc.v:42670.3-42671.51" process $proc$libresoc.v:42670$2276 assign { } { } assign $0\wr_pick_dly$1395[0:0]$2277 \wr_pick_dly$1395$next sync posedge \coresync_clk update \wr_pick_dly$1395 $0\wr_pick_dly$1395[0:0]$2277 end attribute \src "libresoc.v:42672.3-42673.51" process $proc$libresoc.v:42672$2278 assign { } { } assign $0\wr_pick_dly$1348[0:0]$2279 \wr_pick_dly$1348$next sync posedge \coresync_clk update \wr_pick_dly$1348 $0\wr_pick_dly$1348[0:0]$2279 end attribute \src "libresoc.v:42674.3-42675.51" process $proc$libresoc.v:42674$2280 assign { } { } assign $0\wr_pick_dly$1328[0:0]$2281 \wr_pick_dly$1328$next sync posedge \coresync_clk update \wr_pick_dly$1328 $0\wr_pick_dly$1328[0:0]$2281 end attribute \src "libresoc.v:42676.3-42677.51" process $proc$libresoc.v:42676$2282 assign { } { } assign $0\wr_pick_dly$1308[0:0]$2283 \wr_pick_dly$1308$next sync posedge \coresync_clk update \wr_pick_dly$1308 $0\wr_pick_dly$1308[0:0]$2283 end attribute \src "libresoc.v:42678.3-42679.51" process $proc$libresoc.v:42678$2284 assign { } { } assign $0\wr_pick_dly$1288[0:0]$2285 \wr_pick_dly$1288$next sync posedge \coresync_clk update \wr_pick_dly$1288 $0\wr_pick_dly$1288[0:0]$2285 end attribute \src "libresoc.v:42680.3-42681.51" process $proc$libresoc.v:42680$2286 assign { } { } assign $0\wr_pick_dly$1268[0:0]$2287 \wr_pick_dly$1268$next sync posedge \coresync_clk update \wr_pick_dly$1268 $0\wr_pick_dly$1268[0:0]$2287 end attribute \src "libresoc.v:42682.3-42683.51" process $proc$libresoc.v:42682$2288 assign { } { } assign $0\wr_pick_dly$1248[0:0]$2289 \wr_pick_dly$1248$next sync posedge \coresync_clk update \wr_pick_dly$1248 $0\wr_pick_dly$1248[0:0]$2289 end attribute \src "libresoc.v:42684.3-42685.51" process $proc$libresoc.v:42684$2290 assign { } { } assign $0\wr_pick_dly$1220[0:0]$2291 \wr_pick_dly$1220$next sync posedge \coresync_clk update \wr_pick_dly$1220 $0\wr_pick_dly$1220[0:0]$2291 end attribute \src "libresoc.v:42686.3-42687.51" process $proc$libresoc.v:42686$2292 assign { } { } assign $0\wr_pick_dly$1146[0:0]$2293 \wr_pick_dly$1146$next sync posedge \coresync_clk update \wr_pick_dly$1146 $0\wr_pick_dly$1146[0:0]$2293 end attribute \src "libresoc.v:42688.3-42689.51" process $proc$libresoc.v:42688$2294 assign { } { } assign $0\wr_pick_dly$1128[0:0]$2295 \wr_pick_dly$1128$next sync posedge \coresync_clk update \wr_pick_dly$1128 $0\wr_pick_dly$1128[0:0]$2295 end attribute \src "libresoc.v:42690.3-42691.51" process $proc$libresoc.v:42690$2296 assign { } { } assign $0\wr_pick_dly$1109[0:0]$2297 \wr_pick_dly$1109$next sync posedge \coresync_clk update \wr_pick_dly$1109 $0\wr_pick_dly$1109[0:0]$2297 end attribute \src "libresoc.v:42692.3-42693.51" process $proc$libresoc.v:42692$2298 assign { } { } assign $0\wr_pick_dly$1089[0:0]$2299 \wr_pick_dly$1089$next sync posedge \coresync_clk update \wr_pick_dly$1089 $0\wr_pick_dly$1089[0:0]$2299 end attribute \src "libresoc.v:42694.3-42695.51" process $proc$libresoc.v:42694$2300 assign { } { } assign $0\wr_pick_dly$1069[0:0]$2301 \wr_pick_dly$1069$next sync posedge \coresync_clk update \wr_pick_dly$1069 $0\wr_pick_dly$1069[0:0]$2301 end attribute \src "libresoc.v:42696.3-42697.51" process $proc$libresoc.v:42696$2302 assign { } { } assign $0\wr_pick_dly$1047[0:0]$2303 \wr_pick_dly$1047$next sync posedge \coresync_clk update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2303 end attribute \src "libresoc.v:42698.3-42699.51" process $proc$libresoc.v:42698$2304 assign { } { } assign $0\wr_pick_dly$1029[0:0]$2305 \wr_pick_dly$1029$next sync posedge \coresync_clk update \wr_pick_dly$1029 $0\wr_pick_dly$1029[0:0]$2305 end attribute \src "libresoc.v:42700.3-42701.51" process $proc$libresoc.v:42700$2306 assign { } { } assign $0\wr_pick_dly$1008[0:0]$2307 \wr_pick_dly$1008$next sync posedge \coresync_clk update \wr_pick_dly$1008 $0\wr_pick_dly$1008[0:0]$2307 end attribute \src "libresoc.v:42702.3-42703.49" process $proc$libresoc.v:42702$2308 assign { } { } assign $0\wr_pick_dly$989[0:0]$2309 \wr_pick_dly$989$next sync posedge \coresync_clk update \wr_pick_dly$989 $0\wr_pick_dly$989[0:0]$2309 end attribute \src "libresoc.v:42704.3-42705.39" process $proc$libresoc.v:42704$2310 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end attribute \src "libresoc.v:42706.3-42707.53" process $proc$libresoc.v:42706$2311 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end attribute \src "libresoc.v:42708.3-42709.59" process $proc$libresoc.v:42708$2312 assign { } { } assign $0\dp_FAST_fast1_trap0_4[0:0] \dp_FAST_fast1_trap0_4$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_4 $0\dp_FAST_fast1_trap0_4[0:0] end attribute \src "libresoc.v:42710.3-42711.63" process $proc$libresoc.v:42710$2313 assign { } { } assign $0\dp_FAST_fast1_branch0_3[0:0] \dp_FAST_fast1_branch0_3$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_3 $0\dp_FAST_fast1_branch0_3[0:0] end attribute \src "libresoc.v:42712.3-42713.57" process $proc$libresoc.v:42712$2314 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end attribute \src "libresoc.v:42714.3-42715.59" process $proc$libresoc.v:42714$2315 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end attribute \src "libresoc.v:42716.3-42717.63" process $proc$libresoc.v:42716$2316 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end attribute \src "libresoc.v:42718.3-42719.49" process $proc$libresoc.v:42718$2317 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end attribute \src "libresoc.v:42720.3-42721.49" process $proc$libresoc.v:42720$2318 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end attribute \src "libresoc.v:42722.3-42723.57" process $proc$libresoc.v:42722$2319 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end attribute \src "libresoc.v:42724.3-42725.49" process $proc$libresoc.v:42724$2320 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end attribute \src "libresoc.v:42726.3-42727.55" process $proc$libresoc.v:42726$2321 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end attribute \src "libresoc.v:42728.3-42729.57" process $proc$libresoc.v:42728$2322 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end attribute \src "libresoc.v:42730.3-42731.67" process $proc$libresoc.v:42730$2323 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end attribute \src "libresoc.v:42732.3-42733.57" process $proc$libresoc.v:42732$2324 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end attribute \src "libresoc.v:42734.3-42735.57" process $proc$libresoc.v:42734$2325 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end attribute \src "libresoc.v:42736.3-42737.67" process $proc$libresoc.v:42736$2326 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end attribute \src "libresoc.v:42738.3-42739.57" process $proc$libresoc.v:42738$2327 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end attribute \src "libresoc.v:42740.3-42741.57" process $proc$libresoc.v:42740$2328 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end attribute \src "libresoc.v:42742.3-42743.57" process $proc$libresoc.v:42742$2329 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end attribute \src "libresoc.v:42744.3-42745.65" process $proc$libresoc.v:42744$2330 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end attribute \src "libresoc.v:42746.3-42747.57" process $proc$libresoc.v:42746$2331 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end attribute \src "libresoc.v:42748.3-42749.57" process $proc$libresoc.v:42748$2332 assign { } { } assign $0\dp_INT_rabc_ldst0_18[0:0] \dp_INT_rabc_ldst0_18$next sync posedge \coresync_clk update \dp_INT_rabc_ldst0_18 $0\dp_INT_rabc_ldst0_18[0:0] end attribute \src "libresoc.v:42750.3-42751.65" process $proc$libresoc.v:42750$2333 assign { } { } assign $0\dp_INT_rabc_shiftrot0_17[0:0] \dp_INT_rabc_shiftrot0_17$next sync posedge \coresync_clk update \dp_INT_rabc_shiftrot0_17 $0\dp_INT_rabc_shiftrot0_17[0:0] end attribute \src "libresoc.v:42752.3-42753.55" process $proc$libresoc.v:42752$2334 assign { } { } assign $0\dp_INT_rabc_mul0_16[0:0] \dp_INT_rabc_mul0_16$next sync posedge \coresync_clk update \dp_INT_rabc_mul0_16 $0\dp_INT_rabc_mul0_16[0:0] end attribute \src "libresoc.v:42754.3-42755.55" process $proc$libresoc.v:42754$2335 assign { } { } assign $0\dp_INT_rabc_div0_15[0:0] \dp_INT_rabc_div0_15$next sync posedge \coresync_clk update \dp_INT_rabc_div0_15 $0\dp_INT_rabc_div0_15[0:0] end attribute \src "libresoc.v:42756.3-42757.55" process $proc$libresoc.v:42756$2336 assign { } { } assign $0\dp_INT_rabc_spr0_14[0:0] \dp_INT_rabc_spr0_14$next sync posedge \coresync_clk update \dp_INT_rabc_spr0_14 $0\dp_INT_rabc_spr0_14[0:0] end attribute \src "libresoc.v:42758.3-42759.63" process $proc$libresoc.v:42758$2337 assign { } { } assign $0\dp_INT_rabc_logical0_13[0:0] \dp_INT_rabc_logical0_13$next sync posedge \coresync_clk update \dp_INT_rabc_logical0_13 $0\dp_INT_rabc_logical0_13[0:0] end attribute \src "libresoc.v:42760.3-42761.57" process $proc$libresoc.v:42760$2338 assign { } { } assign $0\dp_INT_rabc_trap0_12[0:0] \dp_INT_rabc_trap0_12$next sync posedge \coresync_clk update \dp_INT_rabc_trap0_12 $0\dp_INT_rabc_trap0_12[0:0] end attribute \src "libresoc.v:42762.3-42763.53" process $proc$libresoc.v:42762$2339 assign { } { } assign $0\dp_INT_rabc_cr0_11[0:0] \dp_INT_rabc_cr0_11$next sync posedge \coresync_clk update \dp_INT_rabc_cr0_11 $0\dp_INT_rabc_cr0_11[0:0] end attribute \src "libresoc.v:42764.3-42765.55" process $proc$libresoc.v:42764$2340 assign { } { } assign $0\dp_INT_rabc_alu0_10[0:0] \dp_INT_rabc_alu0_10$next sync posedge \coresync_clk update \dp_INT_rabc_alu0_10 $0\dp_INT_rabc_alu0_10[0:0] end attribute \src "libresoc.v:42766.3-42767.55" process $proc$libresoc.v:42766$2341 assign { } { } assign $0\dp_INT_rabc_ldst0_9[0:0] \dp_INT_rabc_ldst0_9$next sync posedge \coresync_clk update \dp_INT_rabc_ldst0_9 $0\dp_INT_rabc_ldst0_9[0:0] end attribute \src "libresoc.v:42768.3-42769.63" process $proc$libresoc.v:42768$2342 assign { } { } assign $0\dp_INT_rabc_shiftrot0_8[0:0] \dp_INT_rabc_shiftrot0_8$next sync posedge \coresync_clk update \dp_INT_rabc_shiftrot0_8 $0\dp_INT_rabc_shiftrot0_8[0:0] end attribute \src "libresoc.v:42770.3-42771.55" process $proc$libresoc.v:42770$2343 assign { } { } assign $0\dp_INT_rabc_ldst0_7[0:0] \dp_INT_rabc_ldst0_7$next sync posedge \coresync_clk update \dp_INT_rabc_ldst0_7 $0\dp_INT_rabc_ldst0_7[0:0] end attribute \src "libresoc.v:42772.3-42773.63" process $proc$libresoc.v:42772$2344 assign { } { } assign $0\dp_INT_rabc_shiftrot0_6[0:0] \dp_INT_rabc_shiftrot0_6$next sync posedge \coresync_clk update \dp_INT_rabc_shiftrot0_6 $0\dp_INT_rabc_shiftrot0_6[0:0] end attribute \src "libresoc.v:42774.3-42775.53" process $proc$libresoc.v:42774$2345 assign { } { } assign $0\dp_INT_rabc_mul0_5[0:0] \dp_INT_rabc_mul0_5$next sync posedge \coresync_clk update \dp_INT_rabc_mul0_5 $0\dp_INT_rabc_mul0_5[0:0] end attribute \src "libresoc.v:42776.3-42777.53" process $proc$libresoc.v:42776$2346 assign { } { } assign $0\dp_INT_rabc_div0_4[0:0] \dp_INT_rabc_div0_4$next sync posedge \coresync_clk update \dp_INT_rabc_div0_4 $0\dp_INT_rabc_div0_4[0:0] end attribute \src "libresoc.v:42778.3-42779.61" process $proc$libresoc.v:42778$2347 assign { } { } assign $0\dp_INT_rabc_logical0_3[0:0] \dp_INT_rabc_logical0_3$next sync posedge \coresync_clk update \dp_INT_rabc_logical0_3 $0\dp_INT_rabc_logical0_3[0:0] end attribute \src "libresoc.v:42780.3-42781.55" process $proc$libresoc.v:42780$2348 assign { } { } assign $0\dp_INT_rabc_trap0_2[0:0] \dp_INT_rabc_trap0_2$next sync posedge \coresync_clk update \dp_INT_rabc_trap0_2 $0\dp_INT_rabc_trap0_2[0:0] end attribute \src "libresoc.v:42782.3-42783.51" process $proc$libresoc.v:42782$2349 assign { } { } assign $0\dp_INT_rabc_cr0_1[0:0] \dp_INT_rabc_cr0_1$next sync posedge \coresync_clk update \dp_INT_rabc_cr0_1 $0\dp_INT_rabc_cr0_1[0:0] end attribute \src "libresoc.v:42784.3-42785.53" process $proc$libresoc.v:42784$2350 assign { } { } assign $0\dp_INT_rabc_alu0_0[0:0] \dp_INT_rabc_alu0_0$next sync posedge \coresync_clk update \dp_INT_rabc_alu0_0 $0\dp_INT_rabc_alu0_0[0:0] end attribute \src "libresoc.v:42786.3-42787.49" process $proc$libresoc.v:42786$2351 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end attribute \src "libresoc.v:42788.3-42789.31" process $proc$libresoc.v:42788$2352 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end attribute \src "libresoc.v:43503.3-43531.6" process $proc$libresoc.v:43503$2353 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] attribute \src "libresoc.v:43504.5-43504.29" switch \initial attribute \src "libresoc.v:43504.9-43504.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry case assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end attribute \src "libresoc.v:43532.3-43560.6" process $proc$libresoc.v:43532$2354 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] attribute \src "libresoc.v:43533.5-43533.29" switch \initial attribute \src "libresoc.v:43533.9-43533.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit case assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] end attribute \src "libresoc.v:43561.3-43589.6" process $proc$libresoc.v:43561$2355 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] attribute \src "libresoc.v:43562.5-43562.29" switch \initial attribute \src "libresoc.v:43562.9-43562.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed case assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] end attribute \src "libresoc.v:43590.3-43618.6" process $proc$libresoc.v:43590$2356 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] attribute \src "libresoc.v:43591.5-43591.29" switch \initial attribute \src "libresoc.v:43591.9-43591.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len case assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 end end case assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 end sync always update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] end attribute \src "libresoc.v:43619.3-43647.6" process $proc$libresoc.v:43619$2357 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] attribute \src "libresoc.v:43620.5-43620.29" switch \initial attribute \src "libresoc.v:43620.9-43620.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn case assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 end sync always update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] end attribute \src "libresoc.v:43648.3-43676.6" process $proc$libresoc.v:43648$2358 assign { } { } assign { } { } assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360 attribute \src "libresoc.v:43649.5-43649.29" switch \initial attribute \src "libresoc.v:43649.9-43649.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$22[0:0]$2360 $2\fus_cu_issue_i$22[0:0]$2361 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$22[0:0]$2361 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$22[0:0]$2361 $3\fus_cu_issue_i$22[0:0]$2362 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$22[0:0]$2362 \issue_i case assign $3\fus_cu_issue_i$22[0:0]$2362 1'0 end end case assign $1\fus_cu_issue_i$22[0:0]$2360 1'0 end sync always update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359 end attribute \src "libresoc.v:43677.3-43705.6" process $proc$libresoc.v:43677$2363 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365 attribute \src "libresoc.v:43678.5-43678.29" switch \initial attribute \src "libresoc.v:43678.9-43678.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 $2\fus_cu_rdmaskn_i$24[2:0]$2366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$24[2:0]$2366 $3\fus_cu_rdmaskn_i$24[2:0]$2367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 \$256 case assign $3\fus_cu_rdmaskn_i$24[2:0]$2367 3'000 end end case assign $1\fus_cu_rdmaskn_i$24[2:0]$2365 3'000 end sync always update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364 end attribute \src "libresoc.v:43706.3-43734.6" process $proc$libresoc.v:43706$2368 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] attribute \src "libresoc.v:43707.5-43707.29" switch \initial attribute \src "libresoc.v:43707.9-43707.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type case assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end attribute \src "libresoc.v:43735.3-43763.6" process $proc$libresoc.v:43735$2369 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0] attribute \src "libresoc.v:43736.5-43736.29" switch \initial attribute \src "libresoc.v:43736.9-43736.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] $2\fus_oper_i_alu_spr0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_spr0__fn_unit[13:0] $3\fus_oper_i_alu_spr0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] \dec_SPR_SPR__fn_unit case assign $3\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_spr0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0] end attribute \src "libresoc.v:43764.3-43792.6" process $proc$libresoc.v:43764$2370 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] attribute \src "libresoc.v:43765.5-43765.29" switch \initial attribute \src "libresoc.v:43765.9-43765.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn case assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 end sync always update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] end attribute \src "libresoc.v:43793.3-43821.6" process $proc$libresoc.v:43793$2371 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] attribute \src "libresoc.v:43794.5-43794.29" switch \initial attribute \src "libresoc.v:43794.9-43794.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit case assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] end attribute \src "libresoc.v:43822.3-43850.6" process $proc$libresoc.v:43822$2372 assign { } { } assign { } { } assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374 attribute \src "libresoc.v:43823.5-43823.29" switch \initial attribute \src "libresoc.v:43823.9-43823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$25[0:0]$2374 $2\fus_cu_issue_i$25[0:0]$2375 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$25[0:0]$2375 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$25[0:0]$2375 $3\fus_cu_issue_i$25[0:0]$2376 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$25[0:0]$2376 \issue_i case assign $3\fus_cu_issue_i$25[0:0]$2376 1'0 end end case assign $1\fus_cu_issue_i$25[0:0]$2374 1'0 end sync always update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373 end attribute \src "libresoc.v:43851.3-43879.6" process $proc$libresoc.v:43851$2377 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379 attribute \src "libresoc.v:43852.5-43852.29" switch \initial attribute \src "libresoc.v:43852.9-43852.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 $2\fus_cu_rdmaskn_i$27[5:0]$2380 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 6'000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$27[5:0]$2380 $3\fus_cu_rdmaskn_i$27[5:0]$2381 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 \$270 case assign $3\fus_cu_rdmaskn_i$27[5:0]$2381 6'000000 end end case assign $1\fus_cu_rdmaskn_i$27[5:0]$2379 6'000000 end sync always update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378 end attribute \src "libresoc.v:43880.3-43908.6" process $proc$libresoc.v:43880$2382 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] attribute \src "libresoc.v:43881.5-43881.29" switch \initial attribute \src "libresoc.v:43881.9-43881.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV__insn_type case assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end attribute \src "libresoc.v:43909.3-43937.6" process $proc$libresoc.v:43909$2383 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0] attribute \src "libresoc.v:43910.5-43910.29" switch \initial attribute \src "libresoc.v:43910.9-43910.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__fn_unit[13:0] $2\fus_oper_i_alu_div0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__fn_unit[13:0] $3\fus_oper_i_alu_div0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__fn_unit[13:0] \dec_DIV_DIV__fn_unit case assign $3\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_div0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0] end attribute \src "libresoc.v:43938.3-43967.6" process $proc$libresoc.v:43938$2384 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] attribute \src "libresoc.v:43939.5-43939.29" switch \initial attribute \src "libresoc.v:43939.9-43939.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV__imm_data__ok \dec_DIV_DIV__imm_data__data } case assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end attribute \src "libresoc.v:43968.3-43997.6" process $proc$libresoc.v:43968$2385 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] attribute \src "libresoc.v:43969.5-43969.29" switch \initial attribute \src "libresoc.v:43969.9-43969.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV__rc__ok \dec_DIV_DIV__rc__rc } case assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end attribute \src "libresoc.v:43998.3-44027.6" process $proc$libresoc.v:43998$2386 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] attribute \src "libresoc.v:43999.5-43999.29" switch \initial attribute \src "libresoc.v:43999.9-43999.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV__oe__ok \dec_DIV_DIV__oe__oe } case assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end attribute \src "libresoc.v:44028.3-44056.6" process $proc$libresoc.v:44028$2387 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] attribute \src "libresoc.v:44029.5-44029.29" switch \initial attribute \src "libresoc.v:44029.9-44029.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV__invert_in case assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end attribute \src "libresoc.v:44057.3-44085.6" process $proc$libresoc.v:44057$2388 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] attribute \src "libresoc.v:44058.5-44058.29" switch \initial attribute \src "libresoc.v:44058.9-44058.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV__zero_a case assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end attribute \src "libresoc.v:44086.3-44114.6" process $proc$libresoc.v:44086$2389 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] attribute \src "libresoc.v:44087.5-44087.29" switch \initial attribute \src "libresoc.v:44087.9-44087.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV__input_carry case assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 end end case assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 end sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end attribute \src "libresoc.v:44115.3-44143.6" process $proc$libresoc.v:44115$2390 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] attribute \src "libresoc.v:44116.5-44116.29" switch \initial attribute \src "libresoc.v:44116.9-44116.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV__invert_out case assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end attribute \src "libresoc.v:44144.3-44172.6" process $proc$libresoc.v:44144$2391 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] attribute \src "libresoc.v:44145.5-44145.29" switch \initial attribute \src "libresoc.v:44145.9-44145.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV__write_cr0 case assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end attribute \src "libresoc.v:44173.3-44201.6" process $proc$libresoc.v:44173$2392 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] attribute \src "libresoc.v:44174.5-44174.29" switch \initial attribute \src "libresoc.v:44174.9-44174.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV__output_carry case assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end attribute \src "libresoc.v:44202.3-44230.6" process $proc$libresoc.v:44202$2393 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] attribute \src "libresoc.v:44203.5-44203.29" switch \initial attribute \src "libresoc.v:44203.9-44203.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV__is_32bit case assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end attribute \src "libresoc.v:44231.3-44259.6" process $proc$libresoc.v:44231$2394 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] attribute \src "libresoc.v:44232.5-44232.29" switch \initial attribute \src "libresoc.v:44232.9-44232.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV__is_signed case assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 end end case assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 end sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end attribute \src "libresoc.v:44260.3-44288.6" process $proc$libresoc.v:44260$2395 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] attribute \src "libresoc.v:44261.5-44261.29" switch \initial attribute \src "libresoc.v:44261.9-44261.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV__data_len case assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 end end case assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 end sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end attribute \src "libresoc.v:44289.3-44317.6" process $proc$libresoc.v:44289$2396 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] attribute \src "libresoc.v:44290.5-44290.29" switch \initial attribute \src "libresoc.v:44290.9-44290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_div0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_div0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV__insn case assign $3\fus_oper_i_alu_div0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_div0__insn[31:0] 0 end sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end attribute \src "libresoc.v:44318.3-44346.6" process $proc$libresoc.v:44318$2397 assign { } { } assign { } { } assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399 attribute \src "libresoc.v:44319.5-44319.29" switch \initial attribute \src "libresoc.v:44319.9-44319.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$28[0:0]$2399 $2\fus_cu_issue_i$28[0:0]$2400 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$28[0:0]$2400 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$28[0:0]$2400 $3\fus_cu_issue_i$28[0:0]$2401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$28[0:0]$2401 \issue_i case assign $3\fus_cu_issue_i$28[0:0]$2401 1'0 end end case assign $1\fus_cu_issue_i$28[0:0]$2399 1'0 end sync always update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398 end attribute \src "libresoc.v:44347.3-44375.6" process $proc$libresoc.v:44347$2402 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404 attribute \src "libresoc.v:44348.5-44348.29" switch \initial attribute \src "libresoc.v:44348.9-44348.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 $2\fus_cu_rdmaskn_i$30[2:0]$2405 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$30[2:0]$2405 $3\fus_cu_rdmaskn_i$30[2:0]$2406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 \$300 case assign $3\fus_cu_rdmaskn_i$30[2:0]$2406 3'000 end end case assign $1\fus_cu_rdmaskn_i$30[2:0]$2404 3'000 end sync always update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403 end attribute \src "libresoc.v:44376.3-44404.6" process $proc$libresoc.v:44376$2407 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] attribute \src "libresoc.v:44377.5-44377.29" switch \initial attribute \src "libresoc.v:44377.9-44377.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL__insn_type case assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end attribute \src "libresoc.v:44405.3-44433.6" process $proc$libresoc.v:44405$2408 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0] attribute \src "libresoc.v:44406.5-44406.29" switch \initial attribute \src "libresoc.v:44406.9-44406.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] $2\fus_oper_i_alu_mul0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_mul0__fn_unit[13:0] $3\fus_oper_i_alu_mul0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] \dec_MUL_MUL__fn_unit case assign $3\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_mul0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0] end attribute \src "libresoc.v:44434.3-44463.6" process $proc$libresoc.v:44434$2409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] attribute \src "libresoc.v:44435.5-44435.29" switch \initial attribute \src "libresoc.v:44435.9-44435.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL__imm_data__ok \dec_MUL_MUL__imm_data__data } case assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end attribute \src "libresoc.v:44464.3-44493.6" process $proc$libresoc.v:44464$2410 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] attribute \src "libresoc.v:44465.5-44465.29" switch \initial attribute \src "libresoc.v:44465.9-44465.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL__rc__ok \dec_MUL_MUL__rc__rc } case assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 end end case assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 end sync always update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end attribute \src "libresoc.v:44494.3-44523.6" process $proc$libresoc.v:44494$2411 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] attribute \src "libresoc.v:44495.5-44495.29" switch \initial attribute \src "libresoc.v:44495.9-44495.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL__oe__ok \dec_MUL_MUL__oe__oe } case assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end attribute \src "libresoc.v:44524.3-44552.6" process $proc$libresoc.v:44524$2412 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] attribute \src "libresoc.v:44525.5-44525.29" switch \initial attribute \src "libresoc.v:44525.9-44525.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL__write_cr0 case assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 end end case assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 end sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end attribute \src "libresoc.v:44553.3-44581.6" process $proc$libresoc.v:44553$2413 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] attribute \src "libresoc.v:44554.5-44554.29" switch \initial attribute \src "libresoc.v:44554.9-44554.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL__is_32bit case assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end attribute \src "libresoc.v:44582.3-44610.6" process $proc$libresoc.v:44582$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] attribute \src "libresoc.v:44583.5-44583.29" switch \initial attribute \src "libresoc.v:44583.9-44583.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL__is_signed case assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 end end case assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 end sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end attribute \src "libresoc.v:44611.3-44639.6" process $proc$libresoc.v:44611$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] attribute \src "libresoc.v:44612.5-44612.29" switch \initial attribute \src "libresoc.v:44612.9-44612.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL__insn case assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 end sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end attribute \src "libresoc.v:44640.3-44668.6" process $proc$libresoc.v:44640$2416 assign { } { } assign { } { } assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418 attribute \src "libresoc.v:44641.5-44641.29" switch \initial attribute \src "libresoc.v:44641.9-44641.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$31[0:0]$2418 $2\fus_cu_issue_i$31[0:0]$2419 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$31[0:0]$2419 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$31[0:0]$2419 $3\fus_cu_issue_i$31[0:0]$2420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$31[0:0]$2420 \issue_i case assign $3\fus_cu_issue_i$31[0:0]$2420 1'0 end end case assign $1\fus_cu_issue_i$31[0:0]$2418 1'0 end sync always update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417 end attribute \src "libresoc.v:44669.3-44697.6" process $proc$libresoc.v:44669$2421 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423 attribute \src "libresoc.v:44670.5-44670.29" switch \initial attribute \src "libresoc.v:44670.9-44670.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 $2\fus_cu_rdmaskn_i$33[2:0]$2424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$33[2:0]$2424 $3\fus_cu_rdmaskn_i$33[2:0]$2425 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 \$314 case assign $3\fus_cu_rdmaskn_i$33[2:0]$2425 3'000 end end case assign $1\fus_cu_rdmaskn_i$33[2:0]$2423 3'000 end sync always update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422 end attribute \src "libresoc.v:44698.3-44726.6" process $proc$libresoc.v:44698$2426 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] attribute \src "libresoc.v:44699.5-44699.29" switch \initial attribute \src "libresoc.v:44699.9-44699.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT__insn_type case assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end attribute \src "libresoc.v:44727.3-44755.6" process $proc$libresoc.v:44727$2427 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] attribute \src "libresoc.v:44728.5-44728.29" switch \initial attribute \src "libresoc.v:44728.9-44728.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit case assign $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] end attribute \src "libresoc.v:44756.3-44785.6" process $proc$libresoc.v:44756$2428 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] attribute \src "libresoc.v:44757.5-44757.29" switch \initial attribute \src "libresoc.v:44757.9-44757.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data } case assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end attribute \src "libresoc.v:44786.3-44815.6" process $proc$libresoc.v:44786$2429 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] attribute \src "libresoc.v:44787.5-44787.29" switch \initial attribute \src "libresoc.v:44787.9-44787.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__rc } case assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end attribute \src "libresoc.v:44816.3-44845.6" process $proc$libresoc.v:44816$2430 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] attribute \src "libresoc.v:44817.5-44817.29" switch \initial attribute \src "libresoc.v:44817.9-44817.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__oe } case assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end attribute \src "libresoc.v:44846.3-44874.6" process $proc$libresoc.v:44846$2431 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] attribute \src "libresoc.v:44847.5-44847.29" switch \initial attribute \src "libresoc.v:44847.9-44847.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 case assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end attribute \src "libresoc.v:44875.3-44903.6" process $proc$libresoc.v:44875$2432 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] attribute \src "libresoc.v:44876.5-44876.29" switch \initial attribute \src "libresoc.v:44876.9-44876.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] \dec_SHIFT_ROT_SHIFT_ROT__invert_in case assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] end attribute \src "libresoc.v:44904.3-44932.6" process $proc$libresoc.v:44904$2433 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] attribute \src "libresoc.v:44905.5-44905.29" switch \initial attribute \src "libresoc.v:44905.9-44905.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT__input_carry case assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 end end case assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 end sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end attribute \src "libresoc.v:44933.3-44961.6" process $proc$libresoc.v:44933$2434 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] attribute \src "libresoc.v:44934.5-44934.29" switch \initial attribute \src "libresoc.v:44934.9-44934.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_carry case assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end attribute \src "libresoc.v:44962.3-44990.6" process $proc$libresoc.v:44962$2435 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] attribute \src "libresoc.v:44963.5-44963.29" switch \initial attribute \src "libresoc.v:44963.9-44963.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__input_cr case assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end attribute \src "libresoc.v:44991.3-45019.6" process $proc$libresoc.v:44991$2436 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] attribute \src "libresoc.v:44992.5-44992.29" switch \initial attribute \src "libresoc.v:44992.9-44992.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_cr case assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end attribute \src "libresoc.v:45020.3-45048.6" process $proc$libresoc.v:45020$2437 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] attribute \src "libresoc.v:45021.5-45021.29" switch \initial attribute \src "libresoc.v:45021.9-45021.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_32bit case assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end attribute \src "libresoc.v:45049.3-45077.6" process $proc$libresoc.v:45049$2438 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] attribute \src "libresoc.v:45050.5-45050.29" switch \initial attribute \src "libresoc.v:45050.9-45050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_signed case assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 end end case assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 end sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end attribute \src "libresoc.v:45078.3-45106.6" process $proc$libresoc.v:45078$2439 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] attribute \src "libresoc.v:45079.5-45079.29" switch \initial attribute \src "libresoc.v:45079.9-45079.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT__insn case assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 end sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end attribute \src "libresoc.v:45107.3-45135.6" process $proc$libresoc.v:45107$2440 assign { } { } assign { } { } assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442 attribute \src "libresoc.v:45108.5-45108.29" switch \initial attribute \src "libresoc.v:45108.9-45108.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$34[0:0]$2442 $2\fus_cu_issue_i$34[0:0]$2443 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$34[0:0]$2443 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$34[0:0]$2443 $3\fus_cu_issue_i$34[0:0]$2444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$34[0:0]$2444 \issue_i case assign $3\fus_cu_issue_i$34[0:0]$2444 1'0 end end case assign $1\fus_cu_issue_i$34[0:0]$2442 1'0 end sync always update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441 end attribute \src "libresoc.v:45136.3-45164.6" process $proc$libresoc.v:45136$2445 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447 attribute \src "libresoc.v:45137.5-45137.29" switch \initial attribute \src "libresoc.v:45137.9-45137.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 $2\fus_cu_rdmaskn_i$36[4:0]$2448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 5'00000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$36[4:0]$2448 $3\fus_cu_rdmaskn_i$36[4:0]$2449 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 \$328 case assign $3\fus_cu_rdmaskn_i$36[4:0]$2449 5'00000 end end case assign $1\fus_cu_rdmaskn_i$36[4:0]$2447 5'00000 end sync always update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446 end attribute \src "libresoc.v:45165.3-45193.6" process $proc$libresoc.v:45165$2450 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] attribute \src "libresoc.v:45166.5-45166.29" switch \initial attribute \src "libresoc.v:45166.9-45166.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST__insn_type case assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end attribute \src "libresoc.v:45194.3-45222.6" process $proc$libresoc.v:45194$2451 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] attribute \src "libresoc.v:45195.5-45195.29" switch \initial attribute \src "libresoc.v:45195.9-45195.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] \dec_LDST_LDST__fn_unit case assign $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] end attribute \src "libresoc.v:45223.3-45252.6" process $proc$libresoc.v:45223$2452 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] attribute \src "libresoc.v:45224.5-45224.29" switch \initial attribute \src "libresoc.v:45224.9-45224.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST__imm_data__ok \dec_LDST_LDST__imm_data__data } case assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end attribute \src "libresoc.v:45253.3-45281.6" process $proc$libresoc.v:45253$2453 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] attribute \src "libresoc.v:45254.5-45254.29" switch \initial attribute \src "libresoc.v:45254.9-45254.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST__zero_a case assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end attribute \src "libresoc.v:45282.3-45311.6" process $proc$libresoc.v:45282$2454 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] attribute \src "libresoc.v:45283.5-45283.29" switch \initial attribute \src "libresoc.v:45283.9-45283.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST__rc__ok \dec_LDST_LDST__rc__rc } case assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end attribute \src "libresoc.v:45312.3-45341.6" process $proc$libresoc.v:45312$2455 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] attribute \src "libresoc.v:45313.5-45313.29" switch \initial attribute \src "libresoc.v:45313.9-45313.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST__oe__ok \dec_LDST_LDST__oe__oe } case assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end attribute \src "libresoc.v:45342.3-45370.6" process $proc$libresoc.v:45342$2456 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] attribute \src "libresoc.v:45343.5-45343.29" switch \initial attribute \src "libresoc.v:45343.9-45343.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST__is_32bit case assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end attribute \src "libresoc.v:45371.3-45399.6" process $proc$libresoc.v:45371$2457 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] attribute \src "libresoc.v:45372.5-45372.29" switch \initial attribute \src "libresoc.v:45372.9-45372.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST__is_signed case assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end attribute \src "libresoc.v:45400.3-45428.6" process $proc$libresoc.v:45400$2458 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] attribute \src "libresoc.v:45401.5-45401.29" switch \initial attribute \src "libresoc.v:45401.9-45401.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST__data_len case assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 end end case assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 end sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end attribute \src "libresoc.v:45429.3-45457.6" process $proc$libresoc.v:45429$2459 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] attribute \src "libresoc.v:45430.5-45430.29" switch \initial attribute \src "libresoc.v:45430.9-45430.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST__byte_reverse case assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end attribute \src "libresoc.v:45458.3-45486.6" process $proc$libresoc.v:45458$2460 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] attribute \src "libresoc.v:45459.5-45459.29" switch \initial attribute \src "libresoc.v:45459.9-45459.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST__sign_extend case assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 end end case assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 end sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end attribute \src "libresoc.v:45487.3-45515.6" process $proc$libresoc.v:45487$2461 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] attribute \src "libresoc.v:45488.5-45488.29" switch \initial attribute \src "libresoc.v:45488.9-45488.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST__ldst_mode case assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 end end case assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 end sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end attribute \src "libresoc.v:45516.3-45544.6" process $proc$libresoc.v:45516$2462 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] attribute \src "libresoc.v:45517.5-45517.29" switch \initial attribute \src "libresoc.v:45517.9-45517.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST__insn case assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 end end case assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 end sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end attribute \src "libresoc.v:45545.3-45573.6" process $proc$libresoc.v:45545$2463 assign { } { } assign { } { } assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465 attribute \src "libresoc.v:45546.5-45546.29" switch \initial attribute \src "libresoc.v:45546.9-45546.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$37[0:0]$2465 $2\fus_cu_issue_i$37[0:0]$2466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$37[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$37[0:0]$2466 $3\fus_cu_issue_i$37[0:0]$2467 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$37[0:0]$2467 \issue_i case assign $3\fus_cu_issue_i$37[0:0]$2467 1'0 end end case assign $1\fus_cu_issue_i$37[0:0]$2465 1'0 end sync always update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464 end attribute \src "libresoc.v:45574.3-45602.6" process $proc$libresoc.v:45574$2468 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470 attribute \src "libresoc.v:45575.5-45575.29" switch \initial attribute \src "libresoc.v:45575.9-45575.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 $2\fus_cu_rdmaskn_i$39[2:0]$2471 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$39[2:0]$2471 $3\fus_cu_rdmaskn_i$39[2:0]$2472 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 \$350 case assign $3\fus_cu_rdmaskn_i$39[2:0]$2472 3'000 end end case assign $1\fus_cu_rdmaskn_i$39[2:0]$2470 3'000 end sync always update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469 end attribute \src "libresoc.v:45603.3-45611.6" process $proc$libresoc.v:45603$2473 assign { } { } assign { } { } assign $0\dp_INT_rabc_alu0_0$next[0:0]$2474 $1\dp_INT_rabc_alu0_0$next[0:0]$2475 attribute \src "libresoc.v:45604.5-45604.29" switch \initial attribute \src "libresoc.v:45604.9-45604.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_alu0_0$next[0:0]$2475 1'0 case assign $1\dp_INT_rabc_alu0_0$next[0:0]$2475 \rp_INT_rabc_alu0_0 end sync always update \dp_INT_rabc_alu0_0$next $0\dp_INT_rabc_alu0_0$next[0:0]$2474 end attribute \src "libresoc.v:45612.3-45621.6" process $proc$libresoc.v:45612$2476 assign { } { } assign { } { } assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] attribute \src "libresoc.v:45613.5-45613.29" switch \initial attribute \src "libresoc.v:45613.9-45613.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i[63:0] \int_src1__data_o case assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i $0\fus_src2_i[63:0] end attribute \src "libresoc.v:45622.3-45630.6" process $proc$libresoc.v:45622$2477 assign { } { } assign { } { } assign $0\dp_INT_rabc_cr0_1$next[0:0]$2478 $1\dp_INT_rabc_cr0_1$next[0:0]$2479 attribute \src "libresoc.v:45623.5-45623.29" switch \initial attribute \src "libresoc.v:45623.9-45623.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_cr0_1$next[0:0]$2479 1'0 case assign $1\dp_INT_rabc_cr0_1$next[0:0]$2479 \rp_INT_rabc_cr0_1 end sync always update \dp_INT_rabc_cr0_1$next $0\dp_INT_rabc_cr0_1$next[0:0]$2478 end attribute \src "libresoc.v:45631.3-45640.6" process $proc$libresoc.v:45631$2480 assign { } { } assign { } { } assign $0\fus_src2_i$42[63:0]$2481 $1\fus_src2_i$42[63:0]$2482 attribute \src "libresoc.v:45632.5-45632.29" switch \initial attribute \src "libresoc.v:45632.9-45632.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$42[63:0]$2482 \int_src1__data_o case assign $1\fus_src2_i$42[63:0]$2482 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$42 $0\fus_src2_i$42[63:0]$2481 end attribute \src "libresoc.v:45641.3-45649.6" process $proc$libresoc.v:45641$2483 assign { } { } assign { } { } assign $0\dp_INT_rabc_trap0_2$next[0:0]$2484 $1\dp_INT_rabc_trap0_2$next[0:0]$2485 attribute \src "libresoc.v:45642.5-45642.29" switch \initial attribute \src "libresoc.v:45642.9-45642.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_trap0_2$next[0:0]$2485 1'0 case assign $1\dp_INT_rabc_trap0_2$next[0:0]$2485 \rp_INT_rabc_trap0_2 end sync always update \dp_INT_rabc_trap0_2$next $0\dp_INT_rabc_trap0_2$next[0:0]$2484 end attribute \src "libresoc.v:45650.3-45659.6" process $proc$libresoc.v:45650$2486 assign { } { } assign { } { } assign $0\fus_src2_i$45[63:0]$2487 $1\fus_src2_i$45[63:0]$2488 attribute \src "libresoc.v:45651.5-45651.29" switch \initial attribute \src "libresoc.v:45651.9-45651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$45[63:0]$2488 \int_src1__data_o case assign $1\fus_src2_i$45[63:0]$2488 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$45 $0\fus_src2_i$45[63:0]$2487 end attribute \src "libresoc.v:45660.3-45668.6" process $proc$libresoc.v:45660$2489 assign { } { } assign { } { } assign $0\dp_INT_rabc_logical0_3$next[0:0]$2490 $1\dp_INT_rabc_logical0_3$next[0:0]$2491 attribute \src "libresoc.v:45661.5-45661.29" switch \initial attribute \src "libresoc.v:45661.9-45661.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_logical0_3$next[0:0]$2491 1'0 case assign $1\dp_INT_rabc_logical0_3$next[0:0]$2491 \rp_INT_rabc_logical0_3 end sync always update \dp_INT_rabc_logical0_3$next $0\dp_INT_rabc_logical0_3$next[0:0]$2490 end attribute \src "libresoc.v:45669.3-45678.6" process $proc$libresoc.v:45669$2492 assign { } { } assign { } { } assign $0\fus_src2_i$48[63:0]$2493 $1\fus_src2_i$48[63:0]$2494 attribute \src "libresoc.v:45670.5-45670.29" switch \initial attribute \src "libresoc.v:45670.9-45670.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$48[63:0]$2494 \int_src1__data_o case assign $1\fus_src2_i$48[63:0]$2494 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$48 $0\fus_src2_i$48[63:0]$2493 end attribute \src "libresoc.v:45679.3-45687.6" process $proc$libresoc.v:45679$2495 assign { } { } assign { } { } assign $0\dp_INT_rabc_div0_4$next[0:0]$2496 $1\dp_INT_rabc_div0_4$next[0:0]$2497 attribute \src "libresoc.v:45680.5-45680.29" switch \initial attribute \src "libresoc.v:45680.9-45680.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_div0_4$next[0:0]$2497 1'0 case assign $1\dp_INT_rabc_div0_4$next[0:0]$2497 \rp_INT_rabc_div0_4 end sync always update \dp_INT_rabc_div0_4$next $0\dp_INT_rabc_div0_4$next[0:0]$2496 end attribute \src "libresoc.v:45688.3-45697.6" process $proc$libresoc.v:45688$2498 assign { } { } assign { } { } assign $0\fus_src2_i$51[63:0]$2499 $1\fus_src2_i$51[63:0]$2500 attribute \src "libresoc.v:45689.5-45689.29" switch \initial attribute \src "libresoc.v:45689.9-45689.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_div0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$51[63:0]$2500 \int_src1__data_o case assign $1\fus_src2_i$51[63:0]$2500 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$51 $0\fus_src2_i$51[63:0]$2499 end attribute \src "libresoc.v:45698.3-45706.6" process $proc$libresoc.v:45698$2501 assign { } { } assign { } { } assign $0\dp_INT_rabc_mul0_5$next[0:0]$2502 $1\dp_INT_rabc_mul0_5$next[0:0]$2503 attribute \src "libresoc.v:45699.5-45699.29" switch \initial attribute \src "libresoc.v:45699.9-45699.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_mul0_5$next[0:0]$2503 1'0 case assign $1\dp_INT_rabc_mul0_5$next[0:0]$2503 \rp_INT_rabc_mul0_5 end sync always update \dp_INT_rabc_mul0_5$next $0\dp_INT_rabc_mul0_5$next[0:0]$2502 end attribute \src "libresoc.v:45707.3-45716.6" process $proc$libresoc.v:45707$2504 assign { } { } assign { } { } assign $0\fus_src2_i$54[63:0]$2505 $1\fus_src2_i$54[63:0]$2506 attribute \src "libresoc.v:45708.5-45708.29" switch \initial attribute \src "libresoc.v:45708.9-45708.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_mul0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$54[63:0]$2506 \int_src1__data_o case assign $1\fus_src2_i$54[63:0]$2506 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$54 $0\fus_src2_i$54[63:0]$2505 end attribute \src "libresoc.v:45717.3-45725.6" process $proc$libresoc.v:45717$2507 assign { } { } assign { } { } assign $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 attribute \src "libresoc.v:45718.5-45718.29" switch \initial attribute \src "libresoc.v:45718.9-45718.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 1'0 case assign $1\dp_INT_rabc_shiftrot0_6$next[0:0]$2509 \rp_INT_rabc_shiftrot0_6 end sync always update \dp_INT_rabc_shiftrot0_6$next $0\dp_INT_rabc_shiftrot0_6$next[0:0]$2508 end attribute \src "libresoc.v:45726.3-45735.6" process $proc$libresoc.v:45726$2510 assign { } { } assign { } { } assign $0\fus_src2_i$57[63:0]$2511 $1\fus_src2_i$57[63:0]$2512 attribute \src "libresoc.v:45727.5-45727.29" switch \initial attribute \src "libresoc.v:45727.9-45727.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_shiftrot0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$57[63:0]$2512 \int_src1__data_o case assign $1\fus_src2_i$57[63:0]$2512 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2511 end attribute \src "libresoc.v:45736.3-45744.6" process $proc$libresoc.v:45736$2513 assign { } { } assign { } { } assign $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 attribute \src "libresoc.v:45737.5-45737.29" switch \initial attribute \src "libresoc.v:45737.9-45737.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 1'0 case assign $1\dp_INT_rabc_ldst0_7$next[0:0]$2515 \rp_INT_rabc_ldst0_7 end sync always update \dp_INT_rabc_ldst0_7$next $0\dp_INT_rabc_ldst0_7$next[0:0]$2514 end attribute \src "libresoc.v:45745.3-45754.6" process $proc$libresoc.v:45745$2516 assign { } { } assign { } { } assign $0\fus_src2_i$60[63:0]$2517 $1\fus_src2_i$60[63:0]$2518 attribute \src "libresoc.v:45746.5-45746.29" switch \initial attribute \src "libresoc.v:45746.9-45746.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_ldst0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$60[63:0]$2518 \int_src1__data_o case assign $1\fus_src2_i$60[63:0]$2518 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2517 end attribute \src "libresoc.v:45755.3-45763.6" process $proc$libresoc.v:45755$2519 assign { } { } assign { } { } assign $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 attribute \src "libresoc.v:45756.5-45756.29" switch \initial attribute \src "libresoc.v:45756.9-45756.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 1'0 case assign $1\dp_INT_rabc_shiftrot0_8$next[0:0]$2521 \rp_INT_rabc_shiftrot0_8 end sync always update \dp_INT_rabc_shiftrot0_8$next $0\dp_INT_rabc_shiftrot0_8$next[0:0]$2520 end attribute \src "libresoc.v:45764.3-45773.6" process $proc$libresoc.v:45764$2522 assign { } { } assign { } { } assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] attribute \src "libresoc.v:45765.5-45765.29" switch \initial attribute \src "libresoc.v:45765.9-45765.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_shiftrot0_8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i[63:0] \int_src1__data_o case assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src3_i $0\fus_src3_i[63:0] end attribute \src "libresoc.v:45774.3-45782.6" process $proc$libresoc.v:45774$2523 assign { } { } assign { } { } assign $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 attribute \src "libresoc.v:45775.5-45775.29" switch \initial attribute \src "libresoc.v:45775.9-45775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 1'0 case assign $1\dp_INT_rabc_ldst0_9$next[0:0]$2525 \rp_INT_rabc_ldst0_9 end sync always update \dp_INT_rabc_ldst0_9$next $0\dp_INT_rabc_ldst0_9$next[0:0]$2524 end attribute \src "libresoc.v:45783.3-45792.6" process $proc$libresoc.v:45783$2526 assign { } { } assign { } { } assign $0\fus_src3_i$61[63:0]$2527 $1\fus_src3_i$61[63:0]$2528 attribute \src "libresoc.v:45784.5-45784.29" switch \initial attribute \src "libresoc.v:45784.9-45784.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_ldst0_9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$61[63:0]$2528 \int_src1__data_o case assign $1\fus_src3_i$61[63:0]$2528 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src3_i$61 $0\fus_src3_i$61[63:0]$2527 end attribute \src "libresoc.v:45793.3-45801.6" process $proc$libresoc.v:45793$2529 assign { } { } assign { } { } assign $0\dp_INT_rabc_alu0_10$next[0:0]$2530 $1\dp_INT_rabc_alu0_10$next[0:0]$2531 attribute \src "libresoc.v:45794.5-45794.29" switch \initial attribute \src "libresoc.v:45794.9-45794.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_alu0_10$next[0:0]$2531 1'0 case assign $1\dp_INT_rabc_alu0_10$next[0:0]$2531 \rp_INT_rabc_alu0_10 end sync always update \dp_INT_rabc_alu0_10$next $0\dp_INT_rabc_alu0_10$next[0:0]$2530 end attribute \src "libresoc.v:45802.3-45811.6" process $proc$libresoc.v:45802$2532 assign { } { } assign { } { } assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] attribute \src "libresoc.v:45803.5-45803.29" switch \initial attribute \src "libresoc.v:45803.9-45803.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_alu0_10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i[63:0] \int_src1__data_o case assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i $0\fus_src1_i[63:0] end attribute \src "libresoc.v:45812.3-45820.6" process $proc$libresoc.v:45812$2533 assign { } { } assign { } { } assign $0\dp_INT_rabc_cr0_11$next[0:0]$2534 $1\dp_INT_rabc_cr0_11$next[0:0]$2535 attribute \src "libresoc.v:45813.5-45813.29" switch \initial attribute \src "libresoc.v:45813.9-45813.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_cr0_11$next[0:0]$2535 1'0 case assign $1\dp_INT_rabc_cr0_11$next[0:0]$2535 \rp_INT_rabc_cr0_11 end sync always update \dp_INT_rabc_cr0_11$next $0\dp_INT_rabc_cr0_11$next[0:0]$2534 end attribute \src "libresoc.v:45821.3-45830.6" process $proc$libresoc.v:45821$2536 assign { } { } assign { } { } assign $0\fus_src1_i$62[63:0]$2537 $1\fus_src1_i$62[63:0]$2538 attribute \src "libresoc.v:45822.5-45822.29" switch \initial attribute \src "libresoc.v:45822.9-45822.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_cr0_11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$62[63:0]$2538 \int_src1__data_o case assign $1\fus_src1_i$62[63:0]$2538 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$62 $0\fus_src1_i$62[63:0]$2537 end attribute \src "libresoc.v:45831.3-45839.6" process $proc$libresoc.v:45831$2539 assign { } { } assign { } { } assign $0\dp_INT_rabc_trap0_12$next[0:0]$2540 $1\dp_INT_rabc_trap0_12$next[0:0]$2541 attribute \src "libresoc.v:45832.5-45832.29" switch \initial attribute \src "libresoc.v:45832.9-45832.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_trap0_12$next[0:0]$2541 1'0 case assign $1\dp_INT_rabc_trap0_12$next[0:0]$2541 \rp_INT_rabc_trap0_12 end sync always update \dp_INT_rabc_trap0_12$next $0\dp_INT_rabc_trap0_12$next[0:0]$2540 end attribute \src "libresoc.v:45840.3-45849.6" process $proc$libresoc.v:45840$2542 assign { } { } assign { } { } assign $0\fus_src1_i$63[63:0]$2543 $1\fus_src1_i$63[63:0]$2544 attribute \src "libresoc.v:45841.5-45841.29" switch \initial attribute \src "libresoc.v:45841.9-45841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_trap0_12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$63[63:0]$2544 \int_src1__data_o case assign $1\fus_src1_i$63[63:0]$2544 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2543 end attribute \src "libresoc.v:45850.3-45858.6" process $proc$libresoc.v:45850$2545 assign { } { } assign { } { } assign $0\dp_INT_rabc_logical0_13$next[0:0]$2546 $1\dp_INT_rabc_logical0_13$next[0:0]$2547 attribute \src "libresoc.v:45851.5-45851.29" switch \initial attribute \src "libresoc.v:45851.9-45851.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_logical0_13$next[0:0]$2547 1'0 case assign $1\dp_INT_rabc_logical0_13$next[0:0]$2547 \rp_INT_rabc_logical0_13 end sync always update \dp_INT_rabc_logical0_13$next $0\dp_INT_rabc_logical0_13$next[0:0]$2546 end attribute \src "libresoc.v:45859.3-45868.6" process $proc$libresoc.v:45859$2548 assign { } { } assign { } { } assign $0\fus_src1_i$64[63:0]$2549 $1\fus_src1_i$64[63:0]$2550 attribute \src "libresoc.v:45860.5-45860.29" switch \initial attribute \src "libresoc.v:45860.9-45860.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_logical0_13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$64[63:0]$2550 \int_src1__data_o case assign $1\fus_src1_i$64[63:0]$2550 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$64 $0\fus_src1_i$64[63:0]$2549 end attribute \src "libresoc.v:45869.3-45877.6" process $proc$libresoc.v:45869$2551 assign { } { } assign { } { } assign $0\dp_INT_rabc_spr0_14$next[0:0]$2552 $1\dp_INT_rabc_spr0_14$next[0:0]$2553 attribute \src "libresoc.v:45870.5-45870.29" switch \initial attribute \src "libresoc.v:45870.9-45870.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_spr0_14$next[0:0]$2553 1'0 case assign $1\dp_INT_rabc_spr0_14$next[0:0]$2553 \rp_INT_rabc_spr0_14 end sync always update \dp_INT_rabc_spr0_14$next $0\dp_INT_rabc_spr0_14$next[0:0]$2552 end attribute \src "libresoc.v:45878.3-45887.6" process $proc$libresoc.v:45878$2554 assign { } { } assign { } { } assign $0\fus_src1_i$67[63:0]$2555 $1\fus_src1_i$67[63:0]$2556 attribute \src "libresoc.v:45879.5-45879.29" switch \initial attribute \src "libresoc.v:45879.9-45879.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_spr0_14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$67[63:0]$2556 \int_src1__data_o case assign $1\fus_src1_i$67[63:0]$2556 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$67 $0\fus_src1_i$67[63:0]$2555 end attribute \src "libresoc.v:45888.3-45896.6" process $proc$libresoc.v:45888$2557 assign { } { } assign { } { } assign $0\dp_INT_rabc_div0_15$next[0:0]$2558 $1\dp_INT_rabc_div0_15$next[0:0]$2559 attribute \src "libresoc.v:45889.5-45889.29" switch \initial attribute \src "libresoc.v:45889.9-45889.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_div0_15$next[0:0]$2559 1'0 case assign $1\dp_INT_rabc_div0_15$next[0:0]$2559 \rp_INT_rabc_div0_15 end sync always update \dp_INT_rabc_div0_15$next $0\dp_INT_rabc_div0_15$next[0:0]$2558 end attribute \src "libresoc.v:45897.3-45906.6" process $proc$libresoc.v:45897$2560 assign { } { } assign { } { } assign $0\fus_src1_i$68[63:0]$2561 $1\fus_src1_i$68[63:0]$2562 attribute \src "libresoc.v:45898.5-45898.29" switch \initial attribute \src "libresoc.v:45898.9-45898.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_div0_15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$68[63:0]$2562 \int_src1__data_o case assign $1\fus_src1_i$68[63:0]$2562 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$68 $0\fus_src1_i$68[63:0]$2561 end attribute \src "libresoc.v:45907.3-45915.6" process $proc$libresoc.v:45907$2563 assign { } { } assign { } { } assign $0\dp_INT_rabc_mul0_16$next[0:0]$2564 $1\dp_INT_rabc_mul0_16$next[0:0]$2565 attribute \src "libresoc.v:45908.5-45908.29" switch \initial attribute \src "libresoc.v:45908.9-45908.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_mul0_16$next[0:0]$2565 1'0 case assign $1\dp_INT_rabc_mul0_16$next[0:0]$2565 \rp_INT_rabc_mul0_16 end sync always update \dp_INT_rabc_mul0_16$next $0\dp_INT_rabc_mul0_16$next[0:0]$2564 end attribute \src "libresoc.v:45916.3-45925.6" process $proc$libresoc.v:45916$2566 assign { } { } assign { } { } assign $0\fus_src1_i$69[63:0]$2567 $1\fus_src1_i$69[63:0]$2568 attribute \src "libresoc.v:45917.5-45917.29" switch \initial attribute \src "libresoc.v:45917.9-45917.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_mul0_16 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$69[63:0]$2568 \int_src1__data_o case assign $1\fus_src1_i$69[63:0]$2568 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$69 $0\fus_src1_i$69[63:0]$2567 end attribute \src "libresoc.v:45926.3-45934.6" process $proc$libresoc.v:45926$2569 assign { } { } assign { } { } assign $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 attribute \src "libresoc.v:45927.5-45927.29" switch \initial attribute \src "libresoc.v:45927.9-45927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 1'0 case assign $1\dp_INT_rabc_shiftrot0_17$next[0:0]$2571 \rp_INT_rabc_shiftrot0_17 end sync always update \dp_INT_rabc_shiftrot0_17$next $0\dp_INT_rabc_shiftrot0_17$next[0:0]$2570 end attribute \src "libresoc.v:45935.3-45944.6" process $proc$libresoc.v:45935$2572 assign { } { } assign { } { } assign $0\fus_src1_i$70[63:0]$2573 $1\fus_src1_i$70[63:0]$2574 attribute \src "libresoc.v:45936.5-45936.29" switch \initial attribute \src "libresoc.v:45936.9-45936.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_shiftrot0_17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$70[63:0]$2574 \int_src1__data_o case assign $1\fus_src1_i$70[63:0]$2574 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$70 $0\fus_src1_i$70[63:0]$2573 end attribute \src "libresoc.v:45945.3-45953.6" process $proc$libresoc.v:45945$2575 assign { } { } assign { } { } assign $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 attribute \src "libresoc.v:45946.5-45946.29" switch \initial attribute \src "libresoc.v:45946.9-45946.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 1'0 case assign $1\dp_INT_rabc_ldst0_18$next[0:0]$2577 \rp_INT_rabc_ldst0_18 end sync always update \dp_INT_rabc_ldst0_18$next $0\dp_INT_rabc_ldst0_18$next[0:0]$2576 end attribute \src "libresoc.v:45954.3-45963.6" process $proc$libresoc.v:45954$2578 assign { } { } assign { } { } assign $0\fus_src1_i$71[63:0]$2579 $1\fus_src1_i$71[63:0]$2580 attribute \src "libresoc.v:45955.5-45955.29" switch \initial attribute \src "libresoc.v:45955.9-45955.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_INT_rabc_ldst0_18 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$71[63:0]$2580 \int_src1__data_o case assign $1\fus_src1_i$71[63:0]$2580 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$71 $0\fus_src1_i$71[63:0]$2579 end attribute \src "libresoc.v:45964.3-45972.6" process $proc$libresoc.v:45964$2581 assign { } { } assign { } { } assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 attribute \src "libresoc.v:45965.5-45965.29" switch \initial attribute \src "libresoc.v:45965.9-45965.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 1'0 case assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 \rp_XER_xer_so_alu0_0 end sync always update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 end attribute \src "libresoc.v:45973.3-45982.6" process $proc$libresoc.v:45973$2584 assign { } { } assign { } { } assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586 attribute \src "libresoc.v:45974.5-45974.29" switch \initial attribute \src "libresoc.v:45974.9-45974.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$72[0:0]$2586 \xer_src1__data_o [0] case assign $1\fus_src3_i$72[0:0]$2586 1'0 end sync always update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585 end attribute \src "libresoc.v:45983.3-45991.6" process $proc$libresoc.v:45983$2587 assign { } { } assign { } { } assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 attribute \src "libresoc.v:45984.5-45984.29" switch \initial attribute \src "libresoc.v:45984.9-45984.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 1'0 case assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 \rp_XER_xer_so_logical0_1 end sync always update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 end attribute \src "libresoc.v:45992.3-46001.6" process $proc$libresoc.v:45992$2590 assign { } { } assign { } { } assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592 attribute \src "libresoc.v:45993.5-45993.29" switch \initial attribute \src "libresoc.v:45993.9-45993.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_logical0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$73[0:0]$2592 \xer_src1__data_o [0] case assign $1\fus_src3_i$73[0:0]$2592 1'0 end sync always update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591 end attribute \src "libresoc.v:46002.3-46010.6" process $proc$libresoc.v:46002$2593 assign { } { } assign { } { } assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 attribute \src "libresoc.v:46003.5-46003.29" switch \initial attribute \src "libresoc.v:46003.9-46003.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 1'0 case assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 \rp_XER_xer_so_spr0_2 end sync always update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 end attribute \src "libresoc.v:46011.3-46020.6" process $proc$libresoc.v:46011$2596 assign { } { } assign { } { } assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] attribute \src "libresoc.v:46012.5-46012.29" switch \initial attribute \src "libresoc.v:46012.9-46012.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] case assign $1\fus_src4_i[0:0] 1'0 end sync always update \fus_src4_i $0\fus_src4_i[0:0] end attribute \src "libresoc.v:46021.3-46029.6" process $proc$libresoc.v:46021$2597 assign { } { } assign { } { } assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599 attribute \src "libresoc.v:46022.5-46022.29" switch \initial attribute \src "libresoc.v:46022.9-46022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 1'0 case assign $1\dp_XER_xer_so_div0_3$next[0:0]$2599 \rp_XER_xer_so_div0_3 end sync always update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598 end attribute \src "libresoc.v:46030.3-46039.6" process $proc$libresoc.v:46030$2600 assign { } { } assign { } { } assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602 attribute \src "libresoc.v:46031.5-46031.29" switch \initial attribute \src "libresoc.v:46031.9-46031.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_div0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$74[0:0]$2602 \xer_src1__data_o [0] case assign $1\fus_src3_i$74[0:0]$2602 1'0 end sync always update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601 end attribute \src "libresoc.v:46040.3-46048.6" process $proc$libresoc.v:46040$2603 assign { } { } assign { } { } assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 attribute \src "libresoc.v:46041.5-46041.29" switch \initial attribute \src "libresoc.v:46041.9-46041.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 1'0 case assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 \rp_XER_xer_so_mul0_4 end sync always update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 end attribute \src "libresoc.v:46049.3-46058.6" process $proc$libresoc.v:46049$2606 assign { } { } assign { } { } assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608 attribute \src "libresoc.v:46050.5-46050.29" switch \initial attribute \src "libresoc.v:46050.9-46050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_mul0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$75[0:0]$2608 \xer_src1__data_o [0] case assign $1\fus_src3_i$75[0:0]$2608 1'0 end sync always update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607 end attribute \src "libresoc.v:46059.3-46067.6" process $proc$libresoc.v:46059$2609 assign { } { } assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 attribute \src "libresoc.v:46060.5-46060.29" switch \initial attribute \src "libresoc.v:46060.9-46060.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 1'0 case assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 \rp_XER_xer_so_shiftrot0_5 end sync always update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 end attribute \src "libresoc.v:46068.3-46077.6" process $proc$libresoc.v:46068$2612 assign { } { } assign { } { } assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614 attribute \src "libresoc.v:46069.5-46069.29" switch \initial attribute \src "libresoc.v:46069.9-46069.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_so_shiftrot0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src4_i$76[0:0]$2614 \xer_src1__data_o [0] case assign $1\fus_src4_i$76[0:0]$2614 1'0 end sync always update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613 end attribute \src "libresoc.v:46078.3-46086.6" process $proc$libresoc.v:46078$2615 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 attribute \src "libresoc.v:46079.5-46079.29" switch \initial attribute \src "libresoc.v:46079.9-46079.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 1'0 case assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 \rp_XER_xer_ca_alu0_0 end sync always update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 end attribute \src "libresoc.v:46087.3-46096.6" process $proc$libresoc.v:46087$2618 assign { } { } assign { } { } assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620 attribute \src "libresoc.v:46088.5-46088.29" switch \initial attribute \src "libresoc.v:46088.9-46088.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src4_i$77[1:0]$2620 \xer_src2__data_o case assign $1\fus_src4_i$77[1:0]$2620 2'00 end sync always update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619 end attribute \src "libresoc.v:46097.3-46105.6" process $proc$libresoc.v:46097$2621 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 attribute \src "libresoc.v:46098.5-46098.29" switch \initial attribute \src "libresoc.v:46098.9-46098.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 1'0 case assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 \rp_XER_xer_ca_spr0_1 end sync always update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 end attribute \src "libresoc.v:46106.3-46115.6" process $proc$libresoc.v:46106$2624 assign { } { } assign { } { } assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] attribute \src "libresoc.v:46107.5-46107.29" switch \initial attribute \src "libresoc.v:46107.9-46107.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_spr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src6_i[1:0] \xer_src2__data_o case assign $1\fus_src6_i[1:0] 2'00 end sync always update \fus_src6_i $0\fus_src6_i[1:0] end attribute \src "libresoc.v:46116.3-46124.6" process $proc$libresoc.v:46116$2625 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 attribute \src "libresoc.v:46117.5-46117.29" switch \initial attribute \src "libresoc.v:46117.9-46117.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 1'0 case assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 \rp_XER_xer_ca_shiftrot0_2 end sync always update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 end attribute \src "libresoc.v:46125.3-46134.6" process $proc$libresoc.v:46125$2628 assign { } { } assign { } { } assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] attribute \src "libresoc.v:46126.5-46126.29" switch \initial attribute \src "libresoc.v:46126.9-46126.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ca_shiftrot0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src5_i[1:0] \xer_src2__data_o case assign $1\fus_src5_i[1:0] 2'00 end sync always update \fus_src5_i $0\fus_src5_i[1:0] end attribute \src "libresoc.v:46135.3-46143.6" process $proc$libresoc.v:46135$2629 assign { } { } assign { } { } assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 attribute \src "libresoc.v:46136.5-46136.29" switch \initial attribute \src "libresoc.v:46136.9-46136.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 1'0 case assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 \rp_XER_xer_ov_spr0_0 end sync always update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 end attribute \src "libresoc.v:46144.3-46153.6" process $proc$libresoc.v:46144$2632 assign { } { } assign { } { } assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634 attribute \src "libresoc.v:46145.5-46145.29" switch \initial attribute \src "libresoc.v:46145.9-46145.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_XER_xer_ov_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src5_i$78[1:0]$2634 \xer_src3__data_o case assign $1\fus_src5_i$78[1:0]$2634 2'00 end sync always update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633 end attribute \src "libresoc.v:46154.3-46162.6" process $proc$libresoc.v:46154$2635 assign { } { } assign { } { } assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 attribute \src "libresoc.v:46155.5-46155.29" switch \initial attribute \src "libresoc.v:46155.9-46155.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 1'0 case assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 \rp_CR_full_cr_cr0_0 end sync always update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 end attribute \src "libresoc.v:46163.3-46172.6" process $proc$libresoc.v:46163$2638 assign { } { } assign { } { } assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640 attribute \src "libresoc.v:46164.5-46164.29" switch \initial attribute \src "libresoc.v:46164.9-46164.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_full_cr_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$79[31:0]$2640 \cr_full_rd__data_o case assign $1\fus_src3_i$79[31:0]$2640 0 end sync always update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639 end attribute \src "libresoc.v:46173.3-46181.6" process $proc$libresoc.v:46173$2641 assign { } { } assign { } { } assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 attribute \src "libresoc.v:46174.5-46174.29" switch \initial attribute \src "libresoc.v:46174.9-46174.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 1'0 case assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 \rp_CR_cr_a_cr0_0 end sync always update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 end attribute \src "libresoc.v:46182.3-46191.6" process $proc$libresoc.v:46182$2644 assign { } { } assign { } { } assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646 attribute \src "libresoc.v:46183.5-46183.29" switch \initial attribute \src "libresoc.v:46183.9-46183.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_a_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src4_i$80[3:0]$2646 \cr_src1__data_o case assign $1\fus_src4_i$80[3:0]$2646 4'0000 end sync always update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645 end attribute \src "libresoc.v:46192.3-46200.6" process $proc$libresoc.v:46192$2647 assign { } { } assign { } { } assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 attribute \src "libresoc.v:46193.5-46193.29" switch \initial attribute \src "libresoc.v:46193.9-46193.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 1'0 case assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 \rp_CR_cr_a_branch0_1 end sync always update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 end attribute \src "libresoc.v:46201.3-46210.6" process $proc$libresoc.v:46201$2650 assign { } { } assign { } { } assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652 attribute \src "libresoc.v:46202.5-46202.29" switch \initial attribute \src "libresoc.v:46202.9-46202.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_a_branch0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$83[3:0]$2652 \cr_src1__data_o case assign $1\fus_src3_i$83[3:0]$2652 4'0000 end sync always update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651 end attribute \src "libresoc.v:46211.3-46219.6" process $proc$libresoc.v:46211$2653 assign { } { } assign { } { } assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 attribute \src "libresoc.v:46212.5-46212.29" switch \initial attribute \src "libresoc.v:46212.9-46212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 1'0 case assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2655 \rp_CR_cr_b_cr0_0 end sync always update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2654 end attribute \src "libresoc.v:46220.3-46250.6" process $proc$libresoc.v:46220$2656 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\counter$next[1:0]$2657 $4\counter$next[1:0]$2661 attribute \src "libresoc.v:46221.5-46221.29" switch \initial attribute \src "libresoc.v:46221.9-46221.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch \$221 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\counter$next[1:0]$2658 \$223 [1:0] case assign $1\counter$next[1:0]$2658 \counter end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\counter$next[1:0]$2659 $3\counter$next[1:0]$2660 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $3\counter$next[1:0]$2660 $1\counter$next[1:0]$2658 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign { } { } assign $3\counter$next[1:0]$2660 2'10 case assign $3\counter$next[1:0]$2660 $1\counter$next[1:0]$2658 end case assign $2\counter$next[1:0]$2659 $1\counter$next[1:0]$2658 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\counter$next[1:0]$2661 2'00 case assign $4\counter$next[1:0]$2661 $2\counter$next[1:0]$2659 end sync always update \counter$next $0\counter$next[1:0]$2657 end attribute \src "libresoc.v:46251.3-46260.6" process $proc$libresoc.v:46251$2662 assign { } { } assign { } { } assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 attribute \src "libresoc.v:46252.5-46252.29" switch \initial attribute \src "libresoc.v:46252.9-46252.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_b_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src5_i$84[3:0]$2664 \cr_src2__data_o case assign $1\fus_src5_i$84[3:0]$2664 4'0000 end sync always update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 end attribute \src "libresoc.v:46261.3-46269.6" process $proc$libresoc.v:46261$2665 assign { } { } assign { } { } assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 attribute \src "libresoc.v:46262.5-46262.29" switch \initial attribute \src "libresoc.v:46262.9-46262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 1'0 case assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 \rp_CR_cr_c_cr0_0 end sync always update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 end attribute \src "libresoc.v:46270.3-46279.6" process $proc$libresoc.v:46270$2668 assign { } { } assign { } { } assign $0\fus_src6_i$85[3:0]$2669 $1\fus_src6_i$85[3:0]$2670 attribute \src "libresoc.v:46271.5-46271.29" switch \initial attribute \src "libresoc.v:46271.9-46271.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_CR_cr_c_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src6_i$85[3:0]$2670 \cr_src3__data_o case assign $1\fus_src6_i$85[3:0]$2670 4'0000 end sync always update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2669 end attribute \src "libresoc.v:46280.3-46370.6" process $proc$libresoc.v:46280$2671 assign { } { } assign { } { } assign { } { } assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] attribute \src "libresoc.v:46281.5-46281.29" switch \initial attribute \src "libresoc.v:46281.9-46281.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\corebusy_o[0:0] 1'1 case assign $1\corebusy_o[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign { } { } assign $3\corebusy_o[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\corebusy_o[0:0] \fus_cu_busy_o case assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\corebusy_o[0:0] \fus_cu_busy_o$14 case assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\corebusy_o[0:0] \fus_cu_busy_o$17 case assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\corebusy_o[0:0] \fus_cu_busy_o$20 case assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\corebusy_o[0:0] \fus_cu_busy_o$23 case assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\corebusy_o[0:0] \fus_cu_busy_o$26 case assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $10\corebusy_o[0:0] \fus_cu_busy_o$29 case assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $11\corebusy_o[0:0] \fus_cu_busy_o$32 case assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $12\corebusy_o[0:0] \fus_cu_busy_o$35 case assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $13\corebusy_o[0:0] \fus_cu_busy_o$38 case assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] end end case assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] end sync always update \corebusy_o $0\corebusy_o[0:0] end attribute \src "libresoc.v:46371.3-46379.6" process $proc$libresoc.v:46371$2672 assign { } { } assign { } { } assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 attribute \src "libresoc.v:46372.5-46372.29" switch \initial attribute \src "libresoc.v:46372.9-46372.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 1'0 case assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2674 \rp_FAST_fast1_branch0_0 end sync always update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2673 end attribute \src "libresoc.v:46380.3-46389.6" process $proc$libresoc.v:46380$2675 assign { } { } assign { } { } assign $0\fus_src1_i$86[63:0]$2676 $1\fus_src1_i$86[63:0]$2677 attribute \src "libresoc.v:46381.5-46381.29" switch \initial attribute \src "libresoc.v:46381.9-46381.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src1_i$86[63:0]$2677 \fast_src1__data_o case assign $1\fus_src1_i$86[63:0]$2677 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2676 end attribute \src "libresoc.v:46390.3-46410.6" process $proc$libresoc.v:46390$2678 assign { } { } assign { } { } assign { } { } assign $0\core_terminate_o$next[0:0]$2679 $3\core_terminate_o$next[0:0]$2682 attribute \src "libresoc.v:46391.5-46391.29" switch \initial attribute \src "libresoc.v:46391.9-46391.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_terminate_o$next[0:0]$2680 $2\core_terminate_o$next[0:0]$2681 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign { } { } assign $2\core_terminate_o$next[0:0]$2681 1'1 case assign $2\core_terminate_o$next[0:0]$2681 \core_terminate_o end case assign $1\core_terminate_o$next[0:0]$2680 \core_terminate_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\core_terminate_o$next[0:0]$2682 1'0 case assign $3\core_terminate_o$next[0:0]$2682 $1\core_terminate_o$next[0:0]$2680 end sync always update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2679 end attribute \src "libresoc.v:46411.3-46419.6" process $proc$libresoc.v:46411$2683 assign { } { } assign { } { } assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 attribute \src "libresoc.v:46412.5-46412.29" switch \initial attribute \src "libresoc.v:46412.9-46412.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 1'0 case assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 \rp_FAST_fast1_trap0_1 end sync always update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 end attribute \src "libresoc.v:46420.3-46429.6" process $proc$libresoc.v:46420$2686 assign { } { } assign { } { } assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 attribute \src "libresoc.v:46421.5-46421.29" switch \initial attribute \src "libresoc.v:46421.9-46421.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$87[63:0]$2688 \fast_src1__data_o case assign $1\fus_src3_i$87[63:0]$2688 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 end attribute \src "libresoc.v:46430.3-46438.6" process $proc$libresoc.v:46430$2689 assign { } { } assign { } { } assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 attribute \src "libresoc.v:46431.5-46431.29" switch \initial attribute \src "libresoc.v:46431.9-46431.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 1'0 case assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2691 \rp_FAST_fast1_spr0_2 end sync always update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2690 end attribute \src "libresoc.v:46439.3-46448.6" process $proc$libresoc.v:46439$2692 assign { } { } assign { } { } assign $0\fus_src3_i$88[63:0]$2693 $1\fus_src3_i$88[63:0]$2694 attribute \src "libresoc.v:46440.5-46440.29" switch \initial attribute \src "libresoc.v:46440.9-46440.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src3_i$88[63:0]$2694 \fast_src1__data_o case assign $1\fus_src3_i$88[63:0]$2694 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2693 end attribute \src "libresoc.v:46449.3-46477.6" process $proc$libresoc.v:46449$2695 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] attribute \src "libresoc.v:46450.5-46450.29" switch \initial attribute \src "libresoc.v:46450.9-46450.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type case assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end attribute \src "libresoc.v:46478.3-46486.6" process $proc$libresoc.v:46478$2696 assign { } { } assign { } { } assign $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 attribute \src "libresoc.v:46479.5-46479.29" switch \initial attribute \src "libresoc.v:46479.9-46479.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 1'0 case assign $1\dp_FAST_fast1_branch0_3$next[0:0]$2698 \rp_FAST_fast1_branch0_3 end sync always update \dp_FAST_fast1_branch0_3$next $0\dp_FAST_fast1_branch0_3$next[0:0]$2697 end attribute \src "libresoc.v:46487.3-46496.6" process $proc$libresoc.v:46487$2699 assign { } { } assign { } { } assign $0\fus_src2_i$89[63:0]$2700 $1\fus_src2_i$89[63:0]$2701 attribute \src "libresoc.v:46488.5-46488.29" switch \initial attribute \src "libresoc.v:46488.9-46488.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_branch0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$89[63:0]$2701 \fast_src1__data_o case assign $1\fus_src2_i$89[63:0]$2701 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2700 end attribute \src "libresoc.v:46497.3-46505.6" process $proc$libresoc.v:46497$2702 assign { } { } assign { } { } assign $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 attribute \src "libresoc.v:46498.5-46498.29" switch \initial attribute \src "libresoc.v:46498.9-46498.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 1'0 case assign $1\dp_FAST_fast1_trap0_4$next[0:0]$2704 \rp_FAST_fast1_trap0_4 end sync always update \dp_FAST_fast1_trap0_4$next $0\dp_FAST_fast1_trap0_4$next[0:0]$2703 end attribute \src "libresoc.v:46506.3-46515.6" process $proc$libresoc.v:46506$2705 assign { } { } assign { } { } assign $0\fus_src4_i$90[63:0]$2706 $1\fus_src4_i$90[63:0]$2707 attribute \src "libresoc.v:46507.5-46507.29" switch \initial attribute \src "libresoc.v:46507.9-46507.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_FAST_fast1_trap0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src4_i$90[63:0]$2707 \fast_src1__data_o case assign $1\fus_src4_i$90[63:0]$2707 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2706 end attribute \src "libresoc.v:46516.3-46544.6" process $proc$libresoc.v:46516$2708 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] attribute \src "libresoc.v:46517.5-46517.29" switch \initial attribute \src "libresoc.v:46517.9-46517.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] $2\fus_oper_i_alu_alu0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__fn_unit[13:0] $3\fus_oper_i_alu_alu0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] \dec_ALU_ALU__fn_unit case assign $3\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_alu0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] end attribute \src "libresoc.v:46545.3-46553.6" process $proc$libresoc.v:46545$2709 assign { } { } assign { } { } assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 attribute \src "libresoc.v:46546.5-46546.29" switch \initial attribute \src "libresoc.v:46546.9-46546.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 1'0 case assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2711 \rp_SPR_spr1_spr0_0 end sync always update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2710 end attribute \src "libresoc.v:46554.3-46563.6" process $proc$libresoc.v:46554$2712 assign { } { } assign { } { } assign $0\fus_src2_i$91[63:0]$2713 $1\fus_src2_i$91[63:0]$2714 attribute \src "libresoc.v:46555.5-46555.29" switch \initial attribute \src "libresoc.v:46555.9-46555.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" switch \dp_SPR_spr1_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_src2_i$91[63:0]$2714 \spr_spr1__data_o case assign $1\fus_src2_i$91[63:0]$2714 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2713 end attribute \src "libresoc.v:46564.3-46593.6" process $proc$libresoc.v:46564$2715 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] attribute \src "libresoc.v:46565.5-46565.29" switch \initial attribute \src "libresoc.v:46565.9-46565.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } case assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end attribute \src "libresoc.v:46594.3-46602.6" process $proc$libresoc.v:46594$2716 assign { } { } assign { } { } assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 attribute \src "libresoc.v:46595.5-46595.29" switch \initial attribute \src "libresoc.v:46595.9-46595.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$next[0:0]$2718 1'0 case assign $1\wr_pick_dly$next[0:0]$2718 \wr_pick end sync always update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 end attribute \src "libresoc.v:46603.3-46611.6" process $proc$libresoc.v:46603$2719 assign { } { } assign { } { } assign $0\wr_pick_dly$989$next[0:0]$2720 $1\wr_pick_dly$989$next[0:0]$2721 attribute \src "libresoc.v:46604.5-46604.29" switch \initial attribute \src "libresoc.v:46604.9-46604.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$989$next[0:0]$2721 1'0 case assign $1\wr_pick_dly$989$next[0:0]$2721 \wr_pick$986 end sync always update \wr_pick_dly$989$next $0\wr_pick_dly$989$next[0:0]$2720 end attribute \src "libresoc.v:46612.3-46620.6" process $proc$libresoc.v:46612$2722 assign { } { } assign { } { } assign $0\wr_pick_dly$1008$next[0:0]$2723 $1\wr_pick_dly$1008$next[0:0]$2724 attribute \src "libresoc.v:46613.5-46613.29" switch \initial attribute \src "libresoc.v:46613.9-46613.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1008$next[0:0]$2724 1'0 case assign $1\wr_pick_dly$1008$next[0:0]$2724 \wr_pick$1005 end sync always update \wr_pick_dly$1008$next $0\wr_pick_dly$1008$next[0:0]$2723 end attribute \src "libresoc.v:46621.3-46650.6" process $proc$libresoc.v:46621$2725 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] attribute \src "libresoc.v:46622.5-46622.29" switch \initial attribute \src "libresoc.v:46622.9-46622.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } case assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end attribute \src "libresoc.v:46651.3-46659.6" process $proc$libresoc.v:46651$2726 assign { } { } assign { } { } assign $0\wr_pick_dly$1029$next[0:0]$2727 $1\wr_pick_dly$1029$next[0:0]$2728 attribute \src "libresoc.v:46652.5-46652.29" switch \initial attribute \src "libresoc.v:46652.9-46652.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1029$next[0:0]$2728 1'0 case assign $1\wr_pick_dly$1029$next[0:0]$2728 \wr_pick$1026 end sync always update \wr_pick_dly$1029$next $0\wr_pick_dly$1029$next[0:0]$2727 end attribute \src "libresoc.v:46660.3-46668.6" process $proc$libresoc.v:46660$2729 assign { } { } assign { } { } assign $0\wr_pick_dly$1047$next[0:0]$2730 $1\wr_pick_dly$1047$next[0:0]$2731 attribute \src "libresoc.v:46661.5-46661.29" switch \initial attribute \src "libresoc.v:46661.9-46661.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1047$next[0:0]$2731 1'0 case assign $1\wr_pick_dly$1047$next[0:0]$2731 \wr_pick$1044 end sync always update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2730 end attribute \src "libresoc.v:46669.3-46677.6" process $proc$libresoc.v:46669$2732 assign { } { } assign { } { } assign $0\wr_pick_dly$1069$next[0:0]$2733 $1\wr_pick_dly$1069$next[0:0]$2734 attribute \src "libresoc.v:46670.5-46670.29" switch \initial attribute \src "libresoc.v:46670.9-46670.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1069$next[0:0]$2734 1'0 case assign $1\wr_pick_dly$1069$next[0:0]$2734 \wr_pick$1066 end sync always update \wr_pick_dly$1069$next $0\wr_pick_dly$1069$next[0:0]$2733 end attribute \src "libresoc.v:46678.3-46707.6" process $proc$libresoc.v:46678$2735 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] attribute \src "libresoc.v:46679.5-46679.29" switch \initial attribute \src "libresoc.v:46679.9-46679.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } case assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end attribute \src "libresoc.v:46708.3-46716.6" process $proc$libresoc.v:46708$2736 assign { } { } assign { } { } assign $0\wr_pick_dly$1089$next[0:0]$2737 $1\wr_pick_dly$1089$next[0:0]$2738 attribute \src "libresoc.v:46709.5-46709.29" switch \initial attribute \src "libresoc.v:46709.9-46709.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1089$next[0:0]$2738 1'0 case assign $1\wr_pick_dly$1089$next[0:0]$2738 \wr_pick$1086 end sync always update \wr_pick_dly$1089$next $0\wr_pick_dly$1089$next[0:0]$2737 end attribute \src "libresoc.v:46717.3-46725.6" process $proc$libresoc.v:46717$2739 assign { } { } assign { } { } assign $0\wr_pick_dly$1109$next[0:0]$2740 $1\wr_pick_dly$1109$next[0:0]$2741 attribute \src "libresoc.v:46718.5-46718.29" switch \initial attribute \src "libresoc.v:46718.9-46718.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1109$next[0:0]$2741 1'0 case assign $1\wr_pick_dly$1109$next[0:0]$2741 \wr_pick$1106 end sync always update \wr_pick_dly$1109$next $0\wr_pick_dly$1109$next[0:0]$2740 end attribute \src "libresoc.v:46726.3-46734.6" process $proc$libresoc.v:46726$2742 assign { } { } assign { } { } assign $0\wr_pick_dly$1128$next[0:0]$2743 $1\wr_pick_dly$1128$next[0:0]$2744 attribute \src "libresoc.v:46727.5-46727.29" switch \initial attribute \src "libresoc.v:46727.9-46727.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1128$next[0:0]$2744 1'0 case assign $1\wr_pick_dly$1128$next[0:0]$2744 \wr_pick$1125 end sync always update \wr_pick_dly$1128$next $0\wr_pick_dly$1128$next[0:0]$2743 end attribute \src "libresoc.v:46735.3-46763.6" process $proc$libresoc.v:46735$2745 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] attribute \src "libresoc.v:46736.5-46736.29" switch \initial attribute \src "libresoc.v:46736.9-46736.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in case assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end attribute \src "libresoc.v:46764.3-46772.6" process $proc$libresoc.v:46764$2746 assign { } { } assign { } { } assign $0\wr_pick_dly$1146$next[0:0]$2747 $1\wr_pick_dly$1146$next[0:0]$2748 attribute \src "libresoc.v:46765.5-46765.29" switch \initial attribute \src "libresoc.v:46765.9-46765.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1146$next[0:0]$2748 1'0 case assign $1\wr_pick_dly$1146$next[0:0]$2748 \wr_pick$1143 end sync always update \wr_pick_dly$1146$next $0\wr_pick_dly$1146$next[0:0]$2747 end attribute \src "libresoc.v:46773.3-46801.6" process $proc$libresoc.v:46773$2749 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] attribute \src "libresoc.v:46774.5-46774.29" switch \initial attribute \src "libresoc.v:46774.9-46774.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a case assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end attribute \src "libresoc.v:46802.3-46810.6" process $proc$libresoc.v:46802$2750 assign { } { } assign { } { } assign $0\wr_pick_dly$1220$next[0:0]$2751 $1\wr_pick_dly$1220$next[0:0]$2752 attribute \src "libresoc.v:46803.5-46803.29" switch \initial attribute \src "libresoc.v:46803.9-46803.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1220$next[0:0]$2752 1'0 case assign $1\wr_pick_dly$1220$next[0:0]$2752 \wr_pick$1217 end sync always update \wr_pick_dly$1220$next $0\wr_pick_dly$1220$next[0:0]$2751 end attribute \src "libresoc.v:46811.3-46839.6" process $proc$libresoc.v:46811$2753 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] attribute \src "libresoc.v:46812.5-46812.29" switch \initial attribute \src "libresoc.v:46812.9-46812.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU__invert_out case assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end attribute \src "libresoc.v:46840.3-46848.6" process $proc$libresoc.v:46840$2754 assign { } { } assign { } { } assign $0\wr_pick_dly$1248$next[0:0]$2755 $1\wr_pick_dly$1248$next[0:0]$2756 attribute \src "libresoc.v:46841.5-46841.29" switch \initial attribute \src "libresoc.v:46841.9-46841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1248$next[0:0]$2756 1'0 case assign $1\wr_pick_dly$1248$next[0:0]$2756 \wr_pick$1245 end sync always update \wr_pick_dly$1248$next $0\wr_pick_dly$1248$next[0:0]$2755 end attribute \src "libresoc.v:46849.3-46877.6" process $proc$libresoc.v:46849$2757 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] attribute \src "libresoc.v:46850.5-46850.29" switch \initial attribute \src "libresoc.v:46850.9-46850.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU__write_cr0 case assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end attribute \src "libresoc.v:46878.3-46886.6" process $proc$libresoc.v:46878$2758 assign { } { } assign { } { } assign $0\wr_pick_dly$1268$next[0:0]$2759 $1\wr_pick_dly$1268$next[0:0]$2760 attribute \src "libresoc.v:46879.5-46879.29" switch \initial attribute \src "libresoc.v:46879.9-46879.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1268$next[0:0]$2760 1'0 case assign $1\wr_pick_dly$1268$next[0:0]$2760 \wr_pick$1265 end sync always update \wr_pick_dly$1268$next $0\wr_pick_dly$1268$next[0:0]$2759 end attribute \src "libresoc.v:46887.3-46895.6" process $proc$libresoc.v:46887$2761 assign { } { } assign { } { } assign $0\wr_pick_dly$1288$next[0:0]$2762 $1\wr_pick_dly$1288$next[0:0]$2763 attribute \src "libresoc.v:46888.5-46888.29" switch \initial attribute \src "libresoc.v:46888.9-46888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1288$next[0:0]$2763 1'0 case assign $1\wr_pick_dly$1288$next[0:0]$2763 \wr_pick$1285 end sync always update \wr_pick_dly$1288$next $0\wr_pick_dly$1288$next[0:0]$2762 end attribute \src "libresoc.v:46896.3-46924.6" process $proc$libresoc.v:46896$2764 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] attribute \src "libresoc.v:46897.5-46897.29" switch \initial attribute \src "libresoc.v:46897.9-46897.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU__input_carry case assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 end end case assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 end sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end attribute \src "libresoc.v:46925.3-46933.6" process $proc$libresoc.v:46925$2765 assign { } { } assign { } { } assign $0\wr_pick_dly$1308$next[0:0]$2766 $1\wr_pick_dly$1308$next[0:0]$2767 attribute \src "libresoc.v:46926.5-46926.29" switch \initial attribute \src "libresoc.v:46926.9-46926.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1308$next[0:0]$2767 1'0 case assign $1\wr_pick_dly$1308$next[0:0]$2767 \wr_pick$1305 end sync always update \wr_pick_dly$1308$next $0\wr_pick_dly$1308$next[0:0]$2766 end attribute \src "libresoc.v:46934.3-46942.6" process $proc$libresoc.v:46934$2768 assign { } { } assign { } { } assign $0\wr_pick_dly$1328$next[0:0]$2769 $1\wr_pick_dly$1328$next[0:0]$2770 attribute \src "libresoc.v:46935.5-46935.29" switch \initial attribute \src "libresoc.v:46935.9-46935.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1328$next[0:0]$2770 1'0 case assign $1\wr_pick_dly$1328$next[0:0]$2770 \wr_pick$1325 end sync always update \wr_pick_dly$1328$next $0\wr_pick_dly$1328$next[0:0]$2769 end attribute \src "libresoc.v:46943.3-46971.6" process $proc$libresoc.v:46943$2771 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] attribute \src "libresoc.v:46944.5-46944.29" switch \initial attribute \src "libresoc.v:46944.9-46944.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU__output_carry case assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end attribute \src "libresoc.v:46972.3-46980.6" process $proc$libresoc.v:46972$2772 assign { } { } assign { } { } assign $0\wr_pick_dly$1348$next[0:0]$2773 $1\wr_pick_dly$1348$next[0:0]$2774 attribute \src "libresoc.v:46973.5-46973.29" switch \initial attribute \src "libresoc.v:46973.9-46973.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1348$next[0:0]$2774 1'0 case assign $1\wr_pick_dly$1348$next[0:0]$2774 \wr_pick$1345 end sync always update \wr_pick_dly$1348$next $0\wr_pick_dly$1348$next[0:0]$2773 end attribute \src "libresoc.v:46981.3-47009.6" process $proc$libresoc.v:46981$2775 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] attribute \src "libresoc.v:46982.5-46982.29" switch \initial attribute \src "libresoc.v:46982.9-46982.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU__is_32bit case assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end attribute \src "libresoc.v:47010.3-47018.6" process $proc$libresoc.v:47010$2776 assign { } { } assign { } { } assign $0\wr_pick_dly$1395$next[0:0]$2777 $1\wr_pick_dly$1395$next[0:0]$2778 attribute \src "libresoc.v:47011.5-47011.29" switch \initial attribute \src "libresoc.v:47011.9-47011.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1395$next[0:0]$2778 1'0 case assign $1\wr_pick_dly$1395$next[0:0]$2778 \wr_pick$1392 end sync always update \wr_pick_dly$1395$next $0\wr_pick_dly$1395$next[0:0]$2777 end attribute \src "libresoc.v:47019.3-47047.6" process $proc$libresoc.v:47019$2779 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] attribute \src "libresoc.v:47020.5-47020.29" switch \initial attribute \src "libresoc.v:47020.9-47020.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU__is_signed case assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 end end case assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 end sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end attribute \src "libresoc.v:47048.3-47056.6" process $proc$libresoc.v:47048$2780 assign { } { } assign { } { } assign $0\wr_pick_dly$1411$next[0:0]$2781 $1\wr_pick_dly$1411$next[0:0]$2782 attribute \src "libresoc.v:47049.5-47049.29" switch \initial attribute \src "libresoc.v:47049.9-47049.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1411$next[0:0]$2782 1'0 case assign $1\wr_pick_dly$1411$next[0:0]$2782 \wr_pick$1408 end sync always update \wr_pick_dly$1411$next $0\wr_pick_dly$1411$next[0:0]$2781 end attribute \src "libresoc.v:47057.3-47065.6" process $proc$libresoc.v:47057$2783 assign { } { } assign { } { } assign $0\wr_pick_dly$1427$next[0:0]$2784 $1\wr_pick_dly$1427$next[0:0]$2785 attribute \src "libresoc.v:47058.5-47058.29" switch \initial attribute \src "libresoc.v:47058.9-47058.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1427$next[0:0]$2785 1'0 case assign $1\wr_pick_dly$1427$next[0:0]$2785 \wr_pick$1424 end sync always update \wr_pick_dly$1427$next $0\wr_pick_dly$1427$next[0:0]$2784 end attribute \src "libresoc.v:47066.3-47094.6" process $proc$libresoc.v:47066$2786 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] attribute \src "libresoc.v:47067.5-47067.29" switch \initial attribute \src "libresoc.v:47067.9-47067.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU__data_len case assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 end end case assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 end sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end attribute \src "libresoc.v:47095.3-47103.6" process $proc$libresoc.v:47095$2787 assign { } { } assign { } { } assign $0\wr_pick_dly$1461$next[0:0]$2788 $1\wr_pick_dly$1461$next[0:0]$2789 attribute \src "libresoc.v:47096.5-47096.29" switch \initial attribute \src "libresoc.v:47096.9-47096.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1461$next[0:0]$2789 1'0 case assign $1\wr_pick_dly$1461$next[0:0]$2789 \wr_pick$1458 end sync always update \wr_pick_dly$1461$next $0\wr_pick_dly$1461$next[0:0]$2788 end attribute \src "libresoc.v:47104.3-47132.6" process $proc$libresoc.v:47104$2790 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] attribute \src "libresoc.v:47105.5-47105.29" switch \initial attribute \src "libresoc.v:47105.9-47105.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU__insn case assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 end sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end attribute \src "libresoc.v:47133.3-47141.6" process $proc$libresoc.v:47133$2791 assign { } { } assign { } { } assign $0\wr_pick_dly$1477$next[0:0]$2792 $1\wr_pick_dly$1477$next[0:0]$2793 attribute \src "libresoc.v:47134.5-47134.29" switch \initial attribute \src "libresoc.v:47134.9-47134.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1477$next[0:0]$2793 1'0 case assign $1\wr_pick_dly$1477$next[0:0]$2793 \wr_pick$1474 end sync always update \wr_pick_dly$1477$next $0\wr_pick_dly$1477$next[0:0]$2792 end attribute \src "libresoc.v:47142.3-47150.6" process $proc$libresoc.v:47142$2794 assign { } { } assign { } { } assign $0\wr_pick_dly$1493$next[0:0]$2795 $1\wr_pick_dly$1493$next[0:0]$2796 attribute \src "libresoc.v:47143.5-47143.29" switch \initial attribute \src "libresoc.v:47143.9-47143.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1493$next[0:0]$2796 1'0 case assign $1\wr_pick_dly$1493$next[0:0]$2796 \wr_pick$1490 end sync always update \wr_pick_dly$1493$next $0\wr_pick_dly$1493$next[0:0]$2795 end attribute \src "libresoc.v:47151.3-47179.6" process $proc$libresoc.v:47151$2797 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] attribute \src "libresoc.v:47152.5-47152.29" switch \initial attribute \src "libresoc.v:47152.9-47152.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i[0:0] \issue_i case assign $3\fus_cu_issue_i[0:0] 1'0 end end case assign $1\fus_cu_issue_i[0:0] 1'0 end sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end attribute \src "libresoc.v:47180.3-47188.6" process $proc$libresoc.v:47180$2798 assign { } { } assign { } { } assign $0\wr_pick_dly$1509$next[0:0]$2799 $1\wr_pick_dly$1509$next[0:0]$2800 attribute \src "libresoc.v:47181.5-47181.29" switch \initial attribute \src "libresoc.v:47181.9-47181.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1509$next[0:0]$2800 1'0 case assign $1\wr_pick_dly$1509$next[0:0]$2800 \wr_pick$1506 end sync always update \wr_pick_dly$1509$next $0\wr_pick_dly$1509$next[0:0]$2799 end attribute \src "libresoc.v:47189.3-47217.6" process $proc$libresoc.v:47189$2801 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] attribute \src "libresoc.v:47190.5-47190.29" switch \initial attribute \src "libresoc.v:47190.9-47190.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i[3:0] \$228 case assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 end end case assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 end sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end attribute \src "libresoc.v:47218.3-47226.6" process $proc$libresoc.v:47218$2802 assign { } { } assign { } { } assign $0\wr_pick_dly$1545$next[0:0]$2803 $1\wr_pick_dly$1545$next[0:0]$2804 attribute \src "libresoc.v:47219.5-47219.29" switch \initial attribute \src "libresoc.v:47219.9-47219.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1545$next[0:0]$2804 1'0 case assign $1\wr_pick_dly$1545$next[0:0]$2804 \wr_pick$1542 end sync always update \wr_pick_dly$1545$next $0\wr_pick_dly$1545$next[0:0]$2803 end attribute \src "libresoc.v:47227.3-47235.6" process $proc$libresoc.v:47227$2805 assign { } { } assign { } { } assign $0\wr_pick_dly$1561$next[0:0]$2806 $1\wr_pick_dly$1561$next[0:0]$2807 attribute \src "libresoc.v:47228.5-47228.29" switch \initial attribute \src "libresoc.v:47228.9-47228.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1561$next[0:0]$2807 1'0 case assign $1\wr_pick_dly$1561$next[0:0]$2807 \wr_pick$1558 end sync always update \wr_pick_dly$1561$next $0\wr_pick_dly$1561$next[0:0]$2806 end attribute \src "libresoc.v:47236.3-47264.6" process $proc$libresoc.v:47236$2808 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] attribute \src "libresoc.v:47237.5-47237.29" switch \initial attribute \src "libresoc.v:47237.9-47237.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR__insn_type case assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end attribute \src "libresoc.v:47265.3-47273.6" process $proc$libresoc.v:47265$2809 assign { } { } assign { } { } assign $0\wr_pick_dly$1577$next[0:0]$2810 $1\wr_pick_dly$1577$next[0:0]$2811 attribute \src "libresoc.v:47266.5-47266.29" switch \initial attribute \src "libresoc.v:47266.9-47266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1577$next[0:0]$2811 1'0 case assign $1\wr_pick_dly$1577$next[0:0]$2811 \wr_pick$1574 end sync always update \wr_pick_dly$1577$next $0\wr_pick_dly$1577$next[0:0]$2810 end attribute \src "libresoc.v:47274.3-47302.6" process $proc$libresoc.v:47274$2812 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0] attribute \src "libresoc.v:47275.5-47275.29" switch \initial attribute \src "libresoc.v:47275.9-47275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] $2\fus_oper_i_alu_cr0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_cr0__fn_unit[13:0] $3\fus_oper_i_alu_cr0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] \dec_CR_CR__fn_unit case assign $3\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_cr0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0] end attribute \src "libresoc.v:47303.3-47311.6" process $proc$libresoc.v:47303$2813 assign { } { } assign { } { } assign $0\wr_pick_dly$1593$next[0:0]$2814 $1\wr_pick_dly$1593$next[0:0]$2815 attribute \src "libresoc.v:47304.5-47304.29" switch \initial attribute \src "libresoc.v:47304.9-47304.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1593$next[0:0]$2815 1'0 case assign $1\wr_pick_dly$1593$next[0:0]$2815 \wr_pick$1590 end sync always update \wr_pick_dly$1593$next $0\wr_pick_dly$1593$next[0:0]$2814 end attribute \src "libresoc.v:47312.3-47320.6" process $proc$libresoc.v:47312$2816 assign { } { } assign { } { } assign $0\wr_pick_dly$1635$next[0:0]$2817 $1\wr_pick_dly$1635$next[0:0]$2818 attribute \src "libresoc.v:47313.5-47313.29" switch \initial attribute \src "libresoc.v:47313.9-47313.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1635$next[0:0]$2818 1'0 case assign $1\wr_pick_dly$1635$next[0:0]$2818 \wr_pick$1632 end sync always update \wr_pick_dly$1635$next $0\wr_pick_dly$1635$next[0:0]$2817 end attribute \src "libresoc.v:47321.3-47349.6" process $proc$libresoc.v:47321$2819 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] attribute \src "libresoc.v:47322.5-47322.29" switch \initial attribute \src "libresoc.v:47322.9-47322.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR__insn case assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 end sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end attribute \src "libresoc.v:47350.3-47358.6" process $proc$libresoc.v:47350$2820 assign { } { } assign { } { } assign $0\wr_pick_dly$1654$next[0:0]$2821 $1\wr_pick_dly$1654$next[0:0]$2822 attribute \src "libresoc.v:47351.5-47351.29" switch \initial attribute \src "libresoc.v:47351.9-47351.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1654$next[0:0]$2822 1'0 case assign $1\wr_pick_dly$1654$next[0:0]$2822 \wr_pick$1651 end sync always update \wr_pick_dly$1654$next $0\wr_pick_dly$1654$next[0:0]$2821 end attribute \src "libresoc.v:47359.3-47387.6" process $proc$libresoc.v:47359$2823 assign { } { } assign { } { } assign $0\fus_cu_issue_i$13[0:0]$2824 $1\fus_cu_issue_i$13[0:0]$2825 attribute \src "libresoc.v:47360.5-47360.29" switch \initial attribute \src "libresoc.v:47360.9-47360.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$13[0:0]$2825 $2\fus_cu_issue_i$13[0:0]$2826 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$13[0:0]$2826 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$13[0:0]$2826 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$13[0:0]$2826 $3\fus_cu_issue_i$13[0:0]$2827 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$13[0:0]$2827 \issue_i case assign $3\fus_cu_issue_i$13[0:0]$2827 1'0 end end case assign $1\fus_cu_issue_i$13[0:0]$2825 1'0 end sync always update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2824 end attribute \src "libresoc.v:47388.3-47396.6" process $proc$libresoc.v:47388$2828 assign { } { } assign { } { } assign $0\wr_pick_dly$1670$next[0:0]$2829 $1\wr_pick_dly$1670$next[0:0]$2830 attribute \src "libresoc.v:47389.5-47389.29" switch \initial attribute \src "libresoc.v:47389.9-47389.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1670$next[0:0]$2830 1'0 case assign $1\wr_pick_dly$1670$next[0:0]$2830 \wr_pick$1667 end sync always update \wr_pick_dly$1670$next $0\wr_pick_dly$1670$next[0:0]$2829 end attribute \src "libresoc.v:47397.3-47405.6" process $proc$libresoc.v:47397$2831 assign { } { } assign { } { } assign $0\wr_pick_dly$1686$next[0:0]$2832 $1\wr_pick_dly$1686$next[0:0]$2833 attribute \src "libresoc.v:47398.5-47398.29" switch \initial attribute \src "libresoc.v:47398.9-47398.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1686$next[0:0]$2833 1'0 case assign $1\wr_pick_dly$1686$next[0:0]$2833 \wr_pick$1683 end sync always update \wr_pick_dly$1686$next $0\wr_pick_dly$1686$next[0:0]$2832 end attribute \src "libresoc.v:47406.3-47434.6" process $proc$libresoc.v:47406$2834 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$15[5:0]$2835 $1\fus_cu_rdmaskn_i$15[5:0]$2836 attribute \src "libresoc.v:47407.5-47407.29" switch \initial attribute \src "libresoc.v:47407.9-47407.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$15[5:0]$2836 $2\fus_cu_rdmaskn_i$15[5:0]$2837 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 6'000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 6'000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$15[5:0]$2837 $3\fus_cu_rdmaskn_i$15[5:0]$2838 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$15[5:0]$2838 \$250 case assign $3\fus_cu_rdmaskn_i$15[5:0]$2838 6'000000 end end case assign $1\fus_cu_rdmaskn_i$15[5:0]$2836 6'000000 end sync always update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2835 end attribute \src "libresoc.v:47435.3-47443.6" process $proc$libresoc.v:47435$2839 assign { } { } assign { } { } assign $0\wr_pick_dly$1702$next[0:0]$2840 $1\wr_pick_dly$1702$next[0:0]$2841 attribute \src "libresoc.v:47436.5-47436.29" switch \initial attribute \src "libresoc.v:47436.9-47436.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1702$next[0:0]$2841 1'0 case assign $1\wr_pick_dly$1702$next[0:0]$2841 \wr_pick$1699 end sync always update \wr_pick_dly$1702$next $0\wr_pick_dly$1702$next[0:0]$2840 end attribute \src "libresoc.v:47444.3-47472.6" process $proc$libresoc.v:47444$2842 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] attribute \src "libresoc.v:47445.5-47445.29" switch \initial attribute \src "libresoc.v:47445.9-47445.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH__cia case assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end end case assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end attribute \src "libresoc.v:47473.3-47481.6" process $proc$libresoc.v:47473$2843 assign { } { } assign { } { } assign $0\wr_pick_dly$1746$next[0:0]$2844 $1\wr_pick_dly$1746$next[0:0]$2845 attribute \src "libresoc.v:47474.5-47474.29" switch \initial attribute \src "libresoc.v:47474.9-47474.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1746$next[0:0]$2845 1'0 case assign $1\wr_pick_dly$1746$next[0:0]$2845 \wr_pick$1743 end sync always update \wr_pick_dly$1746$next $0\wr_pick_dly$1746$next[0:0]$2844 end attribute \src "libresoc.v:47482.3-47510.6" process $proc$libresoc.v:47482$2846 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] attribute \src "libresoc.v:47483.5-47483.29" switch \initial attribute \src "libresoc.v:47483.9-47483.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH__insn_type case assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end attribute \src "libresoc.v:47511.3-47519.6" process $proc$libresoc.v:47511$2847 assign { } { } assign { } { } assign $0\wr_pick_dly$1762$next[0:0]$2848 $1\wr_pick_dly$1762$next[0:0]$2849 attribute \src "libresoc.v:47512.5-47512.29" switch \initial attribute \src "libresoc.v:47512.9-47512.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1762$next[0:0]$2849 1'0 case assign $1\wr_pick_dly$1762$next[0:0]$2849 \wr_pick$1759 end sync always update \wr_pick_dly$1762$next $0\wr_pick_dly$1762$next[0:0]$2848 end attribute \src "libresoc.v:47520.3-47528.6" process $proc$libresoc.v:47520$2850 assign { } { } assign { } { } assign $0\wr_pick_dly$1786$next[0:0]$2851 $1\wr_pick_dly$1786$next[0:0]$2852 attribute \src "libresoc.v:47521.5-47521.29" switch \initial attribute \src "libresoc.v:47521.9-47521.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1786$next[0:0]$2852 1'0 case assign $1\wr_pick_dly$1786$next[0:0]$2852 \wr_pick$1783 end sync always update \wr_pick_dly$1786$next $0\wr_pick_dly$1786$next[0:0]$2851 end attribute \src "libresoc.v:47529.3-47557.6" process $proc$libresoc.v:47529$2853 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0] attribute \src "libresoc.v:47530.5-47530.29" switch \initial attribute \src "libresoc.v:47530.9-47530.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] $2\fus_oper_i_alu_branch0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_branch0__fn_unit[13:0] $3\fus_oper_i_alu_branch0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] \dec_BRANCH_BRANCH__fn_unit case assign $3\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_branch0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0] end attribute \src "libresoc.v:47558.3-47566.6" process $proc$libresoc.v:47558$2854 assign { } { } assign { } { } assign $0\wr_pick_dly$1806$next[0:0]$2855 $1\wr_pick_dly$1806$next[0:0]$2856 attribute \src "libresoc.v:47559.5-47559.29" switch \initial attribute \src "libresoc.v:47559.9-47559.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wr_pick_dly$1806$next[0:0]$2856 1'0 case assign $1\wr_pick_dly$1806$next[0:0]$2856 \wr_pick$1803 end sync always update \wr_pick_dly$1806$next $0\wr_pick_dly$1806$next[0:0]$2855 end attribute \src "libresoc.v:47567.3-47595.6" process $proc$libresoc.v:47567$2857 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] attribute \src "libresoc.v:47568.5-47568.29" switch \initial attribute \src "libresoc.v:47568.9-47568.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH__insn case assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 end sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end attribute \src "libresoc.v:47596.3-47625.6" process $proc$libresoc.v:47596$2858 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] attribute \src "libresoc.v:47597.5-47597.29" switch \initial attribute \src "libresoc.v:47597.9-47597.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__data } case assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end attribute \src "libresoc.v:47626.3-47654.6" process $proc$libresoc.v:47626$2859 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] attribute \src "libresoc.v:47627.5-47627.29" switch \initial attribute \src "libresoc.v:47627.9-47627.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk case assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 end end case assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 end sync always update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end attribute \src "libresoc.v:47655.3-47683.6" process $proc$libresoc.v:47655$2860 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] attribute \src "libresoc.v:47656.5-47656.29" switch \initial attribute \src "libresoc.v:47656.9-47656.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit case assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end attribute \src "libresoc.v:47684.3-47712.6" process $proc$libresoc.v:47684$2861 assign { } { } assign { } { } assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863 attribute \src "libresoc.v:47685.5-47685.29" switch \initial attribute \src "libresoc.v:47685.9-47685.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$16[0:0]$2863 $2\fus_cu_issue_i$16[0:0]$2864 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$16[0:0]$2864 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$16[0:0]$2864 $3\fus_cu_issue_i$16[0:0]$2865 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$16[0:0]$2865 \issue_i case assign $3\fus_cu_issue_i$16[0:0]$2865 1'0 end end case assign $1\fus_cu_issue_i$16[0:0]$2863 1'0 end sync always update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862 end attribute \src "libresoc.v:47713.3-47741.6" process $proc$libresoc.v:47713$2866 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868 attribute \src "libresoc.v:47714.5-47714.29" switch \initial attribute \src "libresoc.v:47714.9-47714.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 $2\fus_cu_rdmaskn_i$18[2:0]$2869 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$18[2:0]$2869 $3\fus_cu_rdmaskn_i$18[2:0]$2870 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 \$252 case assign $3\fus_cu_rdmaskn_i$18[2:0]$2870 3'000 end end case assign $1\fus_cu_rdmaskn_i$18[2:0]$2868 3'000 end sync always update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867 end attribute \src "libresoc.v:47742.3-47770.6" process $proc$libresoc.v:47742$2871 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] attribute \src "libresoc.v:47743.5-47743.29" switch \initial attribute \src "libresoc.v:47743.9-47743.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type case assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end attribute \src "libresoc.v:47771.3-47799.6" process $proc$libresoc.v:47771$2872 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0] attribute \src "libresoc.v:47772.5-47772.29" switch \initial attribute \src "libresoc.v:47772.9-47772.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] $2\fus_oper_i_alu_trap0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__fn_unit[13:0] $3\fus_oper_i_alu_trap0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] \core_core_fn_unit case assign $3\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_trap0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0] end attribute \src "libresoc.v:47800.3-47828.6" process $proc$libresoc.v:47800$2873 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] attribute \src "libresoc.v:47801.5-47801.29" switch \initial attribute \src "libresoc.v:47801.9-47801.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn case assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 end end case assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 end sync always update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end attribute \src "libresoc.v:47829.3-47857.6" process $proc$libresoc.v:47829$2874 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] attribute \src "libresoc.v:47830.5-47830.29" switch \initial attribute \src "libresoc.v:47830.9-47830.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr case assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end end case assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end attribute \src "libresoc.v:47858.3-47886.6" process $proc$libresoc.v:47858$2875 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] attribute \src "libresoc.v:47859.5-47859.29" switch \initial attribute \src "libresoc.v:47859.9-47859.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia case assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end end case assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end attribute \src "libresoc.v:47887.3-47915.6" process $proc$libresoc.v:47887$2876 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] attribute \src "libresoc.v:47888.5-47888.29" switch \initial attribute \src "libresoc.v:47888.9-47888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit case assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 end end case assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 end sync always update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end attribute \src "libresoc.v:47916.3-47944.6" process $proc$libresoc.v:47916$2877 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] attribute \src "libresoc.v:47917.5-47917.29" switch \initial attribute \src "libresoc.v:47917.9-47917.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype case assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 end end case assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 end sync always update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end attribute \src "libresoc.v:47945.3-47973.6" process $proc$libresoc.v:47945$2878 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] attribute \src "libresoc.v:47946.5-47946.29" switch \initial attribute \src "libresoc.v:47946.9-47946.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr case assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 end end case assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 end sync always update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end attribute \src "libresoc.v:47974.3-48002.6" process $proc$libresoc.v:47974$2879 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] attribute \src "libresoc.v:47975.5-47975.29" switch \initial attribute \src "libresoc.v:47975.9-47975.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } case assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 end end case assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 end sync always update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end attribute \src "libresoc.v:48003.3-48031.6" process $proc$libresoc.v:48003$2880 assign { } { } assign { } { } assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882 attribute \src "libresoc.v:48004.5-48004.29" switch \initial attribute \src "libresoc.v:48004.9-48004.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i$19[0:0]$2882 $2\fus_cu_issue_i$19[0:0]$2883 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_issue_i$19[0:0]$2883 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_issue_i$19[0:0]$2883 $3\fus_cu_issue_i$19[0:0]$2884 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_issue_i$19[0:0]$2884 \issue_i case assign $3\fus_cu_issue_i$19[0:0]$2884 1'0 end end case assign $1\fus_cu_issue_i$19[0:0]$2882 1'0 end sync always update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881 end attribute \src "libresoc.v:48032.3-48060.6" process $proc$libresoc.v:48032$2885 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887 attribute \src "libresoc.v:48033.5-48033.29" switch \initial attribute \src "libresoc.v:48033.9-48033.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 $2\fus_cu_rdmaskn_i$21[3:0]$2888 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 4'0000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_cu_rdmaskn_i$21[3:0]$2888 $3\fus_cu_rdmaskn_i$21[3:0]$2889 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 \$254 case assign $3\fus_cu_rdmaskn_i$21[3:0]$2889 4'0000 end end case assign $1\fus_cu_rdmaskn_i$21[3:0]$2887 4'0000 end sync always update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886 end attribute \src "libresoc.v:48061.3-48089.6" process $proc$libresoc.v:48061$2890 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] attribute \src "libresoc.v:48062.5-48062.29" switch \initial attribute \src "libresoc.v:48062.9-48062.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL__insn_type case assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 end end case assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 end sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end attribute \src "libresoc.v:48090.3-48118.6" process $proc$libresoc.v:48090$2891 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0] attribute \src "libresoc.v:48091.5-48091.29" switch \initial attribute \src "libresoc.v:48091.9-48091.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] $2\fus_oper_i_alu_logical0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__fn_unit[13:0] $3\fus_oper_i_alu_logical0__fn_unit[13:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] \dec_LOGICAL_LOGICAL__fn_unit case assign $3\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 end end case assign $1\fus_oper_i_alu_logical0__fn_unit[13:0] 14'00000000000000 end sync always update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0] end attribute \src "libresoc.v:48119.3-48148.6" process $proc$libresoc.v:48119$2892 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] attribute \src "libresoc.v:48120.5-48120.29" switch \initial attribute \src "libresoc.v:48120.9-48120.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__data } case assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end attribute \src "libresoc.v:48149.3-48178.6" process $proc$libresoc.v:48149$2893 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] attribute \src "libresoc.v:48150.5-48150.29" switch \initial attribute \src "libresoc.v:48150.9-48150.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__rc } case assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end attribute \src "libresoc.v:48179.3-48208.6" process $proc$libresoc.v:48179$2894 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] attribute \src "libresoc.v:48180.5-48180.29" switch \initial attribute \src "libresoc.v:48180.9-48180.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__oe } case assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end attribute \src "libresoc.v:48209.3-48237.6" process $proc$libresoc.v:48209$2895 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] attribute \src "libresoc.v:48210.5-48210.29" switch \initial attribute \src "libresoc.v:48210.9-48210.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL__invert_in case assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end attribute \src "libresoc.v:48238.3-48266.6" process $proc$libresoc.v:48238$2896 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] attribute \src "libresoc.v:48239.5-48239.29" switch \initial attribute \src "libresoc.v:48239.9-48239.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL__zero_a case assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end attribute \src "libresoc.v:48267.3-48295.6" process $proc$libresoc.v:48267$2897 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] attribute \src "libresoc.v:48268.5-48268.29" switch \initial attribute \src "libresoc.v:48268.9-48268.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL__input_carry case assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 end end case assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 end sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end attribute \src "libresoc.v:48296.3-48324.6" process $proc$libresoc.v:48296$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] attribute \src "libresoc.v:48297.5-48297.29" switch \initial attribute \src "libresoc.v:48297.9-48297.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL__invert_out case assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end attribute \src "libresoc.v:48325.3-48353.6" process $proc$libresoc.v:48325$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] attribute \src "libresoc.v:48326.5-48326.29" switch \initial attribute \src "libresoc.v:48326.9-48326.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL__write_cr0 case assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 end end case assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 end sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end connect \$1001 $ternary$libresoc.v:41907$1506_Y connect \$1003 $and$libresoc.v:41908$1507_Y connect \$1006 $and$libresoc.v:41909$1508_Y connect \$1010 $not$libresoc.v:41910$1509_Y connect \$1012 $and$libresoc.v:41911$1510_Y connect \$1019 $and$libresoc.v:41912$1511_Y connect \$1022 $ternary$libresoc.v:41913$1512_Y connect \$1024 $and$libresoc.v:41914$1513_Y connect \$1027 $and$libresoc.v:41915$1514_Y connect \$1031 $not$libresoc.v:41916$1515_Y connect \$1033 $and$libresoc.v:41917$1516_Y connect \$1037 $and$libresoc.v:41918$1517_Y connect \$1040 $ternary$libresoc.v:41919$1518_Y connect \$1042 $and$libresoc.v:41920$1519_Y connect \$1045 $and$libresoc.v:41921$1520_Y connect \$1049 $not$libresoc.v:41922$1521_Y connect \$1051 $and$libresoc.v:41923$1522_Y connect \$1059 $and$libresoc.v:41924$1523_Y connect \$1062 $ternary$libresoc.v:41925$1524_Y connect \$1064 $and$libresoc.v:41926$1525_Y connect \$1067 $and$libresoc.v:41927$1526_Y connect \$1071 $not$libresoc.v:41928$1527_Y connect \$1073 $and$libresoc.v:41929$1528_Y connect \$1079 $and$libresoc.v:41930$1529_Y connect \$1082 $ternary$libresoc.v:41931$1530_Y connect \$1084 $and$libresoc.v:41932$1531_Y connect \$1087 $and$libresoc.v:41933$1532_Y connect \$1091 $not$libresoc.v:41934$1533_Y connect \$1093 $and$libresoc.v:41935$1534_Y connect \$1099 $and$libresoc.v:41936$1535_Y connect \$1102 $ternary$libresoc.v:41937$1536_Y connect \$1104 $and$libresoc.v:41938$1537_Y connect \$1107 $and$libresoc.v:41939$1538_Y connect \$1111 $not$libresoc.v:41940$1539_Y connect \$1113 $and$libresoc.v:41941$1540_Y connect \$1118 $and$libresoc.v:41942$1541_Y connect \$1121 $ternary$libresoc.v:41943$1542_Y connect \$1123 $and$libresoc.v:41944$1543_Y connect \$1126 $and$libresoc.v:41945$1544_Y connect \$1130 $not$libresoc.v:41946$1545_Y connect \$1132 $and$libresoc.v:41947$1546_Y connect \$1136 $and$libresoc.v:41948$1547_Y connect \$1139 $ternary$libresoc.v:41949$1548_Y connect \$1141 $and$libresoc.v:41950$1549_Y connect \$1144 $and$libresoc.v:41951$1550_Y connect \$1147 $not$libresoc.v:41952$1551_Y connect \$1149 $and$libresoc.v:41953$1552_Y connect \$1152 $and$libresoc.v:41954$1553_Y connect \$1155 $ternary$libresoc.v:41955$1554_Y connect \$1158 $or$libresoc.v:41956$1555_Y connect \$1160 $or$libresoc.v:41957$1556_Y connect \$1162 $or$libresoc.v:41958$1557_Y connect \$1164 $or$libresoc.v:41959$1558_Y connect \$1166 $or$libresoc.v:41960$1559_Y connect \$1168 $or$libresoc.v:41961$1560_Y connect \$1170 $or$libresoc.v:41962$1561_Y connect \$1172 $or$libresoc.v:41963$1562_Y connect \$1174 $or$libresoc.v:41964$1563_Y connect \$1177 $or$libresoc.v:41965$1564_Y connect \$1179 $or$libresoc.v:41966$1565_Y connect \$1181 $or$libresoc.v:41967$1566_Y connect \$1183 $or$libresoc.v:41968$1567_Y connect \$1185 $or$libresoc.v:41969$1568_Y connect \$1187 $or$libresoc.v:41970$1569_Y connect \$1189 $or$libresoc.v:41971$1570_Y connect \$1191 $or$libresoc.v:41972$1571_Y connect \$1193 $or$libresoc.v:41973$1572_Y connect \$1195 $or$libresoc.v:41974$1573_Y connect \$1197 $or$libresoc.v:41975$1574_Y connect \$1199 $or$libresoc.v:41976$1575_Y connect \$1201 $or$libresoc.v:41977$1576_Y connect \$1203 $or$libresoc.v:41978$1577_Y connect \$1205 $or$libresoc.v:41979$1578_Y connect \$1207 $or$libresoc.v:41980$1579_Y connect \$1209 $or$libresoc.v:41981$1580_Y connect \$1211 $or$libresoc.v:41982$1581_Y connect \$1213 $and$libresoc.v:41983$1582_Y connect \$1215 $and$libresoc.v:41984$1583_Y connect \$1218 $and$libresoc.v:41985$1584_Y connect \$1221 $not$libresoc.v:41986$1585_Y connect \$1223 $and$libresoc.v:41987$1586_Y connect \$1226 $and$libresoc.v:41988$1587_Y connect \$1229 $ternary$libresoc.v:41989$1588_Y connect \$1231 $and$libresoc.v:41990$1589_Y connect \$1233 $and$libresoc.v:41991$1590_Y connect \$1235 $and$libresoc.v:41992$1591_Y connect \$1237 $and$libresoc.v:41993$1592_Y connect \$1239 $and$libresoc.v:41994$1593_Y connect \$1241 $and$libresoc.v:41995$1594_Y connect \$1243 $and$libresoc.v:41996$1595_Y connect \$1246 $and$libresoc.v:41997$1596_Y connect \$1249 $not$libresoc.v:41998$1597_Y connect \$1251 $and$libresoc.v:41999$1598_Y connect \$1254 $and$libresoc.v:42000$1599_Y connect \$1257 $sub$libresoc.v:42001$1600_Y connect \$1259 $sshl$libresoc.v:42002$1601_Y connect \$1261 $ternary$libresoc.v:42003$1602_Y connect \$1263 $and$libresoc.v:42004$1603_Y connect \$1266 $and$libresoc.v:42005$1604_Y connect \$1269 $not$libresoc.v:42006$1605_Y connect \$1271 $and$libresoc.v:42007$1606_Y connect \$1274 $and$libresoc.v:42008$1607_Y connect \$1277 $sub$libresoc.v:42009$1608_Y connect \$1279 $sshl$libresoc.v:42010$1609_Y connect \$1281 $ternary$libresoc.v:42011$1610_Y connect \$1283 $and$libresoc.v:42012$1611_Y connect \$1286 $and$libresoc.v:42013$1612_Y connect \$1289 $not$libresoc.v:42014$1613_Y connect \$1291 $and$libresoc.v:42015$1614_Y connect \$1294 $and$libresoc.v:42016$1615_Y connect \$1297 $sub$libresoc.v:42017$1616_Y connect \$1299 $sshl$libresoc.v:42018$1617_Y connect \$1301 $ternary$libresoc.v:42019$1618_Y connect \$1303 $and$libresoc.v:42020$1619_Y connect \$1306 $and$libresoc.v:42021$1620_Y connect \$1309 $not$libresoc.v:42022$1621_Y connect \$1311 $and$libresoc.v:42023$1622_Y connect \$1314 $and$libresoc.v:42024$1623_Y connect \$1317 $sub$libresoc.v:42025$1624_Y connect \$1319 $sshl$libresoc.v:42026$1625_Y connect \$1321 $ternary$libresoc.v:42027$1626_Y connect \$1323 $and$libresoc.v:42028$1627_Y connect \$1326 $and$libresoc.v:42029$1628_Y connect \$1329 $not$libresoc.v:42030$1629_Y connect \$1331 $and$libresoc.v:42031$1630_Y connect \$1334 $and$libresoc.v:42032$1631_Y connect \$1337 $sub$libresoc.v:42033$1632_Y connect \$1339 $sshl$libresoc.v:42034$1633_Y connect \$1341 $ternary$libresoc.v:42035$1634_Y connect \$1343 $and$libresoc.v:42036$1635_Y connect \$1346 $and$libresoc.v:42037$1636_Y connect \$1349 $not$libresoc.v:42038$1637_Y connect \$1351 $and$libresoc.v:42039$1638_Y connect \$1354 $and$libresoc.v:42040$1639_Y connect \$1357 $sub$libresoc.v:42041$1640_Y connect \$1359 $sshl$libresoc.v:42042$1641_Y connect \$1361 $ternary$libresoc.v:42043$1642_Y connect \$1363 $or$libresoc.v:42044$1643_Y connect \$1365 $or$libresoc.v:42045$1644_Y connect \$1367 $or$libresoc.v:42046$1645_Y connect \$1369 $or$libresoc.v:42047$1646_Y connect \$1371 $or$libresoc.v:42048$1647_Y connect \$1374 $or$libresoc.v:42049$1648_Y connect \$1376 $or$libresoc.v:42050$1649_Y connect \$1378 $or$libresoc.v:42051$1650_Y connect \$1380 $or$libresoc.v:42052$1651_Y connect \$1382 $or$libresoc.v:42053$1652_Y connect \$1384 $and$libresoc.v:42054$1653_Y connect \$1386 $and$libresoc.v:42055$1654_Y connect \$1388 $and$libresoc.v:42056$1655_Y connect \$1390 $and$libresoc.v:42057$1656_Y connect \$1393 $and$libresoc.v:42058$1657_Y connect \$1396 $not$libresoc.v:42059$1658_Y connect \$1398 $and$libresoc.v:42060$1659_Y connect \$1401 $and$libresoc.v:42061$1660_Y connect \$1404 $ternary$libresoc.v:42062$1661_Y connect \$1406 $and$libresoc.v:42063$1662_Y connect \$1409 $and$libresoc.v:42064$1663_Y connect \$1412 $not$libresoc.v:42065$1664_Y connect \$1414 $and$libresoc.v:42066$1665_Y connect \$1417 $and$libresoc.v:42067$1666_Y connect \$1420 $ternary$libresoc.v:42068$1667_Y connect \$1422 $and$libresoc.v:42069$1668_Y connect \$1425 $and$libresoc.v:42070$1669_Y connect \$1428 $not$libresoc.v:42071$1670_Y connect \$1430 $and$libresoc.v:42072$1671_Y connect \$1433 $and$libresoc.v:42073$1672_Y connect \$1436 $ternary$libresoc.v:42074$1673_Y connect \$1438 $or$libresoc.v:42075$1674_Y connect \$1440 $or$libresoc.v:42076$1675_Y connect \$1443 $or$libresoc.v:42077$1676_Y connect \$1445 $or$libresoc.v:42078$1677_Y connect \$1442 $pos$libresoc.v:42079$1679_Y connect \$1448 $and$libresoc.v:42080$1680_Y connect \$1450 $and$libresoc.v:42081$1681_Y connect \$1452 $and$libresoc.v:42082$1682_Y connect \$1454 $and$libresoc.v:42083$1683_Y connect \$1456 $and$libresoc.v:42084$1684_Y connect \$1459 $and$libresoc.v:42085$1685_Y connect \$1462 $not$libresoc.v:42086$1686_Y connect \$1464 $and$libresoc.v:42087$1687_Y connect \$1467 $and$libresoc.v:42088$1688_Y connect \$1470 $ternary$libresoc.v:42089$1689_Y connect \$1472 $and$libresoc.v:42090$1690_Y connect \$1475 $and$libresoc.v:42091$1691_Y connect \$1478 $not$libresoc.v:42092$1692_Y connect \$1480 $and$libresoc.v:42093$1693_Y connect \$1483 $and$libresoc.v:42094$1694_Y connect \$1486 $ternary$libresoc.v:42095$1695_Y connect \$1488 $and$libresoc.v:42096$1696_Y connect \$1491 $and$libresoc.v:42097$1697_Y connect \$1494 $not$libresoc.v:42098$1698_Y connect \$1496 $and$libresoc.v:42099$1699_Y connect \$1499 $and$libresoc.v:42100$1700_Y connect \$1502 $ternary$libresoc.v:42101$1701_Y connect \$1504 $and$libresoc.v:42102$1702_Y connect \$1507 $and$libresoc.v:42103$1703_Y connect \$1510 $not$libresoc.v:42104$1704_Y connect \$1512 $and$libresoc.v:42105$1705_Y connect \$1515 $and$libresoc.v:42106$1706_Y connect \$1518 $ternary$libresoc.v:42107$1707_Y connect \$1520 $or$libresoc.v:42108$1708_Y connect \$1522 $or$libresoc.v:42109$1709_Y connect \$1524 $or$libresoc.v:42110$1710_Y connect \$1526 $or$libresoc.v:42111$1711_Y connect \$1528 $or$libresoc.v:42112$1712_Y connect \$1530 $or$libresoc.v:42113$1713_Y connect \$1532 $and$libresoc.v:42114$1714_Y connect \$1534 $and$libresoc.v:42115$1715_Y connect \$1536 $and$libresoc.v:42116$1716_Y connect \$1538 $and$libresoc.v:42117$1717_Y connect \$1540 $and$libresoc.v:42118$1718_Y connect \$1543 $and$libresoc.v:42119$1719_Y connect \$1546 $not$libresoc.v:42120$1720_Y connect \$1548 $and$libresoc.v:42121$1721_Y connect \$1551 $and$libresoc.v:42122$1722_Y connect \$1554 $ternary$libresoc.v:42123$1723_Y connect \$1556 $and$libresoc.v:42124$1724_Y connect \$1559 $and$libresoc.v:42125$1725_Y connect \$1562 $not$libresoc.v:42126$1726_Y connect \$1564 $and$libresoc.v:42127$1727_Y connect \$1567 $and$libresoc.v:42128$1728_Y connect \$1570 $ternary$libresoc.v:42129$1729_Y connect \$1572 $and$libresoc.v:42130$1730_Y connect \$1575 $and$libresoc.v:42131$1731_Y connect \$1578 $not$libresoc.v:42132$1732_Y connect \$1580 $and$libresoc.v:42133$1733_Y connect \$1583 $and$libresoc.v:42134$1734_Y connect \$1586 $ternary$libresoc.v:42135$1735_Y connect \$1588 $and$libresoc.v:42136$1736_Y connect \$1591 $and$libresoc.v:42137$1737_Y connect \$1594 $not$libresoc.v:42138$1738_Y connect \$1596 $and$libresoc.v:42139$1739_Y connect \$1599 $and$libresoc.v:42140$1740_Y connect \$1602 $ternary$libresoc.v:42141$1741_Y connect \$1605 $or$libresoc.v:42142$1742_Y connect \$1607 $or$libresoc.v:42143$1743_Y connect \$1609 $or$libresoc.v:42144$1744_Y connect \$1604 $pos$libresoc.v:42145$1746_Y connect \$1613 $or$libresoc.v:42146$1747_Y connect \$1615 $or$libresoc.v:42147$1748_Y connect \$1617 $or$libresoc.v:42148$1749_Y connect \$1612 $pos$libresoc.v:42149$1751_Y connect \$1620 $and$libresoc.v:42150$1752_Y connect \$1622 $and$libresoc.v:42151$1753_Y connect \$1624 $and$libresoc.v:42152$1754_Y connect \$1626 $and$libresoc.v:42153$1755_Y connect \$1628 $and$libresoc.v:42154$1756_Y connect \$1630 $and$libresoc.v:42155$1757_Y connect \$1633 $and$libresoc.v:42156$1758_Y connect \$1637 $not$libresoc.v:42157$1759_Y connect \$1639 $and$libresoc.v:42158$1760_Y connect \$1644 $and$libresoc.v:42159$1761_Y connect \$1647 $ternary$libresoc.v:42160$1762_Y connect \$1649 $and$libresoc.v:42161$1763_Y connect \$1652 $and$libresoc.v:42162$1764_Y connect \$1655 $not$libresoc.v:42163$1765_Y connect \$1657 $and$libresoc.v:42164$1766_Y connect \$1660 $and$libresoc.v:42165$1767_Y connect \$1663 $ternary$libresoc.v:42166$1768_Y connect \$1665 $and$libresoc.v:42167$1769_Y connect \$1668 $and$libresoc.v:42168$1770_Y connect \$1671 $not$libresoc.v:42169$1771_Y connect \$1673 $and$libresoc.v:42170$1772_Y connect \$1676 $and$libresoc.v:42171$1773_Y connect \$1679 $ternary$libresoc.v:42172$1774_Y connect \$1681 $and$libresoc.v:42173$1775_Y connect \$1684 $and$libresoc.v:42174$1776_Y connect \$1687 $not$libresoc.v:42175$1777_Y connect \$1689 $and$libresoc.v:42176$1778_Y connect \$1692 $and$libresoc.v:42177$1779_Y connect \$1695 $ternary$libresoc.v:42178$1780_Y connect \$1697 $and$libresoc.v:42179$1781_Y connect \$1700 $and$libresoc.v:42180$1782_Y connect \$1703 $not$libresoc.v:42181$1783_Y connect \$1705 $and$libresoc.v:42182$1784_Y connect \$1708 $and$libresoc.v:42183$1785_Y connect \$1711 $ternary$libresoc.v:42184$1786_Y connect \$1713 $or$libresoc.v:42185$1787_Y connect \$1715 $or$libresoc.v:42186$1788_Y connect \$1717 $or$libresoc.v:42187$1789_Y connect \$1719 $or$libresoc.v:42188$1790_Y connect \$1721 $or$libresoc.v:42189$1791_Y connect \$1723 $or$libresoc.v:42190$1792_Y connect \$1725 $or$libresoc.v:42191$1793_Y connect \$1727 $or$libresoc.v:42192$1794_Y connect \$1729 $or$libresoc.v:42193$1795_Y connect \$1731 $or$libresoc.v:42194$1796_Y connect \$1733 $or$libresoc.v:42195$1797_Y connect \$1735 $or$libresoc.v:42196$1798_Y connect \$1737 $and$libresoc.v:42197$1799_Y connect \$1739 $and$libresoc.v:42198$1800_Y connect \$1741 $and$libresoc.v:42199$1801_Y connect \$1744 $and$libresoc.v:42200$1802_Y connect \$1747 $not$libresoc.v:42201$1803_Y connect \$1749 $and$libresoc.v:42202$1804_Y connect \$1752 $and$libresoc.v:42203$1805_Y connect \$1755 $ternary$libresoc.v:42204$1806_Y connect \$1757 $and$libresoc.v:42205$1807_Y connect \$1760 $and$libresoc.v:42206$1808_Y connect \$1763 $not$libresoc.v:42207$1809_Y connect \$1765 $and$libresoc.v:42208$1810_Y connect \$1768 $and$libresoc.v:42209$1811_Y connect \$1771 $ternary$libresoc.v:42210$1812_Y connect \$1773 $or$libresoc.v:42211$1813_Y connect \$1776 $or$libresoc.v:42212$1814_Y connect \$1775 $pos$libresoc.v:42213$1816_Y connect \$1779 $and$libresoc.v:42214$1817_Y connect \$1781 $and$libresoc.v:42215$1818_Y connect \$1784 $and$libresoc.v:42216$1819_Y connect \$1787 $not$libresoc.v:42217$1820_Y connect \$1789 $and$libresoc.v:42218$1821_Y connect \$1792 $and$libresoc.v:42219$1822_Y connect \$1795 $ternary$libresoc.v:42220$1823_Y connect \$1797 $pos$libresoc.v:42221$1825_Y connect \$1799 $and$libresoc.v:42222$1826_Y connect \$1801 $and$libresoc.v:42223$1827_Y connect \$1804 $and$libresoc.v:42224$1828_Y connect \$1807 $not$libresoc.v:42225$1829_Y connect \$1809 $and$libresoc.v:42226$1830_Y connect \$1812 $and$libresoc.v:42227$1831_Y connect \$1815 $ternary$libresoc.v:42228$1832_Y connect \$182 $and$libresoc.v:42229$1833_Y connect \$181 $reduce_or$libresoc.v:42230$1834_Y connect \$186 $and$libresoc.v:42231$1835_Y connect \$185 $reduce_or$libresoc.v:42232$1836_Y connect \$190 $and$libresoc.v:42233$1837_Y connect \$189 $reduce_or$libresoc.v:42234$1838_Y connect \$194 $and$libresoc.v:42235$1839_Y connect \$193 $reduce_or$libresoc.v:42236$1840_Y connect \$198 $and$libresoc.v:42237$1841_Y connect \$197 $reduce_or$libresoc.v:42238$1842_Y connect \$202 $and$libresoc.v:42239$1843_Y connect \$201 $reduce_or$libresoc.v:42240$1844_Y connect \$206 $and$libresoc.v:42241$1845_Y connect \$205 $reduce_or$libresoc.v:42242$1846_Y connect \$210 $and$libresoc.v:42243$1847_Y connect \$209 $reduce_or$libresoc.v:42244$1848_Y connect \$214 $and$libresoc.v:42245$1849_Y connect \$213 $reduce_or$libresoc.v:42246$1850_Y connect \$218 $and$libresoc.v:42247$1851_Y connect \$217 $reduce_or$libresoc.v:42248$1852_Y connect \$221 $ne$libresoc.v:42249$1853_Y connect \$224 $sub$libresoc.v:42250$1854_Y connect \$226 $ne$libresoc.v:42251$1855_Y connect \$229 $and$libresoc.v:42252$1856_Y connect \$231 $and$libresoc.v:42253$1857_Y connect \$233 $eq$libresoc.v:42254$1858_Y connect \$235 $or$libresoc.v:42255$1859_Y connect \$237 $and$libresoc.v:42256$1860_Y connect \$239 $or$libresoc.v:42257$1861_Y connect \$241 $eq$libresoc.v:42258$1862_Y connect \$243 $and$libresoc.v:42259$1863_Y connect \$245 $eq$libresoc.v:42260$1864_Y connect \$247 $or$libresoc.v:42261$1865_Y connect \$228 $not$libresoc.v:42262$1866_Y connect \$250 $not$libresoc.v:42263$1867_Y connect \$252 $not$libresoc.v:42264$1868_Y connect \$254 $not$libresoc.v:42265$1869_Y connect \$257 $and$libresoc.v:42266$1870_Y connect \$259 $and$libresoc.v:42267$1871_Y connect \$261 $eq$libresoc.v:42268$1872_Y connect \$263 $or$libresoc.v:42269$1873_Y connect \$265 $and$libresoc.v:42270$1874_Y connect \$267 $or$libresoc.v:42271$1875_Y connect \$256 $not$libresoc.v:42272$1876_Y connect \$271 $and$libresoc.v:42273$1877_Y connect \$273 $and$libresoc.v:42274$1878_Y connect \$275 $eq$libresoc.v:42275$1879_Y connect \$277 $or$libresoc.v:42276$1880_Y connect \$279 $and$libresoc.v:42277$1881_Y connect \$281 $or$libresoc.v:42278$1882_Y connect \$283 $and$libresoc.v:42279$1883_Y connect \$285 $and$libresoc.v:42280$1884_Y connect \$287 $eq$libresoc.v:42281$1885_Y connect \$289 $or$libresoc.v:42282$1886_Y connect \$291 $eq$libresoc.v:42283$1887_Y connect \$293 $and$libresoc.v:42284$1888_Y connect \$295 $eq$libresoc.v:42285$1889_Y connect \$297 $or$libresoc.v:42286$1890_Y connect \$270 $not$libresoc.v:42287$1891_Y connect \$301 $and$libresoc.v:42288$1892_Y connect \$303 $and$libresoc.v:42289$1893_Y connect \$305 $eq$libresoc.v:42290$1894_Y connect \$307 $or$libresoc.v:42291$1895_Y connect \$309 $and$libresoc.v:42292$1896_Y connect \$311 $or$libresoc.v:42293$1897_Y connect \$300 $not$libresoc.v:42294$1898_Y connect \$315 $and$libresoc.v:42295$1899_Y connect \$317 $and$libresoc.v:42296$1900_Y connect \$319 $eq$libresoc.v:42297$1901_Y connect \$321 $or$libresoc.v:42298$1902_Y connect \$323 $and$libresoc.v:42299$1903_Y connect \$325 $or$libresoc.v:42300$1904_Y connect \$314 $not$libresoc.v:42301$1905_Y connect \$329 $and$libresoc.v:42302$1906_Y connect \$331 $and$libresoc.v:42303$1907_Y connect \$333 $eq$libresoc.v:42304$1908_Y connect \$335 $or$libresoc.v:42305$1909_Y connect \$337 $and$libresoc.v:42306$1910_Y connect \$339 $or$libresoc.v:42307$1911_Y connect \$341 $eq$libresoc.v:42308$1912_Y connect \$343 $and$libresoc.v:42309$1913_Y connect \$345 $eq$libresoc.v:42310$1914_Y connect \$347 $or$libresoc.v:42311$1915_Y connect \$328 $not$libresoc.v:42312$1916_Y connect \$350 $not$libresoc.v:42313$1917_Y connect \$352 $and$libresoc.v:42314$1918_Y connect \$354 $and$libresoc.v:42315$1919_Y connect \$356 $not$libresoc.v:42316$1920_Y connect \$358 $and$libresoc.v:42317$1921_Y connect \$360 $and$libresoc.v:42318$1922_Y connect \$362 $ternary$libresoc.v:42319$1923_Y connect \$364 $and$libresoc.v:42320$1924_Y connect \$366 $and$libresoc.v:42321$1925_Y connect \$368 $not$libresoc.v:42322$1926_Y connect \$370 $and$libresoc.v:42323$1927_Y connect \$372 $and$libresoc.v:42324$1928_Y connect \$374 $ternary$libresoc.v:42325$1929_Y connect \$376 $and$libresoc.v:42326$1930_Y connect \$378 $and$libresoc.v:42327$1931_Y connect \$380 $not$libresoc.v:42328$1932_Y connect \$382 $and$libresoc.v:42329$1933_Y connect \$384 $and$libresoc.v:42330$1934_Y connect \$386 $ternary$libresoc.v:42331$1935_Y connect \$388 $and$libresoc.v:42332$1936_Y connect \$390 $and$libresoc.v:42333$1937_Y connect \$392 $not$libresoc.v:42334$1938_Y connect \$394 $and$libresoc.v:42335$1939_Y connect \$396 $and$libresoc.v:42336$1940_Y connect \$398 $ternary$libresoc.v:42337$1941_Y connect \$400 $and$libresoc.v:42338$1942_Y connect \$402 $and$libresoc.v:42339$1943_Y connect \$404 $not$libresoc.v:42340$1944_Y connect \$406 $and$libresoc.v:42341$1945_Y connect \$408 $and$libresoc.v:42342$1946_Y connect \$410 $ternary$libresoc.v:42343$1947_Y connect \$412 $and$libresoc.v:42344$1948_Y connect \$414 $and$libresoc.v:42345$1949_Y connect \$416 $not$libresoc.v:42346$1950_Y connect \$418 $and$libresoc.v:42347$1951_Y connect \$420 $and$libresoc.v:42348$1952_Y connect \$422 $ternary$libresoc.v:42349$1953_Y connect \$424 $and$libresoc.v:42350$1954_Y connect \$426 $and$libresoc.v:42351$1955_Y connect \$428 $not$libresoc.v:42352$1956_Y connect \$430 $and$libresoc.v:42353$1957_Y connect \$432 $and$libresoc.v:42354$1958_Y connect \$434 $ternary$libresoc.v:42355$1959_Y connect \$436 $and$libresoc.v:42356$1960_Y connect \$438 $and$libresoc.v:42357$1961_Y connect \$440 $not$libresoc.v:42358$1962_Y connect \$442 $and$libresoc.v:42359$1963_Y connect \$444 $and$libresoc.v:42360$1964_Y connect \$446 $ternary$libresoc.v:42361$1965_Y connect \$448 $and$libresoc.v:42362$1966_Y connect \$450 $and$libresoc.v:42363$1967_Y connect \$452 $not$libresoc.v:42364$1968_Y connect \$454 $and$libresoc.v:42365$1969_Y connect \$456 $and$libresoc.v:42366$1970_Y connect \$458 $ternary$libresoc.v:42367$1971_Y connect \$460 $and$libresoc.v:42368$1972_Y connect \$462 $and$libresoc.v:42369$1973_Y connect \$464 $not$libresoc.v:42370$1974_Y connect \$466 $and$libresoc.v:42371$1975_Y connect \$468 $and$libresoc.v:42372$1976_Y connect \$470 $ternary$libresoc.v:42373$1977_Y connect \$472 $and$libresoc.v:42374$1978_Y connect \$474 $and$libresoc.v:42375$1979_Y connect \$476 $not$libresoc.v:42376$1980_Y connect \$478 $and$libresoc.v:42377$1981_Y connect \$480 $and$libresoc.v:42378$1982_Y connect \$482 $ternary$libresoc.v:42379$1983_Y connect \$484 $and$libresoc.v:42380$1984_Y connect \$486 $and$libresoc.v:42381$1985_Y connect \$488 $not$libresoc.v:42382$1986_Y connect \$490 $and$libresoc.v:42383$1987_Y connect \$492 $and$libresoc.v:42384$1988_Y connect \$494 $ternary$libresoc.v:42385$1989_Y connect \$496 $and$libresoc.v:42386$1990_Y connect \$498 $and$libresoc.v:42387$1991_Y connect \$500 $not$libresoc.v:42388$1992_Y connect \$502 $and$libresoc.v:42389$1993_Y connect \$504 $and$libresoc.v:42390$1994_Y connect \$506 $ternary$libresoc.v:42391$1995_Y connect \$508 $and$libresoc.v:42392$1996_Y connect \$510 $and$libresoc.v:42393$1997_Y connect \$512 $not$libresoc.v:42394$1998_Y connect \$514 $and$libresoc.v:42395$1999_Y connect \$516 $and$libresoc.v:42396$2000_Y connect \$518 $ternary$libresoc.v:42397$2001_Y connect \$520 $and$libresoc.v:42398$2002_Y connect \$522 $and$libresoc.v:42399$2003_Y connect \$524 $not$libresoc.v:42400$2004_Y connect \$526 $and$libresoc.v:42401$2005_Y connect \$528 $and$libresoc.v:42402$2006_Y connect \$530 $ternary$libresoc.v:42403$2007_Y connect \$532 $and$libresoc.v:42404$2008_Y connect \$534 $and$libresoc.v:42405$2009_Y connect \$536 $not$libresoc.v:42406$2010_Y connect \$538 $and$libresoc.v:42407$2011_Y connect \$540 $and$libresoc.v:42408$2012_Y connect \$542 $ternary$libresoc.v:42409$2013_Y connect \$544 $and$libresoc.v:42410$2014_Y connect \$546 $and$libresoc.v:42411$2015_Y connect \$548 $not$libresoc.v:42412$2016_Y connect \$550 $and$libresoc.v:42413$2017_Y connect \$552 $and$libresoc.v:42414$2018_Y connect \$554 $ternary$libresoc.v:42415$2019_Y connect \$556 $and$libresoc.v:42416$2020_Y connect \$558 $and$libresoc.v:42417$2021_Y connect \$560 $not$libresoc.v:42418$2022_Y connect \$562 $and$libresoc.v:42419$2023_Y connect \$564 $and$libresoc.v:42420$2024_Y connect \$566 $ternary$libresoc.v:42421$2025_Y connect \$568 $and$libresoc.v:42422$2026_Y connect \$570 $and$libresoc.v:42423$2027_Y connect \$572 $not$libresoc.v:42424$2028_Y connect \$574 $and$libresoc.v:42425$2029_Y connect \$576 $and$libresoc.v:42426$2030_Y connect \$578 $ternary$libresoc.v:42427$2031_Y connect \$581 $or$libresoc.v:42428$2032_Y connect \$583 $or$libresoc.v:42429$2033_Y connect \$585 $or$libresoc.v:42430$2034_Y connect \$587 $or$libresoc.v:42431$2035_Y connect \$589 $or$libresoc.v:42432$2036_Y connect \$591 $or$libresoc.v:42433$2037_Y connect \$593 $or$libresoc.v:42434$2038_Y connect \$595 $or$libresoc.v:42435$2039_Y connect \$597 $or$libresoc.v:42436$2040_Y connect \$599 $or$libresoc.v:42437$2041_Y connect \$601 $or$libresoc.v:42438$2042_Y connect \$603 $or$libresoc.v:42439$2043_Y connect \$605 $or$libresoc.v:42440$2044_Y connect \$607 $or$libresoc.v:42441$2045_Y connect \$609 $or$libresoc.v:42442$2046_Y connect \$611 $or$libresoc.v:42443$2047_Y connect \$613 $or$libresoc.v:42444$2048_Y connect \$615 $or$libresoc.v:42445$2049_Y connect \$617 $reduce_or$libresoc.v:42446$2050_Y connect \$619 $and$libresoc.v:42447$2051_Y connect \$621 $and$libresoc.v:42448$2052_Y connect \$623 $eq$libresoc.v:42449$2053_Y connect \$625 $or$libresoc.v:42450$2054_Y connect \$627 $and$libresoc.v:42451$2055_Y connect \$629 $or$libresoc.v:42452$2056_Y connect \$631 $and$libresoc.v:42453$2057_Y connect \$633 $and$libresoc.v:42454$2058_Y connect \$635 $not$libresoc.v:42455$2059_Y connect \$637 $and$libresoc.v:42456$2060_Y connect \$639 $and$libresoc.v:42457$2061_Y connect \$641 $ternary$libresoc.v:42458$2062_Y connect \$643 $and$libresoc.v:42459$2063_Y connect \$645 $and$libresoc.v:42460$2064_Y connect \$647 $not$libresoc.v:42461$2065_Y connect \$649 $and$libresoc.v:42462$2066_Y connect \$651 $and$libresoc.v:42463$2067_Y connect \$653 $ternary$libresoc.v:42464$2068_Y connect \$655 $and$libresoc.v:42465$2069_Y connect \$657 $and$libresoc.v:42466$2070_Y connect \$659 $not$libresoc.v:42467$2071_Y connect \$661 $and$libresoc.v:42468$2072_Y connect \$663 $and$libresoc.v:42469$2073_Y connect \$665 $ternary$libresoc.v:42470$2074_Y connect \$667 $and$libresoc.v:42471$2075_Y connect \$669 $and$libresoc.v:42472$2076_Y connect \$671 $not$libresoc.v:42473$2077_Y connect \$673 $and$libresoc.v:42474$2078_Y connect \$675 $and$libresoc.v:42475$2079_Y connect \$677 $ternary$libresoc.v:42476$2080_Y connect \$679 $and$libresoc.v:42477$2081_Y connect \$681 $and$libresoc.v:42478$2082_Y connect \$683 $not$libresoc.v:42479$2083_Y connect \$685 $and$libresoc.v:42480$2084_Y connect \$687 $and$libresoc.v:42481$2085_Y connect \$689 $ternary$libresoc.v:42482$2086_Y connect \$691 $and$libresoc.v:42483$2087_Y connect \$693 $and$libresoc.v:42484$2088_Y connect \$695 $not$libresoc.v:42485$2089_Y connect \$697 $and$libresoc.v:42486$2090_Y connect \$699 $and$libresoc.v:42487$2091_Y connect \$701 $ternary$libresoc.v:42488$2092_Y connect \$704 $or$libresoc.v:42489$2093_Y connect \$706 $or$libresoc.v:42490$2094_Y connect \$708 $or$libresoc.v:42491$2095_Y connect \$710 $or$libresoc.v:42492$2096_Y connect \$712 $or$libresoc.v:42493$2097_Y connect \$703 $pos$libresoc.v:42494$2099_Y connect \$715 $eq$libresoc.v:42495$2100_Y connect \$717 $and$libresoc.v:42496$2101_Y connect \$719 $eq$libresoc.v:42497$2102_Y connect \$721 $or$libresoc.v:42498$2103_Y connect \$723 $and$libresoc.v:42499$2104_Y connect \$725 $and$libresoc.v:42500$2105_Y connect \$727 $not$libresoc.v:42501$2106_Y connect \$729 $and$libresoc.v:42502$2107_Y connect \$731 $and$libresoc.v:42503$2108_Y connect \$733 $ternary$libresoc.v:42504$2109_Y connect \$735 $and$libresoc.v:42505$2110_Y connect \$737 $and$libresoc.v:42506$2111_Y connect \$739 $not$libresoc.v:42507$2112_Y connect \$741 $and$libresoc.v:42508$2113_Y connect \$743 $and$libresoc.v:42509$2114_Y connect \$745 $ternary$libresoc.v:42510$2115_Y connect \$747 $and$libresoc.v:42511$2116_Y connect \$749 $and$libresoc.v:42512$2117_Y connect \$751 $not$libresoc.v:42513$2118_Y connect \$753 $and$libresoc.v:42514$2119_Y connect \$755 $and$libresoc.v:42515$2120_Y connect \$757 $ternary$libresoc.v:42516$2121_Y connect \$760 $or$libresoc.v:42517$2122_Y connect \$762 $or$libresoc.v:42518$2123_Y connect \$759 $pos$libresoc.v:42519$2125_Y connect \$765 $and$libresoc.v:42520$2126_Y connect \$767 $and$libresoc.v:42521$2127_Y connect \$769 $eq$libresoc.v:42522$2128_Y connect \$771 $or$libresoc.v:42523$2129_Y connect \$773 $and$libresoc.v:42524$2130_Y connect \$775 $and$libresoc.v:42525$2131_Y connect \$777 $not$libresoc.v:42526$2132_Y connect \$779 $and$libresoc.v:42527$2133_Y connect \$781 $and$libresoc.v:42528$2134_Y connect \$783 $ternary$libresoc.v:42529$2135_Y connect \$785 $and$libresoc.v:42530$2136_Y connect \$787 $and$libresoc.v:42531$2137_Y connect \$789 $not$libresoc.v:42532$2138_Y connect \$791 $and$libresoc.v:42533$2139_Y connect \$793 $and$libresoc.v:42534$2140_Y connect \$795 $ternary$libresoc.v:42535$2141_Y connect \$797 $and$libresoc.v:42536$2142_Y connect \$799 $and$libresoc.v:42537$2143_Y connect \$801 $not$libresoc.v:42538$2144_Y connect \$803 $and$libresoc.v:42539$2145_Y connect \$805 $and$libresoc.v:42540$2146_Y connect \$807 $sub$libresoc.v:42541$2147_Y connect \$809 $sshl$libresoc.v:42542$2148_Y connect \$811 $ternary$libresoc.v:42543$2149_Y connect \$813 $and$libresoc.v:42544$2150_Y connect \$815 $and$libresoc.v:42545$2151_Y connect \$817 $not$libresoc.v:42546$2152_Y connect \$819 $and$libresoc.v:42547$2153_Y connect \$821 $and$libresoc.v:42548$2154_Y connect \$823 $sub$libresoc.v:42549$2155_Y connect \$825 $sshl$libresoc.v:42550$2156_Y connect \$827 $ternary$libresoc.v:42551$2157_Y connect \$830 $or$libresoc.v:42552$2158_Y connect \$832 $and$libresoc.v:42553$2159_Y connect \$834 $and$libresoc.v:42554$2160_Y connect \$836 $not$libresoc.v:42555$2161_Y connect \$838 $and$libresoc.v:42556$2162_Y connect \$840 $and$libresoc.v:42557$2163_Y connect \$842 $sub$libresoc.v:42558$2164_Y connect \$844 $sshl$libresoc.v:42559$2165_Y connect \$846 $ternary$libresoc.v:42560$2166_Y connect \$848 $and$libresoc.v:42561$2167_Y connect \$850 $and$libresoc.v:42562$2168_Y connect \$852 $not$libresoc.v:42563$2169_Y connect \$854 $and$libresoc.v:42564$2170_Y connect \$856 $and$libresoc.v:42565$2171_Y connect \$858 $sub$libresoc.v:42566$2172_Y connect \$860 $sshl$libresoc.v:42567$2173_Y connect \$862 $ternary$libresoc.v:42568$2174_Y connect \$864 $and$libresoc.v:42569$2175_Y connect \$866 $and$libresoc.v:42570$2176_Y connect \$868 $not$libresoc.v:42571$2177_Y connect \$870 $and$libresoc.v:42572$2178_Y connect \$872 $and$libresoc.v:42573$2179_Y connect \$874 $ternary$libresoc.v:42574$2180_Y connect \$876 $and$libresoc.v:42575$2181_Y connect \$878 $and$libresoc.v:42576$2182_Y connect \$880 $not$libresoc.v:42577$2183_Y connect \$882 $and$libresoc.v:42578$2184_Y connect \$884 $and$libresoc.v:42579$2185_Y connect \$886 $ternary$libresoc.v:42580$2186_Y connect \$888 $and$libresoc.v:42581$2187_Y connect \$890 $and$libresoc.v:42582$2188_Y connect \$892 $not$libresoc.v:42583$2189_Y connect \$894 $and$libresoc.v:42584$2190_Y connect \$896 $and$libresoc.v:42585$2191_Y connect \$898 $ternary$libresoc.v:42586$2192_Y connect \$900 $and$libresoc.v:42587$2193_Y connect \$902 $and$libresoc.v:42588$2194_Y connect \$904 $not$libresoc.v:42589$2195_Y connect \$906 $and$libresoc.v:42590$2196_Y connect \$908 $and$libresoc.v:42591$2197_Y connect \$910 $ternary$libresoc.v:42592$2198_Y connect \$912 $and$libresoc.v:42593$2199_Y connect \$914 $and$libresoc.v:42594$2200_Y connect \$916 $not$libresoc.v:42595$2201_Y connect \$918 $and$libresoc.v:42596$2202_Y connect \$920 $and$libresoc.v:42597$2203_Y connect \$922 $ternary$libresoc.v:42598$2204_Y connect \$924 $or$libresoc.v:42599$2205_Y connect \$926 $or$libresoc.v:42600$2206_Y connect \$928 $or$libresoc.v:42601$2207_Y connect \$930 $or$libresoc.v:42602$2208_Y connect \$932 $reduce_or$libresoc.v:42603$2209_Y connect \$934 $and$libresoc.v:42604$2210_Y connect \$936 $and$libresoc.v:42605$2211_Y connect \$938 $not$libresoc.v:42606$2212_Y connect \$940 $and$libresoc.v:42607$2213_Y connect \$942 $and$libresoc.v:42608$2214_Y connect \$944 $ternary$libresoc.v:42609$2215_Y connect \$946 $reduce_or$libresoc.v:42610$2216_Y connect \$948 $and$libresoc.v:42611$2217_Y connect \$950 $and$libresoc.v:42612$2218_Y connect \$952 $and$libresoc.v:42613$2219_Y connect \$954 $and$libresoc.v:42614$2220_Y connect \$956 $and$libresoc.v:42615$2221_Y connect \$958 $and$libresoc.v:42616$2222_Y connect \$960 $and$libresoc.v:42617$2223_Y connect \$962 $and$libresoc.v:42618$2224_Y connect \$964 $and$libresoc.v:42619$2225_Y connect \$966 $and$libresoc.v:42620$2226_Y connect \$968 $and$libresoc.v:42621$2227_Y connect \$970 $and$libresoc.v:42622$2228_Y connect \$972 $not$libresoc.v:42623$2229_Y connect \$974 $and$libresoc.v:42624$2230_Y connect \$980 $and$libresoc.v:42625$2231_Y connect \$982 $ternary$libresoc.v:42626$2232_Y connect \$984 $and$libresoc.v:42627$2233_Y connect \$987 $and$libresoc.v:42628$2234_Y connect \$991 $not$libresoc.v:42629$2235_Y connect \$993 $and$libresoc.v:42630$2236_Y connect \$998 $and$libresoc.v:42631$2237_Y connect \$223 \$224 connect \$580 \$615 connect \$829 \$830 connect \$1157 \$1174 connect \$1176 \$1193 connect \$1373 \$1382 connect \o_ok 1'0 connect \ea_ok 1'0 connect \spr_spr1__wen \wp$1811 connect \spr_spr1__addr$175 \addr_en$1814 [3:0] connect \spr_spr1__data_i \fus_dest2_o$162 connect \addr_en$1814 \$1815 connect \wp$1811 \$1812 connect \wr_pick_rise$1057 \$1809 connect \wr_pick$1803 \$1804 connect \wrpick_SPR_spr1_i \$1801 connect \wrflag_spr0_spr1_1 \$1799 connect \state_wen \$1797 connect \state_data_i$174 \fus_dest5_o$161 connect \addr_en$1794 \$1795 connect \wp$1791 \$1792 connect \wr_pick_rise$1017 \$1789 connect \wr_pick$1783 \$1784 connect \wrpick_STATE_msr_i \$1781 connect \wrflag_trap0_msr_4 \$1779 connect \state_nia_wen \$1775 connect \state_data_i \$1773 connect \addr_en$1770 \$1771 connect \wp$1767 \$1768 connect \wr_pick_rise$1016 \$1765 connect \wr_pick$1759 \$1760 connect \wrflag_trap0_nia_3 \$1757 connect \addr_en$1754 \$1755 connect \wp$1751 \$1752 connect \wr_pick_rise$1642 \$1749 connect \wr_pick$1743 \$1744 connect \wrpick_STATE_nia_i [1] \$1741 connect \wrpick_STATE_nia_i [0] \$1739 connect \wrflag_branch0_nia_2 \$1737 connect \fast_dest1__wen \$1735 connect \fast_dest1__addr \$1727 connect \fast_dest1__data_i \$1719 connect \addr_en$1710 \$1711 connect \wp$1707 \$1708 connect \wr_pick_rise$1015 \$1705 connect \wr_pick$1699 \$1700 connect \wrflag_trap0_fast1_2 \$1697 connect \addr_en$1694 \$1695 connect \wp$1691 \$1692 connect \wr_pick_rise$1641 \$1689 connect \wr_pick$1683 \$1684 connect \wrflag_branch0_fast1_1 \$1681 connect \addr_en$1678 \$1679 connect \wp$1675 \$1676 connect \wr_pick_rise$1056 \$1673 connect \wr_pick$1667 \$1668 connect \wrflag_spr0_fast1_2 \$1665 connect \addr_en$1662 \$1663 connect \wp$1659 \$1660 connect \wr_pick_rise$1014 \$1657 connect \wr_pick$1651 \$1652 connect \wrflag_trap0_fast1_1 \$1649 connect \addr_en$1646 \$1647 connect \wp$1643 \$1644 connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1642 connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1641 connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1636 connect \wr_pick_rise$1636 \$1639 connect \wr_pick$1632 \$1633 connect \wrpick_FAST_fast1_i [4] \$1630 connect \wrpick_FAST_fast1_i [3] \$1628 connect \wrpick_FAST_fast1_i [2] \$1626 connect \wrpick_FAST_fast1_i [1] \$1624 connect \wrpick_FAST_fast1_i [0] \$1622 connect \wrflag_branch0_fast1_0 \$1620 connect \xer_wen$173 \$1612 connect \xer_data_i$172 \$1604 connect \addr_en$1601 \$1602 connect \wp$1598 \$1599 connect \wr_pick_rise$1097 \$1596 connect \wr_pick$1590 \$1591 connect \wrflag_mul0_xer_so_3 \$1588 connect \addr_en$1585 \$1586 connect \wp$1582 \$1583 connect \wr_pick_rise$1077 \$1580 connect \wr_pick$1574 \$1575 connect \wrflag_div0_xer_so_3 \$1572 connect \addr_en$1569 \$1570 connect \wp$1566 \$1567 connect \wr_pick_rise$1055 \$1564 connect \wr_pick$1558 \$1559 connect \wrflag_spr0_xer_so_3 \$1556 connect \addr_en$1553 \$1554 connect \wp$1550 \$1551 connect \wr_pick_rise$979 \$1548 connect \wr_pick$1542 \$1543 connect \wrpick_XER_xer_so_i [3] \$1540 connect \wrpick_XER_xer_so_i [2] \$1538 connect \wrpick_XER_xer_so_i [1] \$1536 connect \wrpick_XER_xer_so_i [0] \$1534 connect \wrflag_alu0_xer_so_4 \$1532 connect \xer_wen$171 \$1530 connect \xer_data_i$170 \$1524 connect \addr_en$1517 \$1518 connect \wp$1514 \$1515 connect \wr_pick_rise$1096 \$1512 connect \wr_pick$1506 \$1507 connect \wrflag_mul0_xer_ov_2 \$1504 connect \addr_en$1501 \$1502 connect \wp$1498 \$1499 connect \wr_pick_rise$1076 \$1496 connect \wr_pick$1490 \$1491 connect \wrflag_div0_xer_ov_2 \$1488 connect \addr_en$1485 \$1486 connect \wp$1482 \$1483 connect \wr_pick_rise$1054 \$1480 connect \wr_pick$1474 \$1475 connect \wrflag_spr0_xer_ov_4 \$1472 connect \addr_en$1469 \$1470 connect \wp$1466 \$1467 connect \wr_pick_rise$978 \$1464 connect \wr_pick$1458 \$1459 connect \wrpick_XER_xer_ov_i [3] \$1456 connect \wrpick_XER_xer_ov_i [2] \$1454 connect \wrpick_XER_xer_ov_i [1] \$1452 connect \wrpick_XER_xer_ov_i [0] \$1450 connect \wrflag_alu0_xer_ov_3 \$1448 connect \xer_wen \$1442 connect \xer_data_i \$1440 connect \addr_en$1435 \$1436 connect \wp$1432 \$1433 connect \wr_pick_rise$1116 \$1430 connect \wr_pick$1424 \$1425 connect \wrflag_shiftrot0_xer_ca_2 \$1422 connect \addr_en$1419 \$1420 connect \wp$1416 \$1417 connect \wr_pick_rise$1053 \$1414 connect \wr_pick$1408 \$1409 connect \wrflag_spr0_xer_ca_5 \$1406 connect \addr_en$1403 \$1404 connect \wp$1400 \$1401 connect \wr_pick_rise$977 \$1398 connect \wr_pick$1392 \$1393 connect \wrpick_XER_xer_ca_i [2] \$1390 connect \wrpick_XER_xer_ca_i [1] \$1388 connect \wrpick_XER_xer_ca_i [0] \$1386 connect \wrflag_alu0_xer_ca_2 \$1384 connect \cr_wen \$1382 [7:0] connect \cr_data_i \$1371 connect \addr_en$1356 \$1361 connect \wp$1353 \$1354 connect \wr_pick_rise$1115 \$1351 connect \wr_pick$1345 \$1346 connect \wrflag_shiftrot0_cr_a_1 \$1343 connect \addr_en$1336 \$1341 connect \wp$1333 \$1334 connect \wr_pick_rise$1095 \$1331 connect \wr_pick$1325 \$1326 connect \wrflag_mul0_cr_a_1 \$1323 connect \addr_en$1316 \$1321 connect \wp$1313 \$1314 connect \wr_pick_rise$1075 \$1311 connect \wr_pick$1305 \$1306 connect \wrflag_div0_cr_a_1 \$1303 connect \addr_en$1296 \$1301 connect \wp$1293 \$1294 connect \wr_pick_rise$1035 \$1291 connect \wr_pick$1285 \$1286 connect \wrflag_logical0_cr_a_1 \$1283 connect \addr_en$1276 \$1281 connect \wp$1273 \$1274 connect \wr_pick_rise$996 \$1271 connect \wr_pick$1265 \$1266 connect \wrflag_cr0_cr_a_2 \$1263 connect \addr_en$1256 \$1261 connect \wp$1253 \$1254 connect \wr_pick_rise$976 \$1251 connect \wr_pick$1245 \$1246 connect \wrpick_CR_cr_a_i [5] \$1243 connect \wrpick_CR_cr_a_i [4] \$1241 connect \wrpick_CR_cr_a_i [3] \$1239 connect \wrpick_CR_cr_a_i [2] \$1237 connect \wrpick_CR_cr_a_i [1] \$1235 connect \wrpick_CR_cr_a_i [0] \$1233 connect \wrflag_alu0_cr_a_1 \$1231 connect \cr_full_wr__wen \addr_en$1228 connect \cr_full_wr__data_i \fus_dest2_o connect \addr_en$1228 \$1229 connect \wp$1225 \$1226 connect \wr_pick_rise$995 \$1223 connect \wr_pick$1217 \$1218 connect \wrpick_CR_full_cr_i \$1215 connect \wrflag_cr0_full_cr_1 \$1213 connect \int_dest1__wen \$1211 connect \int_dest1__addr \$1193 [4:0] connect \int_dest1__data_i \$1174 [63:0] connect \addr_en$1154 \$1155 connect \wp$1151 \$1152 connect \wr_pick_rise$1134 \$1149 connect \wr_pick$1143 \$1144 connect \wrflag_ldst0_o_1 \$1141 connect \addr_en$1138 \$1139 connect \wp$1135 \$1136 connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1134 connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1129 connect \wr_pick_rise$1129 \$1132 connect \wr_pick$1125 \$1126 connect \wrflag_ldst0_o_0 \$1123 connect \addr_en$1120 \$1121 connect \wp$1117 \$1118 connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1116 connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1115 connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1110 connect \wr_pick_rise$1110 \$1113 connect \wr_pick$1106 \$1107 connect \wrflag_shiftrot0_o_0 \$1104 connect \addr_en$1101 \$1102 connect \wp$1098 \$1099 connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1097 connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1096 connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1095 connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1090 connect \wr_pick_rise$1090 \$1093 connect \wr_pick$1086 \$1087 connect \wrflag_mul0_o_0 \$1084 connect \addr_en$1081 \$1082 connect \wp$1078 \$1079 connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1077 connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1076 connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1075 connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1070 connect \wr_pick_rise$1070 \$1073 connect \wr_pick$1066 \$1067 connect \wrflag_div0_o_0 \$1064 connect \addr_en$1061 \$1062 connect \wp$1058 \$1059 connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1057 connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1056 connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1055 connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1054 connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1053 connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1048 connect \wr_pick_rise$1048 \$1051 connect \wr_pick$1044 \$1045 connect \wrflag_spr0_o_0 \$1042 connect \addr_en$1039 \$1040 connect \wp$1036 \$1037 connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1035 connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1030 connect \wr_pick_rise$1030 \$1033 connect \wr_pick$1026 \$1027 connect \wrflag_logical0_o_0 \$1024 connect \addr_en$1021 \$1022 connect \wp$1018 \$1019 connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1017 connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1016 connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1015 connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1014 connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1009 connect \wr_pick_rise$1009 \$1012 connect \wr_pick$1005 \$1006 connect \wrflag_trap0_o_0 \$1003 connect \addr_en$1000 \$1001 connect \wp$997 \$998 connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$996 connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$995 connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$990 connect \wr_pick_rise$990 \$993 connect \wr_pick$986 \$987 connect \wrflag_cr0_o_0 \$984 connect \addr_en \$982 connect \wp \$980 connect \fus_cu_wr__go_i [4] \wr_pick_rise$979 connect \fus_cu_wr__go_i [3] \wr_pick_rise$978 connect \fus_cu_wr__go_i [2] \wr_pick_rise$977 connect \fus_cu_wr__go_i [1] \wr_pick_rise$976 connect \fus_cu_wr__go_i [0] \wr_pick_rise connect \wr_pick_rise \$974 connect \wr_pick \$970 connect \wrpick_INT_o_i [9] \$968 connect \wrpick_INT_o_i [8] \$966 connect \wrpick_INT_o_i [7] \$964 connect \wrpick_INT_o_i [6] \$962 connect \wrpick_INT_o_i [5] \$960 connect \wrpick_INT_o_i [4] \$958 connect \wrpick_INT_o_i [3] \$956 connect \wrpick_INT_o_i [2] \$954 connect \wrpick_INT_o_i [1] \$952 connect \wrpick_INT_o_i [0] \$950 connect \wrflag_alu0_o_0 \$948 connect \spr_spr1__ren \$946 connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [3:0] connect \addr_en_SPR_spr1_spr0_0 \$944 connect \rp_SPR_spr1_spr0_0 \$942 connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 connect \pick_SPR_spr1_spr0_0 \$940 connect \rdflag_SPR_spr1_0 \core_spr1_ok connect \fast_src1__ren \$932 connect \fast_src1__addr \$930 connect \addr_en_FAST_fast1_trap0_4 \$922 connect \rp_FAST_fast1_trap0_4 \$920 connect \pick_FAST_fast1_trap0_4 \$918 connect \addr_en_FAST_fast1_branch0_3 \$910 connect \rp_FAST_fast1_branch0_3 \$908 connect \pick_FAST_fast1_branch0_3 \$906 connect \addr_en_FAST_fast1_spr0_2 \$898 connect \rp_FAST_fast1_spr0_2 \$896 connect \pick_FAST_fast1_spr0_2 \$894 connect \addr_en_FAST_fast1_trap0_1 \$886 connect \rp_FAST_fast1_trap0_1 \$884 connect \pick_FAST_fast1_trap0_1 \$882 connect \addr_en_FAST_fast1_branch0_0 \$874 connect \rp_FAST_fast1_branch0_0 \$872 connect \rdpick_FAST_fast1_i [4] \pick_FAST_fast1_trap0_4 connect \rdpick_FAST_fast1_i [3] \pick_FAST_fast1_branch0_3 connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 connect \pick_FAST_fast1_branch0_0 \$870 connect \rdflag_FAST_fast1_1 \core_fast2_ok connect \rdflag_FAST_fast1_0 \core_fast1_ok connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] connect \addr_en_CR_cr_c_cr0_0 \$862 connect \rp_CR_cr_c_cr0_0 \$856 connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 connect \pick_CR_cr_c_cr0_0 \$854 connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] connect \addr_en_CR_cr_b_cr0_0 \$846 connect \rp_CR_cr_b_cr0_0 \$840 connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 connect \pick_CR_cr_b_cr0_0 \$838 connect \rdflag_CR_cr_b_0 \core_cr_in2_ok connect \cr_src1__ren \$830 [7:0] connect \addr_en_CR_cr_a_branch0_1 \$827 connect \rp_CR_cr_a_branch0_1 \$821 connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast1_branch0_3 connect \fus_cu_rd__go_i$82 [0] \dp_FAST_fast1_branch0_0 connect \fus_cu_rd__go_i$82 [2] \dp_CR_cr_a_branch0_1 connect \pick_CR_cr_a_branch0_1 \$819 connect \addr_en_CR_cr_a_cr0_0 \$811 connect \rp_CR_cr_a_cr0_0 \$805 connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 connect \pick_CR_cr_a_cr0_0 \$803 connect \rdflag_CR_cr_a_0 \core_cr_in1_ok connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 connect \addr_en_CR_full_cr_cr0_0 \$795 connect \rp_CR_full_cr_cr0_0 \$793 connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 connect \pick_CR_full_cr_cr0_0 \$791 connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 connect \addr_en_XER_xer_ov_spr0_0 \$783 connect \rp_XER_xer_ov_spr0_0 \$781 connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 connect \pick_XER_xer_ov_spr0_0 \$779 connect \rdflag_XER_xer_ov_0 \$771 connect \xer_src2__ren \$759 connect \addr_en_XER_xer_ca_shiftrot0_2 \$757 connect \rp_XER_xer_ca_shiftrot0_2 \$755 connect \pick_XER_xer_ca_shiftrot0_2 \$753 connect \addr_en_XER_xer_ca_spr0_1 \$745 connect \rp_XER_xer_ca_spr0_1 \$743 connect \pick_XER_xer_ca_spr0_1 \$741 connect \addr_en_XER_xer_ca_alu0_0 \$733 connect \rp_XER_xer_ca_alu0_0 \$731 connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 connect \pick_XER_xer_ca_alu0_0 \$729 connect \rdflag_XER_xer_ca_0 \$721 connect \xer_src1__ren \$703 connect \addr_en_XER_xer_so_shiftrot0_5 \$701 connect \rp_XER_xer_so_shiftrot0_5 \$699 connect \pick_XER_xer_so_shiftrot0_5 \$697 connect \addr_en_XER_xer_so_mul0_4 \$689 connect \rp_XER_xer_so_mul0_4 \$687 connect \pick_XER_xer_so_mul0_4 \$685 connect \addr_en_XER_xer_so_div0_3 \$677 connect \rp_XER_xer_so_div0_3 \$675 connect \pick_XER_xer_so_div0_3 \$673 connect \addr_en_XER_xer_so_spr0_2 \$665 connect \rp_XER_xer_so_spr0_2 \$663 connect \pick_XER_xer_so_spr0_2 \$661 connect \addr_en_XER_xer_so_logical0_1 \$653 connect \rp_XER_xer_so_logical0_1 \$651 connect \pick_XER_xer_so_logical0_1 \$649 connect \addr_en_XER_xer_so_alu0_0 \$641 connect \rp_XER_xer_so_alu0_0 \$639 connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 connect \pick_XER_xer_so_alu0_0 \$637 connect \rdflag_XER_xer_so_0 \$629 connect \int_src1__ren \$617 connect \int_src1__addr \$615 [4:0] connect \addr_en_INT_rabc_ldst0_18 \$578 connect \rp_INT_rabc_ldst0_18 \$576 connect \pick_INT_rabc_ldst0_18 \$574 connect \addr_en_INT_rabc_shiftrot0_17 \$566 connect \rp_INT_rabc_shiftrot0_17 \$564 connect \pick_INT_rabc_shiftrot0_17 \$562 connect \addr_en_INT_rabc_mul0_16 \$554 connect \rp_INT_rabc_mul0_16 \$552 connect \pick_INT_rabc_mul0_16 \$550 connect \addr_en_INT_rabc_div0_15 \$542 connect \rp_INT_rabc_div0_15 \$540 connect \pick_INT_rabc_div0_15 \$538 connect \addr_en_INT_rabc_spr0_14 \$530 connect \rp_INT_rabc_spr0_14 \$528 connect \fus_cu_rd__go_i$66 [1] \dp_SPR_spr1_spr0_0 connect \fus_cu_rd__go_i$66 [2] \dp_FAST_fast1_spr0_2 connect \fus_cu_rd__go_i$66 [4] \dp_XER_xer_ov_spr0_0 connect \fus_cu_rd__go_i$66 [5] \dp_XER_xer_ca_spr0_1 connect \fus_cu_rd__go_i$66 [3] \dp_XER_xer_so_spr0_2 connect \fus_cu_rd__go_i$66 [0] \dp_INT_rabc_spr0_14 connect \pick_INT_rabc_spr0_14 \$526 connect \addr_en_INT_rabc_logical0_13 \$518 connect \rp_INT_rabc_logical0_13 \$516 connect \pick_INT_rabc_logical0_13 \$514 connect \addr_en_INT_rabc_trap0_12 \$506 connect \rp_INT_rabc_trap0_12 \$504 connect \pick_INT_rabc_trap0_12 \$502 connect \addr_en_INT_rabc_cr0_11 \$494 connect \rp_INT_rabc_cr0_11 \$492 connect \pick_INT_rabc_cr0_11 \$490 connect \addr_en_INT_rabc_alu0_10 \$482 connect \rp_INT_rabc_alu0_10 \$480 connect \pick_INT_rabc_alu0_10 \$478 connect \addr_en_INT_rabc_ldst0_9 \$470 connect \rp_INT_rabc_ldst0_9 \$468 connect \pick_INT_rabc_ldst0_9 \$466 connect \addr_en_INT_rabc_shiftrot0_8 \$458 connect \rp_INT_rabc_shiftrot0_8 \$456 connect \pick_INT_rabc_shiftrot0_8 \$454 connect \addr_en_INT_rabc_ldst0_7 \$446 connect \rp_INT_rabc_ldst0_7 \$444 connect \fus_cu_rd__go_i$59 [0] \dp_INT_rabc_ldst0_18 connect \fus_cu_rd__go_i$59 [2] \dp_INT_rabc_ldst0_9 connect \fus_cu_rd__go_i$59 [1] \dp_INT_rabc_ldst0_7 connect \pick_INT_rabc_ldst0_7 \$442 connect \addr_en_INT_rabc_shiftrot0_6 \$434 connect \rp_INT_rabc_shiftrot0_6 \$432 connect \fus_cu_rd__go_i$56 [4] \dp_XER_xer_ca_shiftrot0_2 connect \fus_cu_rd__go_i$56 [3] \dp_XER_xer_so_shiftrot0_5 connect \fus_cu_rd__go_i$56 [0] \dp_INT_rabc_shiftrot0_17 connect \fus_cu_rd__go_i$56 [2] \dp_INT_rabc_shiftrot0_8 connect \fus_cu_rd__go_i$56 [1] \dp_INT_rabc_shiftrot0_6 connect \pick_INT_rabc_shiftrot0_6 \$430 connect \addr_en_INT_rabc_mul0_5 \$422 connect \rp_INT_rabc_mul0_5 \$420 connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_mul0_4 connect \fus_cu_rd__go_i$53 [0] \dp_INT_rabc_mul0_16 connect \fus_cu_rd__go_i$53 [1] \dp_INT_rabc_mul0_5 connect \pick_INT_rabc_mul0_5 \$418 connect \addr_en_INT_rabc_div0_4 \$410 connect \rp_INT_rabc_div0_4 \$408 connect \fus_cu_rd__go_i$50 [2] \dp_XER_xer_so_div0_3 connect \fus_cu_rd__go_i$50 [0] \dp_INT_rabc_div0_15 connect \fus_cu_rd__go_i$50 [1] \dp_INT_rabc_div0_4 connect \pick_INT_rabc_div0_4 \$406 connect \addr_en_INT_rabc_logical0_3 \$398 connect \rp_INT_rabc_logical0_3 \$396 connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_logical0_1 connect \fus_cu_rd__go_i$47 [0] \dp_INT_rabc_logical0_13 connect \fus_cu_rd__go_i$47 [1] \dp_INT_rabc_logical0_3 connect \pick_INT_rabc_logical0_3 \$394 connect \addr_en_INT_rabc_trap0_2 \$386 connect \rp_INT_rabc_trap0_2 \$384 connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast1_trap0_4 connect \fus_cu_rd__go_i$44 [2] \dp_FAST_fast1_trap0_1 connect \fus_cu_rd__go_i$44 [0] \dp_INT_rabc_trap0_12 connect \fus_cu_rd__go_i$44 [1] \dp_INT_rabc_trap0_2 connect \pick_INT_rabc_trap0_2 \$382 connect \addr_en_INT_rabc_cr0_1 \$374 connect \rp_INT_rabc_cr0_1 \$372 connect \fus_cu_rd__go_i$41 [5] \dp_CR_cr_c_cr0_0 connect \fus_cu_rd__go_i$41 [4] \dp_CR_cr_b_cr0_0 connect \fus_cu_rd__go_i$41 [3] \dp_CR_cr_a_cr0_0 connect \fus_cu_rd__go_i$41 [2] \dp_CR_full_cr_cr0_0 connect \fus_cu_rd__go_i$41 [0] \dp_INT_rabc_cr0_11 connect \fus_cu_rd__go_i$41 [1] \dp_INT_rabc_cr0_1 connect \pick_INT_rabc_cr0_1 \$370 connect \addr_en_INT_rabc_alu0_0 \$362 connect \rp_INT_rabc_alu0_0 \$360 connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 connect \fus_cu_rd__go_i [0] \dp_INT_rabc_alu0_10 connect \fus_cu_rd__go_i [1] \dp_INT_rabc_alu0_0 connect \rdpick_INT_rabc_i [18] \pick_INT_rabc_ldst0_18 connect \rdpick_INT_rabc_i [17] \pick_INT_rabc_shiftrot0_17 connect \rdpick_INT_rabc_i [16] \pick_INT_rabc_mul0_16 connect \rdpick_INT_rabc_i [15] \pick_INT_rabc_div0_15 connect \rdpick_INT_rabc_i [14] \pick_INT_rabc_spr0_14 connect \rdpick_INT_rabc_i [13] \pick_INT_rabc_logical0_13 connect \rdpick_INT_rabc_i [12] \pick_INT_rabc_trap0_12 connect \rdpick_INT_rabc_i [11] \pick_INT_rabc_cr0_11 connect \rdpick_INT_rabc_i [10] \pick_INT_rabc_alu0_10 connect \rdpick_INT_rabc_i [9] \pick_INT_rabc_ldst0_9 connect \rdpick_INT_rabc_i [8] \pick_INT_rabc_shiftrot0_8 connect \rdpick_INT_rabc_i [7] \pick_INT_rabc_ldst0_7 connect \rdpick_INT_rabc_i [6] \pick_INT_rabc_shiftrot0_6 connect \rdpick_INT_rabc_i [5] \pick_INT_rabc_mul0_5 connect \rdpick_INT_rabc_i [4] \pick_INT_rabc_div0_4 connect \rdpick_INT_rabc_i [3] \pick_INT_rabc_logical0_3 connect \rdpick_INT_rabc_i [2] \pick_INT_rabc_trap0_2 connect \rdpick_INT_rabc_i [1] \pick_INT_rabc_cr0_1 connect \rdpick_INT_rabc_i [0] \pick_INT_rabc_alu0_0 connect \pick_INT_rabc_alu0_0 \$358 connect \rdflag_INT_rabc_2 \core_reg1_ok connect \rdflag_INT_rabc_1 \core_reg3_ok connect \rdflag_INT_rabc_0 \core_reg2_ok connect \en_ldst0 \$217 connect \en_shiftrot0 \$213 connect \en_mul0 \$209 connect \en_div0 \$205 connect \en_spr0 \$201 connect \en_logical0 \$197 connect \en_trap0 \$193 connect \en_branch0 \$189 connect \en_cr0 \$185 connect \fu_enable [9] \en_ldst0 connect \fu_enable [8] \en_shiftrot0 connect \fu_enable [7] \en_mul0 connect \fu_enable [6] \en_div0 connect \fu_enable [5] \en_spr0 connect \fu_enable [4] \en_logical0 connect \fu_enable [3] \en_trap0 connect \fu_enable [2] \en_branch0 connect \fu_enable [1] \en_cr0 connect \fu_enable [0] \en_alu0 connect \en_alu0 \$181 connect \dec_LDST_sv_a_nz \sv_a_nz connect \dec_LDST_bigendian \bigendian_i connect \dec_LDST_raw_opcode_in \raw_insn_i connect \sv_a_nz$180 \sv_a_nz connect \dec_SHIFT_ROT_bigendian \bigendian_i connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i connect \sv_a_nz$179 \sv_a_nz connect \dec_MUL_bigendian \bigendian_i connect \dec_MUL_raw_opcode_in \raw_insn_i connect \dec_DIV_sv_a_nz \sv_a_nz connect \dec_DIV_bigendian \bigendian_i connect \dec_DIV_raw_opcode_in \raw_insn_i connect \sv_a_nz$178 \sv_a_nz connect \dec_SPR_bigendian \bigendian_i connect \dec_SPR_raw_opcode_in \raw_insn_i connect \dec_LOGICAL_sv_a_nz \sv_a_nz connect \dec_LOGICAL_bigendian \bigendian_i connect \dec_LOGICAL_raw_opcode_in \raw_insn_i connect \sv_a_nz$177 \sv_a_nz connect \dec_BRANCH_bigendian \bigendian_i connect \dec_BRANCH_raw_opcode_in \raw_insn_i connect \sv_a_nz$176 \sv_a_nz connect \dec_CR_bigendian \bigendian_i connect \dec_CR_raw_opcode_in \raw_insn_i connect \dec_ALU_sv_a_nz \sv_a_nz connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end attribute \src "libresoc.v:48921.1-49554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr attribute \src "libresoc.v:48922.7-48922.20" wire $0\initial[0:0] attribute \src "libresoc.v:49468.3-49476.6" wire width 8 $0\ren_delay$17$next[7:0]$3046 attribute \src "libresoc.v:49304.3-49305.43" wire width 8 $0\ren_delay$17[7:0]$3043 attribute \src "libresoc.v:49250.13-49250.35" wire width 8 $0\ren_delay$17[7:0]$3060 attribute \src "libresoc.v:49487.3-49495.6" wire width 8 $0\ren_delay$34$next[7:0]$3050 attribute \src "libresoc.v:49302.3-49303.43" wire width 8 $0\ren_delay$34[7:0]$3041 attribute \src "libresoc.v:49254.13-49254.35" wire width 8 $0\ren_delay$34[7:0]$3062 attribute \src "libresoc.v:49506.3-49514.6" wire width 8 $0\ren_delay$next[7:0]$3054 attribute \src "libresoc.v:49306.3-49307.35" wire width 8 $0\ren_delay[7:0] attribute \src "libresoc.v:49515.3-49524.6" wire width 4 $0\src1__data_o[3:0] attribute \src "libresoc.v:49477.3-49486.6" wire width 4 $0\src2__data_o[3:0] attribute \src "libresoc.v:49496.3-49505.6" wire width 4 $0\src3__data_o[3:0] attribute \src "libresoc.v:49468.3-49476.6" wire width 8 $1\ren_delay$17$next[7:0]$3047 attribute \src "libresoc.v:49487.3-49495.6" wire width 8 $1\ren_delay$34$next[7:0]$3051 attribute \src "libresoc.v:49506.3-49514.6" wire width 8 $1\ren_delay$next[7:0]$3055 attribute \src "libresoc.v:49248.13-49248.30" wire width 8 $1\ren_delay[7:0] attribute \src "libresoc.v:49515.3-49524.6" wire width 4 $1\src1__data_o[3:0] attribute \src "libresoc.v:49477.3-49486.6" wire width 4 $1\src2__data_o[3:0] attribute \src "libresoc.v:49496.3-49505.6" wire width 4 $1\src3__data_o[3:0] attribute \src "libresoc.v:49278.17-49278.125" wire width 4 $or$libresoc.v:49278$3016_Y attribute \src "libresoc.v:49279.18-49279.126" wire width 4 $or$libresoc.v:49279$3017_Y attribute \src "libresoc.v:49280.18-49280.96" wire width 4 $or$libresoc.v:49280$3018_Y attribute \src "libresoc.v:49281.18-49281.96" wire width 4 $or$libresoc.v:49281$3019_Y attribute \src "libresoc.v:49284.18-49284.126" wire width 4 $or$libresoc.v:49284$3022_Y attribute \src "libresoc.v:49285.18-49285.126" wire width 4 $or$libresoc.v:49285$3023_Y attribute \src "libresoc.v:49286.18-49286.97" wire width 4 $or$libresoc.v:49286$3024_Y attribute \src "libresoc.v:49287.18-49287.126" wire width 4 $or$libresoc.v:49287$3025_Y attribute \src "libresoc.v:49288.18-49288.126" wire width 4 $or$libresoc.v:49288$3026_Y attribute \src "libresoc.v:49289.18-49289.97" wire width 4 $or$libresoc.v:49289$3027_Y attribute \src "libresoc.v:49290.18-49290.97" wire width 4 $or$libresoc.v:49290$3028_Y attribute \src "libresoc.v:49292.18-49292.126" wire width 4 $or$libresoc.v:49292$3030_Y attribute \src "libresoc.v:49293.17-49293.125" wire width 4 $or$libresoc.v:49293$3031_Y attribute \src "libresoc.v:49294.18-49294.126" wire width 4 $or$libresoc.v:49294$3032_Y attribute \src "libresoc.v:49295.18-49295.97" wire width 4 $or$libresoc.v:49295$3033_Y attribute \src "libresoc.v:49296.18-49296.126" wire width 4 $or$libresoc.v:49296$3034_Y attribute \src "libresoc.v:49297.18-49297.126" wire width 4 $or$libresoc.v:49297$3035_Y attribute \src "libresoc.v:49298.18-49298.97" wire width 4 $or$libresoc.v:49298$3036_Y attribute \src "libresoc.v:49299.18-49299.97" wire width 4 $or$libresoc.v:49299$3037_Y attribute \src "libresoc.v:49300.17-49300.125" wire width 4 $or$libresoc.v:49300$3038_Y attribute \src "libresoc.v:49301.17-49301.94" wire width 4 $or$libresoc.v:49301$3039_Y attribute \src "libresoc.v:49282.18-49282.100" wire $reduce_or$libresoc.v:49282$3020_Y attribute \src "libresoc.v:49283.17-49283.95" wire $reduce_or$libresoc.v:49283$3021_Y attribute \src "libresoc.v:49291.18-49291.100" wire $reduce_or$libresoc.v:49291$3029_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$15 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$32 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$35 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \data_i$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 3 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 2 \full_rd2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 output 4 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 5 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 input 12 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 13 \full_wr__wen attribute \src "libresoc.v:48922.7-48922.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest20__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_r0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_r20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_r20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_src10__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_src20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_src30__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src30__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_w0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest21__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_r1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_r21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_r21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_src11__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src11__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_src21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_src31__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src31__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_w1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest22__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_r22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_r22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_r2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_r2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_src12__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src12__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_src22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_src32__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src32__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_w2__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_dest13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_dest23__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_r23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_r23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_r3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_r3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_src13__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_src13__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_src23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_src23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_src33__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_src33__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_3_w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_3_w3__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_dest14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_dest24__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_r24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_r24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_r4__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_r4__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_src14__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_src14__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_src24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_src24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_src34__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_src34__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_4_w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_4_w4__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_dest15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_dest25__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_r25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_r25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_r5__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_r5__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_src15__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_src15__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_src25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_src25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_src35__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_src35__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_5_w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_5_w5__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_dest16__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_dest16__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_dest26__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_r26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_r26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_r6__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_r6__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_src16__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_src16__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_src26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_src26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_src36__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_src36__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_6_w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_6_w6__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_dest17__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_dest17__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_dest27__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_r27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_r27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_r7__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_r7__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_src17__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_src17__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_src27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_src27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_src37__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_src37__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_7_w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_7_w7__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$34$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 6 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 7 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 8 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 9 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 10 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 11 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 15 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \wen$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49278$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_4_src14__data_o connect \B \reg_5_src15__data_o connect \Y $or$libresoc.v:49278$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49279$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_6_src16__data_o connect \B \reg_7_src17__data_o connect \Y $or$libresoc.v:49279$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49280$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 connect \Y $or$libresoc.v:49280$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49281$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 connect \Y $or$libresoc.v:49281$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49284$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_0_src20__data_o connect \B \reg_1_src21__data_o connect \Y $or$libresoc.v:49284$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49285$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_2_src22__data_o connect \B \reg_3_src23__data_o connect \Y $or$libresoc.v:49285$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49286$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 connect \Y $or$libresoc.v:49286$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49287$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_4_src24__data_o connect \B \reg_5_src25__data_o connect \Y $or$libresoc.v:49287$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49288$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_6_src26__data_o connect \B \reg_7_src27__data_o connect \Y $or$libresoc.v:49288$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49289$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:49289$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49290$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 connect \Y $or$libresoc.v:49290$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49292$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_0_src30__data_o connect \B \reg_1_src31__data_o connect \Y $or$libresoc.v:49292$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49293$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_0_src10__data_o connect \B \reg_1_src11__data_o connect \Y $or$libresoc.v:49293$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49294$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_2_src32__data_o connect \B \reg_3_src33__data_o connect \Y $or$libresoc.v:49294$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49295$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 connect \Y $or$libresoc.v:49295$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49296$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_4_src34__data_o connect \B \reg_5_src35__data_o connect \Y $or$libresoc.v:49296$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49297$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_6_src36__data_o connect \B \reg_7_src37__data_o connect \Y $or$libresoc.v:49297$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49298$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 connect \Y $or$libresoc.v:49298$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49299$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 connect \Y $or$libresoc.v:49299$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:49300$3038 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reg_2_src12__data_o connect \B \reg_3_src13__data_o connect \Y $or$libresoc.v:49300$3038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:49301$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 connect \Y $or$libresoc.v:49301$3039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:49282$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 connect \Y $reduce_or$libresoc.v:49282$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:49283$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay connect \Y $reduce_or$libresoc.v:49283$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:49291$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 connect \Y $reduce_or$libresoc.v:49291$3029_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:49308.9-49327.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest10__data_i \reg_0_dest10__data_i connect \dest10__wen \reg_0_dest10__wen connect \dest20__data_i \reg_0_dest20__data_i connect \dest20__wen \reg_0_dest20__wen connect \r0__data_o \reg_0_r0__data_o connect \r0__ren \reg_0_r0__ren connect \r20__data_o \reg_0_r20__data_o connect \r20__ren \reg_0_r20__ren connect \src10__data_o \reg_0_src10__data_o connect \src10__ren \reg_0_src10__ren connect \src20__data_o \reg_0_src20__data_o connect \src20__ren \reg_0_src20__ren connect \src30__data_o \reg_0_src30__data_o connect \src30__ren \reg_0_src30__ren connect \w0__data_i \reg_0_w0__data_i connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:49328.9-49347.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest11__data_i \reg_1_dest11__data_i connect \dest11__wen \reg_1_dest11__wen connect \dest21__data_i \reg_1_dest21__data_i connect \dest21__wen \reg_1_dest21__wen connect \r1__data_o \reg_1_r1__data_o connect \r1__ren \reg_1_r1__ren connect \r21__data_o \reg_1_r21__data_o connect \r21__ren \reg_1_r21__ren connect \src11__data_o \reg_1_src11__data_o connect \src11__ren \reg_1_src11__ren connect \src21__data_o \reg_1_src21__data_o connect \src21__ren \reg_1_src21__ren connect \src31__data_o \reg_1_src31__data_o connect \src31__ren \reg_1_src31__ren connect \w1__data_i \reg_1_w1__data_i connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:49348.9-49367.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest12__data_i \reg_2_dest12__data_i connect \dest12__wen \reg_2_dest12__wen connect \dest22__data_i \reg_2_dest22__data_i connect \dest22__wen \reg_2_dest22__wen connect \r22__data_o \reg_2_r22__data_o connect \r22__ren \reg_2_r22__ren connect \r2__data_o \reg_2_r2__data_o connect \r2__ren \reg_2_r2__ren connect \src12__data_o \reg_2_src12__data_o connect \src12__ren \reg_2_src12__ren connect \src22__data_o \reg_2_src22__data_o connect \src22__ren \reg_2_src22__ren connect \src32__data_o \reg_2_src32__data_o connect \src32__ren \reg_2_src32__ren connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:49368.9-49387.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest13__data_i \reg_3_dest13__data_i connect \dest13__wen \reg_3_dest13__wen connect \dest23__data_i \reg_3_dest23__data_i connect \dest23__wen \reg_3_dest23__wen connect \r23__data_o \reg_3_r23__data_o connect \r23__ren \reg_3_r23__ren connect \r3__data_o \reg_3_r3__data_o connect \r3__ren \reg_3_r3__ren connect \src13__data_o \reg_3_src13__data_o connect \src13__ren \reg_3_src13__ren connect \src23__data_o \reg_3_src23__data_o connect \src23__ren \reg_3_src23__ren connect \src33__data_o \reg_3_src33__data_o connect \src33__ren \reg_3_src33__ren connect \w3__data_i \reg_3_w3__data_i connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:49388.9-49407.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest14__data_i \reg_4_dest14__data_i connect \dest14__wen \reg_4_dest14__wen connect \dest24__data_i \reg_4_dest24__data_i connect \dest24__wen \reg_4_dest24__wen connect \r24__data_o \reg_4_r24__data_o connect \r24__ren \reg_4_r24__ren connect \r4__data_o \reg_4_r4__data_o connect \r4__ren \reg_4_r4__ren connect \src14__data_o \reg_4_src14__data_o connect \src14__ren \reg_4_src14__ren connect \src24__data_o \reg_4_src24__data_o connect \src24__ren \reg_4_src24__ren connect \src34__data_o \reg_4_src34__data_o connect \src34__ren \reg_4_src34__ren connect \w4__data_i \reg_4_w4__data_i connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:49408.9-49427.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest15__data_i \reg_5_dest15__data_i connect \dest15__wen \reg_5_dest15__wen connect \dest25__data_i \reg_5_dest25__data_i connect \dest25__wen \reg_5_dest25__wen connect \r25__data_o \reg_5_r25__data_o connect \r25__ren \reg_5_r25__ren connect \r5__data_o \reg_5_r5__data_o connect \r5__ren \reg_5_r5__ren connect \src15__data_o \reg_5_src15__data_o connect \src15__ren \reg_5_src15__ren connect \src25__data_o \reg_5_src25__data_o connect \src25__ren \reg_5_src25__ren connect \src35__data_o \reg_5_src35__data_o connect \src35__ren \reg_5_src35__ren connect \w5__data_i \reg_5_w5__data_i connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:49428.9-49447.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest16__data_i \reg_6_dest16__data_i connect \dest16__wen \reg_6_dest16__wen connect \dest26__data_i \reg_6_dest26__data_i connect \dest26__wen \reg_6_dest26__wen connect \r26__data_o \reg_6_r26__data_o connect \r26__ren \reg_6_r26__ren connect \r6__data_o \reg_6_r6__data_o connect \r6__ren \reg_6_r6__ren connect \src16__data_o \reg_6_src16__data_o connect \src16__ren \reg_6_src16__ren connect \src26__data_o \reg_6_src26__data_o connect \src26__ren \reg_6_src26__ren connect \src36__data_o \reg_6_src36__data_o connect \src36__ren \reg_6_src36__ren connect \w6__data_i \reg_6_w6__data_i connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:49448.9-49467.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest17__data_i \reg_7_dest17__data_i connect \dest17__wen \reg_7_dest17__wen connect \dest27__data_i \reg_7_dest27__data_i connect \dest27__wen \reg_7_dest27__wen connect \r27__data_o \reg_7_r27__data_o connect \r27__ren \reg_7_r27__ren connect \r7__data_o \reg_7_r7__data_o connect \r7__ren \reg_7_r7__ren connect \src17__data_o \reg_7_src17__data_o connect \src17__ren \reg_7_src17__ren connect \src27__data_o \reg_7_src27__data_o connect \src27__ren \reg_7_src27__ren connect \src37__data_o \reg_7_src37__data_o connect \src37__ren \reg_7_src37__ren connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end attribute \src "libresoc.v:48922.7-48922.20" process $proc$libresoc.v:48922$3057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:49248.13-49248.30" process $proc$libresoc.v:49248$3058 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end attribute \src "libresoc.v:49250.13-49250.35" process $proc$libresoc.v:49250$3059 assign { } { } assign $0\ren_delay$17[7:0]$3060 8'00000000 sync always sync init update \ren_delay$17 $0\ren_delay$17[7:0]$3060 end attribute \src "libresoc.v:49254.13-49254.35" process $proc$libresoc.v:49254$3061 assign { } { } assign $0\ren_delay$34[7:0]$3062 8'00000000 sync always sync init update \ren_delay$34 $0\ren_delay$34[7:0]$3062 end attribute \src "libresoc.v:49302.3-49303.43" process $proc$libresoc.v:49302$3040 assign { } { } assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next sync posedge \coresync_clk update \ren_delay$34 $0\ren_delay$34[7:0]$3041 end attribute \src "libresoc.v:49304.3-49305.43" process $proc$libresoc.v:49304$3042 assign { } { } assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next sync posedge \coresync_clk update \ren_delay$17 $0\ren_delay$17[7:0]$3043 end attribute \src "libresoc.v:49306.3-49307.35" process $proc$libresoc.v:49306$3044 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end attribute \src "libresoc.v:49468.3-49476.6" process $proc$libresoc.v:49468$3045 assign { } { } assign { } { } assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 attribute \src "libresoc.v:49469.5-49469.29" switch \initial attribute \src "libresoc.v:49469.9-49469.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$17$next[7:0]$3047 8'00000000 case assign $1\ren_delay$17$next[7:0]$3047 \src2__ren end sync always update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 end attribute \src "libresoc.v:49477.3-49486.6" process $proc$libresoc.v:49477$3048 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] attribute \src "libresoc.v:49478.5-49478.29" switch \initial attribute \src "libresoc.v:49478.9-49478.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$18 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src2__data_o[3:0] \$32 case assign $1\src2__data_o[3:0] 4'0000 end sync always update \src2__data_o $0\src2__data_o[3:0] end attribute \src "libresoc.v:49487.3-49495.6" process $proc$libresoc.v:49487$3049 assign { } { } assign { } { } assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 attribute \src "libresoc.v:49488.5-49488.29" switch \initial attribute \src "libresoc.v:49488.9-49488.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$34$next[7:0]$3051 8'00000000 case assign $1\ren_delay$34$next[7:0]$3051 \src3__ren end sync always update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 end attribute \src "libresoc.v:49496.3-49505.6" process $proc$libresoc.v:49496$3052 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] attribute \src "libresoc.v:49497.5-49497.29" switch \initial attribute \src "libresoc.v:49497.9-49497.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$35 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src3__data_o[3:0] \$49 case assign $1\src3__data_o[3:0] 4'0000 end sync always update \src3__data_o $0\src3__data_o[3:0] end attribute \src "libresoc.v:49506.3-49514.6" process $proc$libresoc.v:49506$3053 assign { } { } assign { } { } assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 attribute \src "libresoc.v:49507.5-49507.29" switch \initial attribute \src "libresoc.v:49507.9-49507.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$next[7:0]$3055 8'00000000 case assign $1\ren_delay$next[7:0]$3055 \src1__ren end sync always update \ren_delay$next $0\ren_delay$next[7:0]$3054 end attribute \src "libresoc.v:49515.3-49524.6" process $proc$libresoc.v:49515$3056 assign { } { } assign { } { } assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] attribute \src "libresoc.v:49516.5-49516.29" switch \initial attribute \src "libresoc.v:49516.9-49516.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src1__data_o[3:0] \$15 case assign $1\src1__data_o[3:0] 4'0000 end sync always update \src1__data_o $0\src1__data_o[3:0] end connect \$9 $or$libresoc.v:49278$3016_Y connect \$11 $or$libresoc.v:49279$3017_Y connect \$13 $or$libresoc.v:49280$3018_Y connect \$15 $or$libresoc.v:49281$3019_Y connect \$18 $reduce_or$libresoc.v:49282$3020_Y connect \$1 $reduce_or$libresoc.v:49283$3021_Y connect \$20 $or$libresoc.v:49284$3022_Y connect \$22 $or$libresoc.v:49285$3023_Y connect \$24 $or$libresoc.v:49286$3024_Y connect \$26 $or$libresoc.v:49287$3025_Y connect \$28 $or$libresoc.v:49288$3026_Y connect \$30 $or$libresoc.v:49289$3027_Y connect \$32 $or$libresoc.v:49290$3028_Y connect \$35 $reduce_or$libresoc.v:49291$3029_Y connect \$37 $or$libresoc.v:49292$3030_Y connect \$3 $or$libresoc.v:49293$3031_Y connect \$39 $or$libresoc.v:49294$3032_Y connect \$41 $or$libresoc.v:49295$3033_Y connect \$43 $or$libresoc.v:49296$3034_Y connect \$45 $or$libresoc.v:49297$3035_Y connect \$47 $or$libresoc.v:49298$3036_Y connect \$49 $or$libresoc.v:49299$3037_Y connect \$5 $or$libresoc.v:49300$3038_Y connect \$7 $or$libresoc.v:49301$3039_Y connect \wen$51 8'00000000 connect \data_i$52 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } connect \reg_7_dest27__data_i 4'0000 connect \reg_6_dest26__data_i 4'0000 connect \reg_5_dest25__data_i 4'0000 connect \reg_4_dest24__data_i 4'0000 connect \reg_3_dest23__data_i 4'0000 connect \reg_2_dest22__data_i 4'0000 connect \reg_1_dest21__data_i 4'0000 connect \reg_0_dest20__data_i 4'0000 connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 connect \reg_7_dest17__data_i \data_i connect \reg_6_dest16__data_i \data_i connect \reg_5_dest15__data_i \data_i connect \reg_4_dest14__data_i \data_i connect \reg_3_dest13__data_i \data_i connect \reg_2_dest12__data_i \data_i connect \reg_1_dest11__data_i \data_i connect \reg_0_dest10__data_i \data_i connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end attribute \src "libresoc.v:49558.1-50615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 attribute \src "libresoc.v:50216.3-50217.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:50389.3-50400.6" wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 attribute \src "libresoc.v:50188.3-50189.61" wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] attribute \src "libresoc.v:50389.3-50400.6" wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 attribute \src "libresoc.v:50190.3-50191.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] attribute \src "libresoc.v:50389.3-50400.6" wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 attribute \src "libresoc.v:50186.3-50187.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] attribute \src "libresoc.v:50214.3-50215.39" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:50536.3-50544.6" wire $0\alu_l_r_alu$next[0:0]$3234 attribute \src "libresoc.v:50158.3-50159.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:50527.3-50535.6" wire $0\alui_l_r_alui$next[0:0]$3231 attribute \src "libresoc.v:50160.3-50161.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:50401.3-50422.6" wire width 64 $0\data_r0__o$next[63:0]$3189 attribute \src "libresoc.v:50182.3-50183.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:50401.3-50422.6" wire $0\data_r0__o_ok$next[0:0]$3190 attribute \src "libresoc.v:50184.3-50185.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:50423.3-50444.6" wire width 32 $0\data_r1__full_cr$next[31:0]$3197 attribute \src "libresoc.v:50178.3-50179.49" wire width 32 $0\data_r1__full_cr[31:0] attribute \src "libresoc.v:50423.3-50444.6" wire $0\data_r1__full_cr_ok$next[0:0]$3198 attribute \src "libresoc.v:50180.3-50181.55" wire $0\data_r1__full_cr_ok[0:0] attribute \src "libresoc.v:50445.3-50466.6" wire width 4 $0\data_r2__cr_a$next[3:0]$3205 attribute \src "libresoc.v:50174.3-50175.43" wire width 4 $0\data_r2__cr_a[3:0] attribute \src "libresoc.v:50445.3-50466.6" wire $0\data_r2__cr_a_ok$next[0:0]$3206 attribute \src "libresoc.v:50176.3-50177.49" wire $0\data_r2__cr_a_ok[0:0] attribute \src "libresoc.v:50545.3-50554.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:50555.3-50564.6" wire width 32 $0\dest2_o[31:0] attribute \src "libresoc.v:50565.3-50574.6" wire width 4 $0\dest3_o[3:0] attribute \src "libresoc.v:49559.7-49559.20" wire $0\initial[0:0] attribute \src "libresoc.v:50344.3-50352.6" wire $0\opc_l_r_opc$next[0:0]$3167 attribute \src "libresoc.v:50200.3-50201.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:50335.3-50343.6" wire $0\opc_l_s_opc$next[0:0]$3164 attribute \src "libresoc.v:50202.3-50203.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:50575.3-50583.6" wire width 3 $0\prev_wr_go$next[2:0]$3240 attribute \src "libresoc.v:50212.3-50213.37" wire width 3 $0\prev_wr_go[2:0] attribute \src "libresoc.v:50289.3-50298.6" wire $0\req_done[0:0] attribute \src "libresoc.v:50380.3-50388.6" wire width 3 $0\req_l_r_req$next[2:0]$3179 attribute \src "libresoc.v:50192.3-50193.39" wire width 3 $0\req_l_r_req[2:0] attribute \src "libresoc.v:50371.3-50379.6" wire width 3 $0\req_l_s_req$next[2:0]$3176 attribute \src "libresoc.v:50194.3-50195.39" wire width 3 $0\req_l_s_req[2:0] attribute \src "libresoc.v:50308.3-50316.6" wire $0\rok_l_r_rdok$next[0:0]$3155 attribute \src "libresoc.v:50208.3-50209.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:50299.3-50307.6" wire $0\rok_l_s_rdok$next[0:0]$3152 attribute \src "libresoc.v:50210.3-50211.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:50326.3-50334.6" wire $0\rst_l_r_rst$next[0:0]$3161 attribute \src "libresoc.v:50204.3-50205.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:50317.3-50325.6" wire $0\rst_l_s_rst$next[0:0]$3158 attribute \src "libresoc.v:50206.3-50207.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:50362.3-50370.6" wire width 6 $0\src_l_r_src$next[5:0]$3173 attribute \src "libresoc.v:50196.3-50197.39" wire width 6 $0\src_l_r_src[5:0] attribute \src "libresoc.v:50353.3-50361.6" wire width 6 $0\src_l_s_src$next[5:0]$3170 attribute \src "libresoc.v:50198.3-50199.39" wire width 6 $0\src_l_s_src[5:0] attribute \src "libresoc.v:50467.3-50476.6" wire width 64 $0\src_r0$next[63:0]$3213 attribute \src "libresoc.v:50172.3-50173.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:50477.3-50486.6" wire width 64 $0\src_r1$next[63:0]$3216 attribute \src "libresoc.v:50170.3-50171.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:50487.3-50496.6" wire width 32 $0\src_r2$next[31:0]$3219 attribute \src "libresoc.v:50168.3-50169.29" wire width 32 $0\src_r2[31:0] attribute \src "libresoc.v:50497.3-50506.6" wire width 4 $0\src_r3$next[3:0]$3222 attribute \src "libresoc.v:50166.3-50167.29" wire width 4 $0\src_r3[3:0] attribute \src "libresoc.v:50507.3-50516.6" wire width 4 $0\src_r4$next[3:0]$3225 attribute \src "libresoc.v:50164.3-50165.29" wire width 4 $0\src_r4[3:0] attribute \src "libresoc.v:50517.3-50526.6" wire width 4 $0\src_r5$next[3:0]$3228 attribute \src "libresoc.v:50162.3-50163.29" wire width 4 $0\src_r5[3:0] attribute \src "libresoc.v:49677.7-49677.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:50389.3-50400.6" wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 attribute \src "libresoc.v:49708.14-49708.47" wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] attribute \src "libresoc.v:50389.3-50400.6" wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 attribute \src "libresoc.v:49712.14-49712.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] attribute \src "libresoc.v:50389.3-50400.6" wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 attribute \src "libresoc.v:49791.13-49791.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] attribute \src "libresoc.v:49815.7-49815.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:50536.3-50544.6" wire $1\alu_l_r_alu$next[0:0]$3235 attribute \src "libresoc.v:49823.7-49823.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:50527.3-50535.6" wire $1\alui_l_r_alui$next[0:0]$3232 attribute \src "libresoc.v:49835.7-49835.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:50401.3-50422.6" wire width 64 $1\data_r0__o$next[63:0]$3191 attribute \src "libresoc.v:49869.14-49869.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:50401.3-50422.6" wire $1\data_r0__o_ok$next[0:0]$3192 attribute \src "libresoc.v:49873.7-49873.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:50423.3-50444.6" wire width 32 $1\data_r1__full_cr$next[31:0]$3199 attribute \src "libresoc.v:49877.14-49877.38" wire width 32 $1\data_r1__full_cr[31:0] attribute \src "libresoc.v:50423.3-50444.6" wire $1\data_r1__full_cr_ok$next[0:0]$3200 attribute \src "libresoc.v:49881.7-49881.33" wire $1\data_r1__full_cr_ok[0:0] attribute \src "libresoc.v:50445.3-50466.6" wire width 4 $1\data_r2__cr_a$next[3:0]$3207 attribute \src "libresoc.v:49885.13-49885.33" wire width 4 $1\data_r2__cr_a[3:0] attribute \src "libresoc.v:50445.3-50466.6" wire $1\data_r2__cr_a_ok$next[0:0]$3208 attribute \src "libresoc.v:49889.7-49889.30" wire $1\data_r2__cr_a_ok[0:0] attribute \src "libresoc.v:50545.3-50554.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:50555.3-50564.6" wire width 32 $1\dest2_o[31:0] attribute \src "libresoc.v:50565.3-50574.6" wire width 4 $1\dest3_o[3:0] attribute \src "libresoc.v:50344.3-50352.6" wire $1\opc_l_r_opc$next[0:0]$3168 attribute \src "libresoc.v:49908.7-49908.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:50335.3-50343.6" wire $1\opc_l_s_opc$next[0:0]$3165 attribute \src "libresoc.v:49912.7-49912.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:50575.3-50583.6" wire width 3 $1\prev_wr_go$next[2:0]$3241 attribute \src "libresoc.v:50012.13-50012.30" wire width 3 $1\prev_wr_go[2:0] attribute \src "libresoc.v:50289.3-50298.6" wire $1\req_done[0:0] attribute \src "libresoc.v:50380.3-50388.6" wire width 3 $1\req_l_r_req$next[2:0]$3180 attribute \src "libresoc.v:50020.13-50020.31" wire width 3 $1\req_l_r_req[2:0] attribute \src "libresoc.v:50371.3-50379.6" wire width 3 $1\req_l_s_req$next[2:0]$3177 attribute \src "libresoc.v:50024.13-50024.31" wire width 3 $1\req_l_s_req[2:0] attribute \src "libresoc.v:50308.3-50316.6" wire $1\rok_l_r_rdok$next[0:0]$3156 attribute \src "libresoc.v:50036.7-50036.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:50299.3-50307.6" wire $1\rok_l_s_rdok$next[0:0]$3153 attribute \src "libresoc.v:50040.7-50040.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:50326.3-50334.6" wire $1\rst_l_r_rst$next[0:0]$3162 attribute \src "libresoc.v:50044.7-50044.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:50317.3-50325.6" wire $1\rst_l_s_rst$next[0:0]$3159 attribute \src "libresoc.v:50048.7-50048.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:50362.3-50370.6" wire width 6 $1\src_l_r_src$next[5:0]$3174 attribute \src "libresoc.v:50068.13-50068.32" wire width 6 $1\src_l_r_src[5:0] attribute \src "libresoc.v:50353.3-50361.6" wire width 6 $1\src_l_s_src$next[5:0]$3171 attribute \src "libresoc.v:50072.13-50072.32" wire width 6 $1\src_l_s_src[5:0] attribute \src "libresoc.v:50467.3-50476.6" wire width 64 $1\src_r0$next[63:0]$3214 attribute \src "libresoc.v:50076.14-50076.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:50477.3-50486.6" wire width 64 $1\src_r1$next[63:0]$3217 attribute \src "libresoc.v:50080.14-50080.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:50487.3-50496.6" wire width 32 $1\src_r2$next[31:0]$3220 attribute \src "libresoc.v:50084.14-50084.28" wire width 32 $1\src_r2[31:0] attribute \src "libresoc.v:50497.3-50506.6" wire width 4 $1\src_r3$next[3:0]$3223 attribute \src "libresoc.v:50088.13-50088.26" wire width 4 $1\src_r3[3:0] attribute \src "libresoc.v:50507.3-50516.6" wire width 4 $1\src_r4$next[3:0]$3226 attribute \src "libresoc.v:50092.13-50092.26" wire width 4 $1\src_r4[3:0] attribute \src "libresoc.v:50517.3-50526.6" wire width 4 $1\src_r5$next[3:0]$3229 attribute \src "libresoc.v:50096.13-50096.26" wire width 4 $1\src_r5[3:0] attribute \src "libresoc.v:50401.3-50422.6" wire width 64 $2\data_r0__o$next[63:0]$3193 attribute \src "libresoc.v:50401.3-50422.6" wire $2\data_r0__o_ok$next[0:0]$3194 attribute \src "libresoc.v:50423.3-50444.6" wire width 32 $2\data_r1__full_cr$next[31:0]$3201 attribute \src "libresoc.v:50423.3-50444.6" wire $2\data_r1__full_cr_ok$next[0:0]$3202 attribute \src "libresoc.v:50445.3-50466.6" wire width 4 $2\data_r2__cr_a$next[3:0]$3209 attribute \src "libresoc.v:50445.3-50466.6" wire $2\data_r2__cr_a_ok$next[0:0]$3210 attribute \src "libresoc.v:50401.3-50422.6" wire $3\data_r0__o_ok$next[0:0]$3195 attribute \src "libresoc.v:50423.3-50444.6" wire $3\data_r1__full_cr_ok$next[0:0]$3203 attribute \src "libresoc.v:50445.3-50466.6" wire $3\data_r2__cr_a_ok$next[0:0]$3211 attribute \src "libresoc.v:50102.18-50102.112" wire width 6 $and$libresoc.v:50102$3064_Y attribute \src "libresoc.v:50103.19-50103.125" wire $and$libresoc.v:50103$3065_Y attribute \src "libresoc.v:50104.19-50104.125" wire $and$libresoc.v:50104$3066_Y attribute \src "libresoc.v:50105.19-50105.125" wire $and$libresoc.v:50105$3067_Y attribute \src "libresoc.v:50106.19-50106.141" wire width 3 $and$libresoc.v:50106$3068_Y attribute \src "libresoc.v:50107.19-50107.121" wire width 3 $and$libresoc.v:50107$3069_Y attribute \src "libresoc.v:50108.19-50108.127" wire $and$libresoc.v:50108$3070_Y attribute \src "libresoc.v:50109.19-50109.127" wire $and$libresoc.v:50109$3071_Y attribute \src "libresoc.v:50110.19-50110.127" wire $and$libresoc.v:50110$3072_Y attribute \src "libresoc.v:50111.18-50111.110" wire $and$libresoc.v:50111$3073_Y attribute \src "libresoc.v:50113.18-50113.98" wire $and$libresoc.v:50113$3075_Y attribute \src "libresoc.v:50115.18-50115.100" wire $and$libresoc.v:50115$3077_Y attribute \src "libresoc.v:50116.18-50116.149" wire width 3 $and$libresoc.v:50116$3078_Y attribute \src "libresoc.v:50118.18-50118.119" wire width 3 $and$libresoc.v:50118$3080_Y attribute \src "libresoc.v:50121.18-50121.116" wire $and$libresoc.v:50121$3083_Y attribute \src "libresoc.v:50125.17-50125.123" wire $and$libresoc.v:50125$3087_Y attribute \src "libresoc.v:50127.18-50127.113" wire $and$libresoc.v:50127$3089_Y attribute \src "libresoc.v:50128.18-50128.125" wire width 3 $and$libresoc.v:50128$3090_Y attribute \src "libresoc.v:50130.18-50130.112" wire $and$libresoc.v:50130$3092_Y attribute \src "libresoc.v:50132.18-50132.125" wire $and$libresoc.v:50132$3094_Y attribute \src "libresoc.v:50133.18-50133.125" wire $and$libresoc.v:50133$3095_Y attribute \src "libresoc.v:50134.18-50134.117" wire $and$libresoc.v:50134$3096_Y attribute \src "libresoc.v:50139.18-50139.129" wire $and$libresoc.v:50139$3101_Y attribute \src "libresoc.v:50140.18-50140.124" wire width 3 $and$libresoc.v:50140$3102_Y attribute \src "libresoc.v:50143.18-50143.116" wire $and$libresoc.v:50143$3105_Y attribute \src "libresoc.v:50144.18-50144.122" wire $and$libresoc.v:50144$3106_Y attribute \src "libresoc.v:50145.18-50145.119" wire $and$libresoc.v:50145$3107_Y attribute \src "libresoc.v:50153.18-50153.133" wire $and$libresoc.v:50153$3115_Y attribute \src "libresoc.v:50154.18-50154.131" wire $and$libresoc.v:50154$3116_Y attribute \src "libresoc.v:50155.18-50155.182" wire width 6 $and$libresoc.v:50155$3117_Y attribute \src "libresoc.v:50156.18-50156.113" wire width 6 $and$libresoc.v:50156$3118_Y attribute \src "libresoc.v:50129.18-50129.113" wire $eq$libresoc.v:50129$3091_Y attribute \src "libresoc.v:50131.18-50131.119" wire $eq$libresoc.v:50131$3093_Y attribute \src "libresoc.v:50112.18-50112.97" wire $not$libresoc.v:50112$3074_Y attribute \src "libresoc.v:50114.18-50114.99" wire $not$libresoc.v:50114$3076_Y attribute \src "libresoc.v:50117.18-50117.113" wire width 3 $not$libresoc.v:50117$3079_Y attribute \src "libresoc.v:50120.18-50120.106" wire $not$libresoc.v:50120$3082_Y attribute \src "libresoc.v:50126.18-50126.119" wire $not$libresoc.v:50126$3088_Y attribute \src "libresoc.v:50141.17-50141.113" wire width 6 $not$libresoc.v:50141$3103_Y attribute \src "libresoc.v:50157.18-50157.114" wire width 6 $not$libresoc.v:50157$3119_Y attribute \src "libresoc.v:50124.18-50124.112" wire $or$libresoc.v:50124$3086_Y attribute \src "libresoc.v:50135.18-50135.122" wire $or$libresoc.v:50135$3097_Y attribute \src "libresoc.v:50136.18-50136.124" wire $or$libresoc.v:50136$3098_Y attribute \src "libresoc.v:50137.18-50137.155" wire width 3 $or$libresoc.v:50137$3099_Y attribute \src "libresoc.v:50138.18-50138.194" wire width 6 $or$libresoc.v:50138$3100_Y attribute \src "libresoc.v:50142.18-50142.120" wire width 3 $or$libresoc.v:50142$3104_Y attribute \src "libresoc.v:50152.17-50152.117" wire width 6 $or$libresoc.v:50152$3114_Y attribute \src "libresoc.v:50101.17-50101.104" wire $reduce_and$libresoc.v:50101$3063_Y attribute \src "libresoc.v:50119.18-50119.106" wire $reduce_or$libresoc.v:50119$3081_Y attribute \src "libresoc.v:50122.18-50122.113" wire $reduce_or$libresoc.v:50122$3084_Y attribute \src "libresoc.v:50123.18-50123.112" wire $reduce_or$libresoc.v:50123$3085_Y attribute \src "libresoc.v:50146.18-50146.118" wire width 64 $ternary$libresoc.v:50146$3108_Y attribute \src "libresoc.v:50147.18-50147.118" wire width 64 $ternary$libresoc.v:50147$3109_Y attribute \src "libresoc.v:50148.18-50148.118" wire width 32 $ternary$libresoc.v:50148$3110_Y attribute \src "libresoc.v:50149.18-50149.118" wire width 4 $ternary$libresoc.v:50149$3111_Y attribute \src "libresoc.v:50150.18-50150.118" wire width 4 $ternary$libresoc.v:50150$3112_Y attribute \src "libresoc.v:50151.18-50151.118" wire width 4 $ternary$libresoc.v:50151$3113_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 3 \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 3 \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 3 \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 3 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 3 \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 3 \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 6 \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 3 \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 6 \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 3 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 3 \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 6 \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 32 \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 4 \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_cr0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_cr0_cr_a$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_cr0_cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_cr0_cr_c attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_cr0_cr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_cr0_cr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_cr0_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_cr0_cr_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_cr0_cr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_cr0_cr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \alu_cr0_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \alu_cr0_full_cr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_cr0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_cr0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_cr0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_cr0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_cr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_cr0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_cr0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 24 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 6 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 5 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 input 9 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 output 8 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 6 input 7 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 18 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 17 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 3 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 32 \data_r1__full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 32 \data_r1__full_cr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__full_cr_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r2__cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r2__cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 19 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 32 output 21 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 20 \full_cr_ok attribute \src "libresoc.v:49559.7-49559.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 16 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 6 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 3 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 11 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 10 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 32 input 12 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 13 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 14 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 15 \src6_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 32 \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 32 \src_r2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r3$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r4$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 4 \src_r5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:50102$3064 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 connect \Y $and$libresoc.v:50102$3064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:50103$3065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:50103$3065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:50104$3066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:50104$3066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:50105$3067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:50105$3067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:50106$3068 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } connect \Y $and$libresoc.v:50106$3068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:50107$3069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:50107$3069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:50108$3070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:50108$3070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:50109$3071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:50109$3071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:50110$3072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:50110$3072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:50111$3073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 connect \Y $and$libresoc.v:50111$3073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:50113$3075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 connect \Y $and$libresoc.v:50113$3075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:50115$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 connect \Y $and$libresoc.v:50115$3077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:50116$3078 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:50116$3078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:50118$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 connect \Y $and$libresoc.v:50118$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:50121$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 connect \Y $and$libresoc.v:50121$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:50125$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:50125$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:50127$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 connect \Y $and$libresoc.v:50127$3089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:50128$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:50128$3090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:50130$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 connect \Y $and$libresoc.v:50130$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:50132$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i connect \Y $and$libresoc.v:50132$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:50133$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o connect \Y $and$libresoc.v:50133$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:50134$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o connect \Y $and$libresoc.v:50134$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:50139$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:50139$3101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:50140$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:50140$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:50143$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:50143$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:50144$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:50144$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:50145$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:50145$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:50153$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:50153$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:50154$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:50154$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:50155$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:50155$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:50156$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 connect \Y $and$libresoc.v:50156$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:50129$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 connect \Y $eq$libresoc.v:50129$3091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:50131$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:50131$3093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:50112$3074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:50112$3074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:50114$3076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:50114$3076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:50117$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:50117$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:50120$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:50120$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:50126$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i connect \Y $not$libresoc.v:50126$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:50141$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:50141$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:50157$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:50157$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:50124$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 connect \Y $or$libresoc.v:50124$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:50135$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:50135$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:50136$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:50136$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:50137$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:50137$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:50138$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:50138$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:50142$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:50142$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:50152$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:50152$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:50101$3063 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $reduce_and$libresoc.v:50101$3063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:50119$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 connect \Y $reduce_or$libresoc.v:50119$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:50122$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:50122$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:50123$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:50123$3085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:50146$3108 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] connect \Y $ternary$libresoc.v:50146$3108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:50147$3109 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] connect \Y $ternary$libresoc.v:50147$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:50148$3110 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:50148$3110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:50149$3111 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] connect \Y $ternary$libresoc.v:50149$3111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:50150$3112 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] connect \Y $ternary$libresoc.v:50150$3112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:50151$3113 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] connect \Y $ternary$libresoc.v:50151$3113_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:50218.11-50240.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \alu_cr0_cr_a connect \cr_a$2 \alu_cr0_cr_a$2 connect \cr_a_ok \cr_a_ok connect \cr_b \alu_cr0_cr_b connect \cr_c \alu_cr0_cr_c connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit connect \cr_op__insn \alu_cr0_cr_op__insn connect \cr_op__insn_type \alu_cr0_cr_op__insn_type connect \full_cr \alu_cr0_full_cr connect \full_cr$1 \alu_cr0_full_cr$1 connect \full_cr_ok \full_cr_ok connect \n_ready_i \alu_cr0_n_ready_i connect \n_valid_o \alu_cr0_n_valid_o connect \o \alu_cr0_o connect \o_ok \o_ok connect \p_ready_o \alu_cr0_p_ready_o connect \p_valid_i \alu_cr0_p_valid_i connect \ra \alu_cr0_ra connect \rb \alu_cr0_rb end attribute \module_not_derived 1 attribute \src "libresoc.v:50241.14-50247.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:50248.15-50254.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:50255.14-50261.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:50262.14-50268.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:50269.14-50275.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:50276.14-50281.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:50282.14-50288.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:49559.7-49559.20" process $proc$libresoc.v:49559$3242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:49677.7-49677.24" process $proc$libresoc.v:49677$3243 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:49708.14-49708.47" process $proc$libresoc.v:49708$3244 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end attribute \src "libresoc.v:49712.14-49712.41" process $proc$libresoc.v:49712$3245 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end attribute \src "libresoc.v:49791.13-49791.45" process $proc$libresoc.v:49791$3246 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end attribute \src "libresoc.v:49815.7-49815.26" process $proc$libresoc.v:49815$3247 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:49823.7-49823.25" process $proc$libresoc.v:49823$3248 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:49835.7-49835.27" process $proc$libresoc.v:49835$3249 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:49869.14-49869.47" process $proc$libresoc.v:49869$3250 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:49873.7-49873.27" process $proc$libresoc.v:49873$3251 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:49877.14-49877.38" process $proc$libresoc.v:49877$3252 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end attribute \src "libresoc.v:49881.7-49881.33" process $proc$libresoc.v:49881$3253 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end attribute \src "libresoc.v:49885.13-49885.33" process $proc$libresoc.v:49885$3254 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end attribute \src "libresoc.v:49889.7-49889.30" process $proc$libresoc.v:49889$3255 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end attribute \src "libresoc.v:49908.7-49908.25" process $proc$libresoc.v:49908$3256 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:49912.7-49912.25" process $proc$libresoc.v:49912$3257 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:50012.13-50012.30" process $proc$libresoc.v:50012$3258 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end attribute \src "libresoc.v:50020.13-50020.31" process $proc$libresoc.v:50020$3259 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end attribute \src "libresoc.v:50024.13-50024.31" process $proc$libresoc.v:50024$3260 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end attribute \src "libresoc.v:50036.7-50036.26" process $proc$libresoc.v:50036$3261 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:50040.7-50040.26" process $proc$libresoc.v:50040$3262 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:50044.7-50044.25" process $proc$libresoc.v:50044$3263 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:50048.7-50048.25" process $proc$libresoc.v:50048$3264 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:50068.13-50068.32" process $proc$libresoc.v:50068$3265 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end attribute \src "libresoc.v:50072.13-50072.32" process $proc$libresoc.v:50072$3266 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end attribute \src "libresoc.v:50076.14-50076.43" process $proc$libresoc.v:50076$3267 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:50080.14-50080.43" process $proc$libresoc.v:50080$3268 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:50084.14-50084.28" process $proc$libresoc.v:50084$3269 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end attribute \src "libresoc.v:50088.13-50088.26" process $proc$libresoc.v:50088$3270 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end attribute \src "libresoc.v:50092.13-50092.26" process $proc$libresoc.v:50092$3271 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end attribute \src "libresoc.v:50096.13-50096.26" process $proc$libresoc.v:50096$3272 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end attribute \src "libresoc.v:50158.3-50159.39" process $proc$libresoc.v:50158$3120 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:50160.3-50161.43" process $proc$libresoc.v:50160$3121 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:50162.3-50163.29" process $proc$libresoc.v:50162$3122 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end attribute \src "libresoc.v:50164.3-50165.29" process $proc$libresoc.v:50164$3123 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end attribute \src "libresoc.v:50166.3-50167.29" process $proc$libresoc.v:50166$3124 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end attribute \src "libresoc.v:50168.3-50169.29" process $proc$libresoc.v:50168$3125 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end attribute \src "libresoc.v:50170.3-50171.29" process $proc$libresoc.v:50170$3126 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:50172.3-50173.29" process $proc$libresoc.v:50172$3127 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:50174.3-50175.43" process $proc$libresoc.v:50174$3128 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end attribute \src "libresoc.v:50176.3-50177.49" process $proc$libresoc.v:50176$3129 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end attribute \src "libresoc.v:50178.3-50179.49" process $proc$libresoc.v:50178$3130 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end attribute \src "libresoc.v:50180.3-50181.55" process $proc$libresoc.v:50180$3131 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end attribute \src "libresoc.v:50182.3-50183.37" process $proc$libresoc.v:50182$3132 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:50184.3-50185.43" process $proc$libresoc.v:50184$3133 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:50186.3-50187.65" process $proc$libresoc.v:50186$3134 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end attribute \src "libresoc.v:50188.3-50189.61" process $proc$libresoc.v:50188$3135 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end attribute \src "libresoc.v:50190.3-50191.55" process $proc$libresoc.v:50190$3136 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end attribute \src "libresoc.v:50192.3-50193.39" process $proc$libresoc.v:50192$3137 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end attribute \src "libresoc.v:50194.3-50195.39" process $proc$libresoc.v:50194$3138 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end attribute \src "libresoc.v:50196.3-50197.39" process $proc$libresoc.v:50196$3139 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end attribute \src "libresoc.v:50198.3-50199.39" process $proc$libresoc.v:50198$3140 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end attribute \src "libresoc.v:50200.3-50201.39" process $proc$libresoc.v:50200$3141 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:50202.3-50203.39" process $proc$libresoc.v:50202$3142 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:50204.3-50205.39" process $proc$libresoc.v:50204$3143 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:50206.3-50207.39" process $proc$libresoc.v:50206$3144 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:50208.3-50209.41" process $proc$libresoc.v:50208$3145 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:50210.3-50211.41" process $proc$libresoc.v:50210$3146 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:50212.3-50213.37" process $proc$libresoc.v:50212$3147 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end attribute \src "libresoc.v:50214.3-50215.39" process $proc$libresoc.v:50214$3148 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:50216.3-50217.25" process $proc$libresoc.v:50216$3149 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:50289.3-50298.6" process $proc$libresoc.v:50289$3150 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:50290.5-50290.29" switch \initial attribute \src "libresoc.v:50290.9-50290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$47 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:50299.3-50307.6" process $proc$libresoc.v:50299$3151 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 attribute \src "libresoc.v:50300.5-50300.29" switch \initial attribute \src "libresoc.v:50300.9-50300.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$3153 1'0 case assign $1\rok_l_s_rdok$next[0:0]$3153 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 end attribute \src "libresoc.v:50308.3-50316.6" process $proc$libresoc.v:50308$3154 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 attribute \src "libresoc.v:50309.5-50309.29" switch \initial attribute \src "libresoc.v:50309.9-50309.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$3156 1'1 case assign $1\rok_l_r_rdok$next[0:0]$3156 \$65 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 end attribute \src "libresoc.v:50317.3-50325.6" process $proc$libresoc.v:50317$3157 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 attribute \src "libresoc.v:50318.5-50318.29" switch \initial attribute \src "libresoc.v:50318.9-50318.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$3159 1'0 case assign $1\rst_l_s_rst$next[0:0]$3159 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 end attribute \src "libresoc.v:50326.3-50334.6" process $proc$libresoc.v:50326$3160 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 attribute \src "libresoc.v:50327.5-50327.29" switch \initial attribute \src "libresoc.v:50327.9-50327.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$3162 1'1 case assign $1\rst_l_r_rst$next[0:0]$3162 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 end attribute \src "libresoc.v:50335.3-50343.6" process $proc$libresoc.v:50335$3163 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 attribute \src "libresoc.v:50336.5-50336.29" switch \initial attribute \src "libresoc.v:50336.9-50336.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$3165 1'0 case assign $1\opc_l_s_opc$next[0:0]$3165 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 end attribute \src "libresoc.v:50344.3-50352.6" process $proc$libresoc.v:50344$3166 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 attribute \src "libresoc.v:50345.5-50345.29" switch \initial attribute \src "libresoc.v:50345.9-50345.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$3168 1'1 case assign $1\opc_l_r_opc$next[0:0]$3168 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 end attribute \src "libresoc.v:50353.3-50361.6" process $proc$libresoc.v:50353$3169 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 attribute \src "libresoc.v:50354.5-50354.29" switch \initial attribute \src "libresoc.v:50354.9-50354.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[5:0]$3171 6'000000 case assign $1\src_l_s_src$next[5:0]$3171 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 end attribute \src "libresoc.v:50362.3-50370.6" process $proc$libresoc.v:50362$3172 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 attribute \src "libresoc.v:50363.5-50363.29" switch \initial attribute \src "libresoc.v:50363.9-50363.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[5:0]$3174 6'111111 case assign $1\src_l_r_src$next[5:0]$3174 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 end attribute \src "libresoc.v:50371.3-50379.6" process $proc$libresoc.v:50371$3175 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 attribute \src "libresoc.v:50372.5-50372.29" switch \initial attribute \src "libresoc.v:50372.9-50372.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[2:0]$3177 3'000 case assign $1\req_l_s_req$next[2:0]$3177 \$67 end sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 end attribute \src "libresoc.v:50380.3-50388.6" process $proc$libresoc.v:50380$3178 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 attribute \src "libresoc.v:50381.5-50381.29" switch \initial attribute \src "libresoc.v:50381.9-50381.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[2:0]$3180 3'111 case assign $1\req_l_r_req$next[2:0]$3180 \$69 end sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 end attribute \src "libresoc.v:50389.3-50400.6" process $proc$libresoc.v:50389$3181 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 attribute \src "libresoc.v:50390.5-50390.29" switch \initial attribute \src "libresoc.v:50390.9-50390.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } case assign $1\alu_cr0_cr_op__fn_unit$next[13:0]$3185 \alu_cr0_cr_op__fn_unit assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type end sync always update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[13:0]$3182 update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 end attribute \src "libresoc.v:50401.3-50422.6" process $proc$libresoc.v:50401$3188 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 assign { } { } assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 attribute \src "libresoc.v:50402.5-50402.29" switch \initial attribute \src "libresoc.v:50402.9-50402.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$3192 $1\data_r0__o$next[63:0]$3191 } { \o_ok \alu_cr0_o } case assign $1\data_r0__o$next[63:0]$3191 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$3192 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$3194 $2\data_r0__o$next[63:0]$3193 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$3193 $1\data_r0__o$next[63:0]$3191 assign $2\data_r0__o_ok$next[0:0]$3194 $1\data_r0__o_ok$next[0:0]$3192 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$3195 1'0 case assign $3\data_r0__o_ok$next[0:0]$3195 $2\data_r0__o_ok$next[0:0]$3194 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 end attribute \src "libresoc.v:50423.3-50444.6" process $proc$libresoc.v:50423$3196 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 assign { } { } assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 attribute \src "libresoc.v:50424.5-50424.29" switch \initial attribute \src "libresoc.v:50424.9-50424.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__full_cr_ok$next[0:0]$3200 $1\data_r1__full_cr$next[31:0]$3199 } { \full_cr_ok \alu_cr0_full_cr } case assign $1\data_r1__full_cr$next[31:0]$3199 \data_r1__full_cr assign $1\data_r1__full_cr_ok$next[0:0]$3200 \data_r1__full_cr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__full_cr_ok$next[0:0]$3202 $2\data_r1__full_cr$next[31:0]$3201 } 33'000000000000000000000000000000000 case assign $2\data_r1__full_cr$next[31:0]$3201 $1\data_r1__full_cr$next[31:0]$3199 assign $2\data_r1__full_cr_ok$next[0:0]$3202 $1\data_r1__full_cr_ok$next[0:0]$3200 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__full_cr_ok$next[0:0]$3203 1'0 case assign $3\data_r1__full_cr_ok$next[0:0]$3203 $2\data_r1__full_cr_ok$next[0:0]$3202 end sync always update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 end attribute \src "libresoc.v:50445.3-50466.6" process $proc$libresoc.v:50445$3204 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 assign { } { } assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 attribute \src "libresoc.v:50446.5-50446.29" switch \initial attribute \src "libresoc.v:50446.9-50446.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__cr_a_ok$next[0:0]$3208 $1\data_r2__cr_a$next[3:0]$3207 } { \cr_a_ok \alu_cr0_cr_a } case assign $1\data_r2__cr_a$next[3:0]$3207 \data_r2__cr_a assign $1\data_r2__cr_a_ok$next[0:0]$3208 \data_r2__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__cr_a_ok$next[0:0]$3210 $2\data_r2__cr_a$next[3:0]$3209 } 5'00000 case assign $2\data_r2__cr_a$next[3:0]$3209 $1\data_r2__cr_a$next[3:0]$3207 assign $2\data_r2__cr_a_ok$next[0:0]$3210 $1\data_r2__cr_a_ok$next[0:0]$3208 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__cr_a_ok$next[0:0]$3211 1'0 case assign $3\data_r2__cr_a_ok$next[0:0]$3211 $2\data_r2__cr_a_ok$next[0:0]$3210 end sync always update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 end attribute \src "libresoc.v:50467.3-50476.6" process $proc$libresoc.v:50467$3212 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 attribute \src "libresoc.v:50468.5-50468.29" switch \initial attribute \src "libresoc.v:50468.9-50468.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$3214 \src1_i case assign $1\src_r0$next[63:0]$3214 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$3213 end attribute \src "libresoc.v:50477.3-50486.6" process $proc$libresoc.v:50477$3215 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 attribute \src "libresoc.v:50478.5-50478.29" switch \initial attribute \src "libresoc.v:50478.9-50478.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$3217 \src2_i case assign $1\src_r1$next[63:0]$3217 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$3216 end attribute \src "libresoc.v:50487.3-50496.6" process $proc$libresoc.v:50487$3218 assign { } { } assign { } { } assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 attribute \src "libresoc.v:50488.5-50488.29" switch \initial attribute \src "libresoc.v:50488.9-50488.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[31:0]$3220 \src3_i case assign $1\src_r2$next[31:0]$3220 \src_r2 end sync always update \src_r2$next $0\src_r2$next[31:0]$3219 end attribute \src "libresoc.v:50497.3-50506.6" process $proc$libresoc.v:50497$3221 assign { } { } assign { } { } assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 attribute \src "libresoc.v:50498.5-50498.29" switch \initial attribute \src "libresoc.v:50498.9-50498.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r3$next[3:0]$3223 \src4_i case assign $1\src_r3$next[3:0]$3223 \src_r3 end sync always update \src_r3$next $0\src_r3$next[3:0]$3222 end attribute \src "libresoc.v:50507.3-50516.6" process $proc$libresoc.v:50507$3224 assign { } { } assign { } { } assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 attribute \src "libresoc.v:50508.5-50508.29" switch \initial attribute \src "libresoc.v:50508.9-50508.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r4$next[3:0]$3226 \src5_i case assign $1\src_r4$next[3:0]$3226 \src_r4 end sync always update \src_r4$next $0\src_r4$next[3:0]$3225 end attribute \src "libresoc.v:50517.3-50526.6" process $proc$libresoc.v:50517$3227 assign { } { } assign { } { } assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 attribute \src "libresoc.v:50518.5-50518.29" switch \initial attribute \src "libresoc.v:50518.9-50518.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r5$next[3:0]$3229 \src6_i case assign $1\src_r5$next[3:0]$3229 \src_r5 end sync always update \src_r5$next $0\src_r5$next[3:0]$3228 end attribute \src "libresoc.v:50527.3-50535.6" process $proc$libresoc.v:50527$3230 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 attribute \src "libresoc.v:50528.5-50528.29" switch \initial attribute \src "libresoc.v:50528.9-50528.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$3232 1'1 case assign $1\alui_l_r_alui$next[0:0]$3232 \$89 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 end attribute \src "libresoc.v:50536.3-50544.6" process $proc$libresoc.v:50536$3233 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 attribute \src "libresoc.v:50537.5-50537.29" switch \initial attribute \src "libresoc.v:50537.9-50537.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$3235 1'1 case assign $1\alu_l_r_alu$next[0:0]$3235 \$91 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 end attribute \src "libresoc.v:50545.3-50554.6" process $proc$libresoc.v:50545$3236 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:50546.5-50546.29" switch \initial attribute \src "libresoc.v:50546.9-50546.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:50555.3-50564.6" process $proc$libresoc.v:50555$3237 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] attribute \src "libresoc.v:50556.5-50556.29" switch \initial attribute \src "libresoc.v:50556.9-50556.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[31:0] \data_r1__full_cr case assign $1\dest2_o[31:0] 0 end sync always update \dest2_o $0\dest2_o[31:0] end attribute \src "libresoc.v:50565.3-50574.6" process $proc$libresoc.v:50565$3238 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] attribute \src "libresoc.v:50566.5-50566.29" switch \initial attribute \src "libresoc.v:50566.9-50566.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[3:0] \data_r2__cr_a case assign $1\dest3_o[3:0] 4'0000 end sync always update \dest3_o $0\dest3_o[3:0] end attribute \src "libresoc.v:50575.3-50583.6" process $proc$libresoc.v:50575$3239 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 attribute \src "libresoc.v:50576.5-50576.29" switch \initial attribute \src "libresoc.v:50576.9-50576.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[2:0]$3241 3'000 case assign $1\prev_wr_go$next[2:0]$3241 \$21 end sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 end connect \$5 $reduce_and$libresoc.v:50101$3063_Y connect \$99 $and$libresoc.v:50102$3064_Y connect \$101 $and$libresoc.v:50103$3065_Y connect \$103 $and$libresoc.v:50104$3066_Y connect \$105 $and$libresoc.v:50105$3067_Y connect \$107 $and$libresoc.v:50106$3068_Y connect \$109 $and$libresoc.v:50107$3069_Y connect \$111 $and$libresoc.v:50108$3070_Y connect \$113 $and$libresoc.v:50109$3071_Y connect \$115 $and$libresoc.v:50110$3072_Y connect \$11 $and$libresoc.v:50111$3073_Y connect \$13 $not$libresoc.v:50112$3074_Y connect \$15 $and$libresoc.v:50113$3075_Y connect \$17 $not$libresoc.v:50114$3076_Y connect \$19 $and$libresoc.v:50115$3077_Y connect \$21 $and$libresoc.v:50116$3078_Y connect \$25 $not$libresoc.v:50117$3079_Y connect \$27 $and$libresoc.v:50118$3080_Y connect \$24 $reduce_or$libresoc.v:50119$3081_Y connect \$23 $not$libresoc.v:50120$3082_Y connect \$31 $and$libresoc.v:50121$3083_Y connect \$33 $reduce_or$libresoc.v:50122$3084_Y connect \$35 $reduce_or$libresoc.v:50123$3085_Y connect \$37 $or$libresoc.v:50124$3086_Y connect \$3 $and$libresoc.v:50125$3087_Y connect \$39 $not$libresoc.v:50126$3088_Y connect \$41 $and$libresoc.v:50127$3089_Y connect \$43 $and$libresoc.v:50128$3090_Y connect \$45 $eq$libresoc.v:50129$3091_Y connect \$47 $and$libresoc.v:50130$3092_Y connect \$49 $eq$libresoc.v:50131$3093_Y connect \$51 $and$libresoc.v:50132$3094_Y connect \$53 $and$libresoc.v:50133$3095_Y connect \$55 $and$libresoc.v:50134$3096_Y connect \$57 $or$libresoc.v:50135$3097_Y connect \$59 $or$libresoc.v:50136$3098_Y connect \$61 $or$libresoc.v:50137$3099_Y connect \$63 $or$libresoc.v:50138$3100_Y connect \$65 $and$libresoc.v:50139$3101_Y connect \$67 $and$libresoc.v:50140$3102_Y connect \$6 $not$libresoc.v:50141$3103_Y connect \$69 $or$libresoc.v:50142$3104_Y connect \$71 $and$libresoc.v:50143$3105_Y connect \$73 $and$libresoc.v:50144$3106_Y connect \$75 $and$libresoc.v:50145$3107_Y connect \$77 $ternary$libresoc.v:50146$3108_Y connect \$79 $ternary$libresoc.v:50147$3109_Y connect \$81 $ternary$libresoc.v:50148$3110_Y connect \$83 $ternary$libresoc.v:50149$3111_Y connect \$85 $ternary$libresoc.v:50150$3112_Y connect \$87 $ternary$libresoc.v:50151$3113_Y connect \$8 $or$libresoc.v:50152$3114_Y connect \$89 $and$libresoc.v:50153$3115_Y connect \$91 $and$libresoc.v:50154$3116_Y connect \$93 $and$libresoc.v:50155$3117_Y connect \$95 $and$libresoc.v:50156$3118_Y connect \$97 $not$libresoc.v:50157$3119_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 connect \cu_rd__rel_o \$99 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_cr0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_cr0_p_valid_i \alui_l_q_alui connect \alu_cr0_cr_c \$87 connect \alu_cr0_cr_b \$85 connect \alu_cr0_cr_a$2 \$83 connect \alu_cr0_full_cr$1 \$81 connect \alu_cr0_rb \$79 connect \alu_cr0_ra \$77 connect \cu_wrmask_o { \$75 \$73 \$71 } connect \reset_r \$63 connect \reset_w \$61 connect \rst_r \$59 connect \reset \$57 connect \wr_any \$37 connect \cu_done_o \$31 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$19 connect \alu_done_dly$next \alu_done connect \alu_done \alu_cr0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$15 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end attribute \src "libresoc.v:50619.1-50668.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l attribute \src "libresoc.v:50620.7-50620.20" wire $0\initial[0:0] attribute \src "libresoc.v:50656.3-50664.6" wire $0\q_int$next[0:0]$3280 attribute \src "libresoc.v:50654.3-50655.27" wire $0\q_int[0:0] attribute \src "libresoc.v:50656.3-50664.6" wire $1\q_int$next[0:0]$3281 attribute \src "libresoc.v:50638.7-50638.19" wire $1\q_int[0:0] attribute \src "libresoc.v:50651.17-50651.96" wire $and$libresoc.v:50651$3275_Y attribute \src "libresoc.v:50650.17-50650.92" wire $not$libresoc.v:50650$3274_Y attribute \src "libresoc.v:50653.17-50653.92" wire $not$libresoc.v:50653$3277_Y attribute \src "libresoc.v:50649.17-50649.98" wire $or$libresoc.v:50649$3273_Y attribute \src "libresoc.v:50652.17-50652.97" wire $or$libresoc.v:50652$3276_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:50620.7-50620.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:50651$3275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:50651$3275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:50650$3274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc connect \Y $not$libresoc.v:50650$3274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:50653$3277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc connect \Y $not$libresoc.v:50653$3277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:50649$3273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int connect \Y $or$libresoc.v:50649$3273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:50652$3276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc connect \Y $or$libresoc.v:50652$3276_Y end attribute \src "libresoc.v:50620.7-50620.20" process $proc$libresoc.v:50620$3282 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:50638.7-50638.19" process $proc$libresoc.v:50638$3283 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:50654.3-50655.27" process $proc$libresoc.v:50654$3278 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:50656.3-50664.6" process $proc$libresoc.v:50656$3279 assign { } { } assign { } { } assign $0\q_int$next[0:0]$3280 $1\q_int$next[0:0]$3281 attribute \src "libresoc.v:50657.5-50657.29" switch \initial attribute \src "libresoc.v:50657.9-50657.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$3281 1'0 case assign $1\q_int$next[0:0]$3281 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$3280 end connect \$9 $or$libresoc.v:50649$3273_Y connect \$1 $not$libresoc.v:50650$3274_Y connect \$3 $and$libresoc.v:50651$3275_Y connect \$5 $or$libresoc.v:50652$3276_Y connect \$7 $not$libresoc.v:50653$3277_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end attribute \src "libresoc.v:50672.1-51413.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg attribute \src "libresoc.v:51217.3-51229.6" wire $0\d_cr_req[0:0] attribute \src "libresoc.v:51024.3-51033.6" wire $0\d_gpr_req[0:0] attribute \src "libresoc.v:51230.3-51245.6" wire $0\d_xer_req[0:0] attribute \src "libresoc.v:51006.3-51023.6" wire $0\dmi_ack_o[0:0] attribute \src "libresoc.v:51246.3-51279.6" wire width 64 $0\dmi_dout[63:0] attribute \src "libresoc.v:51208.3-51216.6" wire $0\dmi_read_log_data$next[0:0]$3398 attribute \src "libresoc.v:50984.3-50985.51" wire $0\dmi_read_log_data[0:0] attribute \src "libresoc.v:51199.3-51207.6" wire $0\dmi_read_log_data_1$next[0:0]$3395 attribute \src "libresoc.v:50986.3-50987.55" wire $0\dmi_read_log_data_1[0:0] attribute \src "libresoc.v:51034.3-51042.6" wire $0\dmi_req_i_1$next[0:0]$3361 attribute \src "libresoc.v:50996.3-50997.39" wire $0\dmi_req_i_1[0:0] attribute \src "libresoc.v:51370.3-51403.6" wire $0\do_dmi_log_rd$next[0:0]$3425 attribute \src "libresoc.v:50998.3-50999.43" wire $0\do_dmi_log_rd[0:0] attribute \src "libresoc.v:51340.3-51369.6" wire $0\do_icreset$next[0:0]$3418 attribute \src "libresoc.v:51000.3-51001.37" wire $0\do_icreset[0:0] attribute \src "libresoc.v:51310.3-51339.6" wire $0\do_reset$next[0:0]$3411 attribute \src "libresoc.v:51002.3-51003.33" wire $0\do_reset[0:0] attribute \src "libresoc.v:51280.3-51309.6" wire $0\do_step$next[0:0]$3404 attribute \src "libresoc.v:51004.3-51005.31" wire $0\do_step[0:0] attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $0\gspr_index$next[6:0]$3383 attribute \src "libresoc.v:50990.3-50991.37" wire width 7 $0\gspr_index[6:0] attribute \src "libresoc.v:50673.7-50673.20" wire $0\initial[0:0] attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $0\log_dmi_addr$next[31:0]$3389 attribute \src "libresoc.v:50988.3-50989.41" wire width 32 $0\log_dmi_addr[31:0] attribute \src "libresoc.v:51093.3-51136.6" wire $0\stopping$next[0:0]$3374 attribute \src "libresoc.v:50992.3-50993.33" wire $0\stopping[0:0] attribute \src "libresoc.v:51043.3-51092.6" wire $0\terminated$next[0:0]$3364 attribute \src "libresoc.v:50994.3-50995.37" wire $0\terminated[0:0] attribute \src "libresoc.v:51217.3-51229.6" wire $1\d_cr_req[0:0] attribute \src "libresoc.v:51024.3-51033.6" wire $1\d_gpr_req[0:0] attribute \src "libresoc.v:51230.3-51245.6" wire $1\d_xer_req[0:0] attribute \src "libresoc.v:51006.3-51023.6" wire $1\dmi_ack_o[0:0] attribute \src "libresoc.v:51246.3-51279.6" wire width 64 $1\dmi_dout[63:0] attribute \src "libresoc.v:51208.3-51216.6" wire $1\dmi_read_log_data$next[0:0]$3399 attribute \src "libresoc.v:50860.7-50860.31" wire $1\dmi_read_log_data[0:0] attribute \src "libresoc.v:51199.3-51207.6" wire $1\dmi_read_log_data_1$next[0:0]$3396 attribute \src "libresoc.v:50864.7-50864.33" wire $1\dmi_read_log_data_1[0:0] attribute \src "libresoc.v:51034.3-51042.6" wire $1\dmi_req_i_1$next[0:0]$3362 attribute \src "libresoc.v:50870.7-50870.25" wire $1\dmi_req_i_1[0:0] attribute \src "libresoc.v:51370.3-51403.6" wire $1\do_dmi_log_rd$next[0:0]$3426 attribute \src "libresoc.v:50876.7-50876.27" wire $1\do_dmi_log_rd[0:0] attribute \src "libresoc.v:51340.3-51369.6" wire $1\do_icreset$next[0:0]$3419 attribute \src "libresoc.v:50880.7-50880.24" wire $1\do_icreset[0:0] attribute \src "libresoc.v:51310.3-51339.6" wire $1\do_reset$next[0:0]$3412 attribute \src "libresoc.v:50884.7-50884.22" wire $1\do_reset[0:0] attribute \src "libresoc.v:51280.3-51309.6" wire $1\do_step$next[0:0]$3405 attribute \src "libresoc.v:50888.7-50888.21" wire $1\do_step[0:0] attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $1\gspr_index$next[6:0]$3384 attribute \src "libresoc.v:50892.13-50892.31" wire width 7 $1\gspr_index[6:0] attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $1\log_dmi_addr$next[31:0]$3390 attribute \src "libresoc.v:50898.14-50898.34" wire width 32 $1\log_dmi_addr[31:0] attribute \src "libresoc.v:51093.3-51136.6" wire $1\stopping$next[0:0]$3375 attribute \src "libresoc.v:50910.7-50910.22" wire $1\stopping[0:0] attribute \src "libresoc.v:51043.3-51092.6" wire $1\terminated$next[0:0]$3365 attribute \src "libresoc.v:50916.7-50916.24" wire $1\terminated[0:0] attribute \src "libresoc.v:51370.3-51403.6" wire $2\do_dmi_log_rd$next[0:0]$3427 attribute \src "libresoc.v:51340.3-51369.6" wire $2\do_icreset$next[0:0]$3420 attribute \src "libresoc.v:51310.3-51339.6" wire $2\do_reset$next[0:0]$3413 attribute \src "libresoc.v:51280.3-51309.6" wire $2\do_step$next[0:0]$3406 attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $2\gspr_index$next[6:0]$3385 attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $2\log_dmi_addr$next[31:0]$3391 attribute \src "libresoc.v:51093.3-51136.6" wire $2\stopping$next[0:0]$3376 attribute \src "libresoc.v:51043.3-51092.6" wire $2\terminated$next[0:0]$3366 attribute \src "libresoc.v:51370.3-51403.6" wire $3\do_dmi_log_rd$next[0:0]$3428 attribute \src "libresoc.v:51340.3-51369.6" wire $3\do_icreset$next[0:0]$3421 attribute \src "libresoc.v:51310.3-51339.6" wire $3\do_reset$next[0:0]$3414 attribute \src "libresoc.v:51280.3-51309.6" wire $3\do_step$next[0:0]$3407 attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $3\gspr_index$next[6:0]$3386 attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $3\log_dmi_addr$next[31:0]$3392 attribute \src "libresoc.v:51093.3-51136.6" wire $3\stopping$next[0:0]$3377 attribute \src "libresoc.v:51043.3-51092.6" wire $3\terminated$next[0:0]$3367 attribute \src "libresoc.v:51370.3-51403.6" wire $4\do_dmi_log_rd$next[0:0]$3429 attribute \src "libresoc.v:51340.3-51369.6" wire $4\do_icreset$next[0:0]$3422 attribute \src "libresoc.v:51310.3-51339.6" wire $4\do_reset$next[0:0]$3415 attribute \src "libresoc.v:51280.3-51309.6" wire $4\do_step$next[0:0]$3408 attribute \src "libresoc.v:51137.3-51164.6" wire width 7 $4\gspr_index$next[6:0]$3387 attribute \src "libresoc.v:51165.3-51198.6" wire width 32 $4\log_dmi_addr$next[31:0]$3393 attribute \src "libresoc.v:51093.3-51136.6" wire $4\stopping$next[0:0]$3378 attribute \src "libresoc.v:51043.3-51092.6" wire $4\terminated$next[0:0]$3368 attribute \src "libresoc.v:51340.3-51369.6" wire $5\do_icreset$next[0:0]$3423 attribute \src "libresoc.v:51310.3-51339.6" wire $5\do_reset$next[0:0]$3416 attribute \src "libresoc.v:51280.3-51309.6" wire $5\do_step$next[0:0]$3409 attribute \src "libresoc.v:51093.3-51136.6" wire $5\stopping$next[0:0]$3379 attribute \src "libresoc.v:51043.3-51092.6" wire $5\terminated$next[0:0]$3369 attribute \src "libresoc.v:51093.3-51136.6" wire $6\stopping$next[0:0]$3380 attribute \src "libresoc.v:51043.3-51092.6" wire $6\terminated$next[0:0]$3370 attribute \src "libresoc.v:51093.3-51136.6" wire $7\stopping$next[0:0]$3381 attribute \src "libresoc.v:51043.3-51092.6" wire $7\terminated$next[0:0]$3371 attribute \src "libresoc.v:51043.3-51092.6" wire $8\terminated$next[0:0]$3372 attribute \src "libresoc.v:50931.19-50931.110" wire width 3 $add$libresoc.v:50931$3294_Y attribute \src "libresoc.v:50925.19-50925.103" wire $and$libresoc.v:50925$3288_Y attribute \src "libresoc.v:50927.19-50927.113" wire $and$libresoc.v:50927$3290_Y attribute \src "libresoc.v:50932.18-50932.110" wire $and$libresoc.v:50932$3295_Y attribute \src "libresoc.v:50934.19-50934.103" wire $and$libresoc.v:50934$3297_Y attribute \src "libresoc.v:50936.19-50936.102" wire $and$libresoc.v:50936$3299_Y attribute \src "libresoc.v:50942.18-50942.101" wire $and$libresoc.v:50942$3305_Y attribute \src "libresoc.v:50944.18-50944.111" wire $and$libresoc.v:50944$3307_Y attribute \src "libresoc.v:50949.18-50949.101" wire $and$libresoc.v:50949$3312_Y attribute \src "libresoc.v:50952.18-50952.111" wire $and$libresoc.v:50952$3315_Y attribute \src "libresoc.v:50957.18-50957.101" wire $and$libresoc.v:50957$3320_Y attribute \src "libresoc.v:50959.18-50959.111" wire $and$libresoc.v:50959$3322_Y attribute \src "libresoc.v:50965.18-50965.101" wire $and$libresoc.v:50965$3328_Y attribute \src "libresoc.v:50967.18-50967.111" wire $and$libresoc.v:50967$3330_Y attribute \src "libresoc.v:50972.18-50972.101" wire $and$libresoc.v:50972$3335_Y attribute \src "libresoc.v:50973.17-50973.99" wire $and$libresoc.v:50973$3336_Y attribute \src "libresoc.v:50975.18-50975.111" wire $and$libresoc.v:50975$3338_Y attribute \src "libresoc.v:50980.18-50980.101" wire $and$libresoc.v:50980$3343_Y attribute \src "libresoc.v:50982.18-50982.111" wire $and$libresoc.v:50982$3345_Y attribute \src "libresoc.v:50922.18-50922.103" wire $eq$libresoc.v:50922$3285_Y attribute \src "libresoc.v:50923.19-50923.104" wire $eq$libresoc.v:50923$3286_Y attribute \src "libresoc.v:50928.19-50928.104" wire $eq$libresoc.v:50928$3291_Y attribute \src "libresoc.v:50929.19-50929.104" wire $eq$libresoc.v:50929$3292_Y attribute \src "libresoc.v:50930.19-50930.104" wire $eq$libresoc.v:50930$3293_Y attribute \src "libresoc.v:50933.19-50933.104" wire $eq$libresoc.v:50933$3296_Y attribute \src "libresoc.v:50937.18-50937.103" wire $eq$libresoc.v:50937$3300_Y attribute \src "libresoc.v:50938.18-50938.103" wire $eq$libresoc.v:50938$3301_Y attribute \src "libresoc.v:50939.18-50939.103" wire $eq$libresoc.v:50939$3302_Y attribute \src "libresoc.v:50945.18-50945.103" wire $eq$libresoc.v:50945$3308_Y attribute \src "libresoc.v:50946.18-50946.103" wire $eq$libresoc.v:50946$3309_Y attribute \src "libresoc.v:50947.18-50947.103" wire $eq$libresoc.v:50947$3310_Y attribute \src "libresoc.v:50953.18-50953.103" wire $eq$libresoc.v:50953$3316_Y attribute \src "libresoc.v:50954.18-50954.103" wire $eq$libresoc.v:50954$3317_Y attribute \src "libresoc.v:50955.18-50955.103" wire $eq$libresoc.v:50955$3318_Y attribute \src "libresoc.v:50960.18-50960.103" wire $eq$libresoc.v:50960$3323_Y attribute \src "libresoc.v:50961.18-50961.103" wire $eq$libresoc.v:50961$3324_Y attribute \src "libresoc.v:50963.18-50963.103" wire $eq$libresoc.v:50963$3326_Y attribute \src "libresoc.v:50968.18-50968.103" wire $eq$libresoc.v:50968$3331_Y attribute \src "libresoc.v:50969.18-50969.103" wire $eq$libresoc.v:50969$3332_Y attribute \src "libresoc.v:50970.18-50970.103" wire $eq$libresoc.v:50970$3333_Y attribute \src "libresoc.v:50976.18-50976.103" wire $eq$libresoc.v:50976$3339_Y attribute \src "libresoc.v:50977.18-50977.103" wire $eq$libresoc.v:50977$3340_Y attribute \src "libresoc.v:50978.18-50978.103" wire $eq$libresoc.v:50978$3341_Y attribute \src "libresoc.v:50983.18-50983.103" wire $eq$libresoc.v:50983$3346_Y attribute \src "libresoc.v:50921.17-50921.103" wire $not$libresoc.v:50921$3284_Y attribute \src "libresoc.v:50924.19-50924.99" wire $not$libresoc.v:50924$3287_Y attribute \src "libresoc.v:50926.19-50926.105" wire $not$libresoc.v:50926$3289_Y attribute \src "libresoc.v:50935.19-50935.95" wire $not$libresoc.v:50935$3298_Y attribute \src "libresoc.v:50941.18-50941.98" wire $not$libresoc.v:50941$3304_Y attribute \src "libresoc.v:50943.18-50943.104" wire $not$libresoc.v:50943$3306_Y attribute \src "libresoc.v:50948.18-50948.98" wire $not$libresoc.v:50948$3311_Y attribute \src "libresoc.v:50950.18-50950.104" wire $not$libresoc.v:50950$3313_Y attribute \src "libresoc.v:50956.18-50956.98" wire $not$libresoc.v:50956$3319_Y attribute \src "libresoc.v:50958.18-50958.104" wire $not$libresoc.v:50958$3321_Y attribute \src "libresoc.v:50962.17-50962.97" wire $not$libresoc.v:50962$3325_Y attribute \src "libresoc.v:50964.18-50964.98" wire $not$libresoc.v:50964$3327_Y attribute \src "libresoc.v:50966.18-50966.104" wire $not$libresoc.v:50966$3329_Y attribute \src "libresoc.v:50971.18-50971.98" wire $not$libresoc.v:50971$3334_Y attribute \src "libresoc.v:50974.18-50974.104" wire $not$libresoc.v:50974$3337_Y attribute \src "libresoc.v:50979.18-50979.98" wire $not$libresoc.v:50979$3342_Y attribute \src "libresoc.v:50981.18-50981.104" wire $not$libresoc.v:50981$3344_Y attribute \src "libresoc.v:50940.17-50940.126" wire width 64 $pos$libresoc.v:50940$3303_Y attribute \src "libresoc.v:50951.17-50951.245" wire width 64 $pos$libresoc.v:50951$3314_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" wire width 3 \$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" wire width 3 \$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" wire \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" wire \$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" wire \$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" wire \$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" wire \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 30 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 input 13 \core_dbg_core_dbg_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 input 16 \core_dbg_core_dbg_maxvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 input 14 \core_dbg_core_dbg_srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" wire width 2 input 12 \core_dbg_core_dbg_subvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 input 11 \core_dbg_core_dbg_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 input 15 \core_dbg_core_dbg_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 input 17 \core_dbg_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 10 \core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" wire output 7 \core_rst_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" wire output 18 \core_stop_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" wire input 19 \core_stopped_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire input 26 \d_cr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 input 25 \d_cr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire output 24 \d_cr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire input 23 \d_gpr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" wire width 7 output 21 \d_gpr_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 input 22 \d_gpr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire output 20 \d_gpr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire input 29 \d_xer_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 input 28 \d_xer_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire output 27 \d_xer_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" wire output 5 \dmi_ack_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" wire width 4 input 1 \dmi_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" wire width 64 input 4 \dmi_din attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" wire width 64 output 6 \dmi_dout attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" wire \dmi_read_log_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" wire \dmi_read_log_data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" wire \dmi_read_log_data_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" wire \dmi_read_log_data_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" wire input 2 \dmi_req_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" wire \dmi_req_i_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire input 3 \dmi_we_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" wire \do_dmi_log_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" wire \do_dmi_log_rd$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" wire \do_icreset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" wire \do_icreset$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" wire \do_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" wire \do_reset$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" wire \do_step attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" wire \do_step$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" wire width 7 \gspr_index attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o attribute \src "libresoc.v:50673.7-50673.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 8 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" wire \stopping attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" wire \stopping$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" wire input 9 \terminate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" wire \terminated attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" wire \terminated$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" cell $add $add$libresoc.v:50931$3294 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 connect \Y $add$libresoc.v:50931$3294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50925$3288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$103 connect \Y $and$libresoc.v:50925$3288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50927$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$107 connect \Y $and$libresoc.v:50927$3290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50932$3295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$9 connect \Y $and$libresoc.v:50932$3295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" cell $and $and$libresoc.v:50934$3297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$120 connect \Y $and$libresoc.v:50934$3297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" cell $and $and$libresoc.v:50936$3299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \stopping connect \B \$124 connect \Y $and$libresoc.v:50936$3299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50942$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$19 connect \Y $and$libresoc.v:50942$3305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50944$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$23 connect \Y $and$libresoc.v:50944$3307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50949$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$33 connect \Y $and$libresoc.v:50949$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50952$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$37 connect \Y $and$libresoc.v:50952$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50957$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$47 connect \Y $and$libresoc.v:50957$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50959$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$51 connect \Y $and$libresoc.v:50959$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50965$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$61 connect \Y $and$libresoc.v:50965$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50967$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$65 connect \Y $and$libresoc.v:50967$3330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50972$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$75 connect \Y $and$libresoc.v:50972$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50973$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$5 connect \Y $and$libresoc.v:50973$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50975$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$79 connect \Y $and$libresoc.v:50975$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $and $and$libresoc.v:50980$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$89 connect \Y $and$libresoc.v:50980$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $and $and$libresoc.v:50982$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$93 connect \Y $and$libresoc.v:50982$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50922$3285 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50922$3285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50923$3286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50923$3286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50928$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50928$3291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50929$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50929$3292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50930$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50930$3293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" cell $eq $eq$libresoc.v:50933$3296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 connect \Y $eq$libresoc.v:50933$3296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50937$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50937$3300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50938$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50938$3301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50939$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50939$3302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50945$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50945$3308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50946$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50946$3309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50947$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50947$3310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50953$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50953$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50954$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50954$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50955$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50955$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50960$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50960$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50961$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50961$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50963$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50963$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50968$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50968$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50969$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50969$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50970$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50970$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50976$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50976$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" cell $eq $eq$libresoc.v:50977$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 connect \Y $eq$libresoc.v:50977$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" cell $eq $eq$libresoc.v:50978$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 connect \Y $eq$libresoc.v:50978$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" cell $eq $eq$libresoc.v:50983$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 connect \Y $eq$libresoc.v:50983$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50921$3284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50921$3284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50924$3287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50924$3287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50926$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50926$3289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" cell $not $not$libresoc.v:50935$3298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step connect \Y $not$libresoc.v:50935$3298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50941$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50941$3304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50943$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50943$3306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50948$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50948$3311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50950$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50950$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50956$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50956$3319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50958$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50958$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50962$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50962$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50964$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50964$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50966$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50966$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50971$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50971$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50974$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50974$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" cell $not $not$libresoc.v:50979$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 connect \Y $not$libresoc.v:50979$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" cell $not $not$libresoc.v:50981$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data connect \Y $not$libresoc.v:50981$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" cell $pos $pos$libresoc.v:50940$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } connect \Y $pos$libresoc.v:50940$3303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" cell $pos $pos$libresoc.v:50951$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } connect \Y $pos$libresoc.v:50951$3314_Y end attribute \src "libresoc.v:50673.7-50673.20" process $proc$libresoc.v:50673$3430 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:50860.7-50860.31" process $proc$libresoc.v:50860$3431 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end attribute \src "libresoc.v:50864.7-50864.33" process $proc$libresoc.v:50864$3432 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end attribute \src "libresoc.v:50870.7-50870.25" process $proc$libresoc.v:50870$3433 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end attribute \src "libresoc.v:50876.7-50876.27" process $proc$libresoc.v:50876$3434 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end attribute \src "libresoc.v:50880.7-50880.24" process $proc$libresoc.v:50880$3435 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end attribute \src "libresoc.v:50884.7-50884.22" process $proc$libresoc.v:50884$3436 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end attribute \src "libresoc.v:50888.7-50888.21" process $proc$libresoc.v:50888$3437 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end attribute \src "libresoc.v:50892.13-50892.31" process $proc$libresoc.v:50892$3438 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end attribute \src "libresoc.v:50898.14-50898.34" process $proc$libresoc.v:50898$3439 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end attribute \src "libresoc.v:50910.7-50910.22" process $proc$libresoc.v:50910$3440 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end attribute \src "libresoc.v:50916.7-50916.24" process $proc$libresoc.v:50916$3441 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end attribute \src "libresoc.v:50984.3-50985.51" process $proc$libresoc.v:50984$3347 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end attribute \src "libresoc.v:50986.3-50987.55" process $proc$libresoc.v:50986$3348 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end attribute \src "libresoc.v:50988.3-50989.41" process $proc$libresoc.v:50988$3349 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end attribute \src "libresoc.v:50990.3-50991.37" process $proc$libresoc.v:50990$3350 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end attribute \src "libresoc.v:50992.3-50993.33" process $proc$libresoc.v:50992$3351 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end attribute \src "libresoc.v:50994.3-50995.37" process $proc$libresoc.v:50994$3352 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end attribute \src "libresoc.v:50996.3-50997.39" process $proc$libresoc.v:50996$3353 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end attribute \src "libresoc.v:50998.3-50999.43" process $proc$libresoc.v:50998$3354 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end attribute \src "libresoc.v:51000.3-51001.37" process $proc$libresoc.v:51000$3355 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end attribute \src "libresoc.v:51002.3-51003.33" process $proc$libresoc.v:51002$3356 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end attribute \src "libresoc.v:51004.3-51005.31" process $proc$libresoc.v:51004$3357 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end attribute \src "libresoc.v:51006.3-51023.6" process $proc$libresoc.v:51006$3358 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] attribute \src "libresoc.v:51007.5-51007.29" switch \initial attribute \src "libresoc.v:51007.9-51007.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dmi_ack_o[0:0] \d_gpr_ack attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dmi_ack_o[0:0] \d_cr_ack attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dmi_ack_o[0:0] \d_xer_ack attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\dmi_ack_o[0:0] \dmi_req_i end sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end attribute \src "libresoc.v:51024.3-51033.6" process $proc$libresoc.v:51024$3359 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] attribute \src "libresoc.v:51025.5-51025.29" switch \initial attribute \src "libresoc.v:51025.9-51025.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\d_gpr_req[0:0] \dmi_req_i case assign $1\d_gpr_req[0:0] 1'0 end sync always update \d_gpr_req $0\d_gpr_req[0:0] end attribute \src "libresoc.v:51034.3-51042.6" process $proc$libresoc.v:51034$3360 assign { } { } assign { } { } assign $0\dmi_req_i_1$next[0:0]$3361 $1\dmi_req_i_1$next[0:0]$3362 attribute \src "libresoc.v:51035.5-51035.29" switch \initial attribute \src "libresoc.v:51035.9-51035.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi_req_i_1$next[0:0]$3362 1'0 case assign $1\dmi_req_i_1$next[0:0]$3362 \dmi_req_i end sync always update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3361 end attribute \src "libresoc.v:51043.3-51092.6" process $proc$libresoc.v:51043$3363 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\terminated$next[0:0]$3364 $8\terminated$next[0:0]$3372 attribute \src "libresoc.v:51044.5-51044.29" switch \initial attribute \src "libresoc.v:51044.9-51044.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$67 \$63 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\terminated$next[0:0]$3365 $2\terminated$next[0:0]$3366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\terminated$next[0:0]$3366 $3\terminated$next[0:0]$3367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$73 \$71 \$69 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } assign { } { } assign $3\terminated$next[0:0]$3367 $6\terminated$next[0:0]$3370 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\terminated$next[0:0]$3368 1'0 case assign $4\terminated$next[0:0]$3368 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\terminated$next[0:0]$3369 1'0 case assign $5\terminated$next[0:0]$3369 $4\terminated$next[0:0]$3368 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\terminated$next[0:0]$3370 1'0 case assign $6\terminated$next[0:0]$3370 $5\terminated$next[0:0]$3369 end case assign $3\terminated$next[0:0]$3367 \terminated end case assign $2\terminated$next[0:0]$3366 \terminated end case assign $1\terminated$next[0:0]$3365 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\terminated$next[0:0]$3371 1'1 case assign $7\terminated$next[0:0]$3371 $1\terminated$next[0:0]$3365 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\terminated$next[0:0]$3372 1'0 case assign $8\terminated$next[0:0]$3372 $7\terminated$next[0:0]$3371 end sync always update \terminated$next $0\terminated$next[0:0]$3364 end attribute \src "libresoc.v:51093.3-51136.6" process $proc$libresoc.v:51093$3373 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\stopping$next[0:0]$3374 $7\stopping$next[0:0]$3381 attribute \src "libresoc.v:51094.5-51094.29" switch \initial attribute \src "libresoc.v:51094.9-51094.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$81 \$77 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\stopping$next[0:0]$3375 $2\stopping$next[0:0]$3376 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\stopping$next[0:0]$3376 $3\stopping$next[0:0]$3377 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$87 \$85 \$83 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } assign $3\stopping$next[0:0]$3377 $5\stopping$next[0:0]$3379 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" switch \dmi_din [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\stopping$next[0:0]$3378 1'1 case assign $4\stopping$next[0:0]$3378 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\stopping$next[0:0]$3379 1'0 case assign $5\stopping$next[0:0]$3379 $4\stopping$next[0:0]$3378 end case assign $3\stopping$next[0:0]$3377 \stopping end case assign $2\stopping$next[0:0]$3376 \stopping end case assign $1\stopping$next[0:0]$3375 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\stopping$next[0:0]$3380 1'1 case assign $6\stopping$next[0:0]$3380 $1\stopping$next[0:0]$3375 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\stopping$next[0:0]$3381 1'0 case assign $7\stopping$next[0:0]$3381 $6\stopping$next[0:0]$3380 end sync always update \stopping$next $0\stopping$next[0:0]$3374 end attribute \src "libresoc.v:51137.3-51164.6" process $proc$libresoc.v:51137$3382 assign { } { } assign { } { } assign { } { } assign $0\gspr_index$next[6:0]$3383 $4\gspr_index$next[6:0]$3387 attribute \src "libresoc.v:51138.5-51138.29" switch \initial attribute \src "libresoc.v:51138.9-51138.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$95 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\gspr_index$next[6:0]$3384 $2\gspr_index$next[6:0]$3385 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\gspr_index$next[6:0]$3385 $3\gspr_index$next[6:0]$3386 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$101 \$99 \$97 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign $3\gspr_index$next[6:0]$3386 \gspr_index attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $3\gspr_index$next[6:0]$3386 \dmi_din [6:0] case assign $3\gspr_index$next[6:0]$3386 \gspr_index end case assign $2\gspr_index$next[6:0]$3385 \gspr_index end case assign $1\gspr_index$next[6:0]$3384 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\gspr_index$next[6:0]$3387 7'0000000 case assign $4\gspr_index$next[6:0]$3387 $1\gspr_index$next[6:0]$3384 end sync always update \gspr_index$next $0\gspr_index$next[6:0]$3383 end attribute \src "libresoc.v:51165.3-51198.6" process $proc$libresoc.v:51165$3388 assign { } { } assign { } { } assign { } { } assign $0\log_dmi_addr$next[31:0]$3389 $4\log_dmi_addr$next[31:0]$3393 attribute \src "libresoc.v:51166.5-51166.29" switch \initial attribute \src "libresoc.v:51166.9-51166.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$109 \$105 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\log_dmi_addr$next[31:0]$3390 $2\log_dmi_addr$next[31:0]$3391 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\log_dmi_addr$next[31:0]$3391 $3\log_dmi_addr$next[31:0]$3392 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$115 \$113 \$111 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $3\log_dmi_addr$next[31:0]$3392 \dmi_din [31:0] case assign $3\log_dmi_addr$next[31:0]$3392 \log_dmi_addr end case assign $2\log_dmi_addr$next[31:0]$3391 \log_dmi_addr end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign $1\log_dmi_addr$next[31:0]$3390 [31:2] \log_dmi_addr [31:2] assign $1\log_dmi_addr$next[31:0]$3390 [1:0] \$117 [1:0] case assign $1\log_dmi_addr$next[31:0]$3390 \log_dmi_addr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\log_dmi_addr$next[31:0]$3393 0 case assign $4\log_dmi_addr$next[31:0]$3393 $1\log_dmi_addr$next[31:0]$3390 end sync always update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3389 end attribute \src "libresoc.v:51199.3-51207.6" process $proc$libresoc.v:51199$3394 assign { } { } assign { } { } assign $0\dmi_read_log_data_1$next[0:0]$3395 $1\dmi_read_log_data_1$next[0:0]$3396 attribute \src "libresoc.v:51200.5-51200.29" switch \initial attribute \src "libresoc.v:51200.9-51200.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi_read_log_data_1$next[0:0]$3396 1'0 case assign $1\dmi_read_log_data_1$next[0:0]$3396 \dmi_read_log_data end sync always update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3395 end attribute \src "libresoc.v:51208.3-51216.6" process $proc$libresoc.v:51208$3397 assign { } { } assign { } { } assign $0\dmi_read_log_data$next[0:0]$3398 $1\dmi_read_log_data$next[0:0]$3399 attribute \src "libresoc.v:51209.5-51209.29" switch \initial attribute \src "libresoc.v:51209.9-51209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi_read_log_data$next[0:0]$3399 1'0 case assign $1\dmi_read_log_data$next[0:0]$3399 \$122 end sync always update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3398 end attribute \src "libresoc.v:51217.3-51229.6" process $proc$libresoc.v:51217$3400 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] attribute \src "libresoc.v:51218.5-51218.29" switch \initial attribute \src "libresoc.v:51218.9-51218.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\d_cr_req[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\d_cr_req[0:0] \dmi_req_i case assign $1\d_cr_req[0:0] 1'0 end sync always update \d_cr_req $0\d_cr_req[0:0] end attribute \src "libresoc.v:51230.3-51245.6" process $proc$libresoc.v:51230$3401 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] attribute \src "libresoc.v:51231.5-51231.29" switch \initial attribute \src "libresoc.v:51231.9-51231.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\d_xer_req[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign $1\d_xer_req[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\d_xer_req[0:0] \dmi_req_i case assign $1\d_xer_req[0:0] 1'0 end sync always update \d_xer_req $0\d_xer_req[0:0] end attribute \src "libresoc.v:51246.3-51279.6" process $proc$libresoc.v:51246$3402 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] attribute \src "libresoc.v:51247.5-51247.29" switch \initial attribute \src "libresoc.v:51247.9-51247.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dmi_dout[63:0] \stat_reg attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dmi_dout[63:0] \core_dbg_pc attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dmi_dout[63:0] \core_dbg_msr attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\dmi_dout[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dmi_dout[63:0] \d_gpr_data attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dmi_dout[63:0] \log_dmi_data attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dmi_dout[63:0] \d_cr_data attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dmi_dout[63:0] \d_xer_data case assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dmi_dout $0\dmi_dout[63:0] end attribute \src "libresoc.v:51280.3-51309.6" process $proc$libresoc.v:51280$3403 assign { } { } assign { } { } assign { } { } assign $0\do_step$next[0:0]$3404 $5\do_step$next[0:0]$3409 attribute \src "libresoc.v:51281.5-51281.29" switch \initial attribute \src "libresoc.v:51281.9-51281.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$11 \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\do_step$next[0:0]$3405 $2\do_step$next[0:0]$3406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\do_step$next[0:0]$3406 $3\do_step$next[0:0]$3407 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$17 \$15 \$13 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $3\do_step$next[0:0]$3407 $4\do_step$next[0:0]$3408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\do_step$next[0:0]$3408 1'1 case assign $4\do_step$next[0:0]$3408 1'0 end case assign $3\do_step$next[0:0]$3407 1'0 end case assign $2\do_step$next[0:0]$3406 1'0 end case assign $1\do_step$next[0:0]$3405 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\do_step$next[0:0]$3409 1'0 case assign $5\do_step$next[0:0]$3409 $1\do_step$next[0:0]$3405 end sync always update \do_step$next $0\do_step$next[0:0]$3404 end attribute \src "libresoc.v:51310.3-51339.6" process $proc$libresoc.v:51310$3410 assign { } { } assign { } { } assign { } { } assign $0\do_reset$next[0:0]$3411 $5\do_reset$next[0:0]$3416 attribute \src "libresoc.v:51311.5-51311.29" switch \initial attribute \src "libresoc.v:51311.9-51311.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$25 \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\do_reset$next[0:0]$3412 $2\do_reset$next[0:0]$3413 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\do_reset$next[0:0]$3413 $3\do_reset$next[0:0]$3414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$31 \$29 \$27 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $3\do_reset$next[0:0]$3414 $4\do_reset$next[0:0]$3415 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\do_reset$next[0:0]$3415 1'1 case assign $4\do_reset$next[0:0]$3415 1'0 end case assign $3\do_reset$next[0:0]$3414 1'0 end case assign $2\do_reset$next[0:0]$3413 1'0 end case assign $1\do_reset$next[0:0]$3412 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\do_reset$next[0:0]$3416 1'0 case assign $5\do_reset$next[0:0]$3416 $1\do_reset$next[0:0]$3412 end sync always update \do_reset$next $0\do_reset$next[0:0]$3411 end attribute \src "libresoc.v:51340.3-51369.6" process $proc$libresoc.v:51340$3417 assign { } { } assign { } { } assign { } { } assign $0\do_icreset$next[0:0]$3418 $5\do_icreset$next[0:0]$3423 attribute \src "libresoc.v:51341.5-51341.29" switch \initial attribute \src "libresoc.v:51341.9-51341.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$39 \$35 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\do_icreset$next[0:0]$3419 $2\do_icreset$next[0:0]$3420 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\do_icreset$next[0:0]$3420 $3\do_icreset$next[0:0]$3421 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$45 \$43 \$41 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $3\do_icreset$next[0:0]$3421 $4\do_icreset$next[0:0]$3422 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" switch \dmi_din [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\do_icreset$next[0:0]$3422 1'1 case assign $4\do_icreset$next[0:0]$3422 1'0 end case assign $3\do_icreset$next[0:0]$3421 1'0 end case assign $2\do_icreset$next[0:0]$3420 1'0 end case assign $1\do_icreset$next[0:0]$3419 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\do_icreset$next[0:0]$3423 1'0 case assign $5\do_icreset$next[0:0]$3423 $1\do_icreset$next[0:0]$3419 end sync always update \do_icreset$next $0\do_icreset$next[0:0]$3418 end attribute \src "libresoc.v:51370.3-51403.6" process $proc$libresoc.v:51370$3424 assign { } { } assign { } { } assign { } { } assign $0\do_dmi_log_rd$next[0:0]$3425 $4\do_dmi_log_rd$next[0:0]$3429 attribute \src "libresoc.v:51371.5-51371.29" switch \initial attribute \src "libresoc.v:51371.9-51371.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" switch { \$53 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\do_dmi_log_rd$next[0:0]$3426 $2\do_dmi_log_rd$next[0:0]$3427 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\do_dmi_log_rd$next[0:0]$3427 $3\do_dmi_log_rd$next[0:0]$3428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" switch { \$59 \$57 \$55 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $3\do_dmi_log_rd$next[0:0]$3428 1'1 case assign $3\do_dmi_log_rd$next[0:0]$3428 1'0 end case assign $2\do_dmi_log_rd$next[0:0]$3427 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\do_dmi_log_rd$next[0:0]$3426 1'1 case assign $1\do_dmi_log_rd$next[0:0]$3426 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\do_dmi_log_rd$next[0:0]$3429 1'0 case assign $4\do_dmi_log_rd$next[0:0]$3429 $1\do_dmi_log_rd$next[0:0]$3426 end sync always update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3425 end connect \$9 $not$libresoc.v:50921$3284_Y connect \$99 $eq$libresoc.v:50922$3285_Y connect \$101 $eq$libresoc.v:50923$3286_Y connect \$103 $not$libresoc.v:50924$3287_Y connect \$105 $and$libresoc.v:50925$3288_Y connect \$107 $not$libresoc.v:50926$3289_Y connect \$109 $and$libresoc.v:50927$3290_Y connect \$111 $eq$libresoc.v:50928$3291_Y connect \$113 $eq$libresoc.v:50929$3292_Y connect \$115 $eq$libresoc.v:50930$3293_Y connect \$118 $add$libresoc.v:50931$3294_Y connect \$11 $and$libresoc.v:50932$3295_Y connect \$120 $eq$libresoc.v:50933$3296_Y connect \$122 $and$libresoc.v:50934$3297_Y connect \$124 $not$libresoc.v:50935$3298_Y connect \$126 $and$libresoc.v:50936$3299_Y connect \$13 $eq$libresoc.v:50937$3300_Y connect \$15 $eq$libresoc.v:50938$3301_Y connect \$17 $eq$libresoc.v:50939$3302_Y connect \$1 $pos$libresoc.v:50940$3303_Y connect \$19 $not$libresoc.v:50941$3304_Y connect \$21 $and$libresoc.v:50942$3305_Y connect \$23 $not$libresoc.v:50943$3306_Y connect \$25 $and$libresoc.v:50944$3307_Y connect \$27 $eq$libresoc.v:50945$3308_Y connect \$29 $eq$libresoc.v:50946$3309_Y connect \$31 $eq$libresoc.v:50947$3310_Y connect \$33 $not$libresoc.v:50948$3311_Y connect \$35 $and$libresoc.v:50949$3312_Y connect \$37 $not$libresoc.v:50950$3313_Y connect \$3 $pos$libresoc.v:50951$3314_Y connect \$39 $and$libresoc.v:50952$3315_Y connect \$41 $eq$libresoc.v:50953$3316_Y connect \$43 $eq$libresoc.v:50954$3317_Y connect \$45 $eq$libresoc.v:50955$3318_Y connect \$47 $not$libresoc.v:50956$3319_Y connect \$49 $and$libresoc.v:50957$3320_Y connect \$51 $not$libresoc.v:50958$3321_Y connect \$53 $and$libresoc.v:50959$3322_Y connect \$55 $eq$libresoc.v:50960$3323_Y connect \$57 $eq$libresoc.v:50961$3324_Y connect \$5 $not$libresoc.v:50962$3325_Y connect \$59 $eq$libresoc.v:50963$3326_Y connect \$61 $not$libresoc.v:50964$3327_Y connect \$63 $and$libresoc.v:50965$3328_Y connect \$65 $not$libresoc.v:50966$3329_Y connect \$67 $and$libresoc.v:50967$3330_Y connect \$69 $eq$libresoc.v:50968$3331_Y connect \$71 $eq$libresoc.v:50969$3332_Y connect \$73 $eq$libresoc.v:50970$3333_Y connect \$75 $not$libresoc.v:50971$3334_Y connect \$77 $and$libresoc.v:50972$3335_Y connect \$7 $and$libresoc.v:50973$3336_Y connect \$79 $not$libresoc.v:50974$3337_Y connect \$81 $and$libresoc.v:50975$3338_Y connect \$83 $eq$libresoc.v:50976$3339_Y connect \$85 $eq$libresoc.v:50977$3340_Y connect \$87 $eq$libresoc.v:50978$3341_Y connect \$89 $not$libresoc.v:50979$3342_Y connect \$91 $and$libresoc.v:50980$3343_Y connect \$93 $not$libresoc.v:50981$3344_Y connect \$95 $and$libresoc.v:50982$3345_Y connect \$97 $eq$libresoc.v:50983$3346_Y connect \$117 \$118 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 connect \terminated_o \terminated connect \icache_rst_o \do_icreset connect \core_rst_o \do_reset connect \core_stop_o \$126 connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end attribute \src "libresoc.v:51417.1-53467.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec attribute \src "libresoc.v:53028.3-53061.6" wire width 3 $0\ALU_cr_in[2:0] attribute \src "libresoc.v:53062.3-53095.6" wire width 3 $0\ALU_cr_out[2:0] attribute \src "libresoc.v:52688.3-52721.6" wire width 2 $0\ALU_cry_in[1:0] attribute \src "libresoc.v:52790.3-52823.6" wire $0\ALU_cry_out[0:0] attribute \src "libresoc.v:52892.3-52925.6" wire width 14 $0\ALU_function_unit[13:0] attribute \src "libresoc.v:52960.3-52993.6" wire width 3 $0\ALU_in1_sel[2:0] attribute \src "libresoc.v:52994.3-53027.6" wire width 4 $0\ALU_in2_sel[3:0] attribute \src "libresoc.v:52926.3-52959.6" wire width 7 $0\ALU_internal_op[6:0] attribute \src "libresoc.v:52722.3-52755.6" wire $0\ALU_inv_a[0:0] attribute \src "libresoc.v:52756.3-52789.6" wire $0\ALU_inv_out[0:0] attribute \src "libresoc.v:52824.3-52857.6" wire $0\ALU_is_32b[0:0] attribute \src "libresoc.v:53096.3-53129.6" wire width 4 $0\ALU_ldst_len[3:0] attribute \src "libresoc.v:52654.3-52687.6" wire width 2 $0\ALU_rc_sel[1:0] attribute \src "libresoc.v:52858.3-52891.6" wire $0\ALU_sgn[0:0] attribute \src "libresoc.v:51418.7-51418.20" wire $0\initial[0:0] attribute \src "libresoc.v:53028.3-53061.6" wire width 3 $1\ALU_cr_in[2:0] attribute \src "libresoc.v:53062.3-53095.6" wire width 3 $1\ALU_cr_out[2:0] attribute \src "libresoc.v:52688.3-52721.6" wire width 2 $1\ALU_cry_in[1:0] attribute \src "libresoc.v:52790.3-52823.6" wire $1\ALU_cry_out[0:0] attribute \src "libresoc.v:52892.3-52925.6" wire width 14 $1\ALU_function_unit[13:0] attribute \src "libresoc.v:52960.3-52993.6" wire width 3 $1\ALU_in1_sel[2:0] attribute \src "libresoc.v:52994.3-53027.6" wire width 4 $1\ALU_in2_sel[3:0] attribute \src "libresoc.v:52926.3-52959.6" wire width 7 $1\ALU_internal_op[6:0] attribute \src "libresoc.v:52722.3-52755.6" wire $1\ALU_inv_a[0:0] attribute \src "libresoc.v:52756.3-52789.6" wire $1\ALU_inv_out[0:0] attribute \src "libresoc.v:52824.3-52857.6" wire $1\ALU_is_32b[0:0] attribute \src "libresoc.v:53096.3-53129.6" wire width 4 $1\ALU_ldst_len[3:0] attribute \src "libresoc.v:52654.3-52687.6" wire width 2 $1\ALU_rc_sel[1:0] attribute \src "libresoc.v:52858.3-52891.6" wire $1\ALU_sgn[0:0] attribute \src "libresoc.v:52619.17-52619.211" wire width 32 $ternary$libresoc.v:52619$3442_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \ALU_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \ALU_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \ALU_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \ALU_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \ALU_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \ALU_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \ALU_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \ALU_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \ALU_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \ALU_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \ALU_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \ALU_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \ALU_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \ALU_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \ALU_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \ALU_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ALU_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \ALU_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \ALU_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \ALU_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec19_ALU_dec19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec19_ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec19_ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec19_ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec19_ALU_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec19_ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec19_ALU_dec19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec19_ALU_dec19_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_ALU_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \ALU_dec31_ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \ALU_dec31_ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \ALU_dec31_ALU_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ALU_dec31_ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \ALU_dec31_ALU_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \ALU_dec31_ALU_dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \ALU_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \ALU_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \ALU_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \ALU_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \ALU_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \ALU_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \ALU_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:51418.7-51418.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:52619$3442 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:52619$3442_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:52620.13-52636.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:52637.13-52653.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end attribute \src "libresoc.v:51418.7-51418.20" process $proc$libresoc.v:51418$3457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:52654.3-52687.6" process $proc$libresoc.v:52654$3443 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] attribute \src "libresoc.v:52655.5-52655.29" switch \initial attribute \src "libresoc.v:52655.9-52655.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_rc_sel[1:0] 2'00 case assign $1\ALU_rc_sel[1:0] 2'00 end sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end attribute \src "libresoc.v:52688.3-52721.6" process $proc$libresoc.v:52688$3444 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] attribute \src "libresoc.v:52689.5-52689.29" switch \initial attribute \src "libresoc.v:52689.9-52689.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_cry_in[1:0] 2'01 case assign $1\ALU_cry_in[1:0] 2'00 end sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end attribute \src "libresoc.v:52722.3-52755.6" process $proc$libresoc.v:52722$3445 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] attribute \src "libresoc.v:52723.5-52723.29" switch \initial attribute \src "libresoc.v:52723.9-52723.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_inv_a[0:0] 1'1 case assign $1\ALU_inv_a[0:0] 1'0 end sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end attribute \src "libresoc.v:52756.3-52789.6" process $proc$libresoc.v:52756$3446 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] attribute \src "libresoc.v:52757.5-52757.29" switch \initial attribute \src "libresoc.v:52757.9-52757.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_inv_out[0:0] 1'0 case assign $1\ALU_inv_out[0:0] 1'0 end sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end attribute \src "libresoc.v:52790.3-52823.6" process $proc$libresoc.v:52790$3447 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] attribute \src "libresoc.v:52791.5-52791.29" switch \initial attribute \src "libresoc.v:52791.9-52791.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_cry_out[0:0] 1'1 case assign $1\ALU_cry_out[0:0] 1'0 end sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end attribute \src "libresoc.v:52824.3-52857.6" process $proc$libresoc.v:52824$3448 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] attribute \src "libresoc.v:52825.5-52825.29" switch \initial attribute \src "libresoc.v:52825.9-52825.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_is_32b[0:0] 1'0 case assign $1\ALU_is_32b[0:0] 1'0 end sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end attribute \src "libresoc.v:52858.3-52891.6" process $proc$libresoc.v:52858$3449 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] attribute \src "libresoc.v:52859.5-52859.29" switch \initial attribute \src "libresoc.v:52859.9-52859.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_sgn[0:0] 1'0 case assign $1\ALU_sgn[0:0] 1'0 end sync always update \ALU_sgn $0\ALU_sgn[0:0] end attribute \src "libresoc.v:52892.3-52925.6" process $proc$libresoc.v:52892$3450 assign { } { } assign { } { } assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] attribute \src "libresoc.v:52893.5-52893.29" switch \initial attribute \src "libresoc.v:52893.9-52893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_function_unit[13:0] \ALU_dec19_ALU_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_function_unit[13:0] \ALU_dec31_ALU_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_function_unit[13:0] 14'00000000000010 case assign $1\ALU_function_unit[13:0] 14'00000000000000 end sync always update \ALU_function_unit $0\ALU_function_unit[13:0] end attribute \src "libresoc.v:52926.3-52959.6" process $proc$libresoc.v:52926$3451 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] attribute \src "libresoc.v:52927.5-52927.29" switch \initial attribute \src "libresoc.v:52927.9-52927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_internal_op[6:0] 7'0000010 case assign $1\ALU_internal_op[6:0] 7'0000000 end sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end attribute \src "libresoc.v:52960.3-52993.6" process $proc$libresoc.v:52960$3452 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] attribute \src "libresoc.v:52961.5-52961.29" switch \initial attribute \src "libresoc.v:52961.9-52961.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_in1_sel[2:0] 3'001 case assign $1\ALU_in1_sel[2:0] 3'000 end sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end attribute \src "libresoc.v:52994.3-53027.6" process $proc$libresoc.v:52994$3453 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] attribute \src "libresoc.v:52995.5-52995.29" switch \initial attribute \src "libresoc.v:52995.9-52995.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_in2_sel[3:0] 4'0101 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_in2_sel[3:0] 4'0011 case assign $1\ALU_in2_sel[3:0] 4'0000 end sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end attribute \src "libresoc.v:53028.3-53061.6" process $proc$libresoc.v:53028$3454 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] attribute \src "libresoc.v:53029.5-53029.29" switch \initial attribute \src "libresoc.v:53029.9-53029.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_cr_in[2:0] 3'000 case assign $1\ALU_cr_in[2:0] 3'000 end sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end attribute \src "libresoc.v:53062.3-53095.6" process $proc$libresoc.v:53062$3455 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] attribute \src "libresoc.v:53063.5-53063.29" switch \initial attribute \src "libresoc.v:53063.9-53063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_cr_out[2:0] 3'000 case assign $1\ALU_cr_out[2:0] 3'000 end sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end attribute \src "libresoc.v:53096.3-53129.6" process $proc$libresoc.v:53096$3456 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] attribute \src "libresoc.v:53097.5-53097.29" switch \initial attribute \src "libresoc.v:53097.9-53097.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ALU_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ALU_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ALU_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ALU_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ALU_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ALU_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ALU_ldst_len[3:0] 4'0000 case assign $1\ALU_ldst_len[3:0] 4'0000 end sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end connect \$1 $ternary$libresoc.v:52619$3442_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect 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"MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \CR_dec31_CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \CR_dec31_CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \CR_dec31_CR_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \CR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \CR_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \CR_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:53472.7-53472.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 10 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:54517$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:54517$3458_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:54518.12-54525.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:54526.12-54533.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end attribute \src "libresoc.v:53472.7-53472.20" process $proc$libresoc.v:53472$3464 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:54534.3-54546.6" process $proc$libresoc.v:54534$3459 assign { } { } assign { } { } assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] attribute \src "libresoc.v:54535.5-54535.29" switch \initial attribute \src "libresoc.v:54535.9-54535.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\CR_function_unit[13:0] \CR_dec19_CR_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\CR_function_unit[13:0] \CR_dec31_CR_dec31_function_unit case assign $1\CR_function_unit[13:0] 14'00000000000000 end sync always update \CR_function_unit $0\CR_function_unit[13:0] end attribute \src "libresoc.v:54547.3-54559.6" process $proc$libresoc.v:54547$3460 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] attribute \src "libresoc.v:54548.5-54548.29" switch \initial attribute \src "libresoc.v:54548.9-54548.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op case assign $1\CR_internal_op[6:0] 7'0000000 end sync always update \CR_internal_op $0\CR_internal_op[6:0] end attribute \src "libresoc.v:54560.3-54572.6" process $proc$libresoc.v:54560$3461 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] attribute \src "libresoc.v:54561.5-54561.29" switch \initial attribute \src "libresoc.v:54561.9-54561.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in case assign $1\CR_cr_in[2:0] 3'000 end sync always update \CR_cr_in $0\CR_cr_in[2:0] end attribute \src "libresoc.v:54573.3-54585.6" process $proc$libresoc.v:54573$3462 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] attribute \src "libresoc.v:54574.5-54574.29" switch \initial attribute \src "libresoc.v:54574.9-54574.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out case assign $1\CR_cr_out[2:0] 3'000 end sync always update \CR_cr_out $0\CR_cr_out[2:0] end attribute \src "libresoc.v:54586.3-54598.6" process $proc$libresoc.v:54586$3463 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] attribute \src "libresoc.v:54587.5-54587.29" switch \initial attribute \src "libresoc.v:54587.9-54587.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel case assign $1\CR_rc_sel[1:0] 2'00 end sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end connect \$1 $ternary$libresoc.v:54517$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \CR_SPR \opcode_in [20:11] connect \CR_MB \opcode_in [10:6] connect \CR_ME \opcode_in [5:1] connect \CR_SH \opcode_in [15:11] connect \CR_BC \opcode_in [10:6] connect \CR_TO \opcode_in [25:21] connect \CR_DS \opcode_in [15:2] connect \CR_D \opcode_in [15:0] connect \CR_BH \opcode_in [12:11] connect \CR_BI \opcode_in [20:16] connect \CR_BO \opcode_in [25:21] connect \CR_FXM \opcode_in [19:12] connect \CR_BT \opcode_in [25:21] connect \CR_BA \opcode_in [20:16] connect \CR_BB \opcode_in [15:11] connect \CR_CR \opcode_in [10:1] connect \CR_BF \opcode_in [25:23] connect \CR_BD \opcode_in [15:2] connect \CR_OE \opcode_in [10] connect \CR_Rc \opcode_in [0] connect \CR_AA \opcode_in [1] connect \CR_LK \opcode_in [0] connect \CR_LI \opcode_in [25:2] connect \CR_ME32 \opcode_in [5:1] connect \CR_MB32 \opcode_in [10:6] connect \CR_sh { \opcode_in [1] \opcode_in [15:11] } connect \CR_SH32 \opcode_in [15:11] connect \CR_L \opcode_in [21] connect \CR_UI \opcode_in [15:0] connect \CR_SI \opcode_in [15:0] connect \CR_RB \opcode_in [15:11] connect \CR_RA \opcode_in [20:16] connect \CR_RT \opcode_in [25:21] connect \CR_RS \opcode_in [25:21] connect \CR_PO \opcode_in [31:26] connect \opcode_in \$1 connect \CR_dec31_opcode_in \opcode_in connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:54940.1-56385.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" module \dec$141 attribute \src "libresoc.v:55969.3-55984.6" wire width 3 $0\BRANCH_cr_in[2:0] attribute \src "libresoc.v:55985.3-56000.6" wire width 3 $0\BRANCH_cr_out[2:0] attribute \src "libresoc.v:55921.3-55936.6" wire width 14 $0\BRANCH_function_unit[13:0] attribute \src "libresoc.v:55953.3-55968.6" wire width 4 $0\BRANCH_in2_sel[3:0] attribute \src "libresoc.v:55937.3-55952.6" wire width 7 $0\BRANCH_internal_op[6:0] attribute \src "libresoc.v:56017.3-56032.6" wire $0\BRANCH_is_32b[0:0] attribute \src "libresoc.v:56033.3-56048.6" wire $0\BRANCH_lk[0:0] attribute \src "libresoc.v:56001.3-56016.6" wire width 2 $0\BRANCH_rc_sel[1:0] attribute \src "libresoc.v:54941.7-54941.20" wire $0\initial[0:0] attribute \src "libresoc.v:55969.3-55984.6" wire width 3 $1\BRANCH_cr_in[2:0] attribute \src "libresoc.v:55985.3-56000.6" wire width 3 $1\BRANCH_cr_out[2:0] attribute \src "libresoc.v:55921.3-55936.6" wire width 14 $1\BRANCH_function_unit[13:0] attribute \src "libresoc.v:55953.3-55968.6" wire width 4 $1\BRANCH_in2_sel[3:0] attribute \src "libresoc.v:55937.3-55952.6" wire width 7 $1\BRANCH_internal_op[6:0] attribute \src "libresoc.v:56017.3-56032.6" wire $1\BRANCH_is_32b[0:0] attribute \src "libresoc.v:56033.3-56048.6" wire $1\BRANCH_lk[0:0] attribute \src "libresoc.v:56001.3-56016.6" wire width 2 $1\BRANCH_rc_sel[1:0] attribute \src "libresoc.v:55909.17-55909.211" wire width 32 $ternary$libresoc.v:55909$3465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \BRANCH_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 19 \BRANCH_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \BRANCH_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \BRANCH_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \BRANCH_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \BRANCH_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 20 \BRANCH_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \BRANCH_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \BRANCH_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 16 \BRANCH_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 11 \BRANCH_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 18 \BRANCH_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \BRANCH_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 17 \BRANCH_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 14 \BRANCH_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 12 \BRANCH_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \BRANCH_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \BRANCH_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 13 \BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \BRANCH_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \BRANCH_dec19_BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \BRANCH_dec19_BRANCH_dec19_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \BRANCH_dec19_BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \BRANCH_dec19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \BRANCH_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \BRANCH_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \BRANCH_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 15 \BRANCH_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:54941.7-54941.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:55909$3465 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:55909$3465_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:55910.16-55920.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out connect \BRANCH_dec19_function_unit \BRANCH_dec19_BRANCH_dec19_function_unit connect \BRANCH_dec19_in2_sel \BRANCH_dec19_BRANCH_dec19_in2_sel connect \BRANCH_dec19_internal_op \BRANCH_dec19_BRANCH_dec19_internal_op connect \BRANCH_dec19_is_32b \BRANCH_dec19_BRANCH_dec19_is_32b connect \BRANCH_dec19_lk \BRANCH_dec19_BRANCH_dec19_lk connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end attribute \src "libresoc.v:54941.7-54941.20" process $proc$libresoc.v:54941$3474 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:55921.3-55936.6" process $proc$libresoc.v:55921$3466 assign { } { } assign { } { } assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] attribute \src "libresoc.v:55922.5-55922.29" switch \initial attribute \src "libresoc.v:55922.9-55922.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_function_unit[13:0] \BRANCH_dec19_BRANCH_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_function_unit[13:0] 14'00000000100000 case assign $1\BRANCH_function_unit[13:0] 14'00000000000000 end sync always update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end attribute \src "libresoc.v:55937.3-55952.6" process $proc$libresoc.v:55937$3467 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] attribute \src "libresoc.v:55938.5-55938.29" switch \initial attribute \src "libresoc.v:55938.9-55938.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_internal_op[6:0] 7'0000110 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_internal_op[6:0] 7'0000111 case assign $1\BRANCH_internal_op[6:0] 7'0000000 end sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end attribute \src "libresoc.v:55953.3-55968.6" process $proc$libresoc.v:55953$3468 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] attribute \src "libresoc.v:55954.5-55954.29" switch \initial attribute \src "libresoc.v:55954.9-55954.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_in2_sel[3:0] 4'0110 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_in2_sel[3:0] 4'0111 case assign $1\BRANCH_in2_sel[3:0] 4'0000 end sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end attribute \src "libresoc.v:55969.3-55984.6" process $proc$libresoc.v:55969$3469 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] attribute \src "libresoc.v:55970.5-55970.29" switch \initial attribute \src "libresoc.v:55970.9-55970.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_cr_in[2:0] 3'010 case assign $1\BRANCH_cr_in[2:0] 3'000 end sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end attribute \src "libresoc.v:55985.3-56000.6" process $proc$libresoc.v:55985$3470 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] attribute \src "libresoc.v:55986.5-55986.29" switch \initial attribute \src "libresoc.v:55986.9-55986.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_cr_out[2:0] 3'000 case assign $1\BRANCH_cr_out[2:0] 3'000 end sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end attribute \src "libresoc.v:56001.3-56016.6" process $proc$libresoc.v:56001$3471 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] attribute \src "libresoc.v:56002.5-56002.29" switch \initial attribute \src "libresoc.v:56002.9-56002.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_rc_sel[1:0] 2'00 case assign $1\BRANCH_rc_sel[1:0] 2'00 end sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end attribute \src "libresoc.v:56017.3-56032.6" process $proc$libresoc.v:56017$3472 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] attribute \src "libresoc.v:56018.5-56018.29" switch \initial attribute \src "libresoc.v:56018.9-56018.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_is_32b[0:0] 1'0 case assign $1\BRANCH_is_32b[0:0] 1'0 end sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end attribute \src "libresoc.v:56033.3-56048.6" process $proc$libresoc.v:56033$3473 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] attribute \src "libresoc.v:56034.5-56034.29" switch \initial attribute \src "libresoc.v:56034.9-56034.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\BRANCH_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\BRANCH_lk[0:0] 1'1 case assign $1\BRANCH_lk[0:0] 1'0 end sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end connect \$1 $ternary$libresoc.v:55909$3465_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \BRANCH_SPR \opcode_in [20:11] connect \BRANCH_MB \opcode_in [10:6] connect \BRANCH_ME \opcode_in [5:1] connect \BRANCH_SH \opcode_in [15:11] connect \BRANCH_BC \opcode_in [10:6] connect \BRANCH_TO \opcode_in [25:21] connect \BRANCH_DS \opcode_in [15:2] connect \BRANCH_D \opcode_in [15:0] connect \BRANCH_BH \opcode_in [12:11] connect \BRANCH_BI \opcode_in [20:16] connect \BRANCH_BO \opcode_in [25:21] connect \BRANCH_FXM \opcode_in [19:12] connect \BRANCH_BT \opcode_in [25:21] connect \BRANCH_BA \opcode_in [20:16] connect \BRANCH_BB \opcode_in [15:11] connect \BRANCH_CR \opcode_in [10:1] connect \BRANCH_BF \opcode_in [25:23] connect \BRANCH_BD \opcode_in [15:2] connect \BRANCH_OE \opcode_in [10] connect \BRANCH_Rc \opcode_in [0] connect \BRANCH_AA \opcode_in [1] connect \BRANCH_LK \opcode_in [0] connect \BRANCH_LI \opcode_in [25:2] connect \BRANCH_ME32 \opcode_in [5:1] connect \BRANCH_MB32 \opcode_in [10:6] connect \BRANCH_sh { \opcode_in [1] \opcode_in [15:11] } connect \BRANCH_SH32 \opcode_in [15:11] connect \BRANCH_L \opcode_in [21] connect \BRANCH_UI \opcode_in [15:0] connect \BRANCH_SI \opcode_in [15:0] connect \BRANCH_RB \opcode_in [15:11] connect \BRANCH_RA \opcode_in [20:16] connect \BRANCH_RT \opcode_in [25:21] connect \BRANCH_RS \opcode_in [25:21] connect \BRANCH_PO \opcode_in [31:26] connect \opcode_in \$1 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:56389.1-58166.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" module \dec$145 attribute \src "libresoc.v:57718.3-57745.6" wire width 3 $0\LOGICAL_cr_in[2:0] attribute \src "libresoc.v:57746.3-57773.6" wire width 3 $0\LOGICAL_cr_out[2:0] attribute \src "libresoc.v:57438.3-57465.6" wire width 2 $0\LOGICAL_cry_in[1:0] attribute \src "libresoc.v:57522.3-57549.6" wire $0\LOGICAL_cry_out[0:0] attribute \src "libresoc.v:57606.3-57633.6" wire width 14 $0\LOGICAL_function_unit[13:0] attribute \src "libresoc.v:57662.3-57689.6" wire width 3 $0\LOGICAL_in1_sel[2:0] attribute \src "libresoc.v:57690.3-57717.6" wire width 4 $0\LOGICAL_in2_sel[3:0] attribute \src "libresoc.v:57634.3-57661.6" wire width 7 $0\LOGICAL_internal_op[6:0] attribute \src "libresoc.v:57466.3-57493.6" wire $0\LOGICAL_inv_a[0:0] attribute \src "libresoc.v:57494.3-57521.6" wire $0\LOGICAL_inv_out[0:0] attribute \src "libresoc.v:57550.3-57577.6" wire $0\LOGICAL_is_32b[0:0] attribute \src "libresoc.v:57774.3-57801.6" wire width 4 $0\LOGICAL_ldst_len[3:0] attribute \src "libresoc.v:57802.3-57829.6" wire width 2 $0\LOGICAL_rc_sel[1:0] attribute \src "libresoc.v:57578.3-57605.6" wire $0\LOGICAL_sgn[0:0] attribute \src "libresoc.v:56390.7-56390.20" wire $0\initial[0:0] attribute \src "libresoc.v:57718.3-57745.6" wire width 3 $1\LOGICAL_cr_in[2:0] attribute \src "libresoc.v:57746.3-57773.6" wire width 3 $1\LOGICAL_cr_out[2:0] attribute \src "libresoc.v:57438.3-57465.6" wire width 2 $1\LOGICAL_cry_in[1:0] attribute \src "libresoc.v:57522.3-57549.6" wire $1\LOGICAL_cry_out[0:0] attribute \src "libresoc.v:57606.3-57633.6" wire width 14 $1\LOGICAL_function_unit[13:0] attribute \src "libresoc.v:57662.3-57689.6" wire width 3 $1\LOGICAL_in1_sel[2:0] attribute \src "libresoc.v:57690.3-57717.6" wire width 4 $1\LOGICAL_in2_sel[3:0] attribute \src "libresoc.v:57634.3-57661.6" wire width 7 $1\LOGICAL_internal_op[6:0] attribute \src "libresoc.v:57466.3-57493.6" wire $1\LOGICAL_inv_a[0:0] attribute \src "libresoc.v:57494.3-57521.6" wire $1\LOGICAL_inv_out[0:0] attribute \src "libresoc.v:57550.3-57577.6" wire $1\LOGICAL_is_32b[0:0] attribute \src "libresoc.v:57774.3-57801.6" wire width 4 $1\LOGICAL_ldst_len[3:0] attribute \src "libresoc.v:57802.3-57829.6" wire width 2 $1\LOGICAL_rc_sel[1:0] attribute \src "libresoc.v:57578.3-57605.6" wire $1\LOGICAL_sgn[0:0] attribute \src "libresoc.v:57420.17-57420.211" wire width 32 $ternary$libresoc.v:57420$3475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \LOGICAL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \LOGICAL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \LOGICAL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \LOGICAL_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \LOGICAL_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \LOGICAL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \LOGICAL_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \LOGICAL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LOGICAL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \LOGICAL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \LOGICAL_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \LOGICAL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \LOGICAL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \LOGICAL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \LOGICAL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \LOGICAL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LOGICAL_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \LOGICAL_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LOGICAL_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LOGICAL_dec31_LOGICAL_dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LOGICAL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \LOGICAL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LOGICAL_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LOGICAL_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \LOGICAL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \LOGICAL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \LOGICAL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:56390.7-56390.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:57420$3475 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:57420$3475_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:57421.17-57437.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end attribute \src "libresoc.v:56390.7-56390.20" process $proc$libresoc.v:56390$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:57438.3-57465.6" process $proc$libresoc.v:57438$3476 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] attribute \src "libresoc.v:57439.5-57439.29" switch \initial attribute \src "libresoc.v:57439.9-57439.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_cry_in[1:0] 2'00 case assign $1\LOGICAL_cry_in[1:0] 2'00 end sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end attribute \src "libresoc.v:57466.3-57493.6" process $proc$libresoc.v:57466$3477 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] attribute \src "libresoc.v:57467.5-57467.29" switch \initial attribute \src "libresoc.v:57467.9-57467.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_inv_a[0:0] 1'0 case assign $1\LOGICAL_inv_a[0:0] 1'0 end sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end attribute \src "libresoc.v:57494.3-57521.6" process $proc$libresoc.v:57494$3478 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] attribute \src "libresoc.v:57495.5-57495.29" switch \initial attribute \src "libresoc.v:57495.9-57495.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_inv_out[0:0] 1'0 case assign $1\LOGICAL_inv_out[0:0] 1'0 end sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end attribute \src "libresoc.v:57522.3-57549.6" process $proc$libresoc.v:57522$3479 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] attribute \src "libresoc.v:57523.5-57523.29" switch \initial attribute \src "libresoc.v:57523.9-57523.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_cry_out[0:0] 1'0 case assign $1\LOGICAL_cry_out[0:0] 1'0 end sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end attribute \src "libresoc.v:57550.3-57577.6" process $proc$libresoc.v:57550$3480 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] attribute \src "libresoc.v:57551.5-57551.29" switch \initial attribute \src "libresoc.v:57551.9-57551.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_is_32b[0:0] 1'0 case assign $1\LOGICAL_is_32b[0:0] 1'0 end sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end attribute \src "libresoc.v:57578.3-57605.6" process $proc$libresoc.v:57578$3481 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] attribute \src "libresoc.v:57579.5-57579.29" switch \initial attribute \src "libresoc.v:57579.9-57579.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_sgn[0:0] 1'0 case assign $1\LOGICAL_sgn[0:0] 1'0 end sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end attribute \src "libresoc.v:57606.3-57633.6" process $proc$libresoc.v:57606$3482 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] attribute \src "libresoc.v:57607.5-57607.29" switch \initial attribute \src "libresoc.v:57607.9-57607.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_function_unit[13:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_function_unit[13:0] 14'00000000010000 case assign $1\LOGICAL_function_unit[13:0] 14'00000000000000 end sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end attribute \src "libresoc.v:57634.3-57661.6" process $proc$libresoc.v:57634$3483 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] attribute \src "libresoc.v:57635.5-57635.29" switch \initial attribute \src "libresoc.v:57635.9-57635.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_internal_op[6:0] 7'1000011 case assign $1\LOGICAL_internal_op[6:0] 7'0000000 end sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end attribute \src "libresoc.v:57662.3-57689.6" process $proc$libresoc.v:57662$3484 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] attribute \src "libresoc.v:57663.5-57663.29" switch \initial attribute \src "libresoc.v:57663.9-57663.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_in1_sel[2:0] 3'100 case assign $1\LOGICAL_in1_sel[2:0] 3'000 end sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end attribute \src "libresoc.v:57690.3-57717.6" process $proc$libresoc.v:57690$3485 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] attribute \src "libresoc.v:57691.5-57691.29" switch \initial attribute \src "libresoc.v:57691.9-57691.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_in2_sel[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_in2_sel[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_in2_sel[3:0] 4'0100 case assign $1\LOGICAL_in2_sel[3:0] 4'0000 end sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end attribute \src "libresoc.v:57718.3-57745.6" process $proc$libresoc.v:57718$3486 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] attribute \src "libresoc.v:57719.5-57719.29" switch \initial attribute \src "libresoc.v:57719.9-57719.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_cr_in[2:0] 3'000 case assign $1\LOGICAL_cr_in[2:0] 3'000 end sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end attribute \src "libresoc.v:57746.3-57773.6" process $proc$libresoc.v:57746$3487 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] attribute \src "libresoc.v:57747.5-57747.29" switch \initial attribute \src "libresoc.v:57747.9-57747.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_cr_out[2:0] 3'000 case assign $1\LOGICAL_cr_out[2:0] 3'000 end sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end attribute \src "libresoc.v:57774.3-57801.6" process $proc$libresoc.v:57774$3488 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] attribute \src "libresoc.v:57775.5-57775.29" switch \initial attribute \src "libresoc.v:57775.9-57775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_ldst_len[3:0] 4'0000 case assign $1\LOGICAL_ldst_len[3:0] 4'0000 end sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end attribute \src "libresoc.v:57802.3-57829.6" process $proc$libresoc.v:57802$3489 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] attribute \src "libresoc.v:57803.5-57803.29" switch \initial attribute \src "libresoc.v:57803.9-57803.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\LOGICAL_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\LOGICAL_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\LOGICAL_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\LOGICAL_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\LOGICAL_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\LOGICAL_rc_sel[1:0] 2'00 case assign $1\LOGICAL_rc_sel[1:0] 2'00 end sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end connect \$1 $ternary$libresoc.v:57420$3475_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \LOGICAL_SPR \opcode_in [20:11] connect \LOGICAL_MB \opcode_in [10:6] connect \LOGICAL_ME \opcode_in [5:1] connect \LOGICAL_SH \opcode_in [15:11] connect \LOGICAL_BC \opcode_in [10:6] connect \LOGICAL_TO \opcode_in [25:21] connect \LOGICAL_DS \opcode_in [15:2] connect \LOGICAL_D \opcode_in [15:0] connect \LOGICAL_BH \opcode_in [12:11] connect \LOGICAL_BI \opcode_in [20:16] connect \LOGICAL_BO \opcode_in [25:21] connect \LOGICAL_FXM \opcode_in [19:12] connect \LOGICAL_BT \opcode_in [25:21] connect \LOGICAL_BA \opcode_in [20:16] connect \LOGICAL_BB \opcode_in [15:11] connect \LOGICAL_CR \opcode_in [10:1] connect \LOGICAL_BF \opcode_in [25:23] connect \LOGICAL_BD \opcode_in [15:2] connect \LOGICAL_OE \opcode_in [10] connect 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \SPR_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \SPR_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \SPR_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \SPR_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \SPR_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \SPR_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \SPR_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SPR_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 10 \SPR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SPR_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 9 \SPR_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SPR_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SPR_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SPR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \SPR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SPR_dec31_SPR_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SPR_dec31_SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SPR_dec31_SPR_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SPR_dec31_SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SPR_dec31_SPR_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SPR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \SPR_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 8 \SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \SPR_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SPR_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:58171.7-58171.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 11 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:59099$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:59099$3491_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:59100.13-59108.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out connect \SPR_dec31_function_unit \SPR_dec31_SPR_dec31_function_unit connect \SPR_dec31_internal_op \SPR_dec31_SPR_dec31_internal_op connect \SPR_dec31_is_32b \SPR_dec31_SPR_dec31_is_32b connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end attribute \src "libresoc.v:58171.7-58171.20" process $proc$libresoc.v:58171$3498 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:59109.3-59118.6" process $proc$libresoc.v:59109$3492 assign { } { } assign { } { } assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] attribute \src "libresoc.v:59110.5-59110.29" switch \initial attribute \src "libresoc.v:59110.9-59110.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SPR_function_unit[13:0] \SPR_dec31_SPR_dec31_function_unit case assign $1\SPR_function_unit[13:0] 14'00000000000000 end sync always update \SPR_function_unit $0\SPR_function_unit[13:0] end attribute \src "libresoc.v:59119.3-59128.6" process $proc$libresoc.v:59119$3493 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] attribute \src "libresoc.v:59120.5-59120.29" switch \initial attribute \src "libresoc.v:59120.9-59120.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op case assign $1\SPR_internal_op[6:0] 7'0000000 end sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end attribute \src "libresoc.v:59129.3-59138.6" process $proc$libresoc.v:59129$3494 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] attribute \src "libresoc.v:59130.5-59130.29" switch \initial attribute \src "libresoc.v:59130.9-59130.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in case assign $1\SPR_cr_in[2:0] 3'000 end sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end attribute \src "libresoc.v:59139.3-59148.6" process $proc$libresoc.v:59139$3495 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] attribute \src "libresoc.v:59140.5-59140.29" switch \initial attribute \src "libresoc.v:59140.9-59140.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out case assign $1\SPR_cr_out[2:0] 3'000 end sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end attribute \src "libresoc.v:59149.3-59158.6" process $proc$libresoc.v:59149$3496 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] attribute \src "libresoc.v:59150.5-59150.29" switch \initial attribute \src "libresoc.v:59150.9-59150.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel case assign $1\SPR_rc_sel[1:0] 2'00 end sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end attribute \src "libresoc.v:59159.3-59168.6" process $proc$libresoc.v:59159$3497 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] attribute \src "libresoc.v:59160.5-59160.29" switch \initial attribute \src "libresoc.v:59160.9-59160.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b case assign $1\SPR_is_32b[0:0] 1'0 end sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end connect \$1 $ternary$libresoc.v:59099$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \SPR_SPR \opcode_in [20:11] connect \SPR_MB \opcode_in [10:6] connect \SPR_ME \opcode_in [5:1] connect \SPR_SH \opcode_in [15:11] connect \SPR_BC \opcode_in [10:6] connect \SPR_TO \opcode_in [25:21] connect \SPR_DS \opcode_in [15:2] connect \SPR_D \opcode_in [15:0] connect \SPR_BH \opcode_in [12:11] connect \SPR_BI \opcode_in [20:16] connect \SPR_BO \opcode_in [25:21] connect \SPR_FXM \opcode_in [19:12] connect \SPR_BT \opcode_in [25:21] connect \SPR_BA \opcode_in [20:16] connect \SPR_BB \opcode_in [15:11] connect \SPR_CR \opcode_in [10:1] connect \SPR_BF \opcode_in [25:23] connect \SPR_BD \opcode_in [15:2] connect \SPR_OE \opcode_in [10] connect \SPR_Rc \opcode_in [0] connect \SPR_AA \opcode_in [1] connect \SPR_LK \opcode_in [0] connect \SPR_LI \opcode_in [25:2] connect \SPR_ME32 \opcode_in [5:1] connect \SPR_MB32 \opcode_in [10:6] connect \SPR_sh { \opcode_in [1] \opcode_in [15:11] } connect \SPR_SH32 \opcode_in [15:11] connect \SPR_L \opcode_in [21] connect \SPR_UI \opcode_in [15:0] connect \SPR_SI \opcode_in [15:0] connect \SPR_RB \opcode_in [15:11] connect \SPR_RA \opcode_in [20:16] connect \SPR_RT \opcode_in [25:21] connect \SPR_RS \opcode_in [25:21] connect \SPR_PO \opcode_in [31:26] connect \opcode_in \$1 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:59509.1-61034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" module \dec$153 attribute \src "libresoc.v:60658.3-60667.6" wire width 3 $0\DIV_cr_in[2:0] attribute \src "libresoc.v:60668.3-60677.6" wire width 3 $0\DIV_cr_out[2:0] attribute \src "libresoc.v:60558.3-60567.6" wire width 2 $0\DIV_cry_in[1:0] attribute \src "libresoc.v:60588.3-60597.6" wire $0\DIV_cry_out[0:0] attribute \src "libresoc.v:60618.3-60627.6" wire width 14 $0\DIV_function_unit[13:0] attribute \src "libresoc.v:60638.3-60647.6" wire width 3 $0\DIV_in1_sel[2:0] attribute \src "libresoc.v:60648.3-60657.6" wire width 4 $0\DIV_in2_sel[3:0] attribute \src "libresoc.v:60628.3-60637.6" wire width 7 $0\DIV_internal_op[6:0] attribute \src "libresoc.v:60568.3-60577.6" wire $0\DIV_inv_a[0:0] attribute \src "libresoc.v:60578.3-60587.6" wire $0\DIV_inv_out[0:0] attribute \src "libresoc.v:60598.3-60607.6" wire $0\DIV_is_32b[0:0] attribute \src "libresoc.v:60678.3-60687.6" wire width 4 $0\DIV_ldst_len[3:0] attribute \src "libresoc.v:60688.3-60697.6" wire width 2 $0\DIV_rc_sel[1:0] attribute \src "libresoc.v:60608.3-60617.6" wire $0\DIV_sgn[0:0] attribute \src "libresoc.v:59510.7-59510.20" wire $0\initial[0:0] attribute \src "libresoc.v:60658.3-60667.6" wire width 3 $1\DIV_cr_in[2:0] attribute \src "libresoc.v:60668.3-60677.6" wire width 3 $1\DIV_cr_out[2:0] attribute \src "libresoc.v:60558.3-60567.6" wire width 2 $1\DIV_cry_in[1:0] attribute \src "libresoc.v:60588.3-60597.6" wire $1\DIV_cry_out[0:0] attribute \src "libresoc.v:60618.3-60627.6" wire width 14 $1\DIV_function_unit[13:0] attribute \src "libresoc.v:60638.3-60647.6" wire width 3 $1\DIV_in1_sel[2:0] attribute \src "libresoc.v:60648.3-60657.6" wire width 4 $1\DIV_in2_sel[3:0] attribute \src "libresoc.v:60628.3-60637.6" wire width 7 $1\DIV_internal_op[6:0] attribute \src "libresoc.v:60568.3-60577.6" wire $1\DIV_inv_a[0:0] attribute \src "libresoc.v:60578.3-60587.6" wire $1\DIV_inv_out[0:0] attribute \src "libresoc.v:60598.3-60607.6" wire $1\DIV_is_32b[0:0] attribute \src "libresoc.v:60678.3-60687.6" wire width 4 $1\DIV_ldst_len[3:0] attribute \src "libresoc.v:60688.3-60697.6" wire width 2 $1\DIV_rc_sel[1:0] attribute \src "libresoc.v:60608.3-60617.6" wire $1\DIV_sgn[0:0] attribute \src "libresoc.v:60540.17-60540.211" wire width 32 $ternary$libresoc.v:60540$3499_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \DIV_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \DIV_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \DIV_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \DIV_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \DIV_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 26 \DIV_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \DIV_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 22 \DIV_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \DIV_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \DIV_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \DIV_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \DIV_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \DIV_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \DIV_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \DIV_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \DIV_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \DIV_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 19 \DIV_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 13 \DIV_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \DIV_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_DIV_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \DIV_dec31_DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \DIV_dec31_DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \DIV_dec31_DIV_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \DIV_dec31_DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \DIV_dec31_DIV_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \DIV_dec31_DIV_dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \DIV_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \DIV_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \DIV_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \DIV_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 15 \DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \DIV_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 16 \DIV_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 21 \DIV_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:59510.7-59510.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:60540$3499 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:60540$3499_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:60541.13-60557.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end attribute \src "libresoc.v:59510.7-59510.20" process $proc$libresoc.v:59510$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:60558.3-60567.6" process $proc$libresoc.v:60558$3500 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] attribute \src "libresoc.v:60559.5-60559.29" switch \initial attribute \src "libresoc.v:60559.9-60559.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in case assign $1\DIV_cry_in[1:0] 2'00 end sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end attribute \src "libresoc.v:60568.3-60577.6" process $proc$libresoc.v:60568$3501 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] attribute \src "libresoc.v:60569.5-60569.29" switch \initial attribute \src "libresoc.v:60569.9-60569.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a case assign $1\DIV_inv_a[0:0] 1'0 end sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end attribute \src "libresoc.v:60578.3-60587.6" process $proc$libresoc.v:60578$3502 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] attribute \src "libresoc.v:60579.5-60579.29" switch \initial attribute \src "libresoc.v:60579.9-60579.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out case assign $1\DIV_inv_out[0:0] 1'0 end sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end attribute \src "libresoc.v:60588.3-60597.6" process $proc$libresoc.v:60588$3503 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] attribute \src "libresoc.v:60589.5-60589.29" switch \initial attribute \src "libresoc.v:60589.9-60589.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out case assign $1\DIV_cry_out[0:0] 1'0 end sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end attribute \src "libresoc.v:60598.3-60607.6" process $proc$libresoc.v:60598$3504 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] attribute \src "libresoc.v:60599.5-60599.29" switch \initial attribute \src "libresoc.v:60599.9-60599.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b case assign $1\DIV_is_32b[0:0] 1'0 end sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end attribute \src "libresoc.v:60608.3-60617.6" process $proc$libresoc.v:60608$3505 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] attribute \src "libresoc.v:60609.5-60609.29" switch \initial attribute \src "libresoc.v:60609.9-60609.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn case assign $1\DIV_sgn[0:0] 1'0 end sync always update \DIV_sgn $0\DIV_sgn[0:0] end attribute \src "libresoc.v:60618.3-60627.6" process $proc$libresoc.v:60618$3506 assign { } { } assign { } { } assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] attribute \src "libresoc.v:60619.5-60619.29" switch \initial attribute \src "libresoc.v:60619.9-60619.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_function_unit[13:0] \DIV_dec31_DIV_dec31_function_unit case assign $1\DIV_function_unit[13:0] 14'00000000000000 end sync always update \DIV_function_unit $0\DIV_function_unit[13:0] end attribute \src "libresoc.v:60628.3-60637.6" process $proc$libresoc.v:60628$3507 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] attribute \src "libresoc.v:60629.5-60629.29" switch \initial attribute \src "libresoc.v:60629.9-60629.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op case assign $1\DIV_internal_op[6:0] 7'0000000 end sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end attribute \src "libresoc.v:60638.3-60647.6" process $proc$libresoc.v:60638$3508 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] attribute \src "libresoc.v:60639.5-60639.29" switch \initial attribute \src "libresoc.v:60639.9-60639.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel case assign $1\DIV_in1_sel[2:0] 3'000 end sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end attribute \src "libresoc.v:60648.3-60657.6" process $proc$libresoc.v:60648$3509 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] attribute \src "libresoc.v:60649.5-60649.29" switch \initial attribute \src "libresoc.v:60649.9-60649.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel case assign $1\DIV_in2_sel[3:0] 4'0000 end sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end attribute \src "libresoc.v:60658.3-60667.6" process $proc$libresoc.v:60658$3510 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] attribute \src "libresoc.v:60659.5-60659.29" switch \initial attribute \src "libresoc.v:60659.9-60659.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in case assign $1\DIV_cr_in[2:0] 3'000 end sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end attribute \src "libresoc.v:60668.3-60677.6" process $proc$libresoc.v:60668$3511 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] attribute \src "libresoc.v:60669.5-60669.29" switch \initial attribute \src "libresoc.v:60669.9-60669.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out case assign $1\DIV_cr_out[2:0] 3'000 end sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end attribute \src "libresoc.v:60678.3-60687.6" process $proc$libresoc.v:60678$3512 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] attribute \src "libresoc.v:60679.5-60679.29" switch \initial attribute \src "libresoc.v:60679.9-60679.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len case assign $1\DIV_ldst_len[3:0] 4'0000 end sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end attribute \src "libresoc.v:60688.3-60697.6" process $proc$libresoc.v:60688$3513 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] attribute \src "libresoc.v:60689.5-60689.29" switch \initial attribute \src "libresoc.v:60689.9-60689.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel case assign $1\DIV_rc_sel[1:0] 2'00 end sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end connect \$1 $ternary$libresoc.v:60540$3499_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \DIV_SPR \opcode_in [20:11] connect \DIV_MB \opcode_in [10:6] connect \DIV_ME \opcode_in [5:1] connect \DIV_SH \opcode_in [15:11] connect \DIV_BC \opcode_in [10:6] connect \DIV_TO \opcode_in [25:21] connect \DIV_DS \opcode_in [15:2] connect \DIV_D \opcode_in [15:0] connect \DIV_BH \opcode_in [12:11] connect \DIV_BI \opcode_in [20:16] connect \DIV_BO \opcode_in [25:21] connect \DIV_FXM \opcode_in [19:12] connect \DIV_BT \opcode_in [25:21] connect \DIV_BA \opcode_in [20:16] connect \DIV_BB \opcode_in [15:11] connect \DIV_CR \opcode_in [10:1] connect \DIV_BF \opcode_in [25:23] connect \DIV_BD \opcode_in [15:2] connect \DIV_OE \opcode_in [10] connect \DIV_Rc \opcode_in [0] connect \DIV_AA \opcode_in [1] connect \DIV_LK \opcode_in [0] connect \DIV_LI \opcode_in [25:2] connect \DIV_ME32 \opcode_in [5:1] connect \DIV_MB32 \opcode_in [10:6] connect \DIV_sh { \opcode_in [1] \opcode_in [15:11] } connect \DIV_SH32 \opcode_in [15:11] connect \DIV_L \opcode_in [21] connect \DIV_UI \opcode_in [15:0] connect \DIV_SI \opcode_in [15:0] connect \DIV_RB \opcode_in [15:11] connect \DIV_RA \opcode_in [20:16] connect \DIV_RT \opcode_in [25:21] connect \DIV_RS \opcode_in [25:21] connect \DIV_PO \opcode_in [31:26] connect \opcode_in \$1 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:61038.1-62459.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" module \dec$158 attribute \src "libresoc.v:62058.3-62070.6" wire width 3 $0\MUL_cr_in[2:0] attribute \src "libresoc.v:62071.3-62083.6" wire width 3 $0\MUL_cr_out[2:0] attribute \src "libresoc.v:62019.3-62031.6" wire width 14 $0\MUL_function_unit[13:0] attribute \src "libresoc.v:62045.3-62057.6" wire width 4 $0\MUL_in2_sel[3:0] attribute \src "libresoc.v:62032.3-62044.6" wire width 7 $0\MUL_internal_op[6:0] attribute \src "libresoc.v:62097.3-62109.6" wire $0\MUL_is_32b[0:0] attribute \src "libresoc.v:62084.3-62096.6" wire width 2 $0\MUL_rc_sel[1:0] attribute \src "libresoc.v:62110.3-62122.6" wire $0\MUL_sgn[0:0] attribute \src "libresoc.v:61039.7-61039.20" wire $0\initial[0:0] attribute \src "libresoc.v:62058.3-62070.6" wire width 3 $1\MUL_cr_in[2:0] attribute \src "libresoc.v:62071.3-62083.6" wire width 3 $1\MUL_cr_out[2:0] attribute \src "libresoc.v:62019.3-62031.6" wire width 14 $1\MUL_function_unit[13:0] attribute \src "libresoc.v:62045.3-62057.6" wire width 4 $1\MUL_in2_sel[3:0] attribute \src "libresoc.v:62032.3-62044.6" wire width 7 $1\MUL_internal_op[6:0] attribute \src "libresoc.v:62097.3-62109.6" wire $1\MUL_is_32b[0:0] attribute \src "libresoc.v:62084.3-62096.6" wire width 2 $1\MUL_rc_sel[1:0] attribute \src "libresoc.v:62110.3-62122.6" wire $1\MUL_sgn[0:0] attribute \src "libresoc.v:62007.17-62007.211" wire width 32 $ternary$libresoc.v:62007$3515_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 18 \MUL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \MUL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \MUL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \MUL_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \MUL_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 19 \MUL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \MUL_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 15 \MUL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \MUL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 17 \MUL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \MUL_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 16 \MUL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 13 \MUL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 11 \MUL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \MUL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MUL_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 12 \MUL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \MUL_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \MUL_dec31_MUL_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \MUL_dec31_MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \MUL_dec31_MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \MUL_dec31_MUL_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \MUL_dec31_MUL_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \MUL_dec31_MUL_dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \MUL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \MUL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \MUL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \MUL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 14 \MUL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:61039.7-61039.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 20 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:62007$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:62007$3515_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:62008.13-62018.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end attribute \src "libresoc.v:61039.7-61039.20" process $proc$libresoc.v:61039$3524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:62019.3-62031.6" process $proc$libresoc.v:62019$3516 assign { } { } assign { } { } assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] attribute \src "libresoc.v:62020.5-62020.29" switch \initial attribute \src "libresoc.v:62020.9-62020.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_function_unit[13:0] \MUL_dec31_MUL_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_function_unit[13:0] 14'00000100000000 case assign $1\MUL_function_unit[13:0] 14'00000000000000 end sync always update \MUL_function_unit $0\MUL_function_unit[13:0] end attribute \src "libresoc.v:62032.3-62044.6" process $proc$libresoc.v:62032$3517 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] attribute \src "libresoc.v:62033.5-62033.29" switch \initial attribute \src "libresoc.v:62033.9-62033.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_internal_op[6:0] 7'0110010 case assign $1\MUL_internal_op[6:0] 7'0000000 end sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end attribute \src "libresoc.v:62045.3-62057.6" process $proc$libresoc.v:62045$3518 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] attribute \src "libresoc.v:62046.5-62046.29" switch \initial attribute \src "libresoc.v:62046.9-62046.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_in2_sel[3:0] 4'0011 case assign $1\MUL_in2_sel[3:0] 4'0000 end sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end attribute \src "libresoc.v:62058.3-62070.6" process $proc$libresoc.v:62058$3519 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] attribute \src "libresoc.v:62059.5-62059.29" switch \initial attribute \src "libresoc.v:62059.9-62059.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_cr_in[2:0] 3'000 case assign $1\MUL_cr_in[2:0] 3'000 end sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end attribute \src "libresoc.v:62071.3-62083.6" process $proc$libresoc.v:62071$3520 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] attribute \src "libresoc.v:62072.5-62072.29" switch \initial attribute \src "libresoc.v:62072.9-62072.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_cr_out[2:0] 3'001 case assign $1\MUL_cr_out[2:0] 3'000 end sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end attribute \src "libresoc.v:62084.3-62096.6" process $proc$libresoc.v:62084$3521 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] attribute \src "libresoc.v:62085.5-62085.29" switch \initial attribute \src "libresoc.v:62085.9-62085.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_rc_sel[1:0] 2'00 case assign $1\MUL_rc_sel[1:0] 2'00 end sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end attribute \src "libresoc.v:62097.3-62109.6" process $proc$libresoc.v:62097$3522 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] attribute \src "libresoc.v:62098.5-62098.29" switch \initial attribute \src "libresoc.v:62098.9-62098.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_is_32b[0:0] 1'0 case assign $1\MUL_is_32b[0:0] 1'0 end sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end attribute \src "libresoc.v:62110.3-62122.6" process $proc$libresoc.v:62110$3523 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] attribute \src "libresoc.v:62111.5-62111.29" switch \initial attribute \src "libresoc.v:62111.9-62111.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\MUL_sgn[0:0] 1'1 case assign $1\MUL_sgn[0:0] 1'0 end sync always update \MUL_sgn $0\MUL_sgn[0:0] end connect \$1 $ternary$libresoc.v:62007$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \MUL_SPR \opcode_in [20:11] connect \MUL_MB \opcode_in [10:6] connect \MUL_ME \opcode_in [5:1] connect \MUL_SH \opcode_in [15:11] connect \MUL_BC \opcode_in [10:6] connect \MUL_TO \opcode_in [25:21] connect \MUL_DS \opcode_in [15:2] connect \MUL_D \opcode_in [15:0] connect \MUL_BH \opcode_in [12:11] connect \MUL_BI \opcode_in [20:16] connect \MUL_BO \opcode_in [25:21] connect \MUL_FXM \opcode_in [19:12] connect \MUL_BT \opcode_in [25:21] connect \MUL_BA \opcode_in [20:16] connect \MUL_BB \opcode_in [15:11] connect \MUL_CR \opcode_in [10:1] connect \MUL_BF \opcode_in [25:23] connect \MUL_BD \opcode_in [15:2] connect \MUL_OE \opcode_in [10] connect \MUL_Rc \opcode_in [0] connect \MUL_AA \opcode_in [1] connect \MUL_LK \opcode_in [0] connect \MUL_LI \opcode_in [25:2] connect \MUL_ME32 \opcode_in [5:1] connect \MUL_MB32 \opcode_in [10:6] connect \MUL_sh { \opcode_in [1] \opcode_in [15:11] } connect \MUL_SH32 \opcode_in [15:11] connect \MUL_L \opcode_in [21] connect \MUL_UI \opcode_in [15:0] connect \MUL_SI \opcode_in [15:0] connect \MUL_RB \opcode_in [15:11] connect \MUL_RA \opcode_in [20:16] connect \MUL_RT \opcode_in [25:21] connect \MUL_RS \opcode_in [25:21] connect \MUL_PO \opcode_in [31:26] connect \opcode_in \$1 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:62463.1-64217.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" module \dec$162 attribute \src "libresoc.v:63792.3-63813.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] attribute \src "libresoc.v:63814.3-63835.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] attribute \src "libresoc.v:63858.3-63879.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] attribute \src "libresoc.v:63660.3-63681.6" wire $0\SHIFT_ROT_cry_out[0:0] attribute \src "libresoc.v:63726.3-63747.6" wire width 14 $0\SHIFT_ROT_function_unit[13:0] attribute \src "libresoc.v:63770.3-63791.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] attribute \src "libresoc.v:63748.3-63769.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] attribute \src "libresoc.v:63638.3-63659.6" wire $0\SHIFT_ROT_inv_a[0:0] attribute \src "libresoc.v:63682.3-63703.6" wire $0\SHIFT_ROT_is_32b[0:0] attribute \src "libresoc.v:63836.3-63857.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] attribute \src "libresoc.v:63704.3-63725.6" wire $0\SHIFT_ROT_sgn[0:0] attribute \src "libresoc.v:62464.7-62464.20" wire $0\initial[0:0] attribute \src "libresoc.v:63792.3-63813.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] attribute \src "libresoc.v:63814.3-63835.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] attribute \src "libresoc.v:63858.3-63879.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] attribute \src "libresoc.v:63660.3-63681.6" wire $1\SHIFT_ROT_cry_out[0:0] attribute \src "libresoc.v:63726.3-63747.6" wire width 14 $1\SHIFT_ROT_function_unit[13:0] attribute \src "libresoc.v:63770.3-63791.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] attribute \src "libresoc.v:63748.3-63769.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] attribute \src "libresoc.v:63638.3-63659.6" wire $1\SHIFT_ROT_inv_a[0:0] attribute \src "libresoc.v:63682.3-63703.6" wire $1\SHIFT_ROT_is_32b[0:0] attribute \src "libresoc.v:63836.3-63857.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] attribute \src "libresoc.v:63704.3-63725.6" wire $1\SHIFT_ROT_sgn[0:0] attribute \src "libresoc.v:63609.17-63609.211" wire width 32 $ternary$libresoc.v:63609$3525_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 22 \SHIFT_ROT_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \SHIFT_ROT_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \SHIFT_ROT_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \SHIFT_ROT_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SHIFT_ROT_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 23 \SHIFT_ROT_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \SHIFT_ROT_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 19 \SHIFT_ROT_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \SHIFT_ROT_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 21 \SHIFT_ROT_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \SHIFT_ROT_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 20 \SHIFT_ROT_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 17 \SHIFT_ROT_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 15 \SHIFT_ROT_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SHIFT_ROT_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SHIFT_ROT_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 16 \SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 8 \SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 11 \SHIFT_ROT_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \SHIFT_ROT_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec30_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \SHIFT_ROT_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 7 \SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \SHIFT_ROT_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \SHIFT_ROT_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \SHIFT_ROT_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \SHIFT_ROT_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 18 \SHIFT_ROT_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "libresoc.v:62464.7-62464.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 24 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:63609$3525 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:63609$3525_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:63610.19-63623.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op connect \SHIFT_ROT_dec30_inv_a \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:63624.19-63637.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op connect \SHIFT_ROT_dec31_inv_a \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end attribute \src "libresoc.v:62464.7-62464.20" process $proc$libresoc.v:62464$3537 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:63638.3-63659.6" process $proc$libresoc.v:63638$3526 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] attribute \src "libresoc.v:63639.5-63639.29" switch \initial attribute \src "libresoc.v:63639.9-63639.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_inv_a[0:0] 1'0 case assign $1\SHIFT_ROT_inv_a[0:0] 1'0 end sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end attribute \src "libresoc.v:63660.3-63681.6" process $proc$libresoc.v:63660$3527 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] attribute \src "libresoc.v:63661.5-63661.29" switch \initial attribute \src "libresoc.v:63661.9-63661.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_cry_out[0:0] 1'0 case assign $1\SHIFT_ROT_cry_out[0:0] 1'0 end sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end attribute \src "libresoc.v:63682.3-63703.6" process $proc$libresoc.v:63682$3528 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] attribute \src "libresoc.v:63683.5-63683.29" switch \initial attribute \src "libresoc.v:63683.9-63683.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_is_32b[0:0] 1'1 case assign $1\SHIFT_ROT_is_32b[0:0] 1'0 end sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end attribute \src "libresoc.v:63704.3-63725.6" process $proc$libresoc.v:63704$3529 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] attribute \src "libresoc.v:63705.5-63705.29" switch \initial attribute \src "libresoc.v:63705.9-63705.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_sgn[0:0] 1'0 case assign $1\SHIFT_ROT_sgn[0:0] 1'0 end sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end attribute \src "libresoc.v:63726.3-63747.6" process $proc$libresoc.v:63726$3530 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] attribute \src "libresoc.v:63727.5-63727.29" switch \initial attribute \src "libresoc.v:63727.9-63727.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_function_unit[13:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000001000 case assign $1\SHIFT_ROT_function_unit[13:0] 14'00000000000000 end sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end attribute \src "libresoc.v:63748.3-63769.6" process $proc$libresoc.v:63748$3531 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] attribute \src "libresoc.v:63749.5-63749.29" switch \initial attribute \src "libresoc.v:63749.9-63749.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 case assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 end sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end attribute \src "libresoc.v:63770.3-63791.6" process $proc$libresoc.v:63770$3532 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] attribute \src "libresoc.v:63771.5-63771.29" switch \initial attribute \src "libresoc.v:63771.9-63771.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 case assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 end sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end attribute \src "libresoc.v:63792.3-63813.6" process $proc$libresoc.v:63792$3533 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] attribute \src "libresoc.v:63793.5-63793.29" switch \initial attribute \src "libresoc.v:63793.9-63793.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_cr_in[2:0] 3'000 case assign $1\SHIFT_ROT_cr_in[2:0] 3'000 end sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end attribute \src "libresoc.v:63814.3-63835.6" process $proc$libresoc.v:63814$3534 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] attribute \src "libresoc.v:63815.5-63815.29" switch \initial attribute \src "libresoc.v:63815.9-63815.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_cr_out[2:0] 3'001 case assign $1\SHIFT_ROT_cr_out[2:0] 3'000 end sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end attribute \src "libresoc.v:63836.3-63857.6" process $proc$libresoc.v:63836$3535 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] attribute \src "libresoc.v:63837.5-63837.29" switch \initial attribute \src "libresoc.v:63837.9-63837.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 case assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 end sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end attribute \src "libresoc.v:63858.3-63879.6" process $proc$libresoc.v:63858$3536 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] attribute \src "libresoc.v:63859.5-63859.29" switch \initial attribute \src "libresoc.v:63859.9-63859.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SHIFT_ROT_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SHIFT_ROT_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SHIFT_ROT_cry_in[1:0] 2'00 case assign $1\SHIFT_ROT_cry_in[1:0] 2'00 end sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end connect \$1 $ternary$libresoc.v:63609$3525_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \SHIFT_ROT_SPR \opcode_in [20:11] connect \SHIFT_ROT_MB \opcode_in [10:6] connect \SHIFT_ROT_ME \opcode_in [5:1] connect \SHIFT_ROT_SH \opcode_in [15:11] connect \SHIFT_ROT_BC \opcode_in [10:6] connect \SHIFT_ROT_TO \opcode_in [25:21] connect \SHIFT_ROT_DS \opcode_in [15:2] connect \SHIFT_ROT_D \opcode_in [15:0] connect \SHIFT_ROT_BH \opcode_in [12:11] connect \SHIFT_ROT_BI \opcode_in [20:16] connect \SHIFT_ROT_BO \opcode_in [25:21] connect \SHIFT_ROT_FXM \opcode_in [19:12] connect \SHIFT_ROT_BT \opcode_in [25:21] connect \SHIFT_ROT_BA \opcode_in [20:16] connect \SHIFT_ROT_BB \opcode_in [15:11] connect \SHIFT_ROT_CR \opcode_in [10:1] connect \SHIFT_ROT_BF \opcode_in [25:23] connect \SHIFT_ROT_BD \opcode_in [15:2] connect \SHIFT_ROT_OE \opcode_in [10] connect \SHIFT_ROT_Rc \opcode_in [0] connect \SHIFT_ROT_AA \opcode_in [1] connect \SHIFT_ROT_LK \opcode_in [0] connect \SHIFT_ROT_LI \opcode_in [25:2] connect \SHIFT_ROT_ME32 \opcode_in [5:1] connect \SHIFT_ROT_MB32 \opcode_in [10:6] connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } connect \SHIFT_ROT_SH32 \opcode_in [15:11] connect \SHIFT_ROT_L \opcode_in [21] connect \SHIFT_ROT_UI \opcode_in [15:0] connect \SHIFT_ROT_SI \opcode_in [15:0] connect \SHIFT_ROT_RB \opcode_in [15:11] connect \SHIFT_ROT_RA \opcode_in [20:16] connect \SHIFT_ROT_RT \opcode_in [25:21] connect \SHIFT_ROT_RS \opcode_in [25:21] connect \SHIFT_ROT_PO \opcode_in [31:26] connect \opcode_in \$1 connect \SHIFT_ROT_dec31_opcode_in \opcode_in connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:64221.1-66730.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" module \dec$166 attribute \src "libresoc.v:65812.3-65869.6" wire $0\LDST_br[0:0] attribute \src "libresoc.v:66276.3-66333.6" wire width 3 $0\LDST_cr_in[2:0] attribute \src "libresoc.v:66334.3-66391.6" wire width 3 $0\LDST_cr_out[2:0] attribute \src "libresoc.v:66044.3-66101.6" wire width 14 $0\LDST_function_unit[13:0] attribute \src "libresoc.v:66160.3-66217.6" wire width 3 $0\LDST_in1_sel[2:0] attribute \src "libresoc.v:66218.3-66275.6" wire width 4 $0\LDST_in2_sel[3:0] attribute \src "libresoc.v:66102.3-66159.6" wire width 7 $0\LDST_internal_op[6:0] attribute \src "libresoc.v:65928.3-65985.6" wire $0\LDST_is_32b[0:0] attribute \src "libresoc.v:65638.3-65695.6" wire width 4 $0\LDST_ldst_len[3:0] attribute \src "libresoc.v:65754.3-65811.6" wire width 2 $0\LDST_rc_sel[1:0] attribute \src "libresoc.v:65986.3-66043.6" wire $0\LDST_sgn[0:0] attribute \src "libresoc.v:65870.3-65927.6" wire $0\LDST_sgn_ext[0:0] attribute \src "libresoc.v:65696.3-65753.6" wire width 2 $0\LDST_upd[1:0] attribute \src "libresoc.v:64222.7-64222.20" wire $0\initial[0:0] attribute \src "libresoc.v:65812.3-65869.6" wire $1\LDST_br[0:0] attribute \src "libresoc.v:66276.3-66333.6" wire width 3 $1\LDST_cr_in[2:0] attribute \src "libresoc.v:66334.3-66391.6" wire width 3 $1\LDST_cr_out[2:0] attribute \src "libresoc.v:66044.3-66101.6" wire width 14 $1\LDST_function_unit[13:0] attribute \src "libresoc.v:66160.3-66217.6" wire width 3 $1\LDST_in1_sel[2:0] attribute \src "libresoc.v:66218.3-66275.6" wire width 4 $1\LDST_in2_sel[3:0] attribute \src "libresoc.v:66102.3-66159.6" wire width 7 $1\LDST_internal_op[6:0] attribute \src "libresoc.v:65928.3-65985.6" wire $1\LDST_is_32b[0:0] attribute \src "libresoc.v:65638.3-65695.6" wire width 4 $1\LDST_ldst_len[3:0] attribute \src "libresoc.v:65754.3-65811.6" wire width 2 $1\LDST_rc_sel[1:0] attribute \src "libresoc.v:65986.3-66043.6" wire $1\LDST_sgn[0:0] attribute \src "libresoc.v:65870.3-65927.6" wire $1\LDST_sgn_ext[0:0] attribute \src "libresoc.v:65696.3-65753.6" wire width 2 $1\LDST_upd[1:0] attribute \src "libresoc.v:65589.17-65589.211" wire width 32 $ternary$libresoc.v:65589$3538_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 24 \LDST_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \LDST_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \LDST_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \LDST_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \LDST_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 output 25 \LDST_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \LDST_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 output 21 \LDST_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \LDST_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \LDST_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \LDST_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 16 \LDST_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 22 \LDST_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 19 \LDST_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 17 \LDST_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \LDST_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \LDST_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 output 18 \LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 13 \LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 9 \LDST_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec31_LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec31_LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec31_LDST_dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec31_LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_LDST_dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec31_LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec31_LDST_dec31_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec31_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec58_LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec58_LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec58_LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec58_LDST_dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec58_LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec58_LDST_dec58_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec58_LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec58_LDST_dec58_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec58_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \LDST_dec62_LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \LDST_dec62_LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec62_LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \LDST_dec62_LDST_dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \LDST_dec62_LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec62_LDST_dec62_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \LDST_dec62_LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \LDST_dec62_LDST_dec62_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \LDST_dec62_opcode_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 6 \LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \LDST_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 11 \LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 10 \LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \LDST_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 12 \LDST_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 14 \LDST_sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 output 20 \LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \LDST_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute 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wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src 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\LDST_dec58_LDST_dec58_upd connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:65622.14-65637.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end attribute \src "libresoc.v:64222.7-64222.20" process $proc$libresoc.v:64222$3552 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:65638.3-65695.6" process $proc$libresoc.v:65638$3539 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] attribute \src "libresoc.v:65639.5-65639.29" switch \initial attribute \src "libresoc.v:65639.9-65639.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_ldst_len[3:0] 4'0100 case assign $1\LDST_ldst_len[3:0] 4'0000 end sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end attribute \src "libresoc.v:65696.3-65753.6" process $proc$libresoc.v:65696$3540 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] attribute \src "libresoc.v:65697.5-65697.29" switch \initial attribute \src "libresoc.v:65697.9-65697.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_upd[1:0] 2'01 case assign $1\LDST_upd[1:0] 2'00 end sync always update \LDST_upd $0\LDST_upd[1:0] end attribute \src "libresoc.v:65754.3-65811.6" process $proc$libresoc.v:65754$3541 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] attribute \src "libresoc.v:65755.5-65755.29" switch \initial attribute \src "libresoc.v:65755.9-65755.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_rc_sel[1:0] 2'00 case assign $1\LDST_rc_sel[1:0] 2'00 end sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end attribute \src "libresoc.v:65812.3-65869.6" process $proc$libresoc.v:65812$3542 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] attribute \src "libresoc.v:65813.5-65813.29" switch \initial attribute \src "libresoc.v:65813.9-65813.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_br[0:0] 1'0 case assign $1\LDST_br[0:0] 1'0 end sync always update \LDST_br $0\LDST_br[0:0] end attribute \src "libresoc.v:65870.3-65927.6" process $proc$libresoc.v:65870$3543 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] attribute \src "libresoc.v:65871.5-65871.29" switch \initial attribute \src "libresoc.v:65871.9-65871.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_sgn_ext[0:0] 1'0 case assign $1\LDST_sgn_ext[0:0] 1'0 end sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end attribute \src "libresoc.v:65928.3-65985.6" process $proc$libresoc.v:65928$3544 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] attribute \src "libresoc.v:65929.5-65929.29" switch \initial attribute \src "libresoc.v:65929.9-65929.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_is_32b[0:0] 1'0 case assign $1\LDST_is_32b[0:0] 1'0 end sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end attribute \src "libresoc.v:65986.3-66043.6" process $proc$libresoc.v:65986$3545 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] attribute \src "libresoc.v:65987.5-65987.29" switch \initial attribute \src "libresoc.v:65987.9-65987.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_sgn[0:0] 1'0 case assign $1\LDST_sgn[0:0] 1'0 end sync always update \LDST_sgn $0\LDST_sgn[0:0] end attribute \src "libresoc.v:66044.3-66101.6" process $proc$libresoc.v:66044$3546 assign { } { } assign { } { } assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] attribute \src "libresoc.v:66045.5-66045.29" switch \initial attribute \src "libresoc.v:66045.9-66045.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_function_unit[13:0] \LDST_dec31_LDST_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_function_unit[13:0] \LDST_dec58_LDST_dec58_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_function_unit[13:0] \LDST_dec62_LDST_dec62_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_function_unit[13:0] 14'00000000000100 case assign $1\LDST_function_unit[13:0] 14'00000000000000 end sync always update \LDST_function_unit $0\LDST_function_unit[13:0] end attribute \src "libresoc.v:66102.3-66159.6" process $proc$libresoc.v:66102$3547 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] attribute \src "libresoc.v:66103.5-66103.29" switch \initial attribute \src "libresoc.v:66103.9-66103.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_internal_op[6:0] 7'0100110 case assign $1\LDST_internal_op[6:0] 7'0000000 end sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end attribute \src "libresoc.v:66160.3-66217.6" process $proc$libresoc.v:66160$3548 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] attribute \src "libresoc.v:66161.5-66161.29" switch \initial attribute \src "libresoc.v:66161.9-66161.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_in1_sel[2:0] 3'010 case assign $1\LDST_in1_sel[2:0] 3'000 end sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end attribute \src "libresoc.v:66218.3-66275.6" process $proc$libresoc.v:66218$3549 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] attribute \src "libresoc.v:66219.5-66219.29" switch \initial attribute \src "libresoc.v:66219.9-66219.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_in2_sel[3:0] 4'0011 case assign $1\LDST_in2_sel[3:0] 4'0000 end sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end attribute \src "libresoc.v:66276.3-66333.6" process $proc$libresoc.v:66276$3550 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] attribute \src "libresoc.v:66277.5-66277.29" switch \initial attribute \src "libresoc.v:66277.9-66277.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_cr_in[2:0] 3'000 case assign $1\LDST_cr_in[2:0] 3'000 end sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end attribute \src "libresoc.v:66334.3-66391.6" process $proc$libresoc.v:66334$3551 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] attribute \src "libresoc.v:66335.5-66335.29" switch \initial attribute \src "libresoc.v:66335.9-66335.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\LDST_cr_out[2:0] 3'000 case assign $1\LDST_cr_out[2:0] 3'000 end sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end connect \$1 $ternary$libresoc.v:65589$3538_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \LDST_SPR \opcode_in [20:11] connect \LDST_MB \opcode_in [10:6] connect \LDST_ME \opcode_in [5:1] connect \LDST_SH \opcode_in [15:11] connect \LDST_BC \opcode_in [10:6] connect \LDST_TO \opcode_in [25:21] connect \LDST_DS \opcode_in [15:2] connect \LDST_D \opcode_in [15:0] connect \LDST_BH \opcode_in [12:11] connect \LDST_BI \opcode_in [20:16] connect \LDST_BO \opcode_in [25:21] connect \LDST_FXM \opcode_in [19:12] connect \LDST_BT \opcode_in [25:21] connect \LDST_BA \opcode_in [20:16] connect \LDST_BB \opcode_in [15:11] connect \LDST_CR \opcode_in [10:1] connect \LDST_BF \opcode_in [25:23] connect \LDST_BD \opcode_in [15:2] connect \LDST_OE \opcode_in [10] connect \LDST_Rc \opcode_in [0] connect \LDST_AA \opcode_in [1] connect \LDST_LK \opcode_in [0] connect \LDST_LI \opcode_in [25:2] connect \LDST_ME32 \opcode_in [5:1] connect \LDST_MB32 \opcode_in [10:6] connect \LDST_sh { \opcode_in [1] \opcode_in [15:11] } connect \LDST_SH32 \opcode_in [15:11] connect \LDST_L \opcode_in [21] connect \LDST_UI \opcode_in [15:0] connect \LDST_SI \opcode_in [15:0] connect \LDST_RB \opcode_in [15:11] connect \LDST_RA \opcode_in [20:16] connect \LDST_RT \opcode_in [25:21] connect \LDST_RS \opcode_in [25:21] connect \LDST_PO \opcode_in [31:26] connect \opcode_in \$1 connect \LDST_dec62_opcode_in \opcode_in connect \LDST_dec58_opcode_in \opcode_in connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:66734.1-74954.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" module \dec$171 attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $0\SV_Etype[1:0] attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $0\SV_Ptype[1:0] attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $0\asmcode[7:0] attribute \src "libresoc.v:73307.3-73451.6" wire $0\br[0:0] attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $0\cr_in[2:0] attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $0\cr_out[2:0] attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $0\cry_in[1:0] attribute \src "libresoc.v:73162.3-73306.6" wire $0\cry_out[0:0] attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $0\form[4:0] attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $0\function_unit[13:0] attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $0\in1_sel[2:0] attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $0\in2_sel[3:0] attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $0\in3_sel[1:0] attribute \src "libresoc.v:66735.7-66735.20" wire $0\initial[0:0] attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $0\internal_op[6:0] attribute \src "libresoc.v:72872.3-73016.6" wire $0\inv_a[0:0] attribute \src "libresoc.v:73017.3-73161.6" wire $0\inv_out[0:0] attribute \src "libresoc.v:73742.3-73886.6" wire $0\is_32b[0:0] attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $0\ldst_len[3:0] attribute \src "libresoc.v:74032.3-74176.6" wire $0\lk[0:0] attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $0\out_sel[2:0] attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $0\rc_sel[1:0] attribute \src "libresoc.v:73597.3-73741.6" wire $0\rsrv[0:0] attribute \src "libresoc.v:74177.3-74321.6" wire $0\sgl_pipe[0:0] attribute \src "libresoc.v:73887.3-74031.6" wire $0\sgn[0:0] attribute \src "libresoc.v:73452.3-73596.6" wire $0\sgn_ext[0:0] attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $0\sv_cr_in[2:0] attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $0\sv_cr_out[2:0] attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $0\sv_in1[2:0] attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $0\sv_in2[2:0] attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $0\sv_in3[2:0] attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $0\sv_out2[2:0] attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $0\sv_out[2:0] attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $0\upd[1:0] attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $1\SV_Etype[1:0] attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $1\SV_Ptype[1:0] attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $1\asmcode[7:0] attribute \src "libresoc.v:73307.3-73451.6" wire $1\br[0:0] attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $1\cr_in[2:0] attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $1\cr_out[2:0] attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $1\cry_in[1:0] attribute \src "libresoc.v:73162.3-73306.6" wire $1\cry_out[0:0] attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $1\form[4:0] attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $1\function_unit[13:0] attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $1\in1_sel[2:0] attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $1\in2_sel[3:0] attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $1\in3_sel[1:0] attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $1\internal_op[6:0] attribute \src "libresoc.v:72872.3-73016.6" wire $1\inv_a[0:0] attribute \src "libresoc.v:73017.3-73161.6" wire $1\inv_out[0:0] attribute \src "libresoc.v:73742.3-73886.6" wire $1\is_32b[0:0] attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $1\ldst_len[3:0] attribute \src "libresoc.v:74032.3-74176.6" wire $1\lk[0:0] attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $1\out_sel[2:0] attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $1\rc_sel[1:0] attribute \src "libresoc.v:73597.3-73741.6" wire $1\rsrv[0:0] attribute \src "libresoc.v:74177.3-74321.6" wire $1\sgl_pipe[0:0] attribute \src "libresoc.v:73887.3-74031.6" wire $1\sgn[0:0] attribute \src "libresoc.v:73452.3-73596.6" wire $1\sgn_ext[0:0] attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $1\sv_cr_in[2:0] attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $1\sv_cr_out[2:0] attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $1\sv_in1[2:0] attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $1\sv_in2[2:0] attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $1\sv_in3[2:0] attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $1\sv_out2[2:0] attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $1\sv_out[2:0] attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $1\upd[1:0] attribute \src "libresoc.v:70117.3-70261.6" wire width 2 $2\SV_Etype[1:0] attribute \src "libresoc.v:70262.3-70406.6" wire width 2 $2\SV_Ptype[1:0] attribute \src "libresoc.v:69972.3-70116.6" wire width 8 $2\asmcode[7:0] attribute \src "libresoc.v:73307.3-73451.6" wire $2\br[0:0] attribute \src "libresoc.v:70987.3-71131.6" wire width 3 $2\cr_in[2:0] attribute \src "libresoc.v:71132.3-71276.6" wire width 3 $2\cr_out[2:0] attribute \src "libresoc.v:72727.3-72871.6" wire width 2 $2\cry_in[1:0] attribute \src "libresoc.v:73162.3-73306.6" wire $2\cry_out[0:0] attribute \src "libresoc.v:69827.3-69971.6" wire width 5 $2\form[4:0] attribute \src "libresoc.v:74322.3-74466.6" wire width 14 $2\function_unit[13:0] attribute \src "libresoc.v:70407.3-70551.6" wire width 3 $2\in1_sel[2:0] attribute \src "libresoc.v:70552.3-70696.6" wire width 4 $2\in2_sel[3:0] attribute \src "libresoc.v:70697.3-70841.6" wire width 2 $2\in3_sel[1:0] attribute \src "libresoc.v:74467.3-74611.6" wire width 7 $2\internal_op[6:0] attribute \src "libresoc.v:72872.3-73016.6" wire $2\inv_a[0:0] attribute \src "libresoc.v:73017.3-73161.6" wire $2\inv_out[0:0] attribute \src "libresoc.v:73742.3-73886.6" wire $2\is_32b[0:0] attribute \src "libresoc.v:72292.3-72436.6" wire width 4 $2\ldst_len[3:0] attribute \src "libresoc.v:74032.3-74176.6" wire $2\lk[0:0] attribute \src "libresoc.v:70842.3-70986.6" wire width 3 $2\out_sel[2:0] attribute \src "libresoc.v:72582.3-72726.6" wire width 2 $2\rc_sel[1:0] attribute \src "libresoc.v:73597.3-73741.6" wire $2\rsrv[0:0] attribute \src "libresoc.v:74177.3-74321.6" wire $2\sgl_pipe[0:0] attribute \src "libresoc.v:73887.3-74031.6" wire $2\sgn[0:0] attribute \src "libresoc.v:73452.3-73596.6" wire $2\sgn_ext[0:0] attribute \src "libresoc.v:72002.3-72146.6" wire width 3 $2\sv_cr_in[2:0] attribute \src "libresoc.v:72147.3-72291.6" wire width 3 $2\sv_cr_out[2:0] attribute \src "libresoc.v:71277.3-71421.6" wire width 3 $2\sv_in1[2:0] attribute \src "libresoc.v:71422.3-71566.6" wire width 3 $2\sv_in2[2:0] attribute \src "libresoc.v:71567.3-71711.6" wire width 3 $2\sv_in3[2:0] attribute \src "libresoc.v:71857.3-72001.6" wire width 3 $2\sv_out2[2:0] attribute \src "libresoc.v:71712.3-71856.6" wire width 3 $2\sv_out[2:0] attribute \src "libresoc.v:72437.3-72581.6" wire width 2 $2\upd[1:0] attribute \src "libresoc.v:69610.17-69610.211" wire width 32 $ternary$libresoc.v:69610$3553_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \A_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \A_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 26 \BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 25 \BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 31 \BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 3 \BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 2 \BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 30 \BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 29 \BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 27 \BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \B_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \B_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \B_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQE_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DQE_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 12 \DQ_DQ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \DQ_PT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DQ_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DQ_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \DQ_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \DQ_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 14 \DS_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DS_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \DS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \DX_d0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \DX_d0_d1_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \DX_d1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \DX_d2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \D_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \D_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \D_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 16 \D_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \EVS_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 output 28 \FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 24 \I_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \I_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 11 \LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \MB32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_IS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MDS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MDS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XBI_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \MDS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MDS_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \MD_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \MD_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \MD_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \MD_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_ME attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \M_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \M_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 24 \OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 21 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 22 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 19 \RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 output 20 \RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire output 23 \Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \SC_LEV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \SC_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 output 5 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \SVL_SVi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \SVL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_ms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \SVL_vs attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \TX_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \TX_XBI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \TX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VA_SHB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VA_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \VA_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VC_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VC_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VC_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \VX_PS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_SIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \VX_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \VX_UIM_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \VX_UIM_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \VX_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \VX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 11 \VX_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFL_FLM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFL_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XFL_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_BHRBE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_DUI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_DUIS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XFX_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XFX_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \XFX_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XL_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 output 34 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 15 \XL_OC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XL_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 output 35 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XO_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XO_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XO_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XS_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XS_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XS_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XS_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX2_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX2_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX2_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX2_UIM_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX2_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \XX2_dc_dm_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX2_dm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX2_dx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \XX3_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_DM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX3_SHW attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX3_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX3_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX3_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \XX3_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \XX3_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \XX3_XO_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_AX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_AX_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_BX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_BX_B attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_CX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_CX_C attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \XX4_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \XX4_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \XX4_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \XX4_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 output 32 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 output 33 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_CT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 7 \X_DCMX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_DRM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_E attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_EO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_EO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_EX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_E_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \X_IH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_IMM8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_L1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_L3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_MO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_NB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_PRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RIC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_RM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_RO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RSp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_RTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_R_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_SP attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_SR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_SX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_SX_S attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_TBR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_TX attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \X_TX_T attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 4 \X_U attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_UIM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \X_VRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \X_W attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \X_WC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \X_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \X_XO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \Z22_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DCM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_DGM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z22_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z22_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \Z22_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 9 \Z22_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRAp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRBp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_FRTp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_R attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 2 \Z23_RMC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire \Z23_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \Z23_TE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 8 \Z23_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 17 \asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 36 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 8 \cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \cry_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec19_dec19_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec19_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec19_dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec19_dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec19_dec19_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec19_dec19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec19_dec19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec19_dec19_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec19_opcode_in attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec22_dec22_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec22_dec22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute 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"LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec22_dec22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec22_dec22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec22_dec22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec22_dec22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" 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attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \in3_sel attribute \src "libresoc.v:66735.7-66735.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 4 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 9 \is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 10 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 32 \opcode_switch$1 attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \out_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 3 \rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \sh attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 18 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" cell $mux $ternary$libresoc.v:69610$3553 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian connect \Y $ternary$libresoc.v:69610$3553_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:69611.9-69646.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype connect \dec19_asmcode \dec19_dec19_asmcode connect \dec19_br \dec19_dec19_br connect \dec19_cr_in \dec19_dec19_cr_in connect \dec19_cr_out \dec19_dec19_cr_out connect \dec19_cry_in \dec19_dec19_cry_in connect \dec19_cry_out \dec19_dec19_cry_out connect \dec19_form \dec19_dec19_form connect \dec19_function_unit \dec19_dec19_function_unit connect \dec19_in1_sel \dec19_dec19_in1_sel connect \dec19_in2_sel \dec19_dec19_in2_sel connect \dec19_in3_sel \dec19_dec19_in3_sel connect \dec19_internal_op \dec19_dec19_internal_op connect \dec19_inv_a \dec19_dec19_inv_a connect \dec19_inv_out \dec19_dec19_inv_out connect \dec19_is_32b \dec19_dec19_is_32b connect \dec19_ldst_len \dec19_dec19_ldst_len connect \dec19_lk \dec19_dec19_lk connect \dec19_out_sel \dec19_dec19_out_sel connect \dec19_rc_sel \dec19_dec19_rc_sel connect \dec19_rsrv \dec19_dec19_rsrv connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe connect \dec19_sgn \dec19_dec19_sgn connect \dec19_sgn_ext \dec19_dec19_sgn_ext connect \dec19_sv_cr_in \dec19_dec19_sv_cr_in connect \dec19_sv_cr_out \dec19_dec19_sv_cr_out connect \dec19_sv_in1 \dec19_dec19_sv_in1 connect \dec19_sv_in2 \dec19_dec19_sv_in2 connect \dec19_sv_in3 \dec19_dec19_sv_in3 connect \dec19_sv_out \dec19_dec19_sv_out connect \dec19_sv_out2 \dec19_dec19_sv_out2 connect \dec19_upd \dec19_dec19_upd connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:69647.9-69682.4" cell \dec22 \dec22 connect \dec22_SV_Etype \dec22_dec22_SV_Etype connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype connect \dec22_asmcode \dec22_dec22_asmcode connect \dec22_br \dec22_dec22_br connect \dec22_cr_in \dec22_dec22_cr_in connect \dec22_cr_out \dec22_dec22_cr_out connect \dec22_cry_in \dec22_dec22_cry_in connect \dec22_cry_out \dec22_dec22_cry_out connect \dec22_form \dec22_dec22_form connect \dec22_function_unit \dec22_dec22_function_unit connect \dec22_in1_sel \dec22_dec22_in1_sel connect \dec22_in2_sel \dec22_dec22_in2_sel connect \dec22_in3_sel \dec22_dec22_in3_sel connect \dec22_internal_op \dec22_dec22_internal_op connect \dec22_inv_a \dec22_dec22_inv_a connect \dec22_inv_out \dec22_dec22_inv_out connect \dec22_is_32b \dec22_dec22_is_32b connect \dec22_ldst_len \dec22_dec22_ldst_len connect \dec22_lk \dec22_dec22_lk connect \dec22_out_sel \dec22_dec22_out_sel connect \dec22_rc_sel \dec22_dec22_rc_sel connect \dec22_rsrv \dec22_dec22_rsrv connect \dec22_sgl_pipe \dec22_dec22_sgl_pipe connect \dec22_sgn \dec22_dec22_sgn connect \dec22_sgn_ext \dec22_dec22_sgn_ext connect \dec22_sv_cr_in \dec22_dec22_sv_cr_in connect \dec22_sv_cr_out \dec22_dec22_sv_cr_out connect \dec22_sv_in1 \dec22_dec22_sv_in1 connect \dec22_sv_in2 \dec22_dec22_sv_in2 connect \dec22_sv_in3 \dec22_dec22_sv_in3 connect \dec22_sv_out \dec22_dec22_sv_out connect \dec22_sv_out2 \dec22_dec22_sv_out2 connect \dec22_upd \dec22_dec22_upd connect \opcode_in \dec22_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:69683.9-69718.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype connect \dec30_asmcode \dec30_dec30_asmcode connect \dec30_br \dec30_dec30_br connect \dec30_cr_in \dec30_dec30_cr_in connect \dec30_cr_out \dec30_dec30_cr_out connect \dec30_cry_in \dec30_dec30_cry_in connect \dec30_cry_out \dec30_dec30_cry_out connect \dec30_form \dec30_dec30_form connect \dec30_function_unit \dec30_dec30_function_unit connect \dec30_in1_sel \dec30_dec30_in1_sel connect \dec30_in2_sel \dec30_dec30_in2_sel connect \dec30_in3_sel \dec30_dec30_in3_sel connect \dec30_internal_op \dec30_dec30_internal_op connect \dec30_inv_a \dec30_dec30_inv_a connect \dec30_inv_out \dec30_dec30_inv_out connect \dec30_is_32b \dec30_dec30_is_32b connect \dec30_ldst_len \dec30_dec30_ldst_len connect \dec30_lk \dec30_dec30_lk connect \dec30_out_sel \dec30_dec30_out_sel connect \dec30_rc_sel \dec30_dec30_rc_sel connect \dec30_rsrv \dec30_dec30_rsrv connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe connect \dec30_sgn \dec30_dec30_sgn connect \dec30_sgn_ext \dec30_dec30_sgn_ext connect \dec30_sv_cr_in \dec30_dec30_sv_cr_in connect \dec30_sv_cr_out \dec30_dec30_sv_cr_out connect \dec30_sv_in1 \dec30_dec30_sv_in1 connect \dec30_sv_in2 \dec30_dec30_sv_in2 connect \dec30_sv_in3 \dec30_dec30_sv_in3 connect \dec30_sv_out \dec30_dec30_sv_out connect \dec30_sv_out2 \dec30_dec30_sv_out2 connect \dec30_upd \dec30_dec30_upd connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:69719.9-69754.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype connect \dec31_asmcode \dec31_dec31_asmcode connect \dec31_br \dec31_dec31_br connect \dec31_cr_in \dec31_dec31_cr_in connect \dec31_cr_out \dec31_dec31_cr_out connect \dec31_cry_in \dec31_dec31_cry_in connect \dec31_cry_out \dec31_dec31_cry_out connect \dec31_form \dec31_dec31_form connect \dec31_function_unit \dec31_dec31_function_unit connect \dec31_in1_sel \dec31_dec31_in1_sel connect \dec31_in2_sel \dec31_dec31_in2_sel connect \dec31_in3_sel \dec31_dec31_in3_sel connect \dec31_internal_op \dec31_dec31_internal_op connect \dec31_inv_a \dec31_dec31_inv_a connect \dec31_inv_out \dec31_dec31_inv_out connect \dec31_is_32b \dec31_dec31_is_32b connect \dec31_ldst_len \dec31_dec31_ldst_len connect \dec31_lk \dec31_dec31_lk connect \dec31_out_sel \dec31_dec31_out_sel connect \dec31_rc_sel \dec31_dec31_rc_sel connect \dec31_rsrv \dec31_dec31_rsrv connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe connect \dec31_sgn \dec31_dec31_sgn connect \dec31_sgn_ext \dec31_dec31_sgn_ext connect \dec31_sv_cr_in \dec31_dec31_sv_cr_in connect \dec31_sv_cr_out \dec31_dec31_sv_cr_out connect \dec31_sv_in1 \dec31_dec31_sv_in1 connect \dec31_sv_in2 \dec31_dec31_sv_in2 connect \dec31_sv_in3 \dec31_dec31_sv_in3 connect \dec31_sv_out \dec31_dec31_sv_out connect \dec31_sv_out2 \dec31_dec31_sv_out2 connect \dec31_upd \dec31_dec31_upd connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:69755.9-69790.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype connect \dec58_asmcode \dec58_dec58_asmcode connect \dec58_br \dec58_dec58_br connect \dec58_cr_in \dec58_dec58_cr_in connect \dec58_cr_out \dec58_dec58_cr_out connect \dec58_cry_in \dec58_dec58_cry_in connect \dec58_cry_out \dec58_dec58_cry_out connect \dec58_form \dec58_dec58_form connect \dec58_function_unit \dec58_dec58_function_unit connect \dec58_in1_sel \dec58_dec58_in1_sel connect \dec58_in2_sel \dec58_dec58_in2_sel connect \dec58_in3_sel \dec58_dec58_in3_sel connect \dec58_internal_op \dec58_dec58_internal_op connect \dec58_inv_a \dec58_dec58_inv_a connect \dec58_inv_out \dec58_dec58_inv_out connect \dec58_is_32b \dec58_dec58_is_32b connect \dec58_ldst_len \dec58_dec58_ldst_len connect \dec58_lk \dec58_dec58_lk connect \dec58_out_sel \dec58_dec58_out_sel connect \dec58_rc_sel \dec58_dec58_rc_sel connect \dec58_rsrv \dec58_dec58_rsrv connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe connect \dec58_sgn \dec58_dec58_sgn connect \dec58_sgn_ext \dec58_dec58_sgn_ext connect \dec58_sv_cr_in \dec58_dec58_sv_cr_in connect \dec58_sv_cr_out \dec58_dec58_sv_cr_out connect \dec58_sv_in1 \dec58_dec58_sv_in1 connect \dec58_sv_in2 \dec58_dec58_sv_in2 connect \dec58_sv_in3 \dec58_dec58_sv_in3 connect \dec58_sv_out \dec58_dec58_sv_out connect \dec58_sv_out2 \dec58_dec58_sv_out2 connect \dec58_upd \dec58_dec58_upd connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:69791.9-69826.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype connect \dec62_asmcode \dec62_dec62_asmcode connect \dec62_br \dec62_dec62_br connect \dec62_cr_in \dec62_dec62_cr_in connect \dec62_cr_out \dec62_dec62_cr_out connect \dec62_cry_in \dec62_dec62_cry_in connect \dec62_cry_out \dec62_dec62_cry_out connect \dec62_form \dec62_dec62_form connect \dec62_function_unit \dec62_dec62_function_unit connect \dec62_in1_sel \dec62_dec62_in1_sel connect \dec62_in2_sel \dec62_dec62_in2_sel connect \dec62_in3_sel \dec62_dec62_in3_sel connect \dec62_internal_op \dec62_dec62_internal_op connect \dec62_inv_a \dec62_dec62_inv_a connect \dec62_inv_out \dec62_dec62_inv_out connect \dec62_is_32b \dec62_dec62_is_32b connect \dec62_ldst_len \dec62_dec62_ldst_len connect \dec62_lk \dec62_dec62_lk connect \dec62_out_sel \dec62_dec62_out_sel connect \dec62_rc_sel \dec62_dec62_rc_sel connect \dec62_rsrv \dec62_dec62_rsrv connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe connect \dec62_sgn \dec62_dec62_sgn connect \dec62_sgn_ext \dec62_dec62_sgn_ext connect \dec62_sv_cr_in \dec62_dec62_sv_cr_in connect \dec62_sv_cr_out \dec62_dec62_sv_cr_out connect \dec62_sv_in1 \dec62_dec62_sv_in1 connect \dec62_sv_in2 \dec62_dec62_sv_in2 connect \dec62_sv_in3 \dec62_dec62_sv_in3 connect \dec62_sv_out \dec62_dec62_sv_out connect \dec62_sv_out2 \dec62_dec62_sv_out2 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end attribute \src "libresoc.v:66735.7-66735.20" process $proc$libresoc.v:66735$3587 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:69827.3-69971.6" process $proc$libresoc.v:69827$3554 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] attribute \src "libresoc.v:69828.5-69828.29" switch \initial attribute \src "libresoc.v:69828.9-69828.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\form[4:0] \dec19_dec19_form attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\form[4:0] \dec30_dec30_form attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\form[4:0] \dec31_dec31_form attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\form[4:0] \dec58_dec58_form attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\form[4:0] \dec62_dec62_form attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\form[4:0] \dec22_dec22_form attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\form[4:0] 5'00011 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\form[4:0] 5'00010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\form[4:0] 5'00010 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\form[4:0] 5'00001 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\form[4:0] 5'00010 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\form[4:0] 5'10011 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\form[4:0] 5'10011 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\form[4:0] 5'10011 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\form[4:0] 5'00100 case assign $1\form[4:0] 5'00000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\form[4:0] 5'00000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\form[4:0] 5'00000 case assign $2\form[4:0] $1\form[4:0] end sync always update \form $0\form[4:0] end attribute \src "libresoc.v:69972.3-70116.6" process $proc$libresoc.v:69972$3555 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] attribute \src "libresoc.v:69973.5-69973.29" switch \initial attribute \src "libresoc.v:69973.9-69973.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\asmcode[7:0] \dec19_dec19_asmcode attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\asmcode[7:0] \dec30_dec30_asmcode attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\asmcode[7:0] \dec31_dec31_asmcode attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\asmcode[7:0] \dec58_dec58_asmcode attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\asmcode[7:0] \dec62_dec62_asmcode attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\asmcode[7:0] \dec22_dec22_asmcode attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\asmcode[7:0] 8'00000111 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\asmcode[7:0] 8'00001000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\asmcode[7:0] 8'00000110 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\asmcode[7:0] 8'00001001 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign $1\asmcode[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\asmcode[7:0] 8'00010001 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\asmcode[7:0] 8'00010010 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\asmcode[7:0] 8'00010100 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\asmcode[7:0] 8'00010101 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\asmcode[7:0] 8'00011101 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\asmcode[7:0] 8'00011111 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\asmcode[7:0] 8'01001110 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\asmcode[7:0] 8'01001111 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\asmcode[7:0] 8'01011000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\asmcode[7:0] 8'01011010 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\asmcode[7:0] 8'01011110 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\asmcode[7:0] 8'01011111 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\asmcode[7:0] 8'01100111 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\asmcode[7:0] 8'01101001 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\asmcode[7:0] 8'10000000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\asmcode[7:0] 8'10001010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\asmcode[7:0] 8'10001011 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\asmcode[7:0] 8'10011000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\asmcode[7:0] 8'10011001 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\asmcode[7:0] 8'10011010 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\asmcode[7:0] 8'10100111 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\asmcode[7:0] 8'10101010 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\asmcode[7:0] 8'10110011 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\asmcode[7:0] 8'10110110 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\asmcode[7:0] 8'10111001 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\asmcode[7:0] 8'10111100 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\asmcode[7:0] 8'11000100 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\asmcode[7:0] 8'11001100 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\asmcode[7:0] 8'11010000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\asmcode[7:0] 8'11010010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\asmcode[7:0] 8'11010011 case assign $1\asmcode[7:0] 8'00000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\asmcode[7:0] 8'00010011 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\asmcode[7:0] 8'10000110 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\asmcode[7:0] 8'10011101 case assign $2\asmcode[7:0] $1\asmcode[7:0] end sync always update \asmcode $0\asmcode[7:0] end attribute \src "libresoc.v:70117.3-70261.6" process $proc$libresoc.v:70117$3556 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] attribute \src "libresoc.v:70118.5-70118.29" switch \initial attribute \src "libresoc.v:70118.9-70118.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\SV_Etype[1:0] \dec19_dec19_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SV_Etype[1:0] \dec30_dec30_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SV_Etype[1:0] \dec31_dec31_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\SV_Etype[1:0] \dec58_dec58_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\SV_Etype[1:0] \dec62_dec62_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\SV_Etype[1:0] \dec22_dec22_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\SV_Etype[1:0] 2'10 case assign $1\SV_Etype[1:0] 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\SV_Etype[1:0] 2'00 case assign $2\SV_Etype[1:0] $1\SV_Etype[1:0] end sync always update \SV_Etype $0\SV_Etype[1:0] end attribute \src "libresoc.v:70262.3-70406.6" process $proc$libresoc.v:70262$3557 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] attribute \src "libresoc.v:70263.5-70263.29" switch \initial attribute \src "libresoc.v:70263.9-70263.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\SV_Ptype[1:0] \dec19_dec19_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\SV_Ptype[1:0] \dec30_dec30_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\SV_Ptype[1:0] \dec31_dec31_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\SV_Ptype[1:0] \dec58_dec58_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\SV_Ptype[1:0] \dec62_dec62_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\SV_Ptype[1:0] \dec22_dec22_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\SV_Ptype[1:0] 2'10 case assign $1\SV_Ptype[1:0] 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\SV_Ptype[1:0] 2'00 case assign $2\SV_Ptype[1:0] $1\SV_Ptype[1:0] end sync always update \SV_Ptype $0\SV_Ptype[1:0] end attribute \src "libresoc.v:70407.3-70551.6" process $proc$libresoc.v:70407$3558 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] attribute \src "libresoc.v:70408.5-70408.29" switch \initial attribute \src "libresoc.v:70408.9-70408.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\in1_sel[2:0] \dec19_dec19_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\in1_sel[2:0] \dec30_dec30_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\in1_sel[2:0] \dec31_dec31_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\in1_sel[2:0] \dec58_dec58_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\in1_sel[2:0] \dec62_dec62_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\in1_sel[2:0] \dec22_dec22_in1_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\in1_sel[2:0] 3'100 case assign $1\in1_sel[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\in1_sel[2:0] 3'000 case assign $2\in1_sel[2:0] $1\in1_sel[2:0] end sync always update \in1_sel $0\in1_sel[2:0] end attribute \src "libresoc.v:70552.3-70696.6" process $proc$libresoc.v:70552$3559 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] attribute \src "libresoc.v:70553.5-70553.29" switch \initial attribute \src "libresoc.v:70553.9-70553.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\in2_sel[3:0] \dec19_dec19_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\in2_sel[3:0] \dec30_dec30_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\in2_sel[3:0] \dec31_dec31_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\in2_sel[3:0] \dec58_dec58_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\in2_sel[3:0] \dec62_dec62_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\in2_sel[3:0] \dec22_dec22_in2_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\in2_sel[3:0] 4'0101 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\in2_sel[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\in2_sel[3:0] 4'0110 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\in2_sel[3:0] 4'0111 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\in2_sel[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\in2_sel[3:0] 4'0011 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\in2_sel[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\in2_sel[3:0] 4'0100 case assign $1\in2_sel[3:0] 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\in2_sel[3:0] 4'0000 case assign $2\in2_sel[3:0] $1\in2_sel[3:0] end sync always update \in2_sel $0\in2_sel[3:0] end attribute \src "libresoc.v:70697.3-70841.6" process $proc$libresoc.v:70697$3560 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] attribute \src "libresoc.v:70698.5-70698.29" switch \initial attribute \src "libresoc.v:70698.9-70698.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\in3_sel[1:0] \dec19_dec19_in3_sel attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\in3_sel[1:0] \dec30_dec30_in3_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\in3_sel[1:0] \dec31_dec31_in3_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\in3_sel[1:0] \dec58_dec58_in3_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\in3_sel[1:0] \dec62_dec62_in3_sel attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\in3_sel[1:0] \dec22_dec22_in3_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\in3_sel[1:0] 2'00 case assign $1\in3_sel[1:0] 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\in3_sel[1:0] 2'00 case assign $2\in3_sel[1:0] $1\in3_sel[1:0] end sync always update \in3_sel $0\in3_sel[1:0] end attribute \src "libresoc.v:70842.3-70986.6" process $proc$libresoc.v:70842$3561 assign { } { } assign { } { } assign { } { } assign $0\out_sel[2:0] $2\out_sel[2:0] attribute \src "libresoc.v:70843.5-70843.29" switch \initial attribute \src "libresoc.v:70843.9-70843.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\out_sel[2:0] \dec19_dec19_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\out_sel[2:0] \dec30_dec30_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\out_sel[2:0] \dec31_dec31_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\out_sel[2:0] \dec58_dec58_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\out_sel[2:0] \dec62_dec62_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\out_sel[2:0] \dec22_dec22_out_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\out_sel[2:0] 3'010 case assign $1\out_sel[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\out_sel[2:0] 3'001 case assign $2\out_sel[2:0] $1\out_sel[2:0] end sync always update \out_sel $0\out_sel[2:0] end attribute \src "libresoc.v:70987.3-71131.6" process $proc$libresoc.v:70987$3562 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] attribute \src "libresoc.v:70988.5-70988.29" switch \initial attribute \src "libresoc.v:70988.9-70988.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\cr_in[2:0] \dec19_dec19_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\cr_in[2:0] \dec30_dec30_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\cr_in[2:0] \dec31_dec31_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\cr_in[2:0] \dec58_dec58_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\cr_in[2:0] \dec62_dec62_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\cr_in[2:0] \dec22_dec22_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\cr_in[2:0] 3'000 case assign $1\cr_in[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\cr_in[2:0] 3'000 case assign $2\cr_in[2:0] $1\cr_in[2:0] end sync always update \cr_in $0\cr_in[2:0] end attribute \src "libresoc.v:71132.3-71276.6" process $proc$libresoc.v:71132$3563 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] attribute \src "libresoc.v:71133.5-71133.29" switch \initial attribute \src "libresoc.v:71133.9-71133.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\cr_out[2:0] \dec19_dec19_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\cr_out[2:0] \dec30_dec30_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\cr_out[2:0] \dec31_dec31_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\cr_out[2:0] \dec58_dec58_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\cr_out[2:0] \dec62_dec62_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\cr_out[2:0] \dec22_dec22_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\cr_out[2:0] 3'000 case assign $1\cr_out[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\cr_out[2:0] 3'000 case assign $2\cr_out[2:0] $1\cr_out[2:0] end sync always update \cr_out $0\cr_out[2:0] end attribute \src "libresoc.v:71277.3-71421.6" process $proc$libresoc.v:71277$3564 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] attribute \src "libresoc.v:71278.5-71278.29" switch \initial attribute \src "libresoc.v:71278.9-71278.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sv_in1[2:0] \dec19_dec19_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sv_in1[2:0] \dec30_dec30_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sv_in1[2:0] \dec31_dec31_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sv_in1[2:0] \dec58_dec58_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sv_in1[2:0] \dec62_dec62_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sv_in1[2:0] \dec22_dec22_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sv_in1[2:0] 3'010 case assign $1\sv_in1[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sv_in1[2:0] 3'000 case assign $2\sv_in1[2:0] $1\sv_in1[2:0] end sync always update \sv_in1 $0\sv_in1[2:0] end attribute \src "libresoc.v:71422.3-71566.6" process $proc$libresoc.v:71422$3565 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] attribute \src "libresoc.v:71423.5-71423.29" switch \initial attribute \src "libresoc.v:71423.9-71423.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sv_in2[2:0] \dec19_dec19_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sv_in2[2:0] \dec30_dec30_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sv_in2[2:0] \dec31_dec31_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sv_in2[2:0] \dec58_dec58_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sv_in2[2:0] \dec62_dec62_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sv_in2[2:0] \dec22_dec22_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sv_in2[2:0] 3'000 case assign $1\sv_in2[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sv_in2[2:0] 3'000 case assign $2\sv_in2[2:0] $1\sv_in2[2:0] end sync always update \sv_in2 $0\sv_in2[2:0] end attribute \src "libresoc.v:71567.3-71711.6" process $proc$libresoc.v:71567$3566 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] attribute \src "libresoc.v:71568.5-71568.29" switch \initial attribute \src "libresoc.v:71568.9-71568.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sv_in3[2:0] \dec19_dec19_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sv_in3[2:0] \dec30_dec30_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sv_in3[2:0] \dec31_dec31_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sv_in3[2:0] \dec58_dec58_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sv_in3[2:0] \dec62_dec62_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sv_in3[2:0] \dec22_dec22_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sv_in3[2:0] 3'000 case assign $1\sv_in3[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sv_in3[2:0] 3'000 case assign $2\sv_in3[2:0] $1\sv_in3[2:0] end sync always update \sv_in3 $0\sv_in3[2:0] end attribute \src "libresoc.v:71712.3-71856.6" process $proc$libresoc.v:71712$3567 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] attribute \src "libresoc.v:71713.5-71713.29" switch \initial attribute \src "libresoc.v:71713.9-71713.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sv_out[2:0] \dec19_dec19_sv_out attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sv_out[2:0] \dec30_dec30_sv_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sv_out[2:0] \dec31_dec31_sv_out attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sv_out[2:0] \dec58_dec58_sv_out attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sv_out[2:0] \dec62_dec62_sv_out attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sv_out[2:0] \dec22_dec22_sv_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sv_out[2:0] 3'001 case assign $1\sv_out[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sv_out[2:0] 3'000 case assign $2\sv_out[2:0] $1\sv_out[2:0] end sync always update \sv_out $0\sv_out[2:0] end attribute \src "libresoc.v:71857.3-72001.6" process $proc$libresoc.v:71857$3568 assign { } { } assign { } { } assign { } { } assign $0\sv_out2[2:0] $2\sv_out2[2:0] attribute \src "libresoc.v:71858.5-71858.29" switch \initial attribute \src "libresoc.v:71858.9-71858.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sv_out2[2:0] \dec19_dec19_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sv_out2[2:0] \dec30_dec30_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sv_out2[2:0] \dec31_dec31_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sv_out2[2:0] \dec58_dec58_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sv_out2[2:0] \dec62_dec62_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sv_out2[2:0] \dec22_dec22_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sv_out2[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sv_out2[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sv_out2[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sv_out2[2:0] 3'000 case assign $1\sv_out2[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sv_out2[2:0] 3'000 case assign $2\sv_out2[2:0] $1\sv_out2[2:0] end sync always update \sv_out2 $0\sv_out2[2:0] end attribute \src "libresoc.v:72002.3-72146.6" process $proc$libresoc.v:72002$3569 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] attribute \src "libresoc.v:72003.5-72003.29" switch \initial attribute \src "libresoc.v:72003.9-72003.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sv_cr_in[2:0] \dec19_dec19_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sv_cr_in[2:0] \dec30_dec30_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sv_cr_in[2:0] \dec31_dec31_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sv_cr_in[2:0] \dec58_dec58_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sv_cr_in[2:0] \dec62_dec62_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sv_cr_in[2:0] \dec22_dec22_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sv_cr_in[2:0] 3'000 case assign $1\sv_cr_in[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sv_cr_in[2:0] 3'000 case assign $2\sv_cr_in[2:0] $1\sv_cr_in[2:0] end sync always update \sv_cr_in $0\sv_cr_in[2:0] end attribute \src "libresoc.v:72147.3-72291.6" process $proc$libresoc.v:72147$3570 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] attribute \src "libresoc.v:72148.5-72148.29" switch \initial attribute \src "libresoc.v:72148.9-72148.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sv_cr_out[2:0] \dec19_dec19_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sv_cr_out[2:0] \dec30_dec30_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sv_cr_out[2:0] \dec31_dec31_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sv_cr_out[2:0] \dec58_dec58_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sv_cr_out[2:0] \dec62_dec62_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sv_cr_out[2:0] \dec22_dec22_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sv_cr_out[2:0] 3'000 case assign $1\sv_cr_out[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sv_cr_out[2:0] 3'000 case assign $2\sv_cr_out[2:0] $1\sv_cr_out[2:0] end sync always update \sv_cr_out $0\sv_cr_out[2:0] end attribute \src "libresoc.v:72292.3-72436.6" process $proc$libresoc.v:72292$3571 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] attribute \src "libresoc.v:72293.5-72293.29" switch \initial attribute \src "libresoc.v:72293.9-72293.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\ldst_len[3:0] \dec19_dec19_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\ldst_len[3:0] \dec30_dec30_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\ldst_len[3:0] \dec31_dec31_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\ldst_len[3:0] \dec58_dec58_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\ldst_len[3:0] \dec62_dec62_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\ldst_len[3:0] \dec22_dec22_ldst_len attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\ldst_len[3:0] 4'0000 case assign $1\ldst_len[3:0] 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\ldst_len[3:0] 4'0000 case assign $2\ldst_len[3:0] $1\ldst_len[3:0] end sync always update \ldst_len $0\ldst_len[3:0] end attribute \src "libresoc.v:72437.3-72581.6" process $proc$libresoc.v:72437$3572 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] attribute \src "libresoc.v:72438.5-72438.29" switch \initial attribute \src "libresoc.v:72438.9-72438.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\upd[1:0] \dec19_dec19_upd attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\upd[1:0] \dec30_dec30_upd attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\upd[1:0] \dec31_dec31_upd attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\upd[1:0] \dec58_dec58_upd attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\upd[1:0] \dec62_dec62_upd attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\upd[1:0] \dec22_dec22_upd attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\upd[1:0] 2'00 case assign $1\upd[1:0] 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\upd[1:0] 2'00 case assign $2\upd[1:0] $1\upd[1:0] end sync always update \upd $0\upd[1:0] end attribute \src "libresoc.v:72582.3-72726.6" process $proc$libresoc.v:72582$3573 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] attribute \src "libresoc.v:72583.5-72583.29" switch \initial attribute \src "libresoc.v:72583.9-72583.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\rc_sel[1:0] \dec19_dec19_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\rc_sel[1:0] \dec30_dec30_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\rc_sel[1:0] \dec31_dec31_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\rc_sel[1:0] \dec58_dec58_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\rc_sel[1:0] \dec62_dec62_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\rc_sel[1:0] \dec22_dec22_rc_sel attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\rc_sel[1:0] 2'00 case assign $1\rc_sel[1:0] 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\rc_sel[1:0] 2'00 case assign $2\rc_sel[1:0] $1\rc_sel[1:0] end sync always update \rc_sel $0\rc_sel[1:0] end attribute \src "libresoc.v:72727.3-72871.6" process $proc$libresoc.v:72727$3574 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] attribute \src "libresoc.v:72728.5-72728.29" switch \initial attribute \src "libresoc.v:72728.9-72728.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\cry_in[1:0] \dec19_dec19_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\cry_in[1:0] \dec30_dec30_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\cry_in[1:0] \dec31_dec31_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\cry_in[1:0] \dec58_dec58_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\cry_in[1:0] \dec62_dec62_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\cry_in[1:0] \dec22_dec22_cry_in attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\cry_in[1:0] 2'00 case assign $1\cry_in[1:0] 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\cry_in[1:0] 2'00 case assign $2\cry_in[1:0] $1\cry_in[1:0] end sync always update \cry_in $0\cry_in[1:0] end attribute \src "libresoc.v:72872.3-73016.6" process $proc$libresoc.v:72872$3575 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] attribute \src "libresoc.v:72873.5-72873.29" switch \initial attribute \src "libresoc.v:72873.9-72873.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\inv_a[0:0] \dec19_dec19_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\inv_a[0:0] \dec30_dec30_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\inv_a[0:0] \dec31_dec31_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\inv_a[0:0] \dec58_dec58_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\inv_a[0:0] \dec62_dec62_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\inv_a[0:0] \dec22_dec22_inv_a attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\inv_a[0:0] 1'0 case assign $1\inv_a[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\inv_a[0:0] 1'0 case assign $2\inv_a[0:0] $1\inv_a[0:0] end sync always update \inv_a $0\inv_a[0:0] end attribute \src "libresoc.v:73017.3-73161.6" process $proc$libresoc.v:73017$3576 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] attribute \src "libresoc.v:73018.5-73018.29" switch \initial attribute \src "libresoc.v:73018.9-73018.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\inv_out[0:0] \dec19_dec19_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\inv_out[0:0] \dec30_dec30_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\inv_out[0:0] \dec31_dec31_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\inv_out[0:0] \dec58_dec58_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\inv_out[0:0] \dec62_dec62_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\inv_out[0:0] \dec22_dec22_inv_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\inv_out[0:0] 1'0 case assign $1\inv_out[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\inv_out[0:0] 1'0 case assign $2\inv_out[0:0] $1\inv_out[0:0] end sync always update \inv_out $0\inv_out[0:0] end attribute \src "libresoc.v:73162.3-73306.6" process $proc$libresoc.v:73162$3577 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] attribute \src "libresoc.v:73163.5-73163.29" switch \initial attribute \src "libresoc.v:73163.9-73163.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\cry_out[0:0] \dec19_dec19_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\cry_out[0:0] \dec30_dec30_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\cry_out[0:0] \dec31_dec31_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\cry_out[0:0] \dec58_dec58_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\cry_out[0:0] \dec62_dec62_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\cry_out[0:0] \dec22_dec22_cry_out attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\cry_out[0:0] 1'0 case assign $1\cry_out[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\cry_out[0:0] 1'0 case assign $2\cry_out[0:0] $1\cry_out[0:0] end sync always update \cry_out $0\cry_out[0:0] end attribute \src "libresoc.v:73307.3-73451.6" process $proc$libresoc.v:73307$3578 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] attribute \src "libresoc.v:73308.5-73308.29" switch \initial attribute \src "libresoc.v:73308.9-73308.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\br[0:0] \dec19_dec19_br attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\br[0:0] \dec30_dec30_br attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\br[0:0] \dec31_dec31_br attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\br[0:0] \dec58_dec58_br attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\br[0:0] \dec62_dec62_br attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\br[0:0] \dec22_dec22_br attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\br[0:0] 1'0 case assign $1\br[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\br[0:0] 1'0 case assign $2\br[0:0] $1\br[0:0] end sync always update \br $0\br[0:0] end attribute \src "libresoc.v:73452.3-73596.6" process $proc$libresoc.v:73452$3579 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] attribute \src "libresoc.v:73453.5-73453.29" switch \initial attribute \src "libresoc.v:73453.9-73453.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sgn_ext[0:0] \dec22_dec22_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sgn_ext[0:0] 1'0 case assign $1\sgn_ext[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sgn_ext[0:0] 1'0 case assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] end sync always update \sgn_ext $0\sgn_ext[0:0] end attribute \src "libresoc.v:73597.3-73741.6" process $proc$libresoc.v:73597$3580 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] attribute \src "libresoc.v:73598.5-73598.29" switch \initial attribute \src "libresoc.v:73598.9-73598.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\rsrv[0:0] \dec19_dec19_rsrv attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\rsrv[0:0] \dec30_dec30_rsrv attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\rsrv[0:0] \dec31_dec31_rsrv attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\rsrv[0:0] \dec58_dec58_rsrv attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\rsrv[0:0] \dec62_dec62_rsrv attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\rsrv[0:0] \dec22_dec22_rsrv attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\rsrv[0:0] 1'0 case assign $1\rsrv[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\rsrv[0:0] 1'0 case assign $2\rsrv[0:0] $1\rsrv[0:0] end sync always update \rsrv $0\rsrv[0:0] end attribute \src "libresoc.v:73742.3-73886.6" process $proc$libresoc.v:73742$3581 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] attribute \src "libresoc.v:73743.5-73743.29" switch \initial attribute \src "libresoc.v:73743.9-73743.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\is_32b[0:0] \dec19_dec19_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\is_32b[0:0] \dec30_dec30_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\is_32b[0:0] \dec31_dec31_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\is_32b[0:0] \dec58_dec58_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\is_32b[0:0] \dec62_dec62_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\is_32b[0:0] \dec22_dec22_is_32b attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\is_32b[0:0] 1'0 case assign $1\is_32b[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\is_32b[0:0] 1'0 case assign $2\is_32b[0:0] $1\is_32b[0:0] end sync always update \is_32b $0\is_32b[0:0] end attribute \src "libresoc.v:73887.3-74031.6" process $proc$libresoc.v:73887$3582 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] attribute \src "libresoc.v:73888.5-73888.29" switch \initial attribute \src "libresoc.v:73888.9-73888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sgn[0:0] \dec19_dec19_sgn attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sgn[0:0] \dec30_dec30_sgn attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sgn[0:0] \dec31_dec31_sgn attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sgn[0:0] \dec58_dec58_sgn attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sgn[0:0] \dec62_dec62_sgn attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sgn[0:0] \dec22_dec22_sgn attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sgn[0:0] 1'0 case assign $1\sgn[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sgn[0:0] 1'0 case assign $2\sgn[0:0] $1\sgn[0:0] end sync always update \sgn $0\sgn[0:0] end attribute \src "libresoc.v:74032.3-74176.6" process $proc$libresoc.v:74032$3583 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] attribute \src "libresoc.v:74033.5-74033.29" switch \initial attribute \src "libresoc.v:74033.9-74033.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\lk[0:0] \dec19_dec19_lk attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\lk[0:0] \dec30_dec30_lk attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\lk[0:0] \dec31_dec31_lk attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\lk[0:0] \dec58_dec58_lk attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\lk[0:0] \dec62_dec62_lk attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\lk[0:0] \dec22_dec22_lk attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\lk[0:0] 1'0 case assign $1\lk[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\lk[0:0] 1'0 case assign $2\lk[0:0] $1\lk[0:0] end sync always update \lk $0\lk[0:0] end attribute \src "libresoc.v:74177.3-74321.6" process $proc$libresoc.v:74177$3584 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] attribute \src "libresoc.v:74178.5-74178.29" switch \initial attribute \src "libresoc.v:74178.9-74178.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\sgl_pipe[0:0] \dec22_dec22_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\sgl_pipe[0:0] 1'0 case assign $1\sgl_pipe[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\sgl_pipe[0:0] 1'1 case assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] end sync always update \sgl_pipe $0\sgl_pipe[0:0] end attribute \src "libresoc.v:74322.3-74466.6" process $proc$libresoc.v:74322$3585 assign { } { } assign { } { } assign { } { } assign $0\function_unit[13:0] $2\function_unit[13:0] attribute \src "libresoc.v:74323.5-74323.29" switch \initial attribute \src "libresoc.v:74323.9-74323.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\function_unit[13:0] \dec19_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\function_unit[13:0] \dec30_dec30_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\function_unit[13:0] \dec31_dec31_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\function_unit[13:0] \dec58_dec58_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\function_unit[13:0] \dec62_dec62_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\function_unit[13:0] \dec22_dec22_function_unit attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\function_unit[13:0] 14'00000000010000 case assign $1\function_unit[13:0] 14'00000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\function_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\function_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\function_unit[13:0] 14'00000000000000 case assign $2\function_unit[13:0] $1\function_unit[13:0] end sync always update \function_unit $0\function_unit[13:0] end attribute \src "libresoc.v:74467.3-74611.6" process $proc$libresoc.v:74467$3586 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] attribute \src "libresoc.v:74468.5-74468.29" switch \initial attribute \src "libresoc.v:74468.9-74468.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 assign { } { } assign $1\internal_op[6:0] \dec19_dec19_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'011110 assign { } { } assign $1\internal_op[6:0] \dec30_dec30_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'011111 assign { } { } assign $1\internal_op[6:0] \dec31_dec31_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'111010 assign { } { } assign $1\internal_op[6:0] \dec58_dec58_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'111110 assign { } { } assign $1\internal_op[6:0] \dec62_dec62_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'010110 assign { } { } assign $1\internal_op[6:0] \dec22_dec22_internal_op attribute \src "libresoc.v:0.0-0.0" case 6'001100 assign { } { } assign $1\internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'001101 assign { } { } assign $1\internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'001110 assign { } { } assign $1\internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'001111 assign { } { } assign $1\internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'010001 assign { } { } assign $1\internal_op[6:0] 7'1001001 attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 6'011101 assign { } { } assign $1\internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 6'010010 assign { } { } assign $1\internal_op[6:0] 7'0000110 attribute \src "libresoc.v:0.0-0.0" case 6'010000 assign { } { } assign $1\internal_op[6:0] 7'0000111 attribute \src "libresoc.v:0.0-0.0" case 6'001011 assign { } { } assign $1\internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 6'001010 assign { } { } assign $1\internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 6'100010 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'100011 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101010 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101011 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101000 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'101001 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'100000 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'100001 assign { } { } assign $1\internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 6'000111 assign { } { } assign $1\internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 6'011000 assign { } { } assign $1\internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 6'011001 assign { } { } assign $1\internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } assign $1\internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } assign $1\internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } assign $1\internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } assign $1\internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'100111 assign { } { } assign $1\internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'101100 assign { } { } assign $1\internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'101101 assign { } { } assign $1\internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'100100 assign { } { } assign $1\internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'100101 assign { } { } assign $1\internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 6'001000 assign { } { } assign $1\internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 6'000010 assign { } { } assign $1\internal_op[6:0] 7'0111111 attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign { } { } assign $1\internal_op[6:0] 7'0111111 attribute \src "libresoc.v:0.0-0.0" case 6'011010 assign { } { } assign $1\internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" case 6'011011 assign { } { } assign $1\internal_op[6:0] 7'1000011 case assign $1\internal_op[6:0] 7'0000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- assign { } { } assign $2\internal_op[6:0] 7'0000101 attribute \src "libresoc.v:0.0-0.0" case 1610612736 assign { } { } assign $2\internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 32'000001---------------0000000011- assign { } { } assign $2\internal_op[6:0] 7'1000100 case assign $2\internal_op[6:0] $1\internal_op[6:0] end sync always update \internal_op $0\internal_op[6:0] end connect \$2 $ternary$libresoc.v:69610$3553_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] connect \VC_VRA \opcode_in [20:16] connect \VC_Rc \opcode_in [10] connect \XS_XO \opcode_in [10:2] connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } connect \XS_RS \opcode_in [25:21] connect \XS_Rc \opcode_in [0] connect \XS_RA \opcode_in [20:16] connect \VA_XO \opcode_in [5:0] connect \VA_VRT \opcode_in [25:21] connect \VA_VRC \opcode_in [10:6] connect \VA_VRB \opcode_in [15:11] connect \VA_VRA \opcode_in [20:16] connect \VA_SHB \opcode_in [9:6] connect \VA_RT \opcode_in [25:21] connect \VA_RC \opcode_in [10:6] connect \VA_RB \opcode_in [15:11] connect \VA_RA \opcode_in [20:16] connect \TX_XO \opcode_in [6:1] connect \TX_XBI \opcode_in [10:7] connect \TX_UI \opcode_in [15:11] connect \TX_RA \opcode_in [20:16] connect \DQE_XO \opcode_in [1:0] connect \DQE_RT \opcode_in [25:21] connect \DQE_RA \opcode_in [20:16] connect \all_PO \opcode_in [31:26] connect \XO_XO \opcode_in [9:1] connect \XO_RT \opcode_in [25:21] connect \XO_Rc \opcode_in [0] connect \XO_RB \opcode_in [15:11] connect \XO_RA \opcode_in [20:16] connect \XO_OE \opcode_in [10] connect \SVL_XO \opcode_in [5:1] connect \SVL_vs \opcode_in [7] connect \SVL_SVi \opcode_in [15:8] connect \SVL_RT \opcode_in [25:21] connect \SVL_Rc \opcode_in [0] connect \SVL_RA \opcode_in [20:16] connect \SVL_ms \opcode_in [6] connect \MD_XO \opcode_in [4:2] connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } connect \MD_RS \opcode_in [25:21] connect \MD_Rc \opcode_in [0] connect \MD_RA \opcode_in [20:16] connect \MD_me \opcode_in [10:5] connect \MD_mb \opcode_in [10:5] connect \M_SH \opcode_in [15:11] connect \M_RS \opcode_in [25:21] connect \M_Rc \opcode_in [0] connect \M_RB \opcode_in [15:11] connect \M_RA \opcode_in [20:16] connect \M_ME \opcode_in [5:1] connect \M_MB \opcode_in [10:6] connect \SC_XO_1 \opcode_in [1:0] connect \SC_XO \opcode_in [1] connect \SC_LEV \opcode_in [11:5] connect \MDS_XO \opcode_in [4:1] connect \MDS_XBI_1 \opcode_in [10:7] connect \MDS_XBI \opcode_in [10:7] connect \MDS_RS \opcode_in [25:21] connect \MDS_Rc \opcode_in [0] connect \MDS_RB \opcode_in [15:11] connect \MDS_RA \opcode_in [20:16] connect \MDS_me \opcode_in [10:5] connect \MDS_mb \opcode_in [10:5] connect \MDS_IS \opcode_in [25:21] connect \MDS_IB \opcode_in [15:11] connect \Z23_XO \opcode_in [8:1] connect \Z23_TE \opcode_in [20:16] connect \Z23_RMC \opcode_in [10:9] connect \Z23_Rc \opcode_in [0] connect \Z23_R \opcode_in [16] connect \Z23_FRTp \opcode_in [25:21] connect \Z23_FRT \opcode_in [25:21] connect \Z23_FRBp \opcode_in [15:11] connect \Z23_FRB \opcode_in [15:11] connect \Z23_FRAp \opcode_in [20:16] connect \Z23_FRA \opcode_in [20:16] connect \XFL_XO \opcode_in [10:1] connect \XFL_W \opcode_in [16] connect \XFL_Rc \opcode_in [0] connect \XFL_L \opcode_in [25] connect \XFL_FRB \opcode_in [15:11] connect \XFL_FLM \opcode_in [24:17] connect \VX_XO_1 \opcode_in [10:0] connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } connect \VX_VRT \opcode_in [25:21] connect \VX_VRB \opcode_in [15:11] connect \VX_VRA \opcode_in [20:16] connect \VX_UIM_3 \opcode_in [17:16] connect \VX_UIM_2 \opcode_in [18:16] connect \VX_UIM_1 \opcode_in [19:16] connect \VX_UIM \opcode_in [20:16] connect \VX_SIM \opcode_in [20:16] connect \VX_RT \opcode_in [25:21] connect \VX_RA \opcode_in [20:16] connect \VX_PS \opcode_in [9] connect \VX_EO \opcode_in [20:16] connect \DS_XO \opcode_in [1:0] connect \DS_VRT \opcode_in [25:21] connect \DS_VRS \opcode_in [25:21] connect \DS_RT \opcode_in [25:21] connect \DS_RSp \opcode_in [25:21] connect \DS_RS \opcode_in [25:21] connect \DS_RA \opcode_in [20:16] connect \DS_FRTp \opcode_in [25:21] connect \DS_FRSp \opcode_in [25:21] connect \DS_DS \opcode_in [15:2] connect \DQ_XO \opcode_in [2:0] connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } connect \DQ_T \opcode_in [25:21] connect \DQ_TX \opcode_in [3] connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } connect \DQ_S \opcode_in [25:21] connect \DQ_SX \opcode_in [3] connect \DQ_RTp \opcode_in [25:21] connect \DQ_RA \opcode_in [20:16] connect \DQ_PT \opcode_in [3:0] connect \DQ_DQ \opcode_in [15:4] connect \DX_XO \opcode_in [5:1] connect \DX_RT \opcode_in [25:21] connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } connect \DX_d2 \opcode_in [0] connect \DX_d1 \opcode_in [20:16] connect \DX_d0 \opcode_in [15:6] connect \XFX_XO \opcode_in [10:1] connect \XFX_SPR \opcode_in [20:11] connect \XFX_RT \opcode_in [25:21] connect \XFX_RS \opcode_in [25:21] connect \XFX_FXM \opcode_in [19:12] connect \XFX_DUIS \opcode_in [20:11] connect \XFX_DUI \opcode_in [25:21] connect \XFX_BHRBE \opcode_in [20:11] connect \EVS_BFA \opcode_in [2:0] connect \Z22_XO \opcode_in [9:1] connect \Z22_SH \opcode_in [15:10] connect \Z22_Rc \opcode_in [0] connect \Z22_FRTp \opcode_in [25:21] connect \Z22_FRT \opcode_in [25:21] connect \Z22_FRAp \opcode_in [20:16] connect \Z22_FRA \opcode_in [20:16] connect \Z22_DGM \opcode_in [15:10] connect \Z22_DCM \opcode_in [15:10] connect \Z22_BF \opcode_in [25:23] connect \XX2_XO_1 \opcode_in [10:2] connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } connect \XX2_UIM_1 \opcode_in [17:16] connect \XX2_UIM \opcode_in [19:16] connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX2_T \opcode_in [25:21] connect \XX2_TX \opcode_in [0] connect \XX2_RT \opcode_in [25:21] connect \XX2_EO \opcode_in [20:16] connect \XX2_DCMX \opcode_in [22:16] connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } connect \XX2_dx \opcode_in [20:16] connect \XX2_dm \opcode_in [2] connect \XX2_dc \opcode_in [6] connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX2_B \opcode_in [15:11] connect \XX2_BX \opcode_in [1] connect \XX2_BF \opcode_in [25:23] connect \D_UI \opcode_in [15:0] connect \D_TO \opcode_in [25:21] connect \D_SI \opcode_in [15:0] connect \D_RT \opcode_in [25:21] connect \D_RS \opcode_in [25:21] connect \D_RA \opcode_in [20:16] connect \D_L \opcode_in [21] connect \D_FRT \opcode_in [25:21] connect \D_FRS \opcode_in [25:21] connect \D_D \opcode_in [15:0] connect \D_BF \opcode_in [25:23] connect \A_XO \opcode_in [5:1] connect \A_RT \opcode_in [25:21] connect \A_Rc \opcode_in [0] connect \A_RB \opcode_in [15:11] connect \A_RA \opcode_in [20:16] connect \A_FRT \opcode_in [25:21] connect \A_FRC \opcode_in [10:6] connect \A_FRB \opcode_in [15:11] connect \A_FRA \opcode_in [20:16] connect \A_BC \opcode_in [10:6] connect \XL_XO \opcode_in [10:1] connect \XL_S \opcode_in [11] connect \XL_OC \opcode_in [25:11] connect \XL_LK \opcode_in [0] connect \XL_BT \opcode_in [25:21] connect \XL_BO_1 \opcode_in [25:21] connect \XL_BO \opcode_in [25:21] connect \XL_BI \opcode_in [20:16] connect \XL_BH \opcode_in [12:11] connect \XL_BFA \opcode_in [20:18] connect \XL_BF \opcode_in [25:23] connect \XL_BB \opcode_in [15:11] connect \XL_BA \opcode_in [20:16] connect \XX4_XO \opcode_in [5:4] connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX4_T \opcode_in [25:21] connect \XX4_TX \opcode_in [0] connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } connect \XX4_C \opcode_in [10:6] connect \XX4_CX \opcode_in [3] connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX4_B \opcode_in [15:11] connect \XX4_BX \opcode_in [1] connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX4_A \opcode_in [20:16] connect \XX4_AX \opcode_in [2] connect \XX3_XO_2 \opcode_in [9:1] connect \XX3_XO_1 \opcode_in [10:3] connect \XX3_XO \opcode_in [10:7] connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \XX3_T \opcode_in [25:21] connect \XX3_TX \opcode_in [0] connect \XX3_SHW \opcode_in [9:8] connect \XX3_Rc \opcode_in [10] connect \XX3_DM \opcode_in [9:8] connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } connect \XX3_B \opcode_in [15:11] connect \XX3_BX \opcode_in [1] connect \XX3_BF \opcode_in [25:23] connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } connect \XX3_A \opcode_in [20:16] connect \XX3_AX \opcode_in [2] connect \I_LK \opcode_in [0] connect \I_LI \opcode_in [25:2] connect \I_AA \opcode_in [1] connect \B_LK \opcode_in [0] connect \B_BO \opcode_in [25:21] connect \B_BI \opcode_in [20:16] connect \B_BD \opcode_in [15:2] connect \B_AA \opcode_in [1] connect \X_XO_1 \opcode_in [8:1] connect \X_XO \opcode_in [10:1] connect \X_WC \opcode_in [22:21] connect \X_W \opcode_in [16] connect \X_VRT \opcode_in [25:21] connect \X_VRS \opcode_in [25:21] connect \X_UIM \opcode_in [20:16] connect \X_U \opcode_in [15:12] connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } connect \X_TX \opcode_in [0] connect \X_TO \opcode_in [25:21] connect \X_TH \opcode_in [25:21] connect \X_TBR \opcode_in [20:11] connect \X_T \opcode_in [25:21] connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } connect \X_SX \opcode_in [0] connect \X_SR \opcode_in [19:16] connect \X_SP \opcode_in [20:19] connect \X_SI \opcode_in [15:11] connect \X_SH \opcode_in [15:11] connect \X_S \opcode_in [25:21] connect \X_RTp \opcode_in [25:21] connect \X_RT \opcode_in [25:21] connect \X_RSp \opcode_in [25:21] connect \X_RS \opcode_in [25:21] connect \X_RO \opcode_in [0] connect \X_RM \opcode_in [12:11] connect \X_RIC \opcode_in [19:18] connect \X_Rc \opcode_in [0] connect \X_RB \opcode_in [15:11] connect \X_RA \opcode_in [20:16] connect \X_R_1 \opcode_in [16] connect \X_R \opcode_in [21] connect \X_PRS \opcode_in [17] connect \X_NB \opcode_in [15:11] connect \X_MO \opcode_in [25:21] connect \X_L3 \opcode_in [17:16] connect \X_L1 \opcode_in [16] connect \X_L \opcode_in [21] connect \X_L2 \opcode_in [22:21] connect \X_IMM8 \opcode_in [18:11] connect \X_IH \opcode_in [23:21] connect \X_FRTp \opcode_in [25:21] connect \X_FRT \opcode_in [25:21] connect \X_FRSp \opcode_in [25:21] connect \X_FRS \opcode_in [25:21] connect \X_FRBp \opcode_in [15:11] connect \X_FRB \opcode_in [15:11] connect \X_FRAp \opcode_in [20:16] connect \X_FRA \opcode_in [20:16] connect \X_FC \opcode_in [15:11] connect \X_EX \opcode_in [0] connect \X_EO_1 \opcode_in [20:16] connect \X_EO \opcode_in [20:19] connect \X_E_1 \opcode_in [19:16] connect \X_E \opcode_in [15] connect \X_DRM \opcode_in [13:11] connect \X_DCMX \opcode_in [22:16] connect \X_CT \opcode_in [24:21] connect \X_BO \opcode_in [25:21] connect \X_BFA \opcode_in [20:18] connect \X_BF \opcode_in [25:23] connect \X_A \opcode_in [25] connect \SPR \opcode_in [20:11] connect \MB \opcode_in [10:6] connect \ME \opcode_in [5:1] connect \SH \opcode_in [15:11] connect \BC \opcode_in [10:6] connect \TO \opcode_in [25:21] connect \DS \opcode_in [15:2] connect \D \opcode_in [15:0] connect \BH \opcode_in [12:11] connect \BI \opcode_in [20:16] connect \BO \opcode_in [25:21] connect \FXM \opcode_in [19:12] connect \BT \opcode_in [25:21] connect \BA \opcode_in [20:16] connect \BB \opcode_in [15:11] connect \CR \opcode_in [10:1] connect \BF \opcode_in [25:23] connect \BD \opcode_in [15:2] connect \OE \opcode_in [10] connect \Rc \opcode_in [0] connect \AA \opcode_in [1] connect \LK \opcode_in [0] connect \LI \opcode_in [25:2] connect \ME32 \opcode_in [5:1] connect \MB32 \opcode_in [10:6] connect \sh { \opcode_in [1] \opcode_in [15:11] } connect \SH32 \opcode_in [15:11] connect \L \opcode_in [21] connect \UI \opcode_in [15:0] connect \SI \opcode_in [15:0] connect \RB \opcode_in [15:11] connect \RA \opcode_in [20:16] connect \RT \opcode_in [25:21] connect \RS \opcode_in [25:21] connect \PO \opcode_in [31:26] connect \opcode_in \$2 connect \opcode_switch$1 \opcode_in connect \dec22_opcode_in \opcode_in connect \dec62_opcode_in \opcode_in connect \dec58_opcode_in \opcode_in connect \dec31_opcode_in \opcode_in connect \dec30_opcode_in \opcode_in connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end attribute \src "libresoc.v:74958.1-77024.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 attribute \src "libresoc.v:76711.3-76762.6" wire width 2 $0\dec19_SV_Etype[1:0] attribute \src "libresoc.v:76763.3-76814.6" wire width 2 $0\dec19_SV_Ptype[1:0] attribute \src "libresoc.v:76087.3-76138.6" wire width 8 $0\dec19_asmcode[7:0] attribute \src "libresoc.v:76295.3-76346.6" wire $0\dec19_br[0:0] attribute \src "libresoc.v:75359.3-75410.6" wire width 3 $0\dec19_cr_in[2:0] attribute \src "libresoc.v:75411.3-75462.6" wire width 3 $0\dec19_cr_out[2:0] attribute \src "libresoc.v:76035.3-76086.6" wire width 2 $0\dec19_cry_in[1:0] attribute \src "libresoc.v:76243.3-76294.6" wire $0\dec19_cry_out[0:0] attribute \src "libresoc.v:76451.3-76502.6" wire width 5 $0\dec19_form[4:0] attribute \src "libresoc.v:75307.3-75358.6" wire width 14 $0\dec19_function_unit[13:0] attribute \src "libresoc.v:76815.3-76866.6" wire width 3 $0\dec19_in1_sel[2:0] attribute \src "libresoc.v:76867.3-76918.6" wire width 4 $0\dec19_in2_sel[3:0] attribute \src "libresoc.v:76919.3-76970.6" wire width 2 $0\dec19_in3_sel[1:0] attribute \src "libresoc.v:75879.3-75930.6" wire width 7 $0\dec19_internal_op[6:0] attribute \src "libresoc.v:76139.3-76190.6" wire $0\dec19_inv_a[0:0] attribute \src "libresoc.v:76191.3-76242.6" wire $0\dec19_inv_out[0:0] attribute \src "libresoc.v:76503.3-76554.6" wire $0\dec19_is_32b[0:0] attribute \src "libresoc.v:75827.3-75878.6" wire width 4 $0\dec19_ldst_len[3:0] attribute \src "libresoc.v:76607.3-76658.6" wire $0\dec19_lk[0:0] attribute \src "libresoc.v:76971.3-77022.6" wire width 3 $0\dec19_out_sel[2:0] attribute \src "libresoc.v:75983.3-76034.6" wire width 2 $0\dec19_rc_sel[1:0] attribute \src "libresoc.v:76399.3-76450.6" wire $0\dec19_rsrv[0:0] attribute \src "libresoc.v:76659.3-76710.6" wire $0\dec19_sgl_pipe[0:0] attribute \src "libresoc.v:76555.3-76606.6" wire $0\dec19_sgn[0:0] attribute \src "libresoc.v:76347.3-76398.6" wire $0\dec19_sgn_ext[0:0] attribute \src "libresoc.v:75723.3-75774.6" wire width 3 $0\dec19_sv_cr_in[2:0] attribute \src "libresoc.v:75775.3-75826.6" wire width 3 $0\dec19_sv_cr_out[2:0] attribute \src "libresoc.v:75463.3-75514.6" wire width 3 $0\dec19_sv_in1[2:0] attribute \src "libresoc.v:75515.3-75566.6" wire width 3 $0\dec19_sv_in2[2:0] attribute \src "libresoc.v:75567.3-75618.6" wire width 3 $0\dec19_sv_in3[2:0] attribute \src "libresoc.v:75671.3-75722.6" wire width 3 $0\dec19_sv_out2[2:0] attribute \src "libresoc.v:75619.3-75670.6" wire width 3 $0\dec19_sv_out[2:0] attribute \src "libresoc.v:75931.3-75982.6" wire width 2 $0\dec19_upd[1:0] attribute \src "libresoc.v:74959.7-74959.20" wire $0\initial[0:0] attribute \src "libresoc.v:76711.3-76762.6" wire width 2 $1\dec19_SV_Etype[1:0] attribute \src "libresoc.v:76763.3-76814.6" wire width 2 $1\dec19_SV_Ptype[1:0] attribute \src "libresoc.v:76087.3-76138.6" wire width 8 $1\dec19_asmcode[7:0] attribute \src "libresoc.v:76295.3-76346.6" wire $1\dec19_br[0:0] attribute \src "libresoc.v:75359.3-75410.6" wire width 3 $1\dec19_cr_in[2:0] attribute \src "libresoc.v:75411.3-75462.6" wire width 3 $1\dec19_cr_out[2:0] attribute \src "libresoc.v:76035.3-76086.6" wire width 2 $1\dec19_cry_in[1:0] attribute \src "libresoc.v:76243.3-76294.6" wire $1\dec19_cry_out[0:0] attribute \src "libresoc.v:76451.3-76502.6" wire width 5 $1\dec19_form[4:0] attribute \src "libresoc.v:75307.3-75358.6" wire width 14 $1\dec19_function_unit[13:0] attribute \src "libresoc.v:76815.3-76866.6" wire width 3 $1\dec19_in1_sel[2:0] attribute \src "libresoc.v:76867.3-76918.6" wire width 4 $1\dec19_in2_sel[3:0] attribute \src "libresoc.v:76919.3-76970.6" wire width 2 $1\dec19_in3_sel[1:0] attribute \src "libresoc.v:75879.3-75930.6" wire width 7 $1\dec19_internal_op[6:0] attribute \src "libresoc.v:76139.3-76190.6" wire $1\dec19_inv_a[0:0] attribute \src "libresoc.v:76191.3-76242.6" wire $1\dec19_inv_out[0:0] attribute \src "libresoc.v:76503.3-76554.6" wire $1\dec19_is_32b[0:0] attribute \src "libresoc.v:75827.3-75878.6" wire width 4 $1\dec19_ldst_len[3:0] attribute \src "libresoc.v:76607.3-76658.6" wire $1\dec19_lk[0:0] attribute \src "libresoc.v:76971.3-77022.6" wire width 3 $1\dec19_out_sel[2:0] attribute \src "libresoc.v:75983.3-76034.6" wire width 2 $1\dec19_rc_sel[1:0] attribute \src "libresoc.v:76399.3-76450.6" wire $1\dec19_rsrv[0:0] attribute \src "libresoc.v:76659.3-76710.6" wire $1\dec19_sgl_pipe[0:0] attribute \src "libresoc.v:76555.3-76606.6" wire $1\dec19_sgn[0:0] attribute \src "libresoc.v:76347.3-76398.6" wire $1\dec19_sgn_ext[0:0] attribute \src "libresoc.v:75723.3-75774.6" wire width 3 $1\dec19_sv_cr_in[2:0] attribute \src "libresoc.v:75775.3-75826.6" wire width 3 $1\dec19_sv_cr_out[2:0] attribute \src "libresoc.v:75463.3-75514.6" wire width 3 $1\dec19_sv_in1[2:0] attribute \src "libresoc.v:75515.3-75566.6" wire width 3 $1\dec19_sv_in2[2:0] attribute \src "libresoc.v:75567.3-75618.6" wire width 3 $1\dec19_sv_in3[2:0] attribute \src "libresoc.v:75671.3-75722.6" wire width 3 $1\dec19_sv_out2[2:0] attribute \src "libresoc.v:75619.3-75670.6" wire width 3 $1\dec19_sv_out[2:0] attribute \src "libresoc.v:75931.3-75982.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec19_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec19_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec19_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec19_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec19_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec19_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec19_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec19_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec19_upd attribute \src "libresoc.v:74959.7-74959.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \src "libresoc.v:74959.7-74959.20" process $proc$libresoc.v:74959$3621 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:75307.3-75358.6" process $proc$libresoc.v:75307$3588 assign { } { } assign { } { } assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] attribute \src "libresoc.v:75308.5-75308.29" switch \initial attribute \src "libresoc.v:75308.9-75308.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_function_unit[13:0] 14'00000010000000 case assign $1\dec19_function_unit[13:0] 14'00000000000000 end sync always update \dec19_function_unit $0\dec19_function_unit[13:0] end attribute \src "libresoc.v:75359.3-75410.6" process $proc$libresoc.v:75359$3589 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] attribute \src "libresoc.v:75360.5-75360.29" switch \initial attribute \src "libresoc.v:75360.9-75360.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_cr_in[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_cr_in[2:0] 3'000 case assign $1\dec19_cr_in[2:0] 3'000 end sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end attribute \src "libresoc.v:75411.3-75462.6" process $proc$libresoc.v:75411$3590 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] attribute \src "libresoc.v:75412.5-75412.29" switch \initial attribute \src "libresoc.v:75412.9-75412.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_cr_out[2:0] 3'000 case assign $1\dec19_cr_out[2:0] 3'000 end sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end attribute \src "libresoc.v:75463.3-75514.6" process $proc$libresoc.v:75463$3591 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] attribute \src "libresoc.v:75464.5-75464.29" switch \initial attribute \src "libresoc.v:75464.9-75464.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sv_in1[2:0] 3'000 case assign $1\dec19_sv_in1[2:0] 3'000 end sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end attribute \src "libresoc.v:75515.3-75566.6" process $proc$libresoc.v:75515$3592 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] attribute \src "libresoc.v:75516.5-75516.29" switch \initial attribute \src "libresoc.v:75516.9-75516.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sv_in2[2:0] 3'000 case assign $1\dec19_sv_in2[2:0] 3'000 end sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end attribute \src "libresoc.v:75567.3-75618.6" process $proc$libresoc.v:75567$3593 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] attribute \src "libresoc.v:75568.5-75568.29" switch \initial attribute \src "libresoc.v:75568.9-75568.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sv_in3[2:0] 3'000 case assign $1\dec19_sv_in3[2:0] 3'000 end sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end attribute \src "libresoc.v:75619.3-75670.6" process $proc$libresoc.v:75619$3594 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] attribute \src "libresoc.v:75620.5-75620.29" switch \initial attribute \src "libresoc.v:75620.9-75620.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sv_out[2:0] 3'000 case assign $1\dec19_sv_out[2:0] 3'000 end sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end attribute \src "libresoc.v:75671.3-75722.6" process $proc$libresoc.v:75671$3595 assign { } { } assign { } { } assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0] attribute \src "libresoc.v:75672.5-75672.29" switch \initial attribute \src "libresoc.v:75672.9-75672.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sv_out2[2:0] 3'000 case assign $1\dec19_sv_out2[2:0] 3'000 end sync always update \dec19_sv_out2 $0\dec19_sv_out2[2:0] end attribute \src "libresoc.v:75723.3-75774.6" process $proc$libresoc.v:75723$3596 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] attribute \src "libresoc.v:75724.5-75724.29" switch \initial attribute \src "libresoc.v:75724.9-75724.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sv_cr_in[2:0] 3'000 case assign $1\dec19_sv_cr_in[2:0] 3'000 end sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end attribute \src "libresoc.v:75775.3-75826.6" process $proc$libresoc.v:75775$3597 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] attribute \src "libresoc.v:75776.5-75776.29" switch \initial attribute \src "libresoc.v:75776.9-75776.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sv_cr_out[2:0] 3'000 case assign $1\dec19_sv_cr_out[2:0] 3'000 end sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end attribute \src "libresoc.v:75827.3-75878.6" process $proc$libresoc.v:75827$3598 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] attribute \src "libresoc.v:75828.5-75828.29" switch \initial attribute \src "libresoc.v:75828.9-75828.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_ldst_len[3:0] 4'0000 case assign $1\dec19_ldst_len[3:0] 4'0000 end sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end attribute \src "libresoc.v:75879.3-75930.6" process $proc$libresoc.v:75879$3599 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] attribute \src "libresoc.v:75880.5-75880.29" switch \initial attribute \src "libresoc.v:75880.9-75880.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_internal_op[6:0] 7'0101010 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_internal_op[6:0] 7'0001000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_internal_op[6:0] 7'0100100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000110 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_internal_op[6:0] 7'1000110 case assign $1\dec19_internal_op[6:0] 7'0000000 end sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end attribute \src "libresoc.v:75931.3-75982.6" process $proc$libresoc.v:75931$3600 assign { } { } assign { } { } assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] attribute \src "libresoc.v:75932.5-75932.29" switch \initial attribute \src "libresoc.v:75932.9-75932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_upd[1:0] 2'00 case assign $1\dec19_upd[1:0] 2'00 end sync always update \dec19_upd $0\dec19_upd[1:0] end attribute \src "libresoc.v:75983.3-76034.6" process $proc$libresoc.v:75983$3601 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] attribute \src "libresoc.v:75984.5-75984.29" switch \initial attribute \src "libresoc.v:75984.9-75984.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_rc_sel[1:0] 2'00 case assign $1\dec19_rc_sel[1:0] 2'00 end sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end attribute \src "libresoc.v:76035.3-76086.6" process $proc$libresoc.v:76035$3602 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] attribute \src "libresoc.v:76036.5-76036.29" switch \initial attribute \src "libresoc.v:76036.9-76036.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_cry_in[1:0] 2'00 case assign $1\dec19_cry_in[1:0] 2'00 end sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end attribute \src "libresoc.v:76087.3-76138.6" process $proc$libresoc.v:76087$3603 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] attribute \src "libresoc.v:76088.5-76088.29" switch \initial attribute \src "libresoc.v:76088.9-76088.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_asmcode[7:0] 8'01101100 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00100101 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00100110 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00100111 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00101000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00101001 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00101010 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00101011 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_asmcode[7:0] 8'00101100 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_asmcode[7:0] 8'00010110 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_asmcode[7:0] 8'00010111 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_asmcode[7:0] 8'00011000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_asmcode[7:0] 8'01001100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_asmcode[7:0] 8'10010001 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_asmcode[7:0] 8'01001000 case assign $1\dec19_asmcode[7:0] 8'00000000 end sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end attribute \src "libresoc.v:76139.3-76190.6" process $proc$libresoc.v:76139$3604 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] attribute \src "libresoc.v:76140.5-76140.29" switch \initial attribute \src "libresoc.v:76140.9-76140.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_inv_a[0:0] 1'0 case assign $1\dec19_inv_a[0:0] 1'0 end sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end attribute \src "libresoc.v:76191.3-76242.6" process $proc$libresoc.v:76191$3605 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] attribute \src "libresoc.v:76192.5-76192.29" switch \initial attribute \src "libresoc.v:76192.9-76192.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_inv_out[0:0] 1'0 case assign $1\dec19_inv_out[0:0] 1'0 end sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end attribute \src "libresoc.v:76243.3-76294.6" process $proc$libresoc.v:76243$3606 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] attribute \src "libresoc.v:76244.5-76244.29" switch \initial attribute \src "libresoc.v:76244.9-76244.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_cry_out[0:0] 1'0 case assign $1\dec19_cry_out[0:0] 1'0 end sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end attribute \src "libresoc.v:76295.3-76346.6" process $proc$libresoc.v:76295$3607 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] attribute \src "libresoc.v:76296.5-76296.29" switch \initial attribute \src "libresoc.v:76296.9-76296.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_br[0:0] 1'0 case assign $1\dec19_br[0:0] 1'0 end sync always update \dec19_br $0\dec19_br[0:0] end attribute \src "libresoc.v:76347.3-76398.6" process $proc$libresoc.v:76347$3608 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] attribute \src "libresoc.v:76348.5-76348.29" switch \initial attribute \src "libresoc.v:76348.9-76348.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sgn_ext[0:0] 1'0 case assign $1\dec19_sgn_ext[0:0] 1'0 end sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end attribute \src "libresoc.v:76399.3-76450.6" process $proc$libresoc.v:76399$3609 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] attribute \src "libresoc.v:76400.5-76400.29" switch \initial attribute \src "libresoc.v:76400.9-76400.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_rsrv[0:0] 1'0 case assign $1\dec19_rsrv[0:0] 1'0 end sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end attribute \src "libresoc.v:76451.3-76502.6" process $proc$libresoc.v:76451$3610 assign { } { } assign { } { } assign $0\dec19_form[4:0] $1\dec19_form[4:0] attribute \src "libresoc.v:76452.5-76452.29" switch \initial attribute \src "libresoc.v:76452.9-76452.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_form[4:0] 5'01001 case assign $1\dec19_form[4:0] 5'00000 end sync always update \dec19_form $0\dec19_form[4:0] end attribute \src "libresoc.v:76503.3-76554.6" process $proc$libresoc.v:76503$3611 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] attribute \src "libresoc.v:76504.5-76504.29" switch \initial attribute \src "libresoc.v:76504.9-76504.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_is_32b[0:0] 1'0 case assign $1\dec19_is_32b[0:0] 1'0 end sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end attribute \src "libresoc.v:76555.3-76606.6" process $proc$libresoc.v:76555$3612 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] attribute \src "libresoc.v:76556.5-76556.29" switch \initial attribute \src "libresoc.v:76556.9-76556.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sgn[0:0] 1'0 case assign $1\dec19_sgn[0:0] 1'0 end sync always update \dec19_sgn $0\dec19_sgn[0:0] end attribute \src "libresoc.v:76607.3-76658.6" process $proc$libresoc.v:76607$3613 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] attribute \src "libresoc.v:76608.5-76608.29" switch \initial attribute \src "libresoc.v:76608.9-76608.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_lk[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_lk[0:0] 1'0 case assign $1\dec19_lk[0:0] 1'0 end sync always update \dec19_lk $0\dec19_lk[0:0] end attribute \src "libresoc.v:76659.3-76710.6" process $proc$libresoc.v:76659$3614 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] attribute \src "libresoc.v:76660.5-76660.29" switch \initial attribute \src "libresoc.v:76660.9-76660.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_sgl_pipe[0:0] 1'0 case assign $1\dec19_sgl_pipe[0:0] 1'0 end sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end attribute \src "libresoc.v:76711.3-76762.6" process $proc$libresoc.v:76711$3615 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] attribute \src "libresoc.v:76712.5-76712.29" switch \initial attribute \src "libresoc.v:76712.9-76712.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_SV_Etype[1:0] 2'00 case assign $1\dec19_SV_Etype[1:0] 2'00 end sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end attribute \src "libresoc.v:76763.3-76814.6" process $proc$libresoc.v:76763$3616 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] attribute \src "libresoc.v:76764.5-76764.29" switch \initial attribute \src "libresoc.v:76764.9-76764.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_SV_Ptype[1:0] 2'00 case assign $1\dec19_SV_Ptype[1:0] 2'00 end sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end attribute \src "libresoc.v:76815.3-76866.6" process $proc$libresoc.v:76815$3617 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] attribute \src "libresoc.v:76816.5-76816.29" switch \initial attribute \src "libresoc.v:76816.9-76816.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_in1_sel[2:0] 3'011 case assign $1\dec19_in1_sel[2:0] 3'000 end sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end attribute \src "libresoc.v:76867.3-76918.6" process $proc$libresoc.v:76867$3618 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] attribute \src "libresoc.v:76868.5-76868.29" switch \initial attribute \src "libresoc.v:76868.9-76868.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_in2_sel[3:0] 4'1100 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_in2_sel[3:0] 4'1100 case assign $1\dec19_in2_sel[3:0] 4'0000 end sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end attribute \src "libresoc.v:76919.3-76970.6" process $proc$libresoc.v:76919$3619 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] attribute \src "libresoc.v:76920.5-76920.29" switch \initial attribute \src "libresoc.v:76920.9-76920.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_in3_sel[1:0] 2'00 case assign $1\dec19_in3_sel[1:0] 2'00 end sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end attribute \src "libresoc.v:76971.3-77022.6" process $proc$libresoc.v:76971$3620 assign { } { } assign { } { } assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] attribute \src "libresoc.v:76972.5-76972.29" switch \initial attribute \src "libresoc.v:76972.9-76972.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100100001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011100001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000100001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111000001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110100001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0011000001 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 assign { } { } assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000010000 assign { } { } assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'1000110000 assign { } { } assign $1\dec19_out_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\dec19_out_sel[2:0] 3'000 case assign $1\dec19_out_sel[2:0] 3'000 end sync always update \dec19_out_sel $0\dec19_out_sel[2:0] end connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:77028.1-79249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\asmcode[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $0\cia[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in2$1[6:0]$3682 attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_in2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in2_ok$2[0:0]$3683 attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_in2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\cr_out[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_out_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\cr_rd[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_rd_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\cr_wr[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\cr_wr_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\ea[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\ea_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$3[0:0]$3685 attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$4[0:0]$3686 attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$5[0:0]$3687 attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$6[0:0]$3688 attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$7[0:0]$3689 attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$8[0:0]$3690 attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal$9[0:0]$3691 attribute \src "libresoc.v:79012.3-79169.6" wire $0\exc_$signal[0:0]$3684 attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fast1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\fast1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fast2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\fast2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fasto1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\fasto1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\fasto2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\fasto2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $0\fn_unit[13:0] attribute \src "libresoc.v:77029.7-77029.20" wire $0\initial[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $0\input_carry[1:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $0\insn[31:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\insn_type[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\is_32bit[0:0] attribute \src "libresoc.v:78988.3-79011.6" wire $0\is_priv_insn[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\lk[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $0\msr[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\oe[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\rc[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\reg3[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\reg3_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $0\rego[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\rego_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $0\spr1[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\spr1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $0\spro[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\spro_ok[0:0] attribute \src "libresoc.v:78914.3-78928.6" wire width 14 $0\tmp_tmp_fn_unit[13:0] attribute \src "libresoc.v:78939.3-78951.6" wire width 7 $0\tmp_tmp_insn_type[6:0] attribute \src "libresoc.v:78929.3-78938.6" wire $0\tmp_tmp_lk[0:0] attribute \src "libresoc.v:78978.3-78987.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $0\tmp_xer_in[2:0] attribute \src "libresoc.v:78968.3-78977.6" wire $0\tmp_xer_out[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $0\trapaddr[12:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $0\traptype[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $0\xer_in[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $0\xer_out[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\asmcode[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $1\cia[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in2$1[6:0]$3692 attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_in2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in2_ok$2[0:0]$3693 attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_in2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\cr_out[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_out_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\cr_rd[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_rd_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\cr_wr[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\cr_wr_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\ea[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\ea_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$3[0:0]$3695 attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$4[0:0]$3696 attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$5[0:0]$3697 attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$6[0:0]$3698 attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$7[0:0]$3699 attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$8[0:0]$3700 attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal$9[0:0]$3701 attribute \src "libresoc.v:79012.3-79169.6" wire $1\exc_$signal[0:0]$3694 attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fast1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\fast1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fast2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\fast2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fasto1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\fasto1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\fasto2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\fasto2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $1\fn_unit[13:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $1\input_carry[1:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $1\insn[31:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\insn_type[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\is_32bit[0:0] attribute \src "libresoc.v:78988.3-79011.6" wire $1\is_priv_insn[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\lk[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $1\msr[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\oe[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\rc[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\rc_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\reg3[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\reg3_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $1\rego[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\rego_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $1\spr1[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\spr1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $1\spro[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\spro_ok[0:0] attribute \src "libresoc.v:78914.3-78928.6" wire width 14 $1\tmp_tmp_fn_unit[13:0] attribute \src "libresoc.v:78939.3-78951.6" wire width 7 $1\tmp_tmp_insn_type[6:0] attribute \src "libresoc.v:78929.3-78938.6" wire $1\tmp_tmp_lk[0:0] attribute \src "libresoc.v:78978.3-78987.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $1\tmp_xer_in[2:0] attribute \src "libresoc.v:78968.3-78977.6" wire $1\tmp_xer_out[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $1\trapaddr[12:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $1\traptype[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $1\xer_in[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $1\xer_out[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\asmcode[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $2\cia[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in2$1[6:0]$3702 attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_in2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in2_ok$2[0:0]$3703 attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_in2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\cr_out[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_out_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\cr_rd[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_rd_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\cr_wr[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\cr_wr_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\ea[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\ea_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$3[0:0]$3705 attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$4[0:0]$3706 attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$5[0:0]$3707 attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$6[0:0]$3708 attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$7[0:0]$3709 attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$8[0:0]$3710 attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal$9[0:0]$3711 attribute \src "libresoc.v:79012.3-79169.6" wire $2\exc_$signal[0:0]$3704 attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fast1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\fast1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fast2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\fast2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fasto1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\fasto1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\fasto2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\fasto2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $2\fn_unit[13:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $2\input_carry[1:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $2\insn[31:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\insn_type[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\is_32bit[0:0] attribute \src "libresoc.v:78988.3-79011.6" wire $2\is_priv_insn[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\lk[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $2\msr[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\oe[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\oe_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\rc[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\rc_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\reg3[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\reg3_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $2\rego[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\rego_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $2\spr1[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\spr1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $2\spro[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\spro_ok[0:0] attribute \src "libresoc.v:78952.3-78967.6" wire width 3 $2\tmp_xer_in[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $2\trapaddr[12:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $2\traptype[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $2\xer_in[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $2\xer_out[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\asmcode[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $3\cia[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in2$1[6:0]$3712 attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_in2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in2_ok$2[0:0]$3713 attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_in2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\cr_out[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_out_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\cr_rd[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_rd_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\cr_wr[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\cr_wr_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\ea[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\ea_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$3[0:0]$3715 attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$4[0:0]$3716 attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$5[0:0]$3717 attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$6[0:0]$3718 attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$7[0:0]$3719 attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$8[0:0]$3720 attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal$9[0:0]$3721 attribute \src "libresoc.v:79012.3-79169.6" wire $3\exc_$signal[0:0]$3714 attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fast1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\fast1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fast2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\fast2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fasto1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\fasto1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\fasto2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\fasto2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $3\fn_unit[13:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $3\input_carry[1:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $3\insn[31:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\insn_type[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\is_32bit[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\lk[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $3\msr[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\oe[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\oe_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\rc[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\rc_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\reg3[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\reg3_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $3\rego[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\rego_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $3\spr1[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\spr1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $3\spro[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\spro_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $3\trapaddr[12:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $3\traptype[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $3\xer_in[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $3\xer_out[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\asmcode[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $4\cia[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in2$1[6:0]$3722 attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_in2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in2_ok$2[0:0]$3723 attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_in2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\cr_out[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_out_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\cr_rd[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_rd_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\cr_wr[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\cr_wr_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\ea[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\ea_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$3[0:0]$3725 attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$4[0:0]$3726 attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$5[0:0]$3727 attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$6[0:0]$3728 attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$7[0:0]$3729 attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$8[0:0]$3730 attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal$9[0:0]$3731 attribute \src "libresoc.v:79012.3-79169.6" wire $4\exc_$signal[0:0]$3724 attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fast1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\fast1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fast2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\fast2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fasto1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\fasto1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\fasto2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\fasto2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 14 $4\fn_unit[13:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 2 $4\input_carry[1:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 32 $4\insn[31:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\insn_type[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\is_32bit[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\lk[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 64 $4\msr[63:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\oe[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\oe_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\rc[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\rc_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\reg1[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\reg1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\reg2[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\reg2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\reg3[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\reg3_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 7 $4\rego[6:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\rego_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $4\spr1[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\spr1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 10 $4\spro[9:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\spro_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 13 $4\trapaddr[12:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 8 $4\traptype[7:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $4\xer_in[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $4\xer_out[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fast1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $5\fast1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fast2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $5\fast2_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fasto1[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $5\fasto1_ok[0:0] attribute \src "libresoc.v:79012.3-79169.6" wire width 3 $5\fasto2[2:0] attribute \src "libresoc.v:79012.3-79169.6" wire $5\fasto2_ok[0:0] attribute \src "libresoc.v:78735.19-78735.122" wire $and$libresoc.v:78735$3632_Y attribute \src "libresoc.v:78736.19-78736.125" wire $and$libresoc.v:78736$3633_Y attribute \src "libresoc.v:78737.19-78737.126" wire $and$libresoc.v:78737$3634_Y attribute \src "libresoc.v:78744.18-78744.114" wire $and$libresoc.v:78744$3641_Y attribute \src "libresoc.v:78745.18-78745.116" wire $and$libresoc.v:78745$3642_Y attribute \src "libresoc.v:78747.18-78747.114" wire $and$libresoc.v:78747$3644_Y attribute \src "libresoc.v:78749.18-78749.110" wire $and$libresoc.v:78749$3646_Y attribute \src "libresoc.v:78761.18-78761.114" wire $and$libresoc.v:78761$3658_Y attribute \src "libresoc.v:78762.18-78762.116" wire $and$libresoc.v:78762$3659_Y attribute \src "libresoc.v:78764.18-78764.114" wire $and$libresoc.v:78764$3661_Y attribute \src "libresoc.v:78766.18-78766.110" wire $and$libresoc.v:78766$3663_Y attribute \src "libresoc.v:78731.19-78731.124" wire $eq$libresoc.v:78731$3628_Y attribute \src "libresoc.v:78732.19-78732.124" wire $eq$libresoc.v:78732$3629_Y attribute \src "libresoc.v:78733.19-78733.124" wire $eq$libresoc.v:78733$3630_Y attribute \src "libresoc.v:78734.19-78734.124" wire $eq$libresoc.v:78734$3631_Y attribute \src "libresoc.v:78738.19-78738.124" wire $eq$libresoc.v:78738$3635_Y attribute \src "libresoc.v:78739.18-78739.117" wire $eq$libresoc.v:78739$3636_Y attribute \src "libresoc.v:78740.18-78740.117" wire $eq$libresoc.v:78740$3637_Y attribute \src "libresoc.v:78742.18-78742.117" wire $eq$libresoc.v:78742$3639_Y attribute \src "libresoc.v:78743.18-78743.127" wire $eq$libresoc.v:78743$3640_Y attribute \src "libresoc.v:78746.18-78746.127" wire $eq$libresoc.v:78746$3643_Y attribute \src "libresoc.v:78750.18-78750.122" wire $eq$libresoc.v:78750$3647_Y attribute \src "libresoc.v:78751.18-78751.122" wire $eq$libresoc.v:78751$3648_Y attribute \src "libresoc.v:78753.18-78753.110" wire $eq$libresoc.v:78753$3650_Y attribute \src "libresoc.v:78754.18-78754.110" wire $eq$libresoc.v:78754$3651_Y attribute \src "libresoc.v:78756.18-78756.112" wire $eq$libresoc.v:78756$3653_Y attribute \src "libresoc.v:78758.18-78758.110" wire $eq$libresoc.v:78758$3655_Y attribute \src "libresoc.v:78760.18-78760.127" wire $eq$libresoc.v:78760$3657_Y attribute \src "libresoc.v:78763.18-78763.127" wire $eq$libresoc.v:78763$3660_Y attribute \src "libresoc.v:78728.19-78728.124" wire width 7 $extend$libresoc.v:78728$3622_Y attribute \src "libresoc.v:78729.19-78729.124" wire width 7 $extend$libresoc.v:78729$3624_Y attribute \src "libresoc.v:78730.19-78730.123" wire width 7 $extend$libresoc.v:78730$3626_Y attribute \src "libresoc.v:78767.18-78767.111" wire width 7 $extend$libresoc.v:78767$3664_Y attribute \src "libresoc.v:78768.18-78768.111" wire width 7 $extend$libresoc.v:78768$3666_Y attribute \src "libresoc.v:78769.18-78769.111" wire width 7 $extend$libresoc.v:78769$3668_Y attribute \src "libresoc.v:78770.18-78770.113" wire width 7 $extend$libresoc.v:78770$3670_Y attribute \src "libresoc.v:78771.18-78771.121" wire width 7 $extend$libresoc.v:78771$3672_Y attribute \src "libresoc.v:78748.18-78748.110" wire $not$libresoc.v:78748$3645_Y attribute \src "libresoc.v:78765.18-78765.110" wire $not$libresoc.v:78765$3662_Y attribute \src "libresoc.v:78741.18-78741.111" wire $or$libresoc.v:78741$3638_Y attribute \src "libresoc.v:78752.18-78752.110" wire $or$libresoc.v:78752$3649_Y attribute \src "libresoc.v:78755.18-78755.110" wire $or$libresoc.v:78755$3652_Y attribute \src "libresoc.v:78757.18-78757.110" wire $or$libresoc.v:78757$3654_Y attribute \src "libresoc.v:78759.18-78759.110" wire $or$libresoc.v:78759$3656_Y attribute \src "libresoc.v:78728.19-78728.124" wire width 7 $pos$libresoc.v:78728$3623_Y attribute \src "libresoc.v:78729.19-78729.124" wire width 7 $pos$libresoc.v:78729$3625_Y attribute \src "libresoc.v:78730.19-78730.123" wire width 7 $pos$libresoc.v:78730$3627_Y attribute \src "libresoc.v:78767.18-78767.111" wire width 7 $pos$libresoc.v:78767$3665_Y attribute \src "libresoc.v:78768.18-78768.111" wire width 7 $pos$libresoc.v:78768$3667_Y attribute \src "libresoc.v:78769.18-78769.111" wire width 7 $pos$libresoc.v:78769$3669_Y attribute \src "libresoc.v:78770.18-78770.113" wire width 7 $pos$libresoc.v:78770$3671_Y attribute \src "libresoc.v:78771.18-78771.121" wire width 7 $pos$libresoc.v:78771$3673_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" wire \$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" wire \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" wire \$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" wire \$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" wire \$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" wire \$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" wire \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 output 5 \asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 output 39 \cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 30 \cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 32 \cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 34 \cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \cr_in2_ok$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 36 \cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 59 \cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 60 \cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 61 \cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 62 \cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 input 64 \cur_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire input 66 \cur_eint attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 input 3 \cur_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 2 \cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 \dec_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 \dec_XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 \dec_XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \dec_X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 \dec_X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_a_fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_a_fast_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_a_reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_a_reg_a_ok attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire width 3 \dec_a_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec_a_spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_a_spr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" wire \dec_a_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_b_fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_b_fast_b_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec_b_reg_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_b_reg_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_c_reg_c attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_c_reg_c_ok attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_in_cr_bitfield attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_in_cr_bitfield_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_bitfield_b_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_in_cr_bitfield_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_bitfield_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_bitfield_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec_cr_in_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_in_cr_fxm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" wire width 3 \dec_cr_in_sel_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_cr_out_cr_bitfield attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_out_cr_bitfield_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec_cr_out_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_cr_out_cr_fxm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" wire width 32 \dec_cr_out_insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_cry_in attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1244" wire \dec_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_o2_fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o2_fast_o2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" wire \dec_o2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_o2_reg_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o2_reg_o2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec_o_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o_fast_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 \dec_o_reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o_reg_o_ok attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 3 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec_o_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_o_spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_out_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 8 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 9 \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 50 \exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 51 \exc_$signal$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 52 \exc_$signal$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 53 \exc_$signal$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 54 \exc_$signal$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 55 \exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 56 \exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 57 \exc_$signal$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1243" wire \ext_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 22 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 24 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 26 \fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 28 \fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 output 42 \fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246" wire \illeg_ok attribute \src "libresoc.v:77029.7-77029.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 output 48 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 output 40 \insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire width 32 \insn_in$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" wire width 32 \insn_in$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" wire width 32 \insn_in$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" wire width 32 \insn_in$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" wire width 32 \insn_in$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 output 41 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire output 63 \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" wire \is_priv_insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire output 43 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 output 38 \msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 46 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1245" wire \priv_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 4 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 44 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 10 \reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 11 \reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 12 \reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 13 \reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 14 \reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 15 \reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 6 \rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \rego_ok attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:415" wire width 3 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 18 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 19 \spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 16 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 65 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \tmp_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_in2$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_in2_ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \tmp_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_fasto2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \tmp_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_rego_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \tmp_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \tmp_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \tmp_tmp_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \tmp_tmp_cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \tmp_tmp_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \tmp_tmp_exc_$signal$27 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \tmp_tmp_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \tmp_tmp_input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \tmp_tmp_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \tmp_tmp_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \tmp_tmp_is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \tmp_tmp_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \tmp_tmp_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \tmp_tmp_rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \tmp_tmp_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \tmp_tmp_traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \tmp_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \tmp_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 output 58 \trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 output 49 \traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 output 20 \xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire output 21 \xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" cell $and $and$libresoc.v:78735$3632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] connect \Y $and$libresoc.v:78735$3632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" cell $and $and$libresoc.v:78736$3633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] connect \Y $and$libresoc.v:78736$3633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" cell $and $and$libresoc.v:78737$3634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] connect \Y $and$libresoc.v:78737$3634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:78744$3641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$37 connect \Y $and$libresoc.v:78744$3641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:78745$3642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$39 connect \B \is_mmu_spr connect \Y $and$libresoc.v:78745$3642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:78747$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$43 connect \Y $and$libresoc.v:78747$3644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:78749$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 connect \Y $and$libresoc.v:78749$3646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:78761$3658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$71 connect \Y $and$libresoc.v:78761$3658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:78762$3659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$73 connect \B \is_mmu_spr connect \Y $and$libresoc.v:78762$3659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:78764$3661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$77 connect \Y $and$libresoc.v:78764$3661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:78766$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 connect \Y $and$libresoc.v:78766$3663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" cell $eq $eq$libresoc.v:78731$3628 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:78731$3628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" cell $eq $eq$libresoc.v:78732$3629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 connect \Y $eq$libresoc.v:78732$3629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" cell $eq $eq$libresoc.v:78733$3630 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:78733$3630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" cell $eq $eq$libresoc.v:78734$3631 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 connect \Y $eq$libresoc.v:78734$3631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" cell $eq $eq$libresoc.v:78738$3635 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 connect \Y $eq$libresoc.v:78738$3635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" cell $eq $eq$libresoc.v:78739$3636 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 connect \Y $eq$libresoc.v:78739$3636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" cell $eq $eq$libresoc.v:78740$3637 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 connect \Y $eq$libresoc.v:78740$3637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" cell $eq $eq$libresoc.v:78742$3639 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 connect \Y $eq$libresoc.v:78742$3639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:78743$3640 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:78743$3640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:78746$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:78746$3643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:78750$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:78750$3647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:78751$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:78751$3648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:78753$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:78753$3650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:78754$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:78754$3651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:78756$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:78756$3653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:78758$3655 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:78758$3655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:78760$3657 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:78760$3657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:78763$3660 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:78763$3660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78728$3622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_b connect \Y $extend$libresoc.v:78728$3622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78729$3624 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_o connect \Y $extend$libresoc.v:78729$3624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78730$3626 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_out_cr_bitfield connect \Y $extend$libresoc.v:78730$3626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78767$3664 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_a_reg_a connect \Y $extend$libresoc.v:78767$3664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78768$3666 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_c_reg_c connect \Y $extend$libresoc.v:78768$3666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78769$3668 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o_reg_o connect \Y $extend$libresoc.v:78769$3668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78770$3670 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o2_reg_o2 connect \Y $extend$libresoc.v:78770$3670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:78771$3672 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield connect \Y $extend$libresoc.v:78771$3672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:78748$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:78748$3645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:78765$3662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:78765$3662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" cell $or $or$libresoc.v:78741$3638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 connect \Y $or$libresoc.v:78741$3638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:78752$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 connect \Y $or$libresoc.v:78752$3649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:78755$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$57 connect \B \$59 connect \Y $or$libresoc.v:78755$3652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:78757$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$61 connect \B \$63 connect \Y $or$libresoc.v:78757$3654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:78759$3656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$65 connect \B \$67 connect \Y $or$libresoc.v:78759$3656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78728$3623 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78728$3622_Y connect \Y $pos$libresoc.v:78728$3623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78729$3625 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78729$3624_Y connect \Y $pos$libresoc.v:78729$3625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78730$3627 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78730$3626_Y connect \Y $pos$libresoc.v:78730$3627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78767$3665 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78767$3664_Y connect \Y $pos$libresoc.v:78767$3665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78768$3667 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78768$3666_Y connect \Y $pos$libresoc.v:78768$3667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78769$3669 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78769$3668_Y connect \Y $pos$libresoc.v:78769$3669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78770$3671 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78770$3670_Y connect \Y $pos$libresoc.v:78770$3671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:78771$3673 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:78771$3672_Y connect \Y $pos$libresoc.v:78771$3673_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:78772.13-78809.4" cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC connect \BI \dec_BI connect \BO \dec_BO connect \BT \dec_BT connect \FXM \dec_FXM connect \LK \dec_LK connect \OE \dec_OE connect \RA \dec_RA connect \RB \dec_RB connect \RS \dec_RS connect \RT \dec_RT connect \Rc \dec_Rc connect \SPR \dec_SPR connect \XL_BT \dec_XL_BT connect \XL_XO \dec_XL_XO connect \X_BF \dec_X_BF connect \X_BFA \dec_X_BFA connect \asmcode \dec_asmcode connect \bigendian \bigendian connect \cr_in \dec_cr_in connect \cr_out \dec_cr_out connect \cry_in \dec_cry_in connect \function_unit \dec_function_unit connect \in1_sel \dec_in1_sel connect \in2_sel \dec_in2_sel connect \in3_sel \dec_in3_sel connect \internal_op \dec_internal_op connect \is_32b \dec_is_32b connect \lk \dec_lk connect \opcode_in \dec_opcode_in connect \out_sel \dec_out_sel connect \raw_opcode_in \raw_opcode_in connect \rc_sel \dec_rc_sel connect \upd \dec_upd end attribute \module_not_derived 1 attribute \src "libresoc.v:78810.9-78825.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA connect \RS \dec_RS connect \SPR \dec_SPR connect \XL_XO \dec_XL_XO connect \fast_a \dec_a_fast_a connect \fast_a_ok \dec_a_fast_a_ok connect \internal_op \dec_internal_op connect \reg_a \dec_a_reg_a connect \reg_a_ok \dec_a_reg_a_ok connect \sel_in \dec_a_sel_in connect \spr_a \dec_a_spr_a connect \spr_a_ok \dec_a_spr_a_ok connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:78826.9-78836.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS connect \XL_XO \dec_XL_XO connect \fast_b \dec_b_fast_b connect \fast_b_ok \dec_b_fast_b_ok connect \internal_op \dec_internal_op connect \reg_b \dec_b_reg_b connect \reg_b_ok \dec_b_reg_b_ok connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:78837.9-78843.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS connect \reg_c \dec_c_reg_c connect \reg_c_ok \dec_c_reg_c_ok connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:78844.13-78863.4" cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC connect \BI \dec_BI connect \BT \dec_BT connect \FXM \dec_FXM connect \X_BFA \dec_X_BFA connect \cr_bitfield \dec_cr_in_cr_bitfield connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok connect \cr_fxm \dec_cr_in_cr_fxm connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok connect \insn_in \dec_cr_in_insn_in connect \internal_op \dec_internal_op connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:78864.14-78876.4" cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT connect \X_BF \dec_X_BF connect \cr_bitfield \dec_cr_out_cr_bitfield connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok connect \cr_fxm \dec_cr_out_cr_fxm connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok connect \insn_in \dec_cr_out_insn_in connect \internal_op \dec_internal_op connect \rc_in \dec_cr_out_rc_in connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:78877.9-78890.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA connect \RT \dec_RT connect \SPR \dec_SPR connect \fast_o \dec_o_fast_o connect \fast_o_ok \dec_o_fast_o_ok connect \internal_op \dec_internal_op connect \reg_o \dec_o_reg_o connect \reg_o_ok \dec_o_reg_o_ok connect \sel_in \dec_o_sel_in connect \spr_o \dec_o_spr_o connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:78891.10-78900.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 connect \fast_o2_ok \dec_o2_fast_o2_ok connect \internal_op \dec_internal_op connect \lk \dec_o2_lk connect \reg_o2 \dec_o2_reg_o2 connect \reg_o2_ok \dec_o2_reg_o2_ok connect \upd \dec_upd end attribute \module_not_derived 1 attribute \src "libresoc.v:78901.16-78907.4" cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op connect \oe \dec_oe_oe connect \oe_ok \dec_oe_oe_ok connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:78908.16-78913.4" cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:77029.7-77029.20" process $proc$libresoc.v:77029$3732 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:78914.3-78928.6" process $proc$libresoc.v:78914$3674 assign { } { } assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] attribute \src "libresoc.v:78915.5-78915.29" switch \initial attribute \src "libresoc.v:78915.9-78915.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$83 \$75 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\tmp_tmp_fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\tmp_tmp_fn_unit[13:0] \dec_function_unit end sync always update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] end attribute \src "libresoc.v:78929.3-78938.6" process $proc$libresoc.v:78929$3675 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] attribute \src "libresoc.v:78930.5-78930.29" switch \initial attribute \src "libresoc.v:78930.9-78930.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\tmp_tmp_lk[0:0] \dec_LK case assign $1\tmp_tmp_lk[0:0] 1'0 end sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end attribute \src "libresoc.v:78939.3-78951.6" process $proc$libresoc.v:78939$3676 assign { } { } assign { } { } assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] attribute \src "libresoc.v:78940.5-78940.29" switch \initial attribute \src "libresoc.v:78940.9-78940.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$49 \$41 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\tmp_tmp_insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\tmp_tmp_insn_type[6:0] 7'0000000 case assign $1\tmp_tmp_insn_type[6:0] \dec_internal_op end sync always update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] end attribute \src "libresoc.v:78952.3-78967.6" process $proc$libresoc.v:78952$3677 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] attribute \src "libresoc.v:78953.5-78953.29" switch \initial attribute \src "libresoc.v:78953.9-78953.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" switch \$106 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\tmp_xer_in[2:0] 3'111 case assign $1\tmp_xer_in[2:0] 3'000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" switch \$108 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\tmp_xer_in[2:0] 3'001 case assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] end sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end attribute \src "libresoc.v:78968.3-78977.6" process $proc$libresoc.v:78968$3678 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] attribute \src "libresoc.v:78969.5-78969.29" switch \initial attribute \src "libresoc.v:78969.9-78969.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\tmp_xer_out[0:0] 1'1 case assign $1\tmp_xer_out[0:0] 1'0 end sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end attribute \src "libresoc.v:78978.3-78987.6" process $proc$libresoc.v:78978$3679 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] attribute \src "libresoc.v:78979.5-78979.29" switch \initial attribute \src "libresoc.v:78979.9-78979.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" switch \$112 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 case assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 end sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end attribute \src "libresoc.v:78988.3-79011.6" process $proc$libresoc.v:78988$3680 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] attribute \src "libresoc.v:78989.5-78989.29" switch \initial attribute \src "libresoc.v:78989.9-78989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54" switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 assign { } { } assign $1\is_priv_insn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1001011 assign { } { } assign $1\is_priv_insn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0101110 , 7'0110001 assign { } { } assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" switch \tmp_tmp_insn [20] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_priv_insn[0:0] 1'1 case assign $2\is_priv_insn[0:0] 1'0 end case assign $1\is_priv_insn[0:0] 1'0 end sync always update \is_priv_insn $0\is_priv_insn[0:0] end attribute \src "libresoc.v:79012.3-79169.6" process $proc$libresoc.v:79012$3681 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] assign $0\spr1[9:0] $1\spr1[9:0] assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] assign $0\msr[63:0] $1\msr[63:0] assign $0\ea_ok[0:0] $1\ea_ok[0:0] assign $0\ea[6:0] $1\ea[6:0] assign { } { } assign $0\cr_out[6:0] $1\cr_out[6:0] assign $0\lk[0:0] $1\lk[0:0] assign $0\cia[63:0] $1\cia[63:0] assign $0\cr_in1[6:0] $1\cr_in1[6:0] assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] assign $0\cr_in2[6:0] $1\cr_in2[6:0] assign $0\cr_in2$1[6:0]$3682 $1\cr_in2$1[6:0]$3692 assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] assign $0\cr_in2_ok$2[0:0]$3683 $1\cr_in2_ok$2[0:0]$3693 assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] assign $0\cr_rd[7:0] $1\cr_rd[7:0] assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] assign $0\cr_wr[7:0] $1\cr_wr[7:0] assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] assign $0\exc_$signal[0:0]$3684 $1\exc_$signal[0:0]$3694 assign $0\exc_$signal$3[0:0]$3685 $1\exc_$signal$3[0:0]$3695 assign $0\exc_$signal$4[0:0]$3686 $1\exc_$signal$4[0:0]$3696 assign $0\exc_$signal$5[0:0]$3687 $1\exc_$signal$5[0:0]$3697 assign $0\exc_$signal$6[0:0]$3688 $1\exc_$signal$6[0:0]$3698 assign $0\exc_$signal$7[0:0]$3689 $1\exc_$signal$7[0:0]$3699 assign $0\exc_$signal$8[0:0]$3690 $1\exc_$signal$8[0:0]$3700 assign $0\exc_$signal$9[0:0]$3691 $1\exc_$signal$9[0:0]$3701 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fn_unit[13:0] $1\fn_unit[13:0] assign $0\input_carry[1:0] $1\input_carry[1:0] assign $0\insn[31:0] $1\insn[31:0] assign $0\insn_type[6:0] $1\insn_type[6:0] assign $0\is_32bit[0:0] $1\is_32bit[0:0] assign $0\oe[0:0] $1\oe[0:0] assign $0\oe_ok[0:0] $1\oe_ok[0:0] assign $0\rc_ok[0:0] $1\rc_ok[0:0] assign $0\reg1[6:0] $1\reg1[6:0] assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] assign $0\reg2[6:0] $1\reg2[6:0] assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] assign $0\reg3[6:0] $1\reg3[6:0] assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] assign $0\rego[6:0] $1\rego[6:0] assign $0\rego_ok[0:0] $1\rego_ok[0:0] assign $0\spro[9:0] $1\spro[9:0] assign $0\spro_ok[0:0] $1\spro_ok[0:0] assign $0\trapaddr[12:0] $1\trapaddr[12:0] assign $0\traptype[7:0] $1\traptype[7:0] assign $0\xer_in[2:0] $1\xer_in[2:0] assign $0\xer_out[0:0] $1\xer_out[0:0] assign $0\fasto1[2:0] $5\fasto1[2:0] assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] assign $0\fasto2[2:0] $5\fasto2[2:0] assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] assign $0\fast1[2:0] $5\fast1[2:0] assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode attribute \src "libresoc.v:79013.5-79013.29" switch \initial attribute \src "libresoc.v:79013.9-79013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" case 5'----1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\fast1[2:0] $2\fast1[2:0] assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] assign $1\fast2[2:0] $2\fast2[2:0] assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] assign $1\rc[0:0] $2\rc[0:0] assign $1\spr1[9:0] $2\spr1[9:0] assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] assign $1\msr[63:0] $2\msr[63:0] assign $1\ea_ok[0:0] $2\ea_ok[0:0] assign $1\ea[6:0] $2\ea[6:0] assign $1\asmcode[7:0] $2\asmcode[7:0] assign $1\cr_out[6:0] $2\cr_out[6:0] assign $1\lk[0:0] $2\lk[0:0] assign $1\cia[63:0] $2\cia[63:0] assign $1\cr_in1[6:0] $2\cr_in1[6:0] assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] assign $1\cr_in2[6:0] $2\cr_in2[6:0] assign $1\cr_in2$1[6:0]$3692 $2\cr_in2$1[6:0]$3702 assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] assign $1\cr_in2_ok$2[0:0]$3693 $2\cr_in2_ok$2[0:0]$3703 assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] assign $1\cr_rd[7:0] $2\cr_rd[7:0] assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] assign $1\cr_wr[7:0] $2\cr_wr[7:0] assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] assign $1\exc_$signal[0:0]$3694 $2\exc_$signal[0:0]$3704 assign $1\exc_$signal$3[0:0]$3695 $2\exc_$signal$3[0:0]$3705 assign $1\exc_$signal$4[0:0]$3696 $2\exc_$signal$4[0:0]$3706 assign $1\exc_$signal$5[0:0]$3697 $2\exc_$signal$5[0:0]$3707 assign $1\exc_$signal$6[0:0]$3698 $2\exc_$signal$6[0:0]$3708 assign $1\exc_$signal$7[0:0]$3699 $2\exc_$signal$7[0:0]$3709 assign $1\exc_$signal$8[0:0]$3700 $2\exc_$signal$8[0:0]$3710 assign $1\exc_$signal$9[0:0]$3701 $2\exc_$signal$9[0:0]$3711 assign $1\fasto1[2:0] $2\fasto1[2:0] assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] assign $1\fasto2[2:0] $2\fasto2[2:0] assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] assign $1\fn_unit[13:0] $2\fn_unit[13:0] assign $1\input_carry[1:0] $2\input_carry[1:0] assign $1\insn[31:0] $2\insn[31:0] assign $1\insn_type[6:0] $2\insn_type[6:0] assign $1\is_32bit[0:0] $2\is_32bit[0:0] assign $1\oe[0:0] $2\oe[0:0] assign $1\oe_ok[0:0] $2\oe_ok[0:0] assign $1\rc_ok[0:0] $2\rc_ok[0:0] assign $1\reg1[6:0] $2\reg1[6:0] assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] assign $1\reg2[6:0] $2\reg2[6:0] assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] assign $1\reg3[6:0] $2\reg3[6:0] assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] assign $1\rego[6:0] $2\rego[6:0] assign $1\rego_ok[0:0] $2\rego_ok[0:0] assign $1\spro[9:0] $2\spro[9:0] assign $1\spro_ok[0:0] $2\spro_ok[0:0] assign $1\trapaddr[12:0] $2\trapaddr[12:0] assign $1\traptype[7:0] $2\traptype[7:0] assign $1\xer_in[2:0] $2\xer_in[2:0] assign $1\xer_out[0:0] $2\xer_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3711 $2\exc_$signal$8[0:0]$3710 $2\exc_$signal$7[0:0]$3709 $2\exc_$signal$6[0:0]$3708 $2\exc_$signal$5[0:0]$3707 $2\exc_$signal$4[0:0]$3706 $2\exc_$signal$3[0:0]$3705 $2\exc_$signal[0:0]$3704 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3703 $2\cr_in2$1[6:0]$3702 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $2\insn[31:0] \dec_opcode_in assign $2\insn_type[6:0] 7'0111111 assign $2\fn_unit[13:0] 14'00000010000000 assign $2\trapaddr[12:0] 13'0000001100000 assign $2\traptype[7:0] 8'00000010 assign $2\msr[63:0] \cur_msr assign $2\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\fast1[2:0] $3\fast1[2:0] assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] assign $2\fast2[2:0] $3\fast2[2:0] assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] assign $2\rc[0:0] $3\rc[0:0] assign $2\spr1[9:0] $3\spr1[9:0] assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] assign $2\msr[63:0] $3\msr[63:0] assign $2\ea_ok[0:0] $3\ea_ok[0:0] assign $2\ea[6:0] $3\ea[6:0] assign $2\asmcode[7:0] $3\asmcode[7:0] assign $2\cr_out[6:0] $3\cr_out[6:0] assign $2\lk[0:0] $3\lk[0:0] assign $2\cia[63:0] $3\cia[63:0] assign $2\cr_in1[6:0] $3\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $3\cr_in2[6:0] assign $2\cr_in2$1[6:0]$3702 $3\cr_in2$1[6:0]$3712 assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] assign $2\cr_in2_ok$2[0:0]$3703 $3\cr_in2_ok$2[0:0]$3713 assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] assign $2\cr_rd[7:0] $3\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $3\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] assign $2\exc_$signal[0:0]$3704 $3\exc_$signal[0:0]$3714 assign $2\exc_$signal$3[0:0]$3705 $3\exc_$signal$3[0:0]$3715 assign $2\exc_$signal$4[0:0]$3706 $3\exc_$signal$4[0:0]$3716 assign $2\exc_$signal$5[0:0]$3707 $3\exc_$signal$5[0:0]$3717 assign $2\exc_$signal$6[0:0]$3708 $3\exc_$signal$6[0:0]$3718 assign $2\exc_$signal$7[0:0]$3709 $3\exc_$signal$7[0:0]$3719 assign $2\exc_$signal$8[0:0]$3710 $3\exc_$signal$8[0:0]$3720 assign $2\exc_$signal$9[0:0]$3711 $3\exc_$signal$9[0:0]$3721 assign $2\fasto1[2:0] $3\fasto1[2:0] assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] assign $2\fasto2[2:0] $3\fasto2[2:0] assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] assign $2\fn_unit[13:0] $3\fn_unit[13:0] assign $2\input_carry[1:0] $3\input_carry[1:0] assign $2\insn[31:0] $3\insn[31:0] assign $2\insn_type[6:0] $3\insn_type[6:0] assign $2\is_32bit[0:0] $3\is_32bit[0:0] assign $2\oe[0:0] $3\oe[0:0] assign $2\oe_ok[0:0] $3\oe_ok[0:0] assign $2\rc_ok[0:0] $3\rc_ok[0:0] assign $2\reg1[6:0] $3\reg1[6:0] assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] assign $2\reg2[6:0] $3\reg2[6:0] assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] assign $2\reg3[6:0] $3\reg3[6:0] assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] assign $2\rego[6:0] $3\rego[6:0] assign $2\rego_ok[0:0] $3\rego_ok[0:0] assign $2\spro[9:0] $3\spro[9:0] assign $2\spro_ok[0:0] $3\spro_ok[0:0] assign $2\trapaddr[12:0] $3\trapaddr[12:0] assign $2\traptype[7:0] $3\traptype[7:0] assign $2\xer_in[2:0] $3\xer_in[2:0] assign $2\xer_out[0:0] $3\xer_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3721 $3\exc_$signal$8[0:0]$3720 $3\exc_$signal$7[0:0]$3719 $3\exc_$signal$6[0:0]$3718 $3\exc_$signal$5[0:0]$3717 $3\exc_$signal$4[0:0]$3716 $3\exc_$signal$3[0:0]$3715 $3\exc_$signal[0:0]$3714 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3713 $3\cr_in2$1[6:0]$3712 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001001000 assign $3\traptype[7:0] 8'00000010 assign $3\msr[63:0] \cur_msr assign $3\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3713 $3\cr_in2$1[6:0]$3712 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[13:0] 14'00000010000000 assign $3\trapaddr[12:0] 13'0000001000000 assign $3\traptype[7:0] 8'01000000 assign { $3\exc_$signal$9[0:0]$3721 $3\exc_$signal$8[0:0]$3720 $3\exc_$signal$7[0:0]$3719 $3\exc_$signal$6[0:0]$3718 $3\exc_$signal$5[0:0]$3717 $3\exc_$signal$4[0:0]$3716 $3\exc_$signal$3[0:0]$3715 $3\exc_$signal[0:0]$3714 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } assign $3\msr[63:0] \cur_msr assign $3\cia[63:0] \cur_pc end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\fast1[2:0] $4\fast1[2:0] assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] assign $2\fast2[2:0] $4\fast2[2:0] assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] assign $2\rc[0:0] $4\rc[0:0] assign $2\spr1[9:0] $4\spr1[9:0] assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] assign $2\msr[63:0] $4\msr[63:0] assign $2\ea_ok[0:0] $4\ea_ok[0:0] assign $2\ea[6:0] $4\ea[6:0] assign $2\asmcode[7:0] $4\asmcode[7:0] assign $2\cr_out[6:0] $4\cr_out[6:0] assign $2\lk[0:0] $4\lk[0:0] assign $2\cia[63:0] $4\cia[63:0] assign $2\cr_in1[6:0] $4\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $4\cr_in2[6:0] assign $2\cr_in2$1[6:0]$3702 $4\cr_in2$1[6:0]$3722 assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] assign $2\cr_in2_ok$2[0:0]$3703 $4\cr_in2_ok$2[0:0]$3723 assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] assign $2\cr_rd[7:0] $4\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $4\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] assign $2\exc_$signal[0:0]$3704 $4\exc_$signal[0:0]$3724 assign $2\exc_$signal$3[0:0]$3705 $4\exc_$signal$3[0:0]$3725 assign $2\exc_$signal$4[0:0]$3706 $4\exc_$signal$4[0:0]$3726 assign $2\exc_$signal$5[0:0]$3707 $4\exc_$signal$5[0:0]$3727 assign $2\exc_$signal$6[0:0]$3708 $4\exc_$signal$6[0:0]$3728 assign $2\exc_$signal$7[0:0]$3709 $4\exc_$signal$7[0:0]$3729 assign $2\exc_$signal$8[0:0]$3710 $4\exc_$signal$8[0:0]$3730 assign $2\exc_$signal$9[0:0]$3711 $4\exc_$signal$9[0:0]$3731 assign $2\fasto1[2:0] $4\fasto1[2:0] assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] assign $2\fasto2[2:0] $4\fasto2[2:0] assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] assign $2\fn_unit[13:0] $4\fn_unit[13:0] assign $2\input_carry[1:0] $4\input_carry[1:0] assign $2\insn[31:0] $4\insn[31:0] assign $2\insn_type[6:0] $4\insn_type[6:0] assign $2\is_32bit[0:0] $4\is_32bit[0:0] assign $2\oe[0:0] $4\oe[0:0] assign $2\oe_ok[0:0] $4\oe_ok[0:0] assign $2\rc_ok[0:0] $4\rc_ok[0:0] assign $2\reg1[6:0] $4\reg1[6:0] assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] assign $2\reg2[6:0] $4\reg2[6:0] assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] assign $2\reg3[6:0] $4\reg3[6:0] assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] assign $2\rego[6:0] $4\rego[6:0] assign $2\rego_ok[0:0] $4\rego_ok[0:0] assign $2\spro[9:0] $4\spro[9:0] assign $2\spro_ok[0:0] $4\spro_ok[0:0] assign $2\trapaddr[12:0] $4\trapaddr[12:0] assign $2\traptype[7:0] $4\traptype[7:0] assign $2\xer_in[2:0] $4\xer_in[2:0] assign $2\xer_out[0:0] $4\xer_out[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3731 $4\exc_$signal$8[0:0]$3730 $4\exc_$signal$7[0:0]$3729 $4\exc_$signal$6[0:0]$3728 $4\exc_$signal$5[0:0]$3727 $4\exc_$signal$4[0:0]$3726 $4\exc_$signal$3[0:0]$3725 $4\exc_$signal[0:0]$3724 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3723 $4\cr_in2$1[6:0]$3722 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 assign $4\trapaddr[12:0] 13'0000000111000 assign $4\traptype[7:0] 8'00000010 assign $4\msr[63:0] \cur_msr assign $4\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3731 $4\exc_$signal$8[0:0]$3730 $4\exc_$signal$7[0:0]$3729 $4\exc_$signal$6[0:0]$3728 $4\exc_$signal$5[0:0]$3727 $4\exc_$signal$4[0:0]$3726 $4\exc_$signal$3[0:0]$3725 $4\exc_$signal[0:0]$3724 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3723 $4\cr_in2$1[6:0]$3722 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[13:0] 14'00000010000000 assign $4\trapaddr[12:0] 13'0000000110000 assign $4\traptype[7:0] 8'00000010 assign $4\msr[63:0] \cur_msr assign $4\cia[63:0] \cur_pc end end attribute \src "libresoc.v:0.0-0.0" case 5'---1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000010010000 assign $1\traptype[7:0] 8'00100000 assign $1\msr[63:0] \cur_msr assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case 5'--1-- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001010000 assign $1\traptype[7:0] 8'00010000 assign $1\msr[63:0] \cur_msr assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case 5'-1--- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001110000 assign $1\traptype[7:0] 8'00000010 assign $1\msr[63:0] \cur_msr assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case 5'1---- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[13:0] 14'00000010000000 assign $1\trapaddr[12:0] 13'0000001110000 assign $1\traptype[7:0] 8'10000000 assign $1\msr[63:0] \cur_msr assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3701 $1\exc_$signal$8[0:0]$3700 $1\exc_$signal$7[0:0]$3699 $1\exc_$signal$6[0:0]$3698 $1\exc_$signal$5[0:0]$3697 $1\exc_$signal$4[0:0]$3696 $1\exc_$signal$3[0:0]$3695 $1\exc_$signal[0:0]$3694 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[13:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3693 $1\cr_in2$1[6:0]$3692 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $5\fasto1[2:0] 3'011 assign $5\fasto1_ok[0:0] 1'1 assign $5\fasto2[2:0] 3'100 assign $5\fasto2_ok[0:0] 1'1 case assign $5\fasto1[2:0] $1\fasto1[2:0] assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] assign $5\fasto2[2:0] $1\fasto2[2:0] assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $5\fast1[2:0] 3'011 assign $5\fast1_ok[0:0] 1'1 assign $5\fast2[2:0] 3'100 assign $5\fast2_ok[0:0] 1'1 case assign $5\fast1[2:0] $1\fast1[2:0] assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] assign $5\fast2[2:0] $1\fast2[2:0] assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] end sync always update \fast1 $0\fast1[2:0] update \fast1_ok $0\fast1_ok[0:0] update \fast2 $0\fast2[2:0] update \fast2_ok $0\fast2_ok[0:0] update \rc $0\rc[0:0] update \spr1 $0\spr1[9:0] update \spr1_ok $0\spr1_ok[0:0] update \msr $0\msr[63:0] update \ea_ok $0\ea_ok[0:0] update \ea $0\ea[6:0] update \asmcode $0\asmcode[7:0] update \cr_out $0\cr_out[6:0] update \lk $0\lk[0:0] update \cia $0\cia[63:0] update \cr_in1 $0\cr_in1[6:0] update \cr_in1_ok $0\cr_in1_ok[0:0] update \cr_in2 $0\cr_in2[6:0] update \cr_in2$1 $0\cr_in2$1[6:0]$3682 update \cr_in2_ok $0\cr_in2_ok[0:0] update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3683 update \cr_out_ok $0\cr_out_ok[0:0] update \cr_rd $0\cr_rd[7:0] update \cr_rd_ok $0\cr_rd_ok[0:0] update \cr_wr $0\cr_wr[7:0] update \cr_wr_ok $0\cr_wr_ok[0:0] update \exc_$signal $0\exc_$signal[0:0]$3684 update \exc_$signal$3 $0\exc_$signal$3[0:0]$3685 update \exc_$signal$4 $0\exc_$signal$4[0:0]$3686 update \exc_$signal$5 $0\exc_$signal$5[0:0]$3687 update \exc_$signal$6 $0\exc_$signal$6[0:0]$3688 update \exc_$signal$7 $0\exc_$signal$7[0:0]$3689 update \exc_$signal$8 $0\exc_$signal$8[0:0]$3690 update \exc_$signal$9 $0\exc_$signal$9[0:0]$3691 update \fasto1 $0\fasto1[2:0] update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] update \fasto2_ok $0\fasto2_ok[0:0] update \fn_unit $0\fn_unit[13:0] update \input_carry $0\input_carry[1:0] update \insn $0\insn[31:0] update \insn_type $0\insn_type[6:0] update \is_32bit $0\is_32bit[0:0] update \oe $0\oe[0:0] update \oe_ok $0\oe_ok[0:0] update \rc_ok $0\rc_ok[0:0] update \reg1 $0\reg1[6:0] update \reg1_ok $0\reg1_ok[0:0] update \reg2 $0\reg2[6:0] update \reg2_ok $0\reg2_ok[0:0] update \reg3 $0\reg3[6:0] update \reg3_ok $0\reg3_ok[0:0] update \rego $0\rego[6:0] update \rego_ok $0\rego_ok[0:0] update \spro $0\spro[9:0] update \spro_ok $0\spro_ok[0:0] update \trapaddr $0\trapaddr[12:0] update \traptype $0\traptype[7:0] update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end connect \$100 $pos$libresoc.v:78728$3623_Y connect \$102 $pos$libresoc.v:78729$3625_Y connect \$104 $pos$libresoc.v:78730$3627_Y connect \$106 $eq$libresoc.v:78731$3628_Y connect \$108 $eq$libresoc.v:78732$3629_Y connect \$110 $eq$libresoc.v:78733$3630_Y connect \$112 $eq$libresoc.v:78734$3631_Y connect \$114 $and$libresoc.v:78735$3632_Y connect \$116 $and$libresoc.v:78736$3633_Y connect \$118 $and$libresoc.v:78737$3634_Y connect \$120 $eq$libresoc.v:78738$3635_Y connect \$28 $eq$libresoc.v:78739$3636_Y connect \$30 $eq$libresoc.v:78740$3637_Y connect \$32 $or$libresoc.v:78741$3638_Y connect \$34 $eq$libresoc.v:78742$3639_Y connect \$37 $eq$libresoc.v:78743$3640_Y connect \$39 $and$libresoc.v:78744$3641_Y connect \$41 $and$libresoc.v:78745$3642_Y connect \$43 $eq$libresoc.v:78746$3643_Y connect \$45 $and$libresoc.v:78747$3644_Y connect \$47 $not$libresoc.v:78748$3645_Y connect \$49 $and$libresoc.v:78749$3646_Y connect \$51 $eq$libresoc.v:78750$3647_Y connect \$53 $eq$libresoc.v:78751$3648_Y connect \$55 $or$libresoc.v:78752$3649_Y connect \$57 $eq$libresoc.v:78753$3650_Y connect \$59 $eq$libresoc.v:78754$3651_Y connect \$61 $or$libresoc.v:78755$3652_Y connect \$63 $eq$libresoc.v:78756$3653_Y connect \$65 $or$libresoc.v:78757$3654_Y connect \$67 $eq$libresoc.v:78758$3655_Y connect \$69 $or$libresoc.v:78759$3656_Y connect \$71 $eq$libresoc.v:78760$3657_Y connect \$73 $and$libresoc.v:78761$3658_Y connect \$75 $and$libresoc.v:78762$3659_Y connect \$77 $eq$libresoc.v:78763$3660_Y connect \$79 $and$libresoc.v:78764$3661_Y connect \$81 $not$libresoc.v:78765$3662_Y connect \$83 $and$libresoc.v:78766$3663_Y connect \$90 $pos$libresoc.v:78767$3665_Y connect \$92 $pos$libresoc.v:78768$3667_Y connect \$94 $pos$libresoc.v:78769$3669_Y connect \$96 $pos$libresoc.v:78770$3671_Y connect \$98 $pos$libresoc.v:78771$3673_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 connect \dec2_exc_$signal$14 1'0 connect \dec2_exc_$signal$15 1'0 connect \dec2_exc_$signal$16 1'0 connect \dec2_exc_$signal$17 1'0 connect \dec2_exc_$signal$18 1'0 connect \tmp_asmcode 8'00000000 connect \tmp_tmp_traptype 8'00000000 connect \tmp_tmp_exc_$signal 1'0 connect \tmp_tmp_exc_$signal$21 1'0 connect \tmp_tmp_exc_$signal$22 1'0 connect \tmp_tmp_exc_$signal$23 1'0 connect \tmp_tmp_exc_$signal$24 1'0 connect \tmp_tmp_exc_$signal$25 1'0 connect \tmp_tmp_exc_$signal$26 1'0 connect \tmp_tmp_exc_$signal$27 1'0 connect \illeg_ok \$120 connect \priv_ok \$118 connect \dec_irq_ok \$116 connect \ext_irq_ok \$114 connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o2_ok \dec_o2_fast_o2 } connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } connect \tmp_cr_out_ok \dec_cr_out_cr_bitfield_ok connect \tmp_cr_out \$104 connect \tmp_cr_in2_ok$20 \dec_cr_in_cr_bitfield_o_ok connect \tmp_cr_in2$19 \$102 connect \tmp_cr_in2_ok \dec_cr_in_cr_bitfield_b_ok connect \tmp_cr_in2 \$100 connect \tmp_cr_in1_ok \dec_cr_in_cr_bitfield_ok connect \tmp_cr_in1 \$98 connect \tmp_ea_ok \dec_o2_reg_o2_ok connect \tmp_ea \$96 connect \tmp_rego_ok \dec_o_reg_o_ok connect \tmp_rego \$94 connect \tmp_reg3_ok \dec_c_reg_c_ok connect \tmp_reg3 \$92 connect \tmp_reg2_ok \dec_b_reg_b_ok connect \tmp_reg2 \dec_b_reg_b connect \tmp_reg1_ok \dec_a_reg_a_ok connect \tmp_reg1 \$90 connect \dec_o2_lk \tmp_tmp_lk connect \sel_in \dec_out_sel connect \dec_o_sel_in \dec_out_sel connect \dec_c_sel_in \dec_in3_sel connect \dec_b_sel_in \dec_in2_sel connect \dec_a_sel_in \dec_in1_sel connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_cr_out connect \dec_cr_in_sel_in \dec_cr_in connect \insn_in$89 \dec_opcode_in connect \insn_in$88 \dec_opcode_in connect \insn_in$87 \dec_opcode_in connect \dec_cr_out_insn_in \dec_opcode_in connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$86 \dec_opcode_in connect \insn_in$85 \dec_opcode_in connect \tmp_tmp_insn \dec_opcode_in connect \dec_a_sv_nz \sv_a_nz connect \tmp_tmp_is_32bit \dec_is_32b connect \tmp_tmp_input_carry \dec_cry_in connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } connect \is_mmu_spr \$69 connect \is_spr_mv \$55 connect \spr { \dec_SPR [4:0] \dec_SPR [9:5] } connect \tmp_tmp_cia \cur_pc connect \tmp_tmp_msr \cur_msr connect \dec_oe_sel_in \dec_rc_sel connect \dec_rc_sel_in \dec_rc_sel connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end attribute \src "libresoc.v:79253.1-79933.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" attribute \generator "nMigen" module \dec22 attribute \src "libresoc.v:79872.3-79881.6" wire width 2 $0\dec22_SV_Etype[1:0] attribute \src "libresoc.v:79882.3-79891.6" wire width 2 $0\dec22_SV_Ptype[1:0] attribute \src "libresoc.v:79752.3-79761.6" wire width 8 $0\dec22_asmcode[7:0] attribute \src "libresoc.v:79792.3-79801.6" wire $0\dec22_br[0:0] attribute \src "libresoc.v:79612.3-79621.6" wire width 3 $0\dec22_cr_in[2:0] attribute \src "libresoc.v:79622.3-79631.6" wire width 3 $0\dec22_cr_out[2:0] attribute \src "libresoc.v:79742.3-79751.6" wire width 2 $0\dec22_cry_in[1:0] attribute \src "libresoc.v:79782.3-79791.6" wire $0\dec22_cry_out[0:0] attribute \src "libresoc.v:79822.3-79831.6" wire width 5 $0\dec22_form[4:0] attribute \src "libresoc.v:79602.3-79611.6" wire width 14 $0\dec22_function_unit[13:0] attribute \src "libresoc.v:79892.3-79901.6" wire width 3 $0\dec22_in1_sel[2:0] attribute \src "libresoc.v:79902.3-79911.6" wire width 4 $0\dec22_in2_sel[3:0] attribute \src "libresoc.v:79912.3-79921.6" wire width 2 $0\dec22_in3_sel[1:0] attribute \src "libresoc.v:79712.3-79721.6" wire width 7 $0\dec22_internal_op[6:0] attribute \src "libresoc.v:79762.3-79771.6" wire $0\dec22_inv_a[0:0] attribute \src "libresoc.v:79772.3-79781.6" wire $0\dec22_inv_out[0:0] attribute \src "libresoc.v:79832.3-79841.6" wire $0\dec22_is_32b[0:0] attribute \src "libresoc.v:79702.3-79711.6" wire width 4 $0\dec22_ldst_len[3:0] attribute \src "libresoc.v:79852.3-79861.6" wire $0\dec22_lk[0:0] attribute \src "libresoc.v:79922.3-79931.6" wire width 3 $0\dec22_out_sel[2:0] attribute \src "libresoc.v:79732.3-79741.6" wire width 2 $0\dec22_rc_sel[1:0] attribute \src "libresoc.v:79812.3-79821.6" wire $0\dec22_rsrv[0:0] attribute \src "libresoc.v:79862.3-79871.6" wire $0\dec22_sgl_pipe[0:0] attribute \src "libresoc.v:79842.3-79851.6" wire $0\dec22_sgn[0:0] attribute \src "libresoc.v:79802.3-79811.6" wire $0\dec22_sgn_ext[0:0] attribute \src "libresoc.v:79682.3-79691.6" wire width 3 $0\dec22_sv_cr_in[2:0] attribute \src "libresoc.v:79692.3-79701.6" wire width 3 $0\dec22_sv_cr_out[2:0] attribute \src "libresoc.v:79632.3-79641.6" wire width 3 $0\dec22_sv_in1[2:0] attribute \src "libresoc.v:79642.3-79651.6" wire width 3 $0\dec22_sv_in2[2:0] attribute \src "libresoc.v:79652.3-79661.6" wire width 3 $0\dec22_sv_in3[2:0] attribute \src "libresoc.v:79672.3-79681.6" wire width 3 $0\dec22_sv_out2[2:0] attribute \src "libresoc.v:79662.3-79671.6" wire width 3 $0\dec22_sv_out[2:0] attribute \src "libresoc.v:79722.3-79731.6" wire width 2 $0\dec22_upd[1:0] attribute \src "libresoc.v:79254.7-79254.20" wire $0\initial[0:0] attribute \src "libresoc.v:79872.3-79881.6" wire width 2 $1\dec22_SV_Etype[1:0] attribute \src "libresoc.v:79882.3-79891.6" wire width 2 $1\dec22_SV_Ptype[1:0] attribute \src "libresoc.v:79752.3-79761.6" wire width 8 $1\dec22_asmcode[7:0] attribute \src "libresoc.v:79792.3-79801.6" wire $1\dec22_br[0:0] attribute \src "libresoc.v:79612.3-79621.6" wire width 3 $1\dec22_cr_in[2:0] attribute \src "libresoc.v:79622.3-79631.6" wire width 3 $1\dec22_cr_out[2:0] attribute \src "libresoc.v:79742.3-79751.6" wire width 2 $1\dec22_cry_in[1:0] attribute \src "libresoc.v:79782.3-79791.6" wire $1\dec22_cry_out[0:0] attribute \src "libresoc.v:79822.3-79831.6" wire width 5 $1\dec22_form[4:0] attribute \src "libresoc.v:79602.3-79611.6" wire width 14 $1\dec22_function_unit[13:0] attribute \src "libresoc.v:79892.3-79901.6" wire width 3 $1\dec22_in1_sel[2:0] attribute \src "libresoc.v:79902.3-79911.6" wire width 4 $1\dec22_in2_sel[3:0] attribute \src "libresoc.v:79912.3-79921.6" wire width 2 $1\dec22_in3_sel[1:0] attribute \src "libresoc.v:79712.3-79721.6" wire width 7 $1\dec22_internal_op[6:0] attribute \src "libresoc.v:79762.3-79771.6" wire $1\dec22_inv_a[0:0] attribute \src "libresoc.v:79772.3-79781.6" wire $1\dec22_inv_out[0:0] attribute \src "libresoc.v:79832.3-79841.6" wire $1\dec22_is_32b[0:0] attribute \src "libresoc.v:79702.3-79711.6" wire width 4 $1\dec22_ldst_len[3:0] attribute \src "libresoc.v:79852.3-79861.6" wire $1\dec22_lk[0:0] attribute \src "libresoc.v:79922.3-79931.6" wire width 3 $1\dec22_out_sel[2:0] attribute \src "libresoc.v:79732.3-79741.6" wire width 2 $1\dec22_rc_sel[1:0] attribute \src "libresoc.v:79812.3-79821.6" wire $1\dec22_rsrv[0:0] attribute \src "libresoc.v:79862.3-79871.6" wire $1\dec22_sgl_pipe[0:0] attribute \src "libresoc.v:79842.3-79851.6" wire $1\dec22_sgn[0:0] attribute \src "libresoc.v:79802.3-79811.6" wire $1\dec22_sgn_ext[0:0] attribute \src "libresoc.v:79682.3-79691.6" wire width 3 $1\dec22_sv_cr_in[2:0] attribute \src "libresoc.v:79692.3-79701.6" wire width 3 $1\dec22_sv_cr_out[2:0] attribute \src "libresoc.v:79632.3-79641.6" wire width 3 $1\dec22_sv_in1[2:0] attribute \src "libresoc.v:79642.3-79651.6" wire width 3 $1\dec22_sv_in2[2:0] attribute \src "libresoc.v:79652.3-79661.6" wire width 3 $1\dec22_sv_in3[2:0] attribute \src "libresoc.v:79672.3-79681.6" wire width 3 $1\dec22_sv_out2[2:0] attribute \src "libresoc.v:79662.3-79671.6" wire width 3 $1\dec22_sv_out[2:0] attribute \src "libresoc.v:79722.3-79731.6" wire width 2 $1\dec22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec22_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec22_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec22_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec22_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec22_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec22_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec22_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec22_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec22_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec22_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec22_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec22_upd attribute \src "libresoc.v:79254.7-79254.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch attribute \src "libresoc.v:79254.7-79254.20" process $proc$libresoc.v:79254$3766 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:79602.3-79611.6" process $proc$libresoc.v:79602$3733 assign { } { } assign { } { } assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] attribute \src "libresoc.v:79603.5-79603.29" switch \initial attribute \src "libresoc.v:79603.9-79603.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_function_unit[13:0] 14'10000000000000 case assign $1\dec22_function_unit[13:0] 14'00000000000000 end sync always update \dec22_function_unit $0\dec22_function_unit[13:0] end attribute \src "libresoc.v:79612.3-79621.6" process $proc$libresoc.v:79612$3734 assign { } { } assign { } { } assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] attribute \src "libresoc.v:79613.5-79613.29" switch \initial attribute \src "libresoc.v:79613.9-79613.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_cr_in[2:0] 3'000 case assign $1\dec22_cr_in[2:0] 3'000 end sync always update \dec22_cr_in $0\dec22_cr_in[2:0] end attribute \src "libresoc.v:79622.3-79631.6" process $proc$libresoc.v:79622$3735 assign { } { } assign { } { } assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] attribute \src "libresoc.v:79623.5-79623.29" switch \initial attribute \src "libresoc.v:79623.9-79623.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_cr_out[2:0] 3'001 case assign $1\dec22_cr_out[2:0] 3'000 end sync always update \dec22_cr_out $0\dec22_cr_out[2:0] end attribute \src "libresoc.v:79632.3-79641.6" process $proc$libresoc.v:79632$3736 assign { } { } assign { } { } assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] attribute \src "libresoc.v:79633.5-79633.29" switch \initial attribute \src "libresoc.v:79633.9-79633.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sv_in1[2:0] 3'000 case assign $1\dec22_sv_in1[2:0] 3'000 end sync always update \dec22_sv_in1 $0\dec22_sv_in1[2:0] end attribute \src "libresoc.v:79642.3-79651.6" process $proc$libresoc.v:79642$3737 assign { } { } assign { } { } assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] attribute \src "libresoc.v:79643.5-79643.29" switch \initial attribute \src "libresoc.v:79643.9-79643.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sv_in2[2:0] 3'000 case assign $1\dec22_sv_in2[2:0] 3'000 end sync always update \dec22_sv_in2 $0\dec22_sv_in2[2:0] end attribute \src "libresoc.v:79652.3-79661.6" process $proc$libresoc.v:79652$3738 assign { } { } assign { } { } assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] attribute \src "libresoc.v:79653.5-79653.29" switch \initial attribute \src "libresoc.v:79653.9-79653.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sv_in3[2:0] 3'000 case assign $1\dec22_sv_in3[2:0] 3'000 end sync always update \dec22_sv_in3 $0\dec22_sv_in3[2:0] end attribute \src "libresoc.v:79662.3-79671.6" process $proc$libresoc.v:79662$3739 assign { } { } assign { } { } assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] attribute \src "libresoc.v:79663.5-79663.29" switch \initial attribute \src "libresoc.v:79663.9-79663.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sv_out[2:0] 3'000 case assign $1\dec22_sv_out[2:0] 3'000 end sync always update \dec22_sv_out $0\dec22_sv_out[2:0] end attribute \src "libresoc.v:79672.3-79681.6" process $proc$libresoc.v:79672$3740 assign { } { } assign { } { } assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0] attribute \src "libresoc.v:79673.5-79673.29" switch \initial attribute \src "libresoc.v:79673.9-79673.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sv_out2[2:0] 3'000 case assign $1\dec22_sv_out2[2:0] 3'000 end sync always update \dec22_sv_out2 $0\dec22_sv_out2[2:0] end attribute \src "libresoc.v:79682.3-79691.6" process $proc$libresoc.v:79682$3741 assign { } { } assign { } { } assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] attribute \src "libresoc.v:79683.5-79683.29" switch \initial attribute \src "libresoc.v:79683.9-79683.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sv_cr_in[2:0] 3'000 case assign $1\dec22_sv_cr_in[2:0] 3'000 end sync always update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] end attribute \src "libresoc.v:79692.3-79701.6" process $proc$libresoc.v:79692$3742 assign { } { } assign { } { } assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] attribute \src "libresoc.v:79693.5-79693.29" switch \initial attribute \src "libresoc.v:79693.9-79693.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sv_cr_out[2:0] 3'000 case assign $1\dec22_sv_cr_out[2:0] 3'000 end sync always update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] end attribute \src "libresoc.v:79702.3-79711.6" process $proc$libresoc.v:79702$3743 assign { } { } assign { } { } assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] attribute \src "libresoc.v:79703.5-79703.29" switch \initial attribute \src "libresoc.v:79703.9-79703.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_ldst_len[3:0] 4'0000 case assign $1\dec22_ldst_len[3:0] 4'0000 end sync always update \dec22_ldst_len $0\dec22_ldst_len[3:0] end attribute \src "libresoc.v:79712.3-79721.6" process $proc$libresoc.v:79712$3744 assign { } { } assign { } { } assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] attribute \src "libresoc.v:79713.5-79713.29" switch \initial attribute \src "libresoc.v:79713.9-79713.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_internal_op[6:0] 7'1001100 case assign $1\dec22_internal_op[6:0] 7'0000000 end sync always update \dec22_internal_op $0\dec22_internal_op[6:0] end attribute \src "libresoc.v:79722.3-79731.6" process $proc$libresoc.v:79722$3745 assign { } { } assign { } { } assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] attribute \src "libresoc.v:79723.5-79723.29" switch \initial attribute \src "libresoc.v:79723.9-79723.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_upd[1:0] 2'00 case assign $1\dec22_upd[1:0] 2'00 end sync always update \dec22_upd $0\dec22_upd[1:0] end attribute \src "libresoc.v:79732.3-79741.6" process $proc$libresoc.v:79732$3746 assign { } { } assign { } { } assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] attribute \src "libresoc.v:79733.5-79733.29" switch \initial attribute \src "libresoc.v:79733.9-79733.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_rc_sel[1:0] 2'10 case assign $1\dec22_rc_sel[1:0] 2'00 end sync always update \dec22_rc_sel $0\dec22_rc_sel[1:0] end attribute \src "libresoc.v:79742.3-79751.6" process $proc$libresoc.v:79742$3747 assign { } { } assign { } { } assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] attribute \src "libresoc.v:79743.5-79743.29" switch \initial attribute \src "libresoc.v:79743.9-79743.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_cry_in[1:0] 2'00 case assign $1\dec22_cry_in[1:0] 2'00 end sync always update \dec22_cry_in $0\dec22_cry_in[1:0] end attribute \src "libresoc.v:79752.3-79761.6" process $proc$libresoc.v:79752$3748 assign { } { } assign { } { } assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] attribute \src "libresoc.v:79753.5-79753.29" switch \initial attribute \src "libresoc.v:79753.9-79753.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_asmcode[7:0] 8'10011100 case assign $1\dec22_asmcode[7:0] 8'00000000 end sync always update \dec22_asmcode $0\dec22_asmcode[7:0] end attribute \src "libresoc.v:79762.3-79771.6" process $proc$libresoc.v:79762$3749 assign { } { } assign { } { } assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] attribute \src "libresoc.v:79763.5-79763.29" switch \initial attribute \src "libresoc.v:79763.9-79763.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_inv_a[0:0] 1'0 case assign $1\dec22_inv_a[0:0] 1'0 end sync always update \dec22_inv_a $0\dec22_inv_a[0:0] end attribute \src "libresoc.v:79772.3-79781.6" process $proc$libresoc.v:79772$3750 assign { } { } assign { } { } assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] attribute \src "libresoc.v:79773.5-79773.29" switch \initial attribute \src "libresoc.v:79773.9-79773.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_inv_out[0:0] 1'0 case assign $1\dec22_inv_out[0:0] 1'0 end sync always update \dec22_inv_out $0\dec22_inv_out[0:0] end attribute \src "libresoc.v:79782.3-79791.6" process $proc$libresoc.v:79782$3751 assign { } { } assign { } { } assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] attribute \src "libresoc.v:79783.5-79783.29" switch \initial attribute \src "libresoc.v:79783.9-79783.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_cry_out[0:0] 1'0 case assign $1\dec22_cry_out[0:0] 1'0 end sync always update \dec22_cry_out $0\dec22_cry_out[0:0] end attribute \src "libresoc.v:79792.3-79801.6" process $proc$libresoc.v:79792$3752 assign { } { } assign { } { } assign $0\dec22_br[0:0] $1\dec22_br[0:0] attribute \src "libresoc.v:79793.5-79793.29" switch \initial attribute \src "libresoc.v:79793.9-79793.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_br[0:0] 1'0 case assign $1\dec22_br[0:0] 1'0 end sync always update \dec22_br $0\dec22_br[0:0] end attribute \src "libresoc.v:79802.3-79811.6" process $proc$libresoc.v:79802$3753 assign { } { } assign { } { } assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] attribute \src "libresoc.v:79803.5-79803.29" switch \initial attribute \src "libresoc.v:79803.9-79803.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sgn_ext[0:0] 1'0 case assign $1\dec22_sgn_ext[0:0] 1'0 end sync always update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] end attribute \src "libresoc.v:79812.3-79821.6" process $proc$libresoc.v:79812$3754 assign { } { } assign { } { } assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] attribute \src "libresoc.v:79813.5-79813.29" switch \initial attribute \src "libresoc.v:79813.9-79813.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_rsrv[0:0] 1'0 case assign $1\dec22_rsrv[0:0] 1'0 end sync always update \dec22_rsrv $0\dec22_rsrv[0:0] end attribute \src "libresoc.v:79822.3-79831.6" process $proc$libresoc.v:79822$3755 assign { } { } assign { } { } assign $0\dec22_form[4:0] $1\dec22_form[4:0] attribute \src "libresoc.v:79823.5-79823.29" switch \initial attribute \src "libresoc.v:79823.9-79823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_form[4:0] 5'11101 case assign $1\dec22_form[4:0] 5'00000 end sync always update \dec22_form $0\dec22_form[4:0] end attribute \src "libresoc.v:79832.3-79841.6" process $proc$libresoc.v:79832$3756 assign { } { } assign { } { } assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] attribute \src "libresoc.v:79833.5-79833.29" switch \initial attribute \src "libresoc.v:79833.9-79833.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_is_32b[0:0] 1'0 case assign $1\dec22_is_32b[0:0] 1'0 end sync always update \dec22_is_32b $0\dec22_is_32b[0:0] end attribute \src "libresoc.v:79842.3-79851.6" process $proc$libresoc.v:79842$3757 assign { } { } assign { } { } assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] attribute \src "libresoc.v:79843.5-79843.29" switch \initial attribute \src "libresoc.v:79843.9-79843.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sgn[0:0] 1'0 case assign $1\dec22_sgn[0:0] 1'0 end sync always update \dec22_sgn $0\dec22_sgn[0:0] end attribute \src "libresoc.v:79852.3-79861.6" process $proc$libresoc.v:79852$3758 assign { } { } assign { } { } assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] attribute \src "libresoc.v:79853.5-79853.29" switch \initial attribute \src "libresoc.v:79853.9-79853.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_lk[0:0] 1'0 case assign $1\dec22_lk[0:0] 1'0 end sync always update \dec22_lk $0\dec22_lk[0:0] end attribute \src "libresoc.v:79862.3-79871.6" process $proc$libresoc.v:79862$3759 assign { } { } assign { } { } assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] attribute \src "libresoc.v:79863.5-79863.29" switch \initial attribute \src "libresoc.v:79863.9-79863.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_sgl_pipe[0:0] 1'0 case assign $1\dec22_sgl_pipe[0:0] 1'0 end sync always update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] end attribute \src "libresoc.v:79872.3-79881.6" process $proc$libresoc.v:79872$3760 assign { } { } assign { } { } assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] attribute \src "libresoc.v:79873.5-79873.29" switch \initial attribute \src "libresoc.v:79873.9-79873.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_SV_Etype[1:0] 2'00 case assign $1\dec22_SV_Etype[1:0] 2'00 end sync always update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] end attribute \src "libresoc.v:79882.3-79891.6" process $proc$libresoc.v:79882$3761 assign { } { } assign { } { } assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] attribute \src "libresoc.v:79883.5-79883.29" switch \initial attribute \src "libresoc.v:79883.9-79883.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_SV_Ptype[1:0] 2'00 case assign $1\dec22_SV_Ptype[1:0] 2'00 end sync always update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] end attribute \src "libresoc.v:79892.3-79901.6" process $proc$libresoc.v:79892$3762 assign { } { } assign { } { } assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] attribute \src "libresoc.v:79893.5-79893.29" switch \initial attribute \src "libresoc.v:79893.9-79893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_in1_sel[2:0] 3'010 case assign $1\dec22_in1_sel[2:0] 3'000 end sync always update \dec22_in1_sel $0\dec22_in1_sel[2:0] end attribute \src "libresoc.v:79902.3-79911.6" process $proc$libresoc.v:79902$3763 assign { } { } assign { } { } assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] attribute \src "libresoc.v:79903.5-79903.29" switch \initial attribute \src "libresoc.v:79903.9-79903.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_in2_sel[3:0] 4'0000 case assign $1\dec22_in2_sel[3:0] 4'0000 end sync always update \dec22_in2_sel $0\dec22_in2_sel[3:0] end attribute \src "libresoc.v:79912.3-79921.6" process $proc$libresoc.v:79912$3764 assign { } { } assign { } { } assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] attribute \src "libresoc.v:79913.5-79913.29" switch \initial attribute \src "libresoc.v:79913.9-79913.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_in3_sel[1:0] 2'00 case assign $1\dec22_in3_sel[1:0] 2'00 end sync always update \dec22_in3_sel $0\dec22_in3_sel[1:0] end attribute \src "libresoc.v:79922.3-79931.6" process $proc$libresoc.v:79922$3765 assign { } { } assign { } { } assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] attribute \src "libresoc.v:79923.5-79923.29" switch \initial attribute \src "libresoc.v:79923.9-79923.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec22_out_sel[2:0] 3'100 case assign $1\dec22_out_sel[2:0] 3'000 end sync always update \dec22_out_sel $0\dec22_out_sel[2:0] end connect \opcode_switch \opcode_in [4:1] end attribute \src "libresoc.v:79937.1-81508.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 attribute \src "libresoc.v:81285.3-81321.6" wire width 2 $0\dec30_SV_Etype[1:0] attribute \src "libresoc.v:81322.3-81358.6" wire width 2 $0\dec30_SV_Ptype[1:0] attribute \src "libresoc.v:80841.3-80877.6" wire width 8 $0\dec30_asmcode[7:0] attribute \src "libresoc.v:80989.3-81025.6" wire $0\dec30_br[0:0] attribute \src "libresoc.v:80323.3-80359.6" wire width 3 $0\dec30_cr_in[2:0] attribute \src "libresoc.v:80360.3-80396.6" wire width 3 $0\dec30_cr_out[2:0] attribute \src "libresoc.v:80804.3-80840.6" wire width 2 $0\dec30_cry_in[1:0] attribute \src "libresoc.v:80952.3-80988.6" wire $0\dec30_cry_out[0:0] attribute \src "libresoc.v:81100.3-81136.6" wire width 5 $0\dec30_form[4:0] attribute \src "libresoc.v:80286.3-80322.6" wire width 14 $0\dec30_function_unit[13:0] attribute \src "libresoc.v:81359.3-81395.6" wire width 3 $0\dec30_in1_sel[2:0] attribute \src "libresoc.v:81396.3-81432.6" wire width 4 $0\dec30_in2_sel[3:0] attribute \src "libresoc.v:81433.3-81469.6" wire width 2 $0\dec30_in3_sel[1:0] attribute \src "libresoc.v:80693.3-80729.6" wire width 7 $0\dec30_internal_op[6:0] attribute \src "libresoc.v:80878.3-80914.6" wire $0\dec30_inv_a[0:0] attribute \src "libresoc.v:80915.3-80951.6" wire $0\dec30_inv_out[0:0] attribute \src "libresoc.v:81137.3-81173.6" wire $0\dec30_is_32b[0:0] attribute \src "libresoc.v:80656.3-80692.6" wire width 4 $0\dec30_ldst_len[3:0] attribute \src "libresoc.v:81211.3-81247.6" wire $0\dec30_lk[0:0] attribute \src "libresoc.v:81470.3-81506.6" wire width 3 $0\dec30_out_sel[2:0] attribute \src "libresoc.v:80767.3-80803.6" wire width 2 $0\dec30_rc_sel[1:0] attribute \src "libresoc.v:81063.3-81099.6" wire $0\dec30_rsrv[0:0] attribute \src "libresoc.v:81248.3-81284.6" wire $0\dec30_sgl_pipe[0:0] attribute \src "libresoc.v:81174.3-81210.6" wire $0\dec30_sgn[0:0] attribute \src "libresoc.v:81026.3-81062.6" wire $0\dec30_sgn_ext[0:0] attribute \src "libresoc.v:80582.3-80618.6" wire width 3 $0\dec30_sv_cr_in[2:0] attribute \src "libresoc.v:80619.3-80655.6" wire width 3 $0\dec30_sv_cr_out[2:0] attribute \src "libresoc.v:80397.3-80433.6" wire width 3 $0\dec30_sv_in1[2:0] attribute \src "libresoc.v:80434.3-80470.6" wire width 3 $0\dec30_sv_in2[2:0] attribute \src "libresoc.v:80471.3-80507.6" wire width 3 $0\dec30_sv_in3[2:0] attribute \src "libresoc.v:80545.3-80581.6" wire width 3 $0\dec30_sv_out2[2:0] attribute \src "libresoc.v:80508.3-80544.6" wire width 3 $0\dec30_sv_out[2:0] attribute \src "libresoc.v:80730.3-80766.6" wire width 2 $0\dec30_upd[1:0] attribute \src "libresoc.v:79938.7-79938.20" wire $0\initial[0:0] attribute \src "libresoc.v:81285.3-81321.6" wire width 2 $1\dec30_SV_Etype[1:0] attribute \src "libresoc.v:81322.3-81358.6" wire width 2 $1\dec30_SV_Ptype[1:0] attribute \src "libresoc.v:80841.3-80877.6" wire width 8 $1\dec30_asmcode[7:0] attribute \src "libresoc.v:80989.3-81025.6" wire $1\dec30_br[0:0] attribute \src "libresoc.v:80323.3-80359.6" wire width 3 $1\dec30_cr_in[2:0] attribute \src "libresoc.v:80360.3-80396.6" wire width 3 $1\dec30_cr_out[2:0] attribute \src "libresoc.v:80804.3-80840.6" wire width 2 $1\dec30_cry_in[1:0] attribute \src "libresoc.v:80952.3-80988.6" wire $1\dec30_cry_out[0:0] attribute \src "libresoc.v:81100.3-81136.6" wire width 5 $1\dec30_form[4:0] attribute \src "libresoc.v:80286.3-80322.6" wire width 14 $1\dec30_function_unit[13:0] attribute \src "libresoc.v:81359.3-81395.6" wire width 3 $1\dec30_in1_sel[2:0] attribute \src "libresoc.v:81396.3-81432.6" wire width 4 $1\dec30_in2_sel[3:0] attribute \src "libresoc.v:81433.3-81469.6" wire width 2 $1\dec30_in3_sel[1:0] attribute \src "libresoc.v:80693.3-80729.6" wire width 7 $1\dec30_internal_op[6:0] attribute \src "libresoc.v:80878.3-80914.6" wire $1\dec30_inv_a[0:0] attribute \src "libresoc.v:80915.3-80951.6" wire $1\dec30_inv_out[0:0] attribute \src "libresoc.v:81137.3-81173.6" wire $1\dec30_is_32b[0:0] attribute \src "libresoc.v:80656.3-80692.6" wire width 4 $1\dec30_ldst_len[3:0] attribute \src "libresoc.v:81211.3-81247.6" wire $1\dec30_lk[0:0] attribute \src "libresoc.v:81470.3-81506.6" wire width 3 $1\dec30_out_sel[2:0] attribute \src "libresoc.v:80767.3-80803.6" wire width 2 $1\dec30_rc_sel[1:0] attribute \src "libresoc.v:81063.3-81099.6" wire $1\dec30_rsrv[0:0] attribute \src "libresoc.v:81248.3-81284.6" wire $1\dec30_sgl_pipe[0:0] attribute \src "libresoc.v:81174.3-81210.6" wire $1\dec30_sgn[0:0] attribute \src "libresoc.v:81026.3-81062.6" wire $1\dec30_sgn_ext[0:0] attribute \src "libresoc.v:80582.3-80618.6" wire width 3 $1\dec30_sv_cr_in[2:0] attribute \src "libresoc.v:80619.3-80655.6" wire width 3 $1\dec30_sv_cr_out[2:0] attribute \src "libresoc.v:80397.3-80433.6" wire width 3 $1\dec30_sv_in1[2:0] attribute \src "libresoc.v:80434.3-80470.6" wire width 3 $1\dec30_sv_in2[2:0] attribute \src "libresoc.v:80471.3-80507.6" wire width 3 $1\dec30_sv_in3[2:0] attribute \src "libresoc.v:80545.3-80581.6" wire width 3 $1\dec30_sv_out2[2:0] attribute \src "libresoc.v:80508.3-80544.6" wire width 3 $1\dec30_sv_out[2:0] attribute \src "libresoc.v:80730.3-80766.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec30_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec30_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec30_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec30_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec30_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec30_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec30_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec30_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec30_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec30_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec30_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec30_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec30_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec30_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec30_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec30_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec30_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec30_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec30_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec30_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec30_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec30_upd attribute \src "libresoc.v:79938.7-79938.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch attribute \src "libresoc.v:79938.7-79938.20" process $proc$libresoc.v:79938$3800 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:80286.3-80322.6" process $proc$libresoc.v:80286$3767 assign { } { } assign { } { } assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] attribute \src "libresoc.v:80287.5-80287.29" switch \initial attribute \src "libresoc.v:80287.9-80287.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_function_unit[13:0] 14'00000000001000 case assign $1\dec30_function_unit[13:0] 14'00000000000000 end sync always update \dec30_function_unit $0\dec30_function_unit[13:0] end attribute \src "libresoc.v:80323.3-80359.6" process $proc$libresoc.v:80323$3768 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] attribute \src "libresoc.v:80324.5-80324.29" switch \initial attribute \src "libresoc.v:80324.9-80324.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_cr_in[2:0] 3'000 case assign $1\dec30_cr_in[2:0] 3'000 end sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end attribute \src "libresoc.v:80360.3-80396.6" process $proc$libresoc.v:80360$3769 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] attribute \src "libresoc.v:80361.5-80361.29" switch \initial attribute \src "libresoc.v:80361.9-80361.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_cr_out[2:0] 3'001 case assign $1\dec30_cr_out[2:0] 3'000 end sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end attribute \src "libresoc.v:80397.3-80433.6" process $proc$libresoc.v:80397$3770 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] attribute \src "libresoc.v:80398.5-80398.29" switch \initial attribute \src "libresoc.v:80398.9-80398.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sv_in1[2:0] 3'000 case assign $1\dec30_sv_in1[2:0] 3'000 end sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end attribute \src "libresoc.v:80434.3-80470.6" process $proc$libresoc.v:80434$3771 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] attribute \src "libresoc.v:80435.5-80435.29" switch \initial attribute \src "libresoc.v:80435.9-80435.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sv_in2[2:0] 3'010 case assign $1\dec30_sv_in2[2:0] 3'000 end sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end attribute \src "libresoc.v:80471.3-80507.6" process $proc$libresoc.v:80471$3772 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] attribute \src "libresoc.v:80472.5-80472.29" switch \initial attribute \src "libresoc.v:80472.9-80472.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sv_in3[2:0] 3'011 case assign $1\dec30_sv_in3[2:0] 3'000 end sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end attribute \src "libresoc.v:80508.3-80544.6" process $proc$libresoc.v:80508$3773 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] attribute \src "libresoc.v:80509.5-80509.29" switch \initial attribute \src "libresoc.v:80509.9-80509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sv_out[2:0] 3'001 case assign $1\dec30_sv_out[2:0] 3'000 end sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end attribute \src "libresoc.v:80545.3-80581.6" process $proc$libresoc.v:80545$3774 assign { } { } assign { } { } assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0] attribute \src "libresoc.v:80546.5-80546.29" switch \initial attribute \src "libresoc.v:80546.9-80546.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sv_out2[2:0] 3'000 case assign $1\dec30_sv_out2[2:0] 3'000 end sync always update \dec30_sv_out2 $0\dec30_sv_out2[2:0] end attribute \src "libresoc.v:80582.3-80618.6" process $proc$libresoc.v:80582$3775 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] attribute \src "libresoc.v:80583.5-80583.29" switch \initial attribute \src "libresoc.v:80583.9-80583.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sv_cr_in[2:0] 3'000 case assign $1\dec30_sv_cr_in[2:0] 3'000 end sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end attribute \src "libresoc.v:80619.3-80655.6" process $proc$libresoc.v:80619$3776 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] attribute \src "libresoc.v:80620.5-80620.29" switch \initial attribute \src "libresoc.v:80620.9-80620.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sv_cr_out[2:0] 3'001 case assign $1\dec30_sv_cr_out[2:0] 3'000 end sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end attribute \src "libresoc.v:80656.3-80692.6" process $proc$libresoc.v:80656$3777 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] attribute \src "libresoc.v:80657.5-80657.29" switch \initial attribute \src "libresoc.v:80657.9-80657.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_ldst_len[3:0] 4'0000 case assign $1\dec30_ldst_len[3:0] 4'0000 end sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end attribute \src "libresoc.v:80693.3-80729.6" process $proc$libresoc.v:80693$3778 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] attribute \src "libresoc.v:80694.5-80694.29" switch \initial attribute \src "libresoc.v:80694.9-80694.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_internal_op[6:0] 7'0111010 case assign $1\dec30_internal_op[6:0] 7'0000000 end sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end attribute \src "libresoc.v:80730.3-80766.6" process $proc$libresoc.v:80730$3779 assign { } { } assign { } { } assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] attribute \src "libresoc.v:80731.5-80731.29" switch \initial attribute \src "libresoc.v:80731.9-80731.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_upd[1:0] 2'00 case assign $1\dec30_upd[1:0] 2'00 end sync always update \dec30_upd $0\dec30_upd[1:0] end attribute \src "libresoc.v:80767.3-80803.6" process $proc$libresoc.v:80767$3780 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] attribute \src "libresoc.v:80768.5-80768.29" switch \initial attribute \src "libresoc.v:80768.9-80768.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_rc_sel[1:0] 2'10 case assign $1\dec30_rc_sel[1:0] 2'00 end sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end attribute \src "libresoc.v:80804.3-80840.6" process $proc$libresoc.v:80804$3781 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] attribute \src "libresoc.v:80805.5-80805.29" switch \initial attribute \src "libresoc.v:80805.9-80805.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_cry_in[1:0] 2'00 case assign $1\dec30_cry_in[1:0] 2'00 end sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end attribute \src "libresoc.v:80841.3-80877.6" process $proc$libresoc.v:80841$3782 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] attribute \src "libresoc.v:80842.5-80842.29" switch \initial attribute \src "libresoc.v:80842.9-80842.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010100 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010100 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010101 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010101 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010110 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010110 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010111 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010111 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010010 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_asmcode[7:0] 8'10010011 case assign $1\dec30_asmcode[7:0] 8'00000000 end sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end attribute \src "libresoc.v:80878.3-80914.6" process $proc$libresoc.v:80878$3783 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] attribute \src "libresoc.v:80879.5-80879.29" switch \initial attribute \src "libresoc.v:80879.9-80879.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_inv_a[0:0] 1'0 case assign $1\dec30_inv_a[0:0] 1'0 end sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end attribute \src "libresoc.v:80915.3-80951.6" process $proc$libresoc.v:80915$3784 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] attribute \src "libresoc.v:80916.5-80916.29" switch \initial attribute \src "libresoc.v:80916.9-80916.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_inv_out[0:0] 1'0 case assign $1\dec30_inv_out[0:0] 1'0 end sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end attribute \src "libresoc.v:80952.3-80988.6" process $proc$libresoc.v:80952$3785 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] attribute \src "libresoc.v:80953.5-80953.29" switch \initial attribute \src "libresoc.v:80953.9-80953.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_cry_out[0:0] 1'0 case assign $1\dec30_cry_out[0:0] 1'0 end sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end attribute \src "libresoc.v:80989.3-81025.6" process $proc$libresoc.v:80989$3786 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] attribute \src "libresoc.v:80990.5-80990.29" switch \initial attribute \src "libresoc.v:80990.9-80990.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_br[0:0] 1'0 case assign $1\dec30_br[0:0] 1'0 end sync always update \dec30_br $0\dec30_br[0:0] end attribute \src "libresoc.v:81026.3-81062.6" process $proc$libresoc.v:81026$3787 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] attribute \src "libresoc.v:81027.5-81027.29" switch \initial attribute \src "libresoc.v:81027.9-81027.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sgn_ext[0:0] 1'0 case assign $1\dec30_sgn_ext[0:0] 1'0 end sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end attribute \src "libresoc.v:81063.3-81099.6" process $proc$libresoc.v:81063$3788 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] attribute \src "libresoc.v:81064.5-81064.29" switch \initial attribute \src "libresoc.v:81064.9-81064.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_rsrv[0:0] 1'0 case assign $1\dec30_rsrv[0:0] 1'0 end sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end attribute \src "libresoc.v:81100.3-81136.6" process $proc$libresoc.v:81100$3789 assign { } { } assign { } { } assign $0\dec30_form[4:0] $1\dec30_form[4:0] attribute \src "libresoc.v:81101.5-81101.29" switch \initial attribute \src "libresoc.v:81101.9-81101.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_form[4:0] 5'10101 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_form[4:0] 5'10100 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_form[4:0] 5'10100 case assign $1\dec30_form[4:0] 5'00000 end sync always update \dec30_form $0\dec30_form[4:0] end attribute \src "libresoc.v:81137.3-81173.6" process $proc$libresoc.v:81137$3790 assign { } { } assign { } { } assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] attribute \src "libresoc.v:81138.5-81138.29" switch \initial attribute \src "libresoc.v:81138.9-81138.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_is_32b[0:0] 1'0 case assign $1\dec30_is_32b[0:0] 1'0 end sync always update \dec30_is_32b $0\dec30_is_32b[0:0] end attribute \src "libresoc.v:81174.3-81210.6" process $proc$libresoc.v:81174$3791 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] attribute \src "libresoc.v:81175.5-81175.29" switch \initial attribute \src "libresoc.v:81175.9-81175.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sgn[0:0] 1'0 case assign $1\dec30_sgn[0:0] 1'0 end sync always update \dec30_sgn $0\dec30_sgn[0:0] end attribute \src "libresoc.v:81211.3-81247.6" process $proc$libresoc.v:81211$3792 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] attribute \src "libresoc.v:81212.5-81212.29" switch \initial attribute \src "libresoc.v:81212.9-81212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_lk[0:0] 1'0 case assign $1\dec30_lk[0:0] 1'0 end sync always update \dec30_lk $0\dec30_lk[0:0] end attribute \src "libresoc.v:81248.3-81284.6" process $proc$libresoc.v:81248$3793 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] attribute \src "libresoc.v:81249.5-81249.29" switch \initial attribute \src "libresoc.v:81249.9-81249.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_sgl_pipe[0:0] 1'0 case assign $1\dec30_sgl_pipe[0:0] 1'0 end sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end attribute \src "libresoc.v:81285.3-81321.6" process $proc$libresoc.v:81285$3794 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] attribute \src "libresoc.v:81286.5-81286.29" switch \initial attribute \src "libresoc.v:81286.9-81286.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_SV_Etype[1:0] 2'10 case assign $1\dec30_SV_Etype[1:0] 2'00 end sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end attribute \src "libresoc.v:81322.3-81358.6" process $proc$libresoc.v:81322$3795 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] attribute \src "libresoc.v:81323.5-81323.29" switch \initial attribute \src "libresoc.v:81323.9-81323.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_SV_Ptype[1:0] 2'01 case assign $1\dec30_SV_Ptype[1:0] 2'00 end sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end attribute \src "libresoc.v:81359.3-81395.6" process $proc$libresoc.v:81359$3796 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] attribute \src "libresoc.v:81360.5-81360.29" switch \initial attribute \src "libresoc.v:81360.9-81360.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_in1_sel[2:0] 3'000 case assign $1\dec30_in1_sel[2:0] 3'000 end sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end attribute \src "libresoc.v:81396.3-81432.6" process $proc$libresoc.v:81396$3797 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] attribute \src "libresoc.v:81397.5-81397.29" switch \initial attribute \src "libresoc.v:81397.9-81397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_in2_sel[3:0] 4'0001 case assign $1\dec30_in2_sel[3:0] 4'0000 end sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end attribute \src "libresoc.v:81433.3-81469.6" process $proc$libresoc.v:81433$3798 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] attribute \src "libresoc.v:81434.5-81434.29" switch \initial attribute \src "libresoc.v:81434.9-81434.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_in3_sel[1:0] 2'01 case assign $1\dec30_in3_sel[1:0] 2'00 end sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end attribute \src "libresoc.v:81470.3-81506.6" process $proc$libresoc.v:81470$3799 assign { } { } assign { } { } assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] attribute \src "libresoc.v:81471.5-81471.29" switch \initial attribute \src "libresoc.v:81471.9-81471.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\dec30_out_sel[2:0] 3'010 case assign $1\dec30_out_sel[2:0] 3'000 end sync always update \dec30_out_sel $0\dec30_out_sel[2:0] end connect \opcode_switch \opcode_in [4:1] end attribute \src "libresoc.v:81512.1-90160.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 attribute \src "libresoc.v:88371.3-88431.6" wire width 2 $0\dec31_SV_Etype[1:0] attribute \src "libresoc.v:88432.3-88492.6" wire width 2 $0\dec31_SV_Ptype[1:0] attribute \src "libresoc.v:88310.3-88370.6" wire width 8 $0\dec31_asmcode[7:0] attribute \src "libresoc.v:89713.3-89773.6" wire $0\dec31_br[0:0] attribute \src "libresoc.v:88737.3-88797.6" wire width 3 $0\dec31_cr_in[2:0] attribute \src "libresoc.v:88798.3-88858.6" wire width 3 $0\dec31_cr_out[2:0] attribute \src "libresoc.v:89469.3-89529.6" wire width 2 $0\dec31_cry_in[1:0] attribute \src "libresoc.v:89652.3-89712.6" wire $0\dec31_cry_out[0:0] attribute \src "libresoc.v:88249.3-88309.6" wire width 5 $0\dec31_form[4:0] attribute \src "libresoc.v:88127.3-88187.6" wire width 14 $0\dec31_function_unit[13:0] attribute \src "libresoc.v:88493.3-88553.6" wire width 3 $0\dec31_in1_sel[2:0] attribute \src "libresoc.v:88554.3-88614.6" wire width 4 $0\dec31_in2_sel[3:0] attribute \src "libresoc.v:88615.3-88675.6" wire width 2 $0\dec31_in3_sel[1:0] attribute \src "libresoc.v:88188.3-88248.6" wire width 7 $0\dec31_internal_op[6:0] attribute \src "libresoc.v:89530.3-89590.6" wire $0\dec31_inv_a[0:0] attribute \src "libresoc.v:89591.3-89651.6" wire $0\dec31_inv_out[0:0] attribute \src "libresoc.v:89896.3-89956.6" wire $0\dec31_is_32b[0:0] attribute \src "libresoc.v:89286.3-89346.6" wire width 4 $0\dec31_ldst_len[3:0] attribute \src "libresoc.v:90018.3-90078.6" wire $0\dec31_lk[0:0] attribute \src "libresoc.v:88676.3-88736.6" wire width 3 $0\dec31_out_sel[2:0] attribute \src "libresoc.v:89408.3-89468.6" wire width 2 $0\dec31_rc_sel[1:0] attribute \src "libresoc.v:89835.3-89895.6" wire $0\dec31_rsrv[0:0] attribute \src "libresoc.v:90079.3-90139.6" wire $0\dec31_sgl_pipe[0:0] attribute \src "libresoc.v:89957.3-90017.6" wire $0\dec31_sgn[0:0] attribute \src "libresoc.v:89774.3-89834.6" wire $0\dec31_sgn_ext[0:0] attribute \src "libresoc.v:89164.3-89224.6" wire width 3 $0\dec31_sv_cr_in[2:0] attribute \src "libresoc.v:89225.3-89285.6" wire width 3 $0\dec31_sv_cr_out[2:0] attribute \src "libresoc.v:88859.3-88919.6" wire width 3 $0\dec31_sv_in1[2:0] attribute \src "libresoc.v:88920.3-88980.6" wire width 3 $0\dec31_sv_in2[2:0] attribute \src "libresoc.v:88981.3-89041.6" wire width 3 $0\dec31_sv_in3[2:0] attribute \src "libresoc.v:89103.3-89163.6" wire width 3 $0\dec31_sv_out2[2:0] attribute \src "libresoc.v:89042.3-89102.6" wire width 3 $0\dec31_sv_out[2:0] attribute \src "libresoc.v:89347.3-89407.6" wire width 2 $0\dec31_upd[1:0] attribute \src "libresoc.v:81513.7-81513.20" wire $0\initial[0:0] attribute \src "libresoc.v:88371.3-88431.6" wire width 2 $1\dec31_SV_Etype[1:0] attribute \src "libresoc.v:88432.3-88492.6" wire width 2 $1\dec31_SV_Ptype[1:0] attribute \src "libresoc.v:88310.3-88370.6" wire width 8 $1\dec31_asmcode[7:0] attribute \src "libresoc.v:89713.3-89773.6" wire $1\dec31_br[0:0] attribute \src "libresoc.v:88737.3-88797.6" wire width 3 $1\dec31_cr_in[2:0] attribute \src "libresoc.v:88798.3-88858.6" wire width 3 $1\dec31_cr_out[2:0] attribute \src "libresoc.v:89469.3-89529.6" wire width 2 $1\dec31_cry_in[1:0] attribute \src "libresoc.v:89652.3-89712.6" wire $1\dec31_cry_out[0:0] attribute \src "libresoc.v:88249.3-88309.6" wire width 5 $1\dec31_form[4:0] attribute \src "libresoc.v:88127.3-88187.6" wire width 14 $1\dec31_function_unit[13:0] attribute \src "libresoc.v:88493.3-88553.6" wire width 3 $1\dec31_in1_sel[2:0] attribute \src "libresoc.v:88554.3-88614.6" wire width 4 $1\dec31_in2_sel[3:0] attribute \src "libresoc.v:88615.3-88675.6" wire width 2 $1\dec31_in3_sel[1:0] attribute \src "libresoc.v:88188.3-88248.6" wire width 7 $1\dec31_internal_op[6:0] attribute \src "libresoc.v:89530.3-89590.6" wire $1\dec31_inv_a[0:0] attribute \src "libresoc.v:89591.3-89651.6" wire $1\dec31_inv_out[0:0] attribute \src "libresoc.v:89896.3-89956.6" wire $1\dec31_is_32b[0:0] attribute \src "libresoc.v:89286.3-89346.6" wire width 4 $1\dec31_ldst_len[3:0] attribute \src "libresoc.v:90018.3-90078.6" wire $1\dec31_lk[0:0] attribute \src "libresoc.v:88676.3-88736.6" wire width 3 $1\dec31_out_sel[2:0] attribute \src "libresoc.v:89408.3-89468.6" wire width 2 $1\dec31_rc_sel[1:0] attribute \src "libresoc.v:89835.3-89895.6" wire $1\dec31_rsrv[0:0] attribute \src "libresoc.v:90079.3-90139.6" wire $1\dec31_sgl_pipe[0:0] attribute \src "libresoc.v:89957.3-90017.6" wire $1\dec31_sgn[0:0] attribute \src "libresoc.v:89774.3-89834.6" wire $1\dec31_sgn_ext[0:0] attribute \src "libresoc.v:89164.3-89224.6" wire width 3 $1\dec31_sv_cr_in[2:0] attribute \src "libresoc.v:89225.3-89285.6" wire width 3 $1\dec31_sv_cr_out[2:0] attribute \src "libresoc.v:88859.3-88919.6" wire width 3 $1\dec31_sv_in1[2:0] attribute \src "libresoc.v:88920.3-88980.6" wire width 3 $1\dec31_sv_in2[2:0] attribute \src "libresoc.v:88981.3-89041.6" wire width 3 $1\dec31_sv_in3[2:0] attribute \src "libresoc.v:89103.3-89163.6" wire width 3 $1\dec31_sv_out2[2:0] attribute \src "libresoc.v:89042.3-89102.6" wire width 3 $1\dec31_sv_out[2:0] attribute \src "libresoc.v:89347.3-89407.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_cry_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec31_dec_sub0_dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 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attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec31_dec_sub9_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute 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\enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_upd attribute \src "libresoc.v:81513.7-81513.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:87479.18-87514.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext connect \dec31_dec_sub0_sv_cr_in \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in connect \dec31_dec_sub0_sv_cr_out \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out connect \dec31_dec_sub0_sv_in1 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 connect \dec31_dec_sub0_sv_in2 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 connect \dec31_dec_sub0_sv_in3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 connect \dec31_dec_sub0_sv_out \dec31_dec_sub0_dec31_dec_sub0_sv_out connect \dec31_dec_sub0_sv_out2 \dec31_dec_sub0_dec31_dec_sub0_sv_out2 connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87515.19-87550.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext connect \dec31_dec_sub10_sv_cr_in \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in connect \dec31_dec_sub10_sv_cr_out \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out connect \dec31_dec_sub10_sv_in1 \dec31_dec_sub10_dec31_dec_sub10_sv_in1 connect \dec31_dec_sub10_sv_in2 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 connect \dec31_dec_sub10_sv_in3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 connect \dec31_dec_sub10_sv_out \dec31_dec_sub10_dec31_dec_sub10_sv_out connect \dec31_dec_sub10_sv_out2 \dec31_dec_sub10_dec31_dec_sub10_sv_out2 connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87551.19-87586.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext connect \dec31_dec_sub11_sv_cr_in \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in connect \dec31_dec_sub11_sv_cr_out \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out connect \dec31_dec_sub11_sv_in1 \dec31_dec_sub11_dec31_dec_sub11_sv_in1 connect \dec31_dec_sub11_sv_in2 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 connect \dec31_dec_sub11_sv_in3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 connect \dec31_dec_sub11_sv_out \dec31_dec_sub11_dec31_dec_sub11_sv_out connect \dec31_dec_sub11_sv_out2 \dec31_dec_sub11_dec31_dec_sub11_sv_out2 connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87587.19-87622.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext connect \dec31_dec_sub15_sv_cr_in \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in connect \dec31_dec_sub15_sv_cr_out \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out connect \dec31_dec_sub15_sv_in1 \dec31_dec_sub15_dec31_dec_sub15_sv_in1 connect \dec31_dec_sub15_sv_in2 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 connect \dec31_dec_sub15_sv_in3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 connect \dec31_dec_sub15_sv_out \dec31_dec_sub15_dec31_dec_sub15_sv_out connect \dec31_dec_sub15_sv_out2 \dec31_dec_sub15_dec31_dec_sub15_sv_out2 connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87623.19-87658.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext connect \dec31_dec_sub16_sv_cr_in \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in connect \dec31_dec_sub16_sv_cr_out \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out connect \dec31_dec_sub16_sv_in1 \dec31_dec_sub16_dec31_dec_sub16_sv_in1 connect \dec31_dec_sub16_sv_in2 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 connect \dec31_dec_sub16_sv_in3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 connect \dec31_dec_sub16_sv_out \dec31_dec_sub16_dec31_dec_sub16_sv_out connect \dec31_dec_sub16_sv_out2 \dec31_dec_sub16_dec31_dec_sub16_sv_out2 connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87659.19-87694.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext connect \dec31_dec_sub18_sv_cr_in \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in connect \dec31_dec_sub18_sv_cr_out \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out connect \dec31_dec_sub18_sv_in1 \dec31_dec_sub18_dec31_dec_sub18_sv_in1 connect \dec31_dec_sub18_sv_in2 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 connect \dec31_dec_sub18_sv_in3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 connect \dec31_dec_sub18_sv_out \dec31_dec_sub18_dec31_dec_sub18_sv_out connect \dec31_dec_sub18_sv_out2 \dec31_dec_sub18_dec31_dec_sub18_sv_out2 connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87695.19-87730.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext connect \dec31_dec_sub19_sv_cr_in \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in connect \dec31_dec_sub19_sv_cr_out \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out connect \dec31_dec_sub19_sv_in1 \dec31_dec_sub19_dec31_dec_sub19_sv_in1 connect \dec31_dec_sub19_sv_in2 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 connect \dec31_dec_sub19_sv_in3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 connect \dec31_dec_sub19_sv_out \dec31_dec_sub19_dec31_dec_sub19_sv_out connect \dec31_dec_sub19_sv_out2 \dec31_dec_sub19_dec31_dec_sub19_sv_out2 connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87731.19-87766.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext connect \dec31_dec_sub20_sv_cr_in \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in connect \dec31_dec_sub20_sv_cr_out \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out connect \dec31_dec_sub20_sv_in1 \dec31_dec_sub20_dec31_dec_sub20_sv_in1 connect \dec31_dec_sub20_sv_in2 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 connect \dec31_dec_sub20_sv_in3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 connect \dec31_dec_sub20_sv_out \dec31_dec_sub20_dec31_dec_sub20_sv_out connect \dec31_dec_sub20_sv_out2 \dec31_dec_sub20_dec31_dec_sub20_sv_out2 connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87767.19-87802.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext connect \dec31_dec_sub21_sv_cr_in \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in connect \dec31_dec_sub21_sv_cr_out \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out connect \dec31_dec_sub21_sv_in1 \dec31_dec_sub21_dec31_dec_sub21_sv_in1 connect \dec31_dec_sub21_sv_in2 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 connect \dec31_dec_sub21_sv_in3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 connect \dec31_dec_sub21_sv_out \dec31_dec_sub21_dec31_dec_sub21_sv_out connect \dec31_dec_sub21_sv_out2 \dec31_dec_sub21_dec31_dec_sub21_sv_out2 connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87803.19-87838.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext connect \dec31_dec_sub22_sv_cr_in \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in connect \dec31_dec_sub22_sv_cr_out \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out connect \dec31_dec_sub22_sv_in1 \dec31_dec_sub22_dec31_dec_sub22_sv_in1 connect \dec31_dec_sub22_sv_in2 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 connect \dec31_dec_sub22_sv_in3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 connect \dec31_dec_sub22_sv_out \dec31_dec_sub22_dec31_dec_sub22_sv_out connect \dec31_dec_sub22_sv_out2 \dec31_dec_sub22_dec31_dec_sub22_sv_out2 connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87839.19-87874.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext connect \dec31_dec_sub23_sv_cr_in \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in connect \dec31_dec_sub23_sv_cr_out \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out connect \dec31_dec_sub23_sv_in1 \dec31_dec_sub23_dec31_dec_sub23_sv_in1 connect \dec31_dec_sub23_sv_in2 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 connect \dec31_dec_sub23_sv_in3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 connect \dec31_dec_sub23_sv_out \dec31_dec_sub23_dec31_dec_sub23_sv_out connect \dec31_dec_sub23_sv_out2 \dec31_dec_sub23_dec31_dec_sub23_sv_out2 connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87875.19-87910.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext connect \dec31_dec_sub24_sv_cr_in \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in connect \dec31_dec_sub24_sv_cr_out \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out connect \dec31_dec_sub24_sv_in1 \dec31_dec_sub24_dec31_dec_sub24_sv_in1 connect \dec31_dec_sub24_sv_in2 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 connect \dec31_dec_sub24_sv_in3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 connect \dec31_dec_sub24_sv_out \dec31_dec_sub24_dec31_dec_sub24_sv_out connect \dec31_dec_sub24_sv_out2 \dec31_dec_sub24_dec31_dec_sub24_sv_out2 connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87911.19-87946.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext connect \dec31_dec_sub26_sv_cr_in \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in connect \dec31_dec_sub26_sv_cr_out \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out connect \dec31_dec_sub26_sv_in1 \dec31_dec_sub26_dec31_dec_sub26_sv_in1 connect \dec31_dec_sub26_sv_in2 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 connect \dec31_dec_sub26_sv_in3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 connect \dec31_dec_sub26_sv_out \dec31_dec_sub26_dec31_dec_sub26_sv_out connect \dec31_dec_sub26_sv_out2 \dec31_dec_sub26_dec31_dec_sub26_sv_out2 connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87947.19-87982.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext connect \dec31_dec_sub27_sv_cr_in \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in connect \dec31_dec_sub27_sv_cr_out \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out connect \dec31_dec_sub27_sv_in1 \dec31_dec_sub27_dec31_dec_sub27_sv_in1 connect \dec31_dec_sub27_sv_in2 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 connect \dec31_dec_sub27_sv_in3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 connect \dec31_dec_sub27_sv_out \dec31_dec_sub27_dec31_dec_sub27_sv_out connect \dec31_dec_sub27_sv_out2 \dec31_dec_sub27_dec31_dec_sub27_sv_out2 connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:87983.19-88018.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext connect \dec31_dec_sub28_sv_cr_in \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in connect \dec31_dec_sub28_sv_cr_out \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out connect \dec31_dec_sub28_sv_in1 \dec31_dec_sub28_dec31_dec_sub28_sv_in1 connect \dec31_dec_sub28_sv_in2 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 connect \dec31_dec_sub28_sv_in3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 connect \dec31_dec_sub28_sv_out \dec31_dec_sub28_dec31_dec_sub28_sv_out connect \dec31_dec_sub28_sv_out2 \dec31_dec_sub28_dec31_dec_sub28_sv_out2 connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:88019.18-88054.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext connect \dec31_dec_sub4_sv_cr_in \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in connect \dec31_dec_sub4_sv_cr_out \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out connect \dec31_dec_sub4_sv_in1 \dec31_dec_sub4_dec31_dec_sub4_sv_in1 connect \dec31_dec_sub4_sv_in2 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 connect \dec31_dec_sub4_sv_in3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 connect \dec31_dec_sub4_sv_out \dec31_dec_sub4_dec31_dec_sub4_sv_out connect \dec31_dec_sub4_sv_out2 \dec31_dec_sub4_dec31_dec_sub4_sv_out2 connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:88055.18-88090.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext connect \dec31_dec_sub8_sv_cr_in \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in connect \dec31_dec_sub8_sv_cr_out \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out connect \dec31_dec_sub8_sv_in1 \dec31_dec_sub8_dec31_dec_sub8_sv_in1 connect \dec31_dec_sub8_sv_in2 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 connect \dec31_dec_sub8_sv_in3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 connect \dec31_dec_sub8_sv_out \dec31_dec_sub8_dec31_dec_sub8_sv_out connect \dec31_dec_sub8_sv_out2 \dec31_dec_sub8_dec31_dec_sub8_sv_out2 connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:88091.18-88126.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext connect \dec31_dec_sub9_sv_cr_in \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in connect \dec31_dec_sub9_sv_cr_out \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out connect \dec31_dec_sub9_sv_in1 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 connect \dec31_dec_sub9_sv_in2 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 connect \dec31_dec_sub9_sv_in3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 connect \dec31_dec_sub9_sv_out \dec31_dec_sub9_dec31_dec_sub9_sv_out connect \dec31_dec_sub9_sv_out2 \dec31_dec_sub9_dec31_dec_sub9_sv_out2 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end attribute \src "libresoc.v:81513.7-81513.20" process $proc$libresoc.v:81513$3834 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:88127.3-88187.6" process $proc$libresoc.v:88127$3801 assign { } { } assign { } { } assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] attribute \src "libresoc.v:88128.5-88128.29" switch \initial attribute \src "libresoc.v:88128.9-88128.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_function_unit[13:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit case assign $1\dec31_function_unit[13:0] 14'00000000000000 end sync always update \dec31_function_unit $0\dec31_function_unit[13:0] end attribute \src "libresoc.v:88188.3-88248.6" process $proc$libresoc.v:88188$3802 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] attribute \src "libresoc.v:88189.5-88189.29" switch \initial attribute \src "libresoc.v:88189.9-88189.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op case assign $1\dec31_internal_op[6:0] 7'0000000 end sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end attribute \src "libresoc.v:88249.3-88309.6" process $proc$libresoc.v:88249$3803 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] attribute \src "libresoc.v:88250.5-88250.29" switch \initial attribute \src "libresoc.v:88250.9-88250.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form case assign $1\dec31_form[4:0] 5'00000 end sync always update \dec31_form $0\dec31_form[4:0] end attribute \src "libresoc.v:88310.3-88370.6" process $proc$libresoc.v:88310$3804 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] attribute \src "libresoc.v:88311.5-88311.29" switch \initial attribute \src "libresoc.v:88311.9-88311.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode case assign $1\dec31_asmcode[7:0] 8'00000000 end sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end attribute \src "libresoc.v:88371.3-88431.6" process $proc$libresoc.v:88371$3805 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] attribute \src "libresoc.v:88372.5-88372.29" switch \initial attribute \src "libresoc.v:88372.9-88372.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Etype attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Etype case assign $1\dec31_SV_Etype[1:0] 2'00 end sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end attribute \src "libresoc.v:88432.3-88492.6" process $proc$libresoc.v:88432$3806 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] attribute \src "libresoc.v:88433.5-88433.29" switch \initial attribute \src "libresoc.v:88433.9-88433.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype case assign $1\dec31_SV_Ptype[1:0] 2'00 end sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end attribute \src "libresoc.v:88493.3-88553.6" process $proc$libresoc.v:88493$3807 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] attribute \src "libresoc.v:88494.5-88494.29" switch \initial attribute \src "libresoc.v:88494.9-88494.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel case assign $1\dec31_in1_sel[2:0] 3'000 end sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end attribute \src "libresoc.v:88554.3-88614.6" process $proc$libresoc.v:88554$3808 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] attribute \src "libresoc.v:88555.5-88555.29" switch \initial attribute \src "libresoc.v:88555.9-88555.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel case assign $1\dec31_in2_sel[3:0] 4'0000 end sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end attribute \src "libresoc.v:88615.3-88675.6" process $proc$libresoc.v:88615$3809 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] attribute \src "libresoc.v:88616.5-88616.29" switch \initial attribute \src "libresoc.v:88616.9-88616.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel case assign $1\dec31_in3_sel[1:0] 2'00 end sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end attribute \src "libresoc.v:88676.3-88736.6" process $proc$libresoc.v:88676$3810 assign { } { } assign { } { } assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] attribute \src "libresoc.v:88677.5-88677.29" switch \initial attribute \src "libresoc.v:88677.9-88677.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_out_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel case assign $1\dec31_out_sel[2:0] 3'000 end sync always update \dec31_out_sel $0\dec31_out_sel[2:0] end attribute \src "libresoc.v:88737.3-88797.6" process $proc$libresoc.v:88737$3811 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] attribute \src "libresoc.v:88738.5-88738.29" switch \initial attribute \src "libresoc.v:88738.9-88738.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in case assign $1\dec31_cr_in[2:0] 3'000 end sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end attribute \src "libresoc.v:88798.3-88858.6" process $proc$libresoc.v:88798$3812 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] attribute \src "libresoc.v:88799.5-88799.29" switch \initial attribute \src "libresoc.v:88799.9-88799.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out case assign $1\dec31_cr_out[2:0] 3'000 end sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end attribute \src "libresoc.v:88859.3-88919.6" process $proc$libresoc.v:88859$3813 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] attribute \src "libresoc.v:88860.5-88860.29" switch \initial attribute \src "libresoc.v:88860.9-88860.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sv_in1[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in1 case assign $1\dec31_sv_in1[2:0] 3'000 end sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end attribute \src "libresoc.v:88920.3-88980.6" process $proc$libresoc.v:88920$3814 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] attribute \src "libresoc.v:88921.5-88921.29" switch \initial attribute \src "libresoc.v:88921.9-88921.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in2 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sv_in2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in2 case assign $1\dec31_sv_in2[2:0] 3'000 end sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end attribute \src "libresoc.v:88981.3-89041.6" process $proc$libresoc.v:88981$3815 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] attribute \src "libresoc.v:88982.5-88982.29" switch \initial attribute \src "libresoc.v:88982.9-88982.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in3 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sv_in3[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in3 case assign $1\dec31_sv_in3[2:0] 3'000 end sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end attribute \src "libresoc.v:89042.3-89102.6" process $proc$libresoc.v:89042$3816 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] attribute \src "libresoc.v:89043.5-89043.29" switch \initial attribute \src "libresoc.v:89043.9-89043.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sv_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out case assign $1\dec31_sv_out[2:0] 3'000 end sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end attribute \src "libresoc.v:89103.3-89163.6" process $proc$libresoc.v:89103$3817 assign { } { } assign { } { } assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0] attribute \src "libresoc.v:89104.5-89104.29" switch \initial attribute \src "libresoc.v:89104.9-89104.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out2 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sv_out2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out2 case assign $1\dec31_sv_out2[2:0] 3'000 end sync always update \dec31_sv_out2 $0\dec31_sv_out2[2:0] end attribute \src "libresoc.v:89164.3-89224.6" process $proc$libresoc.v:89164$3818 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] attribute \src "libresoc.v:89165.5-89165.29" switch \initial attribute \src "libresoc.v:89165.9-89165.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in case assign $1\dec31_sv_cr_in[2:0] 3'000 end sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end attribute \src "libresoc.v:89225.3-89285.6" process $proc$libresoc.v:89225$3819 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] attribute \src "libresoc.v:89226.5-89226.29" switch \initial attribute \src "libresoc.v:89226.9-89226.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out case assign $1\dec31_sv_cr_out[2:0] 3'000 end sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end attribute \src "libresoc.v:89286.3-89346.6" process $proc$libresoc.v:89286$3820 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] attribute \src "libresoc.v:89287.5-89287.29" switch \initial attribute \src "libresoc.v:89287.9-89287.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len case assign $1\dec31_ldst_len[3:0] 4'0000 end sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end attribute \src "libresoc.v:89347.3-89407.6" process $proc$libresoc.v:89347$3821 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] attribute \src "libresoc.v:89348.5-89348.29" switch \initial attribute \src "libresoc.v:89348.9-89348.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd case assign $1\dec31_upd[1:0] 2'00 end sync always update \dec31_upd $0\dec31_upd[1:0] end attribute \src "libresoc.v:89408.3-89468.6" process $proc$libresoc.v:89408$3822 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] attribute \src "libresoc.v:89409.5-89409.29" switch \initial attribute \src "libresoc.v:89409.9-89409.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel case assign $1\dec31_rc_sel[1:0] 2'00 end sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end attribute \src "libresoc.v:89469.3-89529.6" process $proc$libresoc.v:89469$3823 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] attribute \src "libresoc.v:89470.5-89470.29" switch \initial attribute \src "libresoc.v:89470.9-89470.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in case assign $1\dec31_cry_in[1:0] 2'00 end sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end attribute \src "libresoc.v:89530.3-89590.6" process $proc$libresoc.v:89530$3824 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] attribute \src "libresoc.v:89531.5-89531.29" switch \initial attribute \src "libresoc.v:89531.9-89531.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a case assign $1\dec31_inv_a[0:0] 1'0 end sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end attribute \src "libresoc.v:89591.3-89651.6" process $proc$libresoc.v:89591$3825 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] attribute \src "libresoc.v:89592.5-89592.29" switch \initial attribute \src "libresoc.v:89592.9-89592.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out case assign $1\dec31_inv_out[0:0] 1'0 end sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end attribute \src "libresoc.v:89652.3-89712.6" process $proc$libresoc.v:89652$3826 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] attribute \src "libresoc.v:89653.5-89653.29" switch \initial attribute \src "libresoc.v:89653.9-89653.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out case assign $1\dec31_cry_out[0:0] 1'0 end sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end attribute \src "libresoc.v:89713.3-89773.6" process $proc$libresoc.v:89713$3827 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] attribute \src "libresoc.v:89714.5-89714.29" switch \initial attribute \src "libresoc.v:89714.9-89714.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br case assign $1\dec31_br[0:0] 1'0 end sync always update \dec31_br $0\dec31_br[0:0] end attribute \src "libresoc.v:89774.3-89834.6" process $proc$libresoc.v:89774$3828 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] attribute \src "libresoc.v:89775.5-89775.29" switch \initial attribute \src "libresoc.v:89775.9-89775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext case assign $1\dec31_sgn_ext[0:0] 1'0 end sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end attribute \src "libresoc.v:89835.3-89895.6" process $proc$libresoc.v:89835$3829 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] attribute \src "libresoc.v:89836.5-89836.29" switch \initial attribute \src "libresoc.v:89836.9-89836.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv case assign $1\dec31_rsrv[0:0] 1'0 end sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end attribute \src "libresoc.v:89896.3-89956.6" process $proc$libresoc.v:89896$3830 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] attribute \src "libresoc.v:89897.5-89897.29" switch \initial attribute \src "libresoc.v:89897.9-89897.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b case assign $1\dec31_is_32b[0:0] 1'0 end sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end attribute \src "libresoc.v:89957.3-90017.6" process $proc$libresoc.v:89957$3831 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] attribute \src "libresoc.v:89958.5-89958.29" switch \initial attribute \src "libresoc.v:89958.9-89958.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn case assign $1\dec31_sgn[0:0] 1'0 end sync always update \dec31_sgn $0\dec31_sgn[0:0] end attribute \src "libresoc.v:90018.3-90078.6" process $proc$libresoc.v:90018$3832 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] attribute \src "libresoc.v:90019.5-90019.29" switch \initial attribute \src "libresoc.v:90019.9-90019.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk case assign $1\dec31_lk[0:0] 1'0 end sync always update \dec31_lk $0\dec31_lk[0:0] end attribute \src "libresoc.v:90079.3-90139.6" process $proc$libresoc.v:90079$3833 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] attribute \src "libresoc.v:90080.5-90080.29" switch \initial attribute \src "libresoc.v:90080.9-90080.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe case assign $1\dec31_sgl_pipe[0:0] 1'0 end sync always update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] end connect \dec31_dec_sub4_opcode_in \opcode_in connect \dec31_dec_sub24_opcode_in \opcode_in connect \dec31_dec_sub8_opcode_in \opcode_in connect \dec31_dec_sub18_opcode_in \opcode_in connect \dec31_dec_sub16_opcode_in \opcode_in connect \dec31_dec_sub23_opcode_in \opcode_in connect \dec31_dec_sub21_opcode_in \opcode_in connect \dec31_dec_sub20_opcode_in \opcode_in connect \dec31_dec_sub15_opcode_in \opcode_in connect \dec31_dec_sub27_opcode_in \opcode_in connect \dec31_dec_sub11_opcode_in \opcode_in connect \dec31_dec_sub9_opcode_in \opcode_in connect \dec31_dec_sub22_opcode_in \opcode_in connect \dec31_dec_sub19_opcode_in \opcode_in connect \dec31_dec_sub26_opcode_in \opcode_in connect \dec31_dec_sub0_opcode_in \opcode_in connect \dec31_dec_sub28_opcode_in \opcode_in connect \dec31_dec_sub10_opcode_in \opcode_in connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end attribute \src "libresoc.v:90164.1-91141.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 attribute \src "libresoc.v:91026.3-91044.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] attribute \src "libresoc.v:91045.3-91063.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] attribute \src "libresoc.v:90798.3-90816.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] attribute \src "libresoc.v:90874.3-90892.6" wire $0\dec31_dec_sub0_br[0:0] attribute \src "libresoc.v:90532.3-90550.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:90551.3-90569.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:90779.3-90797.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] attribute \src "libresoc.v:90855.3-90873.6" wire $0\dec31_dec_sub0_cry_out[0:0] attribute \src "libresoc.v:90931.3-90949.6" wire width 5 $0\dec31_dec_sub0_form[4:0] attribute \src "libresoc.v:90513.3-90531.6" wire width 14 $0\dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:91064.3-91082.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] attribute \src "libresoc.v:91083.3-91101.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] attribute \src "libresoc.v:91102.3-91120.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] attribute \src "libresoc.v:90722.3-90740.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:90817.3-90835.6" wire $0\dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:90836.3-90854.6" wire $0\dec31_dec_sub0_inv_out[0:0] attribute \src "libresoc.v:90950.3-90968.6" wire $0\dec31_dec_sub0_is_32b[0:0] attribute \src "libresoc.v:90703.3-90721.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:90988.3-91006.6" wire $0\dec31_dec_sub0_lk[0:0] attribute \src "libresoc.v:91121.3-91139.6" wire width 3 $0\dec31_dec_sub0_out_sel[2:0] attribute \src "libresoc.v:90760.3-90778.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:90912.3-90930.6" wire $0\dec31_dec_sub0_rsrv[0:0] attribute \src "libresoc.v:91007.3-91025.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] attribute \src "libresoc.v:90969.3-90987.6" wire $0\dec31_dec_sub0_sgn[0:0] attribute \src "libresoc.v:90893.3-90911.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] attribute \src "libresoc.v:90665.3-90683.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] attribute \src "libresoc.v:90684.3-90702.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] attribute \src "libresoc.v:90570.3-90588.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] attribute \src "libresoc.v:90589.3-90607.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] attribute \src "libresoc.v:90608.3-90626.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] attribute \src "libresoc.v:90646.3-90664.6" wire width 3 $0\dec31_dec_sub0_sv_out2[2:0] attribute \src "libresoc.v:90627.3-90645.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] attribute \src "libresoc.v:90741.3-90759.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] attribute \src "libresoc.v:90165.7-90165.20" wire $0\initial[0:0] attribute \src "libresoc.v:91026.3-91044.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] attribute \src "libresoc.v:91045.3-91063.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] attribute \src "libresoc.v:90798.3-90816.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] attribute \src "libresoc.v:90874.3-90892.6" wire $1\dec31_dec_sub0_br[0:0] attribute \src "libresoc.v:90532.3-90550.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:90551.3-90569.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:90779.3-90797.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] attribute \src "libresoc.v:90855.3-90873.6" wire $1\dec31_dec_sub0_cry_out[0:0] attribute \src "libresoc.v:90931.3-90949.6" wire width 5 $1\dec31_dec_sub0_form[4:0] attribute \src "libresoc.v:90513.3-90531.6" wire width 14 $1\dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:91064.3-91082.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] attribute \src "libresoc.v:91083.3-91101.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] attribute \src "libresoc.v:91102.3-91120.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] attribute \src "libresoc.v:90722.3-90740.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:90817.3-90835.6" wire $1\dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:90836.3-90854.6" wire $1\dec31_dec_sub0_inv_out[0:0] attribute \src "libresoc.v:90950.3-90968.6" wire $1\dec31_dec_sub0_is_32b[0:0] attribute \src "libresoc.v:90703.3-90721.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:90988.3-91006.6" wire $1\dec31_dec_sub0_lk[0:0] attribute \src "libresoc.v:91121.3-91139.6" wire width 3 $1\dec31_dec_sub0_out_sel[2:0] attribute \src "libresoc.v:90760.3-90778.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:90912.3-90930.6" wire $1\dec31_dec_sub0_rsrv[0:0] attribute \src "libresoc.v:91007.3-91025.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] attribute \src "libresoc.v:90969.3-90987.6" wire $1\dec31_dec_sub0_sgn[0:0] attribute \src "libresoc.v:90893.3-90911.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] attribute \src "libresoc.v:90665.3-90683.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] attribute \src "libresoc.v:90684.3-90702.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] attribute \src "libresoc.v:90570.3-90588.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] attribute \src "libresoc.v:90589.3-90607.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] attribute \src "libresoc.v:90608.3-90626.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] attribute \src "libresoc.v:90646.3-90664.6" wire width 3 $1\dec31_dec_sub0_sv_out2[2:0] attribute \src "libresoc.v:90627.3-90645.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] attribute \src "libresoc.v:90741.3-90759.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub0_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub0_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub0_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub0_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub0_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub0_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub0_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub0_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub0_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub0_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub0_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub0_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub0_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub0_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub0_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub0_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub0_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub0_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub0_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub0_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub0_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub0_upd attribute \src "libresoc.v:90165.7-90165.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:90165.7-90165.20" process $proc$libresoc.v:90165$3868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:90513.3-90531.6" process $proc$libresoc.v:90513$3835 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] attribute \src "libresoc.v:90514.5-90514.29" switch \initial attribute \src "libresoc.v:90514.9-90514.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000001000000 case assign $1\dec31_dec_sub0_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] end attribute \src "libresoc.v:90532.3-90550.6" process $proc$libresoc.v:90532$3836 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] attribute \src "libresoc.v:90533.5-90533.29" switch \initial attribute \src "libresoc.v:90533.9-90533.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 case assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end attribute \src "libresoc.v:90551.3-90569.6" process $proc$libresoc.v:90551$3837 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] attribute \src "libresoc.v:90552.5-90552.29" switch \initial attribute \src "libresoc.v:90552.9-90552.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end attribute \src "libresoc.v:90570.3-90588.6" process $proc$libresoc.v:90570$3838 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] attribute \src "libresoc.v:90571.5-90571.29" switch \initial attribute \src "libresoc.v:90571.9-90571.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 case assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end attribute \src "libresoc.v:90589.3-90607.6" process $proc$libresoc.v:90589$3839 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] attribute \src "libresoc.v:90590.5-90590.29" switch \initial attribute \src "libresoc.v:90590.9-90590.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end attribute \src "libresoc.v:90608.3-90626.6" process $proc$libresoc.v:90608$3840 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] attribute \src "libresoc.v:90609.5-90609.29" switch \initial attribute \src "libresoc.v:90609.9-90609.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end attribute \src "libresoc.v:90627.3-90645.6" process $proc$libresoc.v:90627$3841 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] attribute \src "libresoc.v:90628.5-90628.29" switch \initial attribute \src "libresoc.v:90628.9-90628.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end attribute \src "libresoc.v:90646.3-90664.6" process $proc$libresoc.v:90646$3842 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0] attribute \src "libresoc.v:90647.5-90647.29" switch \initial attribute \src "libresoc.v:90647.9-90647.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub0_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0] end attribute \src "libresoc.v:90665.3-90683.6" process $proc$libresoc.v:90665$3843 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] attribute \src "libresoc.v:90666.5-90666.29" switch \initial attribute \src "libresoc.v:90666.9-90666.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'010 case assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end attribute \src "libresoc.v:90684.3-90702.6" process $proc$libresoc.v:90684$3844 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] attribute \src "libresoc.v:90685.5-90685.29" switch \initial attribute \src "libresoc.v:90685.9-90685.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end attribute \src "libresoc.v:90703.3-90721.6" process $proc$libresoc.v:90703$3845 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] attribute \src "libresoc.v:90704.5-90704.29" switch \initial attribute \src "libresoc.v:90704.9-90704.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end attribute \src "libresoc.v:90722.3-90740.6" process $proc$libresoc.v:90722$3846 assign { } { } assign { } { } assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] attribute \src "libresoc.v:90723.5-90723.29" switch \initial attribute \src "libresoc.v:90723.9-90723.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 case assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end attribute \src "libresoc.v:90741.3-90759.6" process $proc$libresoc.v:90741$3847 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] attribute \src "libresoc.v:90742.5-90742.29" switch \initial attribute \src "libresoc.v:90742.9-90742.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_upd[1:0] 2'00 case assign $1\dec31_dec_sub0_upd[1:0] 2'00 end sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end attribute \src "libresoc.v:90760.3-90778.6" process $proc$libresoc.v:90760$3848 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] attribute \src "libresoc.v:90761.5-90761.29" switch \initial attribute \src "libresoc.v:90761.9-90761.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end attribute \src "libresoc.v:90779.3-90797.6" process $proc$libresoc.v:90779$3849 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] attribute \src "libresoc.v:90780.5-90780.29" switch \initial attribute \src "libresoc.v:90780.9-90780.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end attribute \src "libresoc.v:90798.3-90816.6" process $proc$libresoc.v:90798$3850 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] attribute \src "libresoc.v:90799.5-90799.29" switch \initial attribute \src "libresoc.v:90799.9-90799.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 case assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end attribute \src "libresoc.v:90817.3-90835.6" process $proc$libresoc.v:90817$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] attribute \src "libresoc.v:90818.5-90818.29" switch \initial attribute \src "libresoc.v:90818.9-90818.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end attribute \src "libresoc.v:90836.3-90854.6" process $proc$libresoc.v:90836$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] attribute \src "libresoc.v:90837.5-90837.29" switch \initial attribute \src "libresoc.v:90837.9-90837.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end attribute \src "libresoc.v:90855.3-90873.6" process $proc$libresoc.v:90855$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] attribute \src "libresoc.v:90856.5-90856.29" switch \initial attribute \src "libresoc.v:90856.9-90856.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end attribute \src "libresoc.v:90874.3-90892.6" process $proc$libresoc.v:90874$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] attribute \src "libresoc.v:90875.5-90875.29" switch \initial attribute \src "libresoc.v:90875.9-90875.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_br[0:0] 1'0 case assign $1\dec31_dec_sub0_br[0:0] 1'0 end sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end attribute \src "libresoc.v:90893.3-90911.6" process $proc$libresoc.v:90893$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] attribute \src "libresoc.v:90894.5-90894.29" switch \initial attribute \src "libresoc.v:90894.9-90894.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end attribute \src "libresoc.v:90912.3-90930.6" process $proc$libresoc.v:90912$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] attribute \src "libresoc.v:90913.5-90913.29" switch \initial attribute \src "libresoc.v:90913.9-90913.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end attribute \src "libresoc.v:90931.3-90949.6" process $proc$libresoc.v:90931$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] attribute \src "libresoc.v:90932.5-90932.29" switch \initial attribute \src "libresoc.v:90932.9-90932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_form[4:0] 5'11000 case assign $1\dec31_dec_sub0_form[4:0] 5'00000 end sync always update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end attribute \src "libresoc.v:90950.3-90968.6" process $proc$libresoc.v:90950$3858 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] attribute \src "libresoc.v:90951.5-90951.29" switch \initial attribute \src "libresoc.v:90951.9-90951.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end attribute \src "libresoc.v:90969.3-90987.6" process $proc$libresoc.v:90969$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] attribute \src "libresoc.v:90970.5-90970.29" switch \initial attribute \src "libresoc.v:90970.9-90970.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sgn[0:0] 1'0 case assign $1\dec31_dec_sub0_sgn[0:0] 1'0 end sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end attribute \src "libresoc.v:90988.3-91006.6" process $proc$libresoc.v:90988$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] attribute \src "libresoc.v:90989.5-90989.29" switch \initial attribute \src "libresoc.v:90989.9-90989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_lk[0:0] 1'0 case assign $1\dec31_dec_sub0_lk[0:0] 1'0 end sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end attribute \src "libresoc.v:91007.3-91025.6" process $proc$libresoc.v:91007$3861 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] attribute \src "libresoc.v:91008.5-91008.29" switch \initial attribute \src "libresoc.v:91008.9-91008.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end attribute \src "libresoc.v:91026.3-91044.6" process $proc$libresoc.v:91026$3862 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] attribute \src "libresoc.v:91027.5-91027.29" switch \initial attribute \src "libresoc.v:91027.9-91027.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end attribute \src "libresoc.v:91045.3-91063.6" process $proc$libresoc.v:91045$3863 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] attribute \src "libresoc.v:91046.5-91046.29" switch \initial attribute \src "libresoc.v:91046.9-91046.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end attribute \src "libresoc.v:91064.3-91082.6" process $proc$libresoc.v:91064$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] attribute \src "libresoc.v:91065.5-91065.29" switch \initial attribute \src "libresoc.v:91065.9-91065.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 case assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end attribute \src "libresoc.v:91083.3-91101.6" process $proc$libresoc.v:91083$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] attribute \src "libresoc.v:91084.5-91084.29" switch \initial attribute \src "libresoc.v:91084.9-91084.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 case assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end attribute \src "libresoc.v:91102.3-91120.6" process $proc$libresoc.v:91102$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] attribute \src "libresoc.v:91103.5-91103.29" switch \initial attribute \src "libresoc.v:91103.9-91103.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end attribute \src "libresoc.v:91121.3-91139.6" process $proc$libresoc.v:91121$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] attribute \src "libresoc.v:91122.5-91122.29" switch \initial attribute \src "libresoc.v:91122.9-91122.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub0_out_sel[2:0] 3'001 case assign $1\dec31_dec_sub0_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:91145.1-92716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 attribute \src "libresoc.v:92493.3-92529.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] attribute \src "libresoc.v:92530.3-92566.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] attribute \src "libresoc.v:92049.3-92085.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] attribute \src "libresoc.v:92197.3-92233.6" wire $0\dec31_dec_sub10_br[0:0] attribute \src "libresoc.v:91531.3-91567.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] attribute \src "libresoc.v:91568.3-91604.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] attribute \src "libresoc.v:92012.3-92048.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] attribute \src "libresoc.v:92160.3-92196.6" wire $0\dec31_dec_sub10_cry_out[0:0] attribute \src "libresoc.v:92308.3-92344.6" wire width 5 $0\dec31_dec_sub10_form[4:0] attribute \src "libresoc.v:91494.3-91530.6" wire width 14 $0\dec31_dec_sub10_function_unit[13:0] attribute \src "libresoc.v:92567.3-92603.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] attribute \src "libresoc.v:92604.3-92640.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] attribute \src "libresoc.v:92641.3-92677.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] attribute \src "libresoc.v:91901.3-91937.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] attribute \src "libresoc.v:92086.3-92122.6" wire $0\dec31_dec_sub10_inv_a[0:0] attribute \src "libresoc.v:92123.3-92159.6" wire $0\dec31_dec_sub10_inv_out[0:0] attribute \src "libresoc.v:92345.3-92381.6" wire $0\dec31_dec_sub10_is_32b[0:0] attribute \src "libresoc.v:91864.3-91900.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] attribute \src "libresoc.v:92419.3-92455.6" wire $0\dec31_dec_sub10_lk[0:0] attribute \src "libresoc.v:92678.3-92714.6" wire width 3 $0\dec31_dec_sub10_out_sel[2:0] attribute \src "libresoc.v:91975.3-92011.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] attribute \src "libresoc.v:92271.3-92307.6" wire $0\dec31_dec_sub10_rsrv[0:0] attribute \src "libresoc.v:92456.3-92492.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] attribute \src "libresoc.v:92382.3-92418.6" wire $0\dec31_dec_sub10_sgn[0:0] attribute \src "libresoc.v:92234.3-92270.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] attribute \src "libresoc.v:91790.3-91826.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] attribute \src "libresoc.v:91827.3-91863.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] attribute \src "libresoc.v:91605.3-91641.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] attribute \src "libresoc.v:91642.3-91678.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] attribute \src "libresoc.v:91679.3-91715.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] attribute \src "libresoc.v:91753.3-91789.6" wire width 3 $0\dec31_dec_sub10_sv_out2[2:0] attribute \src "libresoc.v:91716.3-91752.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] attribute \src "libresoc.v:91938.3-91974.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] attribute \src "libresoc.v:91146.7-91146.20" wire $0\initial[0:0] attribute \src "libresoc.v:92493.3-92529.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] attribute \src "libresoc.v:92530.3-92566.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] attribute \src "libresoc.v:92049.3-92085.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] attribute \src "libresoc.v:92197.3-92233.6" wire $1\dec31_dec_sub10_br[0:0] attribute \src "libresoc.v:91531.3-91567.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] attribute \src "libresoc.v:91568.3-91604.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] attribute \src "libresoc.v:92012.3-92048.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] attribute \src "libresoc.v:92160.3-92196.6" wire $1\dec31_dec_sub10_cry_out[0:0] attribute \src "libresoc.v:92308.3-92344.6" wire width 5 $1\dec31_dec_sub10_form[4:0] attribute \src "libresoc.v:91494.3-91530.6" wire width 14 $1\dec31_dec_sub10_function_unit[13:0] attribute \src "libresoc.v:92567.3-92603.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] attribute \src "libresoc.v:92604.3-92640.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] attribute \src "libresoc.v:92641.3-92677.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] attribute \src "libresoc.v:91901.3-91937.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] attribute \src "libresoc.v:92086.3-92122.6" wire $1\dec31_dec_sub10_inv_a[0:0] attribute \src "libresoc.v:92123.3-92159.6" wire $1\dec31_dec_sub10_inv_out[0:0] attribute \src "libresoc.v:92345.3-92381.6" wire $1\dec31_dec_sub10_is_32b[0:0] attribute \src "libresoc.v:91864.3-91900.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] attribute \src "libresoc.v:92419.3-92455.6" wire $1\dec31_dec_sub10_lk[0:0] attribute \src "libresoc.v:92678.3-92714.6" wire width 3 $1\dec31_dec_sub10_out_sel[2:0] attribute \src "libresoc.v:91975.3-92011.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] attribute \src "libresoc.v:92271.3-92307.6" wire $1\dec31_dec_sub10_rsrv[0:0] attribute \src "libresoc.v:92456.3-92492.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] attribute \src "libresoc.v:92382.3-92418.6" wire $1\dec31_dec_sub10_sgn[0:0] attribute \src "libresoc.v:92234.3-92270.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] attribute \src "libresoc.v:91790.3-91826.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] attribute \src "libresoc.v:91827.3-91863.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] attribute \src "libresoc.v:91605.3-91641.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] attribute \src "libresoc.v:91642.3-91678.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] attribute \src "libresoc.v:91679.3-91715.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] attribute \src "libresoc.v:91753.3-91789.6" wire width 3 $1\dec31_dec_sub10_sv_out2[2:0] attribute \src "libresoc.v:91716.3-91752.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] attribute \src "libresoc.v:91938.3-91974.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub10_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub10_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub10_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub10_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub10_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub10_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub10_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub10_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub10_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub10_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub10_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub10_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub10_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub10_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub10_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub10_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub10_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub10_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub10_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub10_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub10_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub10_upd attribute \src "libresoc.v:91146.7-91146.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:91146.7-91146.20" process $proc$libresoc.v:91146$3902 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:91494.3-91530.6" process $proc$libresoc.v:91494$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] attribute \src "libresoc.v:91495.5-91495.29" switch \initial attribute \src "libresoc.v:91495.9-91495.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000010 case assign $1\dec31_dec_sub10_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end attribute \src "libresoc.v:91531.3-91567.6" process $proc$libresoc.v:91531$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] attribute \src "libresoc.v:91532.5-91532.29" switch \initial attribute \src "libresoc.v:91532.9-91532.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end attribute \src "libresoc.v:91568.3-91604.6" process $proc$libresoc.v:91568$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] attribute \src "libresoc.v:91569.5-91569.29" switch \initial attribute \src "libresoc.v:91569.9-91569.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end attribute \src "libresoc.v:91605.3-91641.6" process $proc$libresoc.v:91605$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] attribute \src "libresoc.v:91606.5-91606.29" switch \initial attribute \src "libresoc.v:91606.9-91606.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub10_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end attribute \src "libresoc.v:91642.3-91678.6" process $proc$libresoc.v:91642$3873 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] attribute \src "libresoc.v:91643.5-91643.29" switch \initial attribute \src "libresoc.v:91643.9-91643.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end attribute \src "libresoc.v:91679.3-91715.6" process $proc$libresoc.v:91679$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] attribute \src "libresoc.v:91680.5-91680.29" switch \initial attribute \src "libresoc.v:91680.9-91680.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end attribute \src "libresoc.v:91716.3-91752.6" process $proc$libresoc.v:91716$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] attribute \src "libresoc.v:91717.5-91717.29" switch \initial attribute \src "libresoc.v:91717.9-91717.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub10_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end attribute \src "libresoc.v:91753.3-91789.6" process $proc$libresoc.v:91753$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0] attribute \src "libresoc.v:91754.5-91754.29" switch \initial attribute \src "libresoc.v:91754.9-91754.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub10_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0] end attribute \src "libresoc.v:91790.3-91826.6" process $proc$libresoc.v:91790$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] attribute \src "libresoc.v:91791.5-91791.29" switch \initial attribute \src "libresoc.v:91791.9-91791.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end attribute \src "libresoc.v:91827.3-91863.6" process $proc$libresoc.v:91827$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] attribute \src "libresoc.v:91828.5-91828.29" switch \initial attribute \src "libresoc.v:91828.9-91828.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end attribute \src "libresoc.v:91864.3-91900.6" process $proc$libresoc.v:91864$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] attribute \src "libresoc.v:91865.5-91865.29" switch \initial attribute \src "libresoc.v:91865.9-91865.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end attribute \src "libresoc.v:91901.3-91937.6" process $proc$libresoc.v:91901$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] attribute \src "libresoc.v:91902.5-91902.29" switch \initial attribute \src "libresoc.v:91902.9-91902.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 case assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end attribute \src "libresoc.v:91938.3-91974.6" process $proc$libresoc.v:91938$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] attribute \src "libresoc.v:91939.5-91939.29" switch \initial attribute \src "libresoc.v:91939.9-91939.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_upd[1:0] 2'00 case assign $1\dec31_dec_sub10_upd[1:0] 2'00 end sync always update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end attribute \src "libresoc.v:91975.3-92011.6" process $proc$libresoc.v:91975$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] attribute \src "libresoc.v:91976.5-91976.29" switch \initial attribute \src "libresoc.v:91976.9-91976.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end attribute \src "libresoc.v:92012.3-92048.6" process $proc$libresoc.v:92012$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] attribute \src "libresoc.v:92013.5-92013.29" switch \initial attribute \src "libresoc.v:92013.9-92013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 case assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end attribute \src "libresoc.v:92049.3-92085.6" process $proc$libresoc.v:92049$3884 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] attribute \src "libresoc.v:92050.5-92050.29" switch \initial attribute \src "libresoc.v:92050.9-92050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 case assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end attribute \src "libresoc.v:92086.3-92122.6" process $proc$libresoc.v:92086$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] attribute \src "libresoc.v:92087.5-92087.29" switch \initial attribute \src "libresoc.v:92087.9-92087.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end attribute \src "libresoc.v:92123.3-92159.6" process $proc$libresoc.v:92123$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] attribute \src "libresoc.v:92124.5-92124.29" switch \initial attribute \src "libresoc.v:92124.9-92124.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end attribute \src "libresoc.v:92160.3-92196.6" process $proc$libresoc.v:92160$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] attribute \src "libresoc.v:92161.5-92161.29" switch \initial attribute \src "libresoc.v:92161.9-92161.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 case assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end attribute \src "libresoc.v:92197.3-92233.6" process $proc$libresoc.v:92197$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] attribute \src "libresoc.v:92198.5-92198.29" switch \initial attribute \src "libresoc.v:92198.9-92198.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_br[0:0] 1'0 case assign $1\dec31_dec_sub10_br[0:0] 1'0 end sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end attribute \src "libresoc.v:92234.3-92270.6" process $proc$libresoc.v:92234$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] attribute \src "libresoc.v:92235.5-92235.29" switch \initial attribute \src "libresoc.v:92235.9-92235.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end attribute \src "libresoc.v:92271.3-92307.6" process $proc$libresoc.v:92271$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] attribute \src "libresoc.v:92272.5-92272.29" switch \initial attribute \src "libresoc.v:92272.9-92272.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end attribute \src "libresoc.v:92308.3-92344.6" process $proc$libresoc.v:92308$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] attribute \src "libresoc.v:92309.5-92309.29" switch \initial attribute \src "libresoc.v:92309.9-92309.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_form[4:0] 5'10001 case assign $1\dec31_dec_sub10_form[4:0] 5'00000 end sync always update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end attribute \src "libresoc.v:92345.3-92381.6" process $proc$libresoc.v:92345$3892 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] attribute \src "libresoc.v:92346.5-92346.29" switch \initial attribute \src "libresoc.v:92346.9-92346.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end attribute \src "libresoc.v:92382.3-92418.6" process $proc$libresoc.v:92382$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] attribute \src "libresoc.v:92383.5-92383.29" switch \initial attribute \src "libresoc.v:92383.9-92383.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sgn[0:0] 1'0 case assign $1\dec31_dec_sub10_sgn[0:0] 1'0 end sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end attribute \src "libresoc.v:92419.3-92455.6" process $proc$libresoc.v:92419$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] attribute \src "libresoc.v:92420.5-92420.29" switch \initial attribute \src "libresoc.v:92420.9-92420.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_lk[0:0] 1'0 case assign $1\dec31_dec_sub10_lk[0:0] 1'0 end sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end attribute \src "libresoc.v:92456.3-92492.6" process $proc$libresoc.v:92456$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] attribute \src "libresoc.v:92457.5-92457.29" switch \initial attribute \src "libresoc.v:92457.9-92457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end attribute \src "libresoc.v:92493.3-92529.6" process $proc$libresoc.v:92493$3896 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] attribute \src "libresoc.v:92494.5-92494.29" switch \initial attribute \src "libresoc.v:92494.9-92494.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end attribute \src "libresoc.v:92530.3-92566.6" process $proc$libresoc.v:92530$3897 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] attribute \src "libresoc.v:92531.5-92531.29" switch \initial attribute \src "libresoc.v:92531.9-92531.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end attribute \src "libresoc.v:92567.3-92603.6" process $proc$libresoc.v:92567$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] attribute \src "libresoc.v:92568.5-92568.29" switch \initial attribute \src "libresoc.v:92568.9-92568.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 case assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end attribute \src "libresoc.v:92604.3-92640.6" process $proc$libresoc.v:92604$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] attribute \src "libresoc.v:92605.5-92605.29" switch \initial attribute \src "libresoc.v:92605.9-92605.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 case assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end attribute \src "libresoc.v:92641.3-92677.6" process $proc$libresoc.v:92641$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] attribute \src "libresoc.v:92642.5-92642.29" switch \initial attribute \src "libresoc.v:92642.9-92642.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end attribute \src "libresoc.v:92678.3-92714.6" process $proc$libresoc.v:92678$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] attribute \src "libresoc.v:92679.5-92679.29" switch \initial attribute \src "libresoc.v:92679.9-92679.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub10_out_sel[2:0] 3'001 case assign $1\dec31_dec_sub10_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:92720.1-94885.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 attribute \src "libresoc.v:94554.3-94608.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] attribute \src "libresoc.v:94609.3-94663.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] attribute \src "libresoc.v:93894.3-93948.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] attribute \src "libresoc.v:94114.3-94168.6" wire $0\dec31_dec_sub11_br[0:0] attribute \src "libresoc.v:93124.3-93178.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:93179.3-93233.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:93839.3-93893.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] attribute \src "libresoc.v:94059.3-94113.6" wire $0\dec31_dec_sub11_cry_out[0:0] attribute \src "libresoc.v:94279.3-94333.6" wire width 5 $0\dec31_dec_sub11_form[4:0] attribute \src "libresoc.v:93069.3-93123.6" wire width 14 $0\dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:94664.3-94718.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] attribute \src "libresoc.v:94719.3-94773.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:94774.3-94828.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] attribute \src "libresoc.v:93674.3-93728.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:93949.3-94003.6" wire $0\dec31_dec_sub11_inv_a[0:0] attribute \src "libresoc.v:94004.3-94058.6" wire $0\dec31_dec_sub11_inv_out[0:0] attribute \src "libresoc.v:94334.3-94388.6" wire $0\dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:93619.3-93673.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] attribute \src "libresoc.v:94444.3-94498.6" wire $0\dec31_dec_sub11_lk[0:0] attribute \src "libresoc.v:94829.3-94883.6" wire width 3 $0\dec31_dec_sub11_out_sel[2:0] attribute \src "libresoc.v:93784.3-93838.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:94224.3-94278.6" wire $0\dec31_dec_sub11_rsrv[0:0] attribute \src "libresoc.v:94499.3-94553.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] attribute \src "libresoc.v:94389.3-94443.6" wire $0\dec31_dec_sub11_sgn[0:0] attribute \src "libresoc.v:94169.3-94223.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] attribute \src "libresoc.v:93509.3-93563.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] attribute \src "libresoc.v:93564.3-93618.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] attribute \src "libresoc.v:93234.3-93288.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] attribute \src "libresoc.v:93289.3-93343.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] attribute \src "libresoc.v:93344.3-93398.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] attribute \src "libresoc.v:93454.3-93508.6" wire width 3 $0\dec31_dec_sub11_sv_out2[2:0] attribute \src "libresoc.v:93399.3-93453.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] attribute \src "libresoc.v:93729.3-93783.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] attribute \src "libresoc.v:92721.7-92721.20" wire $0\initial[0:0] attribute \src "libresoc.v:94554.3-94608.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] attribute \src "libresoc.v:94609.3-94663.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] attribute \src "libresoc.v:93894.3-93948.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] attribute \src "libresoc.v:94114.3-94168.6" wire $1\dec31_dec_sub11_br[0:0] attribute \src "libresoc.v:93124.3-93178.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:93179.3-93233.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:93839.3-93893.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] attribute \src "libresoc.v:94059.3-94113.6" wire $1\dec31_dec_sub11_cry_out[0:0] attribute \src "libresoc.v:94279.3-94333.6" wire width 5 $1\dec31_dec_sub11_form[4:0] attribute \src "libresoc.v:93069.3-93123.6" wire width 14 $1\dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:94664.3-94718.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] attribute \src "libresoc.v:94719.3-94773.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:94774.3-94828.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] attribute \src "libresoc.v:93674.3-93728.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:93949.3-94003.6" wire $1\dec31_dec_sub11_inv_a[0:0] attribute \src "libresoc.v:94004.3-94058.6" wire $1\dec31_dec_sub11_inv_out[0:0] attribute \src "libresoc.v:94334.3-94388.6" wire $1\dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:93619.3-93673.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] attribute \src "libresoc.v:94444.3-94498.6" wire $1\dec31_dec_sub11_lk[0:0] attribute \src "libresoc.v:94829.3-94883.6" wire width 3 $1\dec31_dec_sub11_out_sel[2:0] attribute \src "libresoc.v:93784.3-93838.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:94224.3-94278.6" wire $1\dec31_dec_sub11_rsrv[0:0] attribute \src "libresoc.v:94499.3-94553.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] attribute \src "libresoc.v:94389.3-94443.6" wire $1\dec31_dec_sub11_sgn[0:0] attribute \src "libresoc.v:94169.3-94223.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] attribute \src "libresoc.v:93509.3-93563.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] attribute \src "libresoc.v:93564.3-93618.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] attribute \src "libresoc.v:93234.3-93288.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] attribute \src "libresoc.v:93289.3-93343.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] attribute \src "libresoc.v:93344.3-93398.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] attribute \src "libresoc.v:93454.3-93508.6" wire width 3 $1\dec31_dec_sub11_sv_out2[2:0] attribute \src "libresoc.v:93399.3-93453.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] attribute \src "libresoc.v:93729.3-93783.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub11_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub11_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub11_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub11_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub11_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub11_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub11_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub11_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub11_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub11_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub11_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub11_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub11_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub11_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub11_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub11_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub11_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub11_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub11_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub11_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub11_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub11_upd attribute \src "libresoc.v:92721.7-92721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:92721.7-92721.20" process $proc$libresoc.v:92721$3936 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:93069.3-93123.6" process $proc$libresoc.v:93069$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] attribute \src "libresoc.v:93070.5-93070.29" switch \initial attribute \src "libresoc.v:93070.9-93070.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000100000000 case assign $1\dec31_dec_sub11_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end attribute \src "libresoc.v:93124.3-93178.6" process $proc$libresoc.v:93124$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] attribute \src "libresoc.v:93125.5-93125.29" switch \initial attribute \src "libresoc.v:93125.9-93125.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end attribute \src "libresoc.v:93179.3-93233.6" process $proc$libresoc.v:93179$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] attribute \src "libresoc.v:93180.5-93180.29" switch \initial attribute \src "libresoc.v:93180.9-93180.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end attribute \src "libresoc.v:93234.3-93288.6" process $proc$libresoc.v:93234$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] attribute \src "libresoc.v:93235.5-93235.29" switch \initial attribute \src "libresoc.v:93235.9-93235.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub11_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end attribute \src "libresoc.v:93289.3-93343.6" process $proc$libresoc.v:93289$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] attribute \src "libresoc.v:93290.5-93290.29" switch \initial attribute \src "libresoc.v:93290.9-93290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 case assign $1\dec31_dec_sub11_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end attribute \src "libresoc.v:93344.3-93398.6" process $proc$libresoc.v:93344$3908 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] attribute \src "libresoc.v:93345.5-93345.29" switch \initial attribute \src "libresoc.v:93345.9-93345.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end attribute \src "libresoc.v:93399.3-93453.6" process $proc$libresoc.v:93399$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] attribute \src "libresoc.v:93400.5-93400.29" switch \initial attribute \src "libresoc.v:93400.9-93400.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub11_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end attribute \src "libresoc.v:93454.3-93508.6" process $proc$libresoc.v:93454$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0] attribute \src "libresoc.v:93455.5-93455.29" switch \initial attribute \src "libresoc.v:93455.9-93455.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub11_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0] end attribute \src "libresoc.v:93509.3-93563.6" process $proc$libresoc.v:93509$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] attribute \src "libresoc.v:93510.5-93510.29" switch \initial attribute \src "libresoc.v:93510.9-93510.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end attribute \src "libresoc.v:93564.3-93618.6" process $proc$libresoc.v:93564$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] attribute \src "libresoc.v:93565.5-93565.29" switch \initial attribute \src "libresoc.v:93565.9-93565.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end attribute \src "libresoc.v:93619.3-93673.6" process $proc$libresoc.v:93619$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] attribute \src "libresoc.v:93620.5-93620.29" switch \initial attribute \src "libresoc.v:93620.9-93620.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end attribute \src "libresoc.v:93674.3-93728.6" process $proc$libresoc.v:93674$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] attribute \src "libresoc.v:93675.5-93675.29" switch \initial attribute \src "libresoc.v:93675.9-93675.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 case assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end attribute \src "libresoc.v:93729.3-93783.6" process $proc$libresoc.v:93729$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] attribute \src "libresoc.v:93730.5-93730.29" switch \initial attribute \src "libresoc.v:93730.9-93730.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_upd[1:0] 2'00 case assign $1\dec31_dec_sub11_upd[1:0] 2'00 end sync always update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end attribute \src "libresoc.v:93784.3-93838.6" process $proc$libresoc.v:93784$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] attribute \src "libresoc.v:93785.5-93785.29" switch \initial attribute \src "libresoc.v:93785.9-93785.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end attribute \src "libresoc.v:93839.3-93893.6" process $proc$libresoc.v:93839$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] attribute \src "libresoc.v:93840.5-93840.29" switch \initial attribute \src "libresoc.v:93840.9-93840.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end attribute \src "libresoc.v:93894.3-93948.6" process $proc$libresoc.v:93894$3918 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] attribute \src "libresoc.v:93895.5-93895.29" switch \initial attribute \src "libresoc.v:93895.9-93895.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 case assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end attribute \src "libresoc.v:93949.3-94003.6" process $proc$libresoc.v:93949$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] attribute \src "libresoc.v:93950.5-93950.29" switch \initial attribute \src "libresoc.v:93950.9-93950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end attribute \src "libresoc.v:94004.3-94058.6" process $proc$libresoc.v:94004$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] attribute \src "libresoc.v:94005.5-94005.29" switch \initial attribute \src "libresoc.v:94005.9-94005.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end attribute \src "libresoc.v:94059.3-94113.6" process $proc$libresoc.v:94059$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] attribute \src "libresoc.v:94060.5-94060.29" switch \initial attribute \src "libresoc.v:94060.9-94060.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end attribute \src "libresoc.v:94114.3-94168.6" process $proc$libresoc.v:94114$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] attribute \src "libresoc.v:94115.5-94115.29" switch \initial attribute \src "libresoc.v:94115.9-94115.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_br[0:0] 1'0 case assign $1\dec31_dec_sub11_br[0:0] 1'0 end sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end attribute \src "libresoc.v:94169.3-94223.6" process $proc$libresoc.v:94169$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] attribute \src "libresoc.v:94170.5-94170.29" switch \initial attribute \src "libresoc.v:94170.9-94170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end attribute \src "libresoc.v:94224.3-94278.6" process $proc$libresoc.v:94224$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] attribute \src "libresoc.v:94225.5-94225.29" switch \initial attribute \src "libresoc.v:94225.9-94225.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end attribute \src "libresoc.v:94279.3-94333.6" process $proc$libresoc.v:94279$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] attribute \src "libresoc.v:94280.5-94280.29" switch \initial attribute \src "libresoc.v:94280.9-94280.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_form[4:0] 5'10001 case assign $1\dec31_dec_sub11_form[4:0] 5'00000 end sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end attribute \src "libresoc.v:94334.3-94388.6" process $proc$libresoc.v:94334$3926 assign { } { } assign { } { } assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] attribute \src "libresoc.v:94335.5-94335.29" switch \initial attribute \src "libresoc.v:94335.9-94335.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 case assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end attribute \src "libresoc.v:94389.3-94443.6" process $proc$libresoc.v:94389$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] attribute \src "libresoc.v:94390.5-94390.29" switch \initial attribute \src "libresoc.v:94390.9-94390.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sgn[0:0] 1'1 case assign $1\dec31_dec_sub11_sgn[0:0] 1'0 end sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end attribute \src "libresoc.v:94444.3-94498.6" process $proc$libresoc.v:94444$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] attribute \src "libresoc.v:94445.5-94445.29" switch \initial attribute \src "libresoc.v:94445.9-94445.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_lk[0:0] 1'0 case assign $1\dec31_dec_sub11_lk[0:0] 1'0 end sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end attribute \src "libresoc.v:94499.3-94553.6" process $proc$libresoc.v:94499$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] attribute \src "libresoc.v:94500.5-94500.29" switch \initial attribute \src "libresoc.v:94500.9-94500.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end attribute \src "libresoc.v:94554.3-94608.6" process $proc$libresoc.v:94554$3930 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] attribute \src "libresoc.v:94555.5-94555.29" switch \initial attribute \src "libresoc.v:94555.9-94555.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end attribute \src "libresoc.v:94609.3-94663.6" process $proc$libresoc.v:94609$3931 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] attribute \src "libresoc.v:94610.5-94610.29" switch \initial attribute \src "libresoc.v:94610.9-94610.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 case assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end attribute \src "libresoc.v:94664.3-94718.6" process $proc$libresoc.v:94664$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] attribute \src "libresoc.v:94665.5-94665.29" switch \initial attribute \src "libresoc.v:94665.9-94665.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 case assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end attribute \src "libresoc.v:94719.3-94773.6" process $proc$libresoc.v:94719$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] attribute \src "libresoc.v:94720.5-94720.29" switch \initial attribute \src "libresoc.v:94720.9-94720.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end attribute \src "libresoc.v:94774.3-94828.6" process $proc$libresoc.v:94774$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] attribute \src "libresoc.v:94775.5-94775.29" switch \initial attribute \src "libresoc.v:94775.9-94775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end attribute \src "libresoc.v:94829.3-94883.6" process $proc$libresoc.v:94829$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] attribute \src "libresoc.v:94830.5-94830.29" switch \initial attribute \src "libresoc.v:94830.9-94830.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub11_out_sel[2:0] 3'001 case assign $1\dec31_dec_sub11_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:94889.1-98638.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 attribute \src "libresoc.v:98019.3-98121.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] attribute \src "libresoc.v:98122.3-98224.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] attribute \src "libresoc.v:96783.3-96885.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] attribute \src "libresoc.v:97195.3-97297.6" wire $0\dec31_dec_sub15_br[0:0] attribute \src "libresoc.v:95341.3-95443.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] attribute \src "libresoc.v:95444.3-95546.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] attribute \src "libresoc.v:96680.3-96782.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] attribute \src "libresoc.v:97092.3-97194.6" wire $0\dec31_dec_sub15_cry_out[0:0] attribute \src "libresoc.v:97504.3-97606.6" wire width 5 $0\dec31_dec_sub15_form[4:0] attribute \src "libresoc.v:95238.3-95340.6" wire width 14 $0\dec31_dec_sub15_function_unit[13:0] attribute \src "libresoc.v:98225.3-98327.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] attribute \src "libresoc.v:98328.3-98430.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] attribute \src "libresoc.v:98431.3-98533.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] attribute \src "libresoc.v:96371.3-96473.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] attribute \src "libresoc.v:96886.3-96988.6" wire $0\dec31_dec_sub15_inv_a[0:0] attribute \src "libresoc.v:96989.3-97091.6" wire $0\dec31_dec_sub15_inv_out[0:0] attribute \src "libresoc.v:97607.3-97709.6" wire $0\dec31_dec_sub15_is_32b[0:0] attribute \src "libresoc.v:96268.3-96370.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] attribute \src "libresoc.v:97813.3-97915.6" wire $0\dec31_dec_sub15_lk[0:0] attribute \src "libresoc.v:98534.3-98636.6" wire width 3 $0\dec31_dec_sub15_out_sel[2:0] attribute \src "libresoc.v:96577.3-96679.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] attribute \src "libresoc.v:97401.3-97503.6" wire $0\dec31_dec_sub15_rsrv[0:0] attribute \src "libresoc.v:97916.3-98018.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] attribute \src "libresoc.v:97710.3-97812.6" wire $0\dec31_dec_sub15_sgn[0:0] attribute \src "libresoc.v:97298.3-97400.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] attribute \src "libresoc.v:96062.3-96164.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] attribute \src "libresoc.v:96165.3-96267.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] attribute \src "libresoc.v:95547.3-95649.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] attribute \src "libresoc.v:95650.3-95752.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] attribute \src "libresoc.v:95753.3-95855.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] attribute \src "libresoc.v:95959.3-96061.6" wire width 3 $0\dec31_dec_sub15_sv_out2[2:0] attribute \src "libresoc.v:95856.3-95958.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] attribute \src "libresoc.v:96474.3-96576.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] attribute \src "libresoc.v:94890.7-94890.20" wire $0\initial[0:0] attribute \src "libresoc.v:98019.3-98121.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] attribute \src "libresoc.v:98122.3-98224.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] attribute \src "libresoc.v:96783.3-96885.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] attribute \src "libresoc.v:97195.3-97297.6" wire $1\dec31_dec_sub15_br[0:0] attribute \src "libresoc.v:95341.3-95443.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] attribute \src "libresoc.v:95444.3-95546.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] attribute \src "libresoc.v:96680.3-96782.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] attribute \src "libresoc.v:97092.3-97194.6" wire $1\dec31_dec_sub15_cry_out[0:0] attribute \src "libresoc.v:97504.3-97606.6" wire width 5 $1\dec31_dec_sub15_form[4:0] attribute \src "libresoc.v:95238.3-95340.6" wire width 14 $1\dec31_dec_sub15_function_unit[13:0] attribute \src "libresoc.v:98225.3-98327.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] attribute \src "libresoc.v:98328.3-98430.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] attribute \src "libresoc.v:98431.3-98533.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] attribute \src "libresoc.v:96371.3-96473.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] attribute \src "libresoc.v:96886.3-96988.6" wire $1\dec31_dec_sub15_inv_a[0:0] attribute \src "libresoc.v:96989.3-97091.6" wire $1\dec31_dec_sub15_inv_out[0:0] attribute \src "libresoc.v:97607.3-97709.6" wire $1\dec31_dec_sub15_is_32b[0:0] attribute \src "libresoc.v:96268.3-96370.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] attribute \src "libresoc.v:97813.3-97915.6" wire $1\dec31_dec_sub15_lk[0:0] attribute \src "libresoc.v:98534.3-98636.6" wire width 3 $1\dec31_dec_sub15_out_sel[2:0] attribute \src "libresoc.v:96577.3-96679.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] attribute \src "libresoc.v:97401.3-97503.6" wire $1\dec31_dec_sub15_rsrv[0:0] attribute \src "libresoc.v:97916.3-98018.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] attribute \src "libresoc.v:97710.3-97812.6" wire $1\dec31_dec_sub15_sgn[0:0] attribute \src "libresoc.v:97298.3-97400.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] attribute \src "libresoc.v:96062.3-96164.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] attribute \src "libresoc.v:96165.3-96267.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] attribute \src "libresoc.v:95547.3-95649.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] attribute \src "libresoc.v:95650.3-95752.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] attribute \src "libresoc.v:95753.3-95855.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] attribute \src "libresoc.v:95959.3-96061.6" wire width 3 $1\dec31_dec_sub15_sv_out2[2:0] attribute \src "libresoc.v:95856.3-95958.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] attribute \src "libresoc.v:96474.3-96576.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub15_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub15_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub15_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub15_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub15_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub15_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub15_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub15_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub15_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub15_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub15_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub15_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub15_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub15_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub15_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub15_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub15_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub15_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub15_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub15_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub15_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub15_upd attribute \src "libresoc.v:94890.7-94890.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:94890.7-94890.20" process $proc$libresoc.v:94890$3970 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:95238.3-95340.6" process $proc$libresoc.v:95238$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] attribute \src "libresoc.v:95239.5-95239.29" switch \initial attribute \src "libresoc.v:95239.9-95239.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000001000000 case assign $1\dec31_dec_sub15_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end attribute \src "libresoc.v:95341.3-95443.6" process $proc$libresoc.v:95341$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] attribute \src "libresoc.v:95342.5-95342.29" switch \initial attribute \src "libresoc.v:95342.9-95342.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 case assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end attribute \src "libresoc.v:95444.3-95546.6" process $proc$libresoc.v:95444$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] attribute \src "libresoc.v:95445.5-95445.29" switch \initial attribute \src "libresoc.v:95445.9-95445.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end attribute \src "libresoc.v:95547.3-95649.6" process $proc$libresoc.v:95547$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] attribute \src "libresoc.v:95548.5-95548.29" switch \initial attribute \src "libresoc.v:95548.9-95548.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub15_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end attribute \src "libresoc.v:95650.3-95752.6" process $proc$libresoc.v:95650$3941 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] attribute \src "libresoc.v:95651.5-95651.29" switch \initial attribute \src "libresoc.v:95651.9-95651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 case assign $1\dec31_dec_sub15_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end attribute \src "libresoc.v:95753.3-95855.6" process $proc$libresoc.v:95753$3942 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] attribute \src "libresoc.v:95754.5-95754.29" switch \initial attribute \src "libresoc.v:95754.9-95754.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end attribute \src "libresoc.v:95856.3-95958.6" process $proc$libresoc.v:95856$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] attribute \src "libresoc.v:95857.5-95857.29" switch \initial attribute \src "libresoc.v:95857.9-95857.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub15_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end attribute \src "libresoc.v:95959.3-96061.6" process $proc$libresoc.v:95959$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0] attribute \src "libresoc.v:95960.5-95960.29" switch \initial attribute \src "libresoc.v:95960.9-95960.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub15_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0] end attribute \src "libresoc.v:96062.3-96164.6" process $proc$libresoc.v:96062$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] attribute \src "libresoc.v:96063.5-96063.29" switch \initial attribute \src "libresoc.v:96063.9-96063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 case assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end attribute \src "libresoc.v:96165.3-96267.6" process $proc$libresoc.v:96165$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] attribute \src "libresoc.v:96166.5-96166.29" switch \initial attribute \src "libresoc.v:96166.9-96166.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end attribute \src "libresoc.v:96268.3-96370.6" process $proc$libresoc.v:96268$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] attribute \src "libresoc.v:96269.5-96269.29" switch \initial attribute \src "libresoc.v:96269.9-96269.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end attribute \src "libresoc.v:96371.3-96473.6" process $proc$libresoc.v:96371$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] attribute \src "libresoc.v:96372.5-96372.29" switch \initial attribute \src "libresoc.v:96372.9-96372.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 case assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end attribute \src "libresoc.v:96474.3-96576.6" process $proc$libresoc.v:96474$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] attribute \src "libresoc.v:96475.5-96475.29" switch \initial attribute \src "libresoc.v:96475.9-96475.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_upd[1:0] 2'00 case assign $1\dec31_dec_sub15_upd[1:0] 2'00 end sync always update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end attribute \src "libresoc.v:96577.3-96679.6" process $proc$libresoc.v:96577$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] attribute \src "libresoc.v:96578.5-96578.29" switch \initial attribute \src "libresoc.v:96578.9-96578.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end attribute \src "libresoc.v:96680.3-96782.6" process $proc$libresoc.v:96680$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] attribute \src "libresoc.v:96681.5-96681.29" switch \initial attribute \src "libresoc.v:96681.9-96681.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end attribute \src "libresoc.v:96783.3-96885.6" process $proc$libresoc.v:96783$3952 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] attribute \src "libresoc.v:96784.5-96784.29" switch \initial attribute \src "libresoc.v:96784.9-96784.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 case assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end attribute \src "libresoc.v:96886.3-96988.6" process $proc$libresoc.v:96886$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] attribute \src "libresoc.v:96887.5-96887.29" switch \initial attribute \src "libresoc.v:96887.9-96887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end attribute \src "libresoc.v:96989.3-97091.6" process $proc$libresoc.v:96989$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] attribute \src "libresoc.v:96990.5-96990.29" switch \initial attribute \src "libresoc.v:96990.9-96990.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end attribute \src "libresoc.v:97092.3-97194.6" process $proc$libresoc.v:97092$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] attribute \src "libresoc.v:97093.5-97093.29" switch \initial attribute \src "libresoc.v:97093.9-97093.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end attribute \src "libresoc.v:97195.3-97297.6" process $proc$libresoc.v:97195$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] attribute \src "libresoc.v:97196.5-97196.29" switch \initial attribute \src "libresoc.v:97196.9-97196.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_br[0:0] 1'0 case assign $1\dec31_dec_sub15_br[0:0] 1'0 end sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end attribute \src "libresoc.v:97298.3-97400.6" process $proc$libresoc.v:97298$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] attribute \src "libresoc.v:97299.5-97299.29" switch \initial attribute \src "libresoc.v:97299.9-97299.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end attribute \src "libresoc.v:97401.3-97503.6" process $proc$libresoc.v:97401$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] attribute \src "libresoc.v:97402.5-97402.29" switch \initial attribute \src "libresoc.v:97402.9-97402.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end attribute \src "libresoc.v:97504.3-97606.6" process $proc$libresoc.v:97504$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] attribute \src "libresoc.v:97505.5-97505.29" switch \initial attribute \src "libresoc.v:97505.9-97505.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_form[4:0] 5'10010 case assign $1\dec31_dec_sub15_form[4:0] 5'00000 end sync always update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end attribute \src "libresoc.v:97607.3-97709.6" process $proc$libresoc.v:97607$3960 assign { } { } assign { } { } assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] attribute \src "libresoc.v:97608.5-97608.29" switch \initial attribute \src "libresoc.v:97608.9-97608.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end attribute \src "libresoc.v:97710.3-97812.6" process $proc$libresoc.v:97710$3961 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] attribute \src "libresoc.v:97711.5-97711.29" switch \initial attribute \src "libresoc.v:97711.9-97711.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sgn[0:0] 1'0 case assign $1\dec31_dec_sub15_sgn[0:0] 1'0 end sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end attribute \src "libresoc.v:97813.3-97915.6" process $proc$libresoc.v:97813$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] attribute \src "libresoc.v:97814.5-97814.29" switch \initial attribute \src "libresoc.v:97814.9-97814.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_lk[0:0] 1'0 case assign $1\dec31_dec_sub15_lk[0:0] 1'0 end sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end attribute \src "libresoc.v:97916.3-98018.6" process $proc$libresoc.v:97916$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] attribute \src "libresoc.v:97917.5-97917.29" switch \initial attribute \src "libresoc.v:97917.9-97917.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 case assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end attribute \src "libresoc.v:98019.3-98121.6" process $proc$libresoc.v:98019$3964 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] attribute \src "libresoc.v:98020.5-98020.29" switch \initial attribute \src "libresoc.v:98020.9-98020.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 case assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end attribute \src "libresoc.v:98122.3-98224.6" process $proc$libresoc.v:98122$3965 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] attribute \src "libresoc.v:98123.5-98123.29" switch \initial attribute \src "libresoc.v:98123.9-98123.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 case assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end attribute \src "libresoc.v:98225.3-98327.6" process $proc$libresoc.v:98225$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] attribute \src "libresoc.v:98226.5-98226.29" switch \initial attribute \src "libresoc.v:98226.9-98226.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 case assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end attribute \src "libresoc.v:98328.3-98430.6" process $proc$libresoc.v:98328$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] attribute \src "libresoc.v:98329.5-98329.29" switch \initial attribute \src "libresoc.v:98329.9-98329.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end attribute \src "libresoc.v:98431.3-98533.6" process $proc$libresoc.v:98431$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] attribute \src "libresoc.v:98432.5-98432.29" switch \initial attribute \src "libresoc.v:98432.9-98432.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end attribute \src "libresoc.v:98534.3-98636.6" process $proc$libresoc.v:98534$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] attribute \src "libresoc.v:98535.5-98535.29" switch \initial attribute \src "libresoc.v:98535.9-98535.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub15_out_sel[2:0] 3'001 case assign $1\dec31_dec_sub15_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:98642.1-99322.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 attribute \src "libresoc.v:99261.3-99270.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] attribute \src "libresoc.v:99271.3-99280.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] attribute \src "libresoc.v:99141.3-99150.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] attribute \src "libresoc.v:99181.3-99190.6" wire $0\dec31_dec_sub16_br[0:0] attribute \src "libresoc.v:99001.3-99010.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] attribute \src "libresoc.v:99011.3-99020.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] attribute \src "libresoc.v:99131.3-99140.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] attribute \src "libresoc.v:99171.3-99180.6" wire $0\dec31_dec_sub16_cry_out[0:0] attribute \src "libresoc.v:99211.3-99220.6" wire width 5 $0\dec31_dec_sub16_form[4:0] attribute \src "libresoc.v:98991.3-99000.6" wire width 14 $0\dec31_dec_sub16_function_unit[13:0] attribute \src "libresoc.v:99281.3-99290.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] attribute \src "libresoc.v:99291.3-99300.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] attribute \src "libresoc.v:99301.3-99310.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] attribute \src "libresoc.v:99101.3-99110.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] attribute \src "libresoc.v:99151.3-99160.6" wire $0\dec31_dec_sub16_inv_a[0:0] attribute \src "libresoc.v:99161.3-99170.6" wire $0\dec31_dec_sub16_inv_out[0:0] attribute \src "libresoc.v:99221.3-99230.6" wire $0\dec31_dec_sub16_is_32b[0:0] attribute \src "libresoc.v:99091.3-99100.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] attribute \src "libresoc.v:99241.3-99250.6" wire $0\dec31_dec_sub16_lk[0:0] attribute \src "libresoc.v:99311.3-99320.6" wire width 3 $0\dec31_dec_sub16_out_sel[2:0] attribute \src "libresoc.v:99121.3-99130.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] attribute \src "libresoc.v:99201.3-99210.6" wire $0\dec31_dec_sub16_rsrv[0:0] attribute \src "libresoc.v:99251.3-99260.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] attribute \src "libresoc.v:99231.3-99240.6" wire $0\dec31_dec_sub16_sgn[0:0] attribute \src "libresoc.v:99191.3-99200.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] attribute \src "libresoc.v:99071.3-99080.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] attribute \src "libresoc.v:99081.3-99090.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] attribute \src "libresoc.v:99021.3-99030.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] attribute \src "libresoc.v:99031.3-99040.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] attribute \src "libresoc.v:99041.3-99050.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] attribute \src "libresoc.v:99061.3-99070.6" wire width 3 $0\dec31_dec_sub16_sv_out2[2:0] attribute \src "libresoc.v:99051.3-99060.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] attribute \src "libresoc.v:99111.3-99120.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] attribute \src "libresoc.v:98643.7-98643.20" wire $0\initial[0:0] attribute \src "libresoc.v:99261.3-99270.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] attribute \src "libresoc.v:99271.3-99280.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] attribute \src "libresoc.v:99141.3-99150.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] attribute \src "libresoc.v:99181.3-99190.6" wire $1\dec31_dec_sub16_br[0:0] attribute \src "libresoc.v:99001.3-99010.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] attribute \src "libresoc.v:99011.3-99020.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] attribute \src "libresoc.v:99131.3-99140.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] attribute \src "libresoc.v:99171.3-99180.6" wire $1\dec31_dec_sub16_cry_out[0:0] attribute \src "libresoc.v:99211.3-99220.6" wire width 5 $1\dec31_dec_sub16_form[4:0] attribute \src "libresoc.v:98991.3-99000.6" wire width 14 $1\dec31_dec_sub16_function_unit[13:0] attribute \src "libresoc.v:99281.3-99290.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] attribute \src "libresoc.v:99291.3-99300.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] attribute \src "libresoc.v:99301.3-99310.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] attribute \src "libresoc.v:99101.3-99110.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] attribute \src "libresoc.v:99151.3-99160.6" wire $1\dec31_dec_sub16_inv_a[0:0] attribute \src "libresoc.v:99161.3-99170.6" wire $1\dec31_dec_sub16_inv_out[0:0] attribute \src "libresoc.v:99221.3-99230.6" wire $1\dec31_dec_sub16_is_32b[0:0] attribute \src "libresoc.v:99091.3-99100.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] attribute \src "libresoc.v:99241.3-99250.6" wire $1\dec31_dec_sub16_lk[0:0] attribute \src "libresoc.v:99311.3-99320.6" wire width 3 $1\dec31_dec_sub16_out_sel[2:0] attribute \src "libresoc.v:99121.3-99130.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] attribute \src "libresoc.v:99201.3-99210.6" wire $1\dec31_dec_sub16_rsrv[0:0] attribute \src "libresoc.v:99251.3-99260.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] attribute \src "libresoc.v:99231.3-99240.6" wire $1\dec31_dec_sub16_sgn[0:0] attribute \src "libresoc.v:99191.3-99200.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] attribute \src "libresoc.v:99071.3-99080.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] attribute \src "libresoc.v:99081.3-99090.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] attribute \src "libresoc.v:99021.3-99030.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] attribute \src "libresoc.v:99031.3-99040.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] attribute \src "libresoc.v:99041.3-99050.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] attribute \src "libresoc.v:99061.3-99070.6" wire width 3 $1\dec31_dec_sub16_sv_out2[2:0] attribute \src "libresoc.v:99051.3-99060.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] attribute \src "libresoc.v:99111.3-99120.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub16_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub16_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub16_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub16_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub16_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub16_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub16_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub16_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub16_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub16_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub16_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub16_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub16_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub16_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub16_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub16_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub16_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub16_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub16_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub16_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub16_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub16_upd attribute \src "libresoc.v:98643.7-98643.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:98643.7-98643.20" process $proc$libresoc.v:98643$4004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:98991.3-99000.6" process $proc$libresoc.v:98991$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] attribute \src "libresoc.v:98992.5-98992.29" switch \initial attribute \src "libresoc.v:98992.9-98992.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000001000000 case assign $1\dec31_dec_sub16_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end attribute \src "libresoc.v:99001.3-99010.6" process $proc$libresoc.v:99001$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] attribute \src "libresoc.v:99002.5-99002.29" switch \initial attribute \src "libresoc.v:99002.9-99002.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 case assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end attribute \src "libresoc.v:99011.3-99020.6" process $proc$libresoc.v:99011$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] attribute \src "libresoc.v:99012.5-99012.29" switch \initial attribute \src "libresoc.v:99012.9-99012.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 case assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end attribute \src "libresoc.v:99021.3-99030.6" process $proc$libresoc.v:99021$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] attribute \src "libresoc.v:99022.5-99022.29" switch \initial attribute \src "libresoc.v:99022.9-99022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub16_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end attribute \src "libresoc.v:99031.3-99040.6" process $proc$libresoc.v:99031$3975 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] attribute \src "libresoc.v:99032.5-99032.29" switch \initial attribute \src "libresoc.v:99032.9-99032.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end attribute \src "libresoc.v:99041.3-99050.6" process $proc$libresoc.v:99041$3976 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] attribute \src "libresoc.v:99042.5-99042.29" switch \initial attribute \src "libresoc.v:99042.9-99042.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end attribute \src "libresoc.v:99051.3-99060.6" process $proc$libresoc.v:99051$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] attribute \src "libresoc.v:99052.5-99052.29" switch \initial attribute \src "libresoc.v:99052.9-99052.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 case assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end attribute \src "libresoc.v:99061.3-99070.6" process $proc$libresoc.v:99061$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0] attribute \src "libresoc.v:99062.5-99062.29" switch \initial attribute \src "libresoc.v:99062.9-99062.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub16_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0] end attribute \src "libresoc.v:99071.3-99080.6" process $proc$libresoc.v:99071$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] attribute \src "libresoc.v:99072.5-99072.29" switch \initial attribute \src "libresoc.v:99072.9-99072.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end attribute \src "libresoc.v:99081.3-99090.6" process $proc$libresoc.v:99081$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] attribute \src "libresoc.v:99082.5-99082.29" switch \initial attribute \src "libresoc.v:99082.9-99082.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end attribute \src "libresoc.v:99091.3-99100.6" process $proc$libresoc.v:99091$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] attribute \src "libresoc.v:99092.5-99092.29" switch \initial attribute \src "libresoc.v:99092.9-99092.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end attribute \src "libresoc.v:99101.3-99110.6" process $proc$libresoc.v:99101$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] attribute \src "libresoc.v:99102.5-99102.29" switch \initial attribute \src "libresoc.v:99102.9-99102.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 case assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end attribute \src "libresoc.v:99111.3-99120.6" process $proc$libresoc.v:99111$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] attribute \src "libresoc.v:99112.5-99112.29" switch \initial attribute \src "libresoc.v:99112.9-99112.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_upd[1:0] 2'00 case assign $1\dec31_dec_sub16_upd[1:0] 2'00 end sync always update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end attribute \src "libresoc.v:99121.3-99130.6" process $proc$libresoc.v:99121$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] attribute \src "libresoc.v:99122.5-99122.29" switch \initial attribute \src "libresoc.v:99122.9-99122.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end attribute \src "libresoc.v:99131.3-99140.6" process $proc$libresoc.v:99131$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] attribute \src "libresoc.v:99132.5-99132.29" switch \initial attribute \src "libresoc.v:99132.9-99132.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end attribute \src "libresoc.v:99141.3-99150.6" process $proc$libresoc.v:99141$3986 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] attribute \src "libresoc.v:99142.5-99142.29" switch \initial attribute \src "libresoc.v:99142.9-99142.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 case assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end attribute \src "libresoc.v:99151.3-99160.6" process $proc$libresoc.v:99151$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] attribute \src "libresoc.v:99152.5-99152.29" switch \initial attribute \src "libresoc.v:99152.9-99152.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end attribute \src "libresoc.v:99161.3-99170.6" process $proc$libresoc.v:99161$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] attribute \src "libresoc.v:99162.5-99162.29" switch \initial attribute \src "libresoc.v:99162.9-99162.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end attribute \src "libresoc.v:99171.3-99180.6" process $proc$libresoc.v:99171$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] attribute \src "libresoc.v:99172.5-99172.29" switch \initial attribute \src "libresoc.v:99172.9-99172.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end attribute \src "libresoc.v:99181.3-99190.6" process $proc$libresoc.v:99181$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] attribute \src "libresoc.v:99182.5-99182.29" switch \initial attribute \src "libresoc.v:99182.9-99182.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_br[0:0] 1'0 case assign $1\dec31_dec_sub16_br[0:0] 1'0 end sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end attribute \src "libresoc.v:99191.3-99200.6" process $proc$libresoc.v:99191$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] attribute \src "libresoc.v:99192.5-99192.29" switch \initial attribute \src "libresoc.v:99192.9-99192.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end attribute \src "libresoc.v:99201.3-99210.6" process $proc$libresoc.v:99201$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] attribute \src "libresoc.v:99202.5-99202.29" switch \initial attribute \src "libresoc.v:99202.9-99202.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end attribute \src "libresoc.v:99211.3-99220.6" process $proc$libresoc.v:99211$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] attribute \src "libresoc.v:99212.5-99212.29" switch \initial attribute \src "libresoc.v:99212.9-99212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_form[4:0] 5'01010 case assign $1\dec31_dec_sub16_form[4:0] 5'00000 end sync always update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end attribute \src "libresoc.v:99221.3-99230.6" process $proc$libresoc.v:99221$3994 assign { } { } assign { } { } assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] attribute \src "libresoc.v:99222.5-99222.29" switch \initial attribute \src "libresoc.v:99222.9-99222.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end attribute \src "libresoc.v:99231.3-99240.6" process $proc$libresoc.v:99231$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] attribute \src "libresoc.v:99232.5-99232.29" switch \initial attribute \src "libresoc.v:99232.9-99232.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sgn[0:0] 1'0 case assign $1\dec31_dec_sub16_sgn[0:0] 1'0 end sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end attribute \src "libresoc.v:99241.3-99250.6" process $proc$libresoc.v:99241$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] attribute \src "libresoc.v:99242.5-99242.29" switch \initial attribute \src "libresoc.v:99242.9-99242.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_lk[0:0] 1'0 case assign $1\dec31_dec_sub16_lk[0:0] 1'0 end sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end attribute \src "libresoc.v:99251.3-99260.6" process $proc$libresoc.v:99251$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] attribute \src "libresoc.v:99252.5-99252.29" switch \initial attribute \src "libresoc.v:99252.9-99252.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end attribute \src "libresoc.v:99261.3-99270.6" process $proc$libresoc.v:99261$3998 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] attribute \src "libresoc.v:99262.5-99262.29" switch \initial attribute \src "libresoc.v:99262.9-99262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'01 case assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end attribute \src "libresoc.v:99271.3-99280.6" process $proc$libresoc.v:99271$3999 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] attribute \src "libresoc.v:99272.5-99272.29" switch \initial attribute \src "libresoc.v:99272.9-99272.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end attribute \src "libresoc.v:99281.3-99290.6" process $proc$libresoc.v:99281$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] attribute \src "libresoc.v:99282.5-99282.29" switch \initial attribute \src "libresoc.v:99282.9-99282.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 case assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end attribute \src "libresoc.v:99291.3-99300.6" process $proc$libresoc.v:99291$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] attribute \src "libresoc.v:99292.5-99292.29" switch \initial attribute \src "libresoc.v:99292.9-99292.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 case assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end attribute \src "libresoc.v:99301.3-99310.6" process $proc$libresoc.v:99301$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] attribute \src "libresoc.v:99302.5-99302.29" switch \initial attribute \src "libresoc.v:99302.9-99302.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end attribute \src "libresoc.v:99311.3-99320.6" process $proc$libresoc.v:99311$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] attribute \src "libresoc.v:99312.5-99312.29" switch \initial attribute \src "libresoc.v:99312.9-99312.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 case assign $1\dec31_dec_sub16_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:99326.1-100402.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 attribute \src "libresoc.v:100269.3-100290.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] attribute \src "libresoc.v:100291.3-100312.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] attribute \src "libresoc.v:100005.3-100026.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] attribute \src "libresoc.v:100093.3-100114.6" wire $0\dec31_dec_sub18_br[0:0] attribute \src "libresoc.v:99697.3-99718.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] attribute \src "libresoc.v:99719.3-99740.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] attribute \src "libresoc.v:99983.3-100004.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] attribute \src "libresoc.v:100071.3-100092.6" wire $0\dec31_dec_sub18_cry_out[0:0] attribute \src "libresoc.v:100159.3-100180.6" wire width 5 $0\dec31_dec_sub18_form[4:0] attribute \src "libresoc.v:99675.3-99696.6" wire width 14 $0\dec31_dec_sub18_function_unit[13:0] attribute \src "libresoc.v:100313.3-100334.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] attribute \src "libresoc.v:100335.3-100356.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] attribute \src "libresoc.v:100357.3-100378.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] attribute \src "libresoc.v:99917.3-99938.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] attribute \src "libresoc.v:100027.3-100048.6" wire $0\dec31_dec_sub18_inv_a[0:0] attribute \src "libresoc.v:100049.3-100070.6" wire $0\dec31_dec_sub18_inv_out[0:0] attribute \src "libresoc.v:100181.3-100202.6" wire $0\dec31_dec_sub18_is_32b[0:0] attribute \src "libresoc.v:99895.3-99916.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] attribute \src "libresoc.v:100225.3-100246.6" wire $0\dec31_dec_sub18_lk[0:0] attribute \src "libresoc.v:100379.3-100400.6" wire width 3 $0\dec31_dec_sub18_out_sel[2:0] attribute \src "libresoc.v:99961.3-99982.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] attribute \src "libresoc.v:100137.3-100158.6" wire $0\dec31_dec_sub18_rsrv[0:0] attribute \src "libresoc.v:100247.3-100268.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] attribute \src "libresoc.v:100203.3-100224.6" wire $0\dec31_dec_sub18_sgn[0:0] attribute \src "libresoc.v:100115.3-100136.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] attribute \src "libresoc.v:99851.3-99872.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] attribute \src "libresoc.v:99873.3-99894.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] attribute \src "libresoc.v:99741.3-99762.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] attribute \src "libresoc.v:99763.3-99784.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] attribute \src "libresoc.v:99785.3-99806.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] attribute \src "libresoc.v:99829.3-99850.6" wire width 3 $0\dec31_dec_sub18_sv_out2[2:0] attribute \src "libresoc.v:99807.3-99828.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] attribute \src "libresoc.v:99939.3-99960.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] attribute \src "libresoc.v:99327.7-99327.20" wire $0\initial[0:0] attribute \src "libresoc.v:100269.3-100290.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] attribute \src "libresoc.v:100291.3-100312.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] attribute \src "libresoc.v:100005.3-100026.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] attribute \src "libresoc.v:100093.3-100114.6" wire $1\dec31_dec_sub18_br[0:0] attribute \src "libresoc.v:99697.3-99718.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] attribute \src "libresoc.v:99719.3-99740.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] attribute \src "libresoc.v:99983.3-100004.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] attribute \src "libresoc.v:100071.3-100092.6" wire $1\dec31_dec_sub18_cry_out[0:0] attribute \src "libresoc.v:100159.3-100180.6" wire width 5 $1\dec31_dec_sub18_form[4:0] attribute \src "libresoc.v:99675.3-99696.6" wire width 14 $1\dec31_dec_sub18_function_unit[13:0] attribute \src "libresoc.v:100313.3-100334.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] attribute \src "libresoc.v:100335.3-100356.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] attribute \src "libresoc.v:100357.3-100378.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] attribute \src "libresoc.v:99917.3-99938.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] attribute \src "libresoc.v:100027.3-100048.6" wire $1\dec31_dec_sub18_inv_a[0:0] attribute \src "libresoc.v:100049.3-100070.6" wire $1\dec31_dec_sub18_inv_out[0:0] attribute \src "libresoc.v:100181.3-100202.6" wire $1\dec31_dec_sub18_is_32b[0:0] attribute \src "libresoc.v:99895.3-99916.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] attribute \src "libresoc.v:100225.3-100246.6" wire $1\dec31_dec_sub18_lk[0:0] attribute \src "libresoc.v:100379.3-100400.6" wire width 3 $1\dec31_dec_sub18_out_sel[2:0] attribute \src "libresoc.v:99961.3-99982.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] attribute \src "libresoc.v:100137.3-100158.6" wire $1\dec31_dec_sub18_rsrv[0:0] attribute \src "libresoc.v:100247.3-100268.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] attribute \src "libresoc.v:100203.3-100224.6" wire $1\dec31_dec_sub18_sgn[0:0] attribute \src "libresoc.v:100115.3-100136.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] attribute \src "libresoc.v:99851.3-99872.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] attribute \src "libresoc.v:99873.3-99894.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] attribute \src "libresoc.v:99741.3-99762.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] attribute \src "libresoc.v:99763.3-99784.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] attribute \src "libresoc.v:99785.3-99806.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] attribute \src "libresoc.v:99829.3-99850.6" wire width 3 $1\dec31_dec_sub18_sv_out2[2:0] attribute \src "libresoc.v:99807.3-99828.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] attribute \src "libresoc.v:99939.3-99960.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub18_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub18_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub18_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub18_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub18_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub18_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub18_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub18_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub18_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub18_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub18_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub18_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub18_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub18_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub18_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub18_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub18_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub18_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub18_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub18_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub18_upd attribute \src "libresoc.v:99327.7-99327.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:100005.3-100026.6" process $proc$libresoc.v:100005$4020 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] attribute \src "libresoc.v:100006.5-100006.29" switch \initial attribute \src "libresoc.v:100006.9-100006.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011110 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001110 case assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end attribute \src "libresoc.v:100027.3-100048.6" process $proc$libresoc.v:100027$4021 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] attribute \src "libresoc.v:100028.5-100028.29" switch \initial attribute \src "libresoc.v:100028.9-100028.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end attribute \src "libresoc.v:100049.3-100070.6" process $proc$libresoc.v:100049$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] attribute \src "libresoc.v:100050.5-100050.29" switch \initial attribute \src "libresoc.v:100050.9-100050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end attribute \src "libresoc.v:100071.3-100092.6" process $proc$libresoc.v:100071$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] attribute \src "libresoc.v:100072.5-100072.29" switch \initial attribute \src "libresoc.v:100072.9-100072.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end attribute \src "libresoc.v:100093.3-100114.6" process $proc$libresoc.v:100093$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] attribute \src "libresoc.v:100094.5-100094.29" switch \initial attribute \src "libresoc.v:100094.9-100094.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_br[0:0] 1'0 case assign $1\dec31_dec_sub18_br[0:0] 1'0 end sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end attribute \src "libresoc.v:100115.3-100136.6" process $proc$libresoc.v:100115$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] attribute \src "libresoc.v:100116.5-100116.29" switch \initial attribute \src "libresoc.v:100116.9-100116.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end attribute \src "libresoc.v:100137.3-100158.6" process $proc$libresoc.v:100137$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] attribute \src "libresoc.v:100138.5-100138.29" switch \initial attribute \src "libresoc.v:100138.9-100138.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end attribute \src "libresoc.v:100159.3-100180.6" process $proc$libresoc.v:100159$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] attribute \src "libresoc.v:100160.5-100160.29" switch \initial attribute \src "libresoc.v:100160.9-100160.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_form[4:0] 5'01000 case assign $1\dec31_dec_sub18_form[4:0] 5'00000 end sync always update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end attribute \src "libresoc.v:100181.3-100202.6" process $proc$libresoc.v:100181$4028 assign { } { } assign { } { } assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] attribute \src "libresoc.v:100182.5-100182.29" switch \initial attribute \src "libresoc.v:100182.9-100182.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end attribute \src "libresoc.v:100203.3-100224.6" process $proc$libresoc.v:100203$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] attribute \src "libresoc.v:100204.5-100204.29" switch \initial attribute \src "libresoc.v:100204.9-100204.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sgn[0:0] 1'0 case assign $1\dec31_dec_sub18_sgn[0:0] 1'0 end sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end attribute \src "libresoc.v:100225.3-100246.6" process $proc$libresoc.v:100225$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] attribute \src "libresoc.v:100226.5-100226.29" switch \initial attribute \src "libresoc.v:100226.9-100226.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_lk[0:0] 1'0 case assign $1\dec31_dec_sub18_lk[0:0] 1'0 end sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end attribute \src "libresoc.v:100247.3-100268.6" process $proc$libresoc.v:100247$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] attribute \src "libresoc.v:100248.5-100248.29" switch \initial attribute \src "libresoc.v:100248.9-100248.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end attribute \src "libresoc.v:100269.3-100290.6" process $proc$libresoc.v:100269$4032 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] attribute \src "libresoc.v:100270.5-100270.29" switch \initial attribute \src "libresoc.v:100270.9-100270.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 case assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end attribute \src "libresoc.v:100291.3-100312.6" process $proc$libresoc.v:100291$4033 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] attribute \src "libresoc.v:100292.5-100292.29" switch \initial attribute \src "libresoc.v:100292.9-100292.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 case assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end attribute \src "libresoc.v:100313.3-100334.6" process $proc$libresoc.v:100313$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] attribute \src "libresoc.v:100314.5-100314.29" switch \initial attribute \src "libresoc.v:100314.9-100314.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 case assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end attribute \src "libresoc.v:100335.3-100356.6" process $proc$libresoc.v:100335$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] attribute \src "libresoc.v:100336.5-100336.29" switch \initial attribute \src "libresoc.v:100336.9-100336.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end attribute \src "libresoc.v:100357.3-100378.6" process $proc$libresoc.v:100357$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] attribute \src "libresoc.v:100358.5-100358.29" switch \initial attribute \src "libresoc.v:100358.9-100358.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end attribute \src "libresoc.v:100379.3-100400.6" process $proc$libresoc.v:100379$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] attribute \src "libresoc.v:100380.5-100380.29" switch \initial attribute \src "libresoc.v:100380.9-100380.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 case assign $1\dec31_dec_sub18_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end attribute \src "libresoc.v:99327.7-99327.20" process $proc$libresoc.v:99327$4038 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:99675.3-99696.6" process $proc$libresoc.v:99675$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] attribute \src "libresoc.v:99676.5-99676.29" switch \initial attribute \src "libresoc.v:99676.9-99676.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 case assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] end attribute \src "libresoc.v:99697.3-99718.6" process $proc$libresoc.v:99697$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] attribute \src "libresoc.v:99698.5-99698.29" switch \initial attribute \src "libresoc.v:99698.9-99698.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end attribute \src "libresoc.v:99719.3-99740.6" process $proc$libresoc.v:99719$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] attribute \src "libresoc.v:99720.5-99720.29" switch \initial attribute \src "libresoc.v:99720.9-99720.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end attribute \src "libresoc.v:99741.3-99762.6" process $proc$libresoc.v:99741$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] attribute \src "libresoc.v:99742.5-99742.29" switch \initial attribute \src "libresoc.v:99742.9-99742.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 case assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end attribute \src "libresoc.v:99763.3-99784.6" process $proc$libresoc.v:99763$4009 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] attribute \src "libresoc.v:99764.5-99764.29" switch \initial attribute \src "libresoc.v:99764.9-99764.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end attribute \src "libresoc.v:99785.3-99806.6" process $proc$libresoc.v:99785$4010 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] attribute \src "libresoc.v:99786.5-99786.29" switch \initial attribute \src "libresoc.v:99786.9-99786.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end attribute \src "libresoc.v:99807.3-99828.6" process $proc$libresoc.v:99807$4011 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] attribute \src "libresoc.v:99808.5-99808.29" switch \initial attribute \src "libresoc.v:99808.9-99808.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 case assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] end attribute \src "libresoc.v:99829.3-99850.6" process $proc$libresoc.v:99829$4012 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] attribute \src "libresoc.v:99830.5-99830.29" switch \initial attribute \src "libresoc.v:99830.9-99830.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub18_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] end attribute \src "libresoc.v:99851.3-99872.6" process $proc$libresoc.v:99851$4013 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] attribute \src "libresoc.v:99852.5-99852.29" switch \initial attribute \src "libresoc.v:99852.9-99852.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] end attribute \src "libresoc.v:99873.3-99894.6" process $proc$libresoc.v:99873$4014 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] attribute \src "libresoc.v:99874.5-99874.29" switch \initial attribute \src "libresoc.v:99874.9-99874.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] end attribute \src "libresoc.v:99895.3-99916.6" process $proc$libresoc.v:99895$4015 assign { } { } assign { } { } assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] attribute \src "libresoc.v:99896.5-99896.29" switch \initial attribute \src "libresoc.v:99896.9-99896.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end attribute \src "libresoc.v:99917.3-99938.6" process $proc$libresoc.v:99917$4016 assign { } { } assign { } { } assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] attribute \src "libresoc.v:99918.5-99918.29" switch \initial attribute \src "libresoc.v:99918.9-99918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 case assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end attribute \src "libresoc.v:99939.3-99960.6" process $proc$libresoc.v:99939$4017 assign { } { } assign { } { } assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] attribute \src "libresoc.v:99940.5-99940.29" switch \initial attribute \src "libresoc.v:99940.9-99940.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_upd[1:0] 2'00 case assign $1\dec31_dec_sub18_upd[1:0] 2'00 end sync always update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end attribute \src "libresoc.v:99961.3-99982.6" process $proc$libresoc.v:99961$4018 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] attribute \src "libresoc.v:99962.5-99962.29" switch \initial attribute \src "libresoc.v:99962.9-99962.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end attribute \src "libresoc.v:99983.3-100004.6" process $proc$libresoc.v:99983$4019 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] attribute \src "libresoc.v:99984.5-99984.29" switch \initial attribute \src "libresoc.v:99984.9-99984.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:100406.1-101383.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 attribute \src "libresoc.v:101268.3-101286.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] attribute \src "libresoc.v:101287.3-101305.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] attribute \src "libresoc.v:101040.3-101058.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] attribute \src "libresoc.v:101116.3-101134.6" wire $0\dec31_dec_sub19_br[0:0] attribute \src "libresoc.v:100774.3-100792.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:100793.3-100811.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:101021.3-101039.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] attribute \src "libresoc.v:101097.3-101115.6" wire $0\dec31_dec_sub19_cry_out[0:0] attribute \src "libresoc.v:101173.3-101191.6" wire width 5 $0\dec31_dec_sub19_form[4:0] attribute \src "libresoc.v:100755.3-100773.6" wire width 14 $0\dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:101306.3-101324.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] attribute \src "libresoc.v:101325.3-101343.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] attribute \src "libresoc.v:101344.3-101362.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] attribute \src "libresoc.v:100964.3-100982.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:101059.3-101077.6" wire $0\dec31_dec_sub19_inv_a[0:0] attribute \src "libresoc.v:101078.3-101096.6" wire $0\dec31_dec_sub19_inv_out[0:0] attribute \src "libresoc.v:101192.3-101210.6" wire $0\dec31_dec_sub19_is_32b[0:0] attribute \src "libresoc.v:100945.3-100963.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] attribute \src "libresoc.v:101230.3-101248.6" wire $0\dec31_dec_sub19_lk[0:0] attribute \src "libresoc.v:101363.3-101381.6" wire width 3 $0\dec31_dec_sub19_out_sel[2:0] attribute \src "libresoc.v:101002.3-101020.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] attribute \src "libresoc.v:101154.3-101172.6" wire $0\dec31_dec_sub19_rsrv[0:0] attribute \src "libresoc.v:101249.3-101267.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] attribute \src "libresoc.v:101211.3-101229.6" wire $0\dec31_dec_sub19_sgn[0:0] attribute \src "libresoc.v:101135.3-101153.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] attribute \src "libresoc.v:100907.3-100925.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] attribute \src "libresoc.v:100926.3-100944.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] attribute \src "libresoc.v:100812.3-100830.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] attribute \src "libresoc.v:100831.3-100849.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] attribute \src "libresoc.v:100850.3-100868.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] attribute \src "libresoc.v:100888.3-100906.6" wire width 3 $0\dec31_dec_sub19_sv_out2[2:0] attribute \src "libresoc.v:100869.3-100887.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] attribute \src "libresoc.v:100983.3-101001.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] attribute \src "libresoc.v:100407.7-100407.20" wire $0\initial[0:0] attribute \src "libresoc.v:101268.3-101286.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] attribute \src "libresoc.v:101287.3-101305.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] attribute \src "libresoc.v:101040.3-101058.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] attribute \src "libresoc.v:101116.3-101134.6" wire $1\dec31_dec_sub19_br[0:0] attribute \src "libresoc.v:100774.3-100792.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:100793.3-100811.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:101021.3-101039.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] attribute \src "libresoc.v:101097.3-101115.6" wire $1\dec31_dec_sub19_cry_out[0:0] attribute \src "libresoc.v:101173.3-101191.6" wire width 5 $1\dec31_dec_sub19_form[4:0] attribute \src "libresoc.v:100755.3-100773.6" wire width 14 $1\dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:101306.3-101324.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] attribute \src "libresoc.v:101325.3-101343.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] attribute \src "libresoc.v:101344.3-101362.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] attribute \src "libresoc.v:100964.3-100982.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:101059.3-101077.6" wire $1\dec31_dec_sub19_inv_a[0:0] attribute \src "libresoc.v:101078.3-101096.6" wire $1\dec31_dec_sub19_inv_out[0:0] attribute \src "libresoc.v:101192.3-101210.6" wire $1\dec31_dec_sub19_is_32b[0:0] attribute \src "libresoc.v:100945.3-100963.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] attribute \src "libresoc.v:101230.3-101248.6" wire $1\dec31_dec_sub19_lk[0:0] attribute \src "libresoc.v:101363.3-101381.6" wire width 3 $1\dec31_dec_sub19_out_sel[2:0] attribute \src "libresoc.v:101002.3-101020.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] attribute \src "libresoc.v:101154.3-101172.6" wire $1\dec31_dec_sub19_rsrv[0:0] attribute \src "libresoc.v:101249.3-101267.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] attribute \src "libresoc.v:101211.3-101229.6" wire $1\dec31_dec_sub19_sgn[0:0] attribute \src "libresoc.v:101135.3-101153.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] attribute \src "libresoc.v:100907.3-100925.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] attribute \src "libresoc.v:100926.3-100944.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] attribute \src "libresoc.v:100812.3-100830.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] attribute \src "libresoc.v:100831.3-100849.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] attribute \src "libresoc.v:100850.3-100868.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] attribute \src "libresoc.v:100888.3-100906.6" wire width 3 $1\dec31_dec_sub19_sv_out2[2:0] attribute \src "libresoc.v:100869.3-100887.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] attribute \src "libresoc.v:100983.3-101001.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub19_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub19_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub19_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub19_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub19_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub19_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub19_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub19_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub19_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub19_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub19_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub19_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub19_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub19_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub19_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub19_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub19_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub19_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub19_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub19_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub19_upd attribute \src "libresoc.v:100407.7-100407.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:100407.7-100407.20" process $proc$libresoc.v:100407$4072 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:100755.3-100773.6" process $proc$libresoc.v:100755$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] attribute \src "libresoc.v:100756.5-100756.29" switch \initial attribute \src "libresoc.v:100756.9-100756.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000001000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_function_unit[13:0] 14'00010000000000 case assign $1\dec31_dec_sub19_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] end attribute \src "libresoc.v:100774.3-100792.6" process $proc$libresoc.v:100774$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] attribute \src "libresoc.v:100775.5-100775.29" switch \initial attribute \src "libresoc.v:100775.9-100775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end attribute \src "libresoc.v:100793.3-100811.6" process $proc$libresoc.v:100793$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] attribute \src "libresoc.v:100794.5-100794.29" switch \initial attribute \src "libresoc.v:100794.9-100794.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end attribute \src "libresoc.v:100812.3-100830.6" process $proc$libresoc.v:100812$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] attribute \src "libresoc.v:100813.5-100813.29" switch \initial attribute \src "libresoc.v:100813.9-100813.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] end attribute \src "libresoc.v:100831.3-100849.6" process $proc$libresoc.v:100831$4043 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] attribute \src "libresoc.v:100832.5-100832.29" switch \initial attribute \src "libresoc.v:100832.9-100832.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] end attribute \src "libresoc.v:100850.3-100868.6" process $proc$libresoc.v:100850$4044 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] attribute \src "libresoc.v:100851.5-100851.29" switch \initial attribute \src "libresoc.v:100851.9-100851.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end attribute \src "libresoc.v:100869.3-100887.6" process $proc$libresoc.v:100869$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] attribute \src "libresoc.v:100870.5-100870.29" switch \initial attribute \src "libresoc.v:100870.9-100870.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] end attribute \src "libresoc.v:100888.3-100906.6" process $proc$libresoc.v:100888$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0] attribute \src "libresoc.v:100889.5-100889.29" switch \initial attribute \src "libresoc.v:100889.9-100889.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub19_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0] end attribute \src "libresoc.v:100907.3-100925.6" process $proc$libresoc.v:100907$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] attribute \src "libresoc.v:100908.5-100908.29" switch \initial attribute \src "libresoc.v:100908.9-100908.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] end attribute \src "libresoc.v:100926.3-100944.6" process $proc$libresoc.v:100926$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] attribute \src "libresoc.v:100927.5-100927.29" switch \initial attribute \src "libresoc.v:100927.9-100927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end attribute \src "libresoc.v:100945.3-100963.6" process $proc$libresoc.v:100945$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] attribute \src "libresoc.v:100946.5-100946.29" switch \initial attribute \src "libresoc.v:100946.9-100946.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end attribute \src "libresoc.v:100964.3-100982.6" process $proc$libresoc.v:100964$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] attribute \src "libresoc.v:100965.5-100965.29" switch \initial attribute \src "libresoc.v:100965.9-100965.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 case assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end attribute \src "libresoc.v:100983.3-101001.6" process $proc$libresoc.v:100983$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] attribute \src "libresoc.v:100984.5-100984.29" switch \initial attribute \src "libresoc.v:100984.9-100984.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_upd[1:0] 2'00 case assign $1\dec31_dec_sub19_upd[1:0] 2'00 end sync always update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end attribute \src "libresoc.v:101002.3-101020.6" process $proc$libresoc.v:101002$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] attribute \src "libresoc.v:101003.5-101003.29" switch \initial attribute \src "libresoc.v:101003.9-101003.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end attribute \src "libresoc.v:101021.3-101039.6" process $proc$libresoc.v:101021$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] attribute \src "libresoc.v:101022.5-101022.29" switch \initial attribute \src "libresoc.v:101022.9-101022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end attribute \src "libresoc.v:101040.3-101058.6" process $proc$libresoc.v:101040$4054 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] attribute \src "libresoc.v:101041.5-101041.29" switch \initial attribute \src "libresoc.v:101041.9-101041.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 case assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end attribute \src "libresoc.v:101059.3-101077.6" process $proc$libresoc.v:101059$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] attribute \src "libresoc.v:101060.5-101060.29" switch \initial attribute \src "libresoc.v:101060.9-101060.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end attribute \src "libresoc.v:101078.3-101096.6" process $proc$libresoc.v:101078$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] attribute \src "libresoc.v:101079.5-101079.29" switch \initial attribute \src "libresoc.v:101079.9-101079.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end attribute \src "libresoc.v:101097.3-101115.6" process $proc$libresoc.v:101097$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] attribute \src "libresoc.v:101098.5-101098.29" switch \initial attribute \src "libresoc.v:101098.9-101098.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end attribute \src "libresoc.v:101116.3-101134.6" process $proc$libresoc.v:101116$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] attribute \src "libresoc.v:101117.5-101117.29" switch \initial attribute \src "libresoc.v:101117.9-101117.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_br[0:0] 1'0 case assign $1\dec31_dec_sub19_br[0:0] 1'0 end sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end attribute \src "libresoc.v:101135.3-101153.6" process $proc$libresoc.v:101135$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] attribute \src "libresoc.v:101136.5-101136.29" switch \initial attribute \src "libresoc.v:101136.9-101136.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end attribute \src "libresoc.v:101154.3-101172.6" process $proc$libresoc.v:101154$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] attribute \src "libresoc.v:101155.5-101155.29" switch \initial attribute \src "libresoc.v:101155.9-101155.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end attribute \src "libresoc.v:101173.3-101191.6" process $proc$libresoc.v:101173$4061 assign { } { } assign { } { } assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] attribute \src "libresoc.v:101174.5-101174.29" switch \initial attribute \src "libresoc.v:101174.9-101174.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_form[4:0] 5'01010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_form[4:0] 5'01010 case assign $1\dec31_dec_sub19_form[4:0] 5'00000 end sync always update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end attribute \src "libresoc.v:101192.3-101210.6" process $proc$libresoc.v:101192$4062 assign { } { } assign { } { } assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] attribute \src "libresoc.v:101193.5-101193.29" switch \initial attribute \src "libresoc.v:101193.9-101193.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end attribute \src "libresoc.v:101211.3-101229.6" process $proc$libresoc.v:101211$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] attribute \src "libresoc.v:101212.5-101212.29" switch \initial attribute \src "libresoc.v:101212.9-101212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sgn[0:0] 1'0 case assign $1\dec31_dec_sub19_sgn[0:0] 1'0 end sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end attribute \src "libresoc.v:101230.3-101248.6" process $proc$libresoc.v:101230$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] attribute \src "libresoc.v:101231.5-101231.29" switch \initial attribute \src "libresoc.v:101231.9-101231.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_lk[0:0] 1'0 case assign $1\dec31_dec_sub19_lk[0:0] 1'0 end sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end attribute \src "libresoc.v:101249.3-101267.6" process $proc$libresoc.v:101249$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] attribute \src "libresoc.v:101250.5-101250.29" switch \initial attribute \src "libresoc.v:101250.9-101250.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end attribute \src "libresoc.v:101268.3-101286.6" process $proc$libresoc.v:101268$4066 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] attribute \src "libresoc.v:101269.5-101269.29" switch \initial attribute \src "libresoc.v:101269.9-101269.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end attribute \src "libresoc.v:101287.3-101305.6" process $proc$libresoc.v:101287$4067 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] attribute \src "libresoc.v:101288.5-101288.29" switch \initial attribute \src "libresoc.v:101288.9-101288.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end attribute \src "libresoc.v:101306.3-101324.6" process $proc$libresoc.v:101306$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] attribute \src "libresoc.v:101307.5-101307.29" switch \initial attribute \src "libresoc.v:101307.9-101307.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 case assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end attribute \src "libresoc.v:101325.3-101343.6" process $proc$libresoc.v:101325$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] attribute \src "libresoc.v:101326.5-101326.29" switch \initial attribute \src "libresoc.v:101326.9-101326.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 case assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end attribute \src "libresoc.v:101344.3-101362.6" process $proc$libresoc.v:101344$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] attribute \src "libresoc.v:101345.5-101345.29" switch \initial attribute \src "libresoc.v:101345.9-101345.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end attribute \src "libresoc.v:101363.3-101381.6" process $proc$libresoc.v:101363$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] attribute \src "libresoc.v:101364.5-101364.29" switch \initial attribute \src "libresoc.v:101364.9-101364.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub19_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub19_out_sel[2:0] 3'011 case assign $1\dec31_dec_sub19_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:101387.1-102562.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 attribute \src "libresoc.v:102411.3-102435.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] attribute \src "libresoc.v:102436.3-102460.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] attribute \src "libresoc.v:102111.3-102135.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] attribute \src "libresoc.v:102211.3-102235.6" wire $0\dec31_dec_sub20_br[0:0] attribute \src "libresoc.v:101761.3-101785.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] attribute \src "libresoc.v:101786.3-101810.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] attribute \src "libresoc.v:102086.3-102110.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] attribute \src "libresoc.v:102186.3-102210.6" wire $0\dec31_dec_sub20_cry_out[0:0] attribute \src "libresoc.v:102286.3-102310.6" wire width 5 $0\dec31_dec_sub20_form[4:0] attribute \src "libresoc.v:101736.3-101760.6" wire width 14 $0\dec31_dec_sub20_function_unit[13:0] attribute \src "libresoc.v:102461.3-102485.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] attribute \src "libresoc.v:102486.3-102510.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] attribute \src "libresoc.v:102511.3-102535.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] attribute \src "libresoc.v:102011.3-102035.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] attribute \src "libresoc.v:102136.3-102160.6" wire $0\dec31_dec_sub20_inv_a[0:0] attribute \src "libresoc.v:102161.3-102185.6" wire $0\dec31_dec_sub20_inv_out[0:0] attribute \src "libresoc.v:102311.3-102335.6" wire $0\dec31_dec_sub20_is_32b[0:0] attribute \src "libresoc.v:101986.3-102010.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] attribute \src "libresoc.v:102361.3-102385.6" wire $0\dec31_dec_sub20_lk[0:0] attribute \src "libresoc.v:102536.3-102560.6" wire width 3 $0\dec31_dec_sub20_out_sel[2:0] attribute \src "libresoc.v:102061.3-102085.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] attribute \src "libresoc.v:102261.3-102285.6" wire $0\dec31_dec_sub20_rsrv[0:0] attribute \src "libresoc.v:102386.3-102410.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] attribute \src "libresoc.v:102336.3-102360.6" wire $0\dec31_dec_sub20_sgn[0:0] attribute \src "libresoc.v:102236.3-102260.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:101936.3-101960.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] attribute \src "libresoc.v:101961.3-101985.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] attribute \src "libresoc.v:101811.3-101835.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] attribute \src "libresoc.v:101836.3-101860.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] attribute \src "libresoc.v:101861.3-101885.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] attribute \src "libresoc.v:101911.3-101935.6" wire width 3 $0\dec31_dec_sub20_sv_out2[2:0] attribute \src "libresoc.v:101886.3-101910.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] attribute \src "libresoc.v:102036.3-102060.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] attribute \src "libresoc.v:101388.7-101388.20" wire $0\initial[0:0] attribute \src "libresoc.v:102411.3-102435.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] attribute \src "libresoc.v:102436.3-102460.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] attribute \src "libresoc.v:102111.3-102135.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] attribute \src "libresoc.v:102211.3-102235.6" wire $1\dec31_dec_sub20_br[0:0] attribute \src "libresoc.v:101761.3-101785.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] attribute \src "libresoc.v:101786.3-101810.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] attribute \src "libresoc.v:102086.3-102110.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] attribute \src "libresoc.v:102186.3-102210.6" wire $1\dec31_dec_sub20_cry_out[0:0] attribute \src "libresoc.v:102286.3-102310.6" wire width 5 $1\dec31_dec_sub20_form[4:0] attribute \src "libresoc.v:101736.3-101760.6" wire width 14 $1\dec31_dec_sub20_function_unit[13:0] attribute \src "libresoc.v:102461.3-102485.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] attribute \src "libresoc.v:102486.3-102510.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] attribute \src "libresoc.v:102511.3-102535.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] attribute \src "libresoc.v:102011.3-102035.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] attribute \src "libresoc.v:102136.3-102160.6" wire $1\dec31_dec_sub20_inv_a[0:0] attribute \src "libresoc.v:102161.3-102185.6" wire $1\dec31_dec_sub20_inv_out[0:0] attribute \src "libresoc.v:102311.3-102335.6" wire $1\dec31_dec_sub20_is_32b[0:0] attribute \src "libresoc.v:101986.3-102010.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] attribute \src "libresoc.v:102361.3-102385.6" wire $1\dec31_dec_sub20_lk[0:0] attribute \src "libresoc.v:102536.3-102560.6" wire width 3 $1\dec31_dec_sub20_out_sel[2:0] attribute \src "libresoc.v:102061.3-102085.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] attribute \src "libresoc.v:102261.3-102285.6" wire $1\dec31_dec_sub20_rsrv[0:0] attribute \src "libresoc.v:102386.3-102410.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] attribute \src "libresoc.v:102336.3-102360.6" wire $1\dec31_dec_sub20_sgn[0:0] attribute \src "libresoc.v:102236.3-102260.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:101936.3-101960.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] attribute \src "libresoc.v:101961.3-101985.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] attribute \src "libresoc.v:101811.3-101835.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] attribute \src "libresoc.v:101836.3-101860.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] attribute \src "libresoc.v:101861.3-101885.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] attribute \src "libresoc.v:101911.3-101935.6" wire width 3 $1\dec31_dec_sub20_sv_out2[2:0] attribute \src "libresoc.v:101886.3-101910.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] attribute \src "libresoc.v:102036.3-102060.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub20_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub20_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub20_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub20_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub20_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub20_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub20_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub20_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub20_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub20_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub20_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub20_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub20_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub20_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub20_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub20_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub20_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub20_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub20_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub20_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub20_upd attribute \src "libresoc.v:101388.7-101388.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:101388.7-101388.20" process $proc$libresoc.v:101388$4106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:101736.3-101760.6" process $proc$libresoc.v:101736$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] attribute \src "libresoc.v:101737.5-101737.29" switch \initial attribute \src "libresoc.v:101737.9-101737.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000100 case assign $1\dec31_dec_sub20_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end attribute \src "libresoc.v:101761.3-101785.6" process $proc$libresoc.v:101761$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] attribute \src "libresoc.v:101762.5-101762.29" switch \initial attribute \src "libresoc.v:101762.9-101762.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end attribute \src "libresoc.v:101786.3-101810.6" process $proc$libresoc.v:101786$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] attribute \src "libresoc.v:101787.5-101787.29" switch \initial attribute \src "libresoc.v:101787.9-101787.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end attribute \src "libresoc.v:101811.3-101835.6" process $proc$libresoc.v:101811$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] attribute \src "libresoc.v:101812.5-101812.29" switch \initial attribute \src "libresoc.v:101812.9-101812.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub20_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end attribute \src "libresoc.v:101836.3-101860.6" process $proc$libresoc.v:101836$4077 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] attribute \src "libresoc.v:101837.5-101837.29" switch \initial attribute \src "libresoc.v:101837.9-101837.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 case assign $1\dec31_dec_sub20_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end attribute \src "libresoc.v:101861.3-101885.6" process $proc$libresoc.v:101861$4078 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] attribute \src "libresoc.v:101862.5-101862.29" switch \initial attribute \src "libresoc.v:101862.9-101862.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sv_in3[2:0] 3'001 case assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end attribute \src "libresoc.v:101886.3-101910.6" process $proc$libresoc.v:101886$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] attribute \src "libresoc.v:101887.5-101887.29" switch \initial attribute \src "libresoc.v:101887.9-101887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 case assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end attribute \src "libresoc.v:101911.3-101935.6" process $proc$libresoc.v:101911$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0] attribute \src "libresoc.v:101912.5-101912.29" switch \initial attribute \src "libresoc.v:101912.9-101912.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub20_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0] end attribute \src "libresoc.v:101936.3-101960.6" process $proc$libresoc.v:101936$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] attribute \src "libresoc.v:101937.5-101937.29" switch \initial attribute \src "libresoc.v:101937.9-101937.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end attribute \src "libresoc.v:101961.3-101985.6" process $proc$libresoc.v:101961$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] attribute \src "libresoc.v:101962.5-101962.29" switch \initial attribute \src "libresoc.v:101962.9-101962.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end attribute \src "libresoc.v:101986.3-102010.6" process $proc$libresoc.v:101986$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] attribute \src "libresoc.v:101987.5-101987.29" switch \initial attribute \src "libresoc.v:101987.9-101987.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 case assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end attribute \src "libresoc.v:102011.3-102035.6" process $proc$libresoc.v:102011$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] attribute \src "libresoc.v:102012.5-102012.29" switch \initial attribute \src "libresoc.v:102012.9-102012.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 case assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end attribute \src "libresoc.v:102036.3-102060.6" process $proc$libresoc.v:102036$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] attribute \src "libresoc.v:102037.5-102037.29" switch \initial attribute \src "libresoc.v:102037.9-102037.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_upd[1:0] 2'00 case assign $1\dec31_dec_sub20_upd[1:0] 2'00 end sync always update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end attribute \src "libresoc.v:102061.3-102085.6" process $proc$libresoc.v:102061$4086 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] attribute \src "libresoc.v:102062.5-102062.29" switch \initial attribute \src "libresoc.v:102062.9-102062.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end attribute \src "libresoc.v:102086.3-102110.6" process $proc$libresoc.v:102086$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] attribute \src "libresoc.v:102087.5-102087.29" switch \initial attribute \src "libresoc.v:102087.9-102087.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end attribute \src "libresoc.v:102111.3-102135.6" process $proc$libresoc.v:102111$4088 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] attribute \src "libresoc.v:102112.5-102112.29" switch \initial attribute \src "libresoc.v:102112.9-102112.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101110 case assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end attribute \src "libresoc.v:102136.3-102160.6" process $proc$libresoc.v:102136$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] attribute \src "libresoc.v:102137.5-102137.29" switch \initial attribute \src "libresoc.v:102137.9-102137.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end attribute \src "libresoc.v:102161.3-102185.6" process $proc$libresoc.v:102161$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] attribute \src "libresoc.v:102162.5-102162.29" switch \initial attribute \src "libresoc.v:102162.9-102162.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end attribute \src "libresoc.v:102186.3-102210.6" process $proc$libresoc.v:102186$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] attribute \src "libresoc.v:102187.5-102187.29" switch \initial attribute \src "libresoc.v:102187.9-102187.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end attribute \src "libresoc.v:102211.3-102235.6" process $proc$libresoc.v:102211$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] attribute \src "libresoc.v:102212.5-102212.29" switch \initial attribute \src "libresoc.v:102212.9-102212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_br[0:0] 1'1 case assign $1\dec31_dec_sub20_br[0:0] 1'0 end sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end attribute \src "libresoc.v:102236.3-102260.6" process $proc$libresoc.v:102236$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:102237.5-102237.29" switch \initial attribute \src "libresoc.v:102237.9-102237.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end attribute \src "libresoc.v:102261.3-102285.6" process $proc$libresoc.v:102261$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] attribute \src "libresoc.v:102262.5-102262.29" switch \initial attribute \src "libresoc.v:102262.9-102262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end attribute \src "libresoc.v:102286.3-102310.6" process $proc$libresoc.v:102286$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] attribute \src "libresoc.v:102287.5-102287.29" switch \initial attribute \src "libresoc.v:102287.9-102287.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_form[4:0] 5'01000 case assign $1\dec31_dec_sub20_form[4:0] 5'00000 end sync always update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end attribute \src "libresoc.v:102311.3-102335.6" process $proc$libresoc.v:102311$4096 assign { } { } assign { } { } assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] attribute \src "libresoc.v:102312.5-102312.29" switch \initial attribute \src "libresoc.v:102312.9-102312.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end attribute \src "libresoc.v:102336.3-102360.6" process $proc$libresoc.v:102336$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] attribute \src "libresoc.v:102337.5-102337.29" switch \initial attribute \src "libresoc.v:102337.9-102337.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sgn[0:0] 1'0 case assign $1\dec31_dec_sub20_sgn[0:0] 1'0 end sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end attribute \src "libresoc.v:102361.3-102385.6" process $proc$libresoc.v:102361$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] attribute \src "libresoc.v:102362.5-102362.29" switch \initial attribute \src "libresoc.v:102362.9-102362.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_lk[0:0] 1'0 case assign $1\dec31_dec_sub20_lk[0:0] 1'0 end sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end attribute \src "libresoc.v:102386.3-102410.6" process $proc$libresoc.v:102386$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] attribute \src "libresoc.v:102387.5-102387.29" switch \initial attribute \src "libresoc.v:102387.9-102387.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 case assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end attribute \src "libresoc.v:102411.3-102435.6" process $proc$libresoc.v:102411$4100 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] attribute \src "libresoc.v:102412.5-102412.29" switch \initial attribute \src "libresoc.v:102412.9-102412.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 case assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] end attribute \src "libresoc.v:102436.3-102460.6" process $proc$libresoc.v:102436$4101 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] attribute \src "libresoc.v:102437.5-102437.29" switch \initial attribute \src "libresoc.v:102437.9-102437.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end attribute \src "libresoc.v:102461.3-102485.6" process $proc$libresoc.v:102461$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] attribute \src "libresoc.v:102462.5-102462.29" switch \initial attribute \src "libresoc.v:102462.9-102462.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 case assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end attribute \src "libresoc.v:102486.3-102510.6" process $proc$libresoc.v:102486$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] attribute \src "libresoc.v:102487.5-102487.29" switch \initial attribute \src "libresoc.v:102487.9-102487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end attribute \src "libresoc.v:102511.3-102535.6" process $proc$libresoc.v:102511$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] attribute \src "libresoc.v:102512.5-102512.29" switch \initial attribute \src "libresoc.v:102512.9-102512.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 case assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end attribute \src "libresoc.v:102536.3-102560.6" process $proc$libresoc.v:102536$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] attribute \src "libresoc.v:102537.5-102537.29" switch \initial attribute \src "libresoc.v:102537.9-102537.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub20_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 case assign $1\dec31_dec_sub20_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:102566.1-104527.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 attribute \src "libresoc.v:104232.3-104280.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] attribute \src "libresoc.v:104281.3-104329.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] attribute \src "libresoc.v:104189.3-104231.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] attribute \src "libresoc.v:103797.3-103845.6" wire $0\dec31_dec_sub21_br[0:0] attribute \src "libresoc.v:102964.3-103012.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] attribute \src "libresoc.v:103013.3-103061.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] attribute \src "libresoc.v:103601.3-103649.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] attribute \src "libresoc.v:103748.3-103796.6" wire $0\dec31_dec_sub21_cry_out[0:0] attribute \src "libresoc.v:103993.3-104041.6" wire width 5 $0\dec31_dec_sub21_form[4:0] attribute \src "libresoc.v:102915.3-102963.6" wire width 14 $0\dec31_dec_sub21_function_unit[13:0] attribute \src "libresoc.v:104330.3-104378.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] attribute \src "libresoc.v:104379.3-104427.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] attribute \src "libresoc.v:104428.3-104476.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] attribute \src "libresoc.v:103454.3-103502.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] attribute \src "libresoc.v:103650.3-103698.6" wire $0\dec31_dec_sub21_inv_a[0:0] attribute \src "libresoc.v:103699.3-103747.6" wire $0\dec31_dec_sub21_inv_out[0:0] attribute \src "libresoc.v:103944.3-103992.6" wire $0\dec31_dec_sub21_is_32b[0:0] attribute \src "libresoc.v:103405.3-103453.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] attribute \src "libresoc.v:104091.3-104139.6" wire $0\dec31_dec_sub21_lk[0:0] attribute \src "libresoc.v:104477.3-104525.6" wire width 3 $0\dec31_dec_sub21_out_sel[2:0] attribute \src "libresoc.v:103552.3-103600.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] attribute \src "libresoc.v:103895.3-103943.6" wire $0\dec31_dec_sub21_rsrv[0:0] attribute \src "libresoc.v:104140.3-104188.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] attribute \src "libresoc.v:104042.3-104090.6" wire $0\dec31_dec_sub21_sgn[0:0] attribute \src "libresoc.v:103846.3-103894.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:103307.3-103355.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] attribute \src "libresoc.v:103356.3-103404.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] attribute \src "libresoc.v:103062.3-103110.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] attribute \src "libresoc.v:103111.3-103159.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] attribute \src "libresoc.v:103160.3-103208.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] attribute \src "libresoc.v:103258.3-103306.6" wire width 3 $0\dec31_dec_sub21_sv_out2[2:0] attribute \src "libresoc.v:103209.3-103257.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] attribute \src "libresoc.v:103503.3-103551.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] attribute \src "libresoc.v:102567.7-102567.20" wire $0\initial[0:0] attribute \src "libresoc.v:104232.3-104280.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] attribute \src "libresoc.v:104281.3-104329.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] attribute \src "libresoc.v:104189.3-104231.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] attribute \src "libresoc.v:103797.3-103845.6" wire $1\dec31_dec_sub21_br[0:0] attribute \src "libresoc.v:102964.3-103012.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] attribute \src "libresoc.v:103013.3-103061.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] attribute \src "libresoc.v:103601.3-103649.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] attribute \src "libresoc.v:103748.3-103796.6" wire $1\dec31_dec_sub21_cry_out[0:0] attribute \src "libresoc.v:103993.3-104041.6" wire width 5 $1\dec31_dec_sub21_form[4:0] attribute \src "libresoc.v:102915.3-102963.6" wire width 14 $1\dec31_dec_sub21_function_unit[13:0] attribute \src "libresoc.v:104330.3-104378.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] attribute \src "libresoc.v:104379.3-104427.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] attribute \src "libresoc.v:104428.3-104476.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] attribute \src "libresoc.v:103454.3-103502.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] attribute \src "libresoc.v:103650.3-103698.6" wire $1\dec31_dec_sub21_inv_a[0:0] attribute \src "libresoc.v:103699.3-103747.6" wire $1\dec31_dec_sub21_inv_out[0:0] attribute \src "libresoc.v:103944.3-103992.6" wire $1\dec31_dec_sub21_is_32b[0:0] attribute \src "libresoc.v:103405.3-103453.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] attribute \src "libresoc.v:104091.3-104139.6" wire $1\dec31_dec_sub21_lk[0:0] attribute \src "libresoc.v:104477.3-104525.6" wire width 3 $1\dec31_dec_sub21_out_sel[2:0] attribute \src "libresoc.v:103552.3-103600.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] attribute \src "libresoc.v:103895.3-103943.6" wire $1\dec31_dec_sub21_rsrv[0:0] attribute \src "libresoc.v:104140.3-104188.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] attribute \src "libresoc.v:104042.3-104090.6" wire $1\dec31_dec_sub21_sgn[0:0] attribute \src "libresoc.v:103846.3-103894.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:103307.3-103355.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] attribute \src "libresoc.v:103356.3-103404.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] attribute \src "libresoc.v:103062.3-103110.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] attribute \src "libresoc.v:103111.3-103159.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] attribute \src "libresoc.v:103160.3-103208.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] attribute \src "libresoc.v:103258.3-103306.6" wire width 3 $1\dec31_dec_sub21_sv_out2[2:0] attribute \src "libresoc.v:103209.3-103257.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] attribute \src "libresoc.v:103503.3-103551.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub21_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub21_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub21_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub21_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub21_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub21_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub21_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub21_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub21_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub21_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub21_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub21_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub21_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub21_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub21_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub21_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub21_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub21_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub21_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub21_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub21_upd attribute \src "libresoc.v:102567.7-102567.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:102567.7-102567.20" process $proc$libresoc.v:102567$4140 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:102915.3-102963.6" process $proc$libresoc.v:102915$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] attribute \src "libresoc.v:102916.5-102916.29" switch \initial attribute \src "libresoc.v:102916.9-102916.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000100 case assign $1\dec31_dec_sub21_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end attribute \src "libresoc.v:102964.3-103012.6" process $proc$libresoc.v:102964$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] attribute \src "libresoc.v:102965.5-102965.29" switch \initial attribute \src "libresoc.v:102965.9-102965.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end attribute \src "libresoc.v:103013.3-103061.6" process $proc$libresoc.v:103013$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] attribute \src "libresoc.v:103014.5-103014.29" switch \initial attribute \src "libresoc.v:103014.9-103014.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end attribute \src "libresoc.v:103062.3-103110.6" process $proc$libresoc.v:103062$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] attribute \src "libresoc.v:103063.5-103063.29" switch \initial attribute \src "libresoc.v:103063.9-103063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end attribute \src "libresoc.v:103111.3-103159.6" process $proc$libresoc.v:103111$4111 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] attribute \src "libresoc.v:103112.5-103112.29" switch \initial attribute \src "libresoc.v:103112.9-103112.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 case assign $1\dec31_dec_sub21_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end attribute \src "libresoc.v:103160.3-103208.6" process $proc$libresoc.v:103160$4112 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] attribute \src "libresoc.v:103161.5-103161.29" switch \initial attribute \src "libresoc.v:103161.9-103161.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 case assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end attribute \src "libresoc.v:103209.3-103257.6" process $proc$libresoc.v:103209$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] attribute \src "libresoc.v:103210.5-103210.29" switch \initial attribute \src "libresoc.v:103210.9-103210.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 case assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end attribute \src "libresoc.v:103258.3-103306.6" process $proc$libresoc.v:103258$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0] attribute \src "libresoc.v:103259.5-103259.29" switch \initial attribute \src "libresoc.v:103259.9-103259.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub21_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0] end attribute \src "libresoc.v:103307.3-103355.6" process $proc$libresoc.v:103307$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] attribute \src "libresoc.v:103308.5-103308.29" switch \initial attribute \src "libresoc.v:103308.9-103308.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end attribute \src "libresoc.v:103356.3-103404.6" process $proc$libresoc.v:103356$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] attribute \src "libresoc.v:103357.5-103357.29" switch \initial attribute \src "libresoc.v:103357.9-103357.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end attribute \src "libresoc.v:103405.3-103453.6" process $proc$libresoc.v:103405$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] attribute \src "libresoc.v:103406.5-103406.29" switch \initial attribute \src "libresoc.v:103406.9-103406.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 case assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end attribute \src "libresoc.v:103454.3-103502.6" process $proc$libresoc.v:103454$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] attribute \src "libresoc.v:103455.5-103455.29" switch \initial attribute \src "libresoc.v:103455.9-103455.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 case assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end attribute \src "libresoc.v:103503.3-103551.6" process $proc$libresoc.v:103503$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] attribute \src "libresoc.v:103504.5-103504.29" switch \initial attribute \src "libresoc.v:103504.9-103504.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_upd[1:0] 2'10 case assign $1\dec31_dec_sub21_upd[1:0] 2'00 end sync always update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end attribute \src "libresoc.v:103552.3-103600.6" process $proc$libresoc.v:103552$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] attribute \src "libresoc.v:103553.5-103553.29" switch \initial attribute \src "libresoc.v:103553.9-103553.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end attribute \src "libresoc.v:103601.3-103649.6" process $proc$libresoc.v:103601$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] attribute \src "libresoc.v:103602.5-103602.29" switch \initial attribute \src "libresoc.v:103602.9-103602.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end attribute \src "libresoc.v:103650.3-103698.6" process $proc$libresoc.v:103650$4122 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] attribute \src "libresoc.v:103651.5-103651.29" switch \initial attribute \src "libresoc.v:103651.9-103651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end attribute \src "libresoc.v:103699.3-103747.6" process $proc$libresoc.v:103699$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] attribute \src "libresoc.v:103700.5-103700.29" switch \initial attribute \src "libresoc.v:103700.9-103700.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end attribute \src "libresoc.v:103748.3-103796.6" process $proc$libresoc.v:103748$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] attribute \src "libresoc.v:103749.5-103749.29" switch \initial attribute \src "libresoc.v:103749.9-103749.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end attribute \src "libresoc.v:103797.3-103845.6" process $proc$libresoc.v:103797$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] attribute \src "libresoc.v:103798.5-103798.29" switch \initial attribute \src "libresoc.v:103798.9-103798.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_br[0:0] 1'0 case assign $1\dec31_dec_sub21_br[0:0] 1'0 end sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end attribute \src "libresoc.v:103846.3-103894.6" process $proc$libresoc.v:103846$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:103847.5-103847.29" switch \initial attribute \src "libresoc.v:103847.9-103847.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end attribute \src "libresoc.v:103895.3-103943.6" process $proc$libresoc.v:103895$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] attribute \src "libresoc.v:103896.5-103896.29" switch \initial attribute \src "libresoc.v:103896.9-103896.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end attribute \src "libresoc.v:103944.3-103992.6" process $proc$libresoc.v:103944$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] attribute \src "libresoc.v:103945.5-103945.29" switch \initial attribute \src "libresoc.v:103945.9-103945.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end attribute \src "libresoc.v:103993.3-104041.6" process $proc$libresoc.v:103993$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] attribute \src "libresoc.v:103994.5-103994.29" switch \initial attribute \src "libresoc.v:103994.9-103994.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_form[4:0] 5'01000 case assign $1\dec31_dec_sub21_form[4:0] 5'00000 end sync always update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end attribute \src "libresoc.v:104042.3-104090.6" process $proc$libresoc.v:104042$4130 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] attribute \src "libresoc.v:104043.5-104043.29" switch \initial attribute \src "libresoc.v:104043.9-104043.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sgn[0:0] 1'0 case assign $1\dec31_dec_sub21_sgn[0:0] 1'0 end sync always update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end attribute \src "libresoc.v:104091.3-104139.6" process $proc$libresoc.v:104091$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] attribute \src "libresoc.v:104092.5-104092.29" switch \initial attribute \src "libresoc.v:104092.9-104092.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_lk[0:0] 1'0 case assign $1\dec31_dec_sub21_lk[0:0] 1'0 end sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end attribute \src "libresoc.v:104140.3-104188.6" process $proc$libresoc.v:104140$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] attribute \src "libresoc.v:104141.5-104141.29" switch \initial attribute \src "libresoc.v:104141.9-104141.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 case assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end attribute \src "libresoc.v:104189.3-104231.6" process $proc$libresoc.v:104189$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] attribute \src "libresoc.v:104190.5-104190.29" switch \initial attribute \src "libresoc.v:104190.9-104190.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'10101000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110010 case assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end attribute \src "libresoc.v:104232.3-104280.6" process $proc$libresoc.v:104232$4134 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] attribute \src "libresoc.v:104233.5-104233.29" switch \initial attribute \src "libresoc.v:104233.9-104233.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 case assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end attribute \src "libresoc.v:104281.3-104329.6" process $proc$libresoc.v:104281$4135 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] attribute \src "libresoc.v:104282.5-104282.29" switch \initial attribute \src "libresoc.v:104282.9-104282.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end attribute \src "libresoc.v:104330.3-104378.6" process $proc$libresoc.v:104330$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] attribute \src "libresoc.v:104331.5-104331.29" switch \initial attribute \src "libresoc.v:104331.9-104331.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 case assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end attribute \src "libresoc.v:104379.3-104427.6" process $proc$libresoc.v:104379$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] attribute \src "libresoc.v:104380.5-104380.29" switch \initial attribute \src "libresoc.v:104380.9-104380.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end attribute \src "libresoc.v:104428.3-104476.6" process $proc$libresoc.v:104428$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] attribute \src "libresoc.v:104429.5-104429.29" switch \initial attribute \src "libresoc.v:104429.9-104429.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 case assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end attribute \src "libresoc.v:104477.3-104525.6" process $proc$libresoc.v:104477$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] attribute \src "libresoc.v:104478.5-104478.29" switch \initial attribute \src "libresoc.v:104478.9-104478.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 case assign $1\dec31_dec_sub21_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:104531.1-106696.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 attribute \src "libresoc.v:106365.3-106419.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] attribute \src "libresoc.v:106420.3-106474.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] attribute \src "libresoc.v:105705.3-105759.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] attribute \src "libresoc.v:105925.3-105979.6" wire $0\dec31_dec_sub22_br[0:0] attribute \src "libresoc.v:104935.3-104989.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:104990.3-105044.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:105650.3-105704.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] attribute \src "libresoc.v:105870.3-105924.6" wire $0\dec31_dec_sub22_cry_out[0:0] attribute \src "libresoc.v:106090.3-106144.6" wire width 5 $0\dec31_dec_sub22_form[4:0] attribute \src "libresoc.v:104880.3-104934.6" wire width 14 $0\dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:106475.3-106529.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:106530.3-106584.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:106585.3-106639.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] attribute \src "libresoc.v:105485.3-105539.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:105760.3-105814.6" wire $0\dec31_dec_sub22_inv_a[0:0] attribute \src "libresoc.v:105815.3-105869.6" wire $0\dec31_dec_sub22_inv_out[0:0] attribute \src "libresoc.v:106145.3-106199.6" wire $0\dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:105430.3-105484.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:106255.3-106309.6" wire $0\dec31_dec_sub22_lk[0:0] attribute \src "libresoc.v:106640.3-106694.6" wire width 3 $0\dec31_dec_sub22_out_sel[2:0] attribute \src "libresoc.v:105595.3-105649.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:106035.3-106089.6" wire $0\dec31_dec_sub22_rsrv[0:0] attribute \src "libresoc.v:106310.3-106364.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] attribute \src "libresoc.v:106200.3-106254.6" wire $0\dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:105980.3-106034.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:105320.3-105374.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] attribute \src "libresoc.v:105375.3-105429.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] attribute \src "libresoc.v:105045.3-105099.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] attribute \src "libresoc.v:105100.3-105154.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] attribute \src "libresoc.v:105155.3-105209.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] attribute \src "libresoc.v:105265.3-105319.6" wire width 3 $0\dec31_dec_sub22_sv_out2[2:0] attribute \src "libresoc.v:105210.3-105264.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] attribute \src "libresoc.v:105540.3-105594.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] attribute \src "libresoc.v:104532.7-104532.20" wire $0\initial[0:0] attribute \src "libresoc.v:106365.3-106419.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] attribute \src "libresoc.v:106420.3-106474.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] attribute \src "libresoc.v:105705.3-105759.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] attribute \src "libresoc.v:105925.3-105979.6" wire $1\dec31_dec_sub22_br[0:0] attribute \src "libresoc.v:104935.3-104989.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:104990.3-105044.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:105650.3-105704.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] attribute \src "libresoc.v:105870.3-105924.6" wire $1\dec31_dec_sub22_cry_out[0:0] attribute \src "libresoc.v:106090.3-106144.6" wire width 5 $1\dec31_dec_sub22_form[4:0] attribute \src "libresoc.v:104880.3-104934.6" wire width 14 $1\dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:106475.3-106529.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:106530.3-106584.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:106585.3-106639.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] attribute \src "libresoc.v:105485.3-105539.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:105760.3-105814.6" wire $1\dec31_dec_sub22_inv_a[0:0] attribute \src "libresoc.v:105815.3-105869.6" wire $1\dec31_dec_sub22_inv_out[0:0] attribute \src "libresoc.v:106145.3-106199.6" wire $1\dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:105430.3-105484.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:106255.3-106309.6" wire $1\dec31_dec_sub22_lk[0:0] attribute \src "libresoc.v:106640.3-106694.6" wire width 3 $1\dec31_dec_sub22_out_sel[2:0] attribute \src "libresoc.v:105595.3-105649.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:106035.3-106089.6" wire $1\dec31_dec_sub22_rsrv[0:0] attribute \src "libresoc.v:106310.3-106364.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] attribute \src "libresoc.v:106200.3-106254.6" wire $1\dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:105980.3-106034.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:105320.3-105374.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] attribute \src "libresoc.v:105375.3-105429.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] attribute \src "libresoc.v:105045.3-105099.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] attribute \src "libresoc.v:105100.3-105154.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] attribute \src "libresoc.v:105155.3-105209.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] attribute \src "libresoc.v:105265.3-105319.6" wire width 3 $1\dec31_dec_sub22_sv_out2[2:0] attribute \src "libresoc.v:105210.3-105264.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] attribute \src "libresoc.v:105540.3-105594.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub22_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub22_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub22_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub22_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub22_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub22_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub22_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub22_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub22_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub22_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub22_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub22_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub22_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub22_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub22_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub22_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub22_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub22_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub22_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub22_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub22_upd attribute \src "libresoc.v:104532.7-104532.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:104532.7-104532.20" process $proc$libresoc.v:104532$4174 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:104880.3-104934.6" process $proc$libresoc.v:104880$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] attribute \src "libresoc.v:104881.5-104881.29" switch \initial attribute \src "libresoc.v:104881.9-104881.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00100000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000010 case assign $1\dec31_dec_sub22_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end attribute \src "libresoc.v:104935.3-104989.6" process $proc$libresoc.v:104935$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] attribute \src "libresoc.v:104936.5-104936.29" switch \initial attribute \src "libresoc.v:104936.9-104936.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end attribute \src "libresoc.v:104990.3-105044.6" process $proc$libresoc.v:104990$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] attribute \src "libresoc.v:104991.5-104991.29" switch \initial attribute \src "libresoc.v:104991.9-104991.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end attribute \src "libresoc.v:105045.3-105099.6" process $proc$libresoc.v:105045$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] attribute \src "libresoc.v:105046.5-105046.29" switch \initial attribute \src "libresoc.v:105046.9-105046.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 case assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end attribute \src "libresoc.v:105100.3-105154.6" process $proc$libresoc.v:105100$4145 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] attribute \src "libresoc.v:105101.5-105101.29" switch \initial attribute \src "libresoc.v:105101.9-105101.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end attribute \src "libresoc.v:105155.3-105209.6" process $proc$libresoc.v:105155$4146 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] attribute \src "libresoc.v:105156.5-105156.29" switch \initial attribute \src "libresoc.v:105156.9-105156.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end attribute \src "libresoc.v:105210.3-105264.6" process $proc$libresoc.v:105210$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] attribute \src "libresoc.v:105211.5-105211.29" switch \initial attribute \src "libresoc.v:105211.9-105211.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 case assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end attribute \src "libresoc.v:105265.3-105319.6" process $proc$libresoc.v:105265$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0] attribute \src "libresoc.v:105266.5-105266.29" switch \initial attribute \src "libresoc.v:105266.9-105266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub22_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0] end attribute \src "libresoc.v:105320.3-105374.6" process $proc$libresoc.v:105320$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] attribute \src "libresoc.v:105321.5-105321.29" switch \initial attribute \src "libresoc.v:105321.9-105321.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end attribute \src "libresoc.v:105375.3-105429.6" process $proc$libresoc.v:105375$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] attribute \src "libresoc.v:105376.5-105376.29" switch \initial attribute \src "libresoc.v:105376.9-105376.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end attribute \src "libresoc.v:105430.3-105484.6" process $proc$libresoc.v:105430$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] attribute \src "libresoc.v:105431.5-105431.29" switch \initial attribute \src "libresoc.v:105431.9-105431.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end attribute \src "libresoc.v:105485.3-105539.6" process $proc$libresoc.v:105485$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] attribute \src "libresoc.v:105486.5-105486.29" switch \initial attribute \src "libresoc.v:105486.9-105486.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 case assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end attribute \src "libresoc.v:105540.3-105594.6" process $proc$libresoc.v:105540$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] attribute \src "libresoc.v:105541.5-105541.29" switch \initial attribute \src "libresoc.v:105541.9-105541.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_upd[1:0] 2'00 case assign $1\dec31_dec_sub22_upd[1:0] 2'00 end sync always update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end attribute \src "libresoc.v:105595.3-105649.6" process $proc$libresoc.v:105595$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] attribute \src "libresoc.v:105596.5-105596.29" switch \initial attribute \src "libresoc.v:105596.9-105596.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end attribute \src "libresoc.v:105650.3-105704.6" process $proc$libresoc.v:105650$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] attribute \src "libresoc.v:105651.5-105651.29" switch \initial attribute \src "libresoc.v:105651.9-105651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end attribute \src "libresoc.v:105705.3-105759.6" process $proc$libresoc.v:105705$4156 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] attribute \src "libresoc.v:105706.5-105706.29" switch \initial attribute \src "libresoc.v:105706.9-105706.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101111 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110101 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001010 case assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end attribute \src "libresoc.v:105760.3-105814.6" process $proc$libresoc.v:105760$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] attribute \src "libresoc.v:105761.5-105761.29" switch \initial attribute \src "libresoc.v:105761.9-105761.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end attribute \src "libresoc.v:105815.3-105869.6" process $proc$libresoc.v:105815$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] attribute \src "libresoc.v:105816.5-105816.29" switch \initial attribute \src "libresoc.v:105816.9-105816.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end attribute \src "libresoc.v:105870.3-105924.6" process $proc$libresoc.v:105870$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] attribute \src "libresoc.v:105871.5-105871.29" switch \initial attribute \src "libresoc.v:105871.9-105871.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end attribute \src "libresoc.v:105925.3-105979.6" process $proc$libresoc.v:105925$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] attribute \src "libresoc.v:105926.5-105926.29" switch \initial attribute \src "libresoc.v:105926.9-105926.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_br[0:0] 1'0 case assign $1\dec31_dec_sub22_br[0:0] 1'0 end sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end attribute \src "libresoc.v:105980.3-106034.6" process $proc$libresoc.v:105980$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:105981.5-105981.29" switch \initial attribute \src "libresoc.v:105981.9-105981.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end attribute \src "libresoc.v:106035.3-106089.6" process $proc$libresoc.v:106035$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] attribute \src "libresoc.v:106036.5-106036.29" switch \initial attribute \src "libresoc.v:106036.9-106036.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end attribute \src "libresoc.v:106090.3-106144.6" process $proc$libresoc.v:106090$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] attribute \src "libresoc.v:106091.5-106091.29" switch \initial attribute \src "libresoc.v:106091.9-106091.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_form[4:0] 5'01000 case assign $1\dec31_dec_sub22_form[4:0] 5'00000 end sync always update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end attribute \src "libresoc.v:106145.3-106199.6" process $proc$libresoc.v:106145$4164 assign { } { } assign { } { } assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] attribute \src "libresoc.v:106146.5-106146.29" switch \initial attribute \src "libresoc.v:106146.9-106146.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end attribute \src "libresoc.v:106200.3-106254.6" process $proc$libresoc.v:106200$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] attribute \src "libresoc.v:106201.5-106201.29" switch \initial attribute \src "libresoc.v:106201.9-106201.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sgn[0:0] 1'0 case assign $1\dec31_dec_sub22_sgn[0:0] 1'0 end sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end attribute \src "libresoc.v:106255.3-106309.6" process $proc$libresoc.v:106255$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] attribute \src "libresoc.v:106256.5-106256.29" switch \initial attribute \src "libresoc.v:106256.9-106256.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_lk[0:0] 1'0 case assign $1\dec31_dec_sub22_lk[0:0] 1'0 end sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end attribute \src "libresoc.v:106310.3-106364.6" process $proc$libresoc.v:106310$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] attribute \src "libresoc.v:106311.5-106311.29" switch \initial attribute \src "libresoc.v:106311.9-106311.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 case assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end attribute \src "libresoc.v:106365.3-106419.6" process $proc$libresoc.v:106365$4168 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] attribute \src "libresoc.v:106366.5-106366.29" switch \initial attribute \src "libresoc.v:106366.9-106366.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 case assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end attribute \src "libresoc.v:106420.3-106474.6" process $proc$libresoc.v:106420$4169 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] attribute \src "libresoc.v:106421.5-106421.29" switch \initial attribute \src "libresoc.v:106421.9-106421.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 case assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end attribute \src "libresoc.v:106475.3-106529.6" process $proc$libresoc.v:106475$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] attribute \src "libresoc.v:106476.5-106476.29" switch \initial attribute \src "libresoc.v:106476.9-106476.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 case assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end attribute \src "libresoc.v:106530.3-106584.6" process $proc$libresoc.v:106530$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] attribute \src "libresoc.v:106531.5-106531.29" switch \initial attribute \src "libresoc.v:106531.9-106531.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 case assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end attribute \src "libresoc.v:106585.3-106639.6" process $proc$libresoc.v:106585$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] attribute \src "libresoc.v:106586.5-106586.29" switch \initial attribute \src "libresoc.v:106586.9-106586.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end attribute \src "libresoc.v:106640.3-106694.6" process $proc$libresoc.v:106640$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] attribute \src "libresoc.v:106641.5-106641.29" switch \initial attribute \src "libresoc.v:106641.9-106641.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10101 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 case assign $1\dec31_dec_sub22_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:106700.1-108667.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 attribute \src "libresoc.v:108372.3-108420.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] attribute \src "libresoc.v:108421.3-108469.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] attribute \src "libresoc.v:107784.3-107832.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] attribute \src "libresoc.v:107980.3-108028.6" wire $0\dec31_dec_sub23_br[0:0] attribute \src "libresoc.v:107098.3-107146.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] attribute \src "libresoc.v:107147.3-107195.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] attribute \src "libresoc.v:107735.3-107783.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] attribute \src "libresoc.v:107931.3-107979.6" wire $0\dec31_dec_sub23_cry_out[0:0] attribute \src "libresoc.v:108127.3-108175.6" wire width 5 $0\dec31_dec_sub23_form[4:0] attribute \src "libresoc.v:107049.3-107097.6" wire width 14 $0\dec31_dec_sub23_function_unit[13:0] attribute \src "libresoc.v:108470.3-108518.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] attribute \src "libresoc.v:108519.3-108567.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] attribute \src "libresoc.v:108568.3-108616.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] attribute \src "libresoc.v:107588.3-107636.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] attribute \src "libresoc.v:107833.3-107881.6" wire $0\dec31_dec_sub23_inv_a[0:0] attribute \src "libresoc.v:107882.3-107930.6" wire $0\dec31_dec_sub23_inv_out[0:0] attribute \src "libresoc.v:108176.3-108224.6" wire $0\dec31_dec_sub23_is_32b[0:0] attribute \src "libresoc.v:107539.3-107587.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] attribute \src "libresoc.v:108274.3-108322.6" wire $0\dec31_dec_sub23_lk[0:0] attribute \src "libresoc.v:108617.3-108665.6" wire width 3 $0\dec31_dec_sub23_out_sel[2:0] attribute \src "libresoc.v:107686.3-107734.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] attribute \src "libresoc.v:108078.3-108126.6" wire $0\dec31_dec_sub23_rsrv[0:0] attribute \src "libresoc.v:108323.3-108371.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] attribute \src "libresoc.v:108225.3-108273.6" wire $0\dec31_dec_sub23_sgn[0:0] attribute \src "libresoc.v:108029.3-108077.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:107441.3-107489.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] attribute \src "libresoc.v:107490.3-107538.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] attribute \src "libresoc.v:107196.3-107244.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] attribute \src "libresoc.v:107245.3-107293.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] attribute \src "libresoc.v:107294.3-107342.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] attribute \src "libresoc.v:107392.3-107440.6" wire width 3 $0\dec31_dec_sub23_sv_out2[2:0] attribute \src "libresoc.v:107343.3-107391.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] attribute \src "libresoc.v:107637.3-107685.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] attribute \src "libresoc.v:106701.7-106701.20" wire $0\initial[0:0] attribute \src "libresoc.v:108372.3-108420.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] attribute \src "libresoc.v:108421.3-108469.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] attribute \src "libresoc.v:107784.3-107832.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] attribute \src "libresoc.v:107980.3-108028.6" wire $1\dec31_dec_sub23_br[0:0] attribute \src "libresoc.v:107098.3-107146.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] attribute \src "libresoc.v:107147.3-107195.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] attribute \src "libresoc.v:107735.3-107783.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] attribute \src "libresoc.v:107931.3-107979.6" wire $1\dec31_dec_sub23_cry_out[0:0] attribute \src "libresoc.v:108127.3-108175.6" wire width 5 $1\dec31_dec_sub23_form[4:0] attribute \src "libresoc.v:107049.3-107097.6" wire width 14 $1\dec31_dec_sub23_function_unit[13:0] attribute \src "libresoc.v:108470.3-108518.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] attribute \src "libresoc.v:108519.3-108567.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] attribute \src "libresoc.v:108568.3-108616.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] attribute \src "libresoc.v:107588.3-107636.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] attribute \src "libresoc.v:107833.3-107881.6" wire $1\dec31_dec_sub23_inv_a[0:0] attribute \src "libresoc.v:107882.3-107930.6" wire $1\dec31_dec_sub23_inv_out[0:0] attribute \src "libresoc.v:108176.3-108224.6" wire $1\dec31_dec_sub23_is_32b[0:0] attribute \src "libresoc.v:107539.3-107587.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] attribute \src "libresoc.v:108274.3-108322.6" wire $1\dec31_dec_sub23_lk[0:0] attribute \src "libresoc.v:108617.3-108665.6" wire width 3 $1\dec31_dec_sub23_out_sel[2:0] attribute \src "libresoc.v:107686.3-107734.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] attribute \src "libresoc.v:108078.3-108126.6" wire $1\dec31_dec_sub23_rsrv[0:0] attribute \src "libresoc.v:108323.3-108371.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] attribute \src "libresoc.v:108225.3-108273.6" wire $1\dec31_dec_sub23_sgn[0:0] attribute \src "libresoc.v:108029.3-108077.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:107441.3-107489.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] attribute \src "libresoc.v:107490.3-107538.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] attribute \src "libresoc.v:107196.3-107244.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] attribute \src "libresoc.v:107245.3-107293.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] attribute \src "libresoc.v:107294.3-107342.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] attribute \src "libresoc.v:107392.3-107440.6" wire width 3 $1\dec31_dec_sub23_sv_out2[2:0] attribute \src "libresoc.v:107343.3-107391.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] attribute \src "libresoc.v:107637.3-107685.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub23_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub23_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub23_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub23_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub23_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub23_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub23_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub23_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub23_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub23_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub23_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub23_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub23_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub23_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub23_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub23_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub23_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub23_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub23_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub23_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub23_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub23_upd attribute \src "libresoc.v:106701.7-106701.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:106701.7-106701.20" process $proc$libresoc.v:106701$4208 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:107049.3-107097.6" process $proc$libresoc.v:107049$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] attribute \src "libresoc.v:107050.5-107050.29" switch \initial attribute \src "libresoc.v:107050.9-107050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000100 case assign $1\dec31_dec_sub23_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end attribute \src "libresoc.v:107098.3-107146.6" process $proc$libresoc.v:107098$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] attribute \src "libresoc.v:107099.5-107099.29" switch \initial attribute \src "libresoc.v:107099.9-107099.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end attribute \src "libresoc.v:107147.3-107195.6" process $proc$libresoc.v:107147$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] attribute \src "libresoc.v:107148.5-107148.29" switch \initial attribute \src "libresoc.v:107148.9-107148.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end attribute \src "libresoc.v:107196.3-107244.6" process $proc$libresoc.v:107196$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] attribute \src "libresoc.v:107197.5-107197.29" switch \initial attribute \src "libresoc.v:107197.9-107197.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end attribute \src "libresoc.v:107245.3-107293.6" process $proc$libresoc.v:107245$4179 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] attribute \src "libresoc.v:107246.5-107246.29" switch \initial attribute \src "libresoc.v:107246.9-107246.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 case assign $1\dec31_dec_sub23_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end attribute \src "libresoc.v:107294.3-107342.6" process $proc$libresoc.v:107294$4180 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] attribute \src "libresoc.v:107295.5-107295.29" switch \initial attribute \src "libresoc.v:107295.9-107295.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 case assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end attribute \src "libresoc.v:107343.3-107391.6" process $proc$libresoc.v:107343$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] attribute \src "libresoc.v:107344.5-107344.29" switch \initial attribute \src "libresoc.v:107344.9-107344.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 case assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end attribute \src "libresoc.v:107392.3-107440.6" process $proc$libresoc.v:107392$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0] attribute \src "libresoc.v:107393.5-107393.29" switch \initial attribute \src "libresoc.v:107393.9-107393.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub23_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0] end attribute \src "libresoc.v:107441.3-107489.6" process $proc$libresoc.v:107441$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] attribute \src "libresoc.v:107442.5-107442.29" switch \initial attribute \src "libresoc.v:107442.9-107442.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end attribute \src "libresoc.v:107490.3-107538.6" process $proc$libresoc.v:107490$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] attribute \src "libresoc.v:107491.5-107491.29" switch \initial attribute \src "libresoc.v:107491.9-107491.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end attribute \src "libresoc.v:107539.3-107587.6" process $proc$libresoc.v:107539$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] attribute \src "libresoc.v:107540.5-107540.29" switch \initial attribute \src "libresoc.v:107540.9-107540.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 case assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end attribute \src "libresoc.v:107588.3-107636.6" process $proc$libresoc.v:107588$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] attribute \src "libresoc.v:107589.5-107589.29" switch \initial attribute \src "libresoc.v:107589.9-107589.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 case assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end attribute \src "libresoc.v:107637.3-107685.6" process $proc$libresoc.v:107637$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] attribute \src "libresoc.v:107638.5-107638.29" switch \initial attribute \src "libresoc.v:107638.9-107638.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_upd[1:0] 2'00 case assign $1\dec31_dec_sub23_upd[1:0] 2'00 end sync always update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end attribute \src "libresoc.v:107686.3-107734.6" process $proc$libresoc.v:107686$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] attribute \src "libresoc.v:107687.5-107687.29" switch \initial attribute \src "libresoc.v:107687.9-107687.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end attribute \src "libresoc.v:107735.3-107783.6" process $proc$libresoc.v:107735$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] attribute \src "libresoc.v:107736.5-107736.29" switch \initial attribute \src "libresoc.v:107736.9-107736.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end attribute \src "libresoc.v:107784.3-107832.6" process $proc$libresoc.v:107784$4190 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] attribute \src "libresoc.v:107785.5-107785.29" switch \initial attribute \src "libresoc.v:107785.9-107785.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111110 case assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end attribute \src "libresoc.v:107833.3-107881.6" process $proc$libresoc.v:107833$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] attribute \src "libresoc.v:107834.5-107834.29" switch \initial attribute \src "libresoc.v:107834.9-107834.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end attribute \src "libresoc.v:107882.3-107930.6" process $proc$libresoc.v:107882$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] attribute \src "libresoc.v:107883.5-107883.29" switch \initial attribute \src "libresoc.v:107883.9-107883.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end attribute \src "libresoc.v:107931.3-107979.6" process $proc$libresoc.v:107931$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] attribute \src "libresoc.v:107932.5-107932.29" switch \initial attribute \src "libresoc.v:107932.9-107932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end attribute \src "libresoc.v:107980.3-108028.6" process $proc$libresoc.v:107980$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] attribute \src "libresoc.v:107981.5-107981.29" switch \initial attribute \src "libresoc.v:107981.9-107981.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_br[0:0] 1'0 case assign $1\dec31_dec_sub23_br[0:0] 1'0 end sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end attribute \src "libresoc.v:108029.3-108077.6" process $proc$libresoc.v:108029$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:108030.5-108030.29" switch \initial attribute \src "libresoc.v:108030.9-108030.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end attribute \src "libresoc.v:108078.3-108126.6" process $proc$libresoc.v:108078$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] attribute \src "libresoc.v:108079.5-108079.29" switch \initial attribute \src "libresoc.v:108079.9-108079.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end attribute \src "libresoc.v:108127.3-108175.6" process $proc$libresoc.v:108127$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] attribute \src "libresoc.v:108128.5-108128.29" switch \initial attribute \src "libresoc.v:108128.9-108128.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_form[4:0] 5'01000 case assign $1\dec31_dec_sub23_form[4:0] 5'00000 end sync always update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end attribute \src "libresoc.v:108176.3-108224.6" process $proc$libresoc.v:108176$4198 assign { } { } assign { } { } assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] attribute \src "libresoc.v:108177.5-108177.29" switch \initial attribute \src "libresoc.v:108177.9-108177.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end attribute \src "libresoc.v:108225.3-108273.6" process $proc$libresoc.v:108225$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] attribute \src "libresoc.v:108226.5-108226.29" switch \initial attribute \src "libresoc.v:108226.9-108226.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sgn[0:0] 1'0 case assign $1\dec31_dec_sub23_sgn[0:0] 1'0 end sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end attribute \src "libresoc.v:108274.3-108322.6" process $proc$libresoc.v:108274$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] attribute \src "libresoc.v:108275.5-108275.29" switch \initial attribute \src "libresoc.v:108275.9-108275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_lk[0:0] 1'0 case assign $1\dec31_dec_sub23_lk[0:0] 1'0 end sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end attribute \src "libresoc.v:108323.3-108371.6" process $proc$libresoc.v:108323$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] attribute \src "libresoc.v:108324.5-108324.29" switch \initial attribute \src "libresoc.v:108324.9-108324.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 case assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end attribute \src "libresoc.v:108372.3-108420.6" process $proc$libresoc.v:108372$4202 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] attribute \src "libresoc.v:108373.5-108373.29" switch \initial attribute \src "libresoc.v:108373.9-108373.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 case assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end attribute \src "libresoc.v:108421.3-108469.6" process $proc$libresoc.v:108421$4203 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] attribute \src "libresoc.v:108422.5-108422.29" switch \initial attribute \src "libresoc.v:108422.9-108422.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end attribute \src "libresoc.v:108470.3-108518.6" process $proc$libresoc.v:108470$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] attribute \src "libresoc.v:108471.5-108471.29" switch \initial attribute \src "libresoc.v:108471.9-108471.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 case assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end attribute \src "libresoc.v:108519.3-108567.6" process $proc$libresoc.v:108519$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] attribute \src "libresoc.v:108520.5-108520.29" switch \initial attribute \src "libresoc.v:108520.9-108520.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end attribute \src "libresoc.v:108568.3-108616.6" process $proc$libresoc.v:108568$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] attribute \src "libresoc.v:108569.5-108569.29" switch \initial attribute \src "libresoc.v:108569.9-108569.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 case assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end attribute \src "libresoc.v:108617.3-108665.6" process $proc$libresoc.v:108617$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] attribute \src "libresoc.v:108618.5-108618.29" switch \initial attribute \src "libresoc.v:108618.9-108618.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01010 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 case assign $1\dec31_dec_sub23_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:108671.1-109648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 attribute \src "libresoc.v:109533.3-109551.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] attribute \src "libresoc.v:109552.3-109570.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] attribute \src "libresoc.v:109305.3-109323.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] attribute \src "libresoc.v:109381.3-109399.6" wire $0\dec31_dec_sub24_br[0:0] attribute \src "libresoc.v:109039.3-109057.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] attribute \src "libresoc.v:109058.3-109076.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] attribute \src "libresoc.v:109286.3-109304.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:109362.3-109380.6" wire $0\dec31_dec_sub24_cry_out[0:0] attribute \src "libresoc.v:109438.3-109456.6" wire width 5 $0\dec31_dec_sub24_form[4:0] attribute \src "libresoc.v:109020.3-109038.6" wire width 14 $0\dec31_dec_sub24_function_unit[13:0] attribute \src "libresoc.v:109571.3-109589.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] attribute \src "libresoc.v:109590.3-109608.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] attribute \src "libresoc.v:109609.3-109627.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] attribute \src "libresoc.v:109229.3-109247.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] attribute \src "libresoc.v:109324.3-109342.6" wire $0\dec31_dec_sub24_inv_a[0:0] attribute \src "libresoc.v:109343.3-109361.6" wire $0\dec31_dec_sub24_inv_out[0:0] attribute \src "libresoc.v:109457.3-109475.6" wire $0\dec31_dec_sub24_is_32b[0:0] attribute \src "libresoc.v:109210.3-109228.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] attribute \src "libresoc.v:109495.3-109513.6" wire $0\dec31_dec_sub24_lk[0:0] attribute \src "libresoc.v:109628.3-109646.6" wire width 3 $0\dec31_dec_sub24_out_sel[2:0] attribute \src "libresoc.v:109267.3-109285.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] attribute \src "libresoc.v:109419.3-109437.6" wire $0\dec31_dec_sub24_rsrv[0:0] attribute \src "libresoc.v:109514.3-109532.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] attribute \src "libresoc.v:109476.3-109494.6" wire $0\dec31_dec_sub24_sgn[0:0] attribute \src "libresoc.v:109400.3-109418.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] attribute \src "libresoc.v:109172.3-109190.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] attribute \src "libresoc.v:109191.3-109209.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] attribute \src "libresoc.v:109077.3-109095.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] attribute \src "libresoc.v:109096.3-109114.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] attribute \src "libresoc.v:109115.3-109133.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] attribute \src "libresoc.v:109153.3-109171.6" wire width 3 $0\dec31_dec_sub24_sv_out2[2:0] attribute \src "libresoc.v:109134.3-109152.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] attribute \src "libresoc.v:109248.3-109266.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] attribute \src "libresoc.v:108672.7-108672.20" wire $0\initial[0:0] attribute \src "libresoc.v:109533.3-109551.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] attribute \src "libresoc.v:109552.3-109570.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] attribute \src "libresoc.v:109305.3-109323.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] attribute \src "libresoc.v:109381.3-109399.6" wire $1\dec31_dec_sub24_br[0:0] attribute \src "libresoc.v:109039.3-109057.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] attribute \src "libresoc.v:109058.3-109076.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] attribute \src "libresoc.v:109286.3-109304.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:109362.3-109380.6" wire $1\dec31_dec_sub24_cry_out[0:0] attribute \src "libresoc.v:109438.3-109456.6" wire width 5 $1\dec31_dec_sub24_form[4:0] attribute \src "libresoc.v:109020.3-109038.6" wire width 14 $1\dec31_dec_sub24_function_unit[13:0] attribute \src "libresoc.v:109571.3-109589.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] attribute \src "libresoc.v:109590.3-109608.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] attribute \src "libresoc.v:109609.3-109627.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] attribute \src "libresoc.v:109229.3-109247.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] attribute \src "libresoc.v:109324.3-109342.6" wire $1\dec31_dec_sub24_inv_a[0:0] attribute \src "libresoc.v:109343.3-109361.6" wire $1\dec31_dec_sub24_inv_out[0:0] attribute \src "libresoc.v:109457.3-109475.6" wire $1\dec31_dec_sub24_is_32b[0:0] attribute \src "libresoc.v:109210.3-109228.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] attribute \src "libresoc.v:109495.3-109513.6" wire $1\dec31_dec_sub24_lk[0:0] attribute \src "libresoc.v:109628.3-109646.6" wire width 3 $1\dec31_dec_sub24_out_sel[2:0] attribute \src "libresoc.v:109267.3-109285.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] attribute \src "libresoc.v:109419.3-109437.6" wire $1\dec31_dec_sub24_rsrv[0:0] attribute \src "libresoc.v:109514.3-109532.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] attribute \src "libresoc.v:109476.3-109494.6" wire $1\dec31_dec_sub24_sgn[0:0] attribute \src "libresoc.v:109400.3-109418.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] attribute \src "libresoc.v:109172.3-109190.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] attribute \src "libresoc.v:109191.3-109209.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] attribute \src "libresoc.v:109077.3-109095.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] attribute \src "libresoc.v:109096.3-109114.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] attribute \src "libresoc.v:109115.3-109133.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] attribute \src "libresoc.v:109153.3-109171.6" wire width 3 $1\dec31_dec_sub24_sv_out2[2:0] attribute \src "libresoc.v:109134.3-109152.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] attribute \src "libresoc.v:109248.3-109266.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub24_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub24_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub24_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub24_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub24_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub24_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub24_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub24_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub24_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub24_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub24_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub24_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub24_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub24_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub24_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub24_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub24_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub24_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub24_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub24_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub24_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub24_upd attribute \src "libresoc.v:108672.7-108672.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:108672.7-108672.20" process $proc$libresoc.v:108672$4242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:109020.3-109038.6" process $proc$libresoc.v:109020$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] attribute \src "libresoc.v:109021.5-109021.29" switch \initial attribute \src "libresoc.v:109021.9-109021.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000001000 case assign $1\dec31_dec_sub24_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end attribute \src "libresoc.v:109039.3-109057.6" process $proc$libresoc.v:109039$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] attribute \src "libresoc.v:109040.5-109040.29" switch \initial attribute \src "libresoc.v:109040.9-109040.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end attribute \src "libresoc.v:109058.3-109076.6" process $proc$libresoc.v:109058$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] attribute \src "libresoc.v:109059.5-109059.29" switch \initial attribute \src "libresoc.v:109059.9-109059.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end attribute \src "libresoc.v:109077.3-109095.6" process $proc$libresoc.v:109077$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] attribute \src "libresoc.v:109078.5-109078.29" switch \initial attribute \src "libresoc.v:109078.9-109078.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 case assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end attribute \src "libresoc.v:109096.3-109114.6" process $proc$libresoc.v:109096$4213 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] attribute \src "libresoc.v:109097.5-109097.29" switch \initial attribute \src "libresoc.v:109097.9-109097.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 case assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end attribute \src "libresoc.v:109115.3-109133.6" process $proc$libresoc.v:109115$4214 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] attribute \src "libresoc.v:109116.5-109116.29" switch \initial attribute \src "libresoc.v:109116.9-109116.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 case assign $1\dec31_dec_sub24_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end attribute \src "libresoc.v:109134.3-109152.6" process $proc$libresoc.v:109134$4215 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] attribute \src "libresoc.v:109135.5-109135.29" switch \initial attribute \src "libresoc.v:109135.9-109135.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub24_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end attribute \src "libresoc.v:109153.3-109171.6" process $proc$libresoc.v:109153$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0] attribute \src "libresoc.v:109154.5-109154.29" switch \initial attribute \src "libresoc.v:109154.9-109154.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub24_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0] end attribute \src "libresoc.v:109172.3-109190.6" process $proc$libresoc.v:109172$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] attribute \src "libresoc.v:109173.5-109173.29" switch \initial attribute \src "libresoc.v:109173.9-109173.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end attribute \src "libresoc.v:109191.3-109209.6" process $proc$libresoc.v:109191$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] attribute \src "libresoc.v:109192.5-109192.29" switch \initial attribute \src "libresoc.v:109192.9-109192.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end attribute \src "libresoc.v:109210.3-109228.6" process $proc$libresoc.v:109210$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] attribute \src "libresoc.v:109211.5-109211.29" switch \initial attribute \src "libresoc.v:109211.9-109211.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end attribute \src "libresoc.v:109229.3-109247.6" process $proc$libresoc.v:109229$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] attribute \src "libresoc.v:109230.5-109230.29" switch \initial attribute \src "libresoc.v:109230.9-109230.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 case assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end attribute \src "libresoc.v:109248.3-109266.6" process $proc$libresoc.v:109248$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] attribute \src "libresoc.v:109249.5-109249.29" switch \initial attribute \src "libresoc.v:109249.9-109249.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_upd[1:0] 2'00 case assign $1\dec31_dec_sub24_upd[1:0] 2'00 end sync always update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end attribute \src "libresoc.v:109267.3-109285.6" process $proc$libresoc.v:109267$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] attribute \src "libresoc.v:109268.5-109268.29" switch \initial attribute \src "libresoc.v:109268.9-109268.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end attribute \src "libresoc.v:109286.3-109304.6" process $proc$libresoc.v:109286$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:109287.5-109287.29" switch \initial attribute \src "libresoc.v:109287.9-109287.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end attribute \src "libresoc.v:109305.3-109323.6" process $proc$libresoc.v:109305$4224 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] attribute \src "libresoc.v:109306.5-109306.29" switch \initial attribute \src "libresoc.v:109306.9-109306.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100110 case assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end attribute \src "libresoc.v:109324.3-109342.6" process $proc$libresoc.v:109324$4225 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] attribute \src "libresoc.v:109325.5-109325.29" switch \initial attribute \src "libresoc.v:109325.9-109325.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end attribute \src "libresoc.v:109343.3-109361.6" process $proc$libresoc.v:109343$4226 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] attribute \src "libresoc.v:109344.5-109344.29" switch \initial attribute \src "libresoc.v:109344.9-109344.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end attribute \src "libresoc.v:109362.3-109380.6" process $proc$libresoc.v:109362$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] attribute \src "libresoc.v:109363.5-109363.29" switch \initial attribute \src "libresoc.v:109363.9-109363.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end attribute \src "libresoc.v:109381.3-109399.6" process $proc$libresoc.v:109381$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] attribute \src "libresoc.v:109382.5-109382.29" switch \initial attribute \src "libresoc.v:109382.9-109382.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_br[0:0] 1'0 case assign $1\dec31_dec_sub24_br[0:0] 1'0 end sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end attribute \src "libresoc.v:109400.3-109418.6" process $proc$libresoc.v:109400$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] attribute \src "libresoc.v:109401.5-109401.29" switch \initial attribute \src "libresoc.v:109401.9-109401.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end attribute \src "libresoc.v:109419.3-109437.6" process $proc$libresoc.v:109419$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] attribute \src "libresoc.v:109420.5-109420.29" switch \initial attribute \src "libresoc.v:109420.9-109420.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end attribute \src "libresoc.v:109438.3-109456.6" process $proc$libresoc.v:109438$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] attribute \src "libresoc.v:109439.5-109439.29" switch \initial attribute \src "libresoc.v:109439.9-109439.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_form[4:0] 5'01000 case assign $1\dec31_dec_sub24_form[4:0] 5'00000 end sync always update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end attribute \src "libresoc.v:109457.3-109475.6" process $proc$libresoc.v:109457$4232 assign { } { } assign { } { } assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] attribute \src "libresoc.v:109458.5-109458.29" switch \initial attribute \src "libresoc.v:109458.9-109458.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 case assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end attribute \src "libresoc.v:109476.3-109494.6" process $proc$libresoc.v:109476$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] attribute \src "libresoc.v:109477.5-109477.29" switch \initial attribute \src "libresoc.v:109477.9-109477.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sgn[0:0] 1'0 case assign $1\dec31_dec_sub24_sgn[0:0] 1'0 end sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end attribute \src "libresoc.v:109495.3-109513.6" process $proc$libresoc.v:109495$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] attribute \src "libresoc.v:109496.5-109496.29" switch \initial attribute \src "libresoc.v:109496.9-109496.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_lk[0:0] 1'0 case assign $1\dec31_dec_sub24_lk[0:0] 1'0 end sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end attribute \src "libresoc.v:109514.3-109532.6" process $proc$libresoc.v:109514$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] attribute \src "libresoc.v:109515.5-109515.29" switch \initial attribute \src "libresoc.v:109515.9-109515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end attribute \src "libresoc.v:109533.3-109551.6" process $proc$libresoc.v:109533$4236 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] attribute \src "libresoc.v:109534.5-109534.29" switch \initial attribute \src "libresoc.v:109534.9-109534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end attribute \src "libresoc.v:109552.3-109570.6" process $proc$libresoc.v:109552$4237 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] attribute \src "libresoc.v:109553.5-109553.29" switch \initial attribute \src "libresoc.v:109553.9-109553.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 case assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end attribute \src "libresoc.v:109571.3-109589.6" process $proc$libresoc.v:109571$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] attribute \src "libresoc.v:109572.5-109572.29" switch \initial attribute \src "libresoc.v:109572.9-109572.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 case assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end attribute \src "libresoc.v:109590.3-109608.6" process $proc$libresoc.v:109590$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] attribute \src "libresoc.v:109591.5-109591.29" switch \initial attribute \src "libresoc.v:109591.9-109591.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end attribute \src "libresoc.v:109609.3-109627.6" process $proc$libresoc.v:109609$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] attribute \src "libresoc.v:109610.5-109610.29" switch \initial attribute \src "libresoc.v:109610.9-109610.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 case assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end attribute \src "libresoc.v:109628.3-109646.6" process $proc$libresoc.v:109628$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] attribute \src "libresoc.v:109629.5-109629.29" switch \initial attribute \src "libresoc.v:109629.9-109629.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub24_out_sel[2:0] 3'010 case assign $1\dec31_dec_sub24_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:109652.1-111718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 attribute \src "libresoc.v:111405.3-111456.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] attribute \src "libresoc.v:111457.3-111508.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] attribute \src "libresoc.v:110781.3-110832.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] attribute \src "libresoc.v:110989.3-111040.6" wire $0\dec31_dec_sub26_br[0:0] attribute \src "libresoc.v:110053.3-110104.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:110105.3-110156.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:110729.3-110780.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:110937.3-110988.6" wire $0\dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:111145.3-111196.6" wire width 5 $0\dec31_dec_sub26_form[4:0] attribute \src "libresoc.v:110001.3-110052.6" wire width 14 $0\dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:111509.3-111560.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:111561.3-111612.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:111613.3-111664.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] attribute \src "libresoc.v:110573.3-110624.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:110833.3-110884.6" wire $0\dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:110885.3-110936.6" wire $0\dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:111197.3-111248.6" wire $0\dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:110521.3-110572.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:111301.3-111352.6" wire $0\dec31_dec_sub26_lk[0:0] attribute \src "libresoc.v:111665.3-111716.6" wire width 3 $0\dec31_dec_sub26_out_sel[2:0] attribute \src "libresoc.v:110677.3-110728.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:111093.3-111144.6" wire $0\dec31_dec_sub26_rsrv[0:0] attribute \src "libresoc.v:111353.3-111404.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] attribute \src "libresoc.v:111249.3-111300.6" wire $0\dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:111041.3-111092.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] attribute \src "libresoc.v:110417.3-110468.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] attribute \src "libresoc.v:110469.3-110520.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] attribute \src "libresoc.v:110157.3-110208.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] attribute \src "libresoc.v:110209.3-110260.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] attribute \src "libresoc.v:110261.3-110312.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] attribute \src "libresoc.v:110365.3-110416.6" wire width 3 $0\dec31_dec_sub26_sv_out2[2:0] attribute \src "libresoc.v:110313.3-110364.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] attribute \src "libresoc.v:110625.3-110676.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] attribute \src "libresoc.v:109653.7-109653.20" wire $0\initial[0:0] attribute \src "libresoc.v:111405.3-111456.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] attribute \src "libresoc.v:111457.3-111508.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] attribute \src "libresoc.v:110781.3-110832.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] attribute \src "libresoc.v:110989.3-111040.6" wire $1\dec31_dec_sub26_br[0:0] attribute \src "libresoc.v:110053.3-110104.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:110105.3-110156.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:110729.3-110780.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:110937.3-110988.6" wire $1\dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:111145.3-111196.6" wire width 5 $1\dec31_dec_sub26_form[4:0] attribute \src "libresoc.v:110001.3-110052.6" wire width 14 $1\dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:111509.3-111560.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:111561.3-111612.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:111613.3-111664.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] attribute \src "libresoc.v:110573.3-110624.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:110833.3-110884.6" wire $1\dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:110885.3-110936.6" wire $1\dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:111197.3-111248.6" wire $1\dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:110521.3-110572.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:111301.3-111352.6" wire $1\dec31_dec_sub26_lk[0:0] attribute \src "libresoc.v:111665.3-111716.6" wire width 3 $1\dec31_dec_sub26_out_sel[2:0] attribute \src "libresoc.v:110677.3-110728.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:111093.3-111144.6" wire $1\dec31_dec_sub26_rsrv[0:0] attribute \src "libresoc.v:111353.3-111404.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] attribute \src "libresoc.v:111249.3-111300.6" wire $1\dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:111041.3-111092.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] attribute \src "libresoc.v:110417.3-110468.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] attribute \src "libresoc.v:110469.3-110520.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] attribute \src "libresoc.v:110157.3-110208.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] attribute \src "libresoc.v:110209.3-110260.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] attribute \src "libresoc.v:110261.3-110312.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] attribute \src "libresoc.v:110365.3-110416.6" wire width 3 $1\dec31_dec_sub26_sv_out2[2:0] attribute \src "libresoc.v:110313.3-110364.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] attribute \src "libresoc.v:110625.3-110676.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub26_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub26_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub26_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub26_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub26_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub26_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub26_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub26_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub26_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub26_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub26_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub26_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub26_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub26_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub26_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub26_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub26_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub26_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub26_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub26_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub26_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub26_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub26_upd attribute \src "libresoc.v:109653.7-109653.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:109653.7-109653.20" process $proc$libresoc.v:109653$4276 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:110001.3-110052.6" process $proc$libresoc.v:110001$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] attribute \src "libresoc.v:110002.5-110002.29" switch \initial attribute \src "libresoc.v:110002.9-110002.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000001000 case assign $1\dec31_dec_sub26_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end attribute \src "libresoc.v:110053.3-110104.6" process $proc$libresoc.v:110053$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] attribute \src "libresoc.v:110054.5-110054.29" switch \initial attribute \src "libresoc.v:110054.9-110054.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end attribute \src "libresoc.v:110105.3-110156.6" process $proc$libresoc.v:110105$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] attribute \src "libresoc.v:110106.5-110106.29" switch \initial attribute \src "libresoc.v:110106.9-110106.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end attribute \src "libresoc.v:110157.3-110208.6" process $proc$libresoc.v:110157$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] attribute \src "libresoc.v:110158.5-110158.29" switch \initial attribute \src "libresoc.v:110158.9-110158.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 case assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end attribute \src "libresoc.v:110209.3-110260.6" process $proc$libresoc.v:110209$4247 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] attribute \src "libresoc.v:110210.5-110210.29" switch \initial attribute \src "libresoc.v:110210.9-110210.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end attribute \src "libresoc.v:110261.3-110312.6" process $proc$libresoc.v:110261$4248 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] attribute \src "libresoc.v:110262.5-110262.29" switch \initial attribute \src "libresoc.v:110262.9-110262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 case assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end attribute \src "libresoc.v:110313.3-110364.6" process $proc$libresoc.v:110313$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] attribute \src "libresoc.v:110314.5-110314.29" switch \initial attribute \src "libresoc.v:110314.9-110314.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub26_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end attribute \src "libresoc.v:110365.3-110416.6" process $proc$libresoc.v:110365$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0] attribute \src "libresoc.v:110366.5-110366.29" switch \initial attribute \src "libresoc.v:110366.9-110366.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub26_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0] end attribute \src "libresoc.v:110417.3-110468.6" process $proc$libresoc.v:110417$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] attribute \src "libresoc.v:110418.5-110418.29" switch \initial attribute \src "libresoc.v:110418.9-110418.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end attribute \src "libresoc.v:110469.3-110520.6" process $proc$libresoc.v:110469$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] attribute \src "libresoc.v:110470.5-110470.29" switch \initial attribute \src "libresoc.v:110470.9-110470.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end attribute \src "libresoc.v:110521.3-110572.6" process $proc$libresoc.v:110521$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] attribute \src "libresoc.v:110522.5-110522.29" switch \initial attribute \src "libresoc.v:110522.9-110522.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end attribute \src "libresoc.v:110573.3-110624.6" process $proc$libresoc.v:110573$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] attribute \src "libresoc.v:110574.5-110574.29" switch \initial attribute \src "libresoc.v:110574.9-110574.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 case assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end attribute \src "libresoc.v:110625.3-110676.6" process $proc$libresoc.v:110625$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] attribute \src "libresoc.v:110626.5-110626.29" switch \initial attribute \src "libresoc.v:110626.9-110626.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_upd[1:0] 2'00 case assign $1\dec31_dec_sub26_upd[1:0] 2'00 end sync always update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end attribute \src "libresoc.v:110677.3-110728.6" process $proc$libresoc.v:110677$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] attribute \src "libresoc.v:110678.5-110678.29" switch \initial attribute \src "libresoc.v:110678.9-110678.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end attribute \src "libresoc.v:110729.3-110780.6" process $proc$libresoc.v:110729$4257 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] attribute \src "libresoc.v:110730.5-110730.29" switch \initial attribute \src "libresoc.v:110730.9-110730.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end attribute \src "libresoc.v:110781.3-110832.6" process $proc$libresoc.v:110781$4258 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] attribute \src "libresoc.v:110782.5-110782.29" switch \initial attribute \src "libresoc.v:110782.9-110782.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100010 case assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end attribute \src "libresoc.v:110833.3-110884.6" process $proc$libresoc.v:110833$4259 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] attribute \src "libresoc.v:110834.5-110834.29" switch \initial attribute \src "libresoc.v:110834.9-110834.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end attribute \src "libresoc.v:110885.3-110936.6" process $proc$libresoc.v:110885$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] attribute \src "libresoc.v:110886.5-110886.29" switch \initial attribute \src "libresoc.v:110886.9-110886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end attribute \src "libresoc.v:110937.3-110988.6" process $proc$libresoc.v:110937$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] attribute \src "libresoc.v:110938.5-110938.29" switch \initial attribute \src "libresoc.v:110938.9-110938.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 case assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end attribute \src "libresoc.v:110989.3-111040.6" process $proc$libresoc.v:110989$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] attribute \src "libresoc.v:110990.5-110990.29" switch \initial attribute \src "libresoc.v:110990.9-110990.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_br[0:0] 1'0 case assign $1\dec31_dec_sub26_br[0:0] 1'0 end sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end attribute \src "libresoc.v:111041.3-111092.6" process $proc$libresoc.v:111041$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] attribute \src "libresoc.v:111042.5-111042.29" switch \initial attribute \src "libresoc.v:111042.9-111042.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end attribute \src "libresoc.v:111093.3-111144.6" process $proc$libresoc.v:111093$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] attribute \src "libresoc.v:111094.5-111094.29" switch \initial attribute \src "libresoc.v:111094.9-111094.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end attribute \src "libresoc.v:111145.3-111196.6" process $proc$libresoc.v:111145$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] attribute \src "libresoc.v:111146.5-111146.29" switch \initial attribute \src "libresoc.v:111146.9-111146.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_form[4:0] 5'10000 case assign $1\dec31_dec_sub26_form[4:0] 5'00000 end sync always update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end attribute \src "libresoc.v:111197.3-111248.6" process $proc$libresoc.v:111197$4266 assign { } { } assign { } { } assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] attribute \src "libresoc.v:111198.5-111198.29" switch \initial attribute \src "libresoc.v:111198.9-111198.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end attribute \src "libresoc.v:111249.3-111300.6" process $proc$libresoc.v:111249$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] attribute \src "libresoc.v:111250.5-111250.29" switch \initial attribute \src "libresoc.v:111250.9-111250.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sgn[0:0] 1'1 case assign $1\dec31_dec_sub26_sgn[0:0] 1'0 end sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end attribute \src "libresoc.v:111301.3-111352.6" process $proc$libresoc.v:111301$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] attribute \src "libresoc.v:111302.5-111302.29" switch \initial attribute \src "libresoc.v:111302.9-111302.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_lk[0:0] 1'0 case assign $1\dec31_dec_sub26_lk[0:0] 1'0 end sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end attribute \src "libresoc.v:111353.3-111404.6" process $proc$libresoc.v:111353$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] attribute \src "libresoc.v:111354.5-111354.29" switch \initial attribute \src "libresoc.v:111354.9-111354.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end attribute \src "libresoc.v:111405.3-111456.6" process $proc$libresoc.v:111405$4270 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] attribute \src "libresoc.v:111406.5-111406.29" switch \initial attribute \src "libresoc.v:111406.9-111406.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end attribute \src "libresoc.v:111457.3-111508.6" process $proc$libresoc.v:111457$4271 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] attribute \src "libresoc.v:111458.5-111458.29" switch \initial attribute \src "libresoc.v:111458.9-111458.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end attribute \src "libresoc.v:111509.3-111560.6" process $proc$libresoc.v:111509$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] attribute \src "libresoc.v:111510.5-111510.29" switch \initial attribute \src "libresoc.v:111510.9-111510.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 case assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end attribute \src "libresoc.v:111561.3-111612.6" process $proc$libresoc.v:111561$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] attribute \src "libresoc.v:111562.5-111562.29" switch \initial attribute \src "libresoc.v:111562.9-111562.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 case assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end attribute \src "libresoc.v:111613.3-111664.6" process $proc$libresoc.v:111613$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] attribute \src "libresoc.v:111614.5-111614.29" switch \initial attribute \src "libresoc.v:111614.9-111614.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 case assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end attribute \src "libresoc.v:111665.3-111716.6" process $proc$libresoc.v:111665$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] attribute \src "libresoc.v:111666.5-111666.29" switch \initial attribute \src "libresoc.v:111666.9-111666.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub26_out_sel[2:0] 3'010 case assign $1\dec31_dec_sub26_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:111722.1-112699.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 attribute \src "libresoc.v:112584.3-112602.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] attribute \src "libresoc.v:112603.3-112621.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] attribute \src "libresoc.v:112356.3-112374.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] attribute \src "libresoc.v:112432.3-112450.6" wire $0\dec31_dec_sub27_br[0:0] attribute \src "libresoc.v:112090.3-112108.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] attribute \src "libresoc.v:112109.3-112127.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] attribute \src "libresoc.v:112337.3-112355.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:112413.3-112431.6" wire $0\dec31_dec_sub27_cry_out[0:0] attribute \src "libresoc.v:112489.3-112507.6" wire width 5 $0\dec31_dec_sub27_form[4:0] attribute \src "libresoc.v:112071.3-112089.6" wire width 14 $0\dec31_dec_sub27_function_unit[13:0] attribute \src "libresoc.v:112622.3-112640.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] attribute \src "libresoc.v:112641.3-112659.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] attribute \src "libresoc.v:112660.3-112678.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] attribute \src "libresoc.v:112280.3-112298.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:112375.3-112393.6" wire $0\dec31_dec_sub27_inv_a[0:0] attribute \src "libresoc.v:112394.3-112412.6" wire $0\dec31_dec_sub27_inv_out[0:0] attribute \src "libresoc.v:112508.3-112526.6" wire $0\dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:112261.3-112279.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] attribute \src "libresoc.v:112546.3-112564.6" wire $0\dec31_dec_sub27_lk[0:0] attribute \src "libresoc.v:112679.3-112697.6" wire width 3 $0\dec31_dec_sub27_out_sel[2:0] attribute \src "libresoc.v:112318.3-112336.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] attribute \src "libresoc.v:112470.3-112488.6" wire $0\dec31_dec_sub27_rsrv[0:0] attribute \src "libresoc.v:112565.3-112583.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] attribute \src "libresoc.v:112527.3-112545.6" wire $0\dec31_dec_sub27_sgn[0:0] attribute \src "libresoc.v:112451.3-112469.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] attribute \src "libresoc.v:112223.3-112241.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] attribute \src "libresoc.v:112242.3-112260.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] attribute \src "libresoc.v:112128.3-112146.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] attribute \src "libresoc.v:112147.3-112165.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] attribute \src "libresoc.v:112166.3-112184.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] attribute \src "libresoc.v:112204.3-112222.6" wire width 3 $0\dec31_dec_sub27_sv_out2[2:0] attribute \src "libresoc.v:112185.3-112203.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] attribute \src "libresoc.v:112299.3-112317.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] attribute \src "libresoc.v:111723.7-111723.20" wire $0\initial[0:0] attribute \src "libresoc.v:112584.3-112602.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] attribute \src "libresoc.v:112603.3-112621.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] attribute \src "libresoc.v:112356.3-112374.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] attribute \src "libresoc.v:112432.3-112450.6" wire $1\dec31_dec_sub27_br[0:0] attribute \src "libresoc.v:112090.3-112108.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] attribute \src "libresoc.v:112109.3-112127.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] attribute \src "libresoc.v:112337.3-112355.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:112413.3-112431.6" wire $1\dec31_dec_sub27_cry_out[0:0] attribute \src "libresoc.v:112489.3-112507.6" wire width 5 $1\dec31_dec_sub27_form[4:0] attribute \src "libresoc.v:112071.3-112089.6" wire width 14 $1\dec31_dec_sub27_function_unit[13:0] attribute \src "libresoc.v:112622.3-112640.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] attribute \src "libresoc.v:112641.3-112659.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] attribute \src "libresoc.v:112660.3-112678.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] attribute \src "libresoc.v:112280.3-112298.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:112375.3-112393.6" wire $1\dec31_dec_sub27_inv_a[0:0] attribute \src "libresoc.v:112394.3-112412.6" wire $1\dec31_dec_sub27_inv_out[0:0] attribute \src "libresoc.v:112508.3-112526.6" wire $1\dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:112261.3-112279.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] attribute \src "libresoc.v:112546.3-112564.6" wire $1\dec31_dec_sub27_lk[0:0] attribute \src "libresoc.v:112679.3-112697.6" wire width 3 $1\dec31_dec_sub27_out_sel[2:0] attribute \src "libresoc.v:112318.3-112336.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] attribute \src "libresoc.v:112470.3-112488.6" wire $1\dec31_dec_sub27_rsrv[0:0] attribute \src "libresoc.v:112565.3-112583.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] attribute \src "libresoc.v:112527.3-112545.6" wire $1\dec31_dec_sub27_sgn[0:0] attribute \src "libresoc.v:112451.3-112469.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] attribute \src "libresoc.v:112223.3-112241.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] attribute \src "libresoc.v:112242.3-112260.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] attribute \src "libresoc.v:112128.3-112146.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] attribute \src "libresoc.v:112147.3-112165.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] attribute \src "libresoc.v:112166.3-112184.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] attribute \src "libresoc.v:112204.3-112222.6" wire width 3 $1\dec31_dec_sub27_sv_out2[2:0] attribute \src "libresoc.v:112185.3-112203.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] attribute \src "libresoc.v:112299.3-112317.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub27_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub27_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub27_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub27_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub27_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub27_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub27_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub27_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub27_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub27_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub27_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub27_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub27_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub27_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub27_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub27_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub27_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub27_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub27_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub27_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub27_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub27_upd attribute \src "libresoc.v:111723.7-111723.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:111723.7-111723.20" process $proc$libresoc.v:111723$4310 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:112071.3-112089.6" process $proc$libresoc.v:112071$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] attribute \src "libresoc.v:112072.5-112072.29" switch \initial attribute \src "libresoc.v:112072.9-112072.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000001000 case assign $1\dec31_dec_sub27_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end attribute \src "libresoc.v:112090.3-112108.6" process $proc$libresoc.v:112090$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] attribute \src "libresoc.v:112091.5-112091.29" switch \initial attribute \src "libresoc.v:112091.9-112091.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end attribute \src "libresoc.v:112109.3-112127.6" process $proc$libresoc.v:112109$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] attribute \src "libresoc.v:112110.5-112110.29" switch \initial attribute \src "libresoc.v:112110.9-112110.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end attribute \src "libresoc.v:112128.3-112146.6" process $proc$libresoc.v:112128$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] attribute \src "libresoc.v:112129.5-112129.29" switch \initial attribute \src "libresoc.v:112129.9-112129.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 case assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end attribute \src "libresoc.v:112147.3-112165.6" process $proc$libresoc.v:112147$4281 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] attribute \src "libresoc.v:112148.5-112148.29" switch \initial attribute \src "libresoc.v:112148.9-112148.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 case assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end attribute \src "libresoc.v:112166.3-112184.6" process $proc$libresoc.v:112166$4282 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] attribute \src "libresoc.v:112167.5-112167.29" switch \initial attribute \src "libresoc.v:112167.9-112167.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 case assign $1\dec31_dec_sub27_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end attribute \src "libresoc.v:112185.3-112203.6" process $proc$libresoc.v:112185$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] attribute \src "libresoc.v:112186.5-112186.29" switch \initial attribute \src "libresoc.v:112186.9-112186.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub27_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end attribute \src "libresoc.v:112204.3-112222.6" process $proc$libresoc.v:112204$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0] attribute \src "libresoc.v:112205.5-112205.29" switch \initial attribute \src "libresoc.v:112205.9-112205.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub27_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0] end attribute \src "libresoc.v:112223.3-112241.6" process $proc$libresoc.v:112223$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] attribute \src "libresoc.v:112224.5-112224.29" switch \initial attribute \src "libresoc.v:112224.9-112224.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end attribute \src "libresoc.v:112242.3-112260.6" process $proc$libresoc.v:112242$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] attribute \src "libresoc.v:112243.5-112243.29" switch \initial attribute \src "libresoc.v:112243.9-112243.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end attribute \src "libresoc.v:112261.3-112279.6" process $proc$libresoc.v:112261$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] attribute \src "libresoc.v:112262.5-112262.29" switch \initial attribute \src "libresoc.v:112262.9-112262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end attribute \src "libresoc.v:112280.3-112298.6" process $proc$libresoc.v:112280$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] attribute \src "libresoc.v:112281.5-112281.29" switch \initial attribute \src "libresoc.v:112281.9-112281.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 case assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end attribute \src "libresoc.v:112299.3-112317.6" process $proc$libresoc.v:112299$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] attribute \src "libresoc.v:112300.5-112300.29" switch \initial attribute \src "libresoc.v:112300.9-112300.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_upd[1:0] 2'00 case assign $1\dec31_dec_sub27_upd[1:0] 2'00 end sync always update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end attribute \src "libresoc.v:112318.3-112336.6" process $proc$libresoc.v:112318$4290 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] attribute \src "libresoc.v:112319.5-112319.29" switch \initial attribute \src "libresoc.v:112319.9-112319.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end attribute \src "libresoc.v:112337.3-112355.6" process $proc$libresoc.v:112337$4291 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:112338.5-112338.29" switch \initial attribute \src "libresoc.v:112338.9-112338.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end attribute \src "libresoc.v:112356.3-112374.6" process $proc$libresoc.v:112356$4292 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] attribute \src "libresoc.v:112357.5-112357.29" switch \initial attribute \src "libresoc.v:112357.9-112357.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011111 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100101 case assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end attribute \src "libresoc.v:112375.3-112393.6" process $proc$libresoc.v:112375$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] attribute \src "libresoc.v:112376.5-112376.29" switch \initial attribute \src "libresoc.v:112376.9-112376.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end attribute \src "libresoc.v:112394.3-112412.6" process $proc$libresoc.v:112394$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] attribute \src "libresoc.v:112395.5-112395.29" switch \initial attribute \src "libresoc.v:112395.9-112395.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end attribute \src "libresoc.v:112413.3-112431.6" process $proc$libresoc.v:112413$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] attribute \src "libresoc.v:112414.5-112414.29" switch \initial attribute \src "libresoc.v:112414.9-112414.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end attribute \src "libresoc.v:112432.3-112450.6" process $proc$libresoc.v:112432$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] attribute \src "libresoc.v:112433.5-112433.29" switch \initial attribute \src "libresoc.v:112433.9-112433.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_br[0:0] 1'0 case assign $1\dec31_dec_sub27_br[0:0] 1'0 end sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end attribute \src "libresoc.v:112451.3-112469.6" process $proc$libresoc.v:112451$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] attribute \src "libresoc.v:112452.5-112452.29" switch \initial attribute \src "libresoc.v:112452.9-112452.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end attribute \src "libresoc.v:112470.3-112488.6" process $proc$libresoc.v:112470$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] attribute \src "libresoc.v:112471.5-112471.29" switch \initial attribute \src "libresoc.v:112471.9-112471.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end attribute \src "libresoc.v:112489.3-112507.6" process $proc$libresoc.v:112489$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] attribute \src "libresoc.v:112490.5-112490.29" switch \initial attribute \src "libresoc.v:112490.9-112490.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_form[4:0] 5'10000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_form[4:0] 5'01000 case assign $1\dec31_dec_sub27_form[4:0] 5'00000 end sync always update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end attribute \src "libresoc.v:112508.3-112526.6" process $proc$libresoc.v:112508$4300 assign { } { } assign { } { } assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] attribute \src "libresoc.v:112509.5-112509.29" switch \initial attribute \src "libresoc.v:112509.9-112509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end attribute \src "libresoc.v:112527.3-112545.6" process $proc$libresoc.v:112527$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] attribute \src "libresoc.v:112528.5-112528.29" switch \initial attribute \src "libresoc.v:112528.9-112528.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sgn[0:0] 1'0 case assign $1\dec31_dec_sub27_sgn[0:0] 1'0 end sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end attribute \src "libresoc.v:112546.3-112564.6" process $proc$libresoc.v:112546$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] attribute \src "libresoc.v:112547.5-112547.29" switch \initial attribute \src "libresoc.v:112547.9-112547.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_lk[0:0] 1'0 case assign $1\dec31_dec_sub27_lk[0:0] 1'0 end sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end attribute \src "libresoc.v:112565.3-112583.6" process $proc$libresoc.v:112565$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] attribute \src "libresoc.v:112566.5-112566.29" switch \initial attribute \src "libresoc.v:112566.9-112566.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end attribute \src "libresoc.v:112584.3-112602.6" process $proc$libresoc.v:112584$4304 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] attribute \src "libresoc.v:112585.5-112585.29" switch \initial attribute \src "libresoc.v:112585.9-112585.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end attribute \src "libresoc.v:112603.3-112621.6" process $proc$libresoc.v:112603$4305 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] attribute \src "libresoc.v:112604.5-112604.29" switch \initial attribute \src "libresoc.v:112604.9-112604.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 case assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end attribute \src "libresoc.v:112622.3-112640.6" process $proc$libresoc.v:112622$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] attribute \src "libresoc.v:112623.5-112623.29" switch \initial attribute \src "libresoc.v:112623.9-112623.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 case assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end attribute \src "libresoc.v:112641.3-112659.6" process $proc$libresoc.v:112641$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] attribute \src "libresoc.v:112642.5-112642.29" switch \initial attribute \src "libresoc.v:112642.9-112642.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end attribute \src "libresoc.v:112660.3-112678.6" process $proc$libresoc.v:112660$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] attribute \src "libresoc.v:112661.5-112661.29" switch \initial attribute \src "libresoc.v:112661.9-112661.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 case assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end attribute \src "libresoc.v:112679.3-112697.6" process $proc$libresoc.v:112679$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] attribute \src "libresoc.v:112680.5-112680.29" switch \initial attribute \src "libresoc.v:112680.9-112680.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub27_out_sel[2:0] 3'010 case assign $1\dec31_dec_sub27_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:112703.1-114274.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 attribute \src "libresoc.v:114051.3-114087.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] attribute \src "libresoc.v:114088.3-114124.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] attribute \src "libresoc.v:113607.3-113643.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] attribute \src "libresoc.v:113755.3-113791.6" wire $0\dec31_dec_sub28_br[0:0] attribute \src "libresoc.v:113089.3-113125.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] attribute \src "libresoc.v:113126.3-113162.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] attribute \src "libresoc.v:113570.3-113606.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] attribute \src "libresoc.v:113718.3-113754.6" wire $0\dec31_dec_sub28_cry_out[0:0] attribute \src "libresoc.v:113866.3-113902.6" wire width 5 $0\dec31_dec_sub28_form[4:0] attribute \src "libresoc.v:113052.3-113088.6" wire width 14 $0\dec31_dec_sub28_function_unit[13:0] attribute \src "libresoc.v:114125.3-114161.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] attribute \src "libresoc.v:114162.3-114198.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] attribute \src "libresoc.v:114199.3-114235.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] attribute \src "libresoc.v:113459.3-113495.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] attribute \src "libresoc.v:113644.3-113680.6" wire $0\dec31_dec_sub28_inv_a[0:0] attribute \src "libresoc.v:113681.3-113717.6" wire $0\dec31_dec_sub28_inv_out[0:0] attribute \src "libresoc.v:113903.3-113939.6" wire $0\dec31_dec_sub28_is_32b[0:0] attribute \src "libresoc.v:113422.3-113458.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] attribute \src "libresoc.v:113977.3-114013.6" wire $0\dec31_dec_sub28_lk[0:0] attribute \src "libresoc.v:114236.3-114272.6" wire width 3 $0\dec31_dec_sub28_out_sel[2:0] attribute \src "libresoc.v:113533.3-113569.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] attribute \src "libresoc.v:113829.3-113865.6" wire $0\dec31_dec_sub28_rsrv[0:0] attribute \src "libresoc.v:114014.3-114050.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] attribute \src "libresoc.v:113940.3-113976.6" wire $0\dec31_dec_sub28_sgn[0:0] attribute \src "libresoc.v:113792.3-113828.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] attribute \src "libresoc.v:113348.3-113384.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] attribute \src "libresoc.v:113385.3-113421.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] attribute \src "libresoc.v:113163.3-113199.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] attribute \src "libresoc.v:113200.3-113236.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] attribute \src "libresoc.v:113237.3-113273.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] attribute \src "libresoc.v:113311.3-113347.6" wire width 3 $0\dec31_dec_sub28_sv_out2[2:0] attribute \src "libresoc.v:113274.3-113310.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] attribute \src "libresoc.v:113496.3-113532.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] attribute \src "libresoc.v:112704.7-112704.20" wire $0\initial[0:0] attribute \src "libresoc.v:114051.3-114087.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] attribute \src "libresoc.v:114088.3-114124.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] attribute \src "libresoc.v:113607.3-113643.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] attribute \src "libresoc.v:113755.3-113791.6" wire $1\dec31_dec_sub28_br[0:0] attribute \src "libresoc.v:113089.3-113125.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] attribute \src "libresoc.v:113126.3-113162.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] attribute \src "libresoc.v:113570.3-113606.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] attribute \src "libresoc.v:113718.3-113754.6" wire $1\dec31_dec_sub28_cry_out[0:0] attribute \src "libresoc.v:113866.3-113902.6" wire width 5 $1\dec31_dec_sub28_form[4:0] attribute \src "libresoc.v:113052.3-113088.6" wire width 14 $1\dec31_dec_sub28_function_unit[13:0] attribute \src "libresoc.v:114125.3-114161.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] attribute \src "libresoc.v:114162.3-114198.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] attribute \src "libresoc.v:114199.3-114235.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] attribute \src "libresoc.v:113459.3-113495.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] attribute \src "libresoc.v:113644.3-113680.6" wire $1\dec31_dec_sub28_inv_a[0:0] attribute \src "libresoc.v:113681.3-113717.6" wire $1\dec31_dec_sub28_inv_out[0:0] attribute \src "libresoc.v:113903.3-113939.6" wire $1\dec31_dec_sub28_is_32b[0:0] attribute \src "libresoc.v:113422.3-113458.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] attribute \src "libresoc.v:113977.3-114013.6" wire $1\dec31_dec_sub28_lk[0:0] attribute \src "libresoc.v:114236.3-114272.6" wire width 3 $1\dec31_dec_sub28_out_sel[2:0] attribute \src "libresoc.v:113533.3-113569.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] attribute \src "libresoc.v:113829.3-113865.6" wire $1\dec31_dec_sub28_rsrv[0:0] attribute \src "libresoc.v:114014.3-114050.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] attribute \src "libresoc.v:113940.3-113976.6" wire $1\dec31_dec_sub28_sgn[0:0] attribute \src "libresoc.v:113792.3-113828.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] attribute \src "libresoc.v:113348.3-113384.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] attribute \src "libresoc.v:113385.3-113421.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] attribute \src "libresoc.v:113163.3-113199.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] attribute \src "libresoc.v:113200.3-113236.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] attribute \src "libresoc.v:113237.3-113273.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] attribute \src "libresoc.v:113311.3-113347.6" wire width 3 $1\dec31_dec_sub28_sv_out2[2:0] attribute \src "libresoc.v:113274.3-113310.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] attribute \src "libresoc.v:113496.3-113532.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub28_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub28_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub28_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub28_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub28_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub28_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub28_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub28_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub28_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub28_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub28_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub28_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub28_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub28_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub28_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub28_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub28_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub28_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub28_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub28_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub28_upd attribute \src "libresoc.v:112704.7-112704.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:112704.7-112704.20" process $proc$libresoc.v:112704$4344 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:113052.3-113088.6" process $proc$libresoc.v:113052$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] attribute \src "libresoc.v:113053.5-113053.29" switch \initial attribute \src "libresoc.v:113053.9-113053.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000010000 case assign $1\dec31_dec_sub28_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end attribute \src "libresoc.v:113089.3-113125.6" process $proc$libresoc.v:113089$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] attribute \src "libresoc.v:113090.5-113090.29" switch \initial attribute \src "libresoc.v:113090.9-113090.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end attribute \src "libresoc.v:113126.3-113162.6" process $proc$libresoc.v:113126$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] attribute \src "libresoc.v:113127.5-113127.29" switch \initial attribute \src "libresoc.v:113127.9-113127.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end attribute \src "libresoc.v:113163.3-113199.6" process $proc$libresoc.v:113163$4314 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] attribute \src "libresoc.v:113164.5-113164.29" switch \initial attribute \src "libresoc.v:113164.9-113164.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 case assign $1\dec31_dec_sub28_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end attribute \src "libresoc.v:113200.3-113236.6" process $proc$libresoc.v:113200$4315 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] attribute \src "libresoc.v:113201.5-113201.29" switch \initial attribute \src "libresoc.v:113201.9-113201.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 case assign $1\dec31_dec_sub28_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end attribute \src "libresoc.v:113237.3-113273.6" process $proc$libresoc.v:113237$4316 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] attribute \src "libresoc.v:113238.5-113238.29" switch \initial attribute \src "libresoc.v:113238.9-113238.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end attribute \src "libresoc.v:113274.3-113310.6" process $proc$libresoc.v:113274$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] attribute \src "libresoc.v:113275.5-113275.29" switch \initial attribute \src "libresoc.v:113275.9-113275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub28_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end attribute \src "libresoc.v:113311.3-113347.6" process $proc$libresoc.v:113311$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0] attribute \src "libresoc.v:113312.5-113312.29" switch \initial attribute \src "libresoc.v:113312.9-113312.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub28_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0] end attribute \src "libresoc.v:113348.3-113384.6" process $proc$libresoc.v:113348$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] attribute \src "libresoc.v:113349.5-113349.29" switch \initial attribute \src "libresoc.v:113349.9-113349.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end attribute \src "libresoc.v:113385.3-113421.6" process $proc$libresoc.v:113385$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] attribute \src "libresoc.v:113386.5-113386.29" switch \initial attribute \src "libresoc.v:113386.9-113386.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end attribute \src "libresoc.v:113422.3-113458.6" process $proc$libresoc.v:113422$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] attribute \src "libresoc.v:113423.5-113423.29" switch \initial attribute \src "libresoc.v:113423.9-113423.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end attribute \src "libresoc.v:113459.3-113495.6" process $proc$libresoc.v:113459$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] attribute \src "libresoc.v:113460.5-113460.29" switch \initial attribute \src "libresoc.v:113460.9-113460.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 case assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end attribute \src "libresoc.v:113496.3-113532.6" process $proc$libresoc.v:113496$4323 assign { } { } assign { } { } assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] attribute \src "libresoc.v:113497.5-113497.29" switch \initial attribute \src "libresoc.v:113497.9-113497.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_upd[1:0] 2'00 case assign $1\dec31_dec_sub28_upd[1:0] 2'00 end sync always update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end attribute \src "libresoc.v:113533.3-113569.6" process $proc$libresoc.v:113533$4324 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] attribute \src "libresoc.v:113534.5-113534.29" switch \initial attribute \src "libresoc.v:113534.9-113534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end attribute \src "libresoc.v:113570.3-113606.6" process $proc$libresoc.v:113570$4325 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] attribute \src "libresoc.v:113571.5-113571.29" switch \initial attribute \src "libresoc.v:113571.9-113571.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end attribute \src "libresoc.v:113607.3-113643.6" process $proc$libresoc.v:113607$4326 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] attribute \src "libresoc.v:113608.5-113608.29" switch \initial attribute \src "libresoc.v:113608.9-113608.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010001 case assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end attribute \src "libresoc.v:113644.3-113680.6" process $proc$libresoc.v:113644$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] attribute \src "libresoc.v:113645.5-113645.29" switch \initial attribute \src "libresoc.v:113645.9-113645.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end attribute \src "libresoc.v:113681.3-113717.6" process $proc$libresoc.v:113681$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] attribute \src "libresoc.v:113682.5-113682.29" switch \initial attribute \src "libresoc.v:113682.9-113682.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end attribute \src "libresoc.v:113718.3-113754.6" process $proc$libresoc.v:113718$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] attribute \src "libresoc.v:113719.5-113719.29" switch \initial attribute \src "libresoc.v:113719.9-113719.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end attribute \src "libresoc.v:113755.3-113791.6" process $proc$libresoc.v:113755$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] attribute \src "libresoc.v:113756.5-113756.29" switch \initial attribute \src "libresoc.v:113756.9-113756.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_br[0:0] 1'0 case assign $1\dec31_dec_sub28_br[0:0] 1'0 end sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end attribute \src "libresoc.v:113792.3-113828.6" process $proc$libresoc.v:113792$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] attribute \src "libresoc.v:113793.5-113793.29" switch \initial attribute \src "libresoc.v:113793.9-113793.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end attribute \src "libresoc.v:113829.3-113865.6" process $proc$libresoc.v:113829$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] attribute \src "libresoc.v:113830.5-113830.29" switch \initial attribute \src "libresoc.v:113830.9-113830.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end attribute \src "libresoc.v:113866.3-113902.6" process $proc$libresoc.v:113866$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] attribute \src "libresoc.v:113867.5-113867.29" switch \initial attribute \src "libresoc.v:113867.9-113867.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_form[4:0] 5'01000 case assign $1\dec31_dec_sub28_form[4:0] 5'00000 end sync always update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end attribute \src "libresoc.v:113903.3-113939.6" process $proc$libresoc.v:113903$4334 assign { } { } assign { } { } assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] attribute \src "libresoc.v:113904.5-113904.29" switch \initial attribute \src "libresoc.v:113904.9-113904.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end attribute \src "libresoc.v:113940.3-113976.6" process $proc$libresoc.v:113940$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] attribute \src "libresoc.v:113941.5-113941.29" switch \initial attribute \src "libresoc.v:113941.9-113941.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sgn[0:0] 1'0 case assign $1\dec31_dec_sub28_sgn[0:0] 1'0 end sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end attribute \src "libresoc.v:113977.3-114013.6" process $proc$libresoc.v:113977$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] attribute \src "libresoc.v:113978.5-113978.29" switch \initial attribute \src "libresoc.v:113978.9-113978.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_lk[0:0] 1'0 case assign $1\dec31_dec_sub28_lk[0:0] 1'0 end sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end attribute \src "libresoc.v:114014.3-114050.6" process $proc$libresoc.v:114014$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] attribute \src "libresoc.v:114015.5-114015.29" switch \initial attribute \src "libresoc.v:114015.9-114015.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end attribute \src "libresoc.v:114051.3-114087.6" process $proc$libresoc.v:114051$4338 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] attribute \src "libresoc.v:114052.5-114052.29" switch \initial attribute \src "libresoc.v:114052.9-114052.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end attribute \src "libresoc.v:114088.3-114124.6" process $proc$libresoc.v:114088$4339 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] attribute \src "libresoc.v:114089.5-114089.29" switch \initial attribute \src "libresoc.v:114089.9-114089.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 case assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end attribute \src "libresoc.v:114125.3-114161.6" process $proc$libresoc.v:114125$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] attribute \src "libresoc.v:114126.5-114126.29" switch \initial attribute \src "libresoc.v:114126.9-114126.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 case assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end attribute \src "libresoc.v:114162.3-114198.6" process $proc$libresoc.v:114162$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] attribute \src "libresoc.v:114163.5-114163.29" switch \initial attribute \src "libresoc.v:114163.9-114163.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end attribute \src "libresoc.v:114199.3-114235.6" process $proc$libresoc.v:114199$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] attribute \src "libresoc.v:114200.5-114200.29" switch \initial attribute \src "libresoc.v:114200.9-114200.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end attribute \src "libresoc.v:114236.3-114272.6" process $proc$libresoc.v:114236$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] attribute \src "libresoc.v:114237.5-114237.29" switch \initial attribute \src "libresoc.v:114237.9-114237.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01001 assign { } { } assign $1\dec31_dec_sub28_out_sel[2:0] 3'010 case assign $1\dec31_dec_sub28_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:114278.1-115057.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 attribute \src "libresoc.v:114978.3-114990.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] attribute \src "libresoc.v:114991.3-115003.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] attribute \src "libresoc.v:114822.3-114834.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] attribute \src "libresoc.v:114874.3-114886.6" wire $0\dec31_dec_sub4_br[0:0] attribute \src "libresoc.v:114640.3-114652.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] attribute \src "libresoc.v:114653.3-114665.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] attribute \src "libresoc.v:114809.3-114821.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] attribute \src "libresoc.v:114861.3-114873.6" wire $0\dec31_dec_sub4_cry_out[0:0] attribute \src "libresoc.v:114913.3-114925.6" wire width 5 $0\dec31_dec_sub4_form[4:0] attribute \src "libresoc.v:114627.3-114639.6" wire width 14 $0\dec31_dec_sub4_function_unit[13:0] attribute \src "libresoc.v:115004.3-115016.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] attribute \src "libresoc.v:115017.3-115029.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] attribute \src "libresoc.v:115030.3-115042.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] attribute \src "libresoc.v:114770.3-114782.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] attribute \src "libresoc.v:114835.3-114847.6" wire $0\dec31_dec_sub4_inv_a[0:0] attribute \src "libresoc.v:114848.3-114860.6" wire $0\dec31_dec_sub4_inv_out[0:0] attribute \src "libresoc.v:114926.3-114938.6" wire $0\dec31_dec_sub4_is_32b[0:0] attribute \src "libresoc.v:114757.3-114769.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] attribute \src "libresoc.v:114952.3-114964.6" wire $0\dec31_dec_sub4_lk[0:0] attribute \src "libresoc.v:115043.3-115055.6" wire width 3 $0\dec31_dec_sub4_out_sel[2:0] attribute \src "libresoc.v:114796.3-114808.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] attribute \src "libresoc.v:114900.3-114912.6" wire $0\dec31_dec_sub4_rsrv[0:0] attribute \src "libresoc.v:114965.3-114977.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] attribute \src "libresoc.v:114939.3-114951.6" wire $0\dec31_dec_sub4_sgn[0:0] attribute \src "libresoc.v:114887.3-114899.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] attribute \src "libresoc.v:114731.3-114743.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] attribute \src "libresoc.v:114744.3-114756.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] attribute \src "libresoc.v:114666.3-114678.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] attribute \src "libresoc.v:114679.3-114691.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] attribute \src "libresoc.v:114692.3-114704.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] attribute \src "libresoc.v:114718.3-114730.6" wire width 3 $0\dec31_dec_sub4_sv_out2[2:0] attribute \src "libresoc.v:114705.3-114717.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] attribute \src "libresoc.v:114783.3-114795.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] attribute \src "libresoc.v:114279.7-114279.20" wire $0\initial[0:0] attribute \src "libresoc.v:114978.3-114990.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] attribute \src "libresoc.v:114991.3-115003.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] attribute \src "libresoc.v:114822.3-114834.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] attribute \src "libresoc.v:114874.3-114886.6" wire $1\dec31_dec_sub4_br[0:0] attribute \src "libresoc.v:114640.3-114652.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] attribute \src "libresoc.v:114653.3-114665.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] attribute \src "libresoc.v:114809.3-114821.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] attribute \src "libresoc.v:114861.3-114873.6" wire $1\dec31_dec_sub4_cry_out[0:0] attribute \src "libresoc.v:114913.3-114925.6" wire width 5 $1\dec31_dec_sub4_form[4:0] attribute \src "libresoc.v:114627.3-114639.6" wire width 14 $1\dec31_dec_sub4_function_unit[13:0] attribute \src "libresoc.v:115004.3-115016.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] attribute \src "libresoc.v:115017.3-115029.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] attribute \src "libresoc.v:115030.3-115042.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] attribute \src "libresoc.v:114770.3-114782.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] attribute \src "libresoc.v:114835.3-114847.6" wire $1\dec31_dec_sub4_inv_a[0:0] attribute \src "libresoc.v:114848.3-114860.6" wire $1\dec31_dec_sub4_inv_out[0:0] attribute \src "libresoc.v:114926.3-114938.6" wire $1\dec31_dec_sub4_is_32b[0:0] attribute \src "libresoc.v:114757.3-114769.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] attribute \src "libresoc.v:114952.3-114964.6" wire $1\dec31_dec_sub4_lk[0:0] attribute \src "libresoc.v:115043.3-115055.6" wire width 3 $1\dec31_dec_sub4_out_sel[2:0] attribute \src "libresoc.v:114796.3-114808.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] attribute \src "libresoc.v:114900.3-114912.6" wire $1\dec31_dec_sub4_rsrv[0:0] attribute \src "libresoc.v:114965.3-114977.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] attribute \src "libresoc.v:114939.3-114951.6" wire $1\dec31_dec_sub4_sgn[0:0] attribute \src "libresoc.v:114887.3-114899.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] attribute \src "libresoc.v:114731.3-114743.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] attribute \src "libresoc.v:114744.3-114756.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] attribute \src "libresoc.v:114666.3-114678.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] attribute \src "libresoc.v:114679.3-114691.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] attribute \src "libresoc.v:114692.3-114704.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] attribute \src "libresoc.v:114718.3-114730.6" wire width 3 $1\dec31_dec_sub4_sv_out2[2:0] attribute \src "libresoc.v:114705.3-114717.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] attribute \src "libresoc.v:114783.3-114795.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub4_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub4_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub4_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub4_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub4_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub4_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub4_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub4_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub4_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub4_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub4_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub4_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub4_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub4_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub4_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub4_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub4_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub4_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub4_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub4_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub4_upd attribute \src "libresoc.v:114279.7-114279.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:114279.7-114279.20" process $proc$libresoc.v:114279$4378 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:114627.3-114639.6" process $proc$libresoc.v:114627$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] attribute \src "libresoc.v:114628.5-114628.29" switch \initial attribute \src "libresoc.v:114628.9-114628.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000010000000 case assign $1\dec31_dec_sub4_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] end attribute \src "libresoc.v:114640.3-114652.6" process $proc$libresoc.v:114640$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] attribute \src "libresoc.v:114641.5-114641.29" switch \initial attribute \src "libresoc.v:114641.9-114641.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end attribute \src "libresoc.v:114653.3-114665.6" process $proc$libresoc.v:114653$4347 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] attribute \src "libresoc.v:114654.5-114654.29" switch \initial attribute \src "libresoc.v:114654.9-114654.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end attribute \src "libresoc.v:114666.3-114678.6" process $proc$libresoc.v:114666$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] attribute \src "libresoc.v:114667.5-114667.29" switch \initial attribute \src "libresoc.v:114667.9-114667.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 case assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end attribute \src "libresoc.v:114679.3-114691.6" process $proc$libresoc.v:114679$4349 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] attribute \src "libresoc.v:114680.5-114680.29" switch \initial attribute \src "libresoc.v:114680.9-114680.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end attribute \src "libresoc.v:114692.3-114704.6" process $proc$libresoc.v:114692$4350 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] attribute \src "libresoc.v:114693.5-114693.29" switch \initial attribute \src "libresoc.v:114693.9-114693.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end attribute \src "libresoc.v:114705.3-114717.6" process $proc$libresoc.v:114705$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] attribute \src "libresoc.v:114706.5-114706.29" switch \initial attribute \src "libresoc.v:114706.9-114706.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 case assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end attribute \src "libresoc.v:114718.3-114730.6" process $proc$libresoc.v:114718$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0] attribute \src "libresoc.v:114719.5-114719.29" switch \initial attribute \src "libresoc.v:114719.9-114719.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub4_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0] end attribute \src "libresoc.v:114731.3-114743.6" process $proc$libresoc.v:114731$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] attribute \src "libresoc.v:114732.5-114732.29" switch \initial attribute \src "libresoc.v:114732.9-114732.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end attribute \src "libresoc.v:114744.3-114756.6" process $proc$libresoc.v:114744$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] attribute \src "libresoc.v:114745.5-114745.29" switch \initial attribute \src "libresoc.v:114745.9-114745.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 case assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end attribute \src "libresoc.v:114757.3-114769.6" process $proc$libresoc.v:114757$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] attribute \src "libresoc.v:114758.5-114758.29" switch \initial attribute \src "libresoc.v:114758.9-114758.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end attribute \src "libresoc.v:114770.3-114782.6" process $proc$libresoc.v:114770$4356 assign { } { } assign { } { } assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] attribute \src "libresoc.v:114771.5-114771.29" switch \initial attribute \src "libresoc.v:114771.9-114771.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 case assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end attribute \src "libresoc.v:114783.3-114795.6" process $proc$libresoc.v:114783$4357 assign { } { } assign { } { } assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] attribute \src "libresoc.v:114784.5-114784.29" switch \initial attribute \src "libresoc.v:114784.9-114784.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_upd[1:0] 2'00 case assign $1\dec31_dec_sub4_upd[1:0] 2'00 end sync always update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end attribute \src "libresoc.v:114796.3-114808.6" process $proc$libresoc.v:114796$4358 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] attribute \src "libresoc.v:114797.5-114797.29" switch \initial attribute \src "libresoc.v:114797.9-114797.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 case assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end attribute \src "libresoc.v:114809.3-114821.6" process $proc$libresoc.v:114809$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] attribute \src "libresoc.v:114810.5-114810.29" switch \initial attribute \src "libresoc.v:114810.9-114810.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end attribute \src "libresoc.v:114822.3-114834.6" process $proc$libresoc.v:114822$4360 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] attribute \src "libresoc.v:114823.5-114823.29" switch \initial attribute \src "libresoc.v:114823.9-114823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001111 case assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end attribute \src "libresoc.v:114835.3-114847.6" process $proc$libresoc.v:114835$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] attribute \src "libresoc.v:114836.5-114836.29" switch \initial attribute \src "libresoc.v:114836.9-114836.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end attribute \src "libresoc.v:114848.3-114860.6" process $proc$libresoc.v:114848$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] attribute \src "libresoc.v:114849.5-114849.29" switch \initial attribute \src "libresoc.v:114849.9-114849.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end attribute \src "libresoc.v:114861.3-114873.6" process $proc$libresoc.v:114861$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] attribute \src "libresoc.v:114862.5-114862.29" switch \initial attribute \src "libresoc.v:114862.9-114862.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end attribute \src "libresoc.v:114874.3-114886.6" process $proc$libresoc.v:114874$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] attribute \src "libresoc.v:114875.5-114875.29" switch \initial attribute \src "libresoc.v:114875.9-114875.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_br[0:0] 1'0 case assign $1\dec31_dec_sub4_br[0:0] 1'0 end sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end attribute \src "libresoc.v:114887.3-114899.6" process $proc$libresoc.v:114887$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] attribute \src "libresoc.v:114888.5-114888.29" switch \initial attribute \src "libresoc.v:114888.9-114888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end attribute \src "libresoc.v:114900.3-114912.6" process $proc$libresoc.v:114900$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] attribute \src "libresoc.v:114901.5-114901.29" switch \initial attribute \src "libresoc.v:114901.9-114901.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end attribute \src "libresoc.v:114913.3-114925.6" process $proc$libresoc.v:114913$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] attribute \src "libresoc.v:114914.5-114914.29" switch \initial attribute \src "libresoc.v:114914.9-114914.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_form[4:0] 5'01000 case assign $1\dec31_dec_sub4_form[4:0] 5'00000 end sync always update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end attribute \src "libresoc.v:114926.3-114938.6" process $proc$libresoc.v:114926$4368 assign { } { } assign { } { } assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] attribute \src "libresoc.v:114927.5-114927.29" switch \initial attribute \src "libresoc.v:114927.9-114927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 case assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end attribute \src "libresoc.v:114939.3-114951.6" process $proc$libresoc.v:114939$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] attribute \src "libresoc.v:114940.5-114940.29" switch \initial attribute \src "libresoc.v:114940.9-114940.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sgn[0:0] 1'0 case assign $1\dec31_dec_sub4_sgn[0:0] 1'0 end sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end attribute \src "libresoc.v:114952.3-114964.6" process $proc$libresoc.v:114952$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] attribute \src "libresoc.v:114953.5-114953.29" switch \initial attribute \src "libresoc.v:114953.9-114953.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_lk[0:0] 1'0 case assign $1\dec31_dec_sub4_lk[0:0] 1'0 end sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end attribute \src "libresoc.v:114965.3-114977.6" process $proc$libresoc.v:114965$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] attribute \src "libresoc.v:114966.5-114966.29" switch \initial attribute \src "libresoc.v:114966.9-114966.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 case assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end attribute \src "libresoc.v:114978.3-114990.6" process $proc$libresoc.v:114978$4372 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] attribute \src "libresoc.v:114979.5-114979.29" switch \initial attribute \src "libresoc.v:114979.9-114979.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 case assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end attribute \src "libresoc.v:114991.3-115003.6" process $proc$libresoc.v:114991$4373 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] attribute \src "libresoc.v:114992.5-114992.29" switch \initial attribute \src "libresoc.v:114992.9-114992.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 case assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end attribute \src "libresoc.v:115004.3-115016.6" process $proc$libresoc.v:115004$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] attribute \src "libresoc.v:115005.5-115005.29" switch \initial attribute \src "libresoc.v:115005.9-115005.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 case assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end attribute \src "libresoc.v:115017.3-115029.6" process $proc$libresoc.v:115017$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] attribute \src "libresoc.v:115018.5-115018.29" switch \initial attribute \src "libresoc.v:115018.9-115018.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end attribute \src "libresoc.v:115030.3-115042.6" process $proc$libresoc.v:115030$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] attribute \src "libresoc.v:115031.5-115031.29" switch \initial attribute \src "libresoc.v:115031.9-115031.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end attribute \src "libresoc.v:115043.3-115055.6" process $proc$libresoc.v:115043$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] attribute \src "libresoc.v:115044.5-115044.29" switch \initial attribute \src "libresoc.v:115044.9-115044.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 case assign $1\dec31_dec_sub4_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:115061.1-116830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 attribute \src "libresoc.v:116571.3-116613.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] attribute \src "libresoc.v:116614.3-116656.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] attribute \src "libresoc.v:116055.3-116097.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] attribute \src "libresoc.v:116227.3-116269.6" wire $0\dec31_dec_sub8_br[0:0] attribute \src "libresoc.v:115453.3-115495.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] attribute \src "libresoc.v:115496.3-115538.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] attribute \src "libresoc.v:116012.3-116054.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] attribute \src "libresoc.v:116184.3-116226.6" wire $0\dec31_dec_sub8_cry_out[0:0] attribute \src "libresoc.v:116356.3-116398.6" wire width 5 $0\dec31_dec_sub8_form[4:0] attribute \src "libresoc.v:115410.3-115452.6" wire width 14 $0\dec31_dec_sub8_function_unit[13:0] attribute \src "libresoc.v:116657.3-116699.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] attribute \src "libresoc.v:116700.3-116742.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] attribute \src "libresoc.v:116743.3-116785.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] attribute \src "libresoc.v:115883.3-115925.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] attribute \src "libresoc.v:116098.3-116140.6" wire $0\dec31_dec_sub8_inv_a[0:0] attribute \src "libresoc.v:116141.3-116183.6" wire $0\dec31_dec_sub8_inv_out[0:0] attribute \src "libresoc.v:116399.3-116441.6" wire $0\dec31_dec_sub8_is_32b[0:0] attribute \src "libresoc.v:115840.3-115882.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] attribute \src "libresoc.v:116485.3-116527.6" wire $0\dec31_dec_sub8_lk[0:0] attribute \src "libresoc.v:116786.3-116828.6" wire width 3 $0\dec31_dec_sub8_out_sel[2:0] attribute \src "libresoc.v:115969.3-116011.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] attribute \src "libresoc.v:116313.3-116355.6" wire $0\dec31_dec_sub8_rsrv[0:0] attribute \src "libresoc.v:116528.3-116570.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] attribute \src "libresoc.v:116442.3-116484.6" wire $0\dec31_dec_sub8_sgn[0:0] attribute \src "libresoc.v:116270.3-116312.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] attribute \src "libresoc.v:115754.3-115796.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] attribute \src "libresoc.v:115797.3-115839.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] attribute \src "libresoc.v:115539.3-115581.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] attribute \src "libresoc.v:115582.3-115624.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] attribute \src "libresoc.v:115625.3-115667.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] attribute \src "libresoc.v:115711.3-115753.6" wire width 3 $0\dec31_dec_sub8_sv_out2[2:0] attribute \src "libresoc.v:115668.3-115710.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] attribute \src "libresoc.v:115926.3-115968.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] attribute \src "libresoc.v:115062.7-115062.20" wire $0\initial[0:0] attribute \src "libresoc.v:116571.3-116613.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] attribute \src "libresoc.v:116614.3-116656.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] attribute \src "libresoc.v:116055.3-116097.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] attribute \src "libresoc.v:116227.3-116269.6" wire $1\dec31_dec_sub8_br[0:0] attribute \src "libresoc.v:115453.3-115495.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] attribute \src "libresoc.v:115496.3-115538.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] attribute \src "libresoc.v:116012.3-116054.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] attribute \src "libresoc.v:116184.3-116226.6" wire $1\dec31_dec_sub8_cry_out[0:0] attribute \src "libresoc.v:116356.3-116398.6" wire width 5 $1\dec31_dec_sub8_form[4:0] attribute \src "libresoc.v:115410.3-115452.6" wire width 14 $1\dec31_dec_sub8_function_unit[13:0] attribute \src "libresoc.v:116657.3-116699.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] attribute \src "libresoc.v:116700.3-116742.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] attribute \src "libresoc.v:116743.3-116785.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] attribute \src "libresoc.v:115883.3-115925.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] attribute \src "libresoc.v:116098.3-116140.6" wire $1\dec31_dec_sub8_inv_a[0:0] attribute \src "libresoc.v:116141.3-116183.6" wire $1\dec31_dec_sub8_inv_out[0:0] attribute \src "libresoc.v:116399.3-116441.6" wire $1\dec31_dec_sub8_is_32b[0:0] attribute \src "libresoc.v:115840.3-115882.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] attribute \src "libresoc.v:116485.3-116527.6" wire $1\dec31_dec_sub8_lk[0:0] attribute \src "libresoc.v:116786.3-116828.6" wire width 3 $1\dec31_dec_sub8_out_sel[2:0] attribute \src "libresoc.v:115969.3-116011.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] attribute \src "libresoc.v:116313.3-116355.6" wire $1\dec31_dec_sub8_rsrv[0:0] attribute \src "libresoc.v:116528.3-116570.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] attribute \src "libresoc.v:116442.3-116484.6" wire $1\dec31_dec_sub8_sgn[0:0] attribute \src "libresoc.v:116270.3-116312.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] attribute \src "libresoc.v:115754.3-115796.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] attribute \src "libresoc.v:115797.3-115839.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] attribute \src "libresoc.v:115539.3-115581.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] attribute \src "libresoc.v:115582.3-115624.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] attribute \src "libresoc.v:115625.3-115667.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] attribute \src "libresoc.v:115711.3-115753.6" wire width 3 $1\dec31_dec_sub8_sv_out2[2:0] attribute \src "libresoc.v:115668.3-115710.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] attribute \src "libresoc.v:115926.3-115968.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub8_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub8_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub8_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub8_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub8_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub8_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub8_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub8_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub8_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub8_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub8_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub8_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub8_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub8_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub8_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub8_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub8_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub8_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub8_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub8_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub8_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub8_upd attribute \src "libresoc.v:115062.7-115062.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:115062.7-115062.20" process $proc$libresoc.v:115062$4412 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:115410.3-115452.6" process $proc$libresoc.v:115410$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] attribute \src "libresoc.v:115411.5-115411.29" switch \initial attribute \src "libresoc.v:115411.9-115411.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000010 case assign $1\dec31_dec_sub8_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end attribute \src "libresoc.v:115453.3-115495.6" process $proc$libresoc.v:115453$4380 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] attribute \src "libresoc.v:115454.5-115454.29" switch \initial attribute \src "libresoc.v:115454.9-115454.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end attribute \src "libresoc.v:115496.3-115538.6" process $proc$libresoc.v:115496$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] attribute \src "libresoc.v:115497.5-115497.29" switch \initial attribute \src "libresoc.v:115497.9-115497.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end attribute \src "libresoc.v:115539.3-115581.6" process $proc$libresoc.v:115539$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] attribute \src "libresoc.v:115540.5-115540.29" switch \initial attribute \src "libresoc.v:115540.9-115540.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub8_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end attribute \src "libresoc.v:115582.3-115624.6" process $proc$libresoc.v:115582$4383 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] attribute \src "libresoc.v:115583.5-115583.29" switch \initial attribute \src "libresoc.v:115583.9-115583.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 case assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end attribute \src "libresoc.v:115625.3-115667.6" process $proc$libresoc.v:115625$4384 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] attribute \src "libresoc.v:115626.5-115626.29" switch \initial attribute \src "libresoc.v:115626.9-115626.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end attribute \src "libresoc.v:115668.3-115710.6" process $proc$libresoc.v:115668$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] attribute \src "libresoc.v:115669.5-115669.29" switch \initial attribute \src "libresoc.v:115669.9-115669.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub8_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end attribute \src "libresoc.v:115711.3-115753.6" process $proc$libresoc.v:115711$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0] attribute \src "libresoc.v:115712.5-115712.29" switch \initial attribute \src "libresoc.v:115712.9-115712.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub8_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0] end attribute \src "libresoc.v:115754.3-115796.6" process $proc$libresoc.v:115754$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] attribute \src "libresoc.v:115755.5-115755.29" switch \initial attribute \src "libresoc.v:115755.9-115755.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end attribute \src "libresoc.v:115797.3-115839.6" process $proc$libresoc.v:115797$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] attribute \src "libresoc.v:115798.5-115798.29" switch \initial attribute \src "libresoc.v:115798.9-115798.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end attribute \src "libresoc.v:115840.3-115882.6" process $proc$libresoc.v:115840$4389 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] attribute \src "libresoc.v:115841.5-115841.29" switch \initial attribute \src "libresoc.v:115841.9-115841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end attribute \src "libresoc.v:115883.3-115925.6" process $proc$libresoc.v:115883$4390 assign { } { } assign { } { } assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] attribute \src "libresoc.v:115884.5-115884.29" switch \initial attribute \src "libresoc.v:115884.9-115884.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 case assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end attribute \src "libresoc.v:115926.3-115968.6" process $proc$libresoc.v:115926$4391 assign { } { } assign { } { } assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] attribute \src "libresoc.v:115927.5-115927.29" switch \initial attribute \src "libresoc.v:115927.9-115927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_upd[1:0] 2'00 case assign $1\dec31_dec_sub8_upd[1:0] 2'00 end sync always update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end attribute \src "libresoc.v:115969.3-116011.6" process $proc$libresoc.v:115969$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] attribute \src "libresoc.v:115970.5-115970.29" switch \initial attribute \src "libresoc.v:115970.9-115970.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end attribute \src "libresoc.v:116012.3-116054.6" process $proc$libresoc.v:116012$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] attribute \src "libresoc.v:116013.5-116013.29" switch \initial attribute \src "libresoc.v:116013.9-116013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 case assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end attribute \src "libresoc.v:116055.3-116097.6" process $proc$libresoc.v:116055$4394 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] attribute \src "libresoc.v:116056.5-116056.29" switch \initial attribute \src "libresoc.v:116056.9-116056.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001001 case assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end attribute \src "libresoc.v:116098.3-116140.6" process $proc$libresoc.v:116098$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] attribute \src "libresoc.v:116099.5-116099.29" switch \initial attribute \src "libresoc.v:116099.9-116099.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 case assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end attribute \src "libresoc.v:116141.3-116183.6" process $proc$libresoc.v:116141$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] attribute \src "libresoc.v:116142.5-116142.29" switch \initial attribute \src "libresoc.v:116142.9-116142.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end attribute \src "libresoc.v:116184.3-116226.6" process $proc$libresoc.v:116184$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] attribute \src "libresoc.v:116185.5-116185.29" switch \initial attribute \src "libresoc.v:116185.9-116185.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 case assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end attribute \src "libresoc.v:116227.3-116269.6" process $proc$libresoc.v:116227$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] attribute \src "libresoc.v:116228.5-116228.29" switch \initial attribute \src "libresoc.v:116228.9-116228.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_br[0:0] 1'0 case assign $1\dec31_dec_sub8_br[0:0] 1'0 end sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end attribute \src "libresoc.v:116270.3-116312.6" process $proc$libresoc.v:116270$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] attribute \src "libresoc.v:116271.5-116271.29" switch \initial attribute \src "libresoc.v:116271.9-116271.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end attribute \src "libresoc.v:116313.3-116355.6" process $proc$libresoc.v:116313$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] attribute \src "libresoc.v:116314.5-116314.29" switch \initial attribute \src "libresoc.v:116314.9-116314.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end attribute \src "libresoc.v:116356.3-116398.6" process $proc$libresoc.v:116356$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] attribute \src "libresoc.v:116357.5-116357.29" switch \initial attribute \src "libresoc.v:116357.9-116357.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_form[4:0] 5'10001 case assign $1\dec31_dec_sub8_form[4:0] 5'00000 end sync always update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end attribute \src "libresoc.v:116399.3-116441.6" process $proc$libresoc.v:116399$4402 assign { } { } assign { } { } assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] attribute \src "libresoc.v:116400.5-116400.29" switch \initial attribute \src "libresoc.v:116400.9-116400.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end attribute \src "libresoc.v:116442.3-116484.6" process $proc$libresoc.v:116442$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] attribute \src "libresoc.v:116443.5-116443.29" switch \initial attribute \src "libresoc.v:116443.9-116443.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sgn[0:0] 1'0 case assign $1\dec31_dec_sub8_sgn[0:0] 1'0 end sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end attribute \src "libresoc.v:116485.3-116527.6" process $proc$libresoc.v:116485$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] attribute \src "libresoc.v:116486.5-116486.29" switch \initial attribute \src "libresoc.v:116486.9-116486.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_lk[0:0] 1'0 case assign $1\dec31_dec_sub8_lk[0:0] 1'0 end sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end attribute \src "libresoc.v:116528.3-116570.6" process $proc$libresoc.v:116528$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] attribute \src "libresoc.v:116529.5-116529.29" switch \initial attribute \src "libresoc.v:116529.9-116529.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end attribute \src "libresoc.v:116571.3-116613.6" process $proc$libresoc.v:116571$4406 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] attribute \src "libresoc.v:116572.5-116572.29" switch \initial attribute \src "libresoc.v:116572.9-116572.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end attribute \src "libresoc.v:116614.3-116656.6" process $proc$libresoc.v:116614$4407 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] attribute \src "libresoc.v:116615.5-116615.29" switch \initial attribute \src "libresoc.v:116615.9-116615.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 case assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end attribute \src "libresoc.v:116657.3-116699.6" process $proc$libresoc.v:116657$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] attribute \src "libresoc.v:116658.5-116658.29" switch \initial attribute \src "libresoc.v:116658.9-116658.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 case assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end attribute \src "libresoc.v:116700.3-116742.6" process $proc$libresoc.v:116700$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] attribute \src "libresoc.v:116701.5-116701.29" switch \initial attribute \src "libresoc.v:116701.9-116701.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 case assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end attribute \src "libresoc.v:116743.3-116785.6" process $proc$libresoc.v:116743$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] attribute \src "libresoc.v:116744.5-116744.29" switch \initial attribute \src "libresoc.v:116744.9-116744.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end attribute \src "libresoc.v:116786.3-116828.6" process $proc$libresoc.v:116786$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] attribute \src "libresoc.v:116787.5-116787.29" switch \initial attribute \src "libresoc.v:116787.9-116787.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10011 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10001 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00100 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10100 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10110 assign { } { } assign $1\dec31_dec_sub8_out_sel[2:0] 3'001 case assign $1\dec31_dec_sub8_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:116834.1-118999.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 attribute \src "libresoc.v:118668.3-118722.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] attribute \src "libresoc.v:118723.3-118777.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] attribute \src "libresoc.v:118008.3-118062.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] attribute \src "libresoc.v:118228.3-118282.6" wire $0\dec31_dec_sub9_br[0:0] attribute \src "libresoc.v:117238.3-117292.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:117293.3-117347.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:117953.3-118007.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] attribute \src "libresoc.v:118173.3-118227.6" wire $0\dec31_dec_sub9_cry_out[0:0] attribute \src "libresoc.v:118393.3-118447.6" wire width 5 $0\dec31_dec_sub9_form[4:0] attribute \src "libresoc.v:117183.3-117237.6" wire width 14 $0\dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:118778.3-118832.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] attribute \src "libresoc.v:118833.3-118887.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:118888.3-118942.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] attribute \src "libresoc.v:117788.3-117842.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:118063.3-118117.6" wire $0\dec31_dec_sub9_inv_a[0:0] attribute \src "libresoc.v:118118.3-118172.6" wire $0\dec31_dec_sub9_inv_out[0:0] attribute \src "libresoc.v:118448.3-118502.6" wire $0\dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:117733.3-117787.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] attribute \src "libresoc.v:118558.3-118612.6" wire $0\dec31_dec_sub9_lk[0:0] attribute \src "libresoc.v:118943.3-118997.6" wire width 3 $0\dec31_dec_sub9_out_sel[2:0] attribute \src "libresoc.v:117898.3-117952.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:118338.3-118392.6" wire $0\dec31_dec_sub9_rsrv[0:0] attribute \src "libresoc.v:118613.3-118667.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] attribute \src "libresoc.v:118503.3-118557.6" wire $0\dec31_dec_sub9_sgn[0:0] attribute \src "libresoc.v:118283.3-118337.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] attribute \src "libresoc.v:117623.3-117677.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] attribute \src "libresoc.v:117678.3-117732.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] attribute \src "libresoc.v:117348.3-117402.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] attribute \src "libresoc.v:117403.3-117457.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] attribute \src "libresoc.v:117458.3-117512.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] attribute \src "libresoc.v:117568.3-117622.6" wire width 3 $0\dec31_dec_sub9_sv_out2[2:0] attribute \src "libresoc.v:117513.3-117567.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] attribute \src "libresoc.v:117843.3-117897.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] attribute \src "libresoc.v:116835.7-116835.20" wire $0\initial[0:0] attribute \src "libresoc.v:118668.3-118722.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] attribute \src "libresoc.v:118723.3-118777.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] attribute \src "libresoc.v:118008.3-118062.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] attribute \src "libresoc.v:118228.3-118282.6" wire $1\dec31_dec_sub9_br[0:0] attribute \src "libresoc.v:117238.3-117292.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:117293.3-117347.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:117953.3-118007.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] attribute \src "libresoc.v:118173.3-118227.6" wire $1\dec31_dec_sub9_cry_out[0:0] attribute \src "libresoc.v:118393.3-118447.6" wire width 5 $1\dec31_dec_sub9_form[4:0] attribute \src "libresoc.v:117183.3-117237.6" wire width 14 $1\dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:118778.3-118832.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] attribute \src "libresoc.v:118833.3-118887.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:118888.3-118942.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] attribute \src "libresoc.v:117788.3-117842.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:118063.3-118117.6" wire $1\dec31_dec_sub9_inv_a[0:0] attribute \src "libresoc.v:118118.3-118172.6" wire $1\dec31_dec_sub9_inv_out[0:0] attribute \src "libresoc.v:118448.3-118502.6" wire $1\dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:117733.3-117787.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] attribute \src "libresoc.v:118558.3-118612.6" wire $1\dec31_dec_sub9_lk[0:0] attribute \src "libresoc.v:118943.3-118997.6" wire width 3 $1\dec31_dec_sub9_out_sel[2:0] attribute \src "libresoc.v:117898.3-117952.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:118338.3-118392.6" wire $1\dec31_dec_sub9_rsrv[0:0] attribute \src "libresoc.v:118613.3-118667.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] attribute \src "libresoc.v:118503.3-118557.6" wire $1\dec31_dec_sub9_sgn[0:0] attribute \src "libresoc.v:118283.3-118337.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] attribute \src "libresoc.v:117623.3-117677.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] attribute \src "libresoc.v:117678.3-117732.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] attribute \src "libresoc.v:117348.3-117402.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] attribute \src "libresoc.v:117403.3-117457.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] attribute \src "libresoc.v:117458.3-117512.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] attribute \src "libresoc.v:117568.3-117622.6" wire width 3 $1\dec31_dec_sub9_sv_out2[2:0] attribute \src "libresoc.v:117513.3-117567.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] attribute \src "libresoc.v:117843.3-117897.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec31_dec_sub9_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec31_dec_sub9_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec31_dec_sub9_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec31_dec_sub9_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec31_dec_sub9_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec31_dec_sub9_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec31_dec_sub9_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec31_dec_sub9_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec31_dec_sub9_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec31_dec_sub9_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec31_dec_sub9_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec31_dec_sub9_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec31_dec_sub9_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec31_dec_sub9_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec31_dec_sub9_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec31_dec_sub9_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec31_dec_sub9_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec31_dec_sub9_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec31_dec_sub9_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec31_dec_sub9_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub9_upd attribute \src "libresoc.v:116835.7-116835.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch attribute \src "libresoc.v:116835.7-116835.20" process $proc$libresoc.v:116835$4446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:117183.3-117237.6" process $proc$libresoc.v:117183$4413 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] attribute \src "libresoc.v:117184.5-117184.29" switch \initial attribute \src "libresoc.v:117184.9-117184.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00001000000000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000100000000 case assign $1\dec31_dec_sub9_function_unit[13:0] 14'00000000000000 end sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end attribute \src "libresoc.v:117238.3-117292.6" process $proc$libresoc.v:117238$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] attribute \src "libresoc.v:117239.5-117239.29" switch \initial attribute \src "libresoc.v:117239.9-117239.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end attribute \src "libresoc.v:117293.3-117347.6" process $proc$libresoc.v:117293$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] attribute \src "libresoc.v:117294.5-117294.29" switch \initial attribute \src "libresoc.v:117294.9-117294.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end attribute \src "libresoc.v:117348.3-117402.6" process $proc$libresoc.v:117348$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] attribute \src "libresoc.v:117349.5-117349.29" switch \initial attribute \src "libresoc.v:117349.9-117349.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 case assign $1\dec31_dec_sub9_sv_in1[2:0] 3'000 end sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end attribute \src "libresoc.v:117403.3-117457.6" process $proc$libresoc.v:117403$4417 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] attribute \src "libresoc.v:117404.5-117404.29" switch \initial attribute \src "libresoc.v:117404.9-117404.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 case assign $1\dec31_dec_sub9_sv_in2[2:0] 3'000 end sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end attribute \src "libresoc.v:117458.3-117512.6" process $proc$libresoc.v:117458$4418 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] attribute \src "libresoc.v:117459.5-117459.29" switch \initial attribute \src "libresoc.v:117459.9-117459.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 case assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 end sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end attribute \src "libresoc.v:117513.3-117567.6" process $proc$libresoc.v:117513$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] attribute \src "libresoc.v:117514.5-117514.29" switch \initial attribute \src "libresoc.v:117514.9-117514.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 case assign $1\dec31_dec_sub9_sv_out[2:0] 3'000 end sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end attribute \src "libresoc.v:117568.3-117622.6" process $proc$libresoc.v:117568$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0] attribute \src "libresoc.v:117569.5-117569.29" switch \initial attribute \src "libresoc.v:117569.9-117569.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 case assign $1\dec31_dec_sub9_sv_out2[2:0] 3'000 end sync always update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0] end attribute \src "libresoc.v:117623.3-117677.6" process $proc$libresoc.v:117623$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] attribute \src "libresoc.v:117624.5-117624.29" switch \initial attribute \src "libresoc.v:117624.9-117624.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 case assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 end sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end attribute \src "libresoc.v:117678.3-117732.6" process $proc$libresoc.v:117678$4422 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] attribute \src "libresoc.v:117679.5-117679.29" switch \initial attribute \src "libresoc.v:117679.9-117679.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 case assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 end sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end attribute \src "libresoc.v:117733.3-117787.6" process $proc$libresoc.v:117733$4423 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] attribute \src "libresoc.v:117734.5-117734.29" switch \initial attribute \src "libresoc.v:117734.9-117734.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 case assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 end sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end attribute \src "libresoc.v:117788.3-117842.6" process $proc$libresoc.v:117788$4424 assign { } { } assign { } { } assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] attribute \src "libresoc.v:117789.5-117789.29" switch \initial attribute \src "libresoc.v:117789.9-117789.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 case assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end attribute \src "libresoc.v:117843.3-117897.6" process $proc$libresoc.v:117843$4425 assign { } { } assign { } { } assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] attribute \src "libresoc.v:117844.5-117844.29" switch \initial attribute \src "libresoc.v:117844.9-117844.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_upd[1:0] 2'00 case assign $1\dec31_dec_sub9_upd[1:0] 2'00 end sync always update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end attribute \src "libresoc.v:117898.3-117952.6" process $proc$libresoc.v:117898$4426 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] attribute \src "libresoc.v:117899.5-117899.29" switch \initial attribute \src "libresoc.v:117899.9-117899.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 case assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 end sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end attribute \src "libresoc.v:117953.3-118007.6" process $proc$libresoc.v:117953$4427 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] attribute \src "libresoc.v:117954.5-117954.29" switch \initial attribute \src "libresoc.v:117954.9-117954.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 case assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 end sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end attribute \src "libresoc.v:118008.3-118062.6" process $proc$libresoc.v:118008$4428 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] attribute \src "libresoc.v:118009.5-118009.29" switch \initial attribute \src "libresoc.v:118009.9-118009.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 case assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 end sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end attribute \src "libresoc.v:118063.3-118117.6" process $proc$libresoc.v:118063$4429 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] attribute \src "libresoc.v:118064.5-118064.29" switch \initial attribute \src "libresoc.v:118064.9-118064.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 case assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 end sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end attribute \src "libresoc.v:118118.3-118172.6" process $proc$libresoc.v:118118$4430 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] attribute \src "libresoc.v:118119.5-118119.29" switch \initial attribute \src "libresoc.v:118119.9-118119.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 case assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 end sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end attribute \src "libresoc.v:118173.3-118227.6" process $proc$libresoc.v:118173$4431 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] attribute \src "libresoc.v:118174.5-118174.29" switch \initial attribute \src "libresoc.v:118174.9-118174.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 case assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 end sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end attribute \src "libresoc.v:118228.3-118282.6" process $proc$libresoc.v:118228$4432 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] attribute \src "libresoc.v:118229.5-118229.29" switch \initial attribute \src "libresoc.v:118229.9-118229.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_br[0:0] 1'0 case assign $1\dec31_dec_sub9_br[0:0] 1'0 end sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end attribute \src "libresoc.v:118283.3-118337.6" process $proc$libresoc.v:118283$4433 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] attribute \src "libresoc.v:118284.5-118284.29" switch \initial attribute \src "libresoc.v:118284.9-118284.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 case assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 end sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end attribute \src "libresoc.v:118338.3-118392.6" process $proc$libresoc.v:118338$4434 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] attribute \src "libresoc.v:118339.5-118339.29" switch \initial attribute \src "libresoc.v:118339.9-118339.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 case assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 end sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end attribute \src "libresoc.v:118393.3-118447.6" process $proc$libresoc.v:118393$4435 assign { } { } assign { } { } assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] attribute \src "libresoc.v:118394.5-118394.29" switch \initial attribute \src "libresoc.v:118394.9-118394.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_form[4:0] 5'10001 case assign $1\dec31_dec_sub9_form[4:0] 5'00000 end sync always update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end attribute \src "libresoc.v:118448.3-118502.6" process $proc$libresoc.v:118448$4436 assign { } { } assign { } { } assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] attribute \src "libresoc.v:118449.5-118449.29" switch \initial attribute \src "libresoc.v:118449.9-118449.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 case assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 end sync always update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end attribute \src "libresoc.v:118503.3-118557.6" process $proc$libresoc.v:118503$4437 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] attribute \src "libresoc.v:118504.5-118504.29" switch \initial attribute \src "libresoc.v:118504.9-118504.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sgn[0:0] 1'1 case assign $1\dec31_dec_sub9_sgn[0:0] 1'0 end sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end attribute \src "libresoc.v:118558.3-118612.6" process $proc$libresoc.v:118558$4438 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] attribute \src "libresoc.v:118559.5-118559.29" switch \initial attribute \src "libresoc.v:118559.9-118559.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_lk[0:0] 1'0 case assign $1\dec31_dec_sub9_lk[0:0] 1'0 end sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end attribute \src "libresoc.v:118613.3-118667.6" process $proc$libresoc.v:118613$4439 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] attribute \src "libresoc.v:118614.5-118614.29" switch \initial attribute \src "libresoc.v:118614.9-118614.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 case assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 end sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end attribute \src "libresoc.v:118668.3-118722.6" process $proc$libresoc.v:118668$4440 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] attribute \src "libresoc.v:118669.5-118669.29" switch \initial attribute \src "libresoc.v:118669.9-118669.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 case assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'00 end sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end attribute \src "libresoc.v:118723.3-118777.6" process $proc$libresoc.v:118723$4441 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] attribute \src "libresoc.v:118724.5-118724.29" switch \initial attribute \src "libresoc.v:118724.9-118724.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 case assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'00 end sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end attribute \src "libresoc.v:118778.3-118832.6" process $proc$libresoc.v:118778$4442 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] attribute \src "libresoc.v:118779.5-118779.29" switch \initial attribute \src "libresoc.v:118779.9-118779.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 case assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 end sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end attribute \src "libresoc.v:118833.3-118887.6" process $proc$libresoc.v:118833$4443 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] attribute \src "libresoc.v:118834.5-118834.29" switch \initial attribute \src "libresoc.v:118834.9-118834.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 case assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 end sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end attribute \src "libresoc.v:118888.3-118942.6" process $proc$libresoc.v:118888$4444 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] attribute \src "libresoc.v:118889.5-118889.29" switch \initial attribute \src "libresoc.v:118889.9-118889.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 case assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 end sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end attribute \src "libresoc.v:118943.3-118997.6" process $proc$libresoc.v:118943$4445 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] attribute \src "libresoc.v:118944.5-118944.29" switch \initial attribute \src "libresoc.v:118944.9-118944.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11100 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01101 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11101 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01110 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11110 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01111 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11111 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'01000 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00010 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10010 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 5'10111 assign { } { } assign $1\dec31_dec_sub9_out_sel[2:0] 3'001 case assign $1\dec31_dec_sub9_out_sel[2:0] 3'000 end sync always update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[2:0] end connect \opcode_switch \opcode_in [10:6] end attribute \src "libresoc.v:119003.1-119881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 attribute \src "libresoc.v:119784.3-119799.6" wire width 2 $0\dec58_SV_Etype[1:0] attribute \src "libresoc.v:119800.3-119815.6" wire width 2 $0\dec58_SV_Ptype[1:0] attribute \src "libresoc.v:119592.3-119607.6" wire width 8 $0\dec58_asmcode[7:0] attribute \src "libresoc.v:119656.3-119671.6" wire $0\dec58_br[0:0] attribute \src "libresoc.v:119368.3-119383.6" wire width 3 $0\dec58_cr_in[2:0] attribute \src "libresoc.v:119384.3-119399.6" wire width 3 $0\dec58_cr_out[2:0] attribute \src "libresoc.v:119576.3-119591.6" wire width 2 $0\dec58_cry_in[1:0] attribute \src "libresoc.v:119640.3-119655.6" wire $0\dec58_cry_out[0:0] attribute \src "libresoc.v:119704.3-119719.6" wire width 5 $0\dec58_form[4:0] attribute \src "libresoc.v:119352.3-119367.6" wire width 14 $0\dec58_function_unit[13:0] attribute \src "libresoc.v:119816.3-119831.6" wire width 3 $0\dec58_in1_sel[2:0] attribute \src "libresoc.v:119832.3-119847.6" wire width 4 $0\dec58_in2_sel[3:0] attribute \src "libresoc.v:119848.3-119863.6" wire width 2 $0\dec58_in3_sel[1:0] attribute \src "libresoc.v:119528.3-119543.6" wire width 7 $0\dec58_internal_op[6:0] attribute \src "libresoc.v:119608.3-119623.6" wire $0\dec58_inv_a[0:0] attribute \src "libresoc.v:119624.3-119639.6" wire $0\dec58_inv_out[0:0] attribute \src "libresoc.v:119720.3-119735.6" wire $0\dec58_is_32b[0:0] attribute \src "libresoc.v:119512.3-119527.6" wire width 4 $0\dec58_ldst_len[3:0] attribute \src "libresoc.v:119752.3-119767.6" wire $0\dec58_lk[0:0] attribute \src "libresoc.v:119864.3-119879.6" wire width 3 $0\dec58_out_sel[2:0] attribute \src "libresoc.v:119560.3-119575.6" wire width 2 $0\dec58_rc_sel[1:0] attribute \src "libresoc.v:119688.3-119703.6" wire $0\dec58_rsrv[0:0] attribute \src "libresoc.v:119768.3-119783.6" wire $0\dec58_sgl_pipe[0:0] attribute \src "libresoc.v:119736.3-119751.6" wire $0\dec58_sgn[0:0] attribute \src "libresoc.v:119672.3-119687.6" wire $0\dec58_sgn_ext[0:0] attribute \src "libresoc.v:119480.3-119495.6" wire width 3 $0\dec58_sv_cr_in[2:0] attribute \src "libresoc.v:119496.3-119511.6" wire width 3 $0\dec58_sv_cr_out[2:0] attribute \src "libresoc.v:119400.3-119415.6" wire width 3 $0\dec58_sv_in1[2:0] attribute \src "libresoc.v:119416.3-119431.6" wire width 3 $0\dec58_sv_in2[2:0] attribute \src "libresoc.v:119432.3-119447.6" wire width 3 $0\dec58_sv_in3[2:0] attribute \src "libresoc.v:119464.3-119479.6" wire width 3 $0\dec58_sv_out2[2:0] attribute \src "libresoc.v:119448.3-119463.6" wire width 3 $0\dec58_sv_out[2:0] attribute \src "libresoc.v:119544.3-119559.6" wire width 2 $0\dec58_upd[1:0] attribute \src "libresoc.v:119004.7-119004.20" wire $0\initial[0:0] attribute \src "libresoc.v:119784.3-119799.6" wire width 2 $1\dec58_SV_Etype[1:0] attribute \src "libresoc.v:119800.3-119815.6" wire width 2 $1\dec58_SV_Ptype[1:0] attribute \src "libresoc.v:119592.3-119607.6" wire width 8 $1\dec58_asmcode[7:0] attribute \src "libresoc.v:119656.3-119671.6" wire $1\dec58_br[0:0] attribute \src "libresoc.v:119368.3-119383.6" wire width 3 $1\dec58_cr_in[2:0] attribute \src "libresoc.v:119384.3-119399.6" wire width 3 $1\dec58_cr_out[2:0] attribute \src "libresoc.v:119576.3-119591.6" wire width 2 $1\dec58_cry_in[1:0] attribute \src "libresoc.v:119640.3-119655.6" wire $1\dec58_cry_out[0:0] attribute \src "libresoc.v:119704.3-119719.6" wire width 5 $1\dec58_form[4:0] attribute \src "libresoc.v:119352.3-119367.6" wire width 14 $1\dec58_function_unit[13:0] attribute \src "libresoc.v:119816.3-119831.6" wire width 3 $1\dec58_in1_sel[2:0] attribute \src "libresoc.v:119832.3-119847.6" wire width 4 $1\dec58_in2_sel[3:0] attribute \src "libresoc.v:119848.3-119863.6" wire width 2 $1\dec58_in3_sel[1:0] attribute \src "libresoc.v:119528.3-119543.6" wire width 7 $1\dec58_internal_op[6:0] attribute \src "libresoc.v:119608.3-119623.6" wire $1\dec58_inv_a[0:0] attribute \src "libresoc.v:119624.3-119639.6" wire $1\dec58_inv_out[0:0] attribute \src "libresoc.v:119720.3-119735.6" wire $1\dec58_is_32b[0:0] attribute \src "libresoc.v:119512.3-119527.6" wire width 4 $1\dec58_ldst_len[3:0] attribute \src "libresoc.v:119752.3-119767.6" wire $1\dec58_lk[0:0] attribute \src "libresoc.v:119864.3-119879.6" wire width 3 $1\dec58_out_sel[2:0] attribute \src "libresoc.v:119560.3-119575.6" wire width 2 $1\dec58_rc_sel[1:0] attribute \src "libresoc.v:119688.3-119703.6" wire $1\dec58_rsrv[0:0] attribute \src "libresoc.v:119768.3-119783.6" wire $1\dec58_sgl_pipe[0:0] attribute \src "libresoc.v:119736.3-119751.6" wire $1\dec58_sgn[0:0] attribute \src "libresoc.v:119672.3-119687.6" wire $1\dec58_sgn_ext[0:0] attribute \src "libresoc.v:119480.3-119495.6" wire width 3 $1\dec58_sv_cr_in[2:0] attribute \src "libresoc.v:119496.3-119511.6" wire width 3 $1\dec58_sv_cr_out[2:0] attribute \src "libresoc.v:119400.3-119415.6" wire width 3 $1\dec58_sv_in1[2:0] attribute \src "libresoc.v:119416.3-119431.6" wire width 3 $1\dec58_sv_in2[2:0] attribute \src "libresoc.v:119432.3-119447.6" wire width 3 $1\dec58_sv_in3[2:0] attribute \src "libresoc.v:119464.3-119479.6" wire width 3 $1\dec58_sv_out2[2:0] attribute \src "libresoc.v:119448.3-119463.6" wire width 3 $1\dec58_sv_out[2:0] attribute \src "libresoc.v:119544.3-119559.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec58_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec58_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec58_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec58_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec58_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec58_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec58_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec58_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec58_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec58_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec58_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec58_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec58_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec58_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec58_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec58_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec58_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec58_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec58_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec58_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec58_upd attribute \src "libresoc.v:119004.7-119004.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:119004.7-119004.20" process $proc$libresoc.v:119004$4480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:119352.3-119367.6" process $proc$libresoc.v:119352$4447 assign { } { } assign { } { } assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] attribute \src "libresoc.v:119353.5-119353.29" switch \initial attribute \src "libresoc.v:119353.9-119353.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_function_unit[13:0] 14'00000000000100 case assign $1\dec58_function_unit[13:0] 14'00000000000000 end sync always update \dec58_function_unit $0\dec58_function_unit[13:0] end attribute \src "libresoc.v:119368.3-119383.6" process $proc$libresoc.v:119368$4448 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] attribute \src "libresoc.v:119369.5-119369.29" switch \initial attribute \src "libresoc.v:119369.9-119369.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_cr_in[2:0] 3'000 case assign $1\dec58_cr_in[2:0] 3'000 end sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end attribute \src "libresoc.v:119384.3-119399.6" process $proc$libresoc.v:119384$4449 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] attribute \src "libresoc.v:119385.5-119385.29" switch \initial attribute \src "libresoc.v:119385.9-119385.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_cr_out[2:0] 3'000 case assign $1\dec58_cr_out[2:0] 3'000 end sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end attribute \src "libresoc.v:119400.3-119415.6" process $proc$libresoc.v:119400$4450 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] attribute \src "libresoc.v:119401.5-119401.29" switch \initial attribute \src "libresoc.v:119401.9-119401.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sv_in1[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sv_in1[2:0] 3'010 case assign $1\dec58_sv_in1[2:0] 3'000 end sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end attribute \src "libresoc.v:119416.3-119431.6" process $proc$libresoc.v:119416$4451 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] attribute \src "libresoc.v:119417.5-119417.29" switch \initial attribute \src "libresoc.v:119417.9-119417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sv_in2[2:0] 3'000 case assign $1\dec58_sv_in2[2:0] 3'000 end sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end attribute \src "libresoc.v:119432.3-119447.6" process $proc$libresoc.v:119432$4452 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] attribute \src "libresoc.v:119433.5-119433.29" switch \initial attribute \src "libresoc.v:119433.9-119433.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sv_in3[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sv_in3[2:0] 3'000 case assign $1\dec58_sv_in3[2:0] 3'000 end sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end attribute \src "libresoc.v:119448.3-119463.6" process $proc$libresoc.v:119448$4453 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] attribute \src "libresoc.v:119449.5-119449.29" switch \initial attribute \src "libresoc.v:119449.9-119449.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sv_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sv_out[2:0] 3'001 case assign $1\dec58_sv_out[2:0] 3'000 end sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end attribute \src "libresoc.v:119464.3-119479.6" process $proc$libresoc.v:119464$4454 assign { } { } assign { } { } assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0] attribute \src "libresoc.v:119465.5-119465.29" switch \initial attribute \src "libresoc.v:119465.9-119465.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sv_out2[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sv_out2[2:0] 3'000 case assign $1\dec58_sv_out2[2:0] 3'000 end sync always update \dec58_sv_out2 $0\dec58_sv_out2[2:0] end attribute \src "libresoc.v:119480.3-119495.6" process $proc$libresoc.v:119480$4455 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] attribute \src "libresoc.v:119481.5-119481.29" switch \initial attribute \src "libresoc.v:119481.9-119481.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sv_cr_in[2:0] 3'000 case assign $1\dec58_sv_cr_in[2:0] 3'000 end sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end attribute \src "libresoc.v:119496.3-119511.6" process $proc$libresoc.v:119496$4456 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] attribute \src "libresoc.v:119497.5-119497.29" switch \initial attribute \src "libresoc.v:119497.9-119497.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sv_cr_out[2:0] 3'000 case assign $1\dec58_sv_cr_out[2:0] 3'000 end sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end attribute \src "libresoc.v:119512.3-119527.6" process $proc$libresoc.v:119512$4457 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] attribute \src "libresoc.v:119513.5-119513.29" switch \initial attribute \src "libresoc.v:119513.9-119513.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_ldst_len[3:0] 4'0100 case assign $1\dec58_ldst_len[3:0] 4'0000 end sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end attribute \src "libresoc.v:119528.3-119543.6" process $proc$libresoc.v:119528$4458 assign { } { } assign { } { } assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] attribute \src "libresoc.v:119529.5-119529.29" switch \initial attribute \src "libresoc.v:119529.9-119529.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_internal_op[6:0] 7'0100101 case assign $1\dec58_internal_op[6:0] 7'0000000 end sync always update \dec58_internal_op $0\dec58_internal_op[6:0] end attribute \src "libresoc.v:119544.3-119559.6" process $proc$libresoc.v:119544$4459 assign { } { } assign { } { } assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] attribute \src "libresoc.v:119545.5-119545.29" switch \initial attribute \src "libresoc.v:119545.9-119545.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_upd[1:0] 2'00 case assign $1\dec58_upd[1:0] 2'00 end sync always update \dec58_upd $0\dec58_upd[1:0] end attribute \src "libresoc.v:119560.3-119575.6" process $proc$libresoc.v:119560$4460 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] attribute \src "libresoc.v:119561.5-119561.29" switch \initial attribute \src "libresoc.v:119561.9-119561.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_rc_sel[1:0] 2'00 case assign $1\dec58_rc_sel[1:0] 2'00 end sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end attribute \src "libresoc.v:119576.3-119591.6" process $proc$libresoc.v:119576$4461 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] attribute \src "libresoc.v:119577.5-119577.29" switch \initial attribute \src "libresoc.v:119577.9-119577.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_cry_in[1:0] 2'00 case assign $1\dec58_cry_in[1:0] 2'00 end sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end attribute \src "libresoc.v:119592.3-119607.6" process $proc$libresoc.v:119592$4462 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] attribute \src "libresoc.v:119593.5-119593.29" switch \initial attribute \src "libresoc.v:119593.9-119593.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_asmcode[7:0] 8'01010010 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_asmcode[7:0] 8'01010101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_asmcode[7:0] 8'01100010 case assign $1\dec58_asmcode[7:0] 8'00000000 end sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end attribute \src "libresoc.v:119608.3-119623.6" process $proc$libresoc.v:119608$4463 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] attribute \src "libresoc.v:119609.5-119609.29" switch \initial attribute \src "libresoc.v:119609.9-119609.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_inv_a[0:0] 1'0 case assign $1\dec58_inv_a[0:0] 1'0 end sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end attribute \src "libresoc.v:119624.3-119639.6" process $proc$libresoc.v:119624$4464 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] attribute \src "libresoc.v:119625.5-119625.29" switch \initial attribute \src "libresoc.v:119625.9-119625.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_inv_out[0:0] 1'0 case assign $1\dec58_inv_out[0:0] 1'0 end sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end attribute \src "libresoc.v:119640.3-119655.6" process $proc$libresoc.v:119640$4465 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] attribute \src "libresoc.v:119641.5-119641.29" switch \initial attribute \src "libresoc.v:119641.9-119641.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_cry_out[0:0] 1'0 case assign $1\dec58_cry_out[0:0] 1'0 end sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end attribute \src "libresoc.v:119656.3-119671.6" process $proc$libresoc.v:119656$4466 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] attribute \src "libresoc.v:119657.5-119657.29" switch \initial attribute \src "libresoc.v:119657.9-119657.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_br[0:0] 1'0 case assign $1\dec58_br[0:0] 1'0 end sync always update \dec58_br $0\dec58_br[0:0] end attribute \src "libresoc.v:119672.3-119687.6" process $proc$libresoc.v:119672$4467 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] attribute \src "libresoc.v:119673.5-119673.29" switch \initial attribute \src "libresoc.v:119673.9-119673.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sgn_ext[0:0] 1'1 case assign $1\dec58_sgn_ext[0:0] 1'0 end sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end attribute \src "libresoc.v:119688.3-119703.6" process $proc$libresoc.v:119688$4468 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] attribute \src "libresoc.v:119689.5-119689.29" switch \initial attribute \src "libresoc.v:119689.9-119689.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_rsrv[0:0] 1'0 case assign $1\dec58_rsrv[0:0] 1'0 end sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end attribute \src "libresoc.v:119704.3-119719.6" process $proc$libresoc.v:119704$4469 assign { } { } assign { } { } assign $0\dec58_form[4:0] $1\dec58_form[4:0] attribute \src "libresoc.v:119705.5-119705.29" switch \initial attribute \src "libresoc.v:119705.9-119705.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_form[4:0] 5'00101 case assign $1\dec58_form[4:0] 5'00000 end sync always update \dec58_form $0\dec58_form[4:0] end attribute \src "libresoc.v:119720.3-119735.6" process $proc$libresoc.v:119720$4470 assign { } { } assign { } { } assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] attribute \src "libresoc.v:119721.5-119721.29" switch \initial attribute \src "libresoc.v:119721.9-119721.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_is_32b[0:0] 1'0 case assign $1\dec58_is_32b[0:0] 1'0 end sync always update \dec58_is_32b $0\dec58_is_32b[0:0] end attribute \src "libresoc.v:119736.3-119751.6" process $proc$libresoc.v:119736$4471 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] attribute \src "libresoc.v:119737.5-119737.29" switch \initial attribute \src "libresoc.v:119737.9-119737.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sgn[0:0] 1'0 case assign $1\dec58_sgn[0:0] 1'0 end sync always update \dec58_sgn $0\dec58_sgn[0:0] end attribute \src "libresoc.v:119752.3-119767.6" process $proc$libresoc.v:119752$4472 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] attribute \src "libresoc.v:119753.5-119753.29" switch \initial attribute \src "libresoc.v:119753.9-119753.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_lk[0:0] 1'0 case assign $1\dec58_lk[0:0] 1'0 end sync always update \dec58_lk $0\dec58_lk[0:0] end attribute \src "libresoc.v:119768.3-119783.6" process $proc$libresoc.v:119768$4473 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] attribute \src "libresoc.v:119769.5-119769.29" switch \initial attribute \src "libresoc.v:119769.9-119769.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_sgl_pipe[0:0] 1'1 case assign $1\dec58_sgl_pipe[0:0] 1'0 end sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end attribute \src "libresoc.v:119784.3-119799.6" process $proc$libresoc.v:119784$4474 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] attribute \src "libresoc.v:119785.5-119785.29" switch \initial attribute \src "libresoc.v:119785.9-119785.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_SV_Etype[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_SV_Etype[1:0] 2'10 case assign $1\dec58_SV_Etype[1:0] 2'00 end sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end attribute \src "libresoc.v:119800.3-119815.6" process $proc$libresoc.v:119800$4475 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] attribute \src "libresoc.v:119801.5-119801.29" switch \initial attribute \src "libresoc.v:119801.9-119801.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_SV_Ptype[1:0] 2'10 case assign $1\dec58_SV_Ptype[1:0] 2'00 end sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end attribute \src "libresoc.v:119816.3-119831.6" process $proc$libresoc.v:119816$4476 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] attribute \src "libresoc.v:119817.5-119817.29" switch \initial attribute \src "libresoc.v:119817.9-119817.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_in1_sel[2:0] 3'010 case assign $1\dec58_in1_sel[2:0] 3'000 end sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end attribute \src "libresoc.v:119832.3-119847.6" process $proc$libresoc.v:119832$4477 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] attribute \src "libresoc.v:119833.5-119833.29" switch \initial attribute \src "libresoc.v:119833.9-119833.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_in2_sel[3:0] 4'1000 case assign $1\dec58_in2_sel[3:0] 4'0000 end sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end attribute \src "libresoc.v:119848.3-119863.6" process $proc$libresoc.v:119848$4478 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] attribute \src "libresoc.v:119849.5-119849.29" switch \initial attribute \src "libresoc.v:119849.9-119849.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_in3_sel[1:0] 2'00 case assign $1\dec58_in3_sel[1:0] 2'00 end sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end attribute \src "libresoc.v:119864.3-119879.6" process $proc$libresoc.v:119864$4479 assign { } { } assign { } { } assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] attribute \src "libresoc.v:119865.5-119865.29" switch \initial attribute \src "libresoc.v:119865.9-119865.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec58_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec58_out_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\dec58_out_sel[2:0] 3'001 case assign $1\dec58_out_sel[2:0] 3'000 end sync always update \dec58_out_sel $0\dec58_out_sel[2:0] end connect \opcode_switch \opcode_in [1:0] end attribute \src "libresoc.v:119885.1-120664.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 attribute \src "libresoc.v:120585.3-120597.6" wire width 2 $0\dec62_SV_Etype[1:0] attribute \src "libresoc.v:120598.3-120610.6" wire width 2 $0\dec62_SV_Ptype[1:0] attribute \src "libresoc.v:120429.3-120441.6" wire width 8 $0\dec62_asmcode[7:0] attribute \src "libresoc.v:120481.3-120493.6" wire $0\dec62_br[0:0] attribute \src "libresoc.v:120247.3-120259.6" wire width 3 $0\dec62_cr_in[2:0] attribute \src "libresoc.v:120260.3-120272.6" wire width 3 $0\dec62_cr_out[2:0] attribute \src "libresoc.v:120416.3-120428.6" wire width 2 $0\dec62_cry_in[1:0] attribute \src "libresoc.v:120468.3-120480.6" wire $0\dec62_cry_out[0:0] attribute \src "libresoc.v:120520.3-120532.6" wire width 5 $0\dec62_form[4:0] attribute \src "libresoc.v:120234.3-120246.6" wire width 14 $0\dec62_function_unit[13:0] attribute \src "libresoc.v:120611.3-120623.6" wire width 3 $0\dec62_in1_sel[2:0] attribute \src "libresoc.v:120624.3-120636.6" wire width 4 $0\dec62_in2_sel[3:0] attribute \src "libresoc.v:120637.3-120649.6" wire width 2 $0\dec62_in3_sel[1:0] attribute \src "libresoc.v:120377.3-120389.6" wire width 7 $0\dec62_internal_op[6:0] attribute \src "libresoc.v:120442.3-120454.6" wire $0\dec62_inv_a[0:0] attribute \src "libresoc.v:120455.3-120467.6" wire $0\dec62_inv_out[0:0] attribute \src "libresoc.v:120533.3-120545.6" wire $0\dec62_is_32b[0:0] attribute \src "libresoc.v:120364.3-120376.6" wire width 4 $0\dec62_ldst_len[3:0] attribute \src "libresoc.v:120559.3-120571.6" wire $0\dec62_lk[0:0] attribute \src "libresoc.v:120650.3-120662.6" wire width 3 $0\dec62_out_sel[2:0] attribute \src "libresoc.v:120403.3-120415.6" wire width 2 $0\dec62_rc_sel[1:0] attribute \src "libresoc.v:120507.3-120519.6" wire $0\dec62_rsrv[0:0] attribute \src "libresoc.v:120572.3-120584.6" wire $0\dec62_sgl_pipe[0:0] attribute \src "libresoc.v:120546.3-120558.6" wire $0\dec62_sgn[0:0] attribute \src "libresoc.v:120494.3-120506.6" wire $0\dec62_sgn_ext[0:0] attribute \src "libresoc.v:120338.3-120350.6" wire width 3 $0\dec62_sv_cr_in[2:0] attribute \src "libresoc.v:120351.3-120363.6" wire width 3 $0\dec62_sv_cr_out[2:0] attribute \src "libresoc.v:120273.3-120285.6" wire width 3 $0\dec62_sv_in1[2:0] attribute \src "libresoc.v:120286.3-120298.6" wire width 3 $0\dec62_sv_in2[2:0] attribute \src "libresoc.v:120299.3-120311.6" wire width 3 $0\dec62_sv_in3[2:0] attribute \src "libresoc.v:120325.3-120337.6" wire width 3 $0\dec62_sv_out2[2:0] attribute \src "libresoc.v:120312.3-120324.6" wire width 3 $0\dec62_sv_out[2:0] attribute \src "libresoc.v:120390.3-120402.6" wire width 2 $0\dec62_upd[1:0] attribute \src "libresoc.v:119886.7-119886.20" wire $0\initial[0:0] attribute \src "libresoc.v:120585.3-120597.6" wire width 2 $1\dec62_SV_Etype[1:0] attribute \src "libresoc.v:120598.3-120610.6" wire width 2 $1\dec62_SV_Ptype[1:0] attribute \src "libresoc.v:120429.3-120441.6" wire width 8 $1\dec62_asmcode[7:0] attribute \src "libresoc.v:120481.3-120493.6" wire $1\dec62_br[0:0] attribute \src "libresoc.v:120247.3-120259.6" wire width 3 $1\dec62_cr_in[2:0] attribute \src "libresoc.v:120260.3-120272.6" wire width 3 $1\dec62_cr_out[2:0] attribute \src "libresoc.v:120416.3-120428.6" wire width 2 $1\dec62_cry_in[1:0] attribute \src "libresoc.v:120468.3-120480.6" wire $1\dec62_cry_out[0:0] attribute \src "libresoc.v:120520.3-120532.6" wire width 5 $1\dec62_form[4:0] attribute \src "libresoc.v:120234.3-120246.6" wire width 14 $1\dec62_function_unit[13:0] attribute \src "libresoc.v:120611.3-120623.6" wire width 3 $1\dec62_in1_sel[2:0] attribute \src "libresoc.v:120624.3-120636.6" wire width 4 $1\dec62_in2_sel[3:0] attribute \src "libresoc.v:120637.3-120649.6" wire width 2 $1\dec62_in3_sel[1:0] attribute \src "libresoc.v:120377.3-120389.6" wire width 7 $1\dec62_internal_op[6:0] attribute \src "libresoc.v:120442.3-120454.6" wire $1\dec62_inv_a[0:0] attribute \src "libresoc.v:120455.3-120467.6" wire $1\dec62_inv_out[0:0] attribute \src "libresoc.v:120533.3-120545.6" wire $1\dec62_is_32b[0:0] attribute \src "libresoc.v:120364.3-120376.6" wire width 4 $1\dec62_ldst_len[3:0] attribute \src "libresoc.v:120559.3-120571.6" wire $1\dec62_lk[0:0] attribute \src "libresoc.v:120650.3-120662.6" wire width 3 $1\dec62_out_sel[2:0] attribute \src "libresoc.v:120403.3-120415.6" wire width 2 $1\dec62_rc_sel[1:0] attribute \src "libresoc.v:120507.3-120519.6" wire $1\dec62_rsrv[0:0] attribute \src "libresoc.v:120572.3-120584.6" wire $1\dec62_sgl_pipe[0:0] attribute \src "libresoc.v:120546.3-120558.6" wire $1\dec62_sgn[0:0] attribute \src "libresoc.v:120494.3-120506.6" wire $1\dec62_sgn_ext[0:0] attribute \src "libresoc.v:120338.3-120350.6" wire width 3 $1\dec62_sv_cr_in[2:0] attribute \src "libresoc.v:120351.3-120363.6" wire width 3 $1\dec62_sv_cr_out[2:0] attribute \src "libresoc.v:120273.3-120285.6" wire width 3 $1\dec62_sv_in1[2:0] attribute \src "libresoc.v:120286.3-120298.6" wire width 3 $1\dec62_sv_in2[2:0] attribute \src "libresoc.v:120299.3-120311.6" wire width 3 $1\dec62_sv_in3[2:0] attribute \src "libresoc.v:120325.3-120337.6" wire width 3 $1\dec62_sv_out2[2:0] attribute \src "libresoc.v:120312.3-120324.6" wire width 3 $1\dec62_sv_out[2:0] attribute \src "libresoc.v:120390.3-120402.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 5 \dec62_SV_Etype attribute \enum_base_type "SVPtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "P1" attribute \enum_value_10 "P2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 6 \dec62_SV_Ptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 8 output 4 \dec62_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 27 \dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 11 \dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 12 \dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 23 \dec62_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 26 \dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" attribute \enum_value_00010 "B" attribute \enum_value_00011 "SC" attribute \enum_value_00100 "D" attribute \enum_value_00101 "DS" attribute \enum_value_00110 "DQ" attribute \enum_value_00111 "DX" attribute \enum_value_01000 "X" attribute \enum_value_01001 "XL" attribute \enum_value_01010 "XFX" attribute \enum_value_01011 "XFL" attribute \enum_value_01100 "XX1" attribute \enum_value_01101 "XX2" attribute \enum_value_01110 "XX3" attribute \enum_value_01111 "XX4" attribute \enum_value_10000 "XS" attribute \enum_value_10001 "XO" attribute \enum_value_10010 "A" attribute \enum_value_10011 "M" attribute \enum_value_10100 "MD" attribute \enum_value_10101 "MDS" attribute \enum_value_10110 "VA" attribute \enum_value_10111 "VC" attribute \enum_value_11000 "VX" attribute \enum_value_11001 "EVX" attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 5 output 3 \dec62_form attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 output 1 \dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 7 \dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 8 \dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 9 \dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 output 2 \dec62_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 24 \dec62_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 25 \dec62_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 30 \dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 output 20 \dec62_ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 32 \dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 10 \dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 22 \dec62_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 29 \dec62_rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 33 \dec62_sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 31 \dec62_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire output 28 \dec62_sgn_ext attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 18 \dec62_sv_cr_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 19 \dec62_sv_cr_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 13 \dec62_sv_in1 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 14 \dec62_sv_in2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 15 \dec62_sv_in3 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 16 \dec62_sv_out attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" attribute \enum_value_010 "Idx1" attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 output 17 \dec62_sv_out2 attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec62_upd attribute \src "libresoc.v:119886.7-119886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch attribute \src "libresoc.v:119886.7-119886.20" process $proc$libresoc.v:119886$4514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:120234.3-120246.6" process $proc$libresoc.v:120234$4481 assign { } { } assign { } { } assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] attribute \src "libresoc.v:120235.5-120235.29" switch \initial attribute \src "libresoc.v:120235.9-120235.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_function_unit[13:0] 14'00000000000100 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_function_unit[13:0] 14'00000000000100 case assign $1\dec62_function_unit[13:0] 14'00000000000000 end sync always update \dec62_function_unit $0\dec62_function_unit[13:0] end attribute \src "libresoc.v:120247.3-120259.6" process $proc$libresoc.v:120247$4482 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] attribute \src "libresoc.v:120248.5-120248.29" switch \initial attribute \src "libresoc.v:120248.9-120248.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_cr_in[2:0] 3'000 case assign $1\dec62_cr_in[2:0] 3'000 end sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end attribute \src "libresoc.v:120260.3-120272.6" process $proc$libresoc.v:120260$4483 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] attribute \src "libresoc.v:120261.5-120261.29" switch \initial attribute \src "libresoc.v:120261.9-120261.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_cr_out[2:0] 3'000 case assign $1\dec62_cr_out[2:0] 3'000 end sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end attribute \src "libresoc.v:120273.3-120285.6" process $proc$libresoc.v:120273$4484 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] attribute \src "libresoc.v:120274.5-120274.29" switch \initial attribute \src "libresoc.v:120274.9-120274.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sv_in1[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sv_in1[2:0] 3'011 case assign $1\dec62_sv_in1[2:0] 3'000 end sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end attribute \src "libresoc.v:120286.3-120298.6" process $proc$libresoc.v:120286$4485 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] attribute \src "libresoc.v:120287.5-120287.29" switch \initial attribute \src "libresoc.v:120287.9-120287.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sv_in2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sv_in2[2:0] 3'000 case assign $1\dec62_sv_in2[2:0] 3'000 end sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end attribute \src "libresoc.v:120299.3-120311.6" process $proc$libresoc.v:120299$4486 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] attribute \src "libresoc.v:120300.5-120300.29" switch \initial attribute \src "libresoc.v:120300.9-120300.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sv_in3[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sv_in3[2:0] 3'010 case assign $1\dec62_sv_in3[2:0] 3'000 end sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end attribute \src "libresoc.v:120312.3-120324.6" process $proc$libresoc.v:120312$4487 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] attribute \src "libresoc.v:120313.5-120313.29" switch \initial attribute \src "libresoc.v:120313.9-120313.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sv_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sv_out[2:0] 3'000 case assign $1\dec62_sv_out[2:0] 3'000 end sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end attribute \src "libresoc.v:120325.3-120337.6" process $proc$libresoc.v:120325$4488 assign { } { } assign { } { } assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0] attribute \src "libresoc.v:120326.5-120326.29" switch \initial attribute \src "libresoc.v:120326.9-120326.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sv_out2[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sv_out2[2:0] 3'001 case assign $1\dec62_sv_out2[2:0] 3'000 end sync always update \dec62_sv_out2 $0\dec62_sv_out2[2:0] end attribute \src "libresoc.v:120338.3-120350.6" process $proc$libresoc.v:120338$4489 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] attribute \src "libresoc.v:120339.5-120339.29" switch \initial attribute \src "libresoc.v:120339.9-120339.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sv_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sv_cr_in[2:0] 3'000 case assign $1\dec62_sv_cr_in[2:0] 3'000 end sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end attribute \src "libresoc.v:120351.3-120363.6" process $proc$libresoc.v:120351$4490 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] attribute \src "libresoc.v:120352.5-120352.29" switch \initial attribute \src "libresoc.v:120352.9-120352.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sv_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sv_cr_out[2:0] 3'000 case assign $1\dec62_sv_cr_out[2:0] 3'000 end sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end attribute \src "libresoc.v:120364.3-120376.6" process $proc$libresoc.v:120364$4491 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] attribute \src "libresoc.v:120365.5-120365.29" switch \initial attribute \src "libresoc.v:120365.9-120365.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_ldst_len[3:0] 4'1000 case assign $1\dec62_ldst_len[3:0] 4'0000 end sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end attribute \src "libresoc.v:120377.3-120389.6" process $proc$libresoc.v:120377$4492 assign { } { } assign { } { } assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] attribute \src "libresoc.v:120378.5-120378.29" switch \initial attribute \src "libresoc.v:120378.9-120378.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_internal_op[6:0] 7'0100110 case assign $1\dec62_internal_op[6:0] 7'0000000 end sync always update \dec62_internal_op $0\dec62_internal_op[6:0] end attribute \src "libresoc.v:120390.3-120402.6" process $proc$libresoc.v:120390$4493 assign { } { } assign { } { } assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] attribute \src "libresoc.v:120391.5-120391.29" switch \initial attribute \src "libresoc.v:120391.9-120391.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_upd[1:0] 2'01 case assign $1\dec62_upd[1:0] 2'00 end sync always update \dec62_upd $0\dec62_upd[1:0] end attribute \src "libresoc.v:120403.3-120415.6" process $proc$libresoc.v:120403$4494 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] attribute \src "libresoc.v:120404.5-120404.29" switch \initial attribute \src "libresoc.v:120404.9-120404.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_rc_sel[1:0] 2'00 case assign $1\dec62_rc_sel[1:0] 2'00 end sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end attribute \src "libresoc.v:120416.3-120428.6" process $proc$libresoc.v:120416$4495 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] attribute \src "libresoc.v:120417.5-120417.29" switch \initial attribute \src "libresoc.v:120417.9-120417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_cry_in[1:0] 2'00 case assign $1\dec62_cry_in[1:0] 2'00 end sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end attribute \src "libresoc.v:120429.3-120441.6" process $proc$libresoc.v:120429$4496 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] attribute \src "libresoc.v:120430.5-120430.29" switch \initial attribute \src "libresoc.v:120430.9-120430.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_asmcode[7:0] 8'10101101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_asmcode[7:0] 8'10110000 case assign $1\dec62_asmcode[7:0] 8'00000000 end sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end attribute \src "libresoc.v:120442.3-120454.6" process $proc$libresoc.v:120442$4497 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] attribute \src "libresoc.v:120443.5-120443.29" switch \initial attribute \src "libresoc.v:120443.9-120443.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_inv_a[0:0] 1'0 case assign $1\dec62_inv_a[0:0] 1'0 end sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end attribute \src "libresoc.v:120455.3-120467.6" process $proc$libresoc.v:120455$4498 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] attribute \src "libresoc.v:120456.5-120456.29" switch \initial attribute \src "libresoc.v:120456.9-120456.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_inv_out[0:0] 1'0 case assign $1\dec62_inv_out[0:0] 1'0 end sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end attribute \src "libresoc.v:120468.3-120480.6" process $proc$libresoc.v:120468$4499 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] attribute \src "libresoc.v:120469.5-120469.29" switch \initial attribute \src "libresoc.v:120469.9-120469.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_cry_out[0:0] 1'0 case assign $1\dec62_cry_out[0:0] 1'0 end sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end attribute \src "libresoc.v:120481.3-120493.6" process $proc$libresoc.v:120481$4500 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] attribute \src "libresoc.v:120482.5-120482.29" switch \initial attribute \src "libresoc.v:120482.9-120482.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_br[0:0] 1'0 case assign $1\dec62_br[0:0] 1'0 end sync always update \dec62_br $0\dec62_br[0:0] end attribute \src "libresoc.v:120494.3-120506.6" process $proc$libresoc.v:120494$4501 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] attribute \src "libresoc.v:120495.5-120495.29" switch \initial attribute \src "libresoc.v:120495.9-120495.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sgn_ext[0:0] 1'0 case assign $1\dec62_sgn_ext[0:0] 1'0 end sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end attribute \src "libresoc.v:120507.3-120519.6" process $proc$libresoc.v:120507$4502 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] attribute \src "libresoc.v:120508.5-120508.29" switch \initial attribute \src "libresoc.v:120508.9-120508.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_rsrv[0:0] 1'0 case assign $1\dec62_rsrv[0:0] 1'0 end sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end attribute \src "libresoc.v:120520.3-120532.6" process $proc$libresoc.v:120520$4503 assign { } { } assign { } { } assign $0\dec62_form[4:0] $1\dec62_form[4:0] attribute \src "libresoc.v:120521.5-120521.29" switch \initial attribute \src "libresoc.v:120521.9-120521.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_form[4:0] 5'00101 case assign $1\dec62_form[4:0] 5'00000 end sync always update \dec62_form $0\dec62_form[4:0] end attribute \src "libresoc.v:120533.3-120545.6" process $proc$libresoc.v:120533$4504 assign { } { } assign { } { } assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] attribute \src "libresoc.v:120534.5-120534.29" switch \initial attribute \src "libresoc.v:120534.9-120534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_is_32b[0:0] 1'0 case assign $1\dec62_is_32b[0:0] 1'0 end sync always update \dec62_is_32b $0\dec62_is_32b[0:0] end attribute \src "libresoc.v:120546.3-120558.6" process $proc$libresoc.v:120546$4505 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] attribute \src "libresoc.v:120547.5-120547.29" switch \initial attribute \src "libresoc.v:120547.9-120547.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sgn[0:0] 1'0 case assign $1\dec62_sgn[0:0] 1'0 end sync always update \dec62_sgn $0\dec62_sgn[0:0] end attribute \src "libresoc.v:120559.3-120571.6" process $proc$libresoc.v:120559$4506 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] attribute \src "libresoc.v:120560.5-120560.29" switch \initial attribute \src "libresoc.v:120560.9-120560.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_lk[0:0] 1'0 case assign $1\dec62_lk[0:0] 1'0 end sync always update \dec62_lk $0\dec62_lk[0:0] end attribute \src "libresoc.v:120572.3-120584.6" process $proc$libresoc.v:120572$4507 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] attribute \src "libresoc.v:120573.5-120573.29" switch \initial attribute \src "libresoc.v:120573.9-120573.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_sgl_pipe[0:0] 1'1 case assign $1\dec62_sgl_pipe[0:0] 1'0 end sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end attribute \src "libresoc.v:120585.3-120597.6" process $proc$libresoc.v:120585$4508 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] attribute \src "libresoc.v:120586.5-120586.29" switch \initial attribute \src "libresoc.v:120586.9-120586.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_SV_Etype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_SV_Etype[1:0] 2'01 case assign $1\dec62_SV_Etype[1:0] 2'00 end sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end attribute \src "libresoc.v:120598.3-120610.6" process $proc$libresoc.v:120598$4509 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] attribute \src "libresoc.v:120599.5-120599.29" switch \initial attribute \src "libresoc.v:120599.9-120599.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_SV_Ptype[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_SV_Ptype[1:0] 2'10 case assign $1\dec62_SV_Ptype[1:0] 2'00 end sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end attribute \src "libresoc.v:120611.3-120623.6" process $proc$libresoc.v:120611$4510 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] attribute \src "libresoc.v:120612.5-120612.29" switch \initial attribute \src "libresoc.v:120612.9-120612.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_in1_sel[2:0] 3'010 case assign $1\dec62_in1_sel[2:0] 3'000 end sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end attribute \src "libresoc.v:120624.3-120636.6" process $proc$libresoc.v:120624$4511 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] attribute \src "libresoc.v:120625.5-120625.29" switch \initial attribute \src "libresoc.v:120625.9-120625.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_in2_sel[3:0] 4'1000 case assign $1\dec62_in2_sel[3:0] 4'0000 end sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end attribute \src "libresoc.v:120637.3-120649.6" process $proc$libresoc.v:120637$4512 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] attribute \src "libresoc.v:120638.5-120638.29" switch \initial attribute \src "libresoc.v:120638.9-120638.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_in3_sel[1:0] 2'01 case assign $1\dec62_in3_sel[1:0] 2'00 end sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end attribute \src "libresoc.v:120650.3-120662.6" process $proc$libresoc.v:120650$4513 assign { } { } assign { } { } assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] attribute \src "libresoc.v:120651.5-120651.29" switch \initial attribute \src "libresoc.v:120651.9-120651.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec62_out_sel[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec62_out_sel[2:0] 3'000 case assign $1\dec62_out_sel[2:0] 3'000 end sync always update \dec62_out_sel $0\dec62_out_sel[2:0] end connect \opcode_switch \opcode_in [1:0] end attribute \src "libresoc.v:120668.1-121251.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU attribute \src "libresoc.v:121214.3-121228.6" wire width 14 $0\ALU__fn_unit[13:0] attribute \src "libresoc.v:121201.3-121213.6" wire width 7 $0\ALU__insn_type[6:0] attribute \src "libresoc.v:121186.3-121200.6" wire $0\ALU__write_cr0[0:0] attribute \src "libresoc.v:120669.7-120669.20" wire $0\initial[0:0] attribute \src "libresoc.v:121214.3-121228.6" wire width 14 $1\ALU__fn_unit[13:0] attribute \src "libresoc.v:121201.3-121213.6" wire width 7 $1\ALU__insn_type[6:0] attribute \src "libresoc.v:121186.3-121200.6" wire $1\ALU__write_cr0[0:0] attribute \src "libresoc.v:121102.18-121102.113" wire $and$libresoc.v:121102$4515_Y attribute \src "libresoc.v:121104.18-121104.110" wire $and$libresoc.v:121104$4517_Y attribute \src "libresoc.v:121117.18-121117.114" wire $and$libresoc.v:121117$4530_Y attribute \src "libresoc.v:121118.18-121118.116" wire $and$libresoc.v:121118$4531_Y attribute \src "libresoc.v:121120.18-121120.114" wire $and$libresoc.v:121120$4533_Y attribute \src "libresoc.v:121122.18-121122.110" wire $and$libresoc.v:121122$4535_Y attribute \src "libresoc.v:121123.17-121123.112" wire $and$libresoc.v:121123$4536_Y attribute \src "libresoc.v:121124.17-121124.114" wire $and$libresoc.v:121124$4537_Y attribute \src "libresoc.v:121105.18-121105.126" wire $eq$libresoc.v:121105$4518_Y attribute \src "libresoc.v:121106.18-121106.126" wire $eq$libresoc.v:121106$4519_Y attribute \src "libresoc.v:121108.18-121108.110" wire $eq$libresoc.v:121108$4521_Y attribute \src "libresoc.v:121109.18-121109.110" wire $eq$libresoc.v:121109$4522_Y attribute \src "libresoc.v:121111.18-121111.112" wire $eq$libresoc.v:121111$4524_Y attribute \src "libresoc.v:121112.17-121112.130" wire $eq$libresoc.v:121112$4525_Y attribute \src "libresoc.v:121114.18-121114.110" wire $eq$libresoc.v:121114$4527_Y attribute \src "libresoc.v:121116.18-121116.131" wire $eq$libresoc.v:121116$4529_Y attribute \src "libresoc.v:121119.18-121119.131" wire $eq$libresoc.v:121119$4532_Y attribute \src "libresoc.v:121125.17-121125.130" wire $eq$libresoc.v:121125$4538_Y attribute \src "libresoc.v:121103.18-121103.110" wire $not$libresoc.v:121103$4516_Y attribute \src "libresoc.v:121121.18-121121.110" wire $not$libresoc.v:121121$4534_Y attribute \src "libresoc.v:121107.18-121107.110" wire $or$libresoc.v:121107$4520_Y attribute \src "libresoc.v:121110.18-121110.110" wire $or$libresoc.v:121110$4523_Y attribute \src "libresoc.v:121113.18-121113.110" wire $or$libresoc.v:121113$4526_Y attribute \src "libresoc.v:121115.18-121115.110" wire $or$libresoc.v:121115$4528_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \ALU__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 4 \ALU__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 5 \ALU__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 6 \ALU__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 15 \ALU__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 20 \ALU__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 3 \ALU__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \ALU__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \ALU__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 17 \ALU__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \ALU__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \ALU__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \ALU__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \ALU__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \ALU__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \ALU__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \ALU__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_ALU_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_ALU_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_ALU_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_ALU_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_ALU_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_ALU_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_ALU_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_ALU_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_ALU_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_ALU_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_ALU_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_ALU_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_ALU_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_ALU_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_ALU_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:120669.7-120669.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121102$4515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:121102$4515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121104$4517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:121104$4517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121117$4530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:121117$4530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121118$4531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:121118$4531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121120$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:121120$4533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121122$4535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:121122$4535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121123$4536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:121123$4536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121124$4537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:121124$4537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:121105$4518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:121105$4518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:121106$4519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:121106$4519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:121108$4521 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:121108$4521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:121109$4522 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:121109$4522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:121111$4524 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:121111$4524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:121112$4525 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:121112$4525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:121114$4527 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:121114$4527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:121116$4529 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:121116$4529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:121119$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:121119$4532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:121125$4538 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:121125$4538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:121103$4516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:121103$4516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:121121$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:121121$4534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:121107$4520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:121107$4520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:121110$4523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:121110$4523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:121113$4526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:121113$4526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:121115$4528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:121115$4528_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:121126.7-121154.4" cell \dec \dec connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS connect \ALU_LI \dec_ALU_LI connect \ALU_OE \dec_ALU_OE connect \ALU_RA \dec_ALU_RA connect \ALU_Rc \dec_ALU_Rc connect \ALU_SH32 \dec_ALU_SH32 connect \ALU_SI \dec_ALU_SI connect \ALU_SPR \dec_ALU_SPR connect \ALU_UI \dec_ALU_UI connect \ALU_cr_out \dec_ALU_cr_out connect \ALU_cry_in \dec_ALU_cry_in connect \ALU_cry_out \dec_ALU_cry_out connect \ALU_function_unit \dec_ALU_function_unit connect \ALU_in1_sel \dec_ALU_in1_sel connect \ALU_in2_sel \dec_ALU_in2_sel connect \ALU_internal_op \dec_ALU_internal_op connect \ALU_inv_a \dec_ALU_inv_a connect \ALU_inv_out \dec_ALU_inv_out connect \ALU_is_32b \dec_ALU_is_32b connect \ALU_ldst_len \dec_ALU_ldst_len connect \ALU_rc_sel \dec_ALU_rc_sel connect \ALU_sgn \dec_ALU_sgn connect \ALU_sh \dec_ALU_sh connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:121155.10-121160.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:121161.10-121172.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS connect \ALU_LI \dec_ALU_LI connect \ALU_SH32 \dec_ALU_SH32 connect \ALU_SI \dec_ALU_SI connect \ALU_UI \dec_ALU_UI connect \ALU_sh \dec_ALU_sh connect \imm_b \dec_bi_imm_b connect \imm_b_ok \dec_bi_imm_b_ok connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:121173.10-121179.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op connect \oe \dec_oe_oe connect \oe_ok \dec_oe_oe_ok connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:121180.10-121185.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:120669.7-120669.20" process $proc$libresoc.v:120669$4542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:121186.3-121200.6" process $proc$libresoc.v:121186$4539 assign { } { } assign { } { } assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] attribute \src "libresoc.v:121187.5-121187.29" switch \initial attribute \src "libresoc.v:121187.9-121187.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_ALU_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 assign { } { } assign $1\ALU__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" case 3'010 , 3'011 assign { } { } assign $1\ALU__write_cr0[0:0] 1'1 case assign $1\ALU__write_cr0[0:0] 1'0 end sync always update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end attribute \src "libresoc.v:121201.3-121213.6" process $proc$libresoc.v:121201$4540 assign { } { } assign { } { } assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] attribute \src "libresoc.v:121202.5-121202.29" switch \initial attribute \src "libresoc.v:121202.9-121202.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\ALU__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\ALU__insn_type[6:0] 7'0000000 case assign $1\ALU__insn_type[6:0] \dec_ALU_internal_op end sync always update \ALU__insn_type $0\ALU__insn_type[6:0] end attribute \src "libresoc.v:121214.3-121228.6" process $proc$libresoc.v:121214$4541 assign { } { } assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] attribute \src "libresoc.v:121215.5-121215.29" switch \initial attribute \src "libresoc.v:121215.9-121215.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\ALU__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\ALU__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ALU__fn_unit[13:0] \dec_ALU_function_unit end sync always update \ALU__fn_unit $0\ALU__fn_unit[13:0] end connect \$10 $and$libresoc.v:121102$4515_Y connect \$12 $not$libresoc.v:121103$4516_Y connect \$14 $and$libresoc.v:121104$4517_Y connect \$16 $eq$libresoc.v:121105$4518_Y connect \$18 $eq$libresoc.v:121106$4519_Y connect \$20 $or$libresoc.v:121107$4520_Y connect \$22 $eq$libresoc.v:121108$4521_Y connect \$24 $eq$libresoc.v:121109$4522_Y connect \$26 $or$libresoc.v:121110$4523_Y connect \$28 $eq$libresoc.v:121111$4524_Y connect \$2 $eq$libresoc.v:121112$4525_Y connect \$30 $or$libresoc.v:121113$4526_Y connect \$32 $eq$libresoc.v:121114$4527_Y connect \$34 $or$libresoc.v:121115$4528_Y connect \$36 $eq$libresoc.v:121116$4529_Y connect \$38 $and$libresoc.v:121117$4530_Y connect \$40 $and$libresoc.v:121118$4531_Y connect \$42 $eq$libresoc.v:121119$4532_Y connect \$44 $and$libresoc.v:121120$4533_Y connect \$46 $not$libresoc.v:121121$4534_Y connect \$48 $and$libresoc.v:121122$4535_Y connect \$4 $and$libresoc.v:121123$4536_Y connect \$6 $and$libresoc.v:121124$4537_Y connect \$8 $eq$libresoc.v:121125$4538_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out connect \ALU__input_carry \dec_ALU_cry_in connect \ALU__invert_out \dec_ALU_inv_out connect \ALU__invert_in \dec_ALU_inv_a connect \ALU__data_len \dec_ALU_ldst_len connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_ALU_in2_sel connect \ALU__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_ALU_in1_sel connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_ALU_SPR [4:0] \dec_ALU_SPR [9:5] } connect \dec_oe_sel_in \dec_ALU_rc_sel connect \dec_rc_sel_in \dec_ALU_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end attribute \src "libresoc.v:121255.1-121735.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH attribute \src "libresoc.v:121685.3-121699.6" wire width 14 $0\BRANCH__fn_unit[13:0] attribute \src "libresoc.v:121710.3-121722.6" wire width 7 $0\BRANCH__insn_type[6:0] attribute \src "libresoc.v:121700.3-121709.6" wire $0\BRANCH__lk[0:0] attribute \src "libresoc.v:121256.7-121256.20" wire $0\initial[0:0] attribute \src "libresoc.v:121685.3-121699.6" wire width 14 $1\BRANCH__fn_unit[13:0] attribute \src "libresoc.v:121710.3-121722.6" wire width 7 $1\BRANCH__insn_type[6:0] attribute \src "libresoc.v:121700.3-121709.6" wire $1\BRANCH__lk[0:0] attribute \src "libresoc.v:121617.18-121617.113" wire $and$libresoc.v:121617$4543_Y attribute \src "libresoc.v:121619.18-121619.110" wire $and$libresoc.v:121619$4545_Y attribute \src "libresoc.v:121632.18-121632.114" wire $and$libresoc.v:121632$4558_Y attribute \src "libresoc.v:121633.18-121633.116" wire $and$libresoc.v:121633$4559_Y attribute \src "libresoc.v:121635.18-121635.114" wire $and$libresoc.v:121635$4561_Y attribute \src "libresoc.v:121637.18-121637.110" wire $and$libresoc.v:121637$4563_Y attribute \src "libresoc.v:121638.17-121638.112" wire $and$libresoc.v:121638$4564_Y attribute \src "libresoc.v:121639.17-121639.114" wire $and$libresoc.v:121639$4565_Y attribute \src "libresoc.v:121620.18-121620.129" wire $eq$libresoc.v:121620$4546_Y attribute \src "libresoc.v:121621.18-121621.129" wire $eq$libresoc.v:121621$4547_Y attribute \src "libresoc.v:121623.18-121623.110" wire $eq$libresoc.v:121623$4549_Y attribute \src "libresoc.v:121624.18-121624.110" wire $eq$libresoc.v:121624$4550_Y attribute \src "libresoc.v:121626.18-121626.112" wire $eq$libresoc.v:121626$4552_Y attribute \src "libresoc.v:121627.17-121627.133" wire $eq$libresoc.v:121627$4553_Y attribute \src "libresoc.v:121629.18-121629.110" wire $eq$libresoc.v:121629$4555_Y attribute \src "libresoc.v:121631.18-121631.134" wire $eq$libresoc.v:121631$4557_Y attribute \src "libresoc.v:121634.18-121634.134" wire $eq$libresoc.v:121634$4560_Y attribute \src "libresoc.v:121640.17-121640.133" wire $eq$libresoc.v:121640$4566_Y attribute \src "libresoc.v:121618.18-121618.110" wire $not$libresoc.v:121618$4544_Y attribute \src "libresoc.v:121636.18-121636.110" wire $not$libresoc.v:121636$4562_Y attribute \src "libresoc.v:121622.18-121622.110" wire $or$libresoc.v:121622$4548_Y attribute \src "libresoc.v:121625.18-121625.110" wire $or$libresoc.v:121625$4551_Y attribute \src "libresoc.v:121628.18-121628.110" wire $or$libresoc.v:121628$4554_Y attribute \src "libresoc.v:121630.18-121630.110" wire $or$libresoc.v:121630$4556_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 3 \BRANCH__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 5 \BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \BRANCH__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 6 \BRANCH__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 4 \BRANCH__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \BRANCH__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 2 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 11 \core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_BRANCH_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_BRANCH_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_BRANCH_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_BRANCH_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_BRANCH_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_BRANCH_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_BRANCH_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_BRANCH_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_BRANCH_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_BRANCH_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_BRANCH_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_BRANCH_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_BRANCH_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:121256.7-121256.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 1 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121617$4543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:121617$4543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121619$4545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:121619$4545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121632$4558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:121632$4558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121633$4559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:121633$4559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121635$4561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:121635$4561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:121637$4563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:121637$4563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121638$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:121638$4564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:121639$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:121639$4565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:121620$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:121620$4546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:121621$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:121621$4547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:121623$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:121623$4549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:121624$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:121624$4550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:121626$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:121626$4552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:121627$4553 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:121627$4553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:121629$4555 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:121629$4555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:121631$4557 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:121631$4557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:121634$4560 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:121634$4560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:121640$4566 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:121640$4566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:121618$4544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:121618$4544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:121636$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:121636$4562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:121622$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:121622$4548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:121625$4551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:121625$4551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:121628$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:121628$4554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:121630$4556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:121630$4556_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:121641.13-121663.4" cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS connect \BRANCH_LI \dec_BRANCH_LI connect \BRANCH_LK \dec_BRANCH_LK connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_Rc \dec_BRANCH_Rc connect \BRANCH_SH32 \dec_BRANCH_SH32 connect \BRANCH_SI \dec_BRANCH_SI connect \BRANCH_SPR \dec_BRANCH_SPR connect \BRANCH_UI \dec_BRANCH_UI connect \BRANCH_cr_out \dec_BRANCH_cr_out connect \BRANCH_function_unit \dec_BRANCH_function_unit connect \BRANCH_in2_sel \dec_BRANCH_in2_sel connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \BRANCH_is_32b \dec_BRANCH_is_32b connect \BRANCH_lk \dec_BRANCH_lk connect \BRANCH_rc_sel \dec_BRANCH_rc_sel connect \BRANCH_sh \dec_BRANCH_sh connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:121664.16-121675.4" cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS connect \BRANCH_LI \dec_BRANCH_LI connect \BRANCH_SH32 \dec_BRANCH_SH32 connect \BRANCH_SI \dec_BRANCH_SI connect \BRANCH_UI \dec_BRANCH_UI connect \BRANCH_sh \dec_BRANCH_sh connect \imm_b \dec_bi_imm_b connect \imm_b_ok \dec_bi_imm_b_ok connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:121676.16-121680.4" cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:121681.16-121684.4" cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:121256.7-121256.20" process $proc$libresoc.v:121256$4570 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:121685.3-121699.6" process $proc$libresoc.v:121685$4567 assign { } { } assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] attribute \src "libresoc.v:121686.5-121686.29" switch \initial attribute \src "libresoc.v:121686.9-121686.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\BRANCH__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\BRANCH__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\BRANCH__fn_unit[13:0] \dec_BRANCH_function_unit end sync always update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end attribute \src "libresoc.v:121700.3-121709.6" process $proc$libresoc.v:121700$4568 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] attribute \src "libresoc.v:121701.5-121701.29" switch \initial attribute \src "libresoc.v:121701.9-121701.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\BRANCH__lk[0:0] \dec_BRANCH_LK case assign $1\BRANCH__lk[0:0] 1'0 end sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end attribute \src "libresoc.v:121710.3-121722.6" process $proc$libresoc.v:121710$4569 assign { } { } assign { } { } assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] attribute \src "libresoc.v:121711.5-121711.29" switch \initial attribute \src "libresoc.v:121711.9-121711.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\BRANCH__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\BRANCH__insn_type[6:0] 7'0000000 case assign $1\BRANCH__insn_type[6:0] \dec_BRANCH_internal_op end sync always update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] end connect \$10 $and$libresoc.v:121617$4543_Y connect \$12 $not$libresoc.v:121618$4544_Y connect \$14 $and$libresoc.v:121619$4545_Y connect \$16 $eq$libresoc.v:121620$4546_Y connect \$18 $eq$libresoc.v:121621$4547_Y connect \$20 $or$libresoc.v:121622$4548_Y connect \$22 $eq$libresoc.v:121623$4549_Y connect \$24 $eq$libresoc.v:121624$4550_Y connect \$26 $or$libresoc.v:121625$4551_Y connect \$28 $eq$libresoc.v:121626$4552_Y connect \$2 $eq$libresoc.v:121627$4553_Y connect \$30 $or$libresoc.v:121628$4554_Y connect \$32 $eq$libresoc.v:121629$4555_Y connect \$34 $or$libresoc.v:121630$4556_Y connect \$36 $eq$libresoc.v:121631$4557_Y connect \$38 $and$libresoc.v:121632$4558_Y connect \$40 $and$libresoc.v:121633$4559_Y connect \$42 $eq$libresoc.v:121634$4560_Y connect \$44 $and$libresoc.v:121635$4561_Y connect \$46 $not$libresoc.v:121636$4562_Y connect \$48 $and$libresoc.v:121637$4563_Y connect \$4 $and$libresoc.v:121638$4564_Y connect \$6 $and$libresoc.v:121639$4565_Y connect \$8 $eq$libresoc.v:121640$4566_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_BRANCH_SPR [4:0] \dec_BRANCH_SPR [9:5] } connect \BRANCH__cia \core_pc connect \dec_oe_sel_in \dec_BRANCH_rc_sel connect \dec_rc_sel_in \dec_BRANCH_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end attribute \src "libresoc.v:121739.1-122111.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR attribute \src "libresoc.v:122088.3-122102.6" wire width 14 $0\CR__fn_unit[13:0] attribute \src "libresoc.v:122075.3-122087.6" wire width 7 $0\CR__insn_type[6:0] attribute \src "libresoc.v:121740.7-121740.20" wire $0\initial[0:0] attribute \src "libresoc.v:122088.3-122102.6" wire width 14 $1\CR__fn_unit[13:0] attribute \src "libresoc.v:122075.3-122087.6" wire width 7 $1\CR__insn_type[6:0] attribute \src "libresoc.v:122030.18-122030.113" wire $and$libresoc.v:122030$4571_Y attribute \src "libresoc.v:122032.18-122032.110" wire $and$libresoc.v:122032$4573_Y attribute \src "libresoc.v:122045.18-122045.114" wire $and$libresoc.v:122045$4586_Y attribute \src "libresoc.v:122046.18-122046.116" wire $and$libresoc.v:122046$4587_Y attribute \src "libresoc.v:122048.18-122048.114" wire $and$libresoc.v:122048$4589_Y attribute \src "libresoc.v:122050.18-122050.110" wire $and$libresoc.v:122050$4591_Y attribute \src "libresoc.v:122051.17-122051.112" wire $and$libresoc.v:122051$4592_Y attribute \src "libresoc.v:122052.17-122052.114" wire $and$libresoc.v:122052$4593_Y attribute \src "libresoc.v:122033.18-122033.125" wire $eq$libresoc.v:122033$4574_Y attribute \src "libresoc.v:122034.18-122034.125" wire $eq$libresoc.v:122034$4575_Y attribute \src "libresoc.v:122036.18-122036.110" wire $eq$libresoc.v:122036$4577_Y attribute \src "libresoc.v:122037.18-122037.110" wire $eq$libresoc.v:122037$4578_Y attribute \src "libresoc.v:122039.18-122039.112" wire $eq$libresoc.v:122039$4580_Y attribute \src "libresoc.v:122040.17-122040.129" wire $eq$libresoc.v:122040$4581_Y attribute \src "libresoc.v:122042.18-122042.110" wire $eq$libresoc.v:122042$4583_Y attribute \src "libresoc.v:122044.18-122044.130" wire $eq$libresoc.v:122044$4585_Y attribute \src "libresoc.v:122047.18-122047.130" wire $eq$libresoc.v:122047$4588_Y attribute \src "libresoc.v:122053.17-122053.129" wire $eq$libresoc.v:122053$4594_Y attribute \src "libresoc.v:122031.18-122031.110" wire $not$libresoc.v:122031$4572_Y attribute \src "libresoc.v:122049.18-122049.110" wire $not$libresoc.v:122049$4590_Y attribute \src "libresoc.v:122035.18-122035.110" wire $or$libresoc.v:122035$4576_Y attribute \src "libresoc.v:122038.18-122038.110" wire $or$libresoc.v:122038$4579_Y attribute \src "libresoc.v:122041.18-122041.110" wire $or$libresoc.v:122041$4582_Y attribute \src "libresoc.v:122043.18-122043.110" wire $or$libresoc.v:122043$4584_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 3 \CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 4 \CR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \CR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_CR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_CR_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_CR_SPR attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_CR_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_CR_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:121740.7-121740.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 5 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122030$4571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:122030$4571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122032$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:122032$4573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122045$4586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:122045$4586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122046$4587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:122046$4587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122048$4589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:122048$4589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122050$4591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:122050$4591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122051$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:122051$4592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122052$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:122052$4593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:122033$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:122033$4574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:122034$4575 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:122034$4575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:122036$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:122036$4577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:122037$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:122037$4578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:122039$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:122039$4580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:122040$4581 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:122040$4581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:122042$4583 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:122042$4583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:122044$4585 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:122044$4585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:122047$4588 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:122047$4588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:122053$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:122053$4594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:122031$4572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:122031$4572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:122049$4590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:122049$4590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:122035$4576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:122035$4576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:122038$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:122038$4579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:122041$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:122041$4582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:122043$4584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:122043$4584_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:122054.13-122065.4" cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc connect \CR_SPR \dec_CR_SPR connect \CR_cr_out \dec_CR_cr_out connect \CR_function_unit \dec_CR_function_unit connect \CR_internal_op \dec_CR_internal_op connect \CR_rc_sel \dec_CR_rc_sel connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:122066.16-122070.4" cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:122071.16-122074.4" cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:121740.7-121740.20" process $proc$libresoc.v:121740$4597 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:122075.3-122087.6" process $proc$libresoc.v:122075$4595 assign { } { } assign { } { } assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] attribute \src "libresoc.v:122076.5-122076.29" switch \initial attribute \src "libresoc.v:122076.9-122076.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\CR__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\CR__insn_type[6:0] 7'0000000 case assign $1\CR__insn_type[6:0] \dec_CR_internal_op end sync always update \CR__insn_type $0\CR__insn_type[6:0] end attribute \src "libresoc.v:122088.3-122102.6" process $proc$libresoc.v:122088$4596 assign { } { } assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0] attribute \src "libresoc.v:122089.5-122089.29" switch \initial attribute \src "libresoc.v:122089.9-122089.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\CR__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\CR__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\CR__fn_unit[13:0] \dec_CR_function_unit end sync always update \CR__fn_unit $0\CR__fn_unit[13:0] end connect \$10 $and$libresoc.v:122030$4571_Y connect \$12 $not$libresoc.v:122031$4572_Y connect \$14 $and$libresoc.v:122032$4573_Y connect \$16 $eq$libresoc.v:122033$4574_Y connect \$18 $eq$libresoc.v:122034$4575_Y connect \$20 $or$libresoc.v:122035$4576_Y connect \$22 $eq$libresoc.v:122036$4577_Y connect \$24 $eq$libresoc.v:122037$4578_Y connect \$26 $or$libresoc.v:122038$4579_Y connect \$28 $eq$libresoc.v:122039$4580_Y connect \$2 $eq$libresoc.v:122040$4581_Y connect \$30 $or$libresoc.v:122041$4582_Y connect \$32 $eq$libresoc.v:122042$4583_Y connect \$34 $or$libresoc.v:122043$4584_Y connect \$36 $eq$libresoc.v:122044$4585_Y connect \$38 $and$libresoc.v:122045$4586_Y connect \$40 $and$libresoc.v:122046$4587_Y connect \$42 $eq$libresoc.v:122047$4588_Y connect \$44 $and$libresoc.v:122048$4589_Y connect \$46 $not$libresoc.v:122049$4590_Y connect \$48 $and$libresoc.v:122050$4591_Y connect \$4 $and$libresoc.v:122051$4592_Y connect \$6 $and$libresoc.v:122052$4593_Y connect \$8 $eq$libresoc.v:122053$4594_Y connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } connect \dec_oe_sel_in \dec_CR_rc_sel connect \dec_rc_sel_in \dec_CR_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end attribute \src "libresoc.v:122115.1-122698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV attribute \src "libresoc.v:122661.3-122675.6" wire width 14 $0\DIV__fn_unit[13:0] attribute \src "libresoc.v:122648.3-122660.6" wire width 7 $0\DIV__insn_type[6:0] attribute \src "libresoc.v:122633.3-122647.6" wire $0\DIV__write_cr0[0:0] attribute \src "libresoc.v:122116.7-122116.20" wire $0\initial[0:0] attribute \src "libresoc.v:122661.3-122675.6" wire width 14 $1\DIV__fn_unit[13:0] attribute \src "libresoc.v:122648.3-122660.6" wire width 7 $1\DIV__insn_type[6:0] attribute \src "libresoc.v:122633.3-122647.6" wire $1\DIV__write_cr0[0:0] attribute \src "libresoc.v:122549.18-122549.113" wire $and$libresoc.v:122549$4598_Y attribute \src "libresoc.v:122551.18-122551.110" wire $and$libresoc.v:122551$4600_Y attribute \src "libresoc.v:122564.18-122564.114" wire $and$libresoc.v:122564$4613_Y attribute \src "libresoc.v:122565.18-122565.116" wire $and$libresoc.v:122565$4614_Y attribute \src "libresoc.v:122567.18-122567.114" wire $and$libresoc.v:122567$4616_Y attribute \src "libresoc.v:122569.18-122569.110" wire $and$libresoc.v:122569$4618_Y attribute \src "libresoc.v:122570.17-122570.112" wire $and$libresoc.v:122570$4619_Y attribute \src "libresoc.v:122571.17-122571.114" wire $and$libresoc.v:122571$4620_Y attribute \src "libresoc.v:122552.18-122552.126" wire $eq$libresoc.v:122552$4601_Y attribute \src "libresoc.v:122553.18-122553.126" wire $eq$libresoc.v:122553$4602_Y attribute \src "libresoc.v:122555.18-122555.110" wire $eq$libresoc.v:122555$4604_Y attribute \src "libresoc.v:122556.18-122556.110" wire $eq$libresoc.v:122556$4605_Y attribute \src "libresoc.v:122558.18-122558.112" wire $eq$libresoc.v:122558$4607_Y attribute \src "libresoc.v:122559.17-122559.130" wire $eq$libresoc.v:122559$4608_Y attribute \src "libresoc.v:122561.18-122561.110" wire $eq$libresoc.v:122561$4610_Y attribute \src "libresoc.v:122563.18-122563.131" wire $eq$libresoc.v:122563$4612_Y attribute \src "libresoc.v:122566.18-122566.131" wire $eq$libresoc.v:122566$4615_Y attribute \src "libresoc.v:122572.17-122572.130" wire $eq$libresoc.v:122572$4621_Y attribute \src "libresoc.v:122550.18-122550.110" wire $not$libresoc.v:122550$4599_Y attribute \src "libresoc.v:122568.18-122568.110" wire $not$libresoc.v:122568$4617_Y attribute \src "libresoc.v:122554.18-122554.110" wire $or$libresoc.v:122554$4603_Y attribute \src "libresoc.v:122557.18-122557.110" wire $or$libresoc.v:122557$4606_Y attribute \src "libresoc.v:122560.18-122560.110" wire $or$libresoc.v:122560$4609_Y attribute \src "libresoc.v:122562.18-122562.110" wire $or$libresoc.v:122562$4611_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \DIV__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 4 \DIV__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 5 \DIV__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 6 \DIV__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 13 \DIV__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 20 \DIV__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 3 \DIV__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \DIV__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \DIV__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 17 \DIV__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \DIV__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \DIV__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \DIV__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \DIV__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \DIV__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \DIV__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \DIV__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_DIV_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_DIV_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_DIV_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_DIV_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_DIV_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_DIV_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_DIV_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_DIV_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_DIV_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_DIV_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_DIV_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_DIV_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_DIV_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_DIV_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_DIV_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:122116.7-122116.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122549$4598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:122549$4598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122551$4600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:122551$4600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122564$4613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:122564$4613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122565$4614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:122565$4614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122567$4616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:122567$4616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:122569$4618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:122569$4618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122570$4619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:122570$4619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:122571$4620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:122571$4620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:122552$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:122552$4601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:122553$4602 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:122553$4602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:122555$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:122555$4604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:122556$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:122556$4605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:122558$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:122558$4607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:122559$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:122559$4608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:122561$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:122561$4610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:122563$4612 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:122563$4612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:122566$4615 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:122566$4615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:122572$4621 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:122572$4621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:122550$4599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:122550$4599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:122568$4617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:122568$4617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:122554$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:122554$4603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:122557$4606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:122557$4606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:122560$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:122560$4609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:122562$4611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:122562$4611_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:122573.13-122601.4" cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS connect \DIV_LI \dec_DIV_LI connect \DIV_OE \dec_DIV_OE connect \DIV_RA \dec_DIV_RA connect \DIV_Rc \dec_DIV_Rc connect \DIV_SH32 \dec_DIV_SH32 connect \DIV_SI \dec_DIV_SI connect \DIV_SPR \dec_DIV_SPR connect \DIV_UI \dec_DIV_UI connect \DIV_cr_out \dec_DIV_cr_out connect \DIV_cry_in \dec_DIV_cry_in connect \DIV_cry_out \dec_DIV_cry_out connect \DIV_function_unit \dec_DIV_function_unit connect \DIV_in1_sel \dec_DIV_in1_sel connect \DIV_in2_sel \dec_DIV_in2_sel connect \DIV_internal_op \dec_DIV_internal_op connect \DIV_inv_a \dec_DIV_inv_a connect \DIV_inv_out \dec_DIV_inv_out connect \DIV_is_32b \dec_DIV_is_32b connect \DIV_ldst_len \dec_DIV_ldst_len connect \DIV_rc_sel \dec_DIV_rc_sel connect \DIV_sgn \dec_DIV_sgn connect \DIV_sh \dec_DIV_sh connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:122602.16-122607.4" cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:122608.16-122619.4" cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS connect \DIV_LI \dec_DIV_LI connect \DIV_SH32 \dec_DIV_SH32 connect \DIV_SI \dec_DIV_SI connect \DIV_UI \dec_DIV_UI connect \DIV_sh \dec_DIV_sh connect \imm_b \dec_bi_imm_b connect \imm_b_ok \dec_bi_imm_b_ok connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:122620.16-122626.4" cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op connect \oe \dec_oe_oe connect \oe_ok \dec_oe_oe_ok connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:122627.16-122632.4" cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:122116.7-122116.20" process $proc$libresoc.v:122116$4625 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:122633.3-122647.6" process $proc$libresoc.v:122633$4622 assign { } { } assign { } { } assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] attribute \src "libresoc.v:122634.5-122634.29" switch \initial attribute \src "libresoc.v:122634.9-122634.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_DIV_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 assign { } { } assign $1\DIV__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" case 3'010 , 3'011 assign { } { } assign $1\DIV__write_cr0[0:0] 1'1 case assign $1\DIV__write_cr0[0:0] 1'0 end sync always update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end attribute \src "libresoc.v:122648.3-122660.6" process $proc$libresoc.v:122648$4623 assign { } { } assign { } { } assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] attribute \src "libresoc.v:122649.5-122649.29" switch \initial attribute \src "libresoc.v:122649.9-122649.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\DIV__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\DIV__insn_type[6:0] 7'0000000 case assign $1\DIV__insn_type[6:0] \dec_DIV_internal_op end sync always update \DIV__insn_type $0\DIV__insn_type[6:0] end attribute \src "libresoc.v:122661.3-122675.6" process $proc$libresoc.v:122661$4624 assign { } { } assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] attribute \src "libresoc.v:122662.5-122662.29" switch \initial attribute \src "libresoc.v:122662.9-122662.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\DIV__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\DIV__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\DIV__fn_unit[13:0] \dec_DIV_function_unit end sync always update \DIV__fn_unit $0\DIV__fn_unit[13:0] end connect \$10 $and$libresoc.v:122549$4598_Y connect \$12 $not$libresoc.v:122550$4599_Y connect \$14 $and$libresoc.v:122551$4600_Y connect \$16 $eq$libresoc.v:122552$4601_Y connect \$18 $eq$libresoc.v:122553$4602_Y connect \$20 $or$libresoc.v:122554$4603_Y connect \$22 $eq$libresoc.v:122555$4604_Y connect \$24 $eq$libresoc.v:122556$4605_Y connect \$26 $or$libresoc.v:122557$4606_Y connect \$28 $eq$libresoc.v:122558$4607_Y connect \$2 $eq$libresoc.v:122559$4608_Y connect \$30 $or$libresoc.v:122560$4609_Y connect \$32 $eq$libresoc.v:122561$4610_Y connect \$34 $or$libresoc.v:122562$4611_Y connect \$36 $eq$libresoc.v:122563$4612_Y connect \$38 $and$libresoc.v:122564$4613_Y connect \$40 $and$libresoc.v:122565$4614_Y connect \$42 $eq$libresoc.v:122566$4615_Y connect \$44 $and$libresoc.v:122567$4616_Y connect \$46 $not$libresoc.v:122568$4617_Y connect \$48 $and$libresoc.v:122569$4618_Y connect \$4 $and$libresoc.v:122570$4619_Y connect \$6 $and$libresoc.v:122571$4620_Y connect \$8 $eq$libresoc.v:122572$4621_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out connect \DIV__input_carry \dec_DIV_cry_in connect \DIV__invert_out \dec_DIV_inv_out connect \DIV__invert_in \dec_DIV_inv_a connect \DIV__data_len \dec_DIV_ldst_len connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_DIV_in2_sel connect \DIV__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_DIV_in1_sel connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_DIV_SPR [4:0] \dec_DIV_SPR [9:5] } connect \dec_oe_sel_in \dec_DIV_rc_sel connect \dec_rc_sel_in \dec_DIV_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end attribute \src "libresoc.v:122702.1-123263.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST attribute \src "libresoc.v:123227.3-123241.6" wire width 14 $0\LDST__fn_unit[13:0] attribute \src "libresoc.v:123214.3-123226.6" wire width 7 $0\LDST__insn_type[6:0] attribute \src "libresoc.v:122703.7-122703.20" wire $0\initial[0:0] attribute \src "libresoc.v:123227.3-123241.6" wire width 14 $1\LDST__fn_unit[13:0] attribute \src "libresoc.v:123214.3-123226.6" wire width 7 $1\LDST__insn_type[6:0] attribute \src "libresoc.v:123131.18-123131.113" wire $and$libresoc.v:123131$4626_Y attribute \src "libresoc.v:123133.18-123133.110" wire $and$libresoc.v:123133$4628_Y attribute \src "libresoc.v:123146.18-123146.114" wire $and$libresoc.v:123146$4641_Y attribute \src "libresoc.v:123147.18-123147.116" wire $and$libresoc.v:123147$4642_Y attribute \src "libresoc.v:123149.18-123149.114" wire $and$libresoc.v:123149$4644_Y attribute \src "libresoc.v:123151.18-123151.110" wire $and$libresoc.v:123151$4646_Y attribute \src "libresoc.v:123152.17-123152.112" wire $and$libresoc.v:123152$4647_Y attribute \src "libresoc.v:123153.17-123153.114" wire $and$libresoc.v:123153$4648_Y attribute \src "libresoc.v:123134.18-123134.127" wire $eq$libresoc.v:123134$4629_Y attribute \src "libresoc.v:123135.18-123135.127" wire $eq$libresoc.v:123135$4630_Y attribute \src "libresoc.v:123137.18-123137.110" wire $eq$libresoc.v:123137$4632_Y attribute \src "libresoc.v:123138.18-123138.110" wire $eq$libresoc.v:123138$4633_Y attribute \src "libresoc.v:123140.18-123140.112" wire $eq$libresoc.v:123140$4635_Y attribute \src "libresoc.v:123141.17-123141.131" wire $eq$libresoc.v:123141$4636_Y attribute \src "libresoc.v:123143.18-123143.110" wire $eq$libresoc.v:123143$4638_Y attribute \src "libresoc.v:123145.18-123145.132" wire $eq$libresoc.v:123145$4640_Y attribute \src "libresoc.v:123148.18-123148.132" wire $eq$libresoc.v:123148$4643_Y attribute \src "libresoc.v:123154.17-123154.131" wire $eq$libresoc.v:123154$4649_Y attribute \src "libresoc.v:123132.18-123132.110" wire $not$libresoc.v:123132$4627_Y attribute \src "libresoc.v:123150.18-123150.110" wire $not$libresoc.v:123150$4645_Y attribute \src "libresoc.v:123136.18-123136.110" wire $or$libresoc.v:123136$4631_Y attribute \src "libresoc.v:123139.18-123139.110" wire $or$libresoc.v:123139$4634_Y attribute \src "libresoc.v:123142.18-123142.110" wire $or$libresoc.v:123142$4637_Y attribute \src "libresoc.v:123144.18-123144.110" wire $or$libresoc.v:123144$4639_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \LDST__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 14 \LDST__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 4 \LDST__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 5 \LDST__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 6 \LDST__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 18 \LDST__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 3 \LDST__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \LDST__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \LDST__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 17 \LDST__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \LDST__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \LDST__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \LDST__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \LDST__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \LDST__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LDST_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LDST_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_LDST_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LDST_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LDST_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LDST_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LDST_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LDST_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_LDST_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_br attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LDST_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_LDST_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LDST_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LDST_sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LDST_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:122703.7-122703.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123131$4626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:123131$4626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123133$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:123133$4628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123146$4641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:123146$4641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123147$4642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:123147$4642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123149$4644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:123149$4644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123151$4646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:123151$4646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123152$4647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:123152$4647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123153$4648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:123153$4648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:123134$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:123134$4629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:123135$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:123135$4630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:123137$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:123137$4632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:123138$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:123138$4633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:123140$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:123140$4635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:123141$4636 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:123141$4636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:123143$4638 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:123143$4638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:123145$4640 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:123145$4640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:123148$4643 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:123148$4643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:123154$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:123154$4649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:123132$4627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:123132$4627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:123150$4645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:123150$4645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:123136$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:123136$4631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:123139$4634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:123139$4634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:123142$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:123142$4637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:123144$4639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:123144$4639_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:123155.13-123182.4" cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS connect \LDST_LI \dec_LDST_LI connect \LDST_OE \dec_LDST_OE connect \LDST_RA \dec_LDST_RA connect \LDST_Rc \dec_LDST_Rc connect \LDST_SH32 \dec_LDST_SH32 connect \LDST_SI \dec_LDST_SI connect \LDST_SPR \dec_LDST_SPR connect \LDST_UI \dec_LDST_UI connect \LDST_br \dec_LDST_br connect \LDST_cr_out \dec_LDST_cr_out connect \LDST_function_unit \dec_LDST_function_unit connect \LDST_in1_sel \dec_LDST_in1_sel connect \LDST_in2_sel \dec_LDST_in2_sel connect \LDST_internal_op \dec_LDST_internal_op connect \LDST_is_32b \dec_LDST_is_32b connect \LDST_ldst_len \dec_LDST_ldst_len connect \LDST_rc_sel \dec_LDST_rc_sel connect \LDST_sgn \dec_LDST_sgn connect \LDST_sgn_ext \dec_LDST_sgn_ext connect \LDST_sh \dec_LDST_sh connect \LDST_upd \dec_LDST_upd connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:123183.16-123188.4" cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:123189.16-123200.4" cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS connect \LDST_LI \dec_LDST_LI connect \LDST_SH32 \dec_LDST_SH32 connect \LDST_SI \dec_LDST_SI connect \LDST_UI \dec_LDST_UI connect \LDST_sh \dec_LDST_sh connect \imm_b \dec_bi_imm_b connect \imm_b_ok \dec_bi_imm_b_ok connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:123201.16-123207.4" cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op connect \oe \dec_oe_oe connect \oe_ok \dec_oe_oe_ok connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:123208.16-123213.4" cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:122703.7-122703.20" process $proc$libresoc.v:122703$4652 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:123214.3-123226.6" process $proc$libresoc.v:123214$4650 assign { } { } assign { } { } assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] attribute \src "libresoc.v:123215.5-123215.29" switch \initial attribute \src "libresoc.v:123215.9-123215.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\LDST__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\LDST__insn_type[6:0] 7'0000000 case assign $1\LDST__insn_type[6:0] \dec_LDST_internal_op end sync always update \LDST__insn_type $0\LDST__insn_type[6:0] end attribute \src "libresoc.v:123227.3-123241.6" process $proc$libresoc.v:123227$4651 assign { } { } assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] attribute \src "libresoc.v:123228.5-123228.29" switch \initial attribute \src "libresoc.v:123228.9-123228.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\LDST__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\LDST__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\LDST__fn_unit[13:0] \dec_LDST_function_unit end sync always update \LDST__fn_unit $0\LDST__fn_unit[13:0] end connect \$10 $and$libresoc.v:123131$4626_Y connect \$12 $not$libresoc.v:123132$4627_Y connect \$14 $and$libresoc.v:123133$4628_Y connect \$16 $eq$libresoc.v:123134$4629_Y connect \$18 $eq$libresoc.v:123135$4630_Y connect \$20 $or$libresoc.v:123136$4631_Y connect \$22 $eq$libresoc.v:123137$4632_Y connect \$24 $eq$libresoc.v:123138$4633_Y connect \$26 $or$libresoc.v:123139$4634_Y connect \$28 $eq$libresoc.v:123140$4635_Y connect \$2 $eq$libresoc.v:123141$4636_Y connect \$30 $or$libresoc.v:123142$4637_Y connect \$32 $eq$libresoc.v:123143$4638_Y connect \$34 $or$libresoc.v:123144$4639_Y connect \$36 $eq$libresoc.v:123145$4640_Y connect \$38 $and$libresoc.v:123146$4641_Y connect \$40 $and$libresoc.v:123147$4642_Y connect \$42 $eq$libresoc.v:123148$4643_Y connect \$44 $and$libresoc.v:123149$4644_Y connect \$46 $not$libresoc.v:123150$4645_Y connect \$48 $and$libresoc.v:123151$4646_Y connect \$4 $and$libresoc.v:123152$4647_Y connect \$6 $and$libresoc.v:123153$4648_Y connect \$8 $eq$libresoc.v:123154$4649_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br connect \LDST__is_signed \dec_LDST_sgn connect \LDST__is_32bit \dec_LDST_is_32b connect \LDST__data_len \dec_LDST_ldst_len connect { \LDST__oe__ok \LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \LDST__rc__ok \LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \LDST__imm_data__ok \LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_LDST_in2_sel connect \LDST__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LDST_in1_sel connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_LDST_SPR [4:0] \dec_LDST_SPR [9:5] } connect \dec_oe_sel_in \dec_LDST_rc_sel connect \dec_rc_sel_in \dec_LDST_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end attribute \src "libresoc.v:123267.1-123850.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL attribute \src "libresoc.v:123813.3-123827.6" wire width 14 $0\LOGICAL__fn_unit[13:0] attribute \src "libresoc.v:123800.3-123812.6" wire width 7 $0\LOGICAL__insn_type[6:0] attribute \src "libresoc.v:123785.3-123799.6" wire $0\LOGICAL__write_cr0[0:0] attribute \src "libresoc.v:123268.7-123268.20" wire $0\initial[0:0] attribute \src "libresoc.v:123813.3-123827.6" wire width 14 $1\LOGICAL__fn_unit[13:0] attribute \src "libresoc.v:123800.3-123812.6" wire width 7 $1\LOGICAL__insn_type[6:0] attribute \src "libresoc.v:123785.3-123799.6" wire $1\LOGICAL__write_cr0[0:0] attribute \src "libresoc.v:123701.18-123701.113" wire $and$libresoc.v:123701$4653_Y attribute \src "libresoc.v:123703.18-123703.110" wire $and$libresoc.v:123703$4655_Y attribute \src "libresoc.v:123716.18-123716.114" wire $and$libresoc.v:123716$4668_Y attribute \src "libresoc.v:123717.18-123717.116" wire $and$libresoc.v:123717$4669_Y attribute \src "libresoc.v:123719.18-123719.114" wire $and$libresoc.v:123719$4671_Y attribute \src "libresoc.v:123721.18-123721.110" wire $and$libresoc.v:123721$4673_Y attribute \src "libresoc.v:123722.17-123722.112" wire $and$libresoc.v:123722$4674_Y attribute \src "libresoc.v:123723.17-123723.114" wire $and$libresoc.v:123723$4675_Y attribute \src "libresoc.v:123704.18-123704.130" wire $eq$libresoc.v:123704$4656_Y attribute \src "libresoc.v:123705.18-123705.130" wire $eq$libresoc.v:123705$4657_Y attribute \src "libresoc.v:123707.18-123707.110" wire $eq$libresoc.v:123707$4659_Y attribute \src "libresoc.v:123708.18-123708.110" wire $eq$libresoc.v:123708$4660_Y attribute \src "libresoc.v:123710.18-123710.112" wire $eq$libresoc.v:123710$4662_Y attribute \src "libresoc.v:123711.17-123711.134" wire $eq$libresoc.v:123711$4663_Y attribute \src "libresoc.v:123713.18-123713.110" wire $eq$libresoc.v:123713$4665_Y attribute \src "libresoc.v:123715.18-123715.135" wire $eq$libresoc.v:123715$4667_Y attribute \src "libresoc.v:123718.18-123718.135" wire $eq$libresoc.v:123718$4670_Y attribute \src "libresoc.v:123724.17-123724.134" wire $eq$libresoc.v:123724$4676_Y attribute \src "libresoc.v:123702.18-123702.110" wire $not$libresoc.v:123702$4654_Y attribute \src "libresoc.v:123720.18-123720.110" wire $not$libresoc.v:123720$4672_Y attribute \src "libresoc.v:123706.18-123706.110" wire $or$libresoc.v:123706$4658_Y attribute \src "libresoc.v:123709.18-123709.110" wire $or$libresoc.v:123709$4661_Y attribute \src "libresoc.v:123712.18-123712.110" wire $or$libresoc.v:123712$4664_Y attribute \src "libresoc.v:123714.18-123714.110" wire $or$libresoc.v:123714$4666_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 19 \LOGICAL__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 4 \LOGICAL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 5 \LOGICAL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 6 \LOGICAL__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 13 \LOGICAL__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 20 \LOGICAL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 3 \LOGICAL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \LOGICAL__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \LOGICAL__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 17 \LOGICAL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \LOGICAL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \LOGICAL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \LOGICAL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \LOGICAL__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \LOGICAL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \LOGICAL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \LOGICAL__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LOGICAL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_LOGICAL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_LOGICAL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LOGICAL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LOGICAL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_LOGICAL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_LOGICAL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LOGICAL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_LOGICAL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_LOGICAL_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LOGICAL_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_LOGICAL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_LOGICAL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_LOGICAL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_LOGICAL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire \dec_ai_sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:123268.7-123268.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123701$4653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:123701$4653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123703$4655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:123703$4655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123716$4668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:123716$4668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123717$4669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:123717$4669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123719$4671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:123719$4671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:123721$4673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:123721$4673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123722$4674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:123722$4674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:123723$4675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:123723$4675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:123704$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:123704$4656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:123705$4657 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:123705$4657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:123707$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:123707$4659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:123708$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:123708$4660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:123710$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:123710$4662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:123711$4663 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:123711$4663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:123713$4665 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:123713$4665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:123715$4667 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:123715$4667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:123718$4670 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:123718$4670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:123724$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:123724$4676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:123702$4654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:123702$4654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:123720$4672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:123720$4672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:123706$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:123706$4658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:123709$4661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:123709$4661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:123712$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:123712$4664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:123714$4666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:123714$4666_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:123725.13-123753.4" cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS connect \LOGICAL_LI \dec_LOGICAL_LI connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_RA \dec_LOGICAL_RA connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \LOGICAL_SH32 \dec_LOGICAL_SH32 connect \LOGICAL_SI \dec_LOGICAL_SI connect \LOGICAL_SPR \dec_LOGICAL_SPR connect \LOGICAL_UI \dec_LOGICAL_UI connect \LOGICAL_cr_out \dec_LOGICAL_cr_out connect \LOGICAL_cry_in \dec_LOGICAL_cry_in connect \LOGICAL_cry_out \dec_LOGICAL_cry_out connect \LOGICAL_function_unit \dec_LOGICAL_function_unit connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel connect \LOGICAL_internal_op \dec_LOGICAL_internal_op connect \LOGICAL_inv_a \dec_LOGICAL_inv_a connect \LOGICAL_inv_out \dec_LOGICAL_inv_out connect \LOGICAL_is_32b \dec_LOGICAL_is_32b connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel connect \LOGICAL_sgn \dec_LOGICAL_sgn connect \LOGICAL_sh \dec_LOGICAL_sh connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:123754.16-123759.4" cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 attribute \src "libresoc.v:123760.16-123771.4" cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS connect \LOGICAL_LI \dec_LOGICAL_LI connect \LOGICAL_SH32 \dec_LOGICAL_SH32 connect \LOGICAL_SI \dec_LOGICAL_SI connect \LOGICAL_UI \dec_LOGICAL_UI connect \LOGICAL_sh \dec_LOGICAL_sh connect \imm_b \dec_bi_imm_b connect \imm_b_ok \dec_bi_imm_b_ok connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:123772.16-123778.4" cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op connect \oe \dec_oe_oe connect \oe_ok \dec_oe_oe_ok connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:123779.16-123784.4" cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:123268.7-123268.20" process $proc$libresoc.v:123268$4680 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:123785.3-123799.6" process $proc$libresoc.v:123785$4677 assign { } { } assign { } { } assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] attribute \src "libresoc.v:123786.5-123786.29" switch \initial attribute \src "libresoc.v:123786.9-123786.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_LOGICAL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 assign { } { } assign $1\LOGICAL__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" case 3'010 , 3'011 assign { } { } assign $1\LOGICAL__write_cr0[0:0] 1'1 case assign $1\LOGICAL__write_cr0[0:0] 1'0 end sync always update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end attribute \src "libresoc.v:123800.3-123812.6" process $proc$libresoc.v:123800$4678 assign { } { } assign { } { } assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] attribute \src "libresoc.v:123801.5-123801.29" switch \initial attribute \src "libresoc.v:123801.9-123801.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\LOGICAL__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\LOGICAL__insn_type[6:0] 7'0000000 case assign $1\LOGICAL__insn_type[6:0] \dec_LOGICAL_internal_op end sync always update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end attribute \src "libresoc.v:123813.3-123827.6" process $proc$libresoc.v:123813$4679 assign { } { } assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] attribute \src "libresoc.v:123814.5-123814.29" switch \initial attribute \src "libresoc.v:123814.9-123814.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\LOGICAL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\LOGICAL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\LOGICAL__fn_unit[13:0] \dec_LOGICAL_function_unit end sync always update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] end connect \$10 $and$libresoc.v:123701$4653_Y connect \$12 $not$libresoc.v:123702$4654_Y connect \$14 $and$libresoc.v:123703$4655_Y connect \$16 $eq$libresoc.v:123704$4656_Y connect \$18 $eq$libresoc.v:123705$4657_Y connect \$20 $or$libresoc.v:123706$4658_Y connect \$22 $eq$libresoc.v:123707$4659_Y connect \$24 $eq$libresoc.v:123708$4660_Y connect \$26 $or$libresoc.v:123709$4661_Y connect \$28 $eq$libresoc.v:123710$4662_Y connect \$2 $eq$libresoc.v:123711$4663_Y connect \$30 $or$libresoc.v:123712$4664_Y connect \$32 $eq$libresoc.v:123713$4665_Y connect \$34 $or$libresoc.v:123714$4666_Y connect \$36 $eq$libresoc.v:123715$4667_Y connect \$38 $and$libresoc.v:123716$4668_Y connect \$40 $and$libresoc.v:123717$4669_Y connect \$42 $eq$libresoc.v:123718$4670_Y connect \$44 $and$libresoc.v:123719$4671_Y connect \$46 $not$libresoc.v:123720$4672_Y connect \$48 $and$libresoc.v:123721$4673_Y connect \$4 $and$libresoc.v:123722$4674_Y connect \$6 $and$libresoc.v:123723$4675_Y connect \$8 $eq$libresoc.v:123724$4676_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out connect \LOGICAL__input_carry \dec_LOGICAL_cry_in connect \LOGICAL__invert_out \dec_LOGICAL_inv_out connect \LOGICAL__invert_in \dec_LOGICAL_inv_a connect \LOGICAL__data_len \dec_LOGICAL_ldst_len connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_LOGICAL_in2_sel connect \LOGICAL__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LOGICAL_in1_sel connect \dec_ai_sv_nz \sv_a_nz connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_LOGICAL_SPR [4:0] \dec_LOGICAL_SPR [9:5] } connect \dec_oe_sel_in \dec_LOGICAL_rc_sel connect \dec_rc_sel_in \dec_LOGICAL_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end attribute \src "libresoc.v:123854.1-124356.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL attribute \src "libresoc.v:124327.3-124341.6" wire width 14 $0\MUL__fn_unit[13:0] attribute \src "libresoc.v:124314.3-124326.6" wire width 7 $0\MUL__insn_type[6:0] attribute \src "libresoc.v:124299.3-124313.6" wire $0\MUL__write_cr0[0:0] attribute \src "libresoc.v:123855.7-123855.20" wire $0\initial[0:0] attribute \src "libresoc.v:124327.3-124341.6" wire width 14 $1\MUL__fn_unit[13:0] attribute \src "libresoc.v:124314.3-124326.6" wire width 7 $1\MUL__insn_type[6:0] attribute \src "libresoc.v:124299.3-124313.6" wire $1\MUL__write_cr0[0:0] attribute \src "libresoc.v:124228.18-124228.113" wire $and$libresoc.v:124228$4681_Y attribute \src "libresoc.v:124230.18-124230.110" wire $and$libresoc.v:124230$4683_Y attribute \src "libresoc.v:124243.18-124243.114" wire $and$libresoc.v:124243$4696_Y attribute \src "libresoc.v:124244.18-124244.116" wire $and$libresoc.v:124244$4697_Y attribute \src "libresoc.v:124246.18-124246.114" wire $and$libresoc.v:124246$4699_Y attribute \src "libresoc.v:124248.18-124248.110" wire $and$libresoc.v:124248$4701_Y attribute \src "libresoc.v:124249.17-124249.112" wire $and$libresoc.v:124249$4702_Y attribute \src "libresoc.v:124250.17-124250.114" wire $and$libresoc.v:124250$4703_Y attribute \src "libresoc.v:124231.18-124231.126" wire $eq$libresoc.v:124231$4684_Y attribute \src "libresoc.v:124232.18-124232.126" wire $eq$libresoc.v:124232$4685_Y attribute \src "libresoc.v:124234.18-124234.110" wire $eq$libresoc.v:124234$4687_Y attribute \src "libresoc.v:124235.18-124235.110" wire $eq$libresoc.v:124235$4688_Y attribute \src "libresoc.v:124237.18-124237.112" wire $eq$libresoc.v:124237$4690_Y attribute \src "libresoc.v:124238.17-124238.130" wire $eq$libresoc.v:124238$4691_Y attribute \src "libresoc.v:124240.18-124240.110" wire $eq$libresoc.v:124240$4693_Y attribute \src "libresoc.v:124242.18-124242.131" wire $eq$libresoc.v:124242$4695_Y attribute \src "libresoc.v:124245.18-124245.131" wire $eq$libresoc.v:124245$4698_Y attribute \src "libresoc.v:124251.17-124251.130" wire $eq$libresoc.v:124251$4704_Y attribute \src "libresoc.v:124229.18-124229.110" wire $not$libresoc.v:124229$4682_Y attribute \src "libresoc.v:124247.18-124247.110" wire $not$libresoc.v:124247$4700_Y attribute \src "libresoc.v:124233.18-124233.110" wire $or$libresoc.v:124233$4686_Y attribute \src "libresoc.v:124236.18-124236.110" wire $or$libresoc.v:124236$4689_Y attribute \src "libresoc.v:124239.18-124239.110" wire $or$libresoc.v:124239$4692_Y attribute \src "libresoc.v:124241.18-124241.110" wire $or$libresoc.v:124241$4694_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 3 \MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 4 \MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 5 \MUL__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 13 \MUL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \MUL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \MUL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \MUL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \MUL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \MUL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \MUL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 6 \MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \MUL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_MUL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_MUL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_MUL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_MUL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_MUL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_MUL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_MUL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_MUL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_MUL_UI attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_MUL_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_MUL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_MUL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_MUL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_MUL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:123855.7-123855.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 14 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124228$4681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:124228$4681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124230$4683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:124230$4683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124243$4696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:124243$4696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124244$4697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:124244$4697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124246$4699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:124246$4699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124248$4701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:124248$4701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124249$4702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:124249$4702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124250$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:124250$4703_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:124231$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:124231$4684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:124232$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:124232$4685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:124234$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:124234$4687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:124235$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:124235$4688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:124237$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:124237$4690_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:124238$4691 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:124238$4691_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:124240$4693 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:124240$4693_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:124242$4695 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:124242$4695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:124245$4698 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:124245$4698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:124251$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:124251$4704_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:124229$4682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:124229$4682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:124247$4700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:124247$4700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:124233$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:124233$4686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:124236$4689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:124236$4689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:124239$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:124239$4692_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:124241$4694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:124241$4694_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:124252.13-124273.4" cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS connect \MUL_LI \dec_MUL_LI connect \MUL_OE \dec_MUL_OE connect \MUL_Rc \dec_MUL_Rc connect \MUL_SH32 \dec_MUL_SH32 connect \MUL_SI \dec_MUL_SI connect \MUL_SPR \dec_MUL_SPR connect \MUL_UI \dec_MUL_UI connect \MUL_cr_out \dec_MUL_cr_out connect \MUL_function_unit \dec_MUL_function_unit connect \MUL_in2_sel \dec_MUL_in2_sel connect \MUL_internal_op \dec_MUL_internal_op connect \MUL_is_32b \dec_MUL_is_32b connect \MUL_rc_sel \dec_MUL_rc_sel connect \MUL_sgn \dec_MUL_sgn connect \MUL_sh \dec_MUL_sh connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:124274.16-124285.4" cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS connect \MUL_LI \dec_MUL_LI connect \MUL_SH32 \dec_MUL_SH32 connect \MUL_SI \dec_MUL_SI connect \MUL_UI \dec_MUL_UI connect \MUL_sh \dec_MUL_sh connect \imm_b \dec_bi_imm_b connect \imm_b_ok \dec_bi_imm_b_ok connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:124286.16-124292.4" cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op connect \oe \dec_oe_oe connect \oe_ok \dec_oe_oe_ok connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:124293.16-124298.4" cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:123855.7-123855.20" process $proc$libresoc.v:123855$4708 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:124299.3-124313.6" process $proc$libresoc.v:124299$4705 assign { } { } assign { } { } assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] attribute \src "libresoc.v:124300.5-124300.29" switch \initial attribute \src "libresoc.v:124300.9-124300.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_MUL_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 assign { } { } assign $1\MUL__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" case 3'010 , 3'011 assign { } { } assign $1\MUL__write_cr0[0:0] 1'1 case assign $1\MUL__write_cr0[0:0] 1'0 end sync always update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end attribute \src "libresoc.v:124314.3-124326.6" process $proc$libresoc.v:124314$4706 assign { } { } assign { } { } assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] attribute \src "libresoc.v:124315.5-124315.29" switch \initial attribute \src "libresoc.v:124315.9-124315.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\MUL__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\MUL__insn_type[6:0] 7'0000000 case assign $1\MUL__insn_type[6:0] \dec_MUL_internal_op end sync always update \MUL__insn_type $0\MUL__insn_type[6:0] end attribute \src "libresoc.v:124327.3-124341.6" process $proc$libresoc.v:124327$4707 assign { } { } assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] attribute \src "libresoc.v:124328.5-124328.29" switch \initial attribute \src "libresoc.v:124328.9-124328.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\MUL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\MUL__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\MUL__fn_unit[13:0] \dec_MUL_function_unit end sync always update \MUL__fn_unit $0\MUL__fn_unit[13:0] end connect \$10 $and$libresoc.v:124228$4681_Y connect \$12 $not$libresoc.v:124229$4682_Y connect \$14 $and$libresoc.v:124230$4683_Y connect \$16 $eq$libresoc.v:124231$4684_Y connect \$18 $eq$libresoc.v:124232$4685_Y connect \$20 $or$libresoc.v:124233$4686_Y connect \$22 $eq$libresoc.v:124234$4687_Y connect \$24 $eq$libresoc.v:124235$4688_Y connect \$26 $or$libresoc.v:124236$4689_Y connect \$28 $eq$libresoc.v:124237$4690_Y connect \$2 $eq$libresoc.v:124238$4691_Y connect \$30 $or$libresoc.v:124239$4692_Y connect \$32 $eq$libresoc.v:124240$4693_Y connect \$34 $or$libresoc.v:124241$4694_Y connect \$36 $eq$libresoc.v:124242$4695_Y connect \$38 $and$libresoc.v:124243$4696_Y connect \$40 $and$libresoc.v:124244$4697_Y connect \$42 $eq$libresoc.v:124245$4698_Y connect \$44 $and$libresoc.v:124246$4699_Y connect \$46 $not$libresoc.v:124247$4700_Y connect \$48 $and$libresoc.v:124248$4701_Y connect \$4 $and$libresoc.v:124249$4702_Y connect \$6 $and$libresoc.v:124250$4703_Y connect \$8 $eq$libresoc.v:124251$4704_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_MUL_in2_sel connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_MUL_SPR [4:0] \dec_MUL_SPR [9:5] } connect \dec_oe_sel_in \dec_MUL_rc_sel connect \dec_rc_sel_in \dec_MUL_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end attribute \src "libresoc.v:124360.1-124906.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT attribute \src "libresoc.v:124872.3-124886.6" wire width 14 $0\SHIFT_ROT__fn_unit[13:0] attribute \src "libresoc.v:124859.3-124871.6" wire width 7 $0\SHIFT_ROT__insn_type[6:0] attribute \src "libresoc.v:124844.3-124858.6" wire $0\SHIFT_ROT__write_cr0[0:0] attribute \src "libresoc.v:124361.7-124361.20" wire $0\initial[0:0] attribute \src "libresoc.v:124872.3-124886.6" wire width 14 $1\SHIFT_ROT__fn_unit[13:0] attribute \src "libresoc.v:124859.3-124871.6" wire width 7 $1\SHIFT_ROT__insn_type[6:0] attribute \src "libresoc.v:124844.3-124858.6" wire $1\SHIFT_ROT__write_cr0[0:0] attribute \src "libresoc.v:124769.18-124769.113" wire $and$libresoc.v:124769$4709_Y attribute \src "libresoc.v:124771.18-124771.110" wire $and$libresoc.v:124771$4711_Y attribute \src "libresoc.v:124784.18-124784.114" wire $and$libresoc.v:124784$4724_Y attribute \src "libresoc.v:124785.18-124785.116" wire $and$libresoc.v:124785$4725_Y attribute \src "libresoc.v:124787.18-124787.114" wire $and$libresoc.v:124787$4727_Y attribute \src "libresoc.v:124789.18-124789.110" wire $and$libresoc.v:124789$4729_Y attribute \src "libresoc.v:124790.17-124790.112" wire $and$libresoc.v:124790$4730_Y attribute \src "libresoc.v:124791.17-124791.114" wire $and$libresoc.v:124791$4731_Y attribute \src "libresoc.v:124772.18-124772.132" wire $eq$libresoc.v:124772$4712_Y attribute \src "libresoc.v:124773.18-124773.132" wire $eq$libresoc.v:124773$4713_Y attribute \src "libresoc.v:124775.18-124775.110" wire $eq$libresoc.v:124775$4715_Y attribute \src "libresoc.v:124776.18-124776.110" wire $eq$libresoc.v:124776$4716_Y attribute \src "libresoc.v:124778.18-124778.112" wire $eq$libresoc.v:124778$4718_Y attribute \src "libresoc.v:124779.17-124779.136" wire $eq$libresoc.v:124779$4719_Y attribute \src "libresoc.v:124781.18-124781.110" wire $eq$libresoc.v:124781$4721_Y attribute \src "libresoc.v:124783.18-124783.137" wire $eq$libresoc.v:124783$4723_Y attribute \src "libresoc.v:124786.18-124786.137" wire $eq$libresoc.v:124786$4726_Y attribute \src "libresoc.v:124792.17-124792.136" wire $eq$libresoc.v:124792$4732_Y attribute \src "libresoc.v:124770.18-124770.110" wire $not$libresoc.v:124770$4710_Y attribute \src "libresoc.v:124788.18-124788.110" wire $not$libresoc.v:124788$4728_Y attribute \src "libresoc.v:124774.18-124774.110" wire $or$libresoc.v:124774$4714_Y attribute \src "libresoc.v:124777.18-124777.110" wire $or$libresoc.v:124777$4717_Y attribute \src "libresoc.v:124780.18-124780.110" wire $or$libresoc.v:124780$4720_Y attribute \src "libresoc.v:124782.18-124782.110" wire $or$libresoc.v:124782$4722_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 3 \SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 4 \SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 5 \SHIFT_ROT__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 12 \SHIFT_ROT__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \SHIFT_ROT__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 18 \SHIFT_ROT__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \SHIFT_ROT__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \SHIFT_ROT__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \SHIFT_ROT__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 17 \SHIFT_ROT__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \SHIFT_ROT__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \SHIFT_ROT__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \SHIFT_ROT__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \SHIFT_ROT__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 7 \SHIFT_ROT__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 6 \SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \SHIFT_ROT__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_SHIFT_ROT_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 \dec_SHIFT_ROT_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 \dec_SHIFT_ROT_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SHIFT_ROT_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SHIFT_ROT_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 \dec_SHIFT_ROT_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_SHIFT_ROT_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SHIFT_ROT_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 \dec_SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SHIFT_ROT_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_cry_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 4 \dec_SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_SHIFT_ROT_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SHIFT_ROT_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SHIFT_ROT_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 \dec_SHIFT_ROT_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 \dec_bi_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:124361.7-124361.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 19 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124769$4709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:124769$4709_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124771$4711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:124771$4711_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124784$4724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:124784$4724_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124785$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:124785$4725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124787$4727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:124787$4727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:124789$4729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:124789$4729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124790$4730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:124790$4730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:124791$4731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:124791$4731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:124772$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:124772$4712_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:124773$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:124773$4713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:124775$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:124775$4715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:124776$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:124776$4716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:124778$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:124778$4718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:124779$4719 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:124779$4719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:124781$4721 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:124781$4721_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:124783$4723 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:124783$4723_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:124786$4726 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:124786$4726_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:124792$4732 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:124792$4732_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:124770$4710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:124770$4710_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:124788$4728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:124788$4728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:124774$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:124774$4714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:124777$4717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:124777$4717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:124780$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:124780$4720_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:124782$4722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:124782$4722_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:124793.13-124818.4" cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI connect \SHIFT_ROT_SPR \dec_SHIFT_ROT_SPR connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:124819.16-124830.4" cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh connect \imm_b \dec_bi_imm_b connect \imm_b_ok \dec_bi_imm_b_ok connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:124831.16-124837.4" cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op connect \oe \dec_oe_oe connect \oe_ok \dec_oe_oe_ok connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:124838.16-124843.4" cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:124361.7-124361.20" process $proc$libresoc.v:124361$4736 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:124844.3-124858.6" process $proc$libresoc.v:124844$4733 assign { } { } assign { } { } assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] attribute \src "libresoc.v:124845.5-124845.29" switch \initial attribute \src "libresoc.v:124845.9-124845.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" switch \dec_SHIFT_ROT_cr_out attribute \src "libresoc.v:0.0-0.0" case 3'001 , 3'101 assign { } { } assign $1\SHIFT_ROT__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" case 3'010 , 3'011 assign { } { } assign $1\SHIFT_ROT__write_cr0[0:0] 1'1 case assign $1\SHIFT_ROT__write_cr0[0:0] 1'0 end sync always update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end attribute \src "libresoc.v:124859.3-124871.6" process $proc$libresoc.v:124859$4734 assign { } { } assign { } { } assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] attribute \src "libresoc.v:124860.5-124860.29" switch \initial attribute \src "libresoc.v:124860.9-124860.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 case assign $1\SHIFT_ROT__insn_type[6:0] \dec_SHIFT_ROT_internal_op end sync always update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end attribute \src "libresoc.v:124872.3-124886.6" process $proc$libresoc.v:124872$4735 assign { } { } assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] attribute \src "libresoc.v:124873.5-124873.29" switch \initial attribute \src "libresoc.v:124873.9-124873.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\SHIFT_ROT__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\SHIFT_ROT__fn_unit[13:0] \dec_SHIFT_ROT_function_unit end sync always update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] end connect \$10 $and$libresoc.v:124769$4709_Y connect \$12 $not$libresoc.v:124770$4710_Y connect \$14 $and$libresoc.v:124771$4711_Y connect \$16 $eq$libresoc.v:124772$4712_Y connect \$18 $eq$libresoc.v:124773$4713_Y connect \$20 $or$libresoc.v:124774$4714_Y connect \$22 $eq$libresoc.v:124775$4715_Y connect \$24 $eq$libresoc.v:124776$4716_Y connect \$26 $or$libresoc.v:124777$4717_Y connect \$28 $eq$libresoc.v:124778$4718_Y connect \$2 $eq$libresoc.v:124779$4719_Y connect \$30 $or$libresoc.v:124780$4720_Y connect \$32 $eq$libresoc.v:124781$4721_Y connect \$34 $or$libresoc.v:124782$4722_Y connect \$36 $eq$libresoc.v:124783$4723_Y connect \$38 $and$libresoc.v:124784$4724_Y connect \$40 $and$libresoc.v:124785$4725_Y connect \$42 $eq$libresoc.v:124786$4726_Y connect \$44 $and$libresoc.v:124787$4727_Y connect \$46 $not$libresoc.v:124788$4728_Y connect \$48 $and$libresoc.v:124789$4729_Y connect \$4 $and$libresoc.v:124790$4730_Y connect \$6 $and$libresoc.v:124791$4731_Y connect \$8 $eq$libresoc.v:124792$4732_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_SHIFT_ROT_SPR [4:0] \dec_SHIFT_ROT_SPR [9:5] } connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end attribute \src "libresoc.v:124910.1-125288.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR attribute \src "libresoc.v:125264.3-125278.6" wire width 14 $0\SPR__fn_unit[13:0] attribute \src "libresoc.v:125251.3-125263.6" wire width 7 $0\SPR__insn_type[6:0] attribute \src "libresoc.v:124911.7-124911.20" wire $0\initial[0:0] attribute \src "libresoc.v:125264.3-125278.6" wire width 14 $1\SPR__fn_unit[13:0] attribute \src "libresoc.v:125251.3-125263.6" wire width 7 $1\SPR__insn_type[6:0] attribute \src "libresoc.v:125205.18-125205.113" wire $and$libresoc.v:125205$4737_Y attribute \src "libresoc.v:125207.18-125207.110" wire $and$libresoc.v:125207$4739_Y attribute \src "libresoc.v:125220.18-125220.114" wire $and$libresoc.v:125220$4752_Y attribute \src "libresoc.v:125221.18-125221.116" wire $and$libresoc.v:125221$4753_Y attribute \src "libresoc.v:125223.18-125223.114" wire $and$libresoc.v:125223$4755_Y attribute \src "libresoc.v:125225.18-125225.110" wire $and$libresoc.v:125225$4757_Y attribute \src "libresoc.v:125226.17-125226.112" wire $and$libresoc.v:125226$4758_Y attribute \src "libresoc.v:125227.17-125227.114" wire $and$libresoc.v:125227$4759_Y attribute \src "libresoc.v:125208.18-125208.126" wire $eq$libresoc.v:125208$4740_Y attribute \src "libresoc.v:125209.18-125209.126" wire $eq$libresoc.v:125209$4741_Y attribute \src "libresoc.v:125211.18-125211.110" wire $eq$libresoc.v:125211$4743_Y attribute \src "libresoc.v:125212.18-125212.110" wire $eq$libresoc.v:125212$4744_Y attribute \src "libresoc.v:125214.18-125214.112" wire $eq$libresoc.v:125214$4746_Y attribute \src "libresoc.v:125215.17-125215.130" wire $eq$libresoc.v:125215$4747_Y attribute \src "libresoc.v:125217.18-125217.110" wire $eq$libresoc.v:125217$4749_Y attribute \src "libresoc.v:125219.18-125219.131" wire $eq$libresoc.v:125219$4751_Y attribute \src "libresoc.v:125222.18-125222.131" wire $eq$libresoc.v:125222$4754_Y attribute \src "libresoc.v:125228.17-125228.130" wire $eq$libresoc.v:125228$4760_Y attribute \src "libresoc.v:125206.18-125206.110" wire $not$libresoc.v:125206$4738_Y attribute \src "libresoc.v:125224.18-125224.110" wire $not$libresoc.v:125224$4756_Y attribute \src "libresoc.v:125210.18-125210.110" wire $or$libresoc.v:125210$4742_Y attribute \src "libresoc.v:125213.18-125213.110" wire $or$libresoc.v:125213$4745_Y attribute \src "libresoc.v:125216.18-125216.110" wire $or$libresoc.v:125216$4748_Y attribute \src "libresoc.v:125218.18-125218.110" wire $or$libresoc.v:125218$4750_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 3 \SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 4 \SPR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 2 \SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 5 \SPR__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SPR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire \dec_SPR_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 \dec_SPR_SPR attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 3 \dec_SPR_cr_out attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 14 \dec_SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 \dec_SPR_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" wire \dec_SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 \dec_SPR_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 \dec_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 \dec_rc_sel_in attribute \src "libresoc.v:124911.7-124911.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" wire width 32 \insn_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 32 \insn_in$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" wire \is_mmu_spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 6 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:125205$4737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 connect \Y $and$libresoc.v:125205$4737_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:125207$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 connect \Y $and$libresoc.v:125207$4739_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:125220$4752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 connect \Y $and$libresoc.v:125220$4752_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:125221$4753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr connect \Y $and$libresoc.v:125221$4753_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:125223$4755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 connect \Y $and$libresoc.v:125223$4755_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $and $and$libresoc.v:125225$4757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:125225$4757_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:125226$4758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 connect \Y $and$libresoc.v:125226$4758_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $and $and$libresoc.v:125227$4759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr connect \Y $and$libresoc.v:125227$4759_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" cell $eq $eq$libresoc.v:125208$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:125208$4740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $eq $eq$libresoc.v:125209$4741 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 connect \Y $eq$libresoc.v:125209$4741_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:125211$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 connect \Y $eq$libresoc.v:125211$4743_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:125212$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 connect \Y $eq$libresoc.v:125212$4744_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $eq $eq$libresoc.v:125214$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 connect \Y $eq$libresoc.v:125214$4746_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:125215$4747 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:125215$4747_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $eq $eq$libresoc.v:125217$4749 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 connect \Y $eq$libresoc.v:125217$4749_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" cell $eq $eq$libresoc.v:125219$4751 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 connect \Y $eq$libresoc.v:125219$4751_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:125222$4754 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:125222$4754_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $eq $eq$libresoc.v:125228$4760 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 14 parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 connect \Y $eq$libresoc.v:125228$4760_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:125206$4738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:125206$4738_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" cell $not $not$libresoc.v:125224$4756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr connect \Y $not$libresoc.v:125224$4756_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" cell $or $or$libresoc.v:125210$4742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 connect \Y $or$libresoc.v:125210$4742_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:125213$4745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 connect \Y $or$libresoc.v:125213$4745_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" cell $or $or$libresoc.v:125216$4748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 connect \Y $or$libresoc.v:125216$4748_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" cell $or $or$libresoc.v:125218$4750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:125218$4750_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:125229.13-125241.4" cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc connect \SPR_SPR \dec_SPR_SPR connect \SPR_cr_out \dec_SPR_cr_out connect \SPR_function_unit \dec_SPR_function_unit connect \SPR_internal_op \dec_SPR_internal_op connect \SPR_is_32b \dec_SPR_is_32b connect \SPR_rc_sel \dec_SPR_rc_sel connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 attribute \src "libresoc.v:125242.16-125246.4" cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 attribute \src "libresoc.v:125247.16-125250.4" cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \sel_in \dec_rc_sel_in end attribute \src "libresoc.v:124911.7-124911.20" process $proc$libresoc.v:124911$4763 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:125251.3-125263.6" process $proc$libresoc.v:125251$4761 assign { } { } assign { } { } assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] attribute \src "libresoc.v:125252.5-125252.29" switch \initial attribute \src "libresoc.v:125252.9-125252.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\SPR__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\SPR__insn_type[6:0] 7'0000000 case assign $1\SPR__insn_type[6:0] \dec_SPR_internal_op end sync always update \SPR__insn_type $0\SPR__insn_type[6:0] end attribute \src "libresoc.v:125264.3-125278.6" process $proc$libresoc.v:125264$4762 assign { } { } assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] attribute \src "libresoc.v:125265.5-125265.29" switch \initial attribute \src "libresoc.v:125265.9-125265.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\SPR__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\SPR__fn_unit[13:0] 14'00000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\SPR__fn_unit[13:0] \dec_SPR_function_unit end sync always update \SPR__fn_unit $0\SPR__fn_unit[13:0] end connect \$10 $and$libresoc.v:125205$4737_Y connect \$12 $not$libresoc.v:125206$4738_Y connect \$14 $and$libresoc.v:125207$4739_Y connect \$16 $eq$libresoc.v:125208$4740_Y connect \$18 $eq$libresoc.v:125209$4741_Y connect \$20 $or$libresoc.v:125210$4742_Y connect \$22 $eq$libresoc.v:125211$4743_Y connect \$24 $eq$libresoc.v:125212$4744_Y connect \$26 $or$libresoc.v:125213$4745_Y connect \$28 $eq$libresoc.v:125214$4746_Y connect \$2 $eq$libresoc.v:125215$4747_Y connect \$30 $or$libresoc.v:125216$4748_Y connect \$32 $eq$libresoc.v:125217$4749_Y connect \$34 $or$libresoc.v:125218$4750_Y connect \$36 $eq$libresoc.v:125219$4751_Y connect \$38 $and$libresoc.v:125220$4752_Y connect \$40 $and$libresoc.v:125221$4753_Y connect \$42 $eq$libresoc.v:125222$4754_Y connect \$44 $and$libresoc.v:125223$4755_Y connect \$46 $not$libresoc.v:125224$4756_Y connect \$48 $and$libresoc.v:125225$4757_Y connect \$4 $and$libresoc.v:125226$4758_Y connect \$6 $and$libresoc.v:125227$4759_Y connect \$8 $eq$libresoc.v:125228$4760_Y connect \SPR__is_32bit \dec_SPR_is_32b connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_SPR_SPR [4:0] \dec_SPR_SPR [9:5] } connect \dec_oe_sel_in \dec_SPR_rc_sel connect \dec_rc_sel_in \dec_SPR_rc_sel connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end attribute \src "libresoc.v:125292.1-125845.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $0\fast_a[2:0] attribute \src "libresoc.v:125749.3-125784.6" wire $0\fast_a_ok[0:0] attribute \src "libresoc.v:125293.7-125293.20" wire $0\initial[0:0] attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $0\reg_a[4:0] attribute \src "libresoc.v:125733.3-125748.6" wire $0\reg_a_ok[0:0] attribute \src "libresoc.v:125785.3-125803.6" wire width 10 $0\spr[9:0] attribute \src "libresoc.v:125823.3-125842.6" wire width 10 $0\spr_a[9:0] attribute \src "libresoc.v:125823.3-125842.6" wire $0\spr_a_ok[0:0] attribute \src "libresoc.v:125804.3-125822.6" wire width 10 $0\sprmap_spr_i[9:0] attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $1\fast_a[2:0] attribute \src "libresoc.v:125749.3-125784.6" wire $1\fast_a_ok[0:0] attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $1\reg_a[4:0] attribute \src "libresoc.v:125733.3-125748.6" wire $1\reg_a_ok[0:0] attribute \src "libresoc.v:125785.3-125803.6" wire width 10 $1\spr[9:0] attribute \src "libresoc.v:125823.3-125842.6" wire width 10 $1\spr_a[9:0] attribute \src "libresoc.v:125823.3-125842.6" wire $1\spr_a_ok[0:0] attribute \src "libresoc.v:125804.3-125822.6" wire width 10 $1\sprmap_spr_i[9:0] attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $2\fast_a[2:0] attribute \src "libresoc.v:125749.3-125784.6" wire $2\fast_a_ok[0:0] attribute \src "libresoc.v:125717.3-125732.6" wire width 5 $2\reg_a[4:0] attribute \src "libresoc.v:125733.3-125748.6" wire $2\reg_a_ok[0:0] attribute \src "libresoc.v:125749.3-125784.6" wire width 3 $3\fast_a[2:0] attribute \src "libresoc.v:125749.3-125784.6" wire $3\fast_a_ok[0:0] attribute \src "libresoc.v:125692.18-125692.108" wire $and$libresoc.v:125692$4765_Y attribute \src "libresoc.v:125701.18-125701.110" wire $and$libresoc.v:125701$4774_Y attribute \src "libresoc.v:125706.18-125706.113" wire $and$libresoc.v:125706$4779_Y attribute \src "libresoc.v:125694.18-125694.112" wire $eq$libresoc.v:125694$4767_Y attribute \src "libresoc.v:125695.18-125695.112" wire $eq$libresoc.v:125695$4768_Y attribute \src "libresoc.v:125696.17-125696.111" wire $eq$libresoc.v:125696$4769_Y attribute \src "libresoc.v:125697.18-125697.112" wire $eq$libresoc.v:125697$4770_Y attribute \src "libresoc.v:125703.18-125703.112" wire $eq$libresoc.v:125703$4776_Y attribute \src "libresoc.v:125707.17-125707.111" wire $eq$libresoc.v:125707$4780_Y attribute \src "libresoc.v:125698.18-125698.109" wire $ne$libresoc.v:125698$4771_Y attribute \src "libresoc.v:125699.18-125699.111" wire $ne$libresoc.v:125699$4772_Y attribute \src "libresoc.v:125708.17-125708.108" wire $ne$libresoc.v:125708$4781_Y attribute \src "libresoc.v:125709.17-125709.110" wire $ne$libresoc.v:125709$4782_Y attribute \src "libresoc.v:125704.18-125704.105" wire $not$libresoc.v:125704$4777_Y attribute \src "libresoc.v:125705.18-125705.108" wire $not$libresoc.v:125705$4778_Y attribute \src "libresoc.v:125691.17-125691.107" wire $or$libresoc.v:125691$4764_Y attribute \src "libresoc.v:125693.18-125693.109" wire $or$libresoc.v:125693$4766_Y attribute \src "libresoc.v:125700.18-125700.110" wire $or$libresoc.v:125700$4773_Y attribute \src "libresoc.v:125702.18-125702.110" wire $or$libresoc.v:125702$4775_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 10 \RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 input 1 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 13 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 8 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 9 \fast_a_ok attribute \src "libresoc.v:125293.7-125293.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 14 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" wire width 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 4 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \reg_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" wire width 5 \rs attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire width 3 input 3 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute 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\enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 6 \spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \spr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_fast_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" wire input 2 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $and $and$libresoc.v:125692$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$9 connect \Y $and$libresoc.v:125692$4765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $and $and$libresoc.v:125701$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$19 connect \B \$25 connect \Y $and$libresoc.v:125701$4774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" cell $and $and$libresoc.v:125706$4779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$35 connect \Y $and$libresoc.v:125706$4779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" cell $eq $eq$libresoc.v:125694$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 connect \Y $eq$libresoc.v:125694$4767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" cell $eq $eq$libresoc.v:125695$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 connect \Y $eq$libresoc.v:125695$4768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" cell $eq $eq$libresoc.v:125696$4769 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 connect \Y $eq$libresoc.v:125696$4769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" cell $eq $eq$libresoc.v:125697$4770 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 connect \Y $eq$libresoc.v:125697$4770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" cell $eq $eq$libresoc.v:125703$4776 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 connect \Y $eq$libresoc.v:125703$4776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" cell $eq $eq$libresoc.v:125707$4780 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 connect \Y $eq$libresoc.v:125707$4780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $ne $ne$libresoc.v:125698$4771 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 connect \Y $ne$libresoc.v:125698$4771_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $ne $ne$libresoc.v:125699$4772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 connect \Y $ne$libresoc.v:125699$4772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $ne $ne$libresoc.v:125708$4781 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 connect \Y $ne$libresoc.v:125708$4781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $ne $ne$libresoc.v:125709$4782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 connect \Y $ne$libresoc.v:125709$4782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" cell $not $not$libresoc.v:125704$4777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] connect \Y $not$libresoc.v:125704$4777_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" cell $not $not$libresoc.v:125705$4778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] connect \Y $not$libresoc.v:125705$4778_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $or $or$libresoc.v:125691$4764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 connect \Y $or$libresoc.v:125691$4764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $or $or$libresoc.v:125693$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$11 connect \Y $or$libresoc.v:125693$4766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $or $or$libresoc.v:125700$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \$23 connect \Y $or$libresoc.v:125700$4773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" cell $or $or$libresoc.v:125702$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \$27 connect \Y $or$libresoc.v:125702$4775_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:125710.10-125716.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok connect \spr_i \sprmap_spr_i connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end attribute \src "libresoc.v:125293.7-125293.20" process $proc$libresoc.v:125293$4789 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:125717.3-125732.6" process $proc$libresoc.v:125717$4783 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] attribute \src "libresoc.v:125718.5-125718.29" switch \initial attribute \src "libresoc.v:125718.9-125718.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg_a[4:0] \ra case assign $1\reg_a[4:0] 5'00000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg_a[4:0] \rs case assign $2\reg_a[4:0] $1\reg_a[4:0] end sync always update \reg_a $0\reg_a[4:0] end attribute \src "libresoc.v:125733.3-125748.6" process $proc$libresoc.v:125733$4784 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] attribute \src "libresoc.v:125734.5-125734.29" switch \initial attribute \src "libresoc.v:125734.9-125734.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg_a_ok[0:0] 1'1 case assign $1\reg_a_ok[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg_a_ok[0:0] 1'1 case assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] end sync always update \reg_a_ok $0\reg_a_ok[0:0] end attribute \src "libresoc.v:125749.3-125784.6" process $proc$libresoc.v:125749$4785 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] attribute \src "libresoc.v:125750.5-125750.29" switch \initial attribute \src "libresoc.v:125750.9-125750.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign { } { } assign { } { } assign $1\fast_a[2:0] $2\fast_a[2:0] assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $2\fast_a[2:0] 3'000 assign $2\fast_a_ok[0:0] 1'1 case assign $2\fast_a[2:0] 3'000 assign $2\fast_a_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'0001000 assign { } { } assign { } { } assign $1\fast_a[2:0] $3\fast_a[2:0] assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $3\fast_a[2:0] 3'000 assign $3\fast_a_ok[0:0] 1'1 case assign $3\fast_a[2:0] 3'000 assign $3\fast_a_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign { } { } assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } case assign $1\fast_a[2:0] 3'000 assign $1\fast_a_ok[0:0] 1'0 end sync always update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end attribute \src "libresoc.v:125785.3-125803.6" process $proc$libresoc.v:125785$4786 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] attribute \src "libresoc.v:125786.5-125786.29" switch \initial attribute \src "libresoc.v:125786.9-125786.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign $1\spr[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001000 assign $1\spr[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case assign $1\spr[9:0] 10'0000000000 end sync always update \spr $0\spr[9:0] end attribute \src "libresoc.v:125804.3-125822.6" process $proc$libresoc.v:125804$4787 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] attribute \src "libresoc.v:125805.5-125805.29" switch \initial attribute \src "libresoc.v:125805.9-125805.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign $1\sprmap_spr_i[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001000 assign $1\sprmap_spr_i[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign $1\sprmap_spr_i[9:0] \spr case assign $1\sprmap_spr_i[9:0] 10'0000000000 end sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end attribute \src "libresoc.v:125823.3-125842.6" process $proc$libresoc.v:125823$4788 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] attribute \src "libresoc.v:125824.5-125824.29" switch \initial attribute \src "libresoc.v:125824.9-125824.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign $1\spr_a[9:0] 10'0000000000 assign $1\spr_a_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0001000 assign $1\spr_a[9:0] 10'0000000000 assign $1\spr_a_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign { } { } assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } case assign $1\spr_a[9:0] 10'0000000000 assign $1\spr_a_ok[0:0] 1'0 end sync always update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end connect \$9 $or$libresoc.v:125691$4764_Y connect \$11 $and$libresoc.v:125692$4765_Y connect \$13 $or$libresoc.v:125693$4766_Y connect \$15 $eq$libresoc.v:125694$4767_Y connect \$17 $eq$libresoc.v:125695$4768_Y connect \$1 $eq$libresoc.v:125696$4769_Y connect \$19 $eq$libresoc.v:125697$4770_Y connect \$21 $ne$libresoc.v:125698$4771_Y connect \$23 $ne$libresoc.v:125699$4772_Y connect \$25 $or$libresoc.v:125700$4773_Y connect \$27 $and$libresoc.v:125701$4774_Y connect \$29 $or$libresoc.v:125702$4775_Y connect \$31 $eq$libresoc.v:125703$4776_Y connect \$33 $not$libresoc.v:125704$4777_Y connect \$35 $not$libresoc.v:125705$4778_Y connect \$37 $and$libresoc.v:125706$4779_Y connect \$3 $eq$libresoc.v:125707$4780_Y connect \$5 $ne$libresoc.v:125708$4781_Y connect \$7 $ne$libresoc.v:125709$4782_Y connect \rs \RS connect \ra \RA end attribute \src "libresoc.v:125849.1-125894.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai attribute \src "libresoc.v:125883.3-125892.6" wire $0\immz_out[0:0] attribute \src "libresoc.v:125850.7-125850.20" wire $0\initial[0:0] attribute \src "libresoc.v:125883.3-125892.6" wire $1\immz_out[0:0] attribute \src "libresoc.v:125878.17-125878.107" wire $and$libresoc.v:125878$4790_Y attribute \src "libresoc.v:125881.17-125881.107" wire $and$libresoc.v:125881$4793_Y attribute \src "libresoc.v:125879.17-125879.111" wire $eq$libresoc.v:125879$4791_Y attribute \src "libresoc.v:125880.17-125880.108" wire $eq$libresoc.v:125880$4792_Y attribute \src "libresoc.v:125882.17-125882.110" wire $eq$libresoc.v:125882$4794_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \ALU_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out attribute \src "libresoc.v:125850.7-125850.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $and $and$libresoc.v:125878$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 connect \Y $and$libresoc.v:125878$4790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $and $and$libresoc.v:125881$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 connect \Y $and$libresoc.v:125881$4793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:125879$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 connect \Y $eq$libresoc.v:125879$4791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:125880$4792 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 connect \Y $eq$libresoc.v:125880$4792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $eq $eq$libresoc.v:125882$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 connect \Y $eq$libresoc.v:125882$4794_Y end attribute \src "libresoc.v:125850.7-125850.20" process $proc$libresoc.v:125850$4796 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:125883.3-125892.6" process $proc$libresoc.v:125883$4795 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] attribute \src "libresoc.v:125884.5-125884.29" switch \initial attribute \src "libresoc.v:125884.9-125884.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\immz_out[0:0] 1'1 case assign $1\immz_out[0:0] 1'0 end sync always update \immz_out $0\immz_out[0:0] end connect \$9 $and$libresoc.v:125878$4790_Y connect \$1 $eq$libresoc.v:125879$4791_Y connect \$3 $eq$libresoc.v:125880$4792_Y connect \$5 $and$libresoc.v:125881$4793_Y connect \$7 $eq$libresoc.v:125882$4794_Y connect \ra \ALU_RA end attribute \src "libresoc.v:125898.1-125943.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" module \dec_ai$148 attribute \src "libresoc.v:125932.3-125941.6" wire $0\immz_out[0:0] attribute \src "libresoc.v:125899.7-125899.20" wire $0\initial[0:0] attribute \src "libresoc.v:125932.3-125941.6" wire $1\immz_out[0:0] attribute \src "libresoc.v:125927.17-125927.107" wire $and$libresoc.v:125927$4797_Y attribute \src "libresoc.v:125930.17-125930.107" wire $and$libresoc.v:125930$4800_Y attribute \src "libresoc.v:125928.17-125928.111" wire $eq$libresoc.v:125928$4798_Y attribute \src "libresoc.v:125929.17-125929.108" wire $eq$libresoc.v:125929$4799_Y attribute \src "libresoc.v:125931.17-125931.110" wire $eq$libresoc.v:125931$4801_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LOGICAL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out attribute \src "libresoc.v:125899.7-125899.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $and $and$libresoc.v:125927$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 connect \Y $and$libresoc.v:125927$4797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $and $and$libresoc.v:125930$4800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 connect \Y $and$libresoc.v:125930$4800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:125928$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 connect \Y $eq$libresoc.v:125928$4798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:125929$4799 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 connect \Y $eq$libresoc.v:125929$4799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $eq $eq$libresoc.v:125931$4801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 connect \Y $eq$libresoc.v:125931$4801_Y end attribute \src "libresoc.v:125899.7-125899.20" process $proc$libresoc.v:125899$4803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:125932.3-125941.6" process $proc$libresoc.v:125932$4802 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] attribute \src "libresoc.v:125933.5-125933.29" switch \initial attribute \src "libresoc.v:125933.9-125933.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\immz_out[0:0] 1'1 case assign $1\immz_out[0:0] 1'0 end sync always update \immz_out $0\immz_out[0:0] end connect \$9 $and$libresoc.v:125927$4797_Y connect \$1 $eq$libresoc.v:125928$4798_Y connect \$3 $eq$libresoc.v:125929$4799_Y connect \$5 $and$libresoc.v:125930$4800_Y connect \$7 $eq$libresoc.v:125931$4801_Y connect \ra \LOGICAL_RA end attribute \src "libresoc.v:125947.1-125992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" module \dec_ai$156 attribute \src "libresoc.v:125981.3-125990.6" wire $0\immz_out[0:0] attribute \src "libresoc.v:125948.7-125948.20" wire $0\initial[0:0] attribute \src "libresoc.v:125981.3-125990.6" wire $1\immz_out[0:0] attribute \src "libresoc.v:125976.17-125976.107" wire $and$libresoc.v:125976$4804_Y attribute \src "libresoc.v:125979.17-125979.107" wire $and$libresoc.v:125979$4807_Y attribute \src "libresoc.v:125977.17-125977.111" wire $eq$libresoc.v:125977$4805_Y attribute \src "libresoc.v:125978.17-125978.108" wire $eq$libresoc.v:125978$4806_Y attribute \src "libresoc.v:125980.17-125980.110" wire $eq$libresoc.v:125980$4808_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \DIV_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out attribute \src "libresoc.v:125948.7-125948.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $and $and$libresoc.v:125976$4804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 connect \Y $and$libresoc.v:125976$4804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $and $and$libresoc.v:125979$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 connect \Y $and$libresoc.v:125979$4807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:125977$4805 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 connect \Y $eq$libresoc.v:125977$4805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:125978$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 connect \Y $eq$libresoc.v:125978$4806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $eq $eq$libresoc.v:125980$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 connect \Y $eq$libresoc.v:125980$4808_Y end attribute \src "libresoc.v:125948.7-125948.20" process $proc$libresoc.v:125948$4810 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:125981.3-125990.6" process $proc$libresoc.v:125981$4809 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] attribute \src "libresoc.v:125982.5-125982.29" switch \initial attribute \src "libresoc.v:125982.9-125982.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\immz_out[0:0] 1'1 case assign $1\immz_out[0:0] 1'0 end sync always update \immz_out $0\immz_out[0:0] end connect \$9 $and$libresoc.v:125976$4804_Y connect \$1 $eq$libresoc.v:125977$4805_Y connect \$3 $eq$libresoc.v:125978$4806_Y connect \$5 $and$libresoc.v:125979$4807_Y connect \$7 $eq$libresoc.v:125980$4808_Y connect \ra \DIV_RA end attribute \src "libresoc.v:125996.1-126041.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" module \dec_ai$169 attribute \src "libresoc.v:126030.3-126039.6" wire $0\immz_out[0:0] attribute \src "libresoc.v:125997.7-125997.20" wire $0\initial[0:0] attribute \src "libresoc.v:126030.3-126039.6" wire $1\immz_out[0:0] attribute \src "libresoc.v:126025.17-126025.107" wire $and$libresoc.v:126025$4811_Y attribute \src "libresoc.v:126028.17-126028.107" wire $and$libresoc.v:126028$4814_Y attribute \src "libresoc.v:126026.17-126026.111" wire $eq$libresoc.v:126026$4812_Y attribute \src "libresoc.v:126027.17-126027.108" wire $eq$libresoc.v:126027$4813_Y attribute \src "libresoc.v:126029.17-126029.110" wire $eq$libresoc.v:126029$4815_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \LDST_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" wire output 2 \immz_out attribute \src "libresoc.v:125997.7-125997.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" wire width 3 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $and $and$libresoc.v:126025$4811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 connect \Y $and$libresoc.v:126025$4811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $and $and$libresoc.v:126028$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 connect \Y $and$libresoc.v:126028$4814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:126026$4812 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 connect \Y $eq$libresoc.v:126026$4812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" cell $eq $eq$libresoc.v:126027$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 connect \Y $eq$libresoc.v:126027$4813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" cell $eq $eq$libresoc.v:126029$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 connect \Y $eq$libresoc.v:126029$4815_Y end attribute \src "libresoc.v:125997.7-125997.20" process $proc$libresoc.v:125997$4817 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:126030.3-126039.6" process $proc$libresoc.v:126030$4816 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] attribute \src "libresoc.v:126031.5-126031.29" switch \initial attribute \src "libresoc.v:126031.9-126031.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\immz_out[0:0] 1'1 case assign $1\immz_out[0:0] 1'0 end sync always update \immz_out $0\immz_out[0:0] end connect \$9 $and$libresoc.v:126025$4811_Y connect \$1 $eq$libresoc.v:126026$4812_Y connect \$3 $eq$libresoc.v:126027$4813_Y connect \$5 $and$libresoc.v:126028$4814_Y connect \$7 $eq$libresoc.v:126029$4815_Y connect \ra \LDST_RA end attribute \src "libresoc.v:126045.1-126243.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $0\fast_b[2:0] attribute \src "libresoc.v:126225.3-126242.6" wire $0\fast_b_ok[0:0] attribute \src "libresoc.v:126046.7-126046.20" wire $0\initial[0:0] attribute \src "libresoc.v:126177.3-126191.6" wire width 7 $0\reg_b[6:0] attribute \src "libresoc.v:126192.3-126206.6" wire $0\reg_b_ok[0:0] attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $1\fast_b[2:0] attribute \src "libresoc.v:126225.3-126242.6" wire $1\fast_b_ok[0:0] attribute \src "libresoc.v:126177.3-126191.6" wire width 7 $1\reg_b[6:0] attribute \src "libresoc.v:126192.3-126206.6" wire $1\reg_b_ok[0:0] attribute \src "libresoc.v:126207.3-126224.6" wire width 3 $2\fast_b[2:0] attribute \src "libresoc.v:126225.3-126242.6" wire $2\fast_b_ok[0:0] attribute \src "libresoc.v:126171.17-126171.117" wire $eq$libresoc.v:126171$4818_Y attribute \src "libresoc.v:126175.17-126175.117" wire $eq$libresoc.v:126175$4824_Y attribute \src "libresoc.v:126173.17-126173.100" wire width 7 $extend$libresoc.v:126173$4820_Y attribute \src "libresoc.v:126174.17-126174.100" wire width 7 $extend$libresoc.v:126174$4822_Y attribute \src "libresoc.v:126172.18-126172.108" wire $not$libresoc.v:126172$4819_Y attribute \src "libresoc.v:126176.17-126176.107" wire $not$libresoc.v:126176$4825_Y attribute \src "libresoc.v:126173.17-126173.100" wire width 7 $pos$libresoc.v:126173$4821_Y attribute \src "libresoc.v:126174.17-126174.100" wire width 7 $pos$libresoc.v:126174$4823_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 6 \RS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 10 input 8 \XL_XO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \fast_b_ok attribute \src "libresoc.v:126046.7-126046.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 9 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 output 2 \reg_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \reg_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" wire width 4 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" cell $eq $eq$libresoc.v:126171$4818 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 connect \Y $eq$libresoc.v:126171$4818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" cell $eq $eq$libresoc.v:126175$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 connect \Y $eq$libresoc.v:126175$4824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126173$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB connect \Y $extend$libresoc.v:126173$4820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126174$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS connect \Y $extend$libresoc.v:126174$4822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" cell $not $not$libresoc.v:126172$4819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \Y $not$libresoc.v:126172$4819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" cell $not $not$libresoc.v:126176$4825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \Y $not$libresoc.v:126176$4825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126173$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:126173$4820_Y connect \Y $pos$libresoc.v:126173$4821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126174$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:126174$4822_Y connect \Y $pos$libresoc.v:126174$4823_Y end attribute \src "libresoc.v:126046.7-126046.20" process $proc$libresoc.v:126046$4830 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:126177.3-126191.6" process $proc$libresoc.v:126177$4826 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] attribute \src "libresoc.v:126178.5-126178.29" switch \initial attribute \src "libresoc.v:126178.9-126178.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\reg_b[6:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'1101 assign { } { } assign $1\reg_b[6:0] \$3 case assign $1\reg_b[6:0] 7'0000000 end sync always update \reg_b $0\reg_b[6:0] end attribute \src "libresoc.v:126192.3-126206.6" process $proc$libresoc.v:126192$4827 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] attribute \src "libresoc.v:126193.5-126193.29" switch \initial attribute \src "libresoc.v:126193.9-126193.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $1\reg_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1101 assign { } { } assign $1\reg_b_ok[0:0] 1'1 case assign $1\reg_b_ok[0:0] 1'0 end sync always update \reg_b_ok $0\reg_b_ok[0:0] end attribute \src "libresoc.v:126207.3-126224.6" process $proc$libresoc.v:126207$4828 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] attribute \src "libresoc.v:126208.5-126208.29" switch \initial attribute \src "libresoc.v:126208.9-126208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b[2:0] $2\fast_b[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" switch { \XL_XO [5] \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\fast_b[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\fast_b[2:0] 3'010 case assign $2\fast_b[2:0] 3'000 end case assign $1\fast_b[2:0] 3'000 end sync always update \fast_b $0\fast_b[2:0] end attribute \src "libresoc.v:126225.3-126242.6" process $proc$libresoc.v:126225$4829 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] attribute \src "libresoc.v:126226.5-126226.29" switch \initial attribute \src "libresoc.v:126226.9-126226.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" switch { \XL_XO [5] \$11 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\fast_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\fast_b_ok[0:0] 1'1 case assign $2\fast_b_ok[0:0] 1'0 end case assign $1\fast_b_ok[0:0] 1'0 end sync always update \fast_b_ok $0\fast_b_ok[0:0] end connect \$9 $eq$libresoc.v:126171$4818_Y connect \$11 $not$libresoc.v:126172$4819_Y connect \$1 $pos$libresoc.v:126173$4821_Y connect \$3 $pos$libresoc.v:126174$4823_Y connect \$5 $eq$libresoc.v:126175$4824_Y connect \$7 $not$libresoc.v:126176$4825_Y end attribute \src "libresoc.v:126247.1-126584.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi attribute \src "libresoc.v:126514.3-126544.6" wire width 16 $0\bd[15:0] attribute \src "libresoc.v:126545.3-126579.6" wire width 16 $0\ds[15:0] attribute \src "libresoc.v:126336.3-126382.6" wire width 64 $0\imm_b[63:0] attribute \src "libresoc.v:126383.3-126429.6" wire $0\imm_b_ok[0:0] attribute \src "libresoc.v:126248.7-126248.20" wire $0\initial[0:0] attribute \src "libresoc.v:126487.3-126513.6" wire width 26 $0\li[25:0] attribute \src "libresoc.v:126430.3-126444.6" wire width 16 $0\si[15:0] attribute \src "libresoc.v:126445.3-126463.6" wire width 32 $0\si_hi[31:0] attribute \src "libresoc.v:126464.3-126486.6" wire width 16 $0\ui[15:0] attribute \src "libresoc.v:126514.3-126544.6" wire width 16 $1\bd[15:0] attribute \src "libresoc.v:126545.3-126579.6" wire width 16 $1\ds[15:0] attribute \src "libresoc.v:126336.3-126382.6" wire width 64 $1\imm_b[63:0] attribute \src "libresoc.v:126383.3-126429.6" wire $1\imm_b_ok[0:0] attribute \src "libresoc.v:126487.3-126513.6" wire width 26 $1\li[25:0] attribute \src "libresoc.v:126430.3-126444.6" wire width 16 $1\si[15:0] attribute \src "libresoc.v:126445.3-126463.6" wire width 32 $1\si_hi[31:0] attribute \src "libresoc.v:126464.3-126486.6" wire width 16 $1\ui[15:0] attribute \src "libresoc.v:126326.17-126326.104" wire width 64 $extend$libresoc.v:126326$4831_Y attribute \src "libresoc.v:126327.18-126327.107" wire width 64 $extend$libresoc.v:126327$4833_Y attribute \src "libresoc.v:126330.17-126330.104" wire width 64 $extend$libresoc.v:126330$4837_Y attribute \src "libresoc.v:126334.17-126334.102" wire width 64 $extend$libresoc.v:126334$4842_Y attribute \src "libresoc.v:126326.17-126326.104" wire width 64 $pos$libresoc.v:126326$4832_Y attribute \src "libresoc.v:126327.18-126327.107" wire width 64 $pos$libresoc.v:126327$4834_Y attribute \src "libresoc.v:126330.17-126330.104" wire width 64 $pos$libresoc.v:126330$4838_Y attribute \src "libresoc.v:126334.17-126334.102" wire width 64 $pos$libresoc.v:126334$4843_Y attribute \src "libresoc.v:126328.18-126328.114" wire width 47 $sshl$libresoc.v:126328$4835_Y attribute \src "libresoc.v:126329.18-126329.113" wire width 27 $sshl$libresoc.v:126329$4836_Y attribute \src "libresoc.v:126331.18-126331.113" wire width 17 $sshl$libresoc.v:126331$4839_Y attribute \src "libresoc.v:126332.18-126332.113" wire width 17 $sshl$libresoc.v:126332$4840_Y attribute \src "libresoc.v:126333.17-126333.109" wire width 47 $sshl$libresoc.v:126333$4841_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \ALU_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \ALU_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \ALU_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \ALU_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \ALU_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \ALU_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \ALU_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok attribute \src "libresoc.v:126248.7-126248.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126326$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh connect \Y $extend$libresoc.v:126326$4831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126327$4833 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 connect \Y $extend$libresoc.v:126327$4833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126330$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI connect \Y $extend$libresoc.v:126330$4837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $extend$libresoc.v:126334$4842 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 connect \Y $extend$libresoc.v:126334$4842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126326$4832 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126326$4831_Y connect \Y $pos$libresoc.v:126326$4832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126327$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126327$4833_Y connect \Y $pos$libresoc.v:126327$4834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126330$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126330$4837_Y connect \Y $pos$libresoc.v:126330$4838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $pos$libresoc.v:126334$4843 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126334$4842_Y connect \Y $pos$libresoc.v:126334$4843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" cell $sshl $sshl$libresoc.v:126328$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 connect \Y $sshl$libresoc.v:126328$4835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" cell $sshl $sshl$libresoc.v:126329$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 connect \Y $sshl$libresoc.v:126329$4836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" cell $sshl $sshl$libresoc.v:126331$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 connect \Y $sshl$libresoc.v:126331$4839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" cell $sshl $sshl$libresoc.v:126332$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 connect \Y $sshl$libresoc.v:126332$4840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $sshl $sshl$libresoc.v:126333$4841 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 connect \Y $sshl$libresoc.v:126333$4841_Y end attribute \src "libresoc.v:126248.7-126248.20" process $proc$libresoc.v:126248$4852 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:126336.3-126382.6" process $proc$libresoc.v:126336$4844 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] attribute \src "libresoc.v:126337.5-126337.29" switch \initial attribute \src "libresoc.v:126337.9-126337.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b[63:0] \$11 case assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \imm_b $0\imm_b[63:0] end attribute \src "libresoc.v:126383.3-126429.6" process $proc$libresoc.v:126383$4845 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] attribute \src "libresoc.v:126384.5-126384.29" switch \initial attribute \src "libresoc.v:126384.9-126384.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 case assign $1\imm_b_ok[0:0] 1'0 end sync always update \imm_b_ok $0\imm_b_ok[0:0] end attribute \src "libresoc.v:126430.3-126444.6" process $proc$libresoc.v:126430$4846 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] attribute \src "libresoc.v:126431.5-126431.29" switch \initial attribute \src "libresoc.v:126431.9-126431.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \ALU_SI case assign $1\si[15:0] 16'0000000000000000 end sync always update \si $0\si[15:0] end attribute \src "libresoc.v:126445.3-126463.6" process $proc$libresoc.v:126445$4847 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] attribute \src "libresoc.v:126446.5-126446.29" switch \initial attribute \src "libresoc.v:126446.9-126446.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] case assign $1\si_hi[31:0] 0 end sync always update \si_hi $0\si_hi[31:0] end attribute \src "libresoc.v:126464.3-126486.6" process $proc$libresoc.v:126464$4848 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] attribute \src "libresoc.v:126465.5-126465.29" switch \initial attribute \src "libresoc.v:126465.9-126465.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \ALU_UI case assign $1\ui[15:0] 16'0000000000000000 end sync always update \ui $0\ui[15:0] end attribute \src "libresoc.v:126487.3-126513.6" process $proc$libresoc.v:126487$4849 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] attribute \src "libresoc.v:126488.5-126488.29" switch \initial attribute \src "libresoc.v:126488.9-126488.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] case assign $1\li[25:0] 26'00000000000000000000000000 end sync always update \li $0\li[25:0] end attribute \src "libresoc.v:126514.3-126544.6" process $proc$libresoc.v:126514$4850 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] attribute \src "libresoc.v:126515.5-126515.29" switch \initial attribute \src "libresoc.v:126515.9-126515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] case assign $1\bd[15:0] 16'0000000000000000 end sync always update \bd $0\bd[15:0] end attribute \src "libresoc.v:126545.3-126579.6" process $proc$libresoc.v:126545$4851 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] attribute \src "libresoc.v:126546.5-126546.29" switch \initial attribute \src "libresoc.v:126546.9-126546.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] case assign $1\ds[15:0] 16'0000000000000000 end sync always update \ds $0\ds[15:0] end connect \$9 $pos$libresoc.v:126326$4832_Y connect \$11 $pos$libresoc.v:126327$4834_Y connect \$14 $sshl$libresoc.v:126328$4835_Y connect \$17 $sshl$libresoc.v:126329$4836_Y connect \$1 $pos$libresoc.v:126330$4838_Y connect \$20 $sshl$libresoc.v:126331$4839_Y connect \$23 $sshl$libresoc.v:126332$4840_Y connect \$4 $sshl$libresoc.v:126333$4841_Y connect \$3 $pos$libresoc.v:126334$4843_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end attribute \src "libresoc.v:126588.1-126925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" module \dec_bi$144 attribute \src "libresoc.v:126855.3-126885.6" wire width 16 $0\bd[15:0] attribute \src "libresoc.v:126886.3-126920.6" wire width 16 $0\ds[15:0] attribute \src "libresoc.v:126677.3-126723.6" wire width 64 $0\imm_b[63:0] attribute \src "libresoc.v:126724.3-126770.6" wire $0\imm_b_ok[0:0] attribute \src "libresoc.v:126589.7-126589.20" wire $0\initial[0:0] attribute \src "libresoc.v:126828.3-126854.6" wire width 26 $0\li[25:0] attribute \src "libresoc.v:126771.3-126785.6" wire width 16 $0\si[15:0] attribute \src "libresoc.v:126786.3-126804.6" wire width 32 $0\si_hi[31:0] attribute \src "libresoc.v:126805.3-126827.6" wire width 16 $0\ui[15:0] attribute \src "libresoc.v:126855.3-126885.6" wire width 16 $1\bd[15:0] attribute \src "libresoc.v:126886.3-126920.6" wire width 16 $1\ds[15:0] attribute \src "libresoc.v:126677.3-126723.6" wire width 64 $1\imm_b[63:0] attribute \src "libresoc.v:126724.3-126770.6" wire $1\imm_b_ok[0:0] attribute \src "libresoc.v:126828.3-126854.6" wire width 26 $1\li[25:0] attribute \src "libresoc.v:126771.3-126785.6" wire width 16 $1\si[15:0] attribute \src "libresoc.v:126786.3-126804.6" wire width 32 $1\si_hi[31:0] attribute \src "libresoc.v:126805.3-126827.6" wire width 16 $1\ui[15:0] attribute \src "libresoc.v:126667.17-126667.107" wire width 64 $extend$libresoc.v:126667$4853_Y attribute \src "libresoc.v:126668.18-126668.110" wire width 64 $extend$libresoc.v:126668$4855_Y attribute \src "libresoc.v:126671.17-126671.107" wire width 64 $extend$libresoc.v:126671$4859_Y attribute \src "libresoc.v:126675.17-126675.102" wire width 64 $extend$libresoc.v:126675$4864_Y attribute \src "libresoc.v:126667.17-126667.107" wire width 64 $pos$libresoc.v:126667$4854_Y attribute \src "libresoc.v:126668.18-126668.110" wire width 64 $pos$libresoc.v:126668$4856_Y attribute \src "libresoc.v:126671.17-126671.107" wire width 64 $pos$libresoc.v:126671$4860_Y attribute \src "libresoc.v:126675.17-126675.102" wire width 64 $pos$libresoc.v:126675$4865_Y attribute \src "libresoc.v:126669.18-126669.117" wire width 47 $sshl$libresoc.v:126669$4857_Y attribute \src "libresoc.v:126670.18-126670.116" wire width 27 $sshl$libresoc.v:126670$4858_Y attribute \src "libresoc.v:126672.18-126672.116" wire width 17 $sshl$libresoc.v:126672$4861_Y attribute \src "libresoc.v:126673.18-126673.116" wire width 17 $sshl$libresoc.v:126673$4862_Y attribute \src "libresoc.v:126674.17-126674.109" wire width 47 $sshl$libresoc.v:126674$4863_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \BRANCH_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \BRANCH_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \BRANCH_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \BRANCH_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \BRANCH_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \BRANCH_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \BRANCH_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok attribute \src "libresoc.v:126589.7-126589.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126667$4853 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh connect \Y $extend$libresoc.v:126667$4853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126668$4855 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 connect \Y $extend$libresoc.v:126668$4855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:126671$4859 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI connect \Y $extend$libresoc.v:126671$4859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $extend$libresoc.v:126675$4864 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 connect \Y $extend$libresoc.v:126675$4864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126667$4854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126667$4853_Y connect \Y $pos$libresoc.v:126667$4854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126668$4856 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126668$4855_Y connect \Y $pos$libresoc.v:126668$4856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:126671$4860 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126671$4859_Y connect \Y $pos$libresoc.v:126671$4860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $pos$libresoc.v:126675$4865 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:126675$4864_Y connect \Y $pos$libresoc.v:126675$4865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" cell $sshl $sshl$libresoc.v:126669$4857 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 connect \Y $sshl$libresoc.v:126669$4857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" cell $sshl $sshl$libresoc.v:126670$4858 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 connect \Y $sshl$libresoc.v:126670$4858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" cell $sshl $sshl$libresoc.v:126672$4861 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 connect \Y $sshl$libresoc.v:126672$4861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" cell $sshl $sshl$libresoc.v:126673$4862 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 connect \Y $sshl$libresoc.v:126673$4862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $sshl $sshl$libresoc.v:126674$4863 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 connect \Y $sshl$libresoc.v:126674$4863_Y end attribute \src "libresoc.v:126589.7-126589.20" process $proc$libresoc.v:126589$4874 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:126677.3-126723.6" process $proc$libresoc.v:126677$4866 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] attribute \src "libresoc.v:126678.5-126678.29" switch \initial attribute \src "libresoc.v:126678.9-126678.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b[63:0] \$11 case assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \imm_b $0\imm_b[63:0] end attribute \src "libresoc.v:126724.3-126770.6" process $proc$libresoc.v:126724$4867 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] attribute \src "libresoc.v:126725.5-126725.29" switch \initial attribute \src "libresoc.v:126725.9-126725.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 case assign $1\imm_b_ok[0:0] 1'0 end sync always update \imm_b_ok $0\imm_b_ok[0:0] end attribute \src "libresoc.v:126771.3-126785.6" process $proc$libresoc.v:126771$4868 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] attribute \src "libresoc.v:126772.5-126772.29" switch \initial attribute \src "libresoc.v:126772.9-126772.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \BRANCH_SI case assign $1\si[15:0] 16'0000000000000000 end sync always update \si $0\si[15:0] end attribute \src "libresoc.v:126786.3-126804.6" process $proc$libresoc.v:126786$4869 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] attribute \src "libresoc.v:126787.5-126787.29" switch \initial attribute \src "libresoc.v:126787.9-126787.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] case assign $1\si_hi[31:0] 0 end sync always update \si_hi $0\si_hi[31:0] end attribute \src "libresoc.v:126805.3-126827.6" process $proc$libresoc.v:126805$4870 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] attribute \src "libresoc.v:126806.5-126806.29" switch \initial attribute \src "libresoc.v:126806.9-126806.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \BRANCH_UI case assign $1\ui[15:0] 16'0000000000000000 end sync always update \ui $0\ui[15:0] end attribute \src "libresoc.v:126828.3-126854.6" process $proc$libresoc.v:126828$4871 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] attribute \src "libresoc.v:126829.5-126829.29" switch \initial attribute \src "libresoc.v:126829.9-126829.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] case assign $1\li[25:0] 26'00000000000000000000000000 end sync always update \li $0\li[25:0] end attribute \src "libresoc.v:126855.3-126885.6" process $proc$libresoc.v:126855$4872 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] attribute \src "libresoc.v:126856.5-126856.29" switch \initial attribute \src "libresoc.v:126856.9-126856.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] case assign $1\bd[15:0] 16'0000000000000000 end sync always update \bd $0\bd[15:0] end attribute \src "libresoc.v:126886.3-126920.6" process $proc$libresoc.v:126886$4873 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] attribute \src "libresoc.v:126887.5-126887.29" switch \initial attribute \src "libresoc.v:126887.9-126887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] case assign $1\ds[15:0] 16'0000000000000000 end sync always update \ds $0\ds[15:0] end connect \$9 $pos$libresoc.v:126667$4854_Y connect \$11 $pos$libresoc.v:126668$4856_Y connect \$14 $sshl$libresoc.v:126669$4857_Y connect \$17 $sshl$libresoc.v:126670$4858_Y connect \$1 $pos$libresoc.v:126671$4860_Y connect \$20 $sshl$libresoc.v:126672$4861_Y connect \$23 $sshl$libresoc.v:126673$4862_Y connect \$4 $sshl$libresoc.v:126674$4863_Y connect \$3 $pos$libresoc.v:126675$4865_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end attribute \src "libresoc.v:126929.1-127266.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" module \dec_bi$149 attribute \src "libresoc.v:127196.3-127226.6" wire width 16 $0\bd[15:0] attribute \src "libresoc.v:127227.3-127261.6" wire width 16 $0\ds[15:0] attribute \src "libresoc.v:127018.3-127064.6" wire width 64 $0\imm_b[63:0] attribute \src "libresoc.v:127065.3-127111.6" wire $0\imm_b_ok[0:0] attribute \src "libresoc.v:126930.7-126930.20" wire $0\initial[0:0] attribute \src "libresoc.v:127169.3-127195.6" wire width 26 $0\li[25:0] attribute \src "libresoc.v:127112.3-127126.6" wire width 16 $0\si[15:0] attribute \src "libresoc.v:127127.3-127145.6" wire width 32 $0\si_hi[31:0] attribute \src "libresoc.v:127146.3-127168.6" wire width 16 $0\ui[15:0] attribute \src "libresoc.v:127196.3-127226.6" wire width 16 $1\bd[15:0] attribute \src "libresoc.v:127227.3-127261.6" wire width 16 $1\ds[15:0] attribute \src "libresoc.v:127018.3-127064.6" wire width 64 $1\imm_b[63:0] attribute \src "libresoc.v:127065.3-127111.6" wire $1\imm_b_ok[0:0] attribute \src "libresoc.v:127169.3-127195.6" wire width 26 $1\li[25:0] attribute \src "libresoc.v:127112.3-127126.6" wire width 16 $1\si[15:0] attribute \src "libresoc.v:127127.3-127145.6" wire width 32 $1\si_hi[31:0] attribute \src "libresoc.v:127146.3-127168.6" wire width 16 $1\ui[15:0] attribute \src "libresoc.v:127008.17-127008.108" wire width 64 $extend$libresoc.v:127008$4875_Y attribute \src "libresoc.v:127009.18-127009.111" wire width 64 $extend$libresoc.v:127009$4877_Y attribute \src "libresoc.v:127012.17-127012.108" wire width 64 $extend$libresoc.v:127012$4881_Y attribute \src "libresoc.v:127016.17-127016.102" wire width 64 $extend$libresoc.v:127016$4886_Y attribute \src "libresoc.v:127008.17-127008.108" wire width 64 $pos$libresoc.v:127008$4876_Y attribute \src "libresoc.v:127009.18-127009.111" wire width 64 $pos$libresoc.v:127009$4878_Y attribute \src "libresoc.v:127012.17-127012.108" wire width 64 $pos$libresoc.v:127012$4882_Y attribute \src "libresoc.v:127016.17-127016.102" wire width 64 $pos$libresoc.v:127016$4887_Y attribute \src "libresoc.v:127010.18-127010.118" wire width 47 $sshl$libresoc.v:127010$4879_Y attribute \src "libresoc.v:127011.18-127011.117" wire width 27 $sshl$libresoc.v:127011$4880_Y attribute \src "libresoc.v:127013.18-127013.117" wire width 17 $sshl$libresoc.v:127013$4883_Y attribute \src "libresoc.v:127014.18-127014.117" wire width 17 $sshl$libresoc.v:127014$4884_Y attribute \src "libresoc.v:127015.17-127015.109" wire width 47 $sshl$libresoc.v:127015$4885_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \LOGICAL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \LOGICAL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \LOGICAL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \LOGICAL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \LOGICAL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \LOGICAL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LOGICAL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok attribute \src "libresoc.v:126930.7-126930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127008$4875 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh connect \Y $extend$libresoc.v:127008$4875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127009$4877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 connect \Y $extend$libresoc.v:127009$4877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127012$4881 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI connect \Y $extend$libresoc.v:127012$4881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $extend$libresoc.v:127016$4886 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 connect \Y $extend$libresoc.v:127016$4886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127008$4876 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127008$4875_Y connect \Y $pos$libresoc.v:127008$4876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127009$4878 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127009$4877_Y connect \Y $pos$libresoc.v:127009$4878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127012$4882 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127012$4881_Y connect \Y $pos$libresoc.v:127012$4882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $pos$libresoc.v:127016$4887 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127016$4886_Y connect \Y $pos$libresoc.v:127016$4887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" cell $sshl $sshl$libresoc.v:127010$4879 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 connect \Y $sshl$libresoc.v:127010$4879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" cell $sshl $sshl$libresoc.v:127011$4880 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 connect \Y $sshl$libresoc.v:127011$4880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" cell $sshl $sshl$libresoc.v:127013$4883 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 connect \Y $sshl$libresoc.v:127013$4883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" cell $sshl $sshl$libresoc.v:127014$4884 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 connect \Y $sshl$libresoc.v:127014$4884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $sshl $sshl$libresoc.v:127015$4885 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 connect \Y $sshl$libresoc.v:127015$4885_Y end attribute \src "libresoc.v:126930.7-126930.20" process $proc$libresoc.v:126930$4896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:127018.3-127064.6" process $proc$libresoc.v:127018$4888 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] attribute \src "libresoc.v:127019.5-127019.29" switch \initial attribute \src "libresoc.v:127019.9-127019.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b[63:0] \$11 case assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \imm_b $0\imm_b[63:0] end attribute \src "libresoc.v:127065.3-127111.6" process $proc$libresoc.v:127065$4889 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] attribute \src "libresoc.v:127066.5-127066.29" switch \initial attribute \src "libresoc.v:127066.9-127066.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 case assign $1\imm_b_ok[0:0] 1'0 end sync always update \imm_b_ok $0\imm_b_ok[0:0] end attribute \src "libresoc.v:127112.3-127126.6" process $proc$libresoc.v:127112$4890 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] attribute \src "libresoc.v:127113.5-127113.29" switch \initial attribute \src "libresoc.v:127113.9-127113.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \LOGICAL_SI case assign $1\si[15:0] 16'0000000000000000 end sync always update \si $0\si[15:0] end attribute \src "libresoc.v:127127.3-127145.6" process $proc$libresoc.v:127127$4891 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] attribute \src "libresoc.v:127128.5-127128.29" switch \initial attribute \src "libresoc.v:127128.9-127128.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] case assign $1\si_hi[31:0] 0 end sync always update \si_hi $0\si_hi[31:0] end attribute \src "libresoc.v:127146.3-127168.6" process $proc$libresoc.v:127146$4892 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] attribute \src "libresoc.v:127147.5-127147.29" switch \initial attribute \src "libresoc.v:127147.9-127147.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \LOGICAL_UI case assign $1\ui[15:0] 16'0000000000000000 end sync always update \ui $0\ui[15:0] end attribute \src "libresoc.v:127169.3-127195.6" process $proc$libresoc.v:127169$4893 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] attribute \src "libresoc.v:127170.5-127170.29" switch \initial attribute \src "libresoc.v:127170.9-127170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] case assign $1\li[25:0] 26'00000000000000000000000000 end sync always update \li $0\li[25:0] end attribute \src "libresoc.v:127196.3-127226.6" process $proc$libresoc.v:127196$4894 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] attribute \src "libresoc.v:127197.5-127197.29" switch \initial attribute \src "libresoc.v:127197.9-127197.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] case assign $1\bd[15:0] 16'0000000000000000 end sync always update \bd $0\bd[15:0] end attribute \src "libresoc.v:127227.3-127261.6" process $proc$libresoc.v:127227$4895 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] attribute \src "libresoc.v:127228.5-127228.29" switch \initial attribute \src "libresoc.v:127228.9-127228.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] case assign $1\ds[15:0] 16'0000000000000000 end sync always update \ds $0\ds[15:0] end connect \$9 $pos$libresoc.v:127008$4876_Y connect \$11 $pos$libresoc.v:127009$4878_Y connect \$14 $sshl$libresoc.v:127010$4879_Y connect \$17 $sshl$libresoc.v:127011$4880_Y connect \$1 $pos$libresoc.v:127012$4882_Y connect \$20 $sshl$libresoc.v:127013$4883_Y connect \$23 $sshl$libresoc.v:127014$4884_Y connect \$4 $sshl$libresoc.v:127015$4885_Y connect \$3 $pos$libresoc.v:127016$4887_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end attribute \src "libresoc.v:127270.1-127607.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" module \dec_bi$157 attribute \src "libresoc.v:127537.3-127567.6" wire width 16 $0\bd[15:0] attribute \src "libresoc.v:127568.3-127602.6" wire width 16 $0\ds[15:0] attribute \src "libresoc.v:127359.3-127405.6" wire width 64 $0\imm_b[63:0] attribute \src "libresoc.v:127406.3-127452.6" wire $0\imm_b_ok[0:0] attribute \src "libresoc.v:127271.7-127271.20" wire $0\initial[0:0] attribute \src "libresoc.v:127510.3-127536.6" wire width 26 $0\li[25:0] attribute \src "libresoc.v:127453.3-127467.6" wire width 16 $0\si[15:0] attribute \src "libresoc.v:127468.3-127486.6" wire width 32 $0\si_hi[31:0] attribute \src "libresoc.v:127487.3-127509.6" wire width 16 $0\ui[15:0] attribute \src "libresoc.v:127537.3-127567.6" wire width 16 $1\bd[15:0] attribute \src "libresoc.v:127568.3-127602.6" wire width 16 $1\ds[15:0] attribute \src "libresoc.v:127359.3-127405.6" wire width 64 $1\imm_b[63:0] attribute \src "libresoc.v:127406.3-127452.6" wire $1\imm_b_ok[0:0] attribute \src "libresoc.v:127510.3-127536.6" wire width 26 $1\li[25:0] attribute \src "libresoc.v:127453.3-127467.6" wire width 16 $1\si[15:0] attribute \src "libresoc.v:127468.3-127486.6" wire width 32 $1\si_hi[31:0] attribute \src "libresoc.v:127487.3-127509.6" wire width 16 $1\ui[15:0] attribute \src "libresoc.v:127349.17-127349.104" wire width 64 $extend$libresoc.v:127349$4897_Y attribute \src "libresoc.v:127350.18-127350.107" wire width 64 $extend$libresoc.v:127350$4899_Y attribute \src "libresoc.v:127353.17-127353.104" wire width 64 $extend$libresoc.v:127353$4903_Y attribute \src "libresoc.v:127357.17-127357.102" wire width 64 $extend$libresoc.v:127357$4908_Y attribute \src "libresoc.v:127349.17-127349.104" wire width 64 $pos$libresoc.v:127349$4898_Y attribute \src "libresoc.v:127350.18-127350.107" wire width 64 $pos$libresoc.v:127350$4900_Y attribute \src "libresoc.v:127353.17-127353.104" wire width 64 $pos$libresoc.v:127353$4904_Y attribute \src "libresoc.v:127357.17-127357.102" wire width 64 $pos$libresoc.v:127357$4909_Y attribute \src "libresoc.v:127351.18-127351.114" wire width 47 $sshl$libresoc.v:127351$4901_Y attribute \src "libresoc.v:127352.18-127352.113" wire width 27 $sshl$libresoc.v:127352$4902_Y attribute \src "libresoc.v:127354.18-127354.113" wire width 17 $sshl$libresoc.v:127354$4905_Y attribute \src "libresoc.v:127355.18-127355.113" wire width 17 $sshl$libresoc.v:127355$4906_Y attribute \src "libresoc.v:127356.17-127356.109" wire width 47 $sshl$libresoc.v:127356$4907_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \DIV_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \DIV_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \DIV_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \DIV_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \DIV_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \DIV_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \DIV_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok attribute \src "libresoc.v:127271.7-127271.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127349$4897 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh connect \Y $extend$libresoc.v:127349$4897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127350$4899 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 connect \Y $extend$libresoc.v:127350$4899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127353$4903 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI connect \Y $extend$libresoc.v:127353$4903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $extend$libresoc.v:127357$4908 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 connect \Y $extend$libresoc.v:127357$4908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127349$4898 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127349$4897_Y connect \Y $pos$libresoc.v:127349$4898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127350$4900 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127350$4899_Y connect \Y $pos$libresoc.v:127350$4900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127353$4904 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127353$4903_Y connect \Y $pos$libresoc.v:127353$4904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $pos$libresoc.v:127357$4909 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127357$4908_Y connect \Y $pos$libresoc.v:127357$4909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" cell $sshl $sshl$libresoc.v:127351$4901 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 connect \Y $sshl$libresoc.v:127351$4901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" cell $sshl $sshl$libresoc.v:127352$4902 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 connect \Y $sshl$libresoc.v:127352$4902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" cell $sshl $sshl$libresoc.v:127354$4905 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 connect \Y $sshl$libresoc.v:127354$4905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" cell $sshl $sshl$libresoc.v:127355$4906 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 connect \Y $sshl$libresoc.v:127355$4906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $sshl $sshl$libresoc.v:127356$4907 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 connect \Y $sshl$libresoc.v:127356$4907_Y end attribute \src "libresoc.v:127271.7-127271.20" process $proc$libresoc.v:127271$4918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:127359.3-127405.6" process $proc$libresoc.v:127359$4910 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] attribute \src "libresoc.v:127360.5-127360.29" switch \initial attribute \src "libresoc.v:127360.9-127360.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b[63:0] \$11 case assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \imm_b $0\imm_b[63:0] end attribute \src "libresoc.v:127406.3-127452.6" process $proc$libresoc.v:127406$4911 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] attribute \src "libresoc.v:127407.5-127407.29" switch \initial attribute \src "libresoc.v:127407.9-127407.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 case assign $1\imm_b_ok[0:0] 1'0 end sync always update \imm_b_ok $0\imm_b_ok[0:0] end attribute \src "libresoc.v:127453.3-127467.6" process $proc$libresoc.v:127453$4912 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] attribute \src "libresoc.v:127454.5-127454.29" switch \initial attribute \src "libresoc.v:127454.9-127454.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \DIV_SI case assign $1\si[15:0] 16'0000000000000000 end sync always update \si $0\si[15:0] end attribute \src "libresoc.v:127468.3-127486.6" process $proc$libresoc.v:127468$4913 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] attribute \src "libresoc.v:127469.5-127469.29" switch \initial attribute \src "libresoc.v:127469.9-127469.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] case assign $1\si_hi[31:0] 0 end sync always update \si_hi $0\si_hi[31:0] end attribute \src "libresoc.v:127487.3-127509.6" process $proc$libresoc.v:127487$4914 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] attribute \src "libresoc.v:127488.5-127488.29" switch \initial attribute \src "libresoc.v:127488.9-127488.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \DIV_UI case assign $1\ui[15:0] 16'0000000000000000 end sync always update \ui $0\ui[15:0] end attribute \src "libresoc.v:127510.3-127536.6" process $proc$libresoc.v:127510$4915 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] attribute \src "libresoc.v:127511.5-127511.29" switch \initial attribute \src "libresoc.v:127511.9-127511.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] case assign $1\li[25:0] 26'00000000000000000000000000 end sync always update \li $0\li[25:0] end attribute \src "libresoc.v:127537.3-127567.6" process $proc$libresoc.v:127537$4916 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] attribute \src "libresoc.v:127538.5-127538.29" switch \initial attribute \src "libresoc.v:127538.9-127538.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] case assign $1\bd[15:0] 16'0000000000000000 end sync always update \bd $0\bd[15:0] end attribute \src "libresoc.v:127568.3-127602.6" process $proc$libresoc.v:127568$4917 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] attribute \src "libresoc.v:127569.5-127569.29" switch \initial attribute \src "libresoc.v:127569.9-127569.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] case assign $1\ds[15:0] 16'0000000000000000 end sync always update \ds $0\ds[15:0] end connect \$9 $pos$libresoc.v:127349$4898_Y connect \$11 $pos$libresoc.v:127350$4900_Y connect \$14 $sshl$libresoc.v:127351$4901_Y connect \$17 $sshl$libresoc.v:127352$4902_Y connect \$1 $pos$libresoc.v:127353$4904_Y connect \$20 $sshl$libresoc.v:127354$4905_Y connect \$23 $sshl$libresoc.v:127355$4906_Y connect \$4 $sshl$libresoc.v:127356$4907_Y connect \$3 $pos$libresoc.v:127357$4909_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end attribute \src "libresoc.v:127611.1-127948.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" module \dec_bi$161 attribute \src "libresoc.v:127878.3-127908.6" wire width 16 $0\bd[15:0] attribute \src "libresoc.v:127909.3-127943.6" wire width 16 $0\ds[15:0] attribute \src "libresoc.v:127700.3-127746.6" wire width 64 $0\imm_b[63:0] attribute \src "libresoc.v:127747.3-127793.6" wire $0\imm_b_ok[0:0] attribute \src "libresoc.v:127612.7-127612.20" wire $0\initial[0:0] attribute \src "libresoc.v:127851.3-127877.6" wire width 26 $0\li[25:0] attribute \src "libresoc.v:127794.3-127808.6" wire width 16 $0\si[15:0] attribute \src "libresoc.v:127809.3-127827.6" wire width 32 $0\si_hi[31:0] attribute \src "libresoc.v:127828.3-127850.6" wire width 16 $0\ui[15:0] attribute \src "libresoc.v:127878.3-127908.6" wire width 16 $1\bd[15:0] attribute \src "libresoc.v:127909.3-127943.6" wire width 16 $1\ds[15:0] attribute \src "libresoc.v:127700.3-127746.6" wire width 64 $1\imm_b[63:0] attribute \src "libresoc.v:127747.3-127793.6" wire $1\imm_b_ok[0:0] attribute \src "libresoc.v:127851.3-127877.6" wire width 26 $1\li[25:0] attribute \src "libresoc.v:127794.3-127808.6" wire width 16 $1\si[15:0] attribute \src "libresoc.v:127809.3-127827.6" wire width 32 $1\si_hi[31:0] attribute \src "libresoc.v:127828.3-127850.6" wire width 16 $1\ui[15:0] attribute \src "libresoc.v:127690.17-127690.104" wire width 64 $extend$libresoc.v:127690$4919_Y attribute \src "libresoc.v:127691.18-127691.107" wire width 64 $extend$libresoc.v:127691$4921_Y attribute \src "libresoc.v:127694.17-127694.104" wire width 64 $extend$libresoc.v:127694$4925_Y attribute \src "libresoc.v:127698.17-127698.102" wire width 64 $extend$libresoc.v:127698$4930_Y attribute \src "libresoc.v:127690.17-127690.104" wire width 64 $pos$libresoc.v:127690$4920_Y attribute \src "libresoc.v:127691.18-127691.107" wire width 64 $pos$libresoc.v:127691$4922_Y attribute \src "libresoc.v:127694.17-127694.104" wire width 64 $pos$libresoc.v:127694$4926_Y attribute \src "libresoc.v:127698.17-127698.102" wire width 64 $pos$libresoc.v:127698$4931_Y attribute \src "libresoc.v:127692.18-127692.114" wire width 47 $sshl$libresoc.v:127692$4923_Y attribute \src "libresoc.v:127693.18-127693.113" wire width 27 $sshl$libresoc.v:127693$4924_Y attribute \src "libresoc.v:127695.18-127695.113" wire width 17 $sshl$libresoc.v:127695$4927_Y attribute \src "libresoc.v:127696.18-127696.113" wire width 17 $sshl$libresoc.v:127696$4928_Y attribute \src "libresoc.v:127697.17-127697.109" wire width 47 $sshl$libresoc.v:127697$4929_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \MUL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \MUL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \MUL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \MUL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \MUL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \MUL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \MUL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok attribute \src "libresoc.v:127612.7-127612.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127690$4919 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh connect \Y $extend$libresoc.v:127690$4919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127691$4921 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 connect \Y $extend$libresoc.v:127691$4921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:127694$4925 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI connect \Y $extend$libresoc.v:127694$4925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $extend$libresoc.v:127698$4930 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 connect \Y $extend$libresoc.v:127698$4930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127690$4920 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127690$4919_Y connect \Y $pos$libresoc.v:127690$4920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127691$4922 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127691$4921_Y connect \Y $pos$libresoc.v:127691$4922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:127694$4926 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127694$4925_Y connect \Y $pos$libresoc.v:127694$4926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $pos$libresoc.v:127698$4931 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:127698$4930_Y connect \Y $pos$libresoc.v:127698$4931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" cell $sshl $sshl$libresoc.v:127692$4923 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 connect \Y $sshl$libresoc.v:127692$4923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" cell $sshl $sshl$libresoc.v:127693$4924 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 connect \Y $sshl$libresoc.v:127693$4924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" cell $sshl $sshl$libresoc.v:127695$4927 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 connect \Y $sshl$libresoc.v:127695$4927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" cell $sshl $sshl$libresoc.v:127696$4928 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 connect \Y $sshl$libresoc.v:127696$4928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $sshl $sshl$libresoc.v:127697$4929 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 connect \Y $sshl$libresoc.v:127697$4929_Y end attribute \src "libresoc.v:127612.7-127612.20" process $proc$libresoc.v:127612$4940 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:127700.3-127746.6" process $proc$libresoc.v:127700$4932 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] attribute \src "libresoc.v:127701.5-127701.29" switch \initial attribute \src "libresoc.v:127701.9-127701.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b[63:0] \$11 case assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \imm_b $0\imm_b[63:0] end attribute \src "libresoc.v:127747.3-127793.6" process $proc$libresoc.v:127747$4933 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] attribute \src "libresoc.v:127748.5-127748.29" switch \initial attribute \src "libresoc.v:127748.9-127748.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 case assign $1\imm_b_ok[0:0] 1'0 end sync always update \imm_b_ok $0\imm_b_ok[0:0] end attribute \src "libresoc.v:127794.3-127808.6" process $proc$libresoc.v:127794$4934 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] attribute \src "libresoc.v:127795.5-127795.29" switch \initial attribute \src "libresoc.v:127795.9-127795.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \MUL_SI case assign $1\si[15:0] 16'0000000000000000 end sync always update \si $0\si[15:0] end attribute \src "libresoc.v:127809.3-127827.6" process $proc$libresoc.v:127809$4935 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] attribute \src "libresoc.v:127810.5-127810.29" switch \initial attribute \src "libresoc.v:127810.9-127810.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] case assign $1\si_hi[31:0] 0 end sync always update \si_hi $0\si_hi[31:0] end attribute \src "libresoc.v:127828.3-127850.6" process $proc$libresoc.v:127828$4936 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] attribute \src "libresoc.v:127829.5-127829.29" switch \initial attribute \src "libresoc.v:127829.9-127829.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \MUL_UI case assign $1\ui[15:0] 16'0000000000000000 end sync always update \ui $0\ui[15:0] end attribute \src "libresoc.v:127851.3-127877.6" process $proc$libresoc.v:127851$4937 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] attribute \src "libresoc.v:127852.5-127852.29" switch \initial attribute \src "libresoc.v:127852.9-127852.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] case assign $1\li[25:0] 26'00000000000000000000000000 end sync always update \li $0\li[25:0] end attribute \src "libresoc.v:127878.3-127908.6" process $proc$libresoc.v:127878$4938 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] attribute \src "libresoc.v:127879.5-127879.29" switch \initial attribute \src "libresoc.v:127879.9-127879.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] case assign $1\bd[15:0] 16'0000000000000000 end sync always update \bd $0\bd[15:0] end attribute \src "libresoc.v:127909.3-127943.6" process $proc$libresoc.v:127909$4939 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] attribute \src "libresoc.v:127910.5-127910.29" switch \initial attribute \src "libresoc.v:127910.9-127910.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] case assign $1\ds[15:0] 16'0000000000000000 end sync always update \ds $0\ds[15:0] end connect \$9 $pos$libresoc.v:127690$4920_Y connect \$11 $pos$libresoc.v:127691$4922_Y connect \$14 $sshl$libresoc.v:127692$4923_Y connect \$17 $sshl$libresoc.v:127693$4924_Y connect \$1 $pos$libresoc.v:127694$4926_Y connect \$20 $sshl$libresoc.v:127695$4927_Y connect \$23 $sshl$libresoc.v:127696$4928_Y connect \$4 $sshl$libresoc.v:127697$4929_Y connect \$3 $pos$libresoc.v:127698$4931_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end attribute \src "libresoc.v:127952.1-128289.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" module \dec_bi$165 attribute \src "libresoc.v:128219.3-128249.6" wire width 16 $0\bd[15:0] attribute \src "libresoc.v:128250.3-128284.6" wire width 16 $0\ds[15:0] attribute \src "libresoc.v:128041.3-128087.6" wire width 64 $0\imm_b[63:0] attribute \src "libresoc.v:128088.3-128134.6" wire $0\imm_b_ok[0:0] attribute \src "libresoc.v:127953.7-127953.20" wire $0\initial[0:0] attribute \src "libresoc.v:128192.3-128218.6" wire width 26 $0\li[25:0] attribute \src "libresoc.v:128135.3-128149.6" wire width 16 $0\si[15:0] attribute \src "libresoc.v:128150.3-128168.6" wire width 32 $0\si_hi[31:0] attribute \src "libresoc.v:128169.3-128191.6" wire width 16 $0\ui[15:0] attribute \src "libresoc.v:128219.3-128249.6" wire width 16 $1\bd[15:0] attribute \src "libresoc.v:128250.3-128284.6" wire width 16 $1\ds[15:0] attribute \src "libresoc.v:128041.3-128087.6" wire width 64 $1\imm_b[63:0] attribute \src "libresoc.v:128088.3-128134.6" wire $1\imm_b_ok[0:0] attribute \src "libresoc.v:128192.3-128218.6" wire width 26 $1\li[25:0] attribute \src "libresoc.v:128135.3-128149.6" wire width 16 $1\si[15:0] attribute \src "libresoc.v:128150.3-128168.6" wire width 32 $1\si_hi[31:0] attribute \src "libresoc.v:128169.3-128191.6" wire width 16 $1\ui[15:0] attribute \src "libresoc.v:128031.17-128031.110" wire width 64 $extend$libresoc.v:128031$4941_Y attribute \src "libresoc.v:128032.18-128032.113" wire width 64 $extend$libresoc.v:128032$4943_Y attribute \src "libresoc.v:128035.17-128035.110" wire width 64 $extend$libresoc.v:128035$4947_Y attribute \src "libresoc.v:128039.17-128039.102" wire width 64 $extend$libresoc.v:128039$4952_Y attribute \src "libresoc.v:128031.17-128031.110" wire width 64 $pos$libresoc.v:128031$4942_Y attribute \src "libresoc.v:128032.18-128032.113" wire width 64 $pos$libresoc.v:128032$4944_Y attribute \src "libresoc.v:128035.17-128035.110" wire width 64 $pos$libresoc.v:128035$4948_Y attribute \src "libresoc.v:128039.17-128039.102" wire width 64 $pos$libresoc.v:128039$4953_Y attribute \src "libresoc.v:128033.18-128033.120" wire width 47 $sshl$libresoc.v:128033$4945_Y attribute \src "libresoc.v:128034.18-128034.119" wire width 27 $sshl$libresoc.v:128034$4946_Y attribute \src "libresoc.v:128036.18-128036.119" wire width 17 $sshl$libresoc.v:128036$4949_Y attribute \src "libresoc.v:128037.18-128037.119" wire width 17 $sshl$libresoc.v:128037$4950_Y attribute \src "libresoc.v:128038.17-128038.109" wire width 47 $sshl$libresoc.v:128038$4951_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \SHIFT_ROT_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \SHIFT_ROT_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \SHIFT_ROT_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \SHIFT_ROT_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \SHIFT_ROT_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \SHIFT_ROT_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \SHIFT_ROT_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok attribute \src "libresoc.v:127953.7-127953.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:128031$4941 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh connect \Y $extend$libresoc.v:128031$4941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:128032$4943 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 connect \Y $extend$libresoc.v:128032$4943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:128035$4947 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI connect \Y $extend$libresoc.v:128035$4947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $extend$libresoc.v:128039$4952 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 connect \Y $extend$libresoc.v:128039$4952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:128031$4942 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128031$4941_Y connect \Y $pos$libresoc.v:128031$4942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:128032$4944 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128032$4943_Y connect \Y $pos$libresoc.v:128032$4944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:128035$4948 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128035$4947_Y connect \Y $pos$libresoc.v:128035$4948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $pos$libresoc.v:128039$4953 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128039$4952_Y connect \Y $pos$libresoc.v:128039$4953_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" cell $sshl $sshl$libresoc.v:128033$4945 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 connect \Y $sshl$libresoc.v:128033$4945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" cell $sshl $sshl$libresoc.v:128034$4946 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 connect \Y $sshl$libresoc.v:128034$4946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" cell $sshl $sshl$libresoc.v:128036$4949 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 connect \Y $sshl$libresoc.v:128036$4949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" cell $sshl $sshl$libresoc.v:128037$4950 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 connect \Y $sshl$libresoc.v:128037$4950_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $sshl $sshl$libresoc.v:128038$4951 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 connect \Y $sshl$libresoc.v:128038$4951_Y end attribute \src "libresoc.v:127953.7-127953.20" process $proc$libresoc.v:127953$4962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:128041.3-128087.6" process $proc$libresoc.v:128041$4954 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] attribute \src "libresoc.v:128042.5-128042.29" switch \initial attribute \src "libresoc.v:128042.9-128042.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b[63:0] \$11 case assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \imm_b $0\imm_b[63:0] end attribute \src "libresoc.v:128088.3-128134.6" process $proc$libresoc.v:128088$4955 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] attribute \src "libresoc.v:128089.5-128089.29" switch \initial attribute \src "libresoc.v:128089.9-128089.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 case assign $1\imm_b_ok[0:0] 1'0 end sync always update \imm_b_ok $0\imm_b_ok[0:0] end attribute \src "libresoc.v:128135.3-128149.6" process $proc$libresoc.v:128135$4956 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] attribute \src "libresoc.v:128136.5-128136.29" switch \initial attribute \src "libresoc.v:128136.9-128136.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \SHIFT_ROT_SI case assign $1\si[15:0] 16'0000000000000000 end sync always update \si $0\si[15:0] end attribute \src "libresoc.v:128150.3-128168.6" process $proc$libresoc.v:128150$4957 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] attribute \src "libresoc.v:128151.5-128151.29" switch \initial attribute \src "libresoc.v:128151.9-128151.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] case assign $1\si_hi[31:0] 0 end sync always update \si_hi $0\si_hi[31:0] end attribute \src "libresoc.v:128169.3-128191.6" process $proc$libresoc.v:128169$4958 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] attribute \src "libresoc.v:128170.5-128170.29" switch \initial attribute \src "libresoc.v:128170.9-128170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \SHIFT_ROT_UI case assign $1\ui[15:0] 16'0000000000000000 end sync always update \ui $0\ui[15:0] end attribute \src "libresoc.v:128192.3-128218.6" process $proc$libresoc.v:128192$4959 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] attribute \src "libresoc.v:128193.5-128193.29" switch \initial attribute \src "libresoc.v:128193.9-128193.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] case assign $1\li[25:0] 26'00000000000000000000000000 end sync always update \li $0\li[25:0] end attribute \src "libresoc.v:128219.3-128249.6" process $proc$libresoc.v:128219$4960 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] attribute \src "libresoc.v:128220.5-128220.29" switch \initial attribute \src "libresoc.v:128220.9-128220.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] case assign $1\bd[15:0] 16'0000000000000000 end sync always update \bd $0\bd[15:0] end attribute \src "libresoc.v:128250.3-128284.6" process $proc$libresoc.v:128250$4961 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] attribute \src "libresoc.v:128251.5-128251.29" switch \initial attribute \src "libresoc.v:128251.9-128251.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] case assign $1\ds[15:0] 16'0000000000000000 end sync always update \ds $0\ds[15:0] end connect \$9 $pos$libresoc.v:128031$4942_Y connect \$11 $pos$libresoc.v:128032$4944_Y connect \$14 $sshl$libresoc.v:128033$4945_Y connect \$17 $sshl$libresoc.v:128034$4946_Y connect \$1 $pos$libresoc.v:128035$4948_Y connect \$20 $sshl$libresoc.v:128036$4949_Y connect \$23 $sshl$libresoc.v:128037$4950_Y connect \$4 $sshl$libresoc.v:128038$4951_Y connect \$3 $pos$libresoc.v:128039$4953_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end attribute \src "libresoc.v:128293.1-128630.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" module \dec_bi$170 attribute \src "libresoc.v:128560.3-128590.6" wire width 16 $0\bd[15:0] attribute \src "libresoc.v:128591.3-128625.6" wire width 16 $0\ds[15:0] attribute \src "libresoc.v:128382.3-128428.6" wire width 64 $0\imm_b[63:0] attribute \src "libresoc.v:128429.3-128475.6" wire $0\imm_b_ok[0:0] attribute \src "libresoc.v:128294.7-128294.20" wire $0\initial[0:0] attribute \src "libresoc.v:128533.3-128559.6" wire width 26 $0\li[25:0] attribute \src "libresoc.v:128476.3-128490.6" wire width 16 $0\si[15:0] attribute \src "libresoc.v:128491.3-128509.6" wire width 32 $0\si_hi[31:0] attribute \src "libresoc.v:128510.3-128532.6" wire width 16 $0\ui[15:0] attribute \src "libresoc.v:128560.3-128590.6" wire width 16 $1\bd[15:0] attribute \src "libresoc.v:128591.3-128625.6" wire width 16 $1\ds[15:0] attribute \src "libresoc.v:128382.3-128428.6" wire width 64 $1\imm_b[63:0] attribute \src "libresoc.v:128429.3-128475.6" wire $1\imm_b_ok[0:0] attribute \src "libresoc.v:128533.3-128559.6" wire width 26 $1\li[25:0] attribute \src "libresoc.v:128476.3-128490.6" wire width 16 $1\si[15:0] attribute \src "libresoc.v:128491.3-128509.6" wire width 32 $1\si_hi[31:0] attribute \src "libresoc.v:128510.3-128532.6" wire width 16 $1\ui[15:0] attribute \src "libresoc.v:128372.17-128372.105" wire width 64 $extend$libresoc.v:128372$4963_Y attribute \src "libresoc.v:128373.18-128373.108" wire width 64 $extend$libresoc.v:128373$4965_Y attribute \src "libresoc.v:128376.17-128376.105" wire width 64 $extend$libresoc.v:128376$4969_Y attribute \src "libresoc.v:128380.17-128380.102" wire width 64 $extend$libresoc.v:128380$4974_Y attribute \src "libresoc.v:128372.17-128372.105" wire width 64 $pos$libresoc.v:128372$4964_Y attribute \src "libresoc.v:128373.18-128373.108" wire width 64 $pos$libresoc.v:128373$4966_Y attribute \src "libresoc.v:128376.17-128376.105" wire width 64 $pos$libresoc.v:128376$4970_Y attribute \src "libresoc.v:128380.17-128380.102" wire width 64 $pos$libresoc.v:128380$4975_Y attribute \src "libresoc.v:128374.18-128374.115" wire width 47 $sshl$libresoc.v:128374$4967_Y attribute \src "libresoc.v:128375.18-128375.114" wire width 27 $sshl$libresoc.v:128375$4968_Y attribute \src "libresoc.v:128377.18-128377.114" wire width 17 $sshl$libresoc.v:128377$4971_Y attribute \src "libresoc.v:128378.18-128378.114" wire width 17 $sshl$libresoc.v:128378$4972_Y attribute \src "libresoc.v:128379.17-128379.109" wire width 47 $sshl$libresoc.v:128379$4973_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" wire width 47 \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" wire width 27 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" wire width 17 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" wire width 17 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 64 \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" wire width 47 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 8 \LDST_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 14 input 9 \LDST_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 24 input 7 \LDST_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 5 \LDST_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 3 \LDST_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 16 input 4 \LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 6 input 6 \LDST_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" wire width 16 \bd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \imm_b_ok attribute \src "libresoc.v:128294.7-128294.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" attribute \enum_value_0010 "CONST_UI" attribute \enum_value_0011 "CONST_SI" attribute \enum_value_0100 "CONST_UI_HI" attribute \enum_value_0101 "CONST_SI_HI" attribute \enum_value_0110 "CONST_LI" attribute \enum_value_0111 "CONST_BD" attribute \enum_value_1000 "CONST_DS" attribute \enum_value_1001 "CONST_M1" attribute \enum_value_1010 "CONST_SH" attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 4 input 10 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 16 \si attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 32 \si_hi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:128372$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh connect \Y $extend$libresoc.v:128372$4963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:128373$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 connect \Y $extend$libresoc.v:128373$4965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $extend$libresoc.v:128376$4969 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI connect \Y $extend$libresoc.v:128376$4969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $extend$libresoc.v:128380$4974 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 connect \Y $extend$libresoc.v:128380$4974_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:128372$4964 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128372$4963_Y connect \Y $pos$libresoc.v:128372$4964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:128373$4966 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128373$4965_Y connect \Y $pos$libresoc.v:128373$4966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" cell $pos $pos$libresoc.v:128376$4970 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128376$4969_Y connect \Y $pos$libresoc.v:128376$4970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $pos $pos$libresoc.v:128380$4975 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:128380$4974_Y connect \Y $pos$libresoc.v:128380$4975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" cell $sshl $sshl$libresoc.v:128374$4967 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 connect \Y $sshl$libresoc.v:128374$4967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" cell $sshl $sshl$libresoc.v:128375$4968 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 connect \Y $sshl$libresoc.v:128375$4968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" cell $sshl $sshl$libresoc.v:128377$4971 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 connect \Y $sshl$libresoc.v:128377$4971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" cell $sshl $sshl$libresoc.v:128378$4972 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 connect \Y $sshl$libresoc.v:128378$4972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" cell $sshl $sshl$libresoc.v:128379$4973 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 connect \Y $sshl$libresoc.v:128379$4973_Y end attribute \src "libresoc.v:128294.7-128294.20" process $proc$libresoc.v:128294$4984 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:128382.3-128428.6" process $proc$libresoc.v:128382$4976 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] attribute \src "libresoc.v:128383.5-128383.29" switch \initial attribute \src "libresoc.v:128383.9-128383.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b[63:0] \$1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b[63:0] \$3 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b[63:0] \$7 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b[63:0] \$9 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b[63:0] \$11 case assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \imm_b $0\imm_b[63:0] end attribute \src "libresoc.v:128429.3-128475.6" process $proc$libresoc.v:128429$4977 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] attribute \src "libresoc.v:128430.5-128430.29" switch \initial attribute \src "libresoc.v:128430.9-128430.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $1\imm_b_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $1\imm_b_ok[0:0] 1'1 case assign $1\imm_b_ok[0:0] 1'0 end sync always update \imm_b_ok $0\imm_b_ok[0:0] end attribute \src "libresoc.v:128476.3-128490.6" process $proc$libresoc.v:128476$4978 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] attribute \src "libresoc.v:128477.5-128477.29" switch \initial attribute \src "libresoc.v:128477.9-128477.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \LDST_SI case assign $1\si[15:0] 16'0000000000000000 end sync always update \si $0\si[15:0] end attribute \src "libresoc.v:128491.3-128509.6" process $proc$libresoc.v:128491$4979 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] attribute \src "libresoc.v:128492.5-128492.29" switch \initial attribute \src "libresoc.v:128492.9-128492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\si_hi[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] case assign $1\si_hi[31:0] 0 end sync always update \si_hi $0\si_hi[31:0] end attribute \src "libresoc.v:128510.3-128532.6" process $proc$libresoc.v:128510$4980 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] attribute \src "libresoc.v:128511.5-128511.29" switch \initial attribute \src "libresoc.v:128511.9-128511.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ui[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \LDST_UI case assign $1\ui[15:0] 16'0000000000000000 end sync always update \ui $0\ui[15:0] end attribute \src "libresoc.v:128533.3-128559.6" process $proc$libresoc.v:128533$4981 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] attribute \src "libresoc.v:128534.5-128534.29" switch \initial attribute \src "libresoc.v:128534.9-128534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\li[25:0] 26'00000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] case assign $1\li[25:0] 26'00000000000000000000000000 end sync always update \li $0\li[25:0] end attribute \src "libresoc.v:128560.3-128590.6" process $proc$libresoc.v:128560$4982 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] attribute \src "libresoc.v:128561.5-128561.29" switch \initial attribute \src "libresoc.v:128561.9-128561.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\bd[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] case assign $1\bd[15:0] 16'0000000000000000 end sync always update \bd $0\bd[15:0] end attribute \src "libresoc.v:128591.3-128625.6" process $proc$libresoc.v:128591$4983 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] attribute \src "libresoc.v:128592.5-128592.29" switch \initial attribute \src "libresoc.v:128592.9-128592.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $1\ds[15:0] 16'0000000000000000 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] case assign $1\ds[15:0] 16'0000000000000000 end sync always update \ds $0\ds[15:0] end connect \$9 $pos$libresoc.v:128372$4964_Y connect \$11 $pos$libresoc.v:128373$4966_Y connect \$14 $sshl$libresoc.v:128374$4967_Y connect \$17 $sshl$libresoc.v:128375$4968_Y connect \$1 $pos$libresoc.v:128376$4970_Y connect \$20 $sshl$libresoc.v:128377$4971_Y connect \$23 $sshl$libresoc.v:128378$4972_Y connect \$4 $sshl$libresoc.v:128379$4973_Y connect \$3 $pos$libresoc.v:128380$4975_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end attribute \src "libresoc.v:128634.1-128682.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c attribute \src "libresoc.v:128635.7-128635.20" wire $0\initial[0:0] attribute \src "libresoc.v:128652.3-128666.6" wire width 5 $0\reg_c[4:0] attribute \src "libresoc.v:128667.3-128681.6" wire $0\reg_c_ok[0:0] attribute \src "libresoc.v:128652.3-128666.6" wire width 5 $1\reg_c[4:0] attribute \src "libresoc.v:128667.3-128681.6" wire $1\reg_c_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 4 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \RS attribute \src "libresoc.v:128635.7-128635.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 1 \reg_c attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \reg_c_ok attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" wire width 2 input 5 \sel_in attribute \src "libresoc.v:128635.7-128635.20" process $proc$libresoc.v:128635$4987 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:128652.3-128666.6" process $proc$libresoc.v:128652$4985 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] attribute \src "libresoc.v:128653.5-128653.29" switch \initial attribute \src "libresoc.v:128653.9-128653.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\reg_c[4:0] \RB attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\reg_c[4:0] \RS case assign $1\reg_c[4:0] 5'00000 end sync always update \reg_c $0\reg_c[4:0] end attribute \src "libresoc.v:128667.3-128681.6" process $proc$libresoc.v:128667$4986 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] attribute \src "libresoc.v:128668.5-128668.29" switch \initial attribute \src "libresoc.v:128668.9-128668.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\reg_c_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\reg_c_ok[0:0] 1'1 case assign $1\reg_c_ok[0:0] 1'0 end sync always update \reg_c_ok $0\reg_c_ok[0:0] end end attribute \src "libresoc.v:128686.1-129222.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in attribute \src "libresoc.v:129042.3-129076.6" wire width 3 $0\cr_bitfield[2:0] attribute \src "libresoc.v:129077.3-129107.6" wire width 3 $0\cr_bitfield_b[2:0] attribute \src "libresoc.v:128875.3-128905.6" wire $0\cr_bitfield_b_ok[0:0] attribute \src "libresoc.v:129108.3-129138.6" wire width 3 $0\cr_bitfield_o[2:0] attribute \src "libresoc.v:128953.3-128983.6" wire $0\cr_bitfield_o_ok[0:0] attribute \src "libresoc.v:128840.3-128874.6" wire $0\cr_bitfield_ok[0:0] attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $0\cr_fxm[7:0] attribute \src "libresoc.v:128984.3-129022.6" wire $0\cr_fxm_ok[0:0] attribute \src "libresoc.v:128687.7-128687.20" wire $0\initial[0:0] attribute \src "libresoc.v:129139.3-129177.6" wire $0\move_one[0:0] attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $0\ppick_i[7:0] attribute \src "libresoc.v:129023.3-129041.6" wire width 2 $0\sv_override[1:0] attribute \src "libresoc.v:129042.3-129076.6" wire width 3 $1\cr_bitfield[2:0] attribute \src "libresoc.v:129077.3-129107.6" wire width 3 $1\cr_bitfield_b[2:0] attribute \src "libresoc.v:128875.3-128905.6" wire $1\cr_bitfield_b_ok[0:0] attribute \src "libresoc.v:129108.3-129138.6" wire width 3 $1\cr_bitfield_o[2:0] attribute \src "libresoc.v:128953.3-128983.6" wire $1\cr_bitfield_o_ok[0:0] attribute \src "libresoc.v:128840.3-128874.6" wire $1\cr_bitfield_ok[0:0] attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $1\cr_fxm[7:0] attribute \src "libresoc.v:128984.3-129022.6" wire $1\cr_fxm_ok[0:0] attribute \src "libresoc.v:129139.3-129177.6" wire $1\move_one[0:0] attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $1\ppick_i[7:0] attribute \src "libresoc.v:129023.3-129041.6" wire width 2 $1\sv_override[1:0] attribute \src "libresoc.v:128906.3-128952.6" wire width 8 $2\cr_fxm[7:0] attribute \src "libresoc.v:129178.3-129221.6" wire width 8 $2\ppick_i[7:0] attribute \src "libresoc.v:128833.17-128833.112" wire $and$libresoc.v:128833$4989_Y attribute \src "libresoc.v:128835.17-128835.112" wire $and$libresoc.v:128835$4991_Y attribute \src "libresoc.v:128832.17-128832.117" wire $eq$libresoc.v:128832$4988_Y attribute \src "libresoc.v:128834.17-128834.117" wire $eq$libresoc.v:128834$4990_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 12 \BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 16 \BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 15 \BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 13 \BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 input 14 \FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 17 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 5 \cr_bitfield attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 7 \cr_bitfield_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 8 \cr_bitfield_b_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 9 \cr_bitfield_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 10 \cr_bitfield_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \cr_bitfield_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 3 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \cr_fxm_ok attribute \src "libresoc.v:128687.7-128687.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 18 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BI" attribute \enum_value_011 "BFA" attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" wire width 3 input 2 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" wire width 2 \sv_override attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" cell $and $and$libresoc.v:128833$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one connect \Y $and$libresoc.v:128833$4989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" cell $and $and$libresoc.v:128835$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one connect \Y $and$libresoc.v:128835$4991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" cell $eq $eq$libresoc.v:128832$4988 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 connect \Y $eq$libresoc.v:128832$4988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" cell $eq $eq$libresoc.v:128834$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 connect \Y $eq$libresoc.v:128834$4990_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:128836.9-128839.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end attribute \src "libresoc.v:128687.7-128687.20" process $proc$libresoc.v:128687$5003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:128840.3-128874.6" process $proc$libresoc.v:128840$4992 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] attribute \src "libresoc.v:128841.5-128841.29" switch \initial attribute \src "libresoc.v:128841.9-128841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 case assign $1\cr_bitfield_ok[0:0] 1'0 end sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end attribute \src "libresoc.v:128875.3-128905.6" process $proc$libresoc.v:128875$4993 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] attribute \src "libresoc.v:128876.5-128876.29" switch \initial attribute \src "libresoc.v:128876.9-128876.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield_b_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_bitfield_b_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\cr_bitfield_b_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_bitfield_b_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_bitfield_b_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_b_ok[0:0] 1'1 case assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end attribute \src "libresoc.v:128906.3-128952.6" process $proc$libresoc.v:128906$4994 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] attribute \src "libresoc.v:128907.5-128907.29" switch \initial attribute \src "libresoc.v:128907.9-128907.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] \ppick_o attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cr_fxm[7:0] 8'11111111 end case assign $1\cr_fxm[7:0] 8'00000000 end sync always update \cr_fxm $0\cr_fxm[7:0] end attribute \src "libresoc.v:128953.3-128983.6" process $proc$libresoc.v:128953$4995 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] attribute \src "libresoc.v:128954.5-128954.29" switch \initial attribute \src "libresoc.v:128954.9-128954.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_bitfield_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\cr_bitfield_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_bitfield_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_bitfield_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_o_ok[0:0] 1'1 case assign $1\cr_bitfield_o_ok[0:0] 1'0 end sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end attribute \src "libresoc.v:128984.3-129022.6" process $proc$libresoc.v:128984$4996 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] attribute \src "libresoc.v:128985.5-128985.29" switch \initial attribute \src "libresoc.v:128985.9-128985.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm_ok[0:0] 1'1 case assign $1\cr_fxm_ok[0:0] 1'0 end sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end attribute \src "libresoc.v:129023.3-129041.6" process $proc$libresoc.v:129023$4997 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] attribute \src "libresoc.v:129024.5-129024.29" switch \initial attribute \src "libresoc.v:129024.9-129024.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\sv_override[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\sv_override[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\sv_override[1:0] 2'10 case assign $1\sv_override[1:0] 2'00 end sync always update \sv_override $0\sv_override[1:0] end attribute \src "libresoc.v:129042.3-129076.6" process $proc$libresoc.v:129042$4998 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] attribute \src "libresoc.v:129043.5-129043.29" switch \initial attribute \src "libresoc.v:129043.9-129043.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\cr_bitfield[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\cr_bitfield[2:0] \BI [4:2] attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\cr_bitfield[2:0] \X_BFA attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield[2:0] \BA [4:2] attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\cr_bitfield[2:0] \BC [4:2] case assign $1\cr_bitfield[2:0] 3'000 end sync always update \cr_bitfield $0\cr_bitfield[2:0] end attribute \src "libresoc.v:129077.3-129107.6" process $proc$libresoc.v:129077$4999 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] attribute \src "libresoc.v:129078.5-129078.29" switch \initial attribute \src "libresoc.v:129078.9-129078.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield_b[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_bitfield_b[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\cr_bitfield_b[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_bitfield_b[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_bitfield_b[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_b[2:0] \BB [4:2] case assign $1\cr_bitfield_b[2:0] 3'000 end sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end attribute \src "libresoc.v:129108.3-129138.6" process $proc$libresoc.v:129108$5000 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] attribute \src "libresoc.v:129109.5-129109.29" switch \initial attribute \src "libresoc.v:129109.9-129109.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_bitfield_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\cr_bitfield_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_bitfield_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_bitfield_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_o[2:0] \BT [4:2] case assign $1\cr_bitfield_o[2:0] 3'000 end sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end attribute \src "libresoc.v:129139.3-129177.6" process $proc$libresoc.v:129139$5001 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] attribute \src "libresoc.v:129140.5-129140.29" switch \initial attribute \src "libresoc.v:129140.9-129140.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\move_one[0:0] \insn_in [20] case assign $1\move_one[0:0] 1'0 end sync always update \move_one $0\move_one[0:0] end attribute \src "libresoc.v:129178.3-129221.6" process $proc$libresoc.v:129178$5002 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] attribute \src "libresoc.v:129179.5-129179.29" switch \initial attribute \src "libresoc.v:129179.9-129179.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] \FXM case assign $2\ppick_i[7:0] 8'00000000 end case assign $1\ppick_i[7:0] 8'00000000 end sync always update \ppick_i $0\ppick_i[7:0] end connect \$1 $eq$libresoc.v:128832$4988_Y connect \$3 $and$libresoc.v:128833$4989_Y connect \$5 $eq$libresoc.v:128834$4990_Y connect \$7 $and$libresoc.v:128835$4991_Y end attribute \src "libresoc.v:129226.1-129588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out attribute \src "libresoc.v:129434.3-129460.6" wire width 3 $0\cr_bitfield[2:0] attribute \src "libresoc.v:129357.3-129383.6" wire $0\cr_bitfield_ok[0:0] attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $0\cr_fxm[7:0] attribute \src "libresoc.v:129384.3-129414.6" wire $0\cr_fxm_ok[0:0] attribute \src "libresoc.v:129227.7-129227.20" wire $0\initial[0:0] attribute \src "libresoc.v:129461.3-129491.6" wire $0\move_one[0:0] attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $0\ppick_i[7:0] attribute \src "libresoc.v:129415.3-129433.6" wire width 2 $0\sv_override[1:0] attribute \src "libresoc.v:129434.3-129460.6" wire width 3 $1\cr_bitfield[2:0] attribute \src "libresoc.v:129357.3-129383.6" wire $1\cr_bitfield_ok[0:0] attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $1\cr_fxm[7:0] attribute \src "libresoc.v:129384.3-129414.6" wire $1\cr_fxm_ok[0:0] attribute \src "libresoc.v:129461.3-129491.6" wire $1\move_one[0:0] attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $1\ppick_i[7:0] attribute \src "libresoc.v:129415.3-129433.6" wire width 2 $1\sv_override[1:0] attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $2\cr_fxm[7:0] attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $2\ppick_i[7:0] attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $3\cr_fxm[7:0] attribute \src "libresoc.v:129492.3-129532.6" wire width 8 $3\ppick_i[7:0] attribute \src "libresoc.v:129533.3-129587.6" wire width 8 $4\cr_fxm[7:0] attribute \src "libresoc.v:129350.17-129350.117" wire $eq$libresoc.v:129350$5004_Y attribute \src "libresoc.v:129351.17-129351.117" wire $eq$libresoc.v:129351$5005_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 8 input 8 \FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 5 input 10 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" wire width 3 input 9 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 6 \cr_bitfield attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 7 \cr_bitfield_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 output 4 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \cr_fxm_ok attribute \src "libresoc.v:129227.7-129227.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 11 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:659" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \ppick_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" wire input 3 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" wire width 3 input 2 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621" wire width 2 \sv_override attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" cell $eq $eq$libresoc.v:129350$5004 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 connect \Y $eq$libresoc.v:129350$5004_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" cell $eq $eq$libresoc.v:129351$5005 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 connect \Y $eq$libresoc.v:129351$5005_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:129352.15-129356.4" cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end attribute \src "libresoc.v:129227.7-129227.20" process $proc$libresoc.v:129227$5013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:129357.3-129383.6" process $proc$libresoc.v:129357$5006 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] attribute \src "libresoc.v:129358.5-129358.29" switch \initial attribute \src "libresoc.v:129358.9-129358.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 case assign $1\cr_bitfield_ok[0:0] 1'0 end sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end attribute \src "libresoc.v:129384.3-129414.6" process $proc$libresoc.v:129384$5007 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] attribute \src "libresoc.v:129385.5-129385.29" switch \initial attribute \src "libresoc.v:129385.9-129385.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_fxm_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm_ok[0:0] 1'1 case assign $1\cr_fxm_ok[0:0] 1'0 end sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end attribute \src "libresoc.v:129415.3-129433.6" process $proc$libresoc.v:129415$5008 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] attribute \src "libresoc.v:129416.5-129416.29" switch \initial attribute \src "libresoc.v:129416.9-129416.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\sv_override[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\sv_override[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\sv_override[1:0] 2'10 case assign $1\sv_override[1:0] 2'00 end sync always update \sv_override $0\sv_override[1:0] end attribute \src "libresoc.v:129434.3-129460.6" process $proc$libresoc.v:129434$5009 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] attribute \src "libresoc.v:129435.5-129435.29" switch \initial attribute \src "libresoc.v:129435.9-129435.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\cr_bitfield[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\cr_bitfield[2:0] \XL_BT [4:2] case assign $1\cr_bitfield[2:0] 3'000 end sync always update \cr_bitfield $0\cr_bitfield[2:0] end attribute \src "libresoc.v:129461.3-129491.6" process $proc$libresoc.v:129461$5010 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] attribute \src "libresoc.v:129462.5-129462.29" switch \initial attribute \src "libresoc.v:129462.9-129462.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\move_one[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\move_one[0:0] \insn_in [20] case assign $1\move_one[0:0] 1'0 end sync always update \move_one $0\move_one[0:0] end attribute \src "libresoc.v:129492.3-129532.6" process $proc$libresoc.v:129492$5011 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] attribute \src "libresoc.v:129493.5-129493.29" switch \initial attribute \src "libresoc.v:129493.9-129493.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\ppick_i[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ppick_i[7:0] \FXM case assign $3\ppick_i[7:0] 8'00000000 end case assign $2\ppick_i[7:0] 8'00000000 end case assign $1\ppick_i[7:0] 8'00000000 end sync always update \ppick_i $0\ppick_i[7:0] end attribute \src "libresoc.v:129533.3-129587.6" process $proc$libresoc.v:129533$5012 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] attribute \src "libresoc.v:129534.5-129534.29" switch \initial attribute \src "libresoc.v:129534.9-129534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\cr_fxm[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\cr_fxm[7:0] \ppick_o attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $4\cr_fxm[7:0] 8'00000001 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\cr_fxm[7:0] \FXM end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cr_fxm[7:0] 8'11111111 end case assign $1\cr_fxm[7:0] 8'00000000 end sync always update \cr_fxm $0\cr_fxm[7:0] end connect \$1 $eq$libresoc.v:129350$5004_Y connect \$3 $eq$libresoc.v:129351$5005_Y end attribute \src "libresoc.v:129592.1-130109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $0\fast_o[2:0] attribute \src "libresoc.v:130062.3-130108.6" wire $0\fast_o_ok[0:0] attribute \src "libresoc.v:129593.7-129593.20" wire $0\initial[0:0] attribute \src "libresoc.v:129964.3-129978.6" wire width 5 $0\reg_o[4:0] attribute \src "libresoc.v:129979.3-129993.6" wire $0\reg_o_ok[0:0] attribute \src "libresoc.v:129994.3-130012.6" wire width 10 $0\spr[9:0] attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $0\spr_o[9:0] attribute \src "libresoc.v:130037.3-130061.6" wire $0\spr_o_ok[0:0] attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $0\sprmap_spr_i[9:0] attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $1\fast_o[2:0] attribute \src "libresoc.v:130062.3-130108.6" wire $1\fast_o_ok[0:0] attribute \src "libresoc.v:129964.3-129978.6" wire width 5 $1\reg_o[4:0] attribute \src "libresoc.v:129979.3-129993.6" wire $1\reg_o_ok[0:0] attribute \src "libresoc.v:129994.3-130012.6" wire width 10 $1\spr[9:0] attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $1\spr_o[9:0] attribute \src "libresoc.v:130037.3-130061.6" wire $1\spr_o_ok[0:0] attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $1\sprmap_spr_i[9:0] attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $2\fast_o[2:0] attribute \src "libresoc.v:130062.3-130108.6" wire $2\fast_o_ok[0:0] attribute \src "libresoc.v:130037.3-130061.6" wire width 10 $2\spr_o[9:0] attribute \src "libresoc.v:130037.3-130061.6" wire $2\spr_o_ok[0:0] attribute \src "libresoc.v:130013.3-130036.6" wire width 10 $2\sprmap_spr_i[9:0] attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $3\fast_o[2:0] attribute \src "libresoc.v:130062.3-130108.6" wire $3\fast_o_ok[0:0] attribute \src "libresoc.v:130062.3-130108.6" wire width 3 $4\fast_o[2:0] attribute \src "libresoc.v:130062.3-130108.6" wire $4\fast_o_ok[0:0] attribute \src "libresoc.v:129953.17-129953.117" wire $eq$libresoc.v:129953$5014_Y attribute \src "libresoc.v:129954.17-129954.117" wire $eq$libresoc.v:129954$5015_Y attribute \src "libresoc.v:129955.17-129955.117" wire $eq$libresoc.v:129955$5016_Y attribute \src "libresoc.v:129956.17-129956.104" wire $not$libresoc.v:129956$5017_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 11 \BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 10 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 9 \RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 10 input 1 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 7 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 8 \fast_o_ok attribute \src "libresoc.v:129593.7-129593.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 12 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 3 \reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \reg_o_ok attribute \enum_base_type "OutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RT" attribute \enum_value_010 "RA" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RT_OR_ZERO" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 3 input 2 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 5 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 6 \spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_fast_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \sprmap_spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" cell $eq $eq$libresoc.v:129953$5014 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:129953$5014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" cell $eq $eq$libresoc.v:129954$5015 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:129954$5015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" cell $eq $eq$libresoc.v:129955$5016 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 connect \Y $eq$libresoc.v:129955$5016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" cell $not $not$libresoc.v:129956$5017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] connect \Y $not$libresoc.v:129956$5017_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:129957.16-129963.4" cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok connect \spr_i \sprmap_spr_i connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end attribute \src "libresoc.v:129593.7-129593.20" process $proc$libresoc.v:129593$5024 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:129964.3-129978.6" process $proc$libresoc.v:129964$5018 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] attribute \src "libresoc.v:129965.5-129965.29" switch \initial attribute \src "libresoc.v:129965.9-129965.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\reg_o[4:0] \RT attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\reg_o[4:0] \RA case assign $1\reg_o[4:0] 5'00000 end sync always update \reg_o $0\reg_o[4:0] end attribute \src "libresoc.v:129979.3-129993.6" process $proc$libresoc.v:129979$5019 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] attribute \src "libresoc.v:129980.5-129980.29" switch \initial attribute \src "libresoc.v:129980.9-129980.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\reg_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\reg_o_ok[0:0] 1'1 case assign $1\reg_o_ok[0:0] 1'0 end sync always update \reg_o_ok $0\reg_o_ok[0:0] end attribute \src "libresoc.v:129994.3-130012.6" process $proc$libresoc.v:129994$5020 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] attribute \src "libresoc.v:129995.5-129995.29" switch \initial attribute \src "libresoc.v:129995.9-129995.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\spr[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\spr[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case assign $1\spr[9:0] 10'0000000000 end sync always update \spr $0\spr[9:0] end attribute \src "libresoc.v:130013.3-130036.6" process $proc$libresoc.v:130013$5021 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] attribute \src "libresoc.v:130014.5-130014.29" switch \initial attribute \src "libresoc.v:130014.9-130014.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\sprmap_spr_i[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\sprmap_spr_i[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sprmap_spr_i[9:0] \spr case assign $2\sprmap_spr_i[9:0] 10'0000000000 end case assign $1\sprmap_spr_i[9:0] 10'0000000000 end sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end attribute \src "libresoc.v:130037.3-130061.6" process $proc$libresoc.v:130037$5022 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] attribute \src "libresoc.v:130038.5-130038.29" switch \initial attribute \src "libresoc.v:130038.9-130038.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\spr_o[9:0] 10'0000000000 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\spr_o[9:0] 10'0000000000 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign { } { } assign $1\spr_o[9:0] $2\spr_o[9:0] assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } case assign $2\spr_o[9:0] 10'0000000000 assign $2\spr_o_ok[0:0] 1'0 end case assign $1\spr_o[9:0] 10'0000000000 assign $1\spr_o_ok[0:0] 1'0 end sync always update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end attribute \src "libresoc.v:130062.3-130108.6" process $proc$libresoc.v:130062$5023 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] attribute \src "libresoc.v:130063.5-130063.29" switch \initial attribute \src "libresoc.v:130063.9-130063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } case assign $2\fast_o[2:0] 3'000 assign $2\fast_o_ok[0:0] 1'0 end case assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:382" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0001000 assign { } { } assign { } { } assign $3\fast_o[2:0] $4\fast_o[2:0] assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $4\fast_o[2:0] 3'000 assign $4\fast_o_ok[0:0] 1'1 case assign $4\fast_o[2:0] $1\fast_o[2:0] assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] end attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { } { } assign { } { } assign $3\fast_o[2:0] 3'011 assign $3\fast_o_ok[0:0] 1'1 case assign $3\fast_o[2:0] $1\fast_o[2:0] assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] end sync always update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end connect \$1 $eq$libresoc.v:129953$5014_Y connect \$3 $eq$libresoc.v:129954$5015_Y connect \$5 $eq$libresoc.v:129955$5016_Y connect \$7 $not$libresoc.v:129956$5017_Y end attribute \src "libresoc.v:130113.1-130281.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $0\fast_o2[2:0] attribute \src "libresoc.v:130261.3-130280.6" wire $0\fast_o2_ok[0:0] attribute \src "libresoc.v:130114.7-130114.20" wire $0\initial[0:0] attribute \src "libresoc.v:130221.3-130230.6" wire width 5 $0\reg_o2[4:0] attribute \src "libresoc.v:130231.3-130240.6" wire $0\reg_o2_ok[0:0] attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $1\fast_o2[2:0] attribute \src "libresoc.v:130261.3-130280.6" wire $1\fast_o2_ok[0:0] attribute \src "libresoc.v:130221.3-130230.6" wire width 5 $1\reg_o2[4:0] attribute \src "libresoc.v:130231.3-130240.6" wire $1\reg_o2_ok[0:0] attribute \src "libresoc.v:130241.3-130260.6" wire width 3 $2\fast_o2[2:0] attribute \src "libresoc.v:130261.3-130280.6" wire $2\fast_o2_ok[0:0] attribute \src "libresoc.v:130219.17-130219.108" wire $eq$libresoc.v:130219$5025_Y attribute \src "libresoc.v:130220.17-130220.108" wire $eq$libresoc.v:130220$5026_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 7 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 4 \fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 5 \fast_o2_ok attribute \src "libresoc.v:130114.7-130114.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 8 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" wire input 1 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 5 output 2 \reg_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \reg_o2_ok attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 input 6 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" cell $eq $eq$libresoc.v:130219$5025 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 connect \Y $eq$libresoc.v:130219$5025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" cell $eq $eq$libresoc.v:130220$5026 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 connect \Y $eq$libresoc.v:130220$5026_Y end attribute \src "libresoc.v:130114.7-130114.20" process $proc$libresoc.v:130114$5031 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:130221.3-130230.6" process $proc$libresoc.v:130221$5027 assign { } { } assign { } { } assign $0\reg_o2[4:0] $1\reg_o2[4:0] attribute \src "libresoc.v:130222.5-130222.29" switch \initial attribute \src "libresoc.v:130222.9-130222.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg_o2[4:0] \RA case assign $1\reg_o2[4:0] 5'00000 end sync always update \reg_o2 $0\reg_o2[4:0] end attribute \src "libresoc.v:130231.3-130240.6" process $proc$libresoc.v:130231$5028 assign { } { } assign { } { } assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] attribute \src "libresoc.v:130232.5-130232.29" switch \initial attribute \src "libresoc.v:130232.9-130232.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg_o2_ok[0:0] 1'1 case assign $1\reg_o2_ok[0:0] 1'0 end sync always update \reg_o2_ok $0\reg_o2_ok[0:0] end attribute \src "libresoc.v:130241.3-130260.6" process $proc$libresoc.v:130241$5029 assign { } { } assign { } { } assign $0\fast_o2[2:0] $1\fast_o2[2:0] attribute \src "libresoc.v:130242.5-130242.29" switch \initial attribute \src "libresoc.v:130242.9-130242.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2[2:0] $2\fast_o2[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast_o2[2:0] 3'001 case assign $2\fast_o2[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { } { } assign $1\fast_o2[2:0] 3'100 case assign $1\fast_o2[2:0] 3'000 end sync always update \fast_o2 $0\fast_o2[2:0] end attribute \src "libresoc.v:130261.3-130280.6" process $proc$libresoc.v:130261$5030 assign { } { } assign { } { } assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] attribute \src "libresoc.v:130262.5-130262.29" switch \initial attribute \src "libresoc.v:130262.9-130262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast_o2_ok[0:0] 1'1 case assign $2\fast_o2_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { } { } assign $1\fast_o2_ok[0:0] 1'1 case assign $1\fast_o2_ok[0:0] 1'0 end sync always update \fast_o2_ok $0\fast_o2_ok[0:0] end connect \$1 $eq$libresoc.v:130219$5025_Y connect \$3 $eq$libresoc.v:130220$5026_Y end attribute \src "libresoc.v:130285.1-130420.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe attribute \src "libresoc.v:130286.7-130286.20" wire $0\initial[0:0] attribute \src "libresoc.v:130378.3-130398.6" wire $0\oe[0:0] attribute \src "libresoc.v:130399.3-130419.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:130378.3-130398.6" wire $1\oe[0:0] attribute \src "libresoc.v:130399.3-130419.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:130378.3-130398.6" wire $2\oe[0:0] attribute \src "libresoc.v:130399.3-130419.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \ALU_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \ALU_internal_op attribute \src "libresoc.v:130286.7-130286.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in attribute \src "libresoc.v:130286.7-130286.20" process $proc$libresoc.v:130286$5034 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:130378.3-130398.6" process $proc$libresoc.v:130378$5032 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:130379.5-130379.29" switch \initial attribute \src "libresoc.v:130379.9-130379.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \ALU_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:130399.3-130419.6" process $proc$libresoc.v:130399$5033 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:130400.5-130400.29" switch \initial attribute \src "libresoc.v:130400.9-130400.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:130424.1-130557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" module \dec_oe$140 attribute \src "libresoc.v:130425.7-130425.20" wire $0\initial[0:0] attribute \src "libresoc.v:130515.3-130535.6" wire $0\oe[0:0] attribute \src "libresoc.v:130536.3-130556.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:130515.3-130535.6" wire $1\oe[0:0] attribute \src "libresoc.v:130536.3-130556.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:130515.3-130535.6" wire $2\oe[0:0] attribute \src "libresoc.v:130536.3-130556.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \CR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \CR_internal_op attribute \src "libresoc.v:130425.7-130425.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in attribute \src "libresoc.v:130425.7-130425.20" process $proc$libresoc.v:130425$5037 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:130515.3-130535.6" process $proc$libresoc.v:130515$5035 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:130516.5-130516.29" switch \initial attribute \src "libresoc.v:130516.9-130516.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \CR_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:130536.3-130556.6" process $proc$libresoc.v:130536$5036 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:130537.5-130537.29" switch \initial attribute \src "libresoc.v:130537.9-130537.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:130561.1-130694.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" module \dec_oe$143 attribute \src "libresoc.v:130562.7-130562.20" wire $0\initial[0:0] attribute \src "libresoc.v:130652.3-130672.6" wire $0\oe[0:0] attribute \src "libresoc.v:130673.3-130693.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:130652.3-130672.6" wire $1\oe[0:0] attribute \src "libresoc.v:130673.3-130693.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:130652.3-130672.6" wire $2\oe[0:0] attribute \src "libresoc.v:130673.3-130693.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \BRANCH_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \BRANCH_internal_op attribute \src "libresoc.v:130562.7-130562.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in attribute \src "libresoc.v:130562.7-130562.20" process $proc$libresoc.v:130562$5040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:130652.3-130672.6" process $proc$libresoc.v:130652$5038 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:130653.5-130653.29" switch \initial attribute \src "libresoc.v:130653.9-130653.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \BRANCH_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:130673.3-130693.6" process $proc$libresoc.v:130673$5039 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:130674.5-130674.29" switch \initial attribute \src "libresoc.v:130674.9-130674.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:130698.1-130833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" module \dec_oe$147 attribute \src "libresoc.v:130699.7-130699.20" wire $0\initial[0:0] attribute \src "libresoc.v:130791.3-130811.6" wire $0\oe[0:0] attribute \src "libresoc.v:130812.3-130832.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:130791.3-130811.6" wire $1\oe[0:0] attribute \src "libresoc.v:130812.3-130832.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:130791.3-130811.6" wire $2\oe[0:0] attribute \src "libresoc.v:130812.3-130832.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LOGICAL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LOGICAL_internal_op attribute \src "libresoc.v:130699.7-130699.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in attribute \src "libresoc.v:130699.7-130699.20" process $proc$libresoc.v:130699$5043 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:130791.3-130811.6" process $proc$libresoc.v:130791$5041 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:130792.5-130792.29" switch \initial attribute \src "libresoc.v:130792.9-130792.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \LOGICAL_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:130812.3-130832.6" process $proc$libresoc.v:130812$5042 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:130813.5-130813.29" switch \initial attribute \src "libresoc.v:130813.9-130813.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:130837.1-130970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" module \dec_oe$152 attribute \src "libresoc.v:130838.7-130838.20" wire $0\initial[0:0] attribute \src "libresoc.v:130928.3-130948.6" wire $0\oe[0:0] attribute \src "libresoc.v:130949.3-130969.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:130928.3-130948.6" wire $1\oe[0:0] attribute \src "libresoc.v:130949.3-130969.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:130928.3-130948.6" wire $2\oe[0:0] attribute \src "libresoc.v:130949.3-130969.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \SPR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SPR_internal_op attribute \src "libresoc.v:130838.7-130838.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 3 \sel_in attribute \src "libresoc.v:130838.7-130838.20" process $proc$libresoc.v:130838$5046 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:130928.3-130948.6" process $proc$libresoc.v:130928$5044 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:130929.5-130929.29" switch \initial attribute \src "libresoc.v:130929.9-130929.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \SPR_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:130949.3-130969.6" process $proc$libresoc.v:130949$5045 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:130950.5-130950.29" switch \initial attribute \src "libresoc.v:130950.9-130950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:130974.1-131109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" module \dec_oe$155 attribute \src "libresoc.v:130975.7-130975.20" wire $0\initial[0:0] attribute \src "libresoc.v:131067.3-131087.6" wire $0\oe[0:0] attribute \src "libresoc.v:131088.3-131108.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:131067.3-131087.6" wire $1\oe[0:0] attribute \src "libresoc.v:131088.3-131108.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:131067.3-131087.6" wire $2\oe[0:0] attribute \src "libresoc.v:131088.3-131108.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \DIV_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \DIV_internal_op attribute \src "libresoc.v:130975.7-130975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in attribute \src "libresoc.v:130975.7-130975.20" process $proc$libresoc.v:130975$5049 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131067.3-131087.6" process $proc$libresoc.v:131067$5047 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:131068.5-131068.29" switch \initial attribute \src "libresoc.v:131068.9-131068.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \DIV_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:131088.3-131108.6" process $proc$libresoc.v:131088$5048 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:131089.5-131089.29" switch \initial attribute \src "libresoc.v:131089.9-131089.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:131113.1-131248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" module \dec_oe$160 attribute \src "libresoc.v:131114.7-131114.20" wire $0\initial[0:0] attribute \src "libresoc.v:131206.3-131226.6" wire $0\oe[0:0] attribute \src "libresoc.v:131227.3-131247.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:131206.3-131226.6" wire $1\oe[0:0] attribute \src "libresoc.v:131227.3-131247.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:131206.3-131226.6" wire $2\oe[0:0] attribute \src "libresoc.v:131227.3-131247.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \MUL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \MUL_internal_op attribute \src "libresoc.v:131114.7-131114.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in attribute \src "libresoc.v:131114.7-131114.20" process $proc$libresoc.v:131114$5052 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131206.3-131226.6" process $proc$libresoc.v:131206$5050 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:131207.5-131207.29" switch \initial attribute \src "libresoc.v:131207.9-131207.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \MUL_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:131227.3-131247.6" process $proc$libresoc.v:131227$5051 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:131228.5-131228.29" switch \initial attribute \src "libresoc.v:131228.9-131228.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:131252.1-131387.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" module \dec_oe$164 attribute \src "libresoc.v:131253.7-131253.20" wire $0\initial[0:0] attribute \src "libresoc.v:131345.3-131365.6" wire $0\oe[0:0] attribute \src "libresoc.v:131366.3-131386.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:131345.3-131365.6" wire $1\oe[0:0] attribute \src "libresoc.v:131366.3-131386.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:131345.3-131365.6" wire $2\oe[0:0] attribute \src "libresoc.v:131366.3-131386.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \SHIFT_ROT_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SHIFT_ROT_internal_op attribute \src "libresoc.v:131253.7-131253.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in attribute \src "libresoc.v:131253.7-131253.20" process $proc$libresoc.v:131253$5055 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131345.3-131365.6" process $proc$libresoc.v:131345$5053 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:131346.5-131346.29" switch \initial attribute \src "libresoc.v:131346.9-131346.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \SHIFT_ROT_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:131366.3-131386.6" process $proc$libresoc.v:131366$5054 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:131367.5-131367.29" switch \initial attribute \src "libresoc.v:131367.9-131367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:131391.1-131526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" module \dec_oe$168 attribute \src "libresoc.v:131392.7-131392.20" wire $0\initial[0:0] attribute \src "libresoc.v:131484.3-131504.6" wire $0\oe[0:0] attribute \src "libresoc.v:131505.3-131525.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:131484.3-131504.6" wire $1\oe[0:0] attribute \src "libresoc.v:131505.3-131525.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:131484.3-131504.6" wire $2\oe[0:0] attribute \src "libresoc.v:131505.3-131525.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LDST_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LDST_internal_op attribute \src "libresoc.v:131392.7-131392.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in attribute \src "libresoc.v:131392.7-131392.20" process $proc$libresoc.v:131392$5058 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131484.3-131504.6" process $proc$libresoc.v:131484$5056 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:131485.5-131485.29" switch \initial attribute \src "libresoc.v:131485.9-131485.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \LDST_OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:131505.3-131525.6" process $proc$libresoc.v:131505$5057 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:131506.5-131506.29" switch \initial attribute \src "libresoc.v:131506.9-131506.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:131530.1-131665.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" module \dec_oe$173 attribute \src "libresoc.v:131531.7-131531.20" wire $0\initial[0:0] attribute \src "libresoc.v:131623.3-131643.6" wire $0\oe[0:0] attribute \src "libresoc.v:131644.3-131664.6" wire $0\oe_ok[0:0] attribute \src "libresoc.v:131623.3-131643.6" wire $1\oe[0:0] attribute \src "libresoc.v:131644.3-131664.6" wire $1\oe_ok[0:0] attribute \src "libresoc.v:131623.3-131643.6" wire $2\oe[0:0] attribute \src "libresoc.v:131644.3-131664.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \OE attribute \src "libresoc.v:131531.7-131531.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" wire width 2 input 5 \sel_in attribute \src "libresoc.v:131531.7-131531.20" process $proc$libresoc.v:131531$5061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131623.3-131643.6" process $proc$libresoc.v:131623$5059 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] attribute \src "libresoc.v:131624.5-131624.29" switch \initial attribute \src "libresoc.v:131624.9-131624.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe[0:0] $2\oe[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe[0:0] \OE case assign $2\oe[0:0] 1'0 end end sync always update \oe $0\oe[0:0] end attribute \src "libresoc.v:131644.3-131664.6" process $proc$libresoc.v:131644$5060 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] attribute \src "libresoc.v:131645.5-131645.29" switch \initial attribute \src "libresoc.v:131645.9-131645.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\oe_ok[0:0] 1'1 case assign $2\oe_ok[0:0] 1'0 end end sync always update \oe_ok $0\oe_ok[0:0] end end attribute \src "libresoc.v:131669.1-131723.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc attribute \src "libresoc.v:131670.7-131670.20" wire $0\initial[0:0] attribute \src "libresoc.v:131685.3-131703.6" wire $0\rc[0:0] attribute \src "libresoc.v:131704.3-131722.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:131685.3-131703.6" wire $1\rc[0:0] attribute \src "libresoc.v:131704.3-131722.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \ALU_Rc attribute \src "libresoc.v:131670.7-131670.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in attribute \src "libresoc.v:131670.7-131670.20" process $proc$libresoc.v:131670$5064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131685.3-131703.6" process $proc$libresoc.v:131685$5062 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:131686.5-131686.29" switch \initial attribute \src "libresoc.v:131686.9-131686.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \ALU_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:131704.3-131722.6" process $proc$libresoc.v:131704$5063 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:131705.5-131705.29" switch \initial attribute \src "libresoc.v:131705.9-131705.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:131727.1-131779.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" module \dec_rc$139 attribute \src "libresoc.v:131728.7-131728.20" wire $0\initial[0:0] attribute \src "libresoc.v:131741.3-131759.6" wire $0\rc[0:0] attribute \src "libresoc.v:131760.3-131778.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:131741.3-131759.6" wire $1\rc[0:0] attribute \src "libresoc.v:131760.3-131778.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \CR_Rc attribute \src "libresoc.v:131728.7-131728.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in attribute \src "libresoc.v:131728.7-131728.20" process $proc$libresoc.v:131728$5067 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131741.3-131759.6" process $proc$libresoc.v:131741$5065 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:131742.5-131742.29" switch \initial attribute \src "libresoc.v:131742.9-131742.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \CR_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:131760.3-131778.6" process $proc$libresoc.v:131760$5066 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:131761.5-131761.29" switch \initial attribute \src "libresoc.v:131761.9-131761.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:131783.1-131835.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" module \dec_rc$142 attribute \src "libresoc.v:131784.7-131784.20" wire $0\initial[0:0] attribute \src "libresoc.v:131797.3-131815.6" wire $0\rc[0:0] attribute \src "libresoc.v:131816.3-131834.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:131797.3-131815.6" wire $1\rc[0:0] attribute \src "libresoc.v:131816.3-131834.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \BRANCH_Rc attribute \src "libresoc.v:131784.7-131784.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in attribute \src "libresoc.v:131784.7-131784.20" process $proc$libresoc.v:131784$5070 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131797.3-131815.6" process $proc$libresoc.v:131797$5068 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:131798.5-131798.29" switch \initial attribute \src "libresoc.v:131798.9-131798.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \BRANCH_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:131816.3-131834.6" process $proc$libresoc.v:131816$5069 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:131817.5-131817.29" switch \initial attribute \src "libresoc.v:131817.9-131817.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:131839.1-131893.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" module \dec_rc$146 attribute \src "libresoc.v:131840.7-131840.20" wire $0\initial[0:0] attribute \src "libresoc.v:131855.3-131873.6" wire $0\rc[0:0] attribute \src "libresoc.v:131874.3-131892.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:131855.3-131873.6" wire $1\rc[0:0] attribute \src "libresoc.v:131874.3-131892.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LOGICAL_Rc attribute \src "libresoc.v:131840.7-131840.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in attribute \src "libresoc.v:131840.7-131840.20" process $proc$libresoc.v:131840$5073 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131855.3-131873.6" process $proc$libresoc.v:131855$5071 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:131856.5-131856.29" switch \initial attribute \src "libresoc.v:131856.9-131856.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \LOGICAL_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:131874.3-131892.6" process $proc$libresoc.v:131874$5072 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:131875.5-131875.29" switch \initial attribute \src "libresoc.v:131875.9-131875.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:131897.1-131949.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" module \dec_rc$151 attribute \src "libresoc.v:131898.7-131898.20" wire $0\initial[0:0] attribute \src "libresoc.v:131911.3-131929.6" wire $0\rc[0:0] attribute \src "libresoc.v:131930.3-131948.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:131911.3-131929.6" wire $1\rc[0:0] attribute \src "libresoc.v:131930.3-131948.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \SPR_Rc attribute \src "libresoc.v:131898.7-131898.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 2 \sel_in attribute \src "libresoc.v:131898.7-131898.20" process $proc$libresoc.v:131898$5076 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131911.3-131929.6" process $proc$libresoc.v:131911$5074 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:131912.5-131912.29" switch \initial attribute \src "libresoc.v:131912.9-131912.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \SPR_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:131930.3-131948.6" process $proc$libresoc.v:131930$5075 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:131931.5-131931.29" switch \initial attribute \src "libresoc.v:131931.9-131931.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:131953.1-132007.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" module \dec_rc$154 attribute \src "libresoc.v:131954.7-131954.20" wire $0\initial[0:0] attribute \src "libresoc.v:131969.3-131987.6" wire $0\rc[0:0] attribute \src "libresoc.v:131988.3-132006.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:131969.3-131987.6" wire $1\rc[0:0] attribute \src "libresoc.v:131988.3-132006.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \DIV_Rc attribute \src "libresoc.v:131954.7-131954.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in attribute \src "libresoc.v:131954.7-131954.20" process $proc$libresoc.v:131954$5079 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:131969.3-131987.6" process $proc$libresoc.v:131969$5077 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:131970.5-131970.29" switch \initial attribute \src "libresoc.v:131970.9-131970.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \DIV_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:131988.3-132006.6" process $proc$libresoc.v:131988$5078 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:131989.5-131989.29" switch \initial attribute \src "libresoc.v:131989.9-131989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:132011.1-132065.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" module \dec_rc$159 attribute \src "libresoc.v:132012.7-132012.20" wire $0\initial[0:0] attribute \src "libresoc.v:132027.3-132045.6" wire $0\rc[0:0] attribute \src "libresoc.v:132046.3-132064.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:132027.3-132045.6" wire $1\rc[0:0] attribute \src "libresoc.v:132046.3-132064.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \MUL_Rc attribute \src "libresoc.v:132012.7-132012.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in attribute \src "libresoc.v:132012.7-132012.20" process $proc$libresoc.v:132012$5082 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:132027.3-132045.6" process $proc$libresoc.v:132027$5080 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:132028.5-132028.29" switch \initial attribute \src "libresoc.v:132028.9-132028.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \MUL_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:132046.3-132064.6" process $proc$libresoc.v:132046$5081 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:132047.5-132047.29" switch \initial attribute \src "libresoc.v:132047.9-132047.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:132069.1-132123.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" module \dec_rc$163 attribute \src "libresoc.v:132070.7-132070.20" wire $0\initial[0:0] attribute \src "libresoc.v:132085.3-132103.6" wire $0\rc[0:0] attribute \src "libresoc.v:132104.3-132122.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:132085.3-132103.6" wire $1\rc[0:0] attribute \src "libresoc.v:132104.3-132122.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \SHIFT_ROT_Rc attribute \src "libresoc.v:132070.7-132070.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in attribute \src "libresoc.v:132070.7-132070.20" process $proc$libresoc.v:132070$5085 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:132085.3-132103.6" process $proc$libresoc.v:132085$5083 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:132086.5-132086.29" switch \initial attribute \src "libresoc.v:132086.9-132086.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \SHIFT_ROT_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:132104.3-132122.6" process $proc$libresoc.v:132104$5084 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:132105.5-132105.29" switch \initial attribute \src "libresoc.v:132105.9-132105.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:132127.1-132181.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" module \dec_rc$167 attribute \src "libresoc.v:132128.7-132128.20" wire $0\initial[0:0] attribute \src "libresoc.v:132143.3-132161.6" wire $0\rc[0:0] attribute \src "libresoc.v:132162.3-132180.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:132143.3-132161.6" wire $1\rc[0:0] attribute \src "libresoc.v:132162.3-132180.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LDST_Rc attribute \src "libresoc.v:132128.7-132128.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in attribute \src "libresoc.v:132128.7-132128.20" process $proc$libresoc.v:132128$5088 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:132143.3-132161.6" process $proc$libresoc.v:132143$5086 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:132144.5-132144.29" switch \initial attribute \src "libresoc.v:132144.9-132144.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \LDST_Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:132162.3-132180.6" process $proc$libresoc.v:132162$5087 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:132163.5-132163.29" switch \initial attribute \src "libresoc.v:132163.9-132163.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:132185.1-132239.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" module \dec_rc$172 attribute \src "libresoc.v:132186.7-132186.20" wire $0\initial[0:0] attribute \src "libresoc.v:132201.3-132219.6" wire $0\rc[0:0] attribute \src "libresoc.v:132220.3-132238.6" wire $0\rc_ok[0:0] attribute \src "libresoc.v:132201.3-132219.6" wire $1\rc[0:0] attribute \src "libresoc.v:132220.3-132238.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \Rc attribute \src "libresoc.v:132186.7-132186.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" wire width 2 input 4 \sel_in attribute \src "libresoc.v:132186.7-132186.20" process $proc$libresoc.v:132186$5091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:132201.3-132219.6" process $proc$libresoc.v:132201$5089 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] attribute \src "libresoc.v:132202.5-132202.29" switch \initial attribute \src "libresoc.v:132202.9-132202.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc[0:0] \Rc attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc[0:0] 1'0 case assign $1\rc[0:0] 1'0 end sync always update \rc $0\rc[0:0] end attribute \src "libresoc.v:132220.3-132238.6" process $proc$libresoc.v:132220$5090 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] attribute \src "libresoc.v:132221.5-132221.29" switch \initial attribute \src "libresoc.v:132221.9-132221.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\rc_ok[0:0] 1'1 case assign $1\rc_ok[0:0] 1'0 end sync always update \rc_ok $0\rc_ok[0:0] end end attribute \src "libresoc.v:132243.1-133487.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 attribute \src "libresoc.v:133044.3-133045.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5231 attribute \src "libresoc.v:133016.3-133017.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 attribute \src "libresoc.v:132986.3-132987.73" wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 attribute \src "libresoc.v:132988.3-132989.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 attribute \src "libresoc.v:132990.3-132991.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5235 attribute \src "libresoc.v:133004.3-133005.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5236 attribute \src "libresoc.v:133018.3-133019.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5237 attribute \src "libresoc.v:132984.3-132985.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__invert_in$next[0:0]$5238 attribute \src "libresoc.v:133000.3-133001.77" wire $0\alu_div0_logical_op__invert_in[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__invert_out$next[0:0]$5239 attribute \src "libresoc.v:133006.3-133007.79" wire $0\alu_div0_logical_op__invert_out[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 attribute \src "libresoc.v:133012.3-133013.75" wire $0\alu_div0_logical_op__is_32bit[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__is_signed$next[0:0]$5241 attribute \src "libresoc.v:133014.3-133015.77" wire $0\alu_div0_logical_op__is_signed[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 attribute \src "libresoc.v:132996.3-132997.71" wire $0\alu_div0_logical_op__oe__oe[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 attribute \src "libresoc.v:132998.3-132999.71" wire $0\alu_div0_logical_op__oe__ok[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__output_carry$next[0:0]$5244 attribute \src "libresoc.v:133010.3-133011.83" wire $0\alu_div0_logical_op__output_carry[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 attribute \src "libresoc.v:132994.3-132995.71" wire $0\alu_div0_logical_op__rc__ok[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 attribute \src "libresoc.v:132992.3-132993.71" wire $0\alu_div0_logical_op__rc__rc[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 attribute \src "libresoc.v:133008.3-133009.77" wire $0\alu_div0_logical_op__write_cr0[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $0\alu_div0_logical_op__zero_a$next[0:0]$5248 attribute \src "libresoc.v:133002.3-133003.71" wire $0\alu_div0_logical_op__zero_a[0:0] attribute \src "libresoc.v:133042.3-133043.40" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:133397.3-133405.6" wire $0\alu_l_r_alu$next[0:0]$5318 attribute \src "libresoc.v:132958.3-132959.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:133388.3-133396.6" wire $0\alui_l_r_alui$next[0:0]$5315 attribute \src "libresoc.v:132960.3-132961.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:133270.3-133291.6" wire width 64 $0\data_r0__o$next[63:0]$5274 attribute \src "libresoc.v:132980.3-132981.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:133270.3-133291.6" wire $0\data_r0__o_ok$next[0:0]$5275 attribute \src "libresoc.v:132982.3-132983.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:133292.3-133313.6" wire width 4 $0\data_r1__cr_a$next[3:0]$5282 attribute \src "libresoc.v:132976.3-132977.43" wire width 4 $0\data_r1__cr_a[3:0] attribute \src "libresoc.v:133292.3-133313.6" wire $0\data_r1__cr_a_ok$next[0:0]$5283 attribute \src "libresoc.v:132978.3-132979.49" wire $0\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:133314.3-133335.6" wire width 2 $0\data_r2__xer_ov$next[1:0]$5290 attribute \src "libresoc.v:132972.3-132973.47" wire width 2 $0\data_r2__xer_ov[1:0] attribute \src "libresoc.v:133314.3-133335.6" wire $0\data_r2__xer_ov_ok$next[0:0]$5291 attribute \src "libresoc.v:132974.3-132975.53" wire $0\data_r2__xer_ov_ok[0:0] attribute \src "libresoc.v:133336.3-133357.6" wire $0\data_r3__xer_so$next[0:0]$5298 attribute \src "libresoc.v:132968.3-132969.47" wire $0\data_r3__xer_so[0:0] attribute \src "libresoc.v:133336.3-133357.6" wire $0\data_r3__xer_so_ok$next[0:0]$5299 attribute \src "libresoc.v:132970.3-132971.53" wire $0\data_r3__xer_so_ok[0:0] attribute \src "libresoc.v:133406.3-133415.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:133416.3-133425.6" wire width 4 $0\dest2_o[3:0] attribute \src "libresoc.v:133426.3-133435.6" wire width 2 $0\dest3_o[1:0] attribute \src "libresoc.v:133436.3-133445.6" wire $0\dest4_o[0:0] attribute \src "libresoc.v:132244.7-132244.20" wire $0\initial[0:0] attribute \src "libresoc.v:133186.3-133194.6" wire $0\opc_l_r_opc$next[0:0]$5216 attribute \src "libresoc.v:133028.3-133029.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:133177.3-133185.6" wire $0\opc_l_s_opc$next[0:0]$5213 attribute \src "libresoc.v:133030.3-133031.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:133446.3-133454.6" wire width 4 $0\prev_wr_go$next[3:0]$5325 attribute \src "libresoc.v:133040.3-133041.37" wire width 4 $0\prev_wr_go[3:0] attribute \src "libresoc.v:133131.3-133140.6" wire $0\req_done[0:0] attribute \src "libresoc.v:133222.3-133230.6" wire width 4 $0\req_l_r_req$next[3:0]$5228 attribute \src "libresoc.v:133020.3-133021.39" wire width 4 $0\req_l_r_req[3:0] attribute \src "libresoc.v:133213.3-133221.6" wire width 4 $0\req_l_s_req$next[3:0]$5225 attribute \src "libresoc.v:133022.3-133023.39" wire width 4 $0\req_l_s_req[3:0] attribute \src "libresoc.v:133150.3-133158.6" wire $0\rok_l_r_rdok$next[0:0]$5204 attribute \src "libresoc.v:133036.3-133037.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:133141.3-133149.6" wire $0\rok_l_s_rdok$next[0:0]$5201 attribute \src "libresoc.v:133038.3-133039.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:133168.3-133176.6" wire $0\rst_l_r_rst$next[0:0]$5210 attribute \src "libresoc.v:133032.3-133033.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:133159.3-133167.6" wire $0\rst_l_s_rst$next[0:0]$5207 attribute \src "libresoc.v:133034.3-133035.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:133204.3-133212.6" wire width 3 $0\src_l_r_src$next[2:0]$5222 attribute \src "libresoc.v:133024.3-133025.39" wire width 3 $0\src_l_r_src[2:0] attribute \src "libresoc.v:133195.3-133203.6" wire width 3 $0\src_l_s_src$next[2:0]$5219 attribute \src "libresoc.v:133026.3-133027.39" wire width 3 $0\src_l_s_src[2:0] attribute \src "libresoc.v:133358.3-133367.6" wire width 64 $0\src_r0$next[63:0]$5306 attribute \src "libresoc.v:132966.3-132967.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:133368.3-133377.6" wire width 64 $0\src_r1$next[63:0]$5309 attribute \src "libresoc.v:132964.3-132965.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:133378.3-133387.6" wire $0\src_r2$next[0:0]$5312 attribute \src "libresoc.v:132962.3-132963.29" wire $0\src_r2[0:0] attribute \src "libresoc.v:132374.7-132374.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5249 attribute \src "libresoc.v:132384.13-132384.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 attribute \src "libresoc.v:132403.14-132403.53" wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 attribute \src "libresoc.v:132407.14-132407.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 attribute \src "libresoc.v:132411.7-132411.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 attribute \src "libresoc.v:132419.13-132419.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5254 attribute \src "libresoc.v:132423.14-132423.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 attribute \src "libresoc.v:132502.13-132502.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__invert_in$next[0:0]$5256 attribute \src "libresoc.v:132506.7-132506.44" wire $1\alu_div0_logical_op__invert_in[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__invert_out$next[0:0]$5257 attribute \src "libresoc.v:132510.7-132510.45" wire $1\alu_div0_logical_op__invert_out[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 attribute \src "libresoc.v:132514.7-132514.43" wire $1\alu_div0_logical_op__is_32bit[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__is_signed$next[0:0]$5259 attribute \src "libresoc.v:132518.7-132518.44" wire $1\alu_div0_logical_op__is_signed[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 attribute \src "libresoc.v:132522.7-132522.41" wire $1\alu_div0_logical_op__oe__oe[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 attribute \src "libresoc.v:132526.7-132526.41" wire $1\alu_div0_logical_op__oe__ok[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__output_carry$next[0:0]$5262 attribute \src "libresoc.v:132530.7-132530.47" wire $1\alu_div0_logical_op__output_carry[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 attribute \src "libresoc.v:132534.7-132534.41" wire $1\alu_div0_logical_op__rc__ok[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 attribute \src "libresoc.v:132538.7-132538.41" wire $1\alu_div0_logical_op__rc__rc[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 attribute \src "libresoc.v:132542.7-132542.44" wire $1\alu_div0_logical_op__write_cr0[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire $1\alu_div0_logical_op__zero_a$next[0:0]$5266 attribute \src "libresoc.v:132546.7-132546.41" wire $1\alu_div0_logical_op__zero_a[0:0] attribute \src "libresoc.v:132572.7-132572.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:133397.3-133405.6" wire $1\alu_l_r_alu$next[0:0]$5319 attribute \src "libresoc.v:132580.7-132580.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:133388.3-133396.6" wire $1\alui_l_r_alui$next[0:0]$5316 attribute \src "libresoc.v:132592.7-132592.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:133270.3-133291.6" wire width 64 $1\data_r0__o$next[63:0]$5276 attribute \src "libresoc.v:132626.14-132626.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:133270.3-133291.6" wire $1\data_r0__o_ok$next[0:0]$5277 attribute \src "libresoc.v:132630.7-132630.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:133292.3-133313.6" wire width 4 $1\data_r1__cr_a$next[3:0]$5284 attribute \src "libresoc.v:132634.13-132634.33" wire width 4 $1\data_r1__cr_a[3:0] attribute \src "libresoc.v:133292.3-133313.6" wire $1\data_r1__cr_a_ok$next[0:0]$5285 attribute \src "libresoc.v:132638.7-132638.30" wire $1\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:133314.3-133335.6" wire width 2 $1\data_r2__xer_ov$next[1:0]$5292 attribute \src "libresoc.v:132642.13-132642.35" wire width 2 $1\data_r2__xer_ov[1:0] attribute \src "libresoc.v:133314.3-133335.6" wire $1\data_r2__xer_ov_ok$next[0:0]$5293 attribute \src "libresoc.v:132646.7-132646.32" wire $1\data_r2__xer_ov_ok[0:0] attribute \src "libresoc.v:133336.3-133357.6" wire $1\data_r3__xer_so$next[0:0]$5300 attribute \src "libresoc.v:132650.7-132650.29" wire $1\data_r3__xer_so[0:0] attribute \src "libresoc.v:133336.3-133357.6" wire $1\data_r3__xer_so_ok$next[0:0]$5301 attribute \src "libresoc.v:132654.7-132654.32" wire $1\data_r3__xer_so_ok[0:0] attribute \src "libresoc.v:133406.3-133415.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:133416.3-133425.6" wire width 4 $1\dest2_o[3:0] attribute \src "libresoc.v:133426.3-133435.6" wire width 2 $1\dest3_o[1:0] attribute \src "libresoc.v:133436.3-133445.6" wire $1\dest4_o[0:0] attribute \src "libresoc.v:133186.3-133194.6" wire $1\opc_l_r_opc$next[0:0]$5217 attribute \src "libresoc.v:132674.7-132674.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:133177.3-133185.6" wire $1\opc_l_s_opc$next[0:0]$5214 attribute \src "libresoc.v:132678.7-132678.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:133446.3-133454.6" wire width 4 $1\prev_wr_go$next[3:0]$5326 attribute \src "libresoc.v:132812.13-132812.30" wire width 4 $1\prev_wr_go[3:0] attribute \src "libresoc.v:133131.3-133140.6" wire $1\req_done[0:0] attribute \src "libresoc.v:133222.3-133230.6" wire width 4 $1\req_l_r_req$next[3:0]$5229 attribute \src "libresoc.v:132820.13-132820.31" wire width 4 $1\req_l_r_req[3:0] attribute \src "libresoc.v:133213.3-133221.6" wire width 4 $1\req_l_s_req$next[3:0]$5226 attribute \src "libresoc.v:132824.13-132824.31" wire width 4 $1\req_l_s_req[3:0] attribute \src "libresoc.v:133150.3-133158.6" wire $1\rok_l_r_rdok$next[0:0]$5205 attribute \src "libresoc.v:132836.7-132836.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:133141.3-133149.6" wire $1\rok_l_s_rdok$next[0:0]$5202 attribute \src "libresoc.v:132840.7-132840.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:133168.3-133176.6" wire $1\rst_l_r_rst$next[0:0]$5211 attribute \src "libresoc.v:132844.7-132844.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:133159.3-133167.6" wire $1\rst_l_s_rst$next[0:0]$5208 attribute \src "libresoc.v:132848.7-132848.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:133204.3-133212.6" wire width 3 $1\src_l_r_src$next[2:0]$5223 attribute \src "libresoc.v:132862.13-132862.31" wire width 3 $1\src_l_r_src[2:0] attribute \src "libresoc.v:133195.3-133203.6" wire width 3 $1\src_l_s_src$next[2:0]$5220 attribute \src "libresoc.v:132866.13-132866.31" wire width 3 $1\src_l_s_src[2:0] attribute \src "libresoc.v:133358.3-133367.6" wire width 64 $1\src_r0$next[63:0]$5307 attribute \src "libresoc.v:132874.14-132874.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:133368.3-133377.6" wire width 64 $1\src_r1$next[63:0]$5310 attribute \src "libresoc.v:132878.14-132878.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:133378.3-133387.6" wire $1\src_r2$next[0:0]$5313 attribute \src "libresoc.v:132882.7-132882.20" wire $1\src_r2[0:0] attribute \src "libresoc.v:133231.3-133269.6" wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 attribute \src "libresoc.v:133231.3-133269.6" wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 attribute \src "libresoc.v:133270.3-133291.6" wire width 64 $2\data_r0__o$next[63:0]$5278 attribute \src "libresoc.v:133270.3-133291.6" wire $2\data_r0__o_ok$next[0:0]$5279 attribute \src "libresoc.v:133292.3-133313.6" wire width 4 $2\data_r1__cr_a$next[3:0]$5286 attribute \src "libresoc.v:133292.3-133313.6" wire $2\data_r1__cr_a_ok$next[0:0]$5287 attribute \src "libresoc.v:133314.3-133335.6" wire width 2 $2\data_r2__xer_ov$next[1:0]$5294 attribute \src "libresoc.v:133314.3-133335.6" wire $2\data_r2__xer_ov_ok$next[0:0]$5295 attribute \src "libresoc.v:133336.3-133357.6" wire $2\data_r3__xer_so$next[0:0]$5302 attribute \src "libresoc.v:133336.3-133357.6" wire $2\data_r3__xer_so_ok$next[0:0]$5303 attribute \src "libresoc.v:133270.3-133291.6" wire $3\data_r0__o_ok$next[0:0]$5280 attribute \src "libresoc.v:133292.3-133313.6" wire $3\data_r1__cr_a_ok$next[0:0]$5288 attribute \src "libresoc.v:133314.3-133335.6" wire $3\data_r2__xer_ov_ok$next[0:0]$5296 attribute \src "libresoc.v:133336.3-133357.6" wire $3\data_r3__xer_so_ok$next[0:0]$5304 attribute \src "libresoc.v:132897.19-132897.133" wire width 3 $and$libresoc.v:132897$5094_Y attribute \src "libresoc.v:132899.19-132899.115" wire width 3 $and$libresoc.v:132899$5096_Y attribute \src "libresoc.v:132900.18-132900.110" wire $and$libresoc.v:132900$5097_Y attribute \src "libresoc.v:132901.19-132901.125" wire $and$libresoc.v:132901$5098_Y attribute \src "libresoc.v:132902.19-132902.125" wire $and$libresoc.v:132902$5099_Y attribute \src "libresoc.v:132903.19-132903.125" wire $and$libresoc.v:132903$5100_Y attribute \src "libresoc.v:132904.19-132904.125" wire $and$libresoc.v:132904$5101_Y attribute \src "libresoc.v:132905.19-132905.149" wire width 4 $and$libresoc.v:132905$5102_Y attribute \src "libresoc.v:132906.19-132906.121" wire width 4 $and$libresoc.v:132906$5103_Y attribute \src "libresoc.v:132907.19-132907.127" wire $and$libresoc.v:132907$5104_Y attribute \src "libresoc.v:132908.19-132908.127" wire $and$libresoc.v:132908$5105_Y attribute \src "libresoc.v:132909.19-132909.127" wire $and$libresoc.v:132909$5106_Y attribute \src "libresoc.v:132910.19-132910.127" wire $and$libresoc.v:132910$5107_Y attribute \src "libresoc.v:132912.18-132912.98" wire $and$libresoc.v:132912$5109_Y attribute \src "libresoc.v:132914.18-132914.100" wire $and$libresoc.v:132914$5111_Y attribute \src "libresoc.v:132915.18-132915.160" wire width 4 $and$libresoc.v:132915$5112_Y attribute \src "libresoc.v:132917.18-132917.119" wire width 4 $and$libresoc.v:132917$5114_Y attribute \src "libresoc.v:132920.17-132920.123" wire $and$libresoc.v:132920$5117_Y attribute \src "libresoc.v:132921.18-132921.116" wire $and$libresoc.v:132921$5118_Y attribute \src "libresoc.v:132926.18-132926.113" wire $and$libresoc.v:132926$5123_Y attribute \src "libresoc.v:132927.18-132927.125" wire width 4 $and$libresoc.v:132927$5124_Y attribute \src "libresoc.v:132929.18-132929.112" wire $and$libresoc.v:132929$5126_Y attribute \src "libresoc.v:132931.18-132931.126" wire $and$libresoc.v:132931$5128_Y attribute \src "libresoc.v:132932.18-132932.126" wire $and$libresoc.v:132932$5129_Y attribute \src "libresoc.v:132933.18-132933.117" wire $and$libresoc.v:132933$5130_Y attribute \src "libresoc.v:132939.18-132939.130" wire $and$libresoc.v:132939$5136_Y attribute \src "libresoc.v:132940.18-132940.124" wire width 4 $and$libresoc.v:132940$5137_Y attribute \src "libresoc.v:132942.18-132942.116" wire $and$libresoc.v:132942$5139_Y attribute \src "libresoc.v:132943.18-132943.119" wire $and$libresoc.v:132943$5140_Y attribute \src "libresoc.v:132944.18-132944.121" wire $and$libresoc.v:132944$5141_Y attribute \src "libresoc.v:132945.18-132945.121" wire $and$libresoc.v:132945$5142_Y attribute \src "libresoc.v:132955.18-132955.134" wire $and$libresoc.v:132955$5152_Y attribute \src "libresoc.v:132956.18-132956.132" wire $and$libresoc.v:132956$5153_Y attribute \src "libresoc.v:132957.18-132957.149" wire width 3 $and$libresoc.v:132957$5154_Y attribute \src "libresoc.v:132928.18-132928.113" wire $eq$libresoc.v:132928$5125_Y attribute \src "libresoc.v:132930.18-132930.119" wire $eq$libresoc.v:132930$5127_Y attribute \src "libresoc.v:132895.19-132895.130" wire $not$libresoc.v:132895$5092_Y attribute \src "libresoc.v:132896.19-132896.136" wire $not$libresoc.v:132896$5093_Y attribute \src "libresoc.v:132898.19-132898.115" wire width 3 $not$libresoc.v:132898$5095_Y attribute \src "libresoc.v:132911.18-132911.97" wire $not$libresoc.v:132911$5108_Y attribute \src "libresoc.v:132913.18-132913.99" wire $not$libresoc.v:132913$5110_Y attribute \src "libresoc.v:132916.18-132916.113" wire width 4 $not$libresoc.v:132916$5113_Y attribute \src "libresoc.v:132919.18-132919.106" wire $not$libresoc.v:132919$5116_Y attribute \src "libresoc.v:132925.18-132925.120" wire $not$libresoc.v:132925$5122_Y attribute \src "libresoc.v:132936.17-132936.113" wire width 3 $not$libresoc.v:132936$5133_Y attribute \src "libresoc.v:132924.18-132924.112" wire $or$libresoc.v:132924$5121_Y attribute \src "libresoc.v:132934.18-132934.122" wire $or$libresoc.v:132934$5131_Y attribute \src "libresoc.v:132935.18-132935.124" wire $or$libresoc.v:132935$5132_Y attribute \src "libresoc.v:132937.18-132937.168" wire width 4 $or$libresoc.v:132937$5134_Y attribute \src "libresoc.v:132938.18-132938.155" wire width 3 $or$libresoc.v:132938$5135_Y attribute \src "libresoc.v:132941.18-132941.120" wire width 4 $or$libresoc.v:132941$5138_Y attribute \src "libresoc.v:132947.17-132947.117" wire width 3 $or$libresoc.v:132947$5144_Y attribute \src "libresoc.v:132952.17-132952.104" wire $reduce_and$libresoc.v:132952$5149_Y attribute \src "libresoc.v:132918.18-132918.106" wire $reduce_or$libresoc.v:132918$5115_Y attribute \src "libresoc.v:132922.18-132922.113" wire $reduce_or$libresoc.v:132922$5119_Y attribute \src "libresoc.v:132923.18-132923.112" wire $reduce_or$libresoc.v:132923$5120_Y attribute \src "libresoc.v:132946.18-132946.158" wire $ternary$libresoc.v:132946$5143_Y attribute \src "libresoc.v:132948.18-132948.159" wire width 64 $ternary$libresoc.v:132948$5145_Y attribute \src "libresoc.v:132949.18-132949.164" wire $ternary$libresoc.v:132949$5146_Y attribute \src "libresoc.v:132950.18-132950.180" wire width 64 $ternary$libresoc.v:132950$5147_Y attribute \src "libresoc.v:132951.18-132951.115" wire width 64 $ternary$libresoc.v:132951$5148_Y attribute \src "libresoc.v:132953.18-132953.125" wire width 64 $ternary$libresoc.v:132953$5150_Y attribute \src "libresoc.v:132954.18-132954.118" wire $ternary$libresoc.v:132954$5151_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 4 \$118 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 4 \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 4 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 4 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 4 \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 4 \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 4 \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 3 \$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 4 \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 4 \$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_div0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_div0_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_div0_logical_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_div0_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_div0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_div0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_div0_logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_div0_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_div0_logical_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_div0_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_div0_logical_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_div0_logical_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_div0_logical_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_div0_logical_op__zero_a$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_div0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_div0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_div0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_div0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_div0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_div0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_div0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_div0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_div0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_div0_xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 4 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 38 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 21 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 20 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 24 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 23 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 22 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 30 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 29 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 4 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ov$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o attribute \src "libresoc.v:132244.7-132244.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \oper_i_alu_div0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 12 \oper_i_alu_div0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 19 \oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \oper_i_alu_div0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \oper_i_alu_div0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \oper_i_alu_div0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \oper_i_alu_div0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \oper_i_alu_div0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_alu_div0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \oper_i_alu_div0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \oper_i_alu_div0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \oper_i_alu_div0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \oper_i_alu_div0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \oper_i_alu_div0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 4 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 4 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 4 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:132897$5094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } connect \Y $and$libresoc.v:132897$5094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:132899$5096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 connect \Y $and$libresoc.v:132899$5096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:132900$5097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 connect \Y $and$libresoc.v:132900$5097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:132901$5098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:132901$5098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:132902$5099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:132902$5099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:132903$5100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:132903$5100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:132904$5101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:132904$5101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:132905$5102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } connect \Y $and$libresoc.v:132905$5102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:132906$5103 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:132906$5103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:132907$5104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:132907$5104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:132908$5105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:132908$5105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:132909$5106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:132909$5106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:132910$5107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o connect \Y $and$libresoc.v:132910$5107_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:132912$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 connect \Y $and$libresoc.v:132912$5109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:132914$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 connect \Y $and$libresoc.v:132914$5111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:132915$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:132915$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:132917$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 connect \Y $and$libresoc.v:132917$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:132920$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:132920$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:132921$5118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 connect \Y $and$libresoc.v:132921$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:132926$5123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 connect \Y $and$libresoc.v:132926$5123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:132927$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:132927$5124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:132929$5126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 connect \Y $and$libresoc.v:132929$5126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:132931$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i connect \Y $and$libresoc.v:132931$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:132932$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o connect \Y $and$libresoc.v:132932$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:132933$5130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o connect \Y $and$libresoc.v:132933$5130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:132939$5136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:132939$5136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:132940$5137 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:132940$5137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:132942$5139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:132942$5139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:132943$5140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:132943$5140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:132944$5141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:132944$5141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:132945$5142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:132945$5142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:132955$5152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:132955$5152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:132956$5153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:132956$5153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:132957$5154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:132957$5154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:132928$5125 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 connect \Y $eq$libresoc.v:132928$5125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:132930$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:132930$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:132895$5092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a connect \Y $not$libresoc.v:132895$5092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:132896$5093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok connect \Y $not$libresoc.v:132896$5093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:132898$5095 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:132898$5095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:132911$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:132911$5108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:132913$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:132913$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:132916$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:132916$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:132919$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 connect \Y $not$libresoc.v:132919$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:132925$5122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i connect \Y $not$libresoc.v:132925$5122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:132936$5133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:132936$5133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:132924$5121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 connect \Y $or$libresoc.v:132924$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:132934$5131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:132934$5131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:132935$5132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:132935$5132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:132937$5134 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:132937$5134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:132938$5135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:132938$5135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:132941$5138 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:132941$5138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:132947$5144 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:132947$5144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:132952$5149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 connect \Y $reduce_and$libresoc.v:132952$5149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:132918$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 connect \Y $reduce_or$libresoc.v:132918$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:132922$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:132922$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:132923$5120 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:132923$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:132946$5143 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a connect \Y $ternary$libresoc.v:132946$5143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:132948$5145 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a connect \Y $ternary$libresoc.v:132948$5145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:132949$5146 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok connect \Y $ternary$libresoc.v:132949$5146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:132950$5147 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok connect \Y $ternary$libresoc.v:132950$5147_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:132951$5148 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel connect \Y $ternary$libresoc.v:132951$5148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:132953$5150 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 connect \Y $ternary$libresoc.v:132953$5150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:132954$5151 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:132954$5151_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:133046.12-133082.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \alu_div0_cr_a connect \cr_a_ok \cr_a_ok connect \logical_op__data_len \alu_div0_logical_op__data_len connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok connect \logical_op__input_carry \alu_div0_logical_op__input_carry connect \logical_op__insn \alu_div0_logical_op__insn connect \logical_op__insn_type \alu_div0_logical_op__insn_type connect \logical_op__invert_in \alu_div0_logical_op__invert_in connect \logical_op__invert_out \alu_div0_logical_op__invert_out connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit connect \logical_op__is_signed \alu_div0_logical_op__is_signed connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok connect \logical_op__output_carry \alu_div0_logical_op__output_carry connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 connect \logical_op__zero_a \alu_div0_logical_op__zero_a connect \n_ready_i \alu_div0_n_ready_i connect \n_valid_o \alu_div0_n_valid_o connect \o \alu_div0_o connect \o_ok \o_ok connect \p_ready_o \alu_div0_p_ready_o connect \p_valid_i \alu_div0_p_valid_i connect \ra \alu_div0_ra connect \rb \alu_div0_rb connect \xer_ov \alu_div0_xer_ov connect \xer_ov_ok \xer_ov_ok connect \xer_so \alu_div0_xer_so connect \xer_so$1 \alu_div0_xer_so$1 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:133083.14-133089.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:133090.15-133096.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:133097.14-133103.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:133104.14-133110.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:133111.14-133117.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:133118.14-133123.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:133124.14-133130.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:132244.7-132244.20" process $proc$libresoc.v:132244$5327 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:132374.7-132374.24" process $proc$libresoc.v:132374$5328 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:132384.13-132384.49" process $proc$libresoc.v:132384$5329 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end attribute \src "libresoc.v:132403.14-132403.53" process $proc$libresoc.v:132403$5330 assign { } { } assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end attribute \src "libresoc.v:132407.14-132407.72" process $proc$libresoc.v:132407$5331 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:132411.7-132411.47" process $proc$libresoc.v:132411$5332 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:132419.13-132419.52" process $proc$libresoc.v:132419$5333 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end attribute \src "libresoc.v:132423.14-132423.47" process $proc$libresoc.v:132423$5334 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end attribute \src "libresoc.v:132502.13-132502.51" process $proc$libresoc.v:132502$5335 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end attribute \src "libresoc.v:132506.7-132506.44" process $proc$libresoc.v:132506$5336 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end attribute \src "libresoc.v:132510.7-132510.45" process $proc$libresoc.v:132510$5337 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end attribute \src "libresoc.v:132514.7-132514.43" process $proc$libresoc.v:132514$5338 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end attribute \src "libresoc.v:132518.7-132518.44" process $proc$libresoc.v:132518$5339 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end attribute \src "libresoc.v:132522.7-132522.41" process $proc$libresoc.v:132522$5340 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end attribute \src "libresoc.v:132526.7-132526.41" process $proc$libresoc.v:132526$5341 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end attribute \src "libresoc.v:132530.7-132530.47" process $proc$libresoc.v:132530$5342 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end attribute \src "libresoc.v:132534.7-132534.41" process $proc$libresoc.v:132534$5343 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end attribute \src "libresoc.v:132538.7-132538.41" process $proc$libresoc.v:132538$5344 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end attribute \src "libresoc.v:132542.7-132542.44" process $proc$libresoc.v:132542$5345 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end attribute \src "libresoc.v:132546.7-132546.41" process $proc$libresoc.v:132546$5346 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end attribute \src "libresoc.v:132572.7-132572.26" process $proc$libresoc.v:132572$5347 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:132580.7-132580.25" process $proc$libresoc.v:132580$5348 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:132592.7-132592.27" process $proc$libresoc.v:132592$5349 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:132626.14-132626.47" process $proc$libresoc.v:132626$5350 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:132630.7-132630.27" process $proc$libresoc.v:132630$5351 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:132634.13-132634.33" process $proc$libresoc.v:132634$5352 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end attribute \src "libresoc.v:132638.7-132638.30" process $proc$libresoc.v:132638$5353 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:132642.13-132642.35" process $proc$libresoc.v:132642$5354 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end attribute \src "libresoc.v:132646.7-132646.32" process $proc$libresoc.v:132646$5355 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end attribute \src "libresoc.v:132650.7-132650.29" process $proc$libresoc.v:132650$5356 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end attribute \src "libresoc.v:132654.7-132654.32" process $proc$libresoc.v:132654$5357 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end attribute \src "libresoc.v:132674.7-132674.25" process $proc$libresoc.v:132674$5358 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:132678.7-132678.25" process $proc$libresoc.v:132678$5359 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:132812.13-132812.30" process $proc$libresoc.v:132812$5360 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end attribute \src "libresoc.v:132820.13-132820.31" process $proc$libresoc.v:132820$5361 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end attribute \src "libresoc.v:132824.13-132824.31" process $proc$libresoc.v:132824$5362 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end attribute \src "libresoc.v:132836.7-132836.26" process $proc$libresoc.v:132836$5363 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:132840.7-132840.26" process $proc$libresoc.v:132840$5364 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:132844.7-132844.25" process $proc$libresoc.v:132844$5365 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:132848.7-132848.25" process $proc$libresoc.v:132848$5366 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:132862.13-132862.31" process $proc$libresoc.v:132862$5367 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end attribute \src "libresoc.v:132866.13-132866.31" process $proc$libresoc.v:132866$5368 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end attribute \src "libresoc.v:132874.14-132874.43" process $proc$libresoc.v:132874$5369 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:132878.14-132878.43" process $proc$libresoc.v:132878$5370 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:132882.7-132882.20" process $proc$libresoc.v:132882$5371 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end attribute \src "libresoc.v:132958.3-132959.39" process $proc$libresoc.v:132958$5155 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:132960.3-132961.43" process $proc$libresoc.v:132960$5156 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:132962.3-132963.29" process $proc$libresoc.v:132962$5157 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end attribute \src "libresoc.v:132964.3-132965.29" process $proc$libresoc.v:132964$5158 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:132966.3-132967.29" process $proc$libresoc.v:132966$5159 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:132968.3-132969.47" process $proc$libresoc.v:132968$5160 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end attribute \src "libresoc.v:132970.3-132971.53" process $proc$libresoc.v:132970$5161 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end attribute \src "libresoc.v:132972.3-132973.47" process $proc$libresoc.v:132972$5162 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end attribute \src "libresoc.v:132974.3-132975.53" process $proc$libresoc.v:132974$5163 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end attribute \src "libresoc.v:132976.3-132977.43" process $proc$libresoc.v:132976$5164 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end attribute \src "libresoc.v:132978.3-132979.49" process $proc$libresoc.v:132978$5165 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:132980.3-132981.37" process $proc$libresoc.v:132980$5166 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:132982.3-132983.43" process $proc$libresoc.v:132982$5167 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:132984.3-132985.77" process $proc$libresoc.v:132984$5168 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end attribute \src "libresoc.v:132986.3-132987.73" process $proc$libresoc.v:132986$5169 assign { } { } assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end attribute \src "libresoc.v:132988.3-132989.87" process $proc$libresoc.v:132988$5170 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:132990.3-132991.83" process $proc$libresoc.v:132990$5171 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:132992.3-132993.71" process $proc$libresoc.v:132992$5172 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end attribute \src "libresoc.v:132994.3-132995.71" process $proc$libresoc.v:132994$5173 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end attribute \src "libresoc.v:132996.3-132997.71" process $proc$libresoc.v:132996$5174 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end attribute \src "libresoc.v:132998.3-132999.71" process $proc$libresoc.v:132998$5175 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end attribute \src "libresoc.v:133000.3-133001.77" process $proc$libresoc.v:133000$5176 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end attribute \src "libresoc.v:133002.3-133003.71" process $proc$libresoc.v:133002$5177 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end attribute \src "libresoc.v:133004.3-133005.81" process $proc$libresoc.v:133004$5178 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end attribute \src "libresoc.v:133006.3-133007.79" process $proc$libresoc.v:133006$5179 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end attribute \src "libresoc.v:133008.3-133009.77" process $proc$libresoc.v:133008$5180 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end attribute \src "libresoc.v:133010.3-133011.83" process $proc$libresoc.v:133010$5181 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end attribute \src "libresoc.v:133012.3-133013.75" process $proc$libresoc.v:133012$5182 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end attribute \src "libresoc.v:133014.3-133015.77" process $proc$libresoc.v:133014$5183 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end attribute \src "libresoc.v:133016.3-133017.75" process $proc$libresoc.v:133016$5184 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end attribute \src "libresoc.v:133018.3-133019.67" process $proc$libresoc.v:133018$5185 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end attribute \src "libresoc.v:133020.3-133021.39" process $proc$libresoc.v:133020$5186 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end attribute \src "libresoc.v:133022.3-133023.39" process $proc$libresoc.v:133022$5187 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end attribute \src "libresoc.v:133024.3-133025.39" process $proc$libresoc.v:133024$5188 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end attribute \src "libresoc.v:133026.3-133027.39" process $proc$libresoc.v:133026$5189 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end attribute \src "libresoc.v:133028.3-133029.39" process $proc$libresoc.v:133028$5190 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:133030.3-133031.39" process $proc$libresoc.v:133030$5191 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:133032.3-133033.39" process $proc$libresoc.v:133032$5192 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:133034.3-133035.39" process $proc$libresoc.v:133034$5193 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:133036.3-133037.41" process $proc$libresoc.v:133036$5194 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:133038.3-133039.41" process $proc$libresoc.v:133038$5195 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:133040.3-133041.37" process $proc$libresoc.v:133040$5196 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end attribute \src "libresoc.v:133042.3-133043.40" process $proc$libresoc.v:133042$5197 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:133044.3-133045.25" process $proc$libresoc.v:133044$5198 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:133131.3-133140.6" process $proc$libresoc.v:133131$5199 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:133132.5-133132.29" switch \initial attribute \src "libresoc.v:133132.9-133132.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$46 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:133141.3-133149.6" process $proc$libresoc.v:133141$5200 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$5201 $1\rok_l_s_rdok$next[0:0]$5202 attribute \src "libresoc.v:133142.5-133142.29" switch \initial attribute \src "libresoc.v:133142.9-133142.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$5202 1'0 case assign $1\rok_l_s_rdok$next[0:0]$5202 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5201 end attribute \src "libresoc.v:133150.3-133158.6" process $proc$libresoc.v:133150$5203 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$5204 $1\rok_l_r_rdok$next[0:0]$5205 attribute \src "libresoc.v:133151.5-133151.29" switch \initial attribute \src "libresoc.v:133151.9-133151.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$5205 1'1 case assign $1\rok_l_r_rdok$next[0:0]$5205 \$64 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5204 end attribute \src "libresoc.v:133159.3-133167.6" process $proc$libresoc.v:133159$5206 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$5207 $1\rst_l_s_rst$next[0:0]$5208 attribute \src "libresoc.v:133160.5-133160.29" switch \initial attribute \src "libresoc.v:133160.9-133160.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$5208 1'0 case assign $1\rst_l_s_rst$next[0:0]$5208 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5207 end attribute \src "libresoc.v:133168.3-133176.6" process $proc$libresoc.v:133168$5209 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$5210 $1\rst_l_r_rst$next[0:0]$5211 attribute \src "libresoc.v:133169.5-133169.29" switch \initial attribute \src "libresoc.v:133169.9-133169.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$5211 1'1 case assign $1\rst_l_r_rst$next[0:0]$5211 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5210 end attribute \src "libresoc.v:133177.3-133185.6" process $proc$libresoc.v:133177$5212 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$5213 $1\opc_l_s_opc$next[0:0]$5214 attribute \src "libresoc.v:133178.5-133178.29" switch \initial attribute \src "libresoc.v:133178.9-133178.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$5214 1'0 case assign $1\opc_l_s_opc$next[0:0]$5214 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5213 end attribute \src "libresoc.v:133186.3-133194.6" process $proc$libresoc.v:133186$5215 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$5216 $1\opc_l_r_opc$next[0:0]$5217 attribute \src "libresoc.v:133187.5-133187.29" switch \initial attribute \src "libresoc.v:133187.9-133187.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$5217 1'1 case assign $1\opc_l_r_opc$next[0:0]$5217 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5216 end attribute \src "libresoc.v:133195.3-133203.6" process $proc$libresoc.v:133195$5218 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$5219 $1\src_l_s_src$next[2:0]$5220 attribute \src "libresoc.v:133196.5-133196.29" switch \initial attribute \src "libresoc.v:133196.9-133196.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[2:0]$5220 3'000 case assign $1\src_l_s_src$next[2:0]$5220 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5219 end attribute \src "libresoc.v:133204.3-133212.6" process $proc$libresoc.v:133204$5221 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$5222 $1\src_l_r_src$next[2:0]$5223 attribute \src "libresoc.v:133205.5-133205.29" switch \initial attribute \src "libresoc.v:133205.9-133205.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[2:0]$5223 3'111 case assign $1\src_l_r_src$next[2:0]$5223 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5222 end attribute \src "libresoc.v:133213.3-133221.6" process $proc$libresoc.v:133213$5224 assign { } { } assign { } { } assign $0\req_l_s_req$next[3:0]$5225 $1\req_l_s_req$next[3:0]$5226 attribute \src "libresoc.v:133214.5-133214.29" switch \initial attribute \src "libresoc.v:133214.9-133214.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[3:0]$5226 4'0000 case assign $1\req_l_s_req$next[3:0]$5226 \$66 end sync always update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5225 end attribute \src "libresoc.v:133222.3-133230.6" process $proc$libresoc.v:133222$5227 assign { } { } assign { } { } assign $0\req_l_r_req$next[3:0]$5228 $1\req_l_r_req$next[3:0]$5229 attribute \src "libresoc.v:133223.5-133223.29" switch \initial attribute \src "libresoc.v:133223.9-133223.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[3:0]$5229 4'1111 case assign $1\req_l_r_req$next[3:0]$5229 \$68 end sync always update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5228 end attribute \src "libresoc.v:133231.3-133269.6" process $proc$libresoc.v:133231$5230 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_div0_logical_op__data_len$next[3:0]$5231 $1\alu_div0_logical_op__data_len$next[3:0]$5249 assign $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 assign { } { } assign { } { } assign $0\alu_div0_logical_op__input_carry$next[1:0]$5235 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 assign $0\alu_div0_logical_op__insn$next[31:0]$5236 $1\alu_div0_logical_op__insn$next[31:0]$5254 assign $0\alu_div0_logical_op__insn_type$next[6:0]$5237 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 assign $0\alu_div0_logical_op__invert_in$next[0:0]$5238 $1\alu_div0_logical_op__invert_in$next[0:0]$5256 assign $0\alu_div0_logical_op__invert_out$next[0:0]$5239 $1\alu_div0_logical_op__invert_out$next[0:0]$5257 assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 assign $0\alu_div0_logical_op__is_signed$next[0:0]$5241 $1\alu_div0_logical_op__is_signed$next[0:0]$5259 assign { } { } assign { } { } assign $0\alu_div0_logical_op__output_carry$next[0:0]$5244 $1\alu_div0_logical_op__output_carry$next[0:0]$5262 assign { } { } assign { } { } assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 assign $0\alu_div0_logical_op__zero_a$next[0:0]$5248 $1\alu_div0_logical_op__zero_a$next[0:0]$5266 assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 attribute \src "libresoc.v:133232.5-133232.29" switch \initial attribute \src "libresoc.v:133232.9-133232.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_div0_logical_op__insn$next[31:0]$5254 $1\alu_div0_logical_op__data_len$next[3:0]$5249 $1\alu_div0_logical_op__is_signed$next[0:0]$5259 $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 $1\alu_div0_logical_op__output_carry$next[0:0]$5262 $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 $1\alu_div0_logical_op__invert_out$next[0:0]$5257 $1\alu_div0_logical_op__input_carry$next[1:0]$5253 $1\alu_div0_logical_op__zero_a$next[0:0]$5266 $1\alu_div0_logical_op__invert_in$next[0:0]$5256 $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 $1\alu_div0_logical_op__insn_type$next[6:0]$5255 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } case assign $1\alu_div0_logical_op__data_len$next[3:0]$5249 \alu_div0_logical_op__data_len assign $1\alu_div0_logical_op__fn_unit$next[13:0]$5250 \alu_div0_logical_op__fn_unit assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 \alu_div0_logical_op__imm_data__data assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 \alu_div0_logical_op__imm_data__ok assign $1\alu_div0_logical_op__input_carry$next[1:0]$5253 \alu_div0_logical_op__input_carry assign $1\alu_div0_logical_op__insn$next[31:0]$5254 \alu_div0_logical_op__insn assign $1\alu_div0_logical_op__insn_type$next[6:0]$5255 \alu_div0_logical_op__insn_type assign $1\alu_div0_logical_op__invert_in$next[0:0]$5256 \alu_div0_logical_op__invert_in assign $1\alu_div0_logical_op__invert_out$next[0:0]$5257 \alu_div0_logical_op__invert_out assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5258 \alu_div0_logical_op__is_32bit assign $1\alu_div0_logical_op__is_signed$next[0:0]$5259 \alu_div0_logical_op__is_signed assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 \alu_div0_logical_op__oe__oe assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 \alu_div0_logical_op__oe__ok assign $1\alu_div0_logical_op__output_carry$next[0:0]$5262 \alu_div0_logical_op__output_carry assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 \alu_div0_logical_op__rc__ok assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 \alu_div0_logical_op__rc__rc assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5265 \alu_div0_logical_op__write_cr0 assign $1\alu_div0_logical_op__zero_a$next[0:0]$5266 \alu_div0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 1'0 assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 1'0 assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 1'0 assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 1'0 assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 1'0 case assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5267 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5251 assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5252 assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5269 $1\alu_div0_logical_op__oe__oe$next[0:0]$5260 assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5270 $1\alu_div0_logical_op__oe__ok$next[0:0]$5261 assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5271 $1\alu_div0_logical_op__rc__ok$next[0:0]$5263 assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5272 $1\alu_div0_logical_op__rc__rc$next[0:0]$5264 end sync always update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5231 update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[13:0]$5232 update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5233 update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5234 update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5235 update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5236 update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5237 update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5238 update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5239 update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5240 update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5241 update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5242 update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5243 update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5244 update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5245 update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5246 update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5247 update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5248 end attribute \src "libresoc.v:133270.3-133291.6" process $proc$libresoc.v:133270$5273 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$5274 $2\data_r0__o$next[63:0]$5278 assign { } { } assign $0\data_r0__o_ok$next[0:0]$5275 $3\data_r0__o_ok$next[0:0]$5280 attribute \src "libresoc.v:133271.5-133271.29" switch \initial attribute \src "libresoc.v:133271.9-133271.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$5277 $1\data_r0__o$next[63:0]$5276 } { \o_ok \alu_div0_o } case assign $1\data_r0__o$next[63:0]$5276 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$5277 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$5279 $2\data_r0__o$next[63:0]$5278 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$5278 $1\data_r0__o$next[63:0]$5276 assign $2\data_r0__o_ok$next[0:0]$5279 $1\data_r0__o_ok$next[0:0]$5277 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$5280 1'0 case assign $3\data_r0__o_ok$next[0:0]$5280 $2\data_r0__o_ok$next[0:0]$5279 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$5274 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5275 end attribute \src "libresoc.v:133292.3-133313.6" process $proc$libresoc.v:133292$5281 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__cr_a$next[3:0]$5282 $2\data_r1__cr_a$next[3:0]$5286 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$5283 $3\data_r1__cr_a_ok$next[0:0]$5288 attribute \src "libresoc.v:133293.5-133293.29" switch \initial attribute \src "libresoc.v:133293.9-133293.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__cr_a_ok$next[0:0]$5285 $1\data_r1__cr_a$next[3:0]$5284 } { \cr_a_ok \alu_div0_cr_a } case assign $1\data_r1__cr_a$next[3:0]$5284 \data_r1__cr_a assign $1\data_r1__cr_a_ok$next[0:0]$5285 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__cr_a_ok$next[0:0]$5287 $2\data_r1__cr_a$next[3:0]$5286 } 5'00000 case assign $2\data_r1__cr_a$next[3:0]$5286 $1\data_r1__cr_a$next[3:0]$5284 assign $2\data_r1__cr_a_ok$next[0:0]$5287 $1\data_r1__cr_a_ok$next[0:0]$5285 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__cr_a_ok$next[0:0]$5288 1'0 case assign $3\data_r1__cr_a_ok$next[0:0]$5288 $2\data_r1__cr_a_ok$next[0:0]$5287 end sync always update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5282 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5283 end attribute \src "libresoc.v:133314.3-133335.6" process $proc$libresoc.v:133314$5289 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__xer_ov$next[1:0]$5290 $2\data_r2__xer_ov$next[1:0]$5294 assign { } { } assign $0\data_r2__xer_ov_ok$next[0:0]$5291 $3\data_r2__xer_ov_ok$next[0:0]$5296 attribute \src "libresoc.v:133315.5-133315.29" switch \initial attribute \src "libresoc.v:133315.9-133315.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__xer_ov_ok$next[0:0]$5293 $1\data_r2__xer_ov$next[1:0]$5292 } { \xer_ov_ok \alu_div0_xer_ov } case assign $1\data_r2__xer_ov$next[1:0]$5292 \data_r2__xer_ov assign $1\data_r2__xer_ov_ok$next[0:0]$5293 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__xer_ov_ok$next[0:0]$5295 $2\data_r2__xer_ov$next[1:0]$5294 } 3'000 case assign $2\data_r2__xer_ov$next[1:0]$5294 $1\data_r2__xer_ov$next[1:0]$5292 assign $2\data_r2__xer_ov_ok$next[0:0]$5295 $1\data_r2__xer_ov_ok$next[0:0]$5293 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__xer_ov_ok$next[0:0]$5296 1'0 case assign $3\data_r2__xer_ov_ok$next[0:0]$5296 $2\data_r2__xer_ov_ok$next[0:0]$5295 end sync always update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5290 update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5291 end attribute \src "libresoc.v:133336.3-133357.6" process $proc$libresoc.v:133336$5297 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r3__xer_so$next[0:0]$5298 $2\data_r3__xer_so$next[0:0]$5302 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$5299 $3\data_r3__xer_so_ok$next[0:0]$5304 attribute \src "libresoc.v:133337.5-133337.29" switch \initial attribute \src "libresoc.v:133337.9-133337.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r3__xer_so_ok$next[0:0]$5301 $1\data_r3__xer_so$next[0:0]$5300 } { \xer_so_ok \alu_div0_xer_so } case assign $1\data_r3__xer_so$next[0:0]$5300 \data_r3__xer_so assign $1\data_r3__xer_so_ok$next[0:0]$5301 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r3__xer_so_ok$next[0:0]$5303 $2\data_r3__xer_so$next[0:0]$5302 } 2'00 case assign $2\data_r3__xer_so$next[0:0]$5302 $1\data_r3__xer_so$next[0:0]$5300 assign $2\data_r3__xer_so_ok$next[0:0]$5303 $1\data_r3__xer_so_ok$next[0:0]$5301 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r3__xer_so_ok$next[0:0]$5304 1'0 case assign $3\data_r3__xer_so_ok$next[0:0]$5304 $2\data_r3__xer_so_ok$next[0:0]$5303 end sync always update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5298 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5299 end attribute \src "libresoc.v:133358.3-133367.6" process $proc$libresoc.v:133358$5305 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$5306 $1\src_r0$next[63:0]$5307 attribute \src "libresoc.v:133359.5-133359.29" switch \initial attribute \src "libresoc.v:133359.9-133359.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$5307 \src_or_imm case assign $1\src_r0$next[63:0]$5307 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$5306 end attribute \src "libresoc.v:133368.3-133377.6" process $proc$libresoc.v:133368$5308 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$5309 $1\src_r1$next[63:0]$5310 attribute \src "libresoc.v:133369.5-133369.29" switch \initial attribute \src "libresoc.v:133369.9-133369.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel$82 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$5310 \src_or_imm$85 case assign $1\src_r1$next[63:0]$5310 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$5309 end attribute \src "libresoc.v:133378.3-133387.6" process $proc$libresoc.v:133378$5311 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$5312 $1\src_r2$next[0:0]$5313 attribute \src "libresoc.v:133379.5-133379.29" switch \initial attribute \src "libresoc.v:133379.9-133379.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[0:0]$5313 \src3_i case assign $1\src_r2$next[0:0]$5313 \src_r2 end sync always update \src_r2$next $0\src_r2$next[0:0]$5312 end attribute \src "libresoc.v:133388.3-133396.6" process $proc$libresoc.v:133388$5314 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$5315 $1\alui_l_r_alui$next[0:0]$5316 attribute \src "libresoc.v:133389.5-133389.29" switch \initial attribute \src "libresoc.v:133389.9-133389.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$5316 1'1 case assign $1\alui_l_r_alui$next[0:0]$5316 \$94 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5315 end attribute \src "libresoc.v:133397.3-133405.6" process $proc$libresoc.v:133397$5317 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$5318 $1\alu_l_r_alu$next[0:0]$5319 attribute \src "libresoc.v:133398.5-133398.29" switch \initial attribute \src "libresoc.v:133398.9-133398.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$5319 1'1 case assign $1\alu_l_r_alu$next[0:0]$5319 \$96 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5318 end attribute \src "libresoc.v:133406.3-133415.6" process $proc$libresoc.v:133406$5320 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:133407.5-133407.29" switch \initial attribute \src "libresoc.v:133407.9-133407.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:133416.3-133425.6" process $proc$libresoc.v:133416$5321 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] attribute \src "libresoc.v:133417.5-133417.29" switch \initial attribute \src "libresoc.v:133417.9-133417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$124 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[3:0] \data_r1__cr_a case assign $1\dest2_o[3:0] 4'0000 end sync always update \dest2_o $0\dest2_o[3:0] end attribute \src "libresoc.v:133426.3-133435.6" process $proc$libresoc.v:133426$5322 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] attribute \src "libresoc.v:133427.5-133427.29" switch \initial attribute \src "libresoc.v:133427.9-133427.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[1:0] \data_r2__xer_ov case assign $1\dest3_o[1:0] 2'00 end sync always update \dest3_o $0\dest3_o[1:0] end attribute \src "libresoc.v:133436.3-133445.6" process $proc$libresoc.v:133436$5323 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] attribute \src "libresoc.v:133437.5-133437.29" switch \initial attribute \src "libresoc.v:133437.9-133437.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$128 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest4_o[0:0] \data_r3__xer_so case assign $1\dest4_o[0:0] 1'0 end sync always update \dest4_o $0\dest4_o[0:0] end attribute \src "libresoc.v:133446.3-133454.6" process $proc$libresoc.v:133446$5324 assign { } { } assign { } { } assign $0\prev_wr_go$next[3:0]$5325 $1\prev_wr_go$next[3:0]$5326 attribute \src "libresoc.v:133447.5-133447.29" switch \initial attribute \src "libresoc.v:133447.9-133447.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[3:0]$5326 4'0000 case assign $1\prev_wr_go$next[3:0]$5326 \$20 end sync always update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5325 end connect \$100 $not$libresoc.v:132895$5092_Y connect \$102 $not$libresoc.v:132896$5093_Y connect \$104 $and$libresoc.v:132897$5094_Y connect \$106 $not$libresoc.v:132898$5095_Y connect \$108 $and$libresoc.v:132899$5096_Y connect \$10 $and$libresoc.v:132900$5097_Y connect \$110 $and$libresoc.v:132901$5098_Y connect \$112 $and$libresoc.v:132902$5099_Y connect \$114 $and$libresoc.v:132903$5100_Y connect \$116 $and$libresoc.v:132904$5101_Y connect \$118 $and$libresoc.v:132905$5102_Y connect \$120 $and$libresoc.v:132906$5103_Y connect \$122 $and$libresoc.v:132907$5104_Y connect \$124 $and$libresoc.v:132908$5105_Y connect \$126 $and$libresoc.v:132909$5106_Y connect \$128 $and$libresoc.v:132910$5107_Y connect \$12 $not$libresoc.v:132911$5108_Y connect \$14 $and$libresoc.v:132912$5109_Y connect \$16 $not$libresoc.v:132913$5110_Y connect \$18 $and$libresoc.v:132914$5111_Y connect \$20 $and$libresoc.v:132915$5112_Y connect \$24 $not$libresoc.v:132916$5113_Y connect \$26 $and$libresoc.v:132917$5114_Y connect \$23 $reduce_or$libresoc.v:132918$5115_Y connect \$22 $not$libresoc.v:132919$5116_Y connect \$2 $and$libresoc.v:132920$5117_Y connect \$30 $and$libresoc.v:132921$5118_Y connect \$32 $reduce_or$libresoc.v:132922$5119_Y connect \$34 $reduce_or$libresoc.v:132923$5120_Y connect \$36 $or$libresoc.v:132924$5121_Y connect \$38 $not$libresoc.v:132925$5122_Y connect \$40 $and$libresoc.v:132926$5123_Y connect \$42 $and$libresoc.v:132927$5124_Y connect \$44 $eq$libresoc.v:132928$5125_Y connect \$46 $and$libresoc.v:132929$5126_Y connect \$48 $eq$libresoc.v:132930$5127_Y connect \$50 $and$libresoc.v:132931$5128_Y connect \$52 $and$libresoc.v:132932$5129_Y connect \$54 $and$libresoc.v:132933$5130_Y connect \$56 $or$libresoc.v:132934$5131_Y connect \$58 $or$libresoc.v:132935$5132_Y connect \$5 $not$libresoc.v:132936$5133_Y connect \$60 $or$libresoc.v:132937$5134_Y connect \$62 $or$libresoc.v:132938$5135_Y connect \$64 $and$libresoc.v:132939$5136_Y connect \$66 $and$libresoc.v:132940$5137_Y connect \$68 $or$libresoc.v:132941$5138_Y connect \$70 $and$libresoc.v:132942$5139_Y connect \$72 $and$libresoc.v:132943$5140_Y connect \$74 $and$libresoc.v:132944$5141_Y connect \$76 $and$libresoc.v:132945$5142_Y connect \$78 $ternary$libresoc.v:132946$5143_Y connect \$7 $or$libresoc.v:132947$5144_Y connect \$80 $ternary$libresoc.v:132948$5145_Y connect \$83 $ternary$libresoc.v:132949$5146_Y connect \$86 $ternary$libresoc.v:132950$5147_Y connect \$88 $ternary$libresoc.v:132951$5148_Y connect \$4 $reduce_and$libresoc.v:132952$5149_Y connect \$90 $ternary$libresoc.v:132953$5150_Y connect \$92 $ternary$libresoc.v:132954$5151_Y connect \$94 $and$libresoc.v:132955$5152_Y connect \$96 $and$libresoc.v:132956$5153_Y connect \$98 $and$libresoc.v:132957$5154_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 connect \cu_rd__rel_o \$108 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_div0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_div0_p_valid_i \alui_l_q_alui connect \alu_div0_xer_so$1 \$92 connect \alu_div0_rb \$90 connect \alu_div0_ra \$88 connect \src_or_imm$85 \$86 connect \src_sel$82 \$83 connect \src_or_imm \$80 connect \src_sel \$78 connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } connect \reset_r \$62 connect \reset_w \$60 connect \rst_r \$58 connect \reset \$56 connect \wr_any \$36 connect \cu_done_o \$30 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$18 connect \alu_done_dly$next \alu_done connect \alu_done \alu_div0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$14 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end attribute \src "libresoc.v:133491.1-133500.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" module \div_state_init attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" wire width 128 input 3 \dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 output 2 \o_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 output 1 \o_q_bits_known connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end attribute \src "libresoc.v:133504.1-133586.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next attribute \src "libresoc.v:133505.7-133505.20" wire $0\initial[0:0] attribute \src "libresoc.v:133570.3-133581.6" wire width 128 $0\o_dividend_quotient[127:0] attribute \src "libresoc.v:133558.3-133569.6" wire width 7 $0\o_q_bits_known[6:0] attribute \src "libresoc.v:133546.3-133557.6" wire width 128 $0\value[127:0] attribute \src "libresoc.v:133570.3-133581.6" wire width 128 $1\o_dividend_quotient[127:0] attribute \src "libresoc.v:133558.3-133569.6" wire width 7 $1\o_q_bits_known[6:0] attribute \src "libresoc.v:133546.3-133557.6" wire width 128 $1\value[127:0] attribute \src "libresoc.v:133540.18-133540.106" wire width 8 $add$libresoc.v:133540$5372_Y attribute \src "libresoc.v:133541.18-133541.109" wire $ge$libresoc.v:133541$5373_Y attribute \src "libresoc.v:133545.17-133545.108" wire $ge$libresoc.v:133545$5377_Y attribute \src "libresoc.v:133544.17-133544.101" wire $not$libresoc.v:133544$5376_Y attribute \src "libresoc.v:133542.17-133542.101" wire width 127 $sshl$libresoc.v:133542$5374_Y attribute \src "libresoc.v:133543.17-133543.109" wire width 129 $sub$libresoc.v:133543$5375_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" wire width 8 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" wire width 8 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 127 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" wire width 128 \difference attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" wire width 64 input 4 \divisor attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known attribute \src "libresoc.v:133505.7-133505.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 output 5 \o_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 output 1 \o_q_bits_known attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" cell $add $add$libresoc.v:133540$5372 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 connect \Y $add$libresoc.v:133540$5372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" cell $ge $ge$libresoc.v:133541$5373 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 connect \Y $ge$libresoc.v:133541$5373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" cell $ge $ge$libresoc.v:133545$5377 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 connect \Y $ge$libresoc.v:133545$5377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" cell $not $not$libresoc.v:133544$5376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] connect \Y $not$libresoc.v:133544$5376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" cell $sshl $sshl$libresoc.v:133542$5374 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 connect \Y $sshl$libresoc.v:133542$5374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" cell $sub $sub$libresoc.v:133543$5375 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 parameter \B_WIDTH 127 parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 connect \Y $sub$libresoc.v:133543$5375_Y end attribute \src "libresoc.v:133505.7-133505.20" process $proc$libresoc.v:133505$5381 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:133546.3-133557.6" process $proc$libresoc.v:133546$5378 assign { } { } assign $0\value[127:0] $1\value[127:0] attribute \src "libresoc.v:133547.5-133547.29" switch \initial attribute \src "libresoc.v:133547.9-133547.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" switch \next_quotient_bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\value[127:0] \difference attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\value[127:0] \i_dividend_quotient end sync always update \value $0\value[127:0] end attribute \src "libresoc.v:133558.3-133569.6" process $proc$libresoc.v:133558$5379 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] attribute \src "libresoc.v:133559.5-133559.29" switch \initial attribute \src "libresoc.v:133559.9-133559.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" switch \$8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o_q_bits_known[6:0] \i_q_bits_known attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o_q_bits_known[6:0] \$10 [6:0] end sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end attribute \src "libresoc.v:133570.3-133581.6" process $proc$libresoc.v:133570$5380 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] attribute \src "libresoc.v:133571.5-133571.29" switch \initial attribute \src "libresoc.v:133571.9-133571.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o_dividend_quotient[127:0] \i_dividend_quotient attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o_dividend_quotient[127:0] { \value [126:0] \next_quotient_bit } end sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end connect \$11 $add$libresoc.v:133540$5372_Y connect \$13 $ge$libresoc.v:133541$5373_Y connect \$2 $sshl$libresoc.v:133542$5374_Y connect \$4 $sub$libresoc.v:133543$5375_Y connect \$6 $not$libresoc.v:133544$5376_Y connect \$8 $ge$libresoc.v:133545$5377_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end attribute \src "libresoc.v:133590.1-133833.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" module \dummy attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 12 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 26 \fast1$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 27 \fast2$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 14 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 24 \ra$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 25 \rb$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 17 \trap_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 9 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 23 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 18 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 8 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 output 22 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 7 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 21 \trap_op__traptype$8 connect \fast2$14 \fast2 connect \fast1$13 \fast1 connect \rb$12 \rb connect \ra$11 \ra connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end attribute \src "libresoc.v:133837.1-133968.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0\_0_[2:0] attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $0\_1_[2:0] attribute \src "libresoc.v:133838.7-133838.20" wire $0\initial[0:0] attribute \src "libresoc.v:133950.3-133959.6" wire width 64 $0\issue__data_o[63:0] attribute \src "libresoc.v:133941.3-133949.6" wire $0\ren_delay$8$next[0:0]$5415 attribute \src "libresoc.v:133918.3-133919.41" wire $0\ren_delay$8[0:0]$5408 attribute \src "libresoc.v:133885.7-133885.27" wire $0\ren_delay$8[0:0]$5429 attribute \src "libresoc.v:133922.3-133930.6" wire $0\ren_delay$next[0:0]$5411 attribute \src "libresoc.v:133920.3-133921.35" wire $0\ren_delay[0:0] attribute \src "libresoc.v:133931.3-133940.6" wire width 64 $0\src1__data_o[63:0] attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 attribute \src "libresoc.v:133910.3-133915.6" wire width 3 $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 attribute \src "libresoc.v:133910.3-133915.6" wire width 64 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 attribute \src "libresoc.v:133950.3-133959.6" wire width 64 $1\issue__data_o[63:0] attribute \src "libresoc.v:133941.3-133949.6" wire $1\ren_delay$8$next[0:0]$5416 attribute \src "libresoc.v:133922.3-133930.6" wire $1\ren_delay$next[0:0]$5412 attribute \src "libresoc.v:133883.7-133883.23" wire $1\ren_delay[0:0] attribute \src "libresoc.v:133931.3-133940.6" wire width 64 $1\src1__data_o[63:0] attribute \src "libresoc.v:133916.26-133916.32" wire width 64 $memrd$\memory$libresoc.v:133916$5405_DATA attribute \src "libresoc.v:133917.30-133917.36" wire width 64 $memrd$\memory$libresoc.v:133917$5406_DATA attribute \src "libresoc.v:0.0-0.0" wire width 3 $memwr$\memory$libresoc.v:133913$5390_ADDR attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:133913$5390_DATA attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:133913$5390_EN attribute \src "libresoc.v:0.0-0.0" wire width 3 $memwr$\memory$libresoc.v:133914$5391_ADDR attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:133914$5391_DATA attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:133914$5391_EN attribute \src "libresoc.v:133908.13-133908.16" wire width 3 \_0_ attribute \src "libresoc.v:133909.13-133909.16" wire width 3 \_1_ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 14 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 12 \dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \dest1__wen attribute \src "libresoc.v:133838.7-133838.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 5 \issue__addr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 4 \issue__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 3 \memory_r_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 3 \memory_r_addr$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 3 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 3 \memory_w_addr$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 8 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \src1__ren attribute \src "libresoc.v:133897.14-133897.20" memory width 64 size 8 \memory attribute \src "libresoc.v:133899.5-133899.37" cell $meminit $meminit$\memory$libresoc.v:133899$5418 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5418 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133900.5-133900.37" cell $meminit $meminit$\memory$libresoc.v:133900$5419 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5419 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133901.5-133901.37" cell $meminit $meminit$\memory$libresoc.v:133901$5420 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5420 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133902.5-133902.37" cell $meminit $meminit$\memory$libresoc.v:133902$5421 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5421 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133903.5-133903.37" cell $meminit $meminit$\memory$libresoc.v:133903$5422 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5422 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133904.5-133904.37" cell $meminit $meminit$\memory$libresoc.v:133904$5423 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5423 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133905.5-133905.37" cell $meminit $meminit$\memory$libresoc.v:133905$5424 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5424 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133906.5-133906.37" cell $meminit $meminit$\memory$libresoc.v:133906$5425 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5425 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133916.26-133916.32" cell $memrd $memrd$\memory$libresoc.v:133916$5405 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" parameter \TRANSPARENT 0 parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x connect \DATA $memrd$\memory$libresoc.v:133916$5405_DATA connect \EN 1'x end attribute \src "libresoc.v:133917.30-133917.36" cell $memrd $memrd$\memory$libresoc.v:133917$5406 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" parameter \TRANSPARENT 0 parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x connect \DATA $memrd$\memory$libresoc.v:133917$5406_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" process $proc$libresoc.v:0$5430 sync always sync init end attribute \src "libresoc.v:133838.7-133838.20" process $proc$libresoc.v:133838$5426 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:133883.7-133883.23" process $proc$libresoc.v:133883$5427 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end attribute \src "libresoc.v:133885.7-133885.27" process $proc$libresoc.v:133885$5428 assign { } { } assign $0\ren_delay$8[0:0]$5429 1'0 sync always sync init update \ren_delay$8 $0\ren_delay$8[0:0]$5429 end attribute \src "libresoc.v:133910.3-133915.6" process $proc$libresoc.v:133910$5392 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\_0_[2:0] \memory_r_addr assign $0\_1_[2:0] \memory_r_addr$3 assign $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 assign $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 assign $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 assign $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 assign $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 assign $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 attribute \src "libresoc.v:133913.5-133913.61" switch \memory_w_en attribute \src "libresoc.v:133913.9-133913.20" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 \memory_w_addr assign $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 \memory_w_data assign $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 64'1111111111111111111111111111111111111111111111111111111111111111 case assign $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 3'xxx assign $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:133914.5-133914.73" switch \memory_w_en$5 attribute \src "libresoc.v:133914.9-133914.23" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 \memory_w_addr$6 assign $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 \memory_w_data$7 assign $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 64'1111111111111111111111111111111111111111111111111111111111111111 case assign $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 3'xxx assign $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] update $memwr$\memory$libresoc.v:133913$5390_ADDR $0$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5393 update $memwr$\memory$libresoc.v:133913$5390_DATA $0$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5394 update $memwr$\memory$libresoc.v:133913$5390_EN $0$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5395 update $memwr$\memory$libresoc.v:133914$5391_ADDR $0$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5396 update $memwr$\memory$libresoc.v:133914$5391_DATA $0$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5397 update $memwr$\memory$libresoc.v:133914$5391_EN $0$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5398 attribute \src "libresoc.v:133913.22-133913.60" memwr \memory $1$memwr$\memory$libresoc.v:133913$5390_ADDR[2:0]$5399 $1$memwr$\memory$libresoc.v:133913$5390_DATA[63:0]$5400 $1$memwr$\memory$libresoc.v:133913$5390_EN[63:0]$5401 0' attribute \src "libresoc.v:133914.26-133914.71" memwr \memory $1$memwr$\memory$libresoc.v:133914$5391_ADDR[2:0]$5402 $1$memwr$\memory$libresoc.v:133914$5391_DATA[63:0]$5403 $1$memwr$\memory$libresoc.v:133914$5391_EN[63:0]$5404 1'1 end attribute \src "libresoc.v:133918.3-133919.41" process $proc$libresoc.v:133918$5407 assign { } { } assign $0\ren_delay$8[0:0]$5408 \ren_delay$8$next sync posedge \coresync_clk update \ren_delay$8 $0\ren_delay$8[0:0]$5408 end attribute \src "libresoc.v:133920.3-133921.35" process $proc$libresoc.v:133920$5409 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end attribute \src "libresoc.v:133922.3-133930.6" process $proc$libresoc.v:133922$5410 assign { } { } assign { } { } assign $0\ren_delay$next[0:0]$5411 $1\ren_delay$next[0:0]$5412 attribute \src "libresoc.v:133923.5-133923.29" switch \initial attribute \src "libresoc.v:133923.9-133923.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$next[0:0]$5412 1'0 case assign $1\ren_delay$next[0:0]$5412 \src1__ren end sync always update \ren_delay$next $0\ren_delay$next[0:0]$5411 end attribute \src "libresoc.v:133931.3-133940.6" process $proc$libresoc.v:133931$5413 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] attribute \src "libresoc.v:133932.5-133932.29" switch \initial attribute \src "libresoc.v:133932.9-133932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch \ren_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src1__data_o[63:0] \memory_r_data case assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \src1__data_o $0\src1__data_o[63:0] end attribute \src "libresoc.v:133941.3-133949.6" process $proc$libresoc.v:133941$5414 assign { } { } assign { } { } assign $0\ren_delay$8$next[0:0]$5415 $1\ren_delay$8$next[0:0]$5416 attribute \src "libresoc.v:133942.5-133942.29" switch \initial attribute \src "libresoc.v:133942.9-133942.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$8$next[0:0]$5416 1'0 case assign $1\ren_delay$8$next[0:0]$5416 \issue__ren end sync always update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5415 end attribute \src "libresoc.v:133950.3-133959.6" process $proc$libresoc.v:133950$5417 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] attribute \src "libresoc.v:133951.5-133951.29" switch \initial attribute \src "libresoc.v:133951.9-133951.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch \ren_delay$8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\issue__data_o[63:0] \memory_r_data$4 case assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \issue__data_o $0\issue__data_o[63:0] end connect \memory_r_data $memrd$\memory$libresoc.v:133916$5405_DATA connect \memory_r_data$4 $memrd$\memory$libresoc.v:133917$5406_DATA connect \memory_w_data$7 \issue__data_i connect \memory_w_en$5 \issue__wen connect \memory_w_addr$6 \issue__addr$1 connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr connect \memory_r_addr$3 \issue__addr connect \memory_r_addr \src1__addr end attribute \src "libresoc.v:133972.1-135922.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 330 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 257 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 258 \cr_a_ok$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 259 \cr_a_ok$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 260 \cr_a_ok$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 261 \cr_a_ok$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 262 \cr_a_ok$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 4 \cu_ad__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 25 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 75 \cu_busy_o$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 82 \cu_busy_o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 103 \cu_busy_o$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 31 \cu_busy_o$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 118 \cu_busy_o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 138 \cu_busy_o$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 157 \cu_busy_o$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 42 \cu_busy_o$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 54 \cu_busy_o$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 24 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 30 \cu_issue_i$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 74 \cu_issue_i$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 81 \cu_issue_i$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 102 \cu_issue_i$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 117 \cu_issue_i$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 137 \cu_issue_i$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 156 \cu_issue_i$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 41 \cu_issue_i$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 53 \cu_issue_i$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 160 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 input 163 \cu_rd__go_i$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 166 \cu_rd__go_i$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 169 \cu_rd__go_i$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 172 \cu_rd__go_i$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 175 \cu_rd__go_i$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 input 178 \cu_rd__go_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 181 \cu_rd__go_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 input 190 \cu_rd__go_i$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 209 \cu_rd__go_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 159 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 output 162 \cu_rd__rel_o$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 165 \cu_rd__rel_o$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 168 \cu_rd__rel_o$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 171 \cu_rd__rel_o$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 174 \cu_rd__rel_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 output 177 \cu_rd__rel_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 180 \cu_rd__rel_o$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 output 189 \cu_rd__rel_o$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 208 \cu_rd__rel_o$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 input 26 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 76 \cu_rdmaskn_i$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 6 input 83 \cu_rdmaskn_i$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 104 \cu_rdmaskn_i$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 119 \cu_rdmaskn_i$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 5 input 139 \cu_rdmaskn_i$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 158 \cu_rdmaskn_i$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 6 input 32 \cu_rdmaskn_i$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 43 \cu_rdmaskn_i$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 input 55 \cu_rdmaskn_i$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 5 \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 2 \cu_st__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 input 221 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 242 \cu_wr__go_i$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 input 244 \cu_wr__go_i$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 293 \cu_wr__go_i$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 224 \cu_wr__go_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 input 227 \cu_wr__go_i$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 input 230 \cu_wr__go_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 input 233 \cu_wr__go_i$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 236 \cu_wr__go_i$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 239 \cu_wr__go_i$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 output 220 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 output 243 \cu_wr__rel_o$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 292 \cu_wr__rel_o$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 223 \cu_wr__rel_o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 output 226 \cu_wr__rel_o$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 output 229 \cu_wr__rel_o$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 output 232 \cu_wr__rel_o$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 235 \cu_wr__rel_o$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 238 \cu_wr__rel_o$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 241 \cu_wr__rel_o$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 245 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 246 \dest1_o$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 247 \dest1_o$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 248 \dest1_o$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 249 \dest1_o$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 250 \dest1_o$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 251 \dest1_o$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 252 \dest1_o$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 298 \dest1_o$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 32 output 256 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 263 \dest2_o$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 265 \dest2_o$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 266 \dest2_o$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 267 \dest2_o$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 268 \dest2_o$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 299 \dest2_o$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 301 \dest2_o$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 310 \dest2_o$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 264 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 272 \dest3_o$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 274 \dest3_o$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 281 \dest3_o$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 282 \dest3_o$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 300 \dest3_o$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 302 \dest3_o$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 305 \dest3_o$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 279 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 288 \dest4_o$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 289 \dest4_o$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 290 \dest4_o$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 306 \dest4_o$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 280 \dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 287 \dest5_o$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 308 \dest5_o$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 273 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 254 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 291 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 294 \fast1_ok$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 295 \fast1_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 296 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 297 \fast2_ok$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 255 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 output 315 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 316 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire input 325 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire input 311 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 output 314 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 317 \ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 318 \ldst_port0_exc_$signal$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 319 \ldst_port0_exc_$signal$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 320 \ldst_port0_exc_$signal$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 321 \ldst_port0_exc_$signal$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 322 \ldst_port0_exc_$signal$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 323 \ldst_port0_exc_$signal$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 324 \ldst_port0_exc_$signal$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire output 312 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire output 313 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 326 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 327 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 328 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 329 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 307 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 303 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 304 \nia_ok$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 253 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 219 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 222 \o_ok$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 225 \o_ok$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 228 \o_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 231 \o_ok$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 234 \o_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 237 \o_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 240 \o_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 22 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 7 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_alu_alu0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 18 \oper_i_alu_alu0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 23 \oper_i_alu_alu0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \oper_i_alu_alu0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \oper_i_alu_alu0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \oper_i_alu_alu0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 21 \oper_i_alu_alu0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \oper_i_alu_alu0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \oper_i_alu_alu0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \oper_i_alu_alu0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \oper_i_alu_alu0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \oper_i_alu_alu0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \oper_i_alu_alu0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \oper_i_alu_alu0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 33 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 35 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 37 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 38 \oper_i_alu_branch0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 36 \oper_i_alu_branch0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 34 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 40 \oper_i_alu_branch0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 39 \oper_i_alu_branch0__lk attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 28 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 29 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 27 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 100 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 85 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 86 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 87 \oper_i_alu_div0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 94 \oper_i_alu_div0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 101 \oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 84 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 92 \oper_i_alu_div0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 95 \oper_i_alu_div0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 98 \oper_i_alu_div0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 99 \oper_i_alu_div0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 90 \oper_i_alu_div0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 91 \oper_i_alu_div0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 97 \oper_i_alu_div0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 89 \oper_i_alu_div0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 88 \oper_i_alu_div0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 96 \oper_i_alu_div0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 93 \oper_i_alu_div0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 72 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 57 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 58 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 59 \oper_i_alu_logical0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 66 \oper_i_alu_logical0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 73 \oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 56 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 64 \oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 67 \oper_i_alu_logical0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 70 \oper_i_alu_logical0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 71 \oper_i_alu_logical0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 62 \oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 63 \oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 69 \oper_i_alu_logical0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 61 \oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 60 \oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 68 \oper_i_alu_logical0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 65 \oper_i_alu_logical0__zero_a attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 106 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 107 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 108 \oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 116 \oper_i_alu_mul0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 105 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 114 \oper_i_alu_mul0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 115 \oper_i_alu_mul0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 111 \oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 112 \oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 110 \oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 109 \oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 113 \oper_i_alu_mul0__write_cr0 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 121 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 123 \oper_i_alu_shift_rot0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 130 \oper_i_alu_shift_rot0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 132 \oper_i_alu_shift_rot0__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 136 \oper_i_alu_shift_rot0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 129 \oper_i_alu_shift_rot0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 134 \oper_i_alu_shift_rot0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 135 \oper_i_alu_shift_rot0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 126 \oper_i_alu_shift_rot0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 127 \oper_i_alu_shift_rot0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 131 \oper_i_alu_shift_rot0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 133 \oper_i_alu_shift_rot0__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 125 \oper_i_alu_shift_rot0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 124 \oper_i_alu_shift_rot0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 128 \oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 78 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 79 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 77 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 80 \oper_i_alu_spr0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 48 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 45 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 46 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 44 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 49 \oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 52 \oper_i_alu_trap0__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 47 \oper_i_alu_trap0__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 51 \oper_i_alu_trap0__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 50 \oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 152 \oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 151 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 141 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 143 \oper_i_ldst_ldst0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 155 \oper_i_ldst_ldst0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 140 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 149 \oper_i_ldst_ldst0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 150 \oper_i_ldst_ldst0__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 154 \oper_i_ldst_ldst0__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 147 \oper_i_ldst_ldst0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 148 \oper_i_ldst_ldst0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 146 \oper_i_ldst_ldst0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 145 \oper_i_ldst_ldst0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 153 \oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 144 \oper_i_ldst_ldst0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 309 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 185 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 186 \src1_i$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 187 \src1_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 188 \src1_i$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 191 \src1_i$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 192 \src1_i$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 193 \src1_i$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 194 \src1_i$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 195 \src1_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 213 \src1_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 161 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 164 \src2_i$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 167 \src2_i$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 170 \src2_i$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 173 \src2_i$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 176 \src2_i$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 179 \src2_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 182 \src2_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 216 \src2_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 218 \src2_i$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 183 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 184 \src3_i$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 196 \src3_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 197 \src3_i$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 199 \src3_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 200 \src3_i$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 32 input 206 \src3_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 210 \src3_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 214 \src3_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 215 \src3_i$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 198 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 201 \src4_i$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 202 \src4_i$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 207 \src4_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 217 \src4_i$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 204 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 205 \src5_i$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 211 \src5_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 203 \src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 4 input 212 \src6_i$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 269 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 270 \xer_ca_ok$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 271 \xer_ca_ok$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 275 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 276 \xer_ov_ok$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 277 \xer_ov_ok$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 278 \xer_ov_ok$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 283 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 284 \xer_so_ok$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 285 \xer_so_ok$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 attribute \src "libresoc.v:135554.8-135596.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok connect \cu_busy_o \cu_busy_o connect \cu_issue_i \cu_issue_i connect \cu_rd__go_i \cu_rd__go_i connect \cu_rd__rel_o \cu_rd__rel_o connect \cu_rdmaskn_i \cu_rdmaskn_i connect \cu_wr__go_i \cu_wr__go_i connect \cu_wr__rel_o \cu_wr__rel_o connect \dest1_o \dest1_o connect \dest2_o \dest2_o$115 connect \dest3_o \dest3_o$122 connect \dest4_o \dest4_o connect \dest5_o \dest5_o$132 connect \o_ok \o_ok connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a connect \src1_i \src1_i connect \src2_i \src2_i connect \src3_i \src3_i$60 connect \src4_i \src4_i$65 connect \xer_ca_ok \xer_ca_ok connect \xer_ov_ok \xer_ov_ok connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:135597.11-135624.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cu_busy_o \cu_busy_o$5 connect \cu_issue_i \cu_issue_i$4 connect \cu_rd__go_i \cu_rd__go_i$70 connect \cu_rd__rel_o \cu_rd__rel_o$69 connect \cu_rdmaskn_i \cu_rdmaskn_i$6 connect \cu_wr__go_i \cu_wr__go_i$137 connect \cu_wr__rel_o \cu_wr__rel_o$136 connect \dest1_o \dest1_o$141 connect \dest2_o \dest2_o$144 connect \dest3_o \dest3_o$147 connect \fast1_ok \fast1_ok connect \fast2_ok \fast2_ok connect \nia_ok \nia_ok connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk connect \src1_i \src1_i$74 connect \src2_i \src2_i$77 connect \src3_i \src3_i$71 end attribute \module_not_derived 1 attribute \src "libresoc.v:135625.7-135650.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$110 connect \cu_busy_o \cu_busy_o$2 connect \cu_issue_i \cu_issue_i$1 connect \cu_rd__go_i \cu_rd__go_i$29 connect \cu_rd__rel_o \cu_rd__rel_o$28 connect \cu_rdmaskn_i \cu_rdmaskn_i$3 connect \cu_wr__go_i \cu_wr__go_i$82 connect \cu_wr__rel_o \cu_wr__rel_o$81 connect \dest1_o \dest1_o$103 connect \dest2_o \dest2_o connect \dest3_o \dest3_o connect \full_cr_ok \full_cr_ok connect \o_ok \o_ok$80 connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type connect \src1_i \src1_i$50 connect \src2_i \src2_i$30 connect \src3_i \src3_i$67 connect \src4_i \src4_i$68 connect \src5_i \src5_i$72 connect \src6_i \src6_i$73 end attribute \module_not_derived 1 attribute \src "libresoc.v:135651.8-135690.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$112 connect \cu_busy_o \cu_busy_o$17 connect \cu_issue_i \cu_issue_i$16 connect \cu_rd__go_i \cu_rd__go_i$38 connect \cu_rd__rel_o \cu_rd__rel_o$37 connect \cu_rdmaskn_i \cu_rdmaskn_i$18 connect \cu_wr__go_i \cu_wr__go_i$94 connect \cu_wr__rel_o \cu_wr__rel_o$93 connect \dest1_o \dest1_o$107 connect \dest2_o \dest2_o$117 connect \dest3_o \dest3_o$127 connect \dest4_o \dest4_o$134 connect \o_ok \o_ok$92 connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a connect \src1_i \src1_i$56 connect \src2_i \src2_i$39 connect \src3_i \src3_i$62 connect \xer_ov_ok \xer_ov_ok$125 connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 attribute \src "libresoc.v:135691.9-135745.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cu_ad__go_i \cu_ad__go_i connect \cu_ad__rel_o \cu_ad__rel_o connect \cu_busy_o \cu_busy_o$26 connect \cu_issue_i \cu_issue_i$25 connect \cu_rd__go_i \cu_rd__go_i$47 connect \cu_rd__rel_o \cu_rd__rel_o$46 connect \cu_rdmaskn_i \cu_rdmaskn_i$27 connect \cu_st__go_i \cu_st__go_i connect \cu_st__rel_o \cu_st__rel_o connect \cu_wr__go_i \cu_wr__go_i$102 connect \cu_wr__rel_o \cu_wr__rel_o$101 connect \ea \ea connect \ldst_port0_addr_i \ldst_port0_addr_i connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o connect \ldst_port0_busy_o \ldst_port0_busy_o connect \ldst_port0_data_len \ldst_port0_data_len connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok connect \o \o connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a connect \src1_i \src1_i$59 connect \src2_i \src2_i$48 connect \src3_i \src3_i$49 end attribute \module_not_derived 1 attribute \src "libresoc.v:135746.12-135781.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$111 connect \cu_busy_o \cu_busy_o$11 connect \cu_issue_i \cu_issue_i$10 connect \cu_rd__go_i \cu_rd__go_i$35 connect \cu_rd__rel_o \cu_rd__rel_o$34 connect \cu_rdmaskn_i \cu_rdmaskn_i$12 connect \cu_wr__go_i \cu_wr__go_i$88 connect \cu_wr__rel_o \cu_wr__rel_o$87 connect \dest1_o \dest1_o$105 connect \dest2_o \dest2_o$116 connect \o_ok \o_ok$86 connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a connect \src1_i \src1_i$52 connect \src2_i \src2_i$36 connect \src3_i \src3_i$61 end attribute \module_not_derived 1 attribute \src "libresoc.v:135782.8-135815.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$113 connect \cu_busy_o \cu_busy_o$20 connect \cu_issue_i \cu_issue_i$19 connect \cu_rd__go_i \cu_rd__go_i$41 connect \cu_rd__rel_o \cu_rd__rel_o$40 connect \cu_rdmaskn_i \cu_rdmaskn_i$21 connect \cu_wr__go_i \cu_wr__go_i$97 connect \cu_wr__rel_o \cu_wr__rel_o$96 connect \dest1_o \dest1_o$108 connect \dest2_o \dest2_o$118 connect \dest3_o \dest3_o$128 connect \dest4_o \dest4_o$135 connect \o_ok \o_ok$95 connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 connect \src1_i \src1_i$57 connect \src2_i \src2_i$42 connect \src3_i \src3_i$63 connect \xer_ov_ok \xer_ov_ok$126 connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 attribute \src "libresoc.v:135816.13-135854.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \cr_a_ok$114 connect \cu_busy_o \cu_busy_o$23 connect \cu_issue_i \cu_issue_i$22 connect \cu_rd__go_i \cu_rd__go_i$44 connect \cu_rd__rel_o \cu_rd__rel_o$43 connect \cu_rdmaskn_i \cu_rdmaskn_i$24 connect \cu_wr__go_i \cu_wr__go_i$100 connect \cu_wr__rel_o \cu_wr__rel_o$99 connect \dest1_o \dest1_o$109 connect \dest2_o \dest2_o$119 connect \dest3_o \dest3_o$123 connect \o_ok \o_ok$98 connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 connect \src1_i \src1_i$58 connect \src2_i \src2_i$45 connect \src3_i \src3_i connect \src4_i \src4_i$64 connect \src5_i \src5_i connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 attribute \src "libresoc.v:135855.8-135887.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cu_busy_o \cu_busy_o$14 connect \cu_issue_i \cu_issue_i$13 connect \cu_rd__go_i \cu_rd__go_i$54 connect \cu_rd__rel_o \cu_rd__rel_o$53 connect \cu_rdmaskn_i \cu_rdmaskn_i$15 connect \cu_wr__go_i \cu_wr__go_i$91 connect \cu_wr__rel_o \cu_wr__rel_o$90 connect \dest1_o \dest1_o$106 connect \dest2_o \dest2_o$150 connect \dest3_o \dest3_o$143 connect \dest4_o \dest4_o$133 connect \dest5_o \dest5_o connect \dest6_o \dest6_o connect \fast1_ok \fast1_ok$139 connect \o_ok \o_ok$89 connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit connect \spr1_ok \spr1_ok connect \src1_i \src1_i$55 connect \src2_i \src2_i$79 connect \src3_i \src3_i$76 connect \src4_i \src4_i connect \src5_i \src5_i$66 connect \src6_i \src6_i connect \xer_ca_ok \xer_ca_ok$120 connect \xer_ov_ok \xer_ov_ok$124 connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 attribute \src "libresoc.v:135888.9-135921.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cu_busy_o \cu_busy_o$8 connect \cu_issue_i \cu_issue_i$7 connect \cu_rd__go_i \cu_rd__go_i$32 connect \cu_rd__rel_o \cu_rd__rel_o$31 connect \cu_rdmaskn_i \cu_rdmaskn_i$9 connect \cu_wr__go_i \cu_wr__go_i$85 connect \cu_wr__rel_o \cu_wr__rel_o$84 connect \dest1_o \dest1_o$104 connect \dest2_o \dest2_o$142 connect \dest3_o \dest3_o$145 connect \dest4_o \dest4_o$148 connect \dest5_o \dest5_o$149 connect \fast1_ok \fast1_ok$138 connect \fast2_ok \fast2_ok$140 connect \msr_ok \msr_ok connect \nia_ok \nia_ok$146 connect \o_ok \o_ok$83 connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype connect \src1_i \src1_i$51 connect \src2_i \src2_i$33 connect \src3_i \src3_i$75 connect \src4_i \src4_i$78 end end attribute \src "libresoc.v:135926.1-135984.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l attribute \src "libresoc.v:135927.7-135927.20" wire $0\initial[0:0] attribute \src "libresoc.v:135972.3-135980.6" wire $0\q_int$next[0:0]$5441 attribute \src "libresoc.v:135970.3-135971.27" wire $0\q_int[0:0] attribute \src "libresoc.v:135972.3-135980.6" wire $1\q_int$next[0:0]$5442 attribute \src "libresoc.v:135951.7-135951.19" wire $1\q_int[0:0] attribute \src "libresoc.v:135962.17-135962.96" wire $and$libresoc.v:135962$5431_Y attribute \src "libresoc.v:135967.17-135967.96" wire $and$libresoc.v:135967$5436_Y attribute \src "libresoc.v:135964.18-135964.95" wire $not$libresoc.v:135964$5433_Y attribute \src "libresoc.v:135966.17-135966.94" wire $not$libresoc.v:135966$5435_Y attribute \src "libresoc.v:135969.17-135969.94" wire $not$libresoc.v:135969$5438_Y attribute \src "libresoc.v:135963.18-135963.100" wire $or$libresoc.v:135963$5432_Y attribute \src "libresoc.v:135965.18-135965.101" wire $or$libresoc.v:135965$5434_Y attribute \src "libresoc.v:135968.17-135968.99" wire $or$libresoc.v:135968$5437_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:135927.7-135927.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:135962$5431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:135962$5431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:135967$5436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:135967$5436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:135964$5433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l connect \Y $not$libresoc.v:135964$5433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:135966$5435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l connect \Y $not$libresoc.v:135966$5435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:135969$5438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l connect \Y $not$libresoc.v:135969$5438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:135963$5432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l connect \Y $or$libresoc.v:135963$5432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:135965$5434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int connect \Y $or$libresoc.v:135965$5434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:135968$5437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l connect \Y $or$libresoc.v:135968$5437_Y end attribute \src "libresoc.v:135927.7-135927.20" process $proc$libresoc.v:135927$5443 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:135951.7-135951.19" process $proc$libresoc.v:135951$5444 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:135970.3-135971.27" process $proc$libresoc.v:135970$5439 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:135972.3-135980.6" process $proc$libresoc.v:135972$5440 assign { } { } assign { } { } assign $0\q_int$next[0:0]$5441 $1\q_int$next[0:0]$5442 attribute \src "libresoc.v:135973.5-135973.29" switch \initial attribute \src "libresoc.v:135973.9-135973.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$5442 1'0 case assign $1\q_int$next[0:0]$5442 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$5441 end connect \$9 $and$libresoc.v:135962$5431_Y connect \$11 $or$libresoc.v:135963$5432_Y connect \$13 $not$libresoc.v:135964$5433_Y connect \$15 $or$libresoc.v:135965$5434_Y connect \$1 $not$libresoc.v:135966$5435_Y connect \$3 $and$libresoc.v:135967$5436_Y connect \$5 $or$libresoc.v:135968$5437_Y connect \$7 $not$libresoc.v:135969$5438_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end attribute \src "libresoc.v:135988.1-136367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem attribute \src "libresoc.v:136319.3-136328.6" wire $0\a_busy_o[0:0] attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $0\f_badaddr_o$next[44:0]$5513 attribute \src "libresoc.v:136130.3-136131.39" wire width 45 $0\f_badaddr_o[44:0] attribute \src "libresoc.v:136329.3-136346.6" wire $0\f_busy_o[0:0] attribute \src "libresoc.v:136276.3-136298.6" wire $0\f_fetch_err_o$next[0:0]$5508 attribute \src "libresoc.v:136132.3-136133.43" wire $0\f_fetch_err_o[0:0] attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $0\f_instr_o[63:0] attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $0\ibus__adr$next[44:0]$5503 attribute \src "libresoc.v:136134.3-136135.35" wire width 45 $0\ibus__adr[44:0] attribute \src "libresoc.v:136144.3-136171.6" wire $0\ibus__cyc$next[0:0]$5479 attribute \src "libresoc.v:136142.3-136143.35" wire $0\ibus__cyc[0:0] attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $0\ibus__sel$next[7:0]$5491 attribute \src "libresoc.v:136138.3-136139.35" wire width 8 $0\ibus__sel[7:0] attribute \src "libresoc.v:136172.3-136199.6" wire $0\ibus__stb$next[0:0]$5485 attribute \src "libresoc.v:136140.3-136141.35" wire $0\ibus__stb[0:0] attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $0\ibus_rdata$next[63:0]$5497 attribute \src "libresoc.v:136136.3-136137.37" wire width 64 $0\ibus_rdata[63:0] attribute \src "libresoc.v:135989.7-135989.20" wire $0\initial[0:0] attribute \src "libresoc.v:136319.3-136328.6" wire $1\a_busy_o[0:0] attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $1\f_badaddr_o$next[44:0]$5514 attribute \src "libresoc.v:136053.14-136053.44" wire width 45 $1\f_badaddr_o[44:0] attribute \src "libresoc.v:136329.3-136346.6" wire $1\f_busy_o[0:0] attribute \src "libresoc.v:136276.3-136298.6" wire $1\f_fetch_err_o$next[0:0]$5509 attribute \src "libresoc.v:136060.7-136060.27" wire $1\f_fetch_err_o[0:0] attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $1\f_instr_o[63:0] attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $1\ibus__adr$next[44:0]$5504 attribute \src "libresoc.v:136074.14-136074.42" wire width 45 $1\ibus__adr[44:0] attribute \src "libresoc.v:136144.3-136171.6" wire $1\ibus__cyc$next[0:0]$5480 attribute \src "libresoc.v:136079.7-136079.23" wire $1\ibus__cyc[0:0] attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $1\ibus__sel$next[7:0]$5492 attribute \src "libresoc.v:136088.13-136088.30" wire width 8 $1\ibus__sel[7:0] attribute \src "libresoc.v:136172.3-136199.6" wire $1\ibus__stb$next[0:0]$5486 attribute \src "libresoc.v:136093.7-136093.23" wire $1\ibus__stb[0:0] attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $1\ibus_rdata$next[63:0]$5498 attribute \src "libresoc.v:136097.14-136097.47" wire width 64 $1\ibus_rdata[63:0] attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $2\f_badaddr_o$next[44:0]$5515 attribute \src "libresoc.v:136329.3-136346.6" wire $2\f_busy_o[0:0] attribute \src "libresoc.v:136276.3-136298.6" wire $2\f_fetch_err_o$next[0:0]$5510 attribute \src "libresoc.v:136347.3-136364.6" wire width 64 $2\f_instr_o[63:0] attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $2\ibus__adr$next[44:0]$5505 attribute \src "libresoc.v:136144.3-136171.6" wire $2\ibus__cyc$next[0:0]$5481 attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $2\ibus__sel$next[7:0]$5493 attribute \src "libresoc.v:136172.3-136199.6" wire $2\ibus__stb$next[0:0]$5487 attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $2\ibus_rdata$next[63:0]$5499 attribute \src "libresoc.v:136299.3-136318.6" wire width 45 $3\f_badaddr_o$next[44:0]$5516 attribute \src "libresoc.v:136276.3-136298.6" wire $3\f_fetch_err_o$next[0:0]$5511 attribute \src "libresoc.v:136253.3-136275.6" wire width 45 $3\ibus__adr$next[44:0]$5506 attribute \src "libresoc.v:136144.3-136171.6" wire $3\ibus__cyc$next[0:0]$5482 attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $3\ibus__sel$next[7:0]$5494 attribute \src "libresoc.v:136172.3-136199.6" wire $3\ibus__stb$next[0:0]$5488 attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $3\ibus_rdata$next[63:0]$5500 attribute \src "libresoc.v:136144.3-136171.6" wire $4\ibus__cyc$next[0:0]$5483 attribute \src "libresoc.v:136200.3-136227.6" wire width 8 $4\ibus__sel$next[7:0]$5495 attribute \src "libresoc.v:136172.3-136199.6" wire $4\ibus__stb$next[0:0]$5489 attribute \src "libresoc.v:136228.3-136252.6" wire width 64 $4\ibus_rdata$next[63:0]$5501 attribute \src "libresoc.v:136106.18-136106.110" wire $and$libresoc.v:136106$5447_Y attribute \src "libresoc.v:136112.18-136112.110" wire $and$libresoc.v:136112$5453_Y attribute \src "libresoc.v:136117.18-136117.110" wire $and$libresoc.v:136117$5458_Y attribute \src "libresoc.v:136120.17-136120.108" wire $and$libresoc.v:136120$5461_Y attribute \src "libresoc.v:136123.18-136123.110" wire $and$libresoc.v:136123$5464_Y attribute \src "libresoc.v:136124.18-136124.115" wire $and$libresoc.v:136124$5465_Y attribute \src "libresoc.v:136126.18-136126.115" wire $and$libresoc.v:136126$5467_Y attribute \src "libresoc.v:136105.18-136105.105" wire $not$libresoc.v:136105$5446_Y attribute \src "libresoc.v:136108.18-136108.105" wire $not$libresoc.v:136108$5449_Y attribute \src "libresoc.v:136109.17-136109.104" wire $not$libresoc.v:136109$5450_Y attribute \src "libresoc.v:136111.18-136111.105" wire $not$libresoc.v:136111$5452_Y attribute \src "libresoc.v:136114.18-136114.105" wire $not$libresoc.v:136114$5455_Y attribute \src "libresoc.v:136116.18-136116.105" wire $not$libresoc.v:136116$5457_Y attribute \src "libresoc.v:136119.18-136119.105" wire $not$libresoc.v:136119$5460_Y attribute \src "libresoc.v:136122.18-136122.105" wire $not$libresoc.v:136122$5463_Y attribute \src "libresoc.v:136125.18-136125.105" wire $not$libresoc.v:136125$5466_Y attribute \src "libresoc.v:136127.18-136127.105" wire $not$libresoc.v:136127$5468_Y attribute \src "libresoc.v:136129.17-136129.104" wire $not$libresoc.v:136129$5470_Y attribute \src "libresoc.v:136104.17-136104.103" wire $or$libresoc.v:136104$5445_Y attribute \src "libresoc.v:136107.18-136107.115" wire $or$libresoc.v:136107$5448_Y attribute \src "libresoc.v:136110.18-136110.106" wire $or$libresoc.v:136110$5451_Y attribute \src "libresoc.v:136113.18-136113.115" wire $or$libresoc.v:136113$5454_Y attribute \src "libresoc.v:136115.18-136115.106" wire $or$libresoc.v:136115$5456_Y attribute \src "libresoc.v:136118.18-136118.115" wire $or$libresoc.v:136118$5459_Y attribute \src "libresoc.v:136121.18-136121.106" wire $or$libresoc.v:136121$5462_Y attribute \src "libresoc.v:136128.17-136128.114" wire $or$libresoc.v:136128$5469_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" wire \a_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 input 2 \a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" wire output 5 \f_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" wire \f_fetch_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" wire \f_fetch_err_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" wire width 64 output 6 \f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" wire \f_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" wire input 4 \f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 9 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 45 output 14 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 45 \ibus__adr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 8 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire \ibus__cyc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 64 input 13 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 10 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 8 output 12 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 8 \ibus__sel$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 11 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire \ibus__stb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next attribute \src "libresoc.v:135989.7-135989.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $and $and$libresoc.v:136106$5447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 connect \Y $and$libresoc.v:136106$5447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $and $and$libresoc.v:136112$5453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 connect \Y $and$libresoc.v:136112$5453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $and $and$libresoc.v:136117$5458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 connect \Y $and$libresoc.v:136117$5458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $and $and$libresoc.v:136120$5461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 connect \Y $and$libresoc.v:136120$5461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $and $and$libresoc.v:136123$5464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 connect \Y $and$libresoc.v:136123$5464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" cell $and $and$libresoc.v:136124$5465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err connect \Y $and$libresoc.v:136124$5465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" cell $and $and$libresoc.v:136126$5467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err connect \Y $and$libresoc.v:136126$5467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $not $not$libresoc.v:136105$5446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i connect \Y $not$libresoc.v:136105$5446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $not $not$libresoc.v:136108$5449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i connect \Y $not$libresoc.v:136108$5449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $not $not$libresoc.v:136109$5450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i connect \Y $not$libresoc.v:136109$5450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $not $not$libresoc.v:136111$5452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i connect \Y $not$libresoc.v:136111$5452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $not $not$libresoc.v:136114$5455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i connect \Y $not$libresoc.v:136114$5455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $not $not$libresoc.v:136116$5457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i connect \Y $not$libresoc.v:136116$5457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $not $not$libresoc.v:136119$5460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i connect \Y $not$libresoc.v:136119$5460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" cell $not $not$libresoc.v:136122$5463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i connect \Y $not$libresoc.v:136122$5463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" cell $not $not$libresoc.v:136125$5466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i connect \Y $not$libresoc.v:136125$5466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" cell $not $not$libresoc.v:136127$5468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i connect \Y $not$libresoc.v:136127$5468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $not $not$libresoc.v:136129$5470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i connect \Y $not$libresoc.v:136129$5470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136104$5445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 connect \Y $or$libresoc.v:136104$5445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136107$5448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err connect \Y $or$libresoc.v:136107$5448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136110$5451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 connect \Y $or$libresoc.v:136110$5451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136113$5454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err connect \Y $or$libresoc.v:136113$5454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136115$5456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 connect \Y $or$libresoc.v:136115$5456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136118$5459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err connect \Y $or$libresoc.v:136118$5459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136121$5462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 connect \Y $or$libresoc.v:136121$5462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" cell $or $or$libresoc.v:136128$5469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err connect \Y $or$libresoc.v:136128$5469_Y end attribute \src "libresoc.v:135989.7-135989.20" process $proc$libresoc.v:135989$5520 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:136053.14-136053.44" process $proc$libresoc.v:136053$5521 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end attribute \src "libresoc.v:136060.7-136060.27" process $proc$libresoc.v:136060$5522 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end attribute \src "libresoc.v:136074.14-136074.42" process $proc$libresoc.v:136074$5523 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end attribute \src "libresoc.v:136079.7-136079.23" process $proc$libresoc.v:136079$5524 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end attribute \src "libresoc.v:136088.13-136088.30" process $proc$libresoc.v:136088$5525 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end attribute \src "libresoc.v:136093.7-136093.23" process $proc$libresoc.v:136093$5526 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end attribute \src "libresoc.v:136097.14-136097.47" process $proc$libresoc.v:136097$5527 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end attribute \src "libresoc.v:136130.3-136131.39" process $proc$libresoc.v:136130$5471 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end attribute \src "libresoc.v:136132.3-136133.43" process $proc$libresoc.v:136132$5472 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end attribute \src "libresoc.v:136134.3-136135.35" process $proc$libresoc.v:136134$5473 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end attribute \src "libresoc.v:136136.3-136137.37" process $proc$libresoc.v:136136$5474 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end attribute \src "libresoc.v:136138.3-136139.35" process $proc$libresoc.v:136138$5475 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end attribute \src "libresoc.v:136140.3-136141.35" process $proc$libresoc.v:136140$5476 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end attribute \src "libresoc.v:136142.3-136143.35" process $proc$libresoc.v:136142$5477 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end attribute \src "libresoc.v:136144.3-136171.6" process $proc$libresoc.v:136144$5478 assign { } { } assign { } { } assign { } { } assign $0\ibus__cyc$next[0:0]$5479 $4\ibus__cyc$next[0:0]$5483 attribute \src "libresoc.v:136145.5-136145.29" switch \initial attribute \src "libresoc.v:136145.9-136145.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ibus__cyc$next[0:0]$5480 $2\ibus__cyc$next[0:0]$5481 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\ibus__cyc$next[0:0]$5481 $3\ibus__cyc$next[0:0]$5482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ibus__cyc$next[0:0]$5482 1'0 case assign $3\ibus__cyc$next[0:0]$5482 \ibus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\ibus__cyc$next[0:0]$5481 1'1 case assign $2\ibus__cyc$next[0:0]$5481 \ibus__cyc end case assign $1\ibus__cyc$next[0:0]$5480 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\ibus__cyc$next[0:0]$5483 1'0 case assign $4\ibus__cyc$next[0:0]$5483 $1\ibus__cyc$next[0:0]$5480 end sync always update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5479 end attribute \src "libresoc.v:136172.3-136199.6" process $proc$libresoc.v:136172$5484 assign { } { } assign { } { } assign { } { } assign $0\ibus__stb$next[0:0]$5485 $4\ibus__stb$next[0:0]$5489 attribute \src "libresoc.v:136173.5-136173.29" switch \initial attribute \src "libresoc.v:136173.9-136173.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ibus__stb$next[0:0]$5486 $2\ibus__stb$next[0:0]$5487 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\ibus__stb$next[0:0]$5487 $3\ibus__stb$next[0:0]$5488 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ibus__stb$next[0:0]$5488 1'0 case assign $3\ibus__stb$next[0:0]$5488 \ibus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\ibus__stb$next[0:0]$5487 1'1 case assign $2\ibus__stb$next[0:0]$5487 \ibus__stb end case assign $1\ibus__stb$next[0:0]$5486 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\ibus__stb$next[0:0]$5489 1'0 case assign $4\ibus__stb$next[0:0]$5489 $1\ibus__stb$next[0:0]$5486 end sync always update \ibus__stb$next $0\ibus__stb$next[0:0]$5485 end attribute \src "libresoc.v:136200.3-136227.6" process $proc$libresoc.v:136200$5490 assign { } { } assign { } { } assign { } { } assign $0\ibus__sel$next[7:0]$5491 $4\ibus__sel$next[7:0]$5495 attribute \src "libresoc.v:136201.5-136201.29" switch \initial attribute \src "libresoc.v:136201.9-136201.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ibus__sel$next[7:0]$5492 $2\ibus__sel$next[7:0]$5493 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\ibus__sel$next[7:0]$5493 $3\ibus__sel$next[7:0]$5494 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ibus__sel$next[7:0]$5494 8'00000000 case assign $3\ibus__sel$next[7:0]$5494 \ibus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\ibus__sel$next[7:0]$5493 8'11111111 case assign $2\ibus__sel$next[7:0]$5493 \ibus__sel end case assign $1\ibus__sel$next[7:0]$5492 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\ibus__sel$next[7:0]$5495 8'00000000 case assign $4\ibus__sel$next[7:0]$5495 $1\ibus__sel$next[7:0]$5492 end sync always update \ibus__sel$next $0\ibus__sel$next[7:0]$5491 end attribute \src "libresoc.v:136228.3-136252.6" process $proc$libresoc.v:136228$5496 assign { } { } assign { } { } assign { } { } assign $0\ibus_rdata$next[63:0]$5497 $4\ibus_rdata$next[63:0]$5501 attribute \src "libresoc.v:136229.5-136229.29" switch \initial attribute \src "libresoc.v:136229.9-136229.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ibus_rdata$next[63:0]$5498 $2\ibus_rdata$next[63:0]$5499 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\ibus_rdata$next[63:0]$5499 $3\ibus_rdata$next[63:0]$5500 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ibus_rdata$next[63:0]$5500 \ibus__dat_r case assign $3\ibus_rdata$next[63:0]$5500 \ibus_rdata end case assign $2\ibus_rdata$next[63:0]$5499 \ibus_rdata end case assign $1\ibus_rdata$next[63:0]$5498 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\ibus_rdata$next[63:0]$5501 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $4\ibus_rdata$next[63:0]$5501 $1\ibus_rdata$next[63:0]$5498 end sync always update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5497 end attribute \src "libresoc.v:136253.3-136275.6" process $proc$libresoc.v:136253$5502 assign { } { } assign { } { } assign { } { } assign $0\ibus__adr$next[44:0]$5503 $3\ibus__adr$next[44:0]$5506 attribute \src "libresoc.v:136254.5-136254.29" switch \initial attribute \src "libresoc.v:136254.9-136254.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ibus__adr$next[44:0]$5504 $2\ibus__adr$next[44:0]$5505 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$43 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $2\ibus__adr$next[44:0]$5505 \ibus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\ibus__adr$next[44:0]$5505 \a_pc_i [47:3] case assign $2\ibus__adr$next[44:0]$5505 \ibus__adr end case assign $1\ibus__adr$next[44:0]$5504 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ibus__adr$next[44:0]$5506 45'000000000000000000000000000000000000000000000 case assign $3\ibus__adr$next[44:0]$5506 $1\ibus__adr$next[44:0]$5504 end sync always update \ibus__adr$next $0\ibus__adr$next[44:0]$5503 end attribute \src "libresoc.v:136276.3-136298.6" process $proc$libresoc.v:136276$5507 assign { } { } assign { } { } assign { } { } assign $0\f_fetch_err_o$next[0:0]$5508 $3\f_fetch_err_o$next[0:0]$5511 attribute \src "libresoc.v:136277.5-136277.29" switch \initial attribute \src "libresoc.v:136277.9-136277.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\f_fetch_err_o$next[0:0]$5509 $2\f_fetch_err_o$next[0:0]$5510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$47 \$45 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\f_fetch_err_o$next[0:0]$5510 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\f_fetch_err_o$next[0:0]$5510 1'0 case assign $2\f_fetch_err_o$next[0:0]$5510 \f_fetch_err_o end case assign $1\f_fetch_err_o$next[0:0]$5509 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\f_fetch_err_o$next[0:0]$5511 1'0 case assign $3\f_fetch_err_o$next[0:0]$5511 $1\f_fetch_err_o$next[0:0]$5509 end sync always update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5508 end attribute \src "libresoc.v:136299.3-136318.6" process $proc$libresoc.v:136299$5512 assign { } { } assign { } { } assign { } { } assign $0\f_badaddr_o$next[44:0]$5513 $3\f_badaddr_o$next[44:0]$5516 attribute \src "libresoc.v:136300.5-136300.29" switch \initial attribute \src "libresoc.v:136300.9-136300.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\f_badaddr_o$next[44:0]$5514 $2\f_badaddr_o$next[44:0]$5515 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$51 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\f_badaddr_o$next[44:0]$5515 \ibus__adr case assign $2\f_badaddr_o$next[44:0]$5515 \f_badaddr_o end case assign $1\f_badaddr_o$next[44:0]$5514 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\f_badaddr_o$next[44:0]$5516 45'000000000000000000000000000000000000000000000 case assign $3\f_badaddr_o$next[44:0]$5516 $1\f_badaddr_o$next[44:0]$5514 end sync always update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5513 end attribute \src "libresoc.v:136319.3-136328.6" process $proc$libresoc.v:136319$5517 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] attribute \src "libresoc.v:136320.5-136320.29" switch \initial attribute \src "libresoc.v:136320.9-136320.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\a_busy_o[0:0] \ibus__cyc case assign $1\a_busy_o[0:0] 1'0 end sync always update \a_busy_o $0\a_busy_o[0:0] end attribute \src "libresoc.v:136329.3-136346.6" process $proc$libresoc.v:136329$5518 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] attribute \src "libresoc.v:136330.5-136330.29" switch \initial attribute \src "libresoc.v:136330.9-136330.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" switch \f_fetch_err_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\f_busy_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\f_busy_o[0:0] \ibus__cyc end case assign $1\f_busy_o[0:0] 1'0 end sync always update \f_busy_o $0\f_busy_o[0:0] end attribute \src "libresoc.v:136347.3-136364.6" process $proc$libresoc.v:136347$5519 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] attribute \src "libresoc.v:136348.5-136348.29" switch \initial attribute \src "libresoc.v:136348.9-136348.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" switch \f_fetch_err_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\f_instr_o[63:0] \ibus_rdata end case assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \f_instr_o $0\f_instr_o[63:0] end connect \$9 $or$libresoc.v:136104$5445_Y connect \$11 $not$libresoc.v:136105$5446_Y connect \$13 $and$libresoc.v:136106$5447_Y connect \$15 $or$libresoc.v:136107$5448_Y connect \$17 $not$libresoc.v:136108$5449_Y connect \$1 $not$libresoc.v:136109$5450_Y connect \$19 $or$libresoc.v:136110$5451_Y connect \$21 $not$libresoc.v:136111$5452_Y connect \$23 $and$libresoc.v:136112$5453_Y connect \$25 $or$libresoc.v:136113$5454_Y connect \$27 $not$libresoc.v:136114$5455_Y connect \$29 $or$libresoc.v:136115$5456_Y connect \$31 $not$libresoc.v:136116$5457_Y connect \$33 $and$libresoc.v:136117$5458_Y connect \$35 $or$libresoc.v:136118$5459_Y connect \$37 $not$libresoc.v:136119$5460_Y connect \$3 $and$libresoc.v:136120$5461_Y connect \$39 $or$libresoc.v:136121$5462_Y connect \$41 $not$libresoc.v:136122$5463_Y connect \$43 $and$libresoc.v:136123$5464_Y connect \$45 $and$libresoc.v:136124$5465_Y connect \$47 $not$libresoc.v:136125$5466_Y connect \$49 $and$libresoc.v:136126$5467_Y connect \$51 $not$libresoc.v:136127$5468_Y connect \$5 $or$libresoc.v:136128$5469_Y connect \$7 $not$libresoc.v:136129$5470_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end attribute \src "libresoc.v:136371.1-136698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input attribute \src "libresoc.v:136661.3-136672.6" wire width 64 $0\a[63:0] attribute \src "libresoc.v:136372.7-136372.20" wire $0\initial[0:0] attribute \src "libresoc.v:136673.3-136691.6" wire width 2 $0\xer_ca$23[1:0]$5531 attribute \src "libresoc.v:136661.3-136672.6" wire width 64 $1\a[63:0] attribute \src "libresoc.v:136673.3-136691.6" wire width 2 $1\xer_ca$23[1:0]$5532 attribute \src "libresoc.v:136660.18-136660.100" wire width 64 $not$libresoc.v:136660$5528_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 26 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \alu_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 13 \alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 36 \alu_op__input_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 41 \alu_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \alu_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \alu_op__write_cr0$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \src "libresoc.v:136372.7-136372.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 42 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 43 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 22 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 output 45 \xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" cell $not $not$libresoc.v:136660$5528 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \Y $not$libresoc.v:136660$5528_Y end attribute \src "libresoc.v:136372.7-136372.20" process $proc$libresoc.v:136372$5533 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:136661.3-136672.6" process $proc$libresoc.v:136661$5529 assign { } { } assign $0\a[63:0] $1\a[63:0] attribute \src "libresoc.v:136662.5-136662.29" switch \initial attribute \src "libresoc.v:136662.9-136662.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" switch \alu_op__invert_in attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\a[63:0] \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\a[63:0] \ra end sync always update \a $0\a[63:0] end attribute \src "libresoc.v:136673.3-136691.6" process $proc$libresoc.v:136673$5530 assign { } { } assign { } { } assign $0\xer_ca$23[1:0]$5531 $1\xer_ca$23[1:0]$5532 attribute \src "libresoc.v:136674.5-136674.29" switch \initial attribute \src "libresoc.v:136674.9-136674.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" switch \alu_op__input_carry attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\xer_ca$23[1:0]$5532 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\xer_ca$23[1:0]$5532 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\xer_ca$23[1:0]$5532 \xer_ca case assign $1\xer_ca$23[1:0]$5532 2'00 end sync always update \xer_ca$23 $0\xer_ca$23[1:0]$5531 end connect \$24 $not$libresoc.v:136660$5528_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so connect \rb$21 \rb connect \b \rb connect \ra$20 \a end attribute \src "libresoc.v:136702.1-137030.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 attribute \src "libresoc.v:136992.3-137003.6" wire width 64 $0\a[63:0] attribute \src "libresoc.v:136703.7-136703.20" wire $0\initial[0:0] attribute \src "libresoc.v:137004.3-137022.6" wire width 2 $0\xer_ca$23[1:0]$5537 attribute \src "libresoc.v:136992.3-137003.6" wire width 64 $1\a[63:0] attribute \src "libresoc.v:137004.3-137022.6" wire width 2 $1\xer_ca$23[1:0]$5538 attribute \src "libresoc.v:136991.18-136991.100" wire width 64 $not$libresoc.v:136991$5534_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \src "libresoc.v:136703.7-136703.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 41 \ra$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 42 \rb$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 43 \rc$21 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 26 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \sr_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 34 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 17 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 40 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 22 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 output 45 \xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" cell $not $not$libresoc.v:136991$5534 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \Y $not$libresoc.v:136991$5534_Y end attribute \src "libresoc.v:136703.7-136703.20" process $proc$libresoc.v:136703$5539 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:136992.3-137003.6" process $proc$libresoc.v:136992$5535 assign { } { } assign $0\a[63:0] $1\a[63:0] attribute \src "libresoc.v:136993.5-136993.29" switch \initial attribute \src "libresoc.v:136993.9-136993.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" switch \sr_op__invert_in attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\a[63:0] \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\a[63:0] \ra end sync always update \a $0\a[63:0] end attribute \src "libresoc.v:137004.3-137022.6" process $proc$libresoc.v:137004$5536 assign { } { } assign { } { } assign $0\xer_ca$23[1:0]$5537 $1\xer_ca$23[1:0]$5538 attribute \src "libresoc.v:137005.5-137005.29" switch \initial attribute \src "libresoc.v:137005.9-137005.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" switch \sr_op__input_carry attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\xer_ca$23[1:0]$5538 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\xer_ca$23[1:0]$5538 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\xer_ca$23[1:0]$5538 \xer_ca case assign $1\xer_ca$23[1:0]$5538 2'00 end sync always update \xer_ca$23 $0\xer_ca$23[1:0]$5537 end connect \$24 $not$libresoc.v:136991$5534_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so connect \rb$20 \b connect \b \rb connect \ra$19 \a end attribute \src "libresoc.v:137034.1-137337.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 attribute \src "libresoc.v:137319.3-137330.6" wire width 64 $0\b[63:0] attribute \src "libresoc.v:137035.7-137035.20" wire $0\initial[0:0] attribute \src "libresoc.v:137319.3-137330.6" wire width 64 $1\b[63:0] attribute \src "libresoc.v:137318.18-137318.100" wire width 64 $not$libresoc.v:137318$5540_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \src "libresoc.v:137035.7-137035.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 33 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 40 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 41 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 42 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" cell $not $not$libresoc.v:137318$5540 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb connect \Y $not$libresoc.v:137318$5540_Y end attribute \src "libresoc.v:137035.7-137035.20" process $proc$libresoc.v:137035$5542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:137319.3-137330.6" process $proc$libresoc.v:137319$5541 assign { } { } assign $0\b[63:0] $1\b[63:0] attribute \src "libresoc.v:137320.5-137320.29" switch \initial attribute \src "libresoc.v:137320.9-137320.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" switch \logical_op__invert_in attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\b[63:0] \$23 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\b[63:0] \rb end sync always update \b $0\b[63:0] end connect \$23 $not$libresoc.v:137318$5540_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so connect \rb$21 \b connect \ra$20 \a connect \a \ra end attribute \src "libresoc.v:137341.1-137644.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 attribute \src "libresoc.v:137626.3-137637.6" wire width 64 $0\a[63:0] attribute \src "libresoc.v:137342.7-137342.20" wire $0\initial[0:0] attribute \src "libresoc.v:137626.3-137637.6" wire width 64 $1\a[63:0] attribute \src "libresoc.v:137625.18-137625.100" wire width 64 $not$libresoc.v:137625$5543_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \src "libresoc.v:137342.7-137342.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 33 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 40 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 41 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 42 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" cell $not $not$libresoc.v:137625$5543 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \Y $not$libresoc.v:137625$5543_Y end attribute \src "libresoc.v:137342.7-137342.20" process $proc$libresoc.v:137342$5545 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:137626.3-137637.6" process $proc$libresoc.v:137626$5544 assign { } { } assign $0\a[63:0] $1\a[63:0] attribute \src "libresoc.v:137627.5-137627.29" switch \initial attribute \src "libresoc.v:137627.9-137627.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" switch \logical_op__invert_in attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\a[63:0] \$23 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\a[63:0] \ra end sync always update \a $0\a[63:0] end connect \$23 $not$libresoc.v:137625$5543_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so connect \rb$21 \rb connect \b \rb connect \ra$20 \a end attribute \src "libresoc.v:137648.1-137904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" module \input$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 28 \mul_op__insn$13 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 23 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 24 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 22 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 21 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 32 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 29 \ra$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 30 \rb$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 15 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$16 \xer_so connect \rb$15 \rb connect \b \rb connect \ra$14 \a connect \a \ra end attribute \src "libresoc.v:137908.1-138047.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 attribute \src "libresoc.v:137993.3-137997.6" wire width 64 $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 attribute \src "libresoc.v:137993.3-137997.6" wire width 64 $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $0\_0_[4:0] attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $0\_1_[4:0] attribute \src "libresoc.v:138013.3-138022.6" wire width 64 $0\dmi__data_o[63:0] attribute \src "libresoc.v:137909.7-137909.20" wire $0\initial[0:0] attribute \src "libresoc.v:138023.3-138031.6" wire $0\ren_delay$4$next[0:0]$5596 attribute \src "libresoc.v:138000.3-138001.41" wire $0\ren_delay$4[0:0]$5589 attribute \src "libresoc.v:137944.7-137944.27" wire $0\ren_delay$4[0:0]$5634 attribute \src "libresoc.v:138004.3-138012.6" wire $0\ren_delay$next[0:0]$5592 attribute \src "libresoc.v:138002.3-138003.35" wire $0\ren_delay[0:0] attribute \src "libresoc.v:138032.3-138041.6" wire width 64 $0\src1__data_o[63:0] attribute \src "libresoc.v:137993.3-137997.6" wire width 5 $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 attribute \src "libresoc.v:137993.3-137997.6" wire width 64 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 attribute \src "libresoc.v:137993.3-137997.6" wire width 64 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 attribute \src "libresoc.v:138013.3-138022.6" wire width 64 $1\dmi__data_o[63:0] attribute \src "libresoc.v:138023.3-138031.6" wire $1\ren_delay$4$next[0:0]$5597 attribute \src "libresoc.v:138004.3-138012.6" wire $1\ren_delay$next[0:0]$5593 attribute \src "libresoc.v:137942.7-137942.23" wire $1\ren_delay[0:0] attribute \src "libresoc.v:138032.3-138041.6" wire width 64 $1\src1__data_o[63:0] attribute \src "libresoc.v:137998.26-137998.32" wire width 64 $memrd$\memory$libresoc.v:137998$5586_DATA attribute \src "libresoc.v:137999.30-137999.36" wire width 64 $memrd$\memory$libresoc.v:137999$5587_DATA attribute \src "libresoc.v:0.0-0.0" wire width 5 $memwr$\memory$libresoc.v:137996$5578_ADDR attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:137996$5578_DATA attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:137996$5578_EN attribute \src "libresoc.v:137991.13-137991.16" wire width 5 \_0_ attribute \src "libresoc.v:137992.13-137992.16" wire width 5 \_1_ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 11 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 9 \dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 8 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 2 \dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren attribute \src "libresoc.v:137909.7-137909.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 5 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 6 \src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \src1__ren attribute \src "libresoc.v:137956.14-137956.20" memory width 64 size 32 \memory attribute \src "libresoc.v:137958.5-137958.37" cell $meminit $meminit$\memory$libresoc.v:137958$5599 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5599 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137959.5-137959.37" cell $meminit $meminit$\memory$libresoc.v:137959$5600 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5600 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137960.5-137960.37" cell $meminit $meminit$\memory$libresoc.v:137960$5601 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5601 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137961.5-137961.37" cell $meminit $meminit$\memory$libresoc.v:137961$5602 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5602 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137962.5-137962.37" cell $meminit $meminit$\memory$libresoc.v:137962$5603 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5603 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137963.5-137963.37" cell $meminit $meminit$\memory$libresoc.v:137963$5604 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5604 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137964.5-137964.37" cell $meminit $meminit$\memory$libresoc.v:137964$5605 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5605 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137965.5-137965.37" cell $meminit $meminit$\memory$libresoc.v:137965$5606 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5606 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137966.5-137966.37" cell $meminit $meminit$\memory$libresoc.v:137966$5607 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5607 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137967.5-137967.37" cell $meminit $meminit$\memory$libresoc.v:137967$5608 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5608 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137968.5-137968.38" cell $meminit $meminit$\memory$libresoc.v:137968$5609 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5609 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137969.5-137969.38" cell $meminit $meminit$\memory$libresoc.v:137969$5610 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5610 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137970.5-137970.38" cell $meminit $meminit$\memory$libresoc.v:137970$5611 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5611 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137971.5-137971.38" cell $meminit $meminit$\memory$libresoc.v:137971$5612 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5612 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137972.5-137972.38" cell $meminit $meminit$\memory$libresoc.v:137972$5613 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5613 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137973.5-137973.38" cell $meminit $meminit$\memory$libresoc.v:137973$5614 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5614 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137974.5-137974.38" cell $meminit $meminit$\memory$libresoc.v:137974$5615 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5615 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137975.5-137975.38" cell $meminit $meminit$\memory$libresoc.v:137975$5616 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5616 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137976.5-137976.38" cell $meminit $meminit$\memory$libresoc.v:137976$5617 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5617 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137977.5-137977.38" cell $meminit $meminit$\memory$libresoc.v:137977$5618 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5618 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137978.5-137978.38" cell $meminit $meminit$\memory$libresoc.v:137978$5619 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5619 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137979.5-137979.38" cell $meminit $meminit$\memory$libresoc.v:137979$5620 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5620 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137980.5-137980.38" cell $meminit $meminit$\memory$libresoc.v:137980$5621 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5621 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137981.5-137981.38" cell $meminit $meminit$\memory$libresoc.v:137981$5622 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5622 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137982.5-137982.38" cell $meminit $meminit$\memory$libresoc.v:137982$5623 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5623 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137983.5-137983.38" cell $meminit $meminit$\memory$libresoc.v:137983$5624 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5624 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137984.5-137984.38" cell $meminit $meminit$\memory$libresoc.v:137984$5625 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5625 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137985.5-137985.38" cell $meminit $meminit$\memory$libresoc.v:137985$5626 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5626 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137986.5-137986.38" cell $meminit $meminit$\memory$libresoc.v:137986$5627 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5627 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137987.5-137987.38" cell $meminit $meminit$\memory$libresoc.v:137987$5628 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5628 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137988.5-137988.38" cell $meminit $meminit$\memory$libresoc.v:137988$5629 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5629 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137989.5-137989.38" cell $meminit $meminit$\memory$libresoc.v:137989$5630 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 5630 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:137998.26-137998.32" cell $memrd $memrd$\memory$libresoc.v:137998$5586 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" parameter \TRANSPARENT 0 parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x connect \DATA $memrd$\memory$libresoc.v:137998$5586_DATA connect \EN 1'x end attribute \src "libresoc.v:137999.30-137999.36" cell $memrd $memrd$\memory$libresoc.v:137999$5587 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" parameter \TRANSPARENT 0 parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x connect \DATA $memrd$\memory$libresoc.v:137999$5587_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" process $proc$libresoc.v:0$5635 sync always sync init end attribute \src "libresoc.v:137909.7-137909.20" process $proc$libresoc.v:137909$5631 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:137942.7-137942.23" process $proc$libresoc.v:137942$5632 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end attribute \src "libresoc.v:137944.7-137944.27" process $proc$libresoc.v:137944$5633 assign { } { } assign $0\ren_delay$4[0:0]$5634 1'0 sync always sync init update \ren_delay$4 $0\ren_delay$4[0:0]$5634 end attribute \src "libresoc.v:137993.3-137997.6" process $proc$libresoc.v:137993$5579 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\_0_[4:0] \memory_r_addr assign $0\_1_[4:0] \memory_r_addr$2 assign $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 assign $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 assign $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 attribute \src "libresoc.v:137996.5-137996.61" switch \memory_w_en attribute \src "libresoc.v:137996.9-137996.20" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 \memory_w_addr assign $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 \memory_w_data assign $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 64'1111111111111111111111111111111111111111111111111111111111111111 case assign $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 5'xxxxx assign $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[4:0] update \_1_ $0\_1_[4:0] update $memwr$\memory$libresoc.v:137996$5578_ADDR $0$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5580 update $memwr$\memory$libresoc.v:137996$5578_DATA $0$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5581 update $memwr$\memory$libresoc.v:137996$5578_EN $0$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5582 attribute \src "libresoc.v:137996.22-137996.60" memwr \memory $1$memwr$\memory$libresoc.v:137996$5578_ADDR[4:0]$5583 $1$memwr$\memory$libresoc.v:137996$5578_DATA[63:0]$5584 $1$memwr$\memory$libresoc.v:137996$5578_EN[63:0]$5585 0' end attribute \src "libresoc.v:138000.3-138001.41" process $proc$libresoc.v:138000$5588 assign { } { } assign $0\ren_delay$4[0:0]$5589 \ren_delay$4$next sync posedge \coresync_clk update \ren_delay$4 $0\ren_delay$4[0:0]$5589 end attribute \src "libresoc.v:138002.3-138003.35" process $proc$libresoc.v:138002$5590 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end attribute \src "libresoc.v:138004.3-138012.6" process $proc$libresoc.v:138004$5591 assign { } { } assign { } { } assign $0\ren_delay$next[0:0]$5592 $1\ren_delay$next[0:0]$5593 attribute \src "libresoc.v:138005.5-138005.29" switch \initial attribute \src "libresoc.v:138005.9-138005.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$next[0:0]$5593 1'0 case assign $1\ren_delay$next[0:0]$5593 \dmi__ren end sync always update \ren_delay$next $0\ren_delay$next[0:0]$5592 end attribute \src "libresoc.v:138013.3-138022.6" process $proc$libresoc.v:138013$5594 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] attribute \src "libresoc.v:138014.5-138014.29" switch \initial attribute \src "libresoc.v:138014.9-138014.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch \ren_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi__data_o[63:0] \memory_r_data case assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dmi__data_o $0\dmi__data_o[63:0] end attribute \src "libresoc.v:138023.3-138031.6" process $proc$libresoc.v:138023$5595 assign { } { } assign { } { } assign $0\ren_delay$4$next[0:0]$5596 $1\ren_delay$4$next[0:0]$5597 attribute \src "libresoc.v:138024.5-138024.29" switch \initial attribute \src "libresoc.v:138024.9-138024.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$4$next[0:0]$5597 1'0 case assign $1\ren_delay$4$next[0:0]$5597 \src1__ren end sync always update \ren_delay$4$next $0\ren_delay$4$next[0:0]$5596 end attribute \src "libresoc.v:138032.3-138041.6" process $proc$libresoc.v:138032$5598 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] attribute \src "libresoc.v:138033.5-138033.29" switch \initial attribute \src "libresoc.v:138033.9-138033.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch \ren_delay$4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src1__data_o[63:0] \memory_r_data$3 case assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \src1__data_o $0\src1__data_o[63:0] end connect \memory_r_data $memrd$\memory$libresoc.v:137998$5586_DATA connect \memory_r_data$3 $memrd$\memory$libresoc.v:137999$5587_DATA connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr connect \memory_r_addr$2 \src1__addr connect \memory_r_addr \dmi__addr end attribute \src "libresoc.v:138051.1-140621.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag attribute \src "libresoc.v:140035.3-140061.6" wire $0\TAP_bus__tdo[0:0] attribute \src "libresoc.v:139683.3-139698.6" wire $0\TAP_tdo[0:0] attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $0\dmi0__addr_i$next[3:0]$6023 attribute \src "libresoc.v:139586.3-139587.41" wire width 4 $0\dmi0__addr_i[3:0] attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $0\dmi0__din$next[63:0]$6036 attribute \src "libresoc.v:139582.3-139583.35" wire width 64 $0\dmi0__din[63:0] attribute \src "libresoc.v:139885.3-139901.6" wire $0\dmi0_addrsr__oe$next[0:0]$5960 attribute \src "libresoc.v:139614.3-139615.47" wire $0\dmi0_addrsr__oe[0:0] attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5964 attribute \src "libresoc.v:139612.3-139613.47" wire width 8 $0\dmi0_addrsr_reg[7:0] attribute \src "libresoc.v:139867.3-139875.6" wire $0\dmi0_addrsr_update_core$next[0:0]$5954 attribute \src "libresoc.v:139618.3-139619.63" wire $0\dmi0_addrsr_update_core[0:0] attribute \src "libresoc.v:139876.3-139884.6" wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 attribute \src "libresoc.v:139616.3-139617.73" wire $0\dmi0_addrsr_update_core_prev[0:0] attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $0\dmi0_datasr__i$next[63:0]$6041 attribute \src "libresoc.v:139580.3-139581.45" wire width 64 $0\dmi0_datasr__i[63:0] attribute \src "libresoc.v:139941.3-139957.6" wire width 2 $0\dmi0_datasr__oe$next[1:0]$5975 attribute \src "libresoc.v:139606.3-139607.47" wire width 2 $0\dmi0_datasr__oe[1:0] attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $0\dmi0_datasr_reg$next[63:0]$5979 attribute \src "libresoc.v:139604.3-139605.47" wire width 64 $0\dmi0_datasr_reg[63:0] attribute \src "libresoc.v:139923.3-139931.6" wire $0\dmi0_datasr_update_core$next[0:0]$5969 attribute \src "libresoc.v:139610.3-139611.63" wire $0\dmi0_datasr_update_core[0:0] attribute \src "libresoc.v:139932.3-139940.6" wire $0\dmi0_datasr_update_core_prev$next[0:0]$5972 attribute \src "libresoc.v:139608.3-139609.73" wire $0\dmi0_datasr_update_core_prev[0:0] attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $0\fsm_state$455$next[2:0]$6029 attribute \src "libresoc.v:139584.3-139585.45" wire width 3 $0\fsm_state$455[2:0]$5875 attribute \src "libresoc.v:138649.13-138649.35" wire width 3 $0\fsm_state$455[2:0]$6078 attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $0\fsm_state$next[2:0]$6006 attribute \src "libresoc.v:139592.3-139593.35" wire width 3 $0\fsm_state[2:0] attribute \src "libresoc.v:138052.7-138052.20" wire $0\initial[0:0] attribute \src "libresoc.v:140419.3-140439.6" wire width 130 $0\io_bd$next[129:0]$6061 attribute \src "libresoc.v:139644.3-139645.27" wire width 130 $0\io_bd[129:0] attribute \src "libresoc.v:140401.3-140418.6" wire width 130 $0\io_sr$next[129:0]$6057 attribute \src "libresoc.v:139646.3-139647.27" wire width 130 $0\io_sr[129:0] attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $0\jtag_wb__adr$next[28:0]$6000 attribute \src "libresoc.v:139594.3-139595.41" wire width 29 $0\jtag_wb__adr[28:0] attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $0\jtag_wb__dat_w$next[63:0]$6013 attribute \src "libresoc.v:139590.3-139591.45" wire width 64 $0\jtag_wb__dat_w[63:0] attribute \src "libresoc.v:139773.3-139789.6" wire $0\jtag_wb_addrsr__oe$next[0:0]$5930 attribute \src "libresoc.v:139630.3-139631.53" wire $0\jtag_wb_addrsr__oe[0:0] attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5934 attribute \src "libresoc.v:139628.3-139629.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] attribute \src "libresoc.v:139755.3-139763.6" wire $0\jtag_wb_addrsr_update_core$next[0:0]$5924 attribute \src "libresoc.v:139634.3-139635.69" wire $0\jtag_wb_addrsr_update_core[0:0] attribute \src "libresoc.v:139764.3-139772.6" wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 attribute \src "libresoc.v:139632.3-139633.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6018 attribute \src "libresoc.v:139588.3-139589.51" wire width 64 $0\jtag_wb_datasr__i[63:0] attribute \src "libresoc.v:139829.3-139845.6" wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5945 attribute \src "libresoc.v:139622.3-139623.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5949 attribute \src "libresoc.v:139620.3-139621.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] attribute \src "libresoc.v:139811.3-139819.6" wire $0\jtag_wb_datasr_update_core$next[0:0]$5939 attribute \src "libresoc.v:139626.3-139627.69" wire $0\jtag_wb_datasr_update_core[0:0] attribute \src "libresoc.v:139820.3-139828.6" wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 attribute \src "libresoc.v:139624.3-139625.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] attribute \src "libresoc.v:139717.3-139733.6" wire $0\sr0__oe$next[0:0]$5915 attribute \src "libresoc.v:139638.3-139639.31" wire $0\sr0__oe[0:0] attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $0\sr0_reg$next[2:0]$5919 attribute \src "libresoc.v:139636.3-139637.31" wire width 3 $0\sr0_reg[2:0] attribute \src "libresoc.v:139699.3-139707.6" wire $0\sr0_update_core$next[0:0]$5909 attribute \src "libresoc.v:139642.3-139643.47" wire $0\sr0_update_core[0:0] attribute \src "libresoc.v:139708.3-139716.6" wire $0\sr0_update_core_prev$next[0:0]$5912 attribute \src "libresoc.v:139640.3-139641.57" wire $0\sr0_update_core_prev[0:0] attribute \src "libresoc.v:140391.3-140400.6" wire width 3 $0\sr5__i[2:0] attribute \src "libresoc.v:139997.3-140013.6" wire $0\sr5__oe$next[0:0]$5990 attribute \src "libresoc.v:139598.3-139599.31" wire $0\sr5__oe[0:0] attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $0\sr5_reg$next[2:0]$5994 attribute \src "libresoc.v:139596.3-139597.31" wire width 3 $0\sr5_reg[2:0] attribute \src "libresoc.v:139979.3-139987.6" wire $0\sr5_update_core$next[0:0]$5984 attribute \src "libresoc.v:139602.3-139603.47" wire $0\sr5_update_core[0:0] attribute \src "libresoc.v:139988.3-139996.6" wire $0\sr5_update_core_prev$next[0:0]$5987 attribute \src "libresoc.v:139600.3-139601.57" wire $0\sr5_update_core_prev[0:0] attribute \src "libresoc.v:140370.3-140390.6" wire $0\wb_dcache_en$next[0:0]$6046 attribute \src "libresoc.v:139576.3-139577.41" wire $0\wb_dcache_en[0:0] attribute \src "libresoc.v:140370.3-140390.6" wire $0\wb_icache_en$next[0:0]$6047 attribute \src "libresoc.v:139574.3-139575.41" wire $0\wb_icache_en[0:0] attribute \src "libresoc.v:140370.3-140390.6" wire $0\wb_sram_en$next[0:0]$6048 attribute \src "libresoc.v:139578.3-139579.37" wire $0\wb_sram_en[0:0] attribute \src "libresoc.v:140035.3-140061.6" wire $1\TAP_bus__tdo[0:0] attribute \src "libresoc.v:139683.3-139698.6" wire $1\TAP_tdo[0:0] attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $1\dmi0__addr_i$next[3:0]$6024 attribute \src "libresoc.v:138562.13-138562.32" wire width 4 $1\dmi0__addr_i[3:0] attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $1\dmi0__din$next[63:0]$6037 attribute \src "libresoc.v:138567.14-138567.46" wire width 64 $1\dmi0__din[63:0] attribute \src "libresoc.v:139885.3-139901.6" wire $1\dmi0_addrsr__oe$next[0:0]$5961 attribute \src "libresoc.v:138581.7-138581.29" wire $1\dmi0_addrsr__oe[0:0] attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5965 attribute \src "libresoc.v:138589.13-138589.36" wire width 8 $1\dmi0_addrsr_reg[7:0] attribute \src "libresoc.v:139867.3-139875.6" wire $1\dmi0_addrsr_update_core$next[0:0]$5955 attribute \src "libresoc.v:138597.7-138597.37" wire $1\dmi0_addrsr_update_core[0:0] attribute \src "libresoc.v:139876.3-139884.6" wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 attribute \src "libresoc.v:138601.7-138601.42" wire $1\dmi0_addrsr_update_core_prev[0:0] attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $1\dmi0_datasr__i$next[63:0]$6042 attribute \src "libresoc.v:138605.14-138605.51" wire width 64 $1\dmi0_datasr__i[63:0] attribute \src "libresoc.v:139941.3-139957.6" wire width 2 $1\dmi0_datasr__oe$next[1:0]$5976 attribute \src "libresoc.v:138611.13-138611.35" wire width 2 $1\dmi0_datasr__oe[1:0] attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $1\dmi0_datasr_reg$next[63:0]$5980 attribute \src "libresoc.v:138619.14-138619.52" wire width 64 $1\dmi0_datasr_reg[63:0] attribute \src "libresoc.v:139923.3-139931.6" wire $1\dmi0_datasr_update_core$next[0:0]$5970 attribute \src "libresoc.v:138627.7-138627.37" wire $1\dmi0_datasr_update_core[0:0] attribute \src "libresoc.v:139932.3-139940.6" wire $1\dmi0_datasr_update_core_prev$next[0:0]$5973 attribute \src "libresoc.v:138631.7-138631.42" wire $1\dmi0_datasr_update_core_prev[0:0] attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $1\fsm_state$455$next[2:0]$6030 attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $1\fsm_state$next[2:0]$6007 attribute \src "libresoc.v:138647.13-138647.29" wire width 3 $1\fsm_state[2:0] attribute \src "libresoc.v:140419.3-140439.6" wire width 130 $1\io_bd$next[129:0]$6062 attribute \src "libresoc.v:138847.15-138847.61" wire width 130 $1\io_bd[129:0] attribute \src "libresoc.v:140401.3-140418.6" wire width 130 $1\io_sr$next[129:0]$6058 attribute \src "libresoc.v:138859.15-138859.61" wire width 130 $1\io_sr[129:0] attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $1\jtag_wb__adr$next[28:0]$6001 attribute \src "libresoc.v:138868.14-138868.41" wire width 29 $1\jtag_wb__adr[28:0] attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $1\jtag_wb__dat_w$next[63:0]$6014 attribute \src "libresoc.v:138877.14-138877.51" wire width 64 $1\jtag_wb__dat_w[63:0] attribute \src "libresoc.v:139773.3-139789.6" wire $1\jtag_wb_addrsr__oe$next[0:0]$5931 attribute \src "libresoc.v:138891.7-138891.32" wire $1\jtag_wb_addrsr__oe[0:0] attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5935 attribute \src "libresoc.v:138899.14-138899.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] attribute \src "libresoc.v:139755.3-139763.6" wire $1\jtag_wb_addrsr_update_core$next[0:0]$5925 attribute \src "libresoc.v:138907.7-138907.40" wire $1\jtag_wb_addrsr_update_core[0:0] attribute \src "libresoc.v:139764.3-139772.6" wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 attribute \src "libresoc.v:138911.7-138911.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6019 attribute \src "libresoc.v:138915.14-138915.54" wire width 64 $1\jtag_wb_datasr__i[63:0] attribute \src "libresoc.v:139829.3-139845.6" wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5946 attribute \src "libresoc.v:138921.13-138921.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5950 attribute \src "libresoc.v:138929.14-138929.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] attribute \src "libresoc.v:139811.3-139819.6" wire $1\jtag_wb_datasr_update_core$next[0:0]$5940 attribute \src "libresoc.v:138937.7-138937.40" wire $1\jtag_wb_datasr_update_core[0:0] attribute \src "libresoc.v:139820.3-139828.6" wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 attribute \src "libresoc.v:138941.7-138941.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] attribute \src "libresoc.v:139717.3-139733.6" wire $1\sr0__oe$next[0:0]$5916 attribute \src "libresoc.v:139275.7-139275.21" wire $1\sr0__oe[0:0] attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $1\sr0_reg$next[2:0]$5920 attribute \src "libresoc.v:139283.13-139283.27" wire width 3 $1\sr0_reg[2:0] attribute \src "libresoc.v:139699.3-139707.6" wire $1\sr0_update_core$next[0:0]$5910 attribute \src "libresoc.v:139291.7-139291.29" wire $1\sr0_update_core[0:0] attribute \src "libresoc.v:139708.3-139716.6" wire $1\sr0_update_core_prev$next[0:0]$5913 attribute \src "libresoc.v:139295.7-139295.34" wire $1\sr0_update_core_prev[0:0] attribute \src "libresoc.v:140391.3-140400.6" wire width 3 $1\sr5__i[2:0] attribute \src "libresoc.v:139997.3-140013.6" wire $1\sr5__oe$next[0:0]$5991 attribute \src "libresoc.v:139305.7-139305.21" wire $1\sr5__oe[0:0] attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $1\sr5_reg$next[2:0]$5995 attribute \src "libresoc.v:139313.13-139313.27" wire width 3 $1\sr5_reg[2:0] attribute \src "libresoc.v:139979.3-139987.6" wire $1\sr5_update_core$next[0:0]$5985 attribute \src "libresoc.v:139321.7-139321.29" wire $1\sr5_update_core[0:0] attribute \src "libresoc.v:139988.3-139996.6" wire $1\sr5_update_core_prev$next[0:0]$5988 attribute \src "libresoc.v:139325.7-139325.34" wire $1\sr5_update_core_prev[0:0] attribute \src "libresoc.v:140370.3-140390.6" wire $1\wb_dcache_en$next[0:0]$6049 attribute \src "libresoc.v:139330.7-139330.26" wire $1\wb_dcache_en[0:0] attribute \src "libresoc.v:140370.3-140390.6" wire $1\wb_icache_en$next[0:0]$6050 attribute \src "libresoc.v:139335.7-139335.26" wire $1\wb_icache_en[0:0] attribute \src "libresoc.v:140370.3-140390.6" wire $1\wb_sram_en$next[0:0]$6051 attribute \src "libresoc.v:139339.7-139339.24" wire $1\wb_sram_en[0:0] attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $2\dmi0__addr_i$next[3:0]$6025 attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $2\dmi0__din$next[63:0]$6038 attribute \src "libresoc.v:139885.3-139901.6" wire $2\dmi0_addrsr__oe$next[0:0]$5962 attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5966 attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $2\dmi0_datasr__i$next[63:0]$6043 attribute \src "libresoc.v:139941.3-139957.6" wire width 2 $2\dmi0_datasr__oe$next[1:0]$5977 attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $2\dmi0_datasr_reg$next[63:0]$5981 attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $2\fsm_state$455$next[2:0]$6031 attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $2\fsm_state$next[2:0]$6008 attribute \src "libresoc.v:140419.3-140439.6" wire width 130 $2\io_bd$next[129:0]$6063 attribute \src "libresoc.v:140401.3-140418.6" wire width 130 $2\io_sr$next[129:0]$6059 attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $2\jtag_wb__adr$next[28:0]$6002 attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $2\jtag_wb__dat_w$next[63:0]$6015 attribute \src "libresoc.v:139773.3-139789.6" wire $2\jtag_wb_addrsr__oe$next[0:0]$5932 attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5936 attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6020 attribute \src "libresoc.v:139829.3-139845.6" wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5947 attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5951 attribute \src "libresoc.v:139717.3-139733.6" wire $2\sr0__oe$next[0:0]$5917 attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $2\sr0_reg$next[2:0]$5921 attribute \src "libresoc.v:139997.3-140013.6" wire $2\sr5__oe$next[0:0]$5992 attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $2\sr5_reg$next[2:0]$5996 attribute \src "libresoc.v:140370.3-140390.6" wire $2\wb_dcache_en$next[0:0]$6052 attribute \src "libresoc.v:140370.3-140390.6" wire $2\wb_icache_en$next[0:0]$6053 attribute \src "libresoc.v:140370.3-140390.6" wire $2\wb_sram_en$next[0:0]$6054 attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $3\dmi0__addr_i$next[3:0]$6026 attribute \src "libresoc.v:140314.3-140340.6" wire width 64 $3\dmi0__din$next[63:0]$6039 attribute \src "libresoc.v:139902.3-139922.6" wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5967 attribute \src "libresoc.v:140341.3-140369.6" wire width 64 $3\dmi0_datasr__i$next[63:0]$6044 attribute \src "libresoc.v:139958.3-139978.6" wire width 64 $3\dmi0_datasr_reg$next[63:0]$5982 attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $3\fsm_state$455$next[2:0]$6032 attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $3\fsm_state$next[2:0]$6009 attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $3\jtag_wb__adr$next[28:0]$6003 attribute \src "libresoc.v:140160.3-140186.6" wire width 64 $3\jtag_wb__dat_w$next[63:0]$6016 attribute \src "libresoc.v:139790.3-139810.6" wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5937 attribute \src "libresoc.v:140187.3-140215.6" wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6021 attribute \src "libresoc.v:139846.3-139866.6" wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5952 attribute \src "libresoc.v:139734.3-139754.6" wire width 3 $3\sr0_reg$next[2:0]$5922 attribute \src "libresoc.v:140014.3-140034.6" wire width 3 $3\sr5_reg$next[2:0]$5997 attribute \src "libresoc.v:140216.3-140260.6" wire width 4 $4\dmi0__addr_i$next[3:0]$6027 attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $4\fsm_state$455$next[2:0]$6033 attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $4\fsm_state$next[2:0]$6010 attribute \src "libresoc.v:140062.3-140106.6" wire width 29 $4\jtag_wb__adr$next[28:0]$6004 attribute \src "libresoc.v:140261.3-140313.6" wire width 3 $5\fsm_state$455$next[2:0]$6034 attribute \src "libresoc.v:140107.3-140159.6" wire width 3 $5\fsm_state$next[2:0]$6011 attribute \src "libresoc.v:139536.19-139536.112" wire width 30 $add$libresoc.v:139536$5830_Y attribute \src "libresoc.v:139537.19-139537.112" wire width 30 $add$libresoc.v:139537$5831_Y attribute \src "libresoc.v:139544.19-139544.112" wire width 5 $add$libresoc.v:139544$5839_Y attribute \src "libresoc.v:139545.19-139545.112" wire width 5 $add$libresoc.v:139545$5840_Y attribute \src "libresoc.v:139386.18-139386.112" wire $and$libresoc.v:139386$5680_Y attribute \src "libresoc.v:139453.18-139453.108" wire $and$libresoc.v:139453$5747_Y attribute \src "libresoc.v:139464.18-139464.110" wire $and$libresoc.v:139464$5758_Y attribute \src "libresoc.v:139466.19-139466.110" wire $and$libresoc.v:139466$5760_Y attribute \src "libresoc.v:139469.19-139469.114" wire $and$libresoc.v:139469$5763_Y attribute \src "libresoc.v:139471.19-139471.112" wire $and$libresoc.v:139471$5765_Y attribute \src "libresoc.v:139473.19-139473.113" wire $and$libresoc.v:139473$5767_Y attribute \src "libresoc.v:139476.19-139476.121" wire $and$libresoc.v:139476$5770_Y attribute \src "libresoc.v:139479.19-139479.114" wire $and$libresoc.v:139479$5773_Y attribute \src "libresoc.v:139481.19-139481.112" wire $and$libresoc.v:139481$5775_Y attribute \src "libresoc.v:139483.19-139483.113" wire $and$libresoc.v:139483$5777_Y attribute \src "libresoc.v:139485.19-139485.132" wire $and$libresoc.v:139485$5779_Y attribute \src "libresoc.v:139490.19-139490.114" wire $and$libresoc.v:139490$5784_Y attribute \src "libresoc.v:139492.19-139492.112" wire $and$libresoc.v:139492$5786_Y attribute \src "libresoc.v:139494.19-139494.113" wire $and$libresoc.v:139494$5788_Y attribute \src "libresoc.v:139496.19-139496.132" wire $and$libresoc.v:139496$5790_Y attribute \src "libresoc.v:139500.19-139500.114" wire $and$libresoc.v:139500$5794_Y attribute \src "libresoc.v:139502.19-139502.112" wire $and$libresoc.v:139502$5796_Y attribute \src "libresoc.v:139504.19-139504.113" wire $and$libresoc.v:139504$5798_Y attribute \src "libresoc.v:139506.19-139506.129" wire $and$libresoc.v:139506$5800_Y attribute \src "libresoc.v:139512.19-139512.114" wire $and$libresoc.v:139512$5806_Y attribute \src "libresoc.v:139514.19-139514.112" wire $and$libresoc.v:139514$5808_Y attribute \src "libresoc.v:139516.19-139516.113" wire $and$libresoc.v:139516$5810_Y attribute \src "libresoc.v:139518.19-139518.129" wire $and$libresoc.v:139518$5812_Y attribute \src "libresoc.v:139522.19-139522.114" wire $and$libresoc.v:139522$5816_Y attribute \src "libresoc.v:139524.19-139524.112" wire $and$libresoc.v:139524$5818_Y attribute \src "libresoc.v:139526.19-139526.113" wire $and$libresoc.v:139526$5820_Y attribute \src "libresoc.v:139528.19-139528.121" wire $and$libresoc.v:139528$5822_Y attribute \src "libresoc.v:139531.18-139531.108" wire $and$libresoc.v:139531$5825_Y attribute \src "libresoc.v:139541.18-139541.111" wire $and$libresoc.v:139541$5836_Y attribute \src "libresoc.v:139563.17-139563.106" wire $and$libresoc.v:139563$5858_Y attribute \src "libresoc.v:139342.17-139342.110" wire $eq$libresoc.v:139342$5636_Y attribute \src "libresoc.v:139353.18-139353.111" wire $eq$libresoc.v:139353$5647_Y attribute \src "libresoc.v:139364.18-139364.111" wire $eq$libresoc.v:139364$5658_Y attribute \src "libresoc.v:139397.17-139397.110" wire $eq$libresoc.v:139397$5691_Y attribute \src "libresoc.v:139398.18-139398.111" wire $eq$libresoc.v:139398$5692_Y attribute \src "libresoc.v:139409.18-139409.111" wire $eq$libresoc.v:139409$5703_Y attribute \src "libresoc.v:139431.18-139431.111" wire $eq$libresoc.v:139431$5725_Y attribute \src "libresoc.v:139460.19-139460.112" wire $eq$libresoc.v:139460$5754_Y attribute \src "libresoc.v:139461.19-139461.112" wire $eq$libresoc.v:139461$5755_Y attribute \src "libresoc.v:139463.19-139463.112" wire $eq$libresoc.v:139463$5757_Y attribute \src "libresoc.v:139467.19-139467.112" wire $eq$libresoc.v:139467$5761_Y attribute \src "libresoc.v:139475.18-139475.111" wire $eq$libresoc.v:139475$5769_Y attribute \src "libresoc.v:139477.19-139477.112" wire $eq$libresoc.v:139477$5771_Y attribute \src "libresoc.v:139486.18-139486.111" wire $eq$libresoc.v:139486$5780_Y attribute \src "libresoc.v:139487.19-139487.112" wire $eq$libresoc.v:139487$5781_Y attribute \src "libresoc.v:139488.19-139488.112" wire $eq$libresoc.v:139488$5782_Y attribute \src "libresoc.v:139498.19-139498.112" wire $eq$libresoc.v:139498$5792_Y attribute \src "libresoc.v:139507.19-139507.112" wire $eq$libresoc.v:139507$5801_Y attribute \src "libresoc.v:139508.17-139508.110" wire $eq$libresoc.v:139508$5802_Y attribute \src "libresoc.v:139509.18-139509.111" wire $eq$libresoc.v:139509$5803_Y attribute \src "libresoc.v:139510.19-139510.112" wire $eq$libresoc.v:139510$5804_Y attribute \src "libresoc.v:139519.19-139519.112" wire $eq$libresoc.v:139519$5813_Y attribute \src "libresoc.v:139529.19-139529.110" wire $eq$libresoc.v:139529$5823_Y attribute \src "libresoc.v:139532.19-139532.110" wire $eq$libresoc.v:139532$5826_Y attribute \src "libresoc.v:139533.19-139533.110" wire $eq$libresoc.v:139533$5827_Y attribute \src "libresoc.v:139535.19-139535.110" wire $eq$libresoc.v:139535$5829_Y attribute \src "libresoc.v:139539.19-139539.116" wire $eq$libresoc.v:139539$5834_Y attribute \src "libresoc.v:139540.19-139540.116" wire $eq$libresoc.v:139540$5835_Y attribute \src "libresoc.v:139543.19-139543.116" wire $eq$libresoc.v:139543$5838_Y attribute \src "libresoc.v:139546.18-139546.111" wire $eq$libresoc.v:139546$5841_Y attribute \src "libresoc.v:139547.18-139547.111" wire $eq$libresoc.v:139547$5842_Y attribute \src "libresoc.v:139538.19-139538.106" wire width 8 $extend$libresoc.v:139538$5832_Y attribute \src "libresoc.v:139468.19-139468.109" wire $ne$libresoc.v:139468$5762_Y attribute \src "libresoc.v:139470.19-139470.109" wire $ne$libresoc.v:139470$5764_Y attribute \src "libresoc.v:139472.19-139472.109" wire $ne$libresoc.v:139472$5766_Y attribute \src "libresoc.v:139478.19-139478.120" wire $ne$libresoc.v:139478$5772_Y attribute \src "libresoc.v:139480.19-139480.120" wire $ne$libresoc.v:139480$5774_Y attribute \src "libresoc.v:139482.19-139482.120" wire $ne$libresoc.v:139482$5776_Y attribute \src "libresoc.v:139489.19-139489.120" wire $ne$libresoc.v:139489$5783_Y attribute \src "libresoc.v:139491.19-139491.120" wire $ne$libresoc.v:139491$5785_Y attribute \src "libresoc.v:139493.19-139493.120" wire $ne$libresoc.v:139493$5787_Y attribute \src "libresoc.v:139499.19-139499.117" wire $ne$libresoc.v:139499$5793_Y attribute \src "libresoc.v:139501.19-139501.117" wire $ne$libresoc.v:139501$5795_Y attribute \src "libresoc.v:139503.19-139503.117" wire $ne$libresoc.v:139503$5797_Y attribute \src "libresoc.v:139511.19-139511.117" wire $ne$libresoc.v:139511$5805_Y attribute \src "libresoc.v:139513.19-139513.117" wire $ne$libresoc.v:139513$5807_Y attribute \src "libresoc.v:139515.19-139515.117" wire $ne$libresoc.v:139515$5809_Y attribute \src "libresoc.v:139521.19-139521.109" wire $ne$libresoc.v:139521$5815_Y attribute \src "libresoc.v:139523.19-139523.109" wire $ne$libresoc.v:139523$5817_Y attribute \src "libresoc.v:139525.19-139525.109" wire $ne$libresoc.v:139525$5819_Y attribute \src "libresoc.v:139474.19-139474.110" wire $not$libresoc.v:139474$5768_Y attribute \src "libresoc.v:139484.19-139484.121" wire $not$libresoc.v:139484$5778_Y attribute \src "libresoc.v:139495.19-139495.121" wire $not$libresoc.v:139495$5789_Y attribute \src "libresoc.v:139505.19-139505.118" wire $not$libresoc.v:139505$5799_Y attribute \src "libresoc.v:139517.19-139517.118" wire $not$libresoc.v:139517$5811_Y attribute \src "libresoc.v:139527.19-139527.110" wire $not$libresoc.v:139527$5821_Y attribute \src "libresoc.v:139530.19-139530.100" wire $not$libresoc.v:139530$5824_Y attribute \src "libresoc.v:139375.18-139375.104" wire $or$libresoc.v:139375$5669_Y attribute \src "libresoc.v:139420.18-139420.104" wire $or$libresoc.v:139420$5714_Y attribute \src "libresoc.v:139442.18-139442.104" wire $or$libresoc.v:139442$5736_Y attribute \src "libresoc.v:139462.19-139462.107" wire $or$libresoc.v:139462$5756_Y attribute \src "libresoc.v:139465.19-139465.107" wire $or$libresoc.v:139465$5759_Y attribute \src "libresoc.v:139497.18-139497.104" wire $or$libresoc.v:139497$5791_Y attribute \src "libresoc.v:139520.18-139520.104" wire $or$libresoc.v:139520$5814_Y attribute \src "libresoc.v:139534.19-139534.107" wire $or$libresoc.v:139534$5828_Y attribute \src "libresoc.v:139542.19-139542.107" wire $or$libresoc.v:139542$5837_Y attribute \src "libresoc.v:139552.17-139552.101" wire $or$libresoc.v:139552$5847_Y attribute \src "libresoc.v:139538.19-139538.106" wire width 8 $pos$libresoc.v:139538$5833_Y attribute \src "libresoc.v:139343.18-139343.132" wire $ternary$libresoc.v:139343$5637_Y attribute \src "libresoc.v:139344.19-139344.134" wire $ternary$libresoc.v:139344$5638_Y attribute \src "libresoc.v:139345.19-139345.134" wire $ternary$libresoc.v:139345$5639_Y attribute \src "libresoc.v:139346.19-139346.133" wire $ternary$libresoc.v:139346$5640_Y attribute \src "libresoc.v:139347.19-139347.134" wire $ternary$libresoc.v:139347$5641_Y attribute \src "libresoc.v:139348.19-139348.132" wire $ternary$libresoc.v:139348$5642_Y attribute \src "libresoc.v:139349.19-139349.132" wire $ternary$libresoc.v:139349$5643_Y attribute \src "libresoc.v:139350.19-139350.132" wire $ternary$libresoc.v:139350$5644_Y attribute \src "libresoc.v:139351.19-139351.132" wire $ternary$libresoc.v:139351$5645_Y attribute \src "libresoc.v:139352.19-139352.132" wire $ternary$libresoc.v:139352$5646_Y attribute \src "libresoc.v:139354.19-139354.132" wire $ternary$libresoc.v:139354$5648_Y attribute \src "libresoc.v:139355.19-139355.132" wire $ternary$libresoc.v:139355$5649_Y attribute \src "libresoc.v:139356.19-139356.132" wire $ternary$libresoc.v:139356$5650_Y attribute \src "libresoc.v:139357.19-139357.132" wire $ternary$libresoc.v:139357$5651_Y attribute \src "libresoc.v:139358.19-139358.132" wire $ternary$libresoc.v:139358$5652_Y attribute \src "libresoc.v:139359.19-139359.133" wire $ternary$libresoc.v:139359$5653_Y attribute \src "libresoc.v:139360.19-139360.133" wire $ternary$libresoc.v:139360$5654_Y attribute \src "libresoc.v:139361.19-139361.134" wire $ternary$libresoc.v:139361$5655_Y attribute \src "libresoc.v:139362.19-139362.132" wire $ternary$libresoc.v:139362$5656_Y attribute \src "libresoc.v:139363.19-139363.134" wire $ternary$libresoc.v:139363$5657_Y attribute \src "libresoc.v:139365.19-139365.134" wire $ternary$libresoc.v:139365$5659_Y attribute \src "libresoc.v:139366.19-139366.133" wire $ternary$libresoc.v:139366$5660_Y attribute \src "libresoc.v:139367.19-139367.133" wire $ternary$libresoc.v:139367$5661_Y attribute \src "libresoc.v:139368.19-139368.133" wire $ternary$libresoc.v:139368$5662_Y attribute \src "libresoc.v:139369.19-139369.133" wire $ternary$libresoc.v:139369$5663_Y attribute \src "libresoc.v:139370.19-139370.133" wire $ternary$libresoc.v:139370$5664_Y attribute \src "libresoc.v:139371.19-139371.133" wire $ternary$libresoc.v:139371$5665_Y attribute \src "libresoc.v:139372.19-139372.134" wire $ternary$libresoc.v:139372$5666_Y attribute \src "libresoc.v:139373.19-139373.133" wire $ternary$libresoc.v:139373$5667_Y attribute \src "libresoc.v:139374.19-139374.134" wire $ternary$libresoc.v:139374$5668_Y attribute \src "libresoc.v:139376.19-139376.134" wire $ternary$libresoc.v:139376$5670_Y attribute \src "libresoc.v:139377.19-139377.133" wire $ternary$libresoc.v:139377$5671_Y attribute \src "libresoc.v:139378.19-139378.134" wire $ternary$libresoc.v:139378$5672_Y attribute \src "libresoc.v:139379.19-139379.135" wire $ternary$libresoc.v:139379$5673_Y attribute \src "libresoc.v:139380.19-139380.134" wire $ternary$libresoc.v:139380$5674_Y attribute \src "libresoc.v:139381.19-139381.135" wire $ternary$libresoc.v:139381$5675_Y attribute \src "libresoc.v:139382.19-139382.135" wire $ternary$libresoc.v:139382$5676_Y attribute \src "libresoc.v:139383.19-139383.134" wire $ternary$libresoc.v:139383$5677_Y attribute \src "libresoc.v:139384.19-139384.135" wire $ternary$libresoc.v:139384$5678_Y attribute \src "libresoc.v:139385.19-139385.135" wire $ternary$libresoc.v:139385$5679_Y attribute \src "libresoc.v:139387.19-139387.134" wire $ternary$libresoc.v:139387$5681_Y attribute \src "libresoc.v:139388.19-139388.135" wire $ternary$libresoc.v:139388$5682_Y attribute \src "libresoc.v:139389.19-139389.135" wire $ternary$libresoc.v:139389$5683_Y attribute \src "libresoc.v:139390.19-139390.134" wire $ternary$libresoc.v:139390$5684_Y attribute \src "libresoc.v:139391.19-139391.135" wire $ternary$libresoc.v:139391$5685_Y attribute \src "libresoc.v:139392.19-139392.135" wire $ternary$libresoc.v:139392$5686_Y attribute \src "libresoc.v:139393.19-139393.134" wire $ternary$libresoc.v:139393$5687_Y attribute \src "libresoc.v:139394.19-139394.135" wire $ternary$libresoc.v:139394$5688_Y attribute \src "libresoc.v:139395.19-139395.135" wire $ternary$libresoc.v:139395$5689_Y attribute \src "libresoc.v:139396.19-139396.134" wire $ternary$libresoc.v:139396$5690_Y attribute \src "libresoc.v:139399.19-139399.135" wire $ternary$libresoc.v:139399$5693_Y attribute \src "libresoc.v:139400.19-139400.133" wire $ternary$libresoc.v:139400$5694_Y attribute \src "libresoc.v:139401.19-139401.132" wire $ternary$libresoc.v:139401$5695_Y attribute \src "libresoc.v:139402.19-139402.133" wire $ternary$libresoc.v:139402$5696_Y attribute \src "libresoc.v:139403.19-139403.133" wire $ternary$libresoc.v:139403$5697_Y attribute \src "libresoc.v:139404.19-139404.132" wire $ternary$libresoc.v:139404$5698_Y attribute \src "libresoc.v:139405.19-139405.133" wire $ternary$libresoc.v:139405$5699_Y attribute \src "libresoc.v:139406.19-139406.134" wire $ternary$libresoc.v:139406$5700_Y attribute \src "libresoc.v:139407.19-139407.133" wire $ternary$libresoc.v:139407$5701_Y attribute \src "libresoc.v:139408.19-139408.134" wire $ternary$libresoc.v:139408$5702_Y attribute \src "libresoc.v:139410.19-139410.134" wire $ternary$libresoc.v:139410$5704_Y attribute \src "libresoc.v:139411.19-139411.133" wire $ternary$libresoc.v:139411$5705_Y attribute \src "libresoc.v:139412.19-139412.134" wire $ternary$libresoc.v:139412$5706_Y attribute \src "libresoc.v:139413.19-139413.134" wire $ternary$libresoc.v:139413$5707_Y attribute \src "libresoc.v:139414.19-139414.133" wire $ternary$libresoc.v:139414$5708_Y attribute \src "libresoc.v:139415.19-139415.134" wire $ternary$libresoc.v:139415$5709_Y attribute \src "libresoc.v:139416.19-139416.134" wire $ternary$libresoc.v:139416$5710_Y attribute \src "libresoc.v:139417.19-139417.133" wire $ternary$libresoc.v:139417$5711_Y attribute \src "libresoc.v:139418.19-139418.134" wire $ternary$libresoc.v:139418$5712_Y attribute \src "libresoc.v:139419.19-139419.134" wire $ternary$libresoc.v:139419$5713_Y attribute \src "libresoc.v:139421.19-139421.133" wire $ternary$libresoc.v:139421$5715_Y attribute \src "libresoc.v:139422.19-139422.134" wire $ternary$libresoc.v:139422$5716_Y attribute \src "libresoc.v:139423.19-139423.134" wire $ternary$libresoc.v:139423$5717_Y attribute \src "libresoc.v:139424.19-139424.133" wire $ternary$libresoc.v:139424$5718_Y attribute \src "libresoc.v:139425.19-139425.134" wire $ternary$libresoc.v:139425$5719_Y attribute \src "libresoc.v:139426.19-139426.133" wire $ternary$libresoc.v:139426$5720_Y attribute \src "libresoc.v:139427.19-139427.133" wire $ternary$libresoc.v:139427$5721_Y attribute \src "libresoc.v:139428.19-139428.134" wire $ternary$libresoc.v:139428$5722_Y attribute \src "libresoc.v:139429.19-139429.134" wire $ternary$libresoc.v:139429$5723_Y attribute \src "libresoc.v:139430.19-139430.133" wire $ternary$libresoc.v:139430$5724_Y attribute \src "libresoc.v:139432.19-139432.134" wire $ternary$libresoc.v:139432$5726_Y attribute \src "libresoc.v:139433.19-139433.134" wire $ternary$libresoc.v:139433$5727_Y attribute \src "libresoc.v:139434.19-139434.133" wire $ternary$libresoc.v:139434$5728_Y attribute \src "libresoc.v:139435.19-139435.134" wire $ternary$libresoc.v:139435$5729_Y attribute \src "libresoc.v:139436.19-139436.134" wire $ternary$libresoc.v:139436$5730_Y attribute \src "libresoc.v:139437.19-139437.133" wire $ternary$libresoc.v:139437$5731_Y attribute \src "libresoc.v:139438.19-139438.134" wire $ternary$libresoc.v:139438$5732_Y attribute \src "libresoc.v:139439.19-139439.134" wire $ternary$libresoc.v:139439$5733_Y attribute \src "libresoc.v:139440.19-139440.133" wire $ternary$libresoc.v:139440$5734_Y attribute \src "libresoc.v:139441.19-139441.134" wire $ternary$libresoc.v:139441$5735_Y attribute \src "libresoc.v:139443.19-139443.134" wire $ternary$libresoc.v:139443$5737_Y attribute \src "libresoc.v:139444.19-139444.133" wire $ternary$libresoc.v:139444$5738_Y attribute \src "libresoc.v:139445.19-139445.134" wire $ternary$libresoc.v:139445$5739_Y attribute \src "libresoc.v:139446.19-139446.134" wire $ternary$libresoc.v:139446$5740_Y attribute \src "libresoc.v:139447.19-139447.133" wire $ternary$libresoc.v:139447$5741_Y attribute \src "libresoc.v:139448.19-139448.134" wire $ternary$libresoc.v:139448$5742_Y attribute \src "libresoc.v:139449.19-139449.134" wire $ternary$libresoc.v:139449$5743_Y attribute \src "libresoc.v:139450.19-139450.133" wire $ternary$libresoc.v:139450$5744_Y attribute \src "libresoc.v:139451.19-139451.134" wire $ternary$libresoc.v:139451$5745_Y attribute \src "libresoc.v:139452.19-139452.135" wire $ternary$libresoc.v:139452$5746_Y attribute \src "libresoc.v:139454.19-139454.134" wire $ternary$libresoc.v:139454$5748_Y attribute \src "libresoc.v:139455.19-139455.135" wire $ternary$libresoc.v:139455$5749_Y attribute \src "libresoc.v:139456.19-139456.134" wire $ternary$libresoc.v:139456$5750_Y attribute \src "libresoc.v:139457.19-139457.133" wire $ternary$libresoc.v:139457$5751_Y attribute \src "libresoc.v:139458.19-139458.133" wire $ternary$libresoc.v:139458$5752_Y attribute \src "libresoc.v:139459.19-139459.133" wire $ternary$libresoc.v:139459$5753_Y attribute \src "libresoc.v:139548.18-139548.132" wire $ternary$libresoc.v:139548$5843_Y attribute \src "libresoc.v:139549.18-139549.133" wire $ternary$libresoc.v:139549$5844_Y attribute \src "libresoc.v:139550.18-139550.133" wire $ternary$libresoc.v:139550$5845_Y attribute \src "libresoc.v:139551.18-139551.134" wire $ternary$libresoc.v:139551$5846_Y attribute \src "libresoc.v:139553.18-139553.131" wire $ternary$libresoc.v:139553$5848_Y attribute \src "libresoc.v:139554.18-139554.132" wire $ternary$libresoc.v:139554$5849_Y attribute \src "libresoc.v:139555.18-139555.131" wire $ternary$libresoc.v:139555$5850_Y attribute \src "libresoc.v:139556.18-139556.132" wire $ternary$libresoc.v:139556$5851_Y attribute \src "libresoc.v:139557.18-139557.132" wire $ternary$libresoc.v:139557$5852_Y attribute \src "libresoc.v:139558.18-139558.131" wire $ternary$libresoc.v:139558$5853_Y attribute \src "libresoc.v:139559.18-139559.133" wire $ternary$libresoc.v:139559$5854_Y attribute \src "libresoc.v:139560.18-139560.133" wire $ternary$libresoc.v:139560$5855_Y attribute \src "libresoc.v:139561.18-139561.132" wire $ternary$libresoc.v:139561$5856_Y attribute \src "libresoc.v:139562.18-139562.133" wire $ternary$libresoc.v:139562$5857_Y attribute \src "libresoc.v:139564.18-139564.133" wire $ternary$libresoc.v:139564$5859_Y attribute \src "libresoc.v:139565.18-139565.132" wire $ternary$libresoc.v:139565$5860_Y attribute \src "libresoc.v:139566.18-139566.133" wire $ternary$libresoc.v:139566$5861_Y attribute \src "libresoc.v:139567.18-139567.133" wire $ternary$libresoc.v:139567$5862_Y attribute \src "libresoc.v:139568.18-139568.132" wire $ternary$libresoc.v:139568$5863_Y attribute \src "libresoc.v:139569.18-139569.133" wire $ternary$libresoc.v:139569$5864_Y attribute \src "libresoc.v:139570.18-139570.133" wire $ternary$libresoc.v:139570$5865_Y attribute \src "libresoc.v:139571.18-139571.132" wire $ternary$libresoc.v:139571$5866_Y attribute \src "libresoc.v:139572.18-139572.133" wire $ternary$libresoc.v:139572$5867_Y attribute \src "libresoc.v:139573.18-139573.133" wire $ternary$libresoc.v:139573$5868_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$101 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$103 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$105 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$107 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$109 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$11 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$111 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$113 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$115 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$117 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$119 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$121 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$123 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$125 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$127 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$129 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$13 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$131 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$133 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$135 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$137 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$139 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$141 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$143 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$145 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$147 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$149 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$15 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$151 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$153 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$155 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$157 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$159 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$161 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$163 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$165 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$167 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$169 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" wire \$17 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$171 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$173 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$175 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$177 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$179 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$181 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$183 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$185 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$187 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$189 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$19 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$191 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$193 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$195 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$197 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$199 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$201 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$203 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$205 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$207 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$209 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$21 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$211 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$213 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$215 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$217 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$219 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$221 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$223 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$225 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$227 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$229 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$23 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$231 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$233 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$235 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$237 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$239 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$241 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$243 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$245 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$247 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$249 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$25 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$251 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$253 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$255 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$257 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$259 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$261 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$263 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$265 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$267 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$269 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$27 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$271 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$273 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$275 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$277 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$279 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$281 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$283 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$285 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$287 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$289 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$29 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$291 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$293 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$295 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$297 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$299 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$3 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$301 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$303 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$305 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$307 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$309 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$311 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$313 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$315 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$317 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$319 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$321 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$323 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$325 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$327 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$329 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$33 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$331 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$333 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$335 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$337 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$339 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$341 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$343 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$345 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$347 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$349 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$35 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$351 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$353 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$355 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$357 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$359 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$361 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$363 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$365 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$367 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$369 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$37 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$371 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$373 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$375 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$377 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$379 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$381 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$383 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$385 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$387 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$389 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$391 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$393 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$395 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$397 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$399 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$401 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$403 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$405 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$407 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$409 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$411 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$413 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$415 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$417 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$419 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$421 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$423 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$425 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$427 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$429 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$43 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$431 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$433 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" wire \$435 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" wire \$436 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" wire \$439 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" wire \$441 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" wire \$443 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" wire \$445 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" wire width 30 \$447 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" wire width 30 \$448 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" wire \$45 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" wire width 30 \$450 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" wire width 30 \$451 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 8 \$453 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" wire \$456 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" wire \$458 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" wire \$460 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" wire \$462 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" wire width 5 \$464 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" wire width 5 \$465 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" wire width 5 \$467 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" wire width 5 \$468 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" wire \$47 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" wire \$49 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$5 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$51 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$53 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$55 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$57 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$59 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$61 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$63 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$65 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$67 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$69 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$7 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$71 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$73 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$75 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$77 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$79 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$81 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$83 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$85 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$87 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$89 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" wire \$9 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$91 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$93 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$95 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$97 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 280 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 140 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire output 271 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 281 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire \_fsm_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" wire \_fsm_isdr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire \_fsm_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire \_fsm_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire \_fsm_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" wire \_idblock_TAP_id_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" wire \_idblock_id_bypass attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" wire \_idblock_select_id attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 282 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire input 5 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 4 output 1 \dmi0__addr_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 4 \dmi0__addr_i$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 output 4 \dmi0__din attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 \dmi0__din$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 input 6 \dmi0__dout attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire output 2 \dmi0__req_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire output 3 \dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire width 8 \dmi0_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire width 8 \dmi0_addrsr__o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire \dmi0_addrsr__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire \dmi0_addrsr__oe$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \dmi0_addrsr_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \dmi0_addrsr_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 8 \dmi0_addrsr_reg attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 8 \dmi0_addrsr_reg$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \dmi0_addrsr_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \dmi0_addrsr_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_addrsr_update_core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_addrsr_update_core$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_addrsr_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_addrsr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 64 \dmi0_datasr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 64 \dmi0_datasr__i$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 64 \dmi0_datasr__o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 2 \dmi0_datasr__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 2 \dmi0_datasr__oe$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \dmi0_datasr_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire width 2 \dmi0_datasr_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \dmi0_datasr_reg attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \dmi0_datasr_reg$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \dmi0_datasr_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \dmi0_datasr_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_datasr_update_core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_datasr_update_core$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 268 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 137 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 269 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 138 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 270 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 139 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" wire width 3 \fsm_state$455 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" wire width 3 \fsm_state$455$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 222 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 93 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 91 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 223 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 224 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 225 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 95 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 96 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 94 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 226 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 227 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 228 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 98 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 99 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 97 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 229 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 230 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 231 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 101 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 102 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 100 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 232 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 233 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 234 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 104 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 105 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 103 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 235 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 236 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 237 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 107 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 108 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 106 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 238 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 239 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 216 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 85 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 217 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 218 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 219 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 89 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 90 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 88 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 220 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 221 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 240 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 110 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 111 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 109 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 241 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 242 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 243 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 113 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 114 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 112 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 244 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 245 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 246 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 116 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 117 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 115 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 247 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 248 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 249 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 119 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 120 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 118 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 250 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 251 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 252 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 122 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 123 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 253 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 254 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 255 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 125 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 126 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 124 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 256 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 257 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 258 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 128 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 129 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 127 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 259 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 260 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 261 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 131 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 132 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 130 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 262 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 263 \gpio_s7__pad__oe attribute \src "libresoc.v:138052.7-138052.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" wire width 130 \io_bd attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" wire width 130 \io_bd$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" wire \io_bd2core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" wire \io_bd2io attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" wire \io_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" wire \io_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" wire width 130 \io_sr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" wire width 130 \io_sr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 278 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 output 272 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 274 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 input 279 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 output 277 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 273 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 275 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 276 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire \jtag_wb_addrsr__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire \jtag_wb_addrsr__oe$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \jtag_wb_addrsr_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \jtag_wb_addrsr_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 29 \jtag_wb_addrsr_reg attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 29 \jtag_wb_addrsr_reg$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \jtag_wb_addrsr_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \jtag_wb_addrsr_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_addrsr_update_core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_addrsr_update_core$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_addrsr_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_addrsr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 64 \jtag_wb_datasr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 64 \jtag_wb_datasr__i$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 64 \jtag_wb_datasr__o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 2 \jtag_wb_datasr__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 2 \jtag_wb_datasr__oe$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \jtag_wb_datasr_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire width 2 \jtag_wb_datasr_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \jtag_wb_datasr_reg attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \jtag_wb_datasr_reg$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \jtag_wb_datasr_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \jtag_wb_datasr_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_datasr_update_core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_datasr_update_core$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 10 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 141 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 11 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 142 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 144 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 13 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 12 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 143 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 136 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 267 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 134 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 135 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 133 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 265 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 266 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 7 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 170 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 188 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 58 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 189 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 59 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 190 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 40 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 171 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 41 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 172 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 173 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 174 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 44 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 175 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 176 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 46 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 177 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 47 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 178 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 179 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 180 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 50 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 181 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 185 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 52 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 183 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 182 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 56 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 187 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 14 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 145 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 191 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 146 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 16 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 17 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 15 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 147 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 148 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 198 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 68 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 199 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 200 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 201 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 71 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 72 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 202 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 203 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 204 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 74 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 205 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 206 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 207 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 78 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 208 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 209 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 210 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 80 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 81 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 79 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 211 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 212 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 213 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 83 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 84 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 82 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 214 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 215 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 149 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 19 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 20 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 18 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 150 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 151 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 152 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 22 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 23 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 21 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 153 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 154 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 155 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 25 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 156 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 157 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 158 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 28 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 29 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 159 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 160 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 161 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 32 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 162 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 163 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 164 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 34 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 35 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 165 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 166 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 167 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 38 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 168 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 169 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 192 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 62 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 193 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 194 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 195 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 65 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 196 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 197 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 53 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 184 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 186 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire \sr0__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire \sr0__oe$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \sr0_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \sr0_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr0_reg attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr0_reg$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \sr0_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \sr0_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \sr0_update_core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \sr0_update_core$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr0_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr0_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire width 3 \sr5__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire \sr5__ie attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire width 3 \sr5__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire \sr5__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" wire \sr5__oe$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \sr5_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \sr5_isir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr5_reg attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr5_reg$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \sr5_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \sr5_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \sr5_update_core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \sr5_update_core$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr5_update_core_prev attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr5_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire output 8 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \wb_dcache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire output 9 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \wb_icache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" cell $add $add$libresoc.v:139536$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 connect \Y $add$libresoc.v:139536$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" cell $add $add$libresoc.v:139537$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 connect \Y $add$libresoc.v:139537$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" cell $add $add$libresoc.v:139544$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 connect \Y $add$libresoc.v:139544$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" cell $add $add$libresoc.v:139545$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 connect \Y $add$libresoc.v:139545$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" cell $and $and$libresoc.v:139386$5680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture connect \Y $and$libresoc.v:139386$5680_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" cell $and $and$libresoc.v:139453$5747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 connect \Y $and$libresoc.v:139453$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" cell $and $and$libresoc.v:139464$5758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift connect \Y $and$libresoc.v:139464$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" cell $and $and$libresoc.v:139466$5760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$319 connect \Y $and$libresoc.v:139466$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $and $and$libresoc.v:139469$5763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$325 connect \B \_fsm_capture connect \Y $and$libresoc.v:139469$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $and $and$libresoc.v:139471$5765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$329 connect \B \_fsm_shift connect \Y $and$libresoc.v:139471$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $and $and$libresoc.v:139473$5767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$333 connect \B \_fsm_update connect \Y $and$libresoc.v:139473$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $and $and$libresoc.v:139476$5770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev connect \B \$337 connect \Y $and$libresoc.v:139476$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $and $and$libresoc.v:139479$5773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$343 connect \B \_fsm_capture connect \Y $and$libresoc.v:139479$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $and $and$libresoc.v:139481$5775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$347 connect \B \_fsm_shift connect \Y $and$libresoc.v:139481$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $and $and$libresoc.v:139483$5777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$351 connect \B \_fsm_update connect \Y $and$libresoc.v:139483$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $and $and$libresoc.v:139485$5779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev connect \B \$355 connect \Y $and$libresoc.v:139485$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $and $and$libresoc.v:139490$5784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$363 connect \B \_fsm_capture connect \Y $and$libresoc.v:139490$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $and $and$libresoc.v:139492$5786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$367 connect \B \_fsm_shift connect \Y $and$libresoc.v:139492$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $and $and$libresoc.v:139494$5788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$371 connect \B \_fsm_update connect \Y $and$libresoc.v:139494$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $and $and$libresoc.v:139496$5790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev connect \B \$375 connect \Y $and$libresoc.v:139496$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $and $and$libresoc.v:139500$5794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$381 connect \B \_fsm_capture connect \Y $and$libresoc.v:139500$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $and $and$libresoc.v:139502$5796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$385 connect \B \_fsm_shift connect \Y $and$libresoc.v:139502$5796_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $and $and$libresoc.v:139504$5798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$389 connect \B \_fsm_update connect \Y $and$libresoc.v:139504$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $and $and$libresoc.v:139506$5800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev connect \B \$393 connect \Y $and$libresoc.v:139506$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $and $and$libresoc.v:139512$5806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$401 connect \B \_fsm_capture connect \Y $and$libresoc.v:139512$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $and $and$libresoc.v:139514$5808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$405 connect \B \_fsm_shift connect \Y $and$libresoc.v:139514$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $and $and$libresoc.v:139516$5810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$409 connect \B \_fsm_update connect \Y $and$libresoc.v:139516$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $and $and$libresoc.v:139518$5812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev connect \B \$413 connect \Y $and$libresoc.v:139518$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $and $and$libresoc.v:139522$5816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$419 connect \B \_fsm_capture connect \Y $and$libresoc.v:139522$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $and $and$libresoc.v:139524$5818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$423 connect \B \_fsm_shift connect \Y $and$libresoc.v:139524$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $and $and$libresoc.v:139526$5820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$427 connect \B \_fsm_update connect \Y $and$libresoc.v:139526$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $and $and$libresoc.v:139528$5822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev connect \B \$431 connect \Y $and$libresoc.v:139528$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" cell $and $and$libresoc.v:139531$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$41 connect \Y $and$libresoc.v:139531$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" cell $and $and$libresoc.v:139541$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$43 connect \B \_fsm_update connect \Y $and$libresoc.v:139541$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $and $and$libresoc.v:139563$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 connect \Y $and$libresoc.v:139563$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" cell $eq $eq$libresoc.v:139342$5636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 connect \Y $eq$libresoc.v:139342$5636_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139353$5647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 connect \Y $eq$libresoc.v:139353$5647_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139364$5658 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 connect \Y $eq$libresoc.v:139364$5658_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $eq $eq$libresoc.v:139397$5691 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 connect \Y $eq$libresoc.v:139397$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139398$5692 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 connect \Y $eq$libresoc.v:139398$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139409$5703 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 connect \Y $eq$libresoc.v:139409$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" cell $eq $eq$libresoc.v:139431$5725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 connect \Y $eq$libresoc.v:139431$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139460$5754 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 connect \Y $eq$libresoc.v:139460$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139461$5755 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 connect \Y $eq$libresoc.v:139461$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" cell $eq $eq$libresoc.v:139463$5757 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 connect \Y $eq$libresoc.v:139463$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139467$5761 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 connect \Y $eq$libresoc.v:139467$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139475$5769 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 connect \Y $eq$libresoc.v:139475$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139477$5771 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 connect \Y $eq$libresoc.v:139477$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $eq $eq$libresoc.v:139486$5780 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 connect \Y $eq$libresoc.v:139486$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139487$5781 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 connect \Y $eq$libresoc.v:139487$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139488$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 connect \Y $eq$libresoc.v:139488$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139498$5792 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 connect \Y $eq$libresoc.v:139498$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139507$5801 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 connect \Y $eq$libresoc.v:139507$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $eq $eq$libresoc.v:139508$5802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 connect \Y $eq$libresoc.v:139508$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" cell $eq $eq$libresoc.v:139509$5803 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 connect \Y $eq$libresoc.v:139509$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139510$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 connect \Y $eq$libresoc.v:139510$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" cell $eq $eq$libresoc.v:139519$5813 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1011 connect \Y $eq$libresoc.v:139519$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" cell $eq $eq$libresoc.v:139529$5823 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 connect \Y $eq$libresoc.v:139529$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" cell $eq $eq$libresoc.v:139532$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 connect \Y $eq$libresoc.v:139532$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" cell $eq $eq$libresoc.v:139533$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 connect \Y $eq$libresoc.v:139533$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" cell $eq $eq$libresoc.v:139535$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 connect \Y $eq$libresoc.v:139535$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" cell $eq $eq$libresoc.v:139539$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fsm_state$455 connect \B 1'1 connect \Y $eq$libresoc.v:139539$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" cell $eq $eq$libresoc.v:139540$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \fsm_state$455 connect \B 2'10 connect \Y $eq$libresoc.v:139540$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" cell $eq $eq$libresoc.v:139543$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \fsm_state$455 connect \B 2'10 connect \Y $eq$libresoc.v:139543$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" cell $eq $eq$libresoc.v:139546$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 connect \Y $eq$libresoc.v:139546$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" cell $eq $eq$libresoc.v:139547$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 connect \Y $eq$libresoc.v:139547$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" cell $pos $extend$libresoc.v:139538$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i connect \Y $extend$libresoc.v:139538$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $ne $ne$libresoc.v:139468$5762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 connect \Y $ne$libresoc.v:139468$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $ne $ne$libresoc.v:139470$5764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 connect \Y $ne$libresoc.v:139470$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $ne $ne$libresoc.v:139472$5766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 connect \Y $ne$libresoc.v:139472$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $ne $ne$libresoc.v:139478$5772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139478$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $ne $ne$libresoc.v:139480$5774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139480$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $ne $ne$libresoc.v:139482$5776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139482$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $ne $ne$libresoc.v:139489$5783 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139489$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $ne $ne$libresoc.v:139491$5785 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139491$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $ne $ne$libresoc.v:139493$5787 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139493$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $ne $ne$libresoc.v:139499$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139499$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $ne $ne$libresoc.v:139501$5795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139501$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $ne $ne$libresoc.v:139503$5797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139503$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $ne $ne$libresoc.v:139511$5805 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139511$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $ne $ne$libresoc.v:139513$5807 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139513$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $ne $ne$libresoc.v:139515$5809 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 connect \Y $ne$libresoc.v:139515$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" cell $ne $ne$libresoc.v:139521$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 connect \Y $ne$libresoc.v:139521$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" cell $ne $ne$libresoc.v:139523$5817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 connect \Y $ne$libresoc.v:139523$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" cell $ne $ne$libresoc.v:139525$5819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 connect \Y $ne$libresoc.v:139525$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $not $not$libresoc.v:139474$5768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core connect \Y $not$libresoc.v:139474$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $not $not$libresoc.v:139484$5778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core connect \Y $not$libresoc.v:139484$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $not $not$libresoc.v:139495$5789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core connect \Y $not$libresoc.v:139495$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $not $not$libresoc.v:139505$5799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core connect \Y $not$libresoc.v:139505$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $not $not$libresoc.v:139517$5811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core connect \Y $not$libresoc.v:139517$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" cell $not $not$libresoc.v:139527$5821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core connect \Y $not$libresoc.v:139527$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" cell $not $not$libresoc.v:139530$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$436 connect \Y $not$libresoc.v:139530$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $or $or$libresoc.v:139375$5669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 connect \Y $or$libresoc.v:139375$5669_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $or $or$libresoc.v:139420$5714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 connect \Y $or$libresoc.v:139420$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" cell $or $or$libresoc.v:139442$5736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 connect \Y $or$libresoc.v:139442$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $or $or$libresoc.v:139462$5756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$311 connect \B \$313 connect \Y $or$libresoc.v:139462$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" cell $or $or$libresoc.v:139465$5759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$315 connect \B \$317 connect \Y $or$libresoc.v:139465$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" cell $or $or$libresoc.v:139497$5791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 connect \Y $or$libresoc.v:139497$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" cell $or $or$libresoc.v:139520$5814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 connect \Y $or$libresoc.v:139520$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" cell $or $or$libresoc.v:139534$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$439 connect \B \$441 connect \Y $or$libresoc.v:139534$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" cell $or $or$libresoc.v:139542$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$456 connect \B \$458 connect \Y $or$libresoc.v:139542$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" cell $or $or$libresoc.v:139552$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 connect \Y $or$libresoc.v:139552$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" cell $pos $pos$libresoc.v:139538$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:139538$5832_Y connect \Y $pos$libresoc.v:139538$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139343$5637 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o connect \B \io_bd [24] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139343$5637_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139344$5638 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe connect \B \io_bd [25] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139344$5638_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139345$5639 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i connect \B \io_bd [26] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139345$5639_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139346$5640 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o connect \B \io_bd [27] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139346$5640_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139347$5641 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe connect \B \io_bd [28] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139347$5641_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139348$5642 parameter \WIDTH 1 connect \A \sdr_a_0__core__o connect \B \io_bd [29] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139348$5642_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139349$5643 parameter \WIDTH 1 connect \A \sdr_a_1__core__o connect \B \io_bd [30] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139349$5643_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139350$5644 parameter \WIDTH 1 connect \A \sdr_a_2__core__o connect \B \io_bd [31] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139350$5644_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139351$5645 parameter \WIDTH 1 connect \A \sdr_a_3__core__o connect \B \io_bd [32] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139351$5645_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139352$5646 parameter \WIDTH 1 connect \A \sdr_a_4__core__o connect \B \io_bd [33] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139352$5646_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139354$5648 parameter \WIDTH 1 connect \A \sdr_a_5__core__o connect \B \io_bd [34] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139354$5648_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139355$5649 parameter \WIDTH 1 connect \A \sdr_a_6__core__o connect \B \io_bd [35] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139355$5649_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139356$5650 parameter \WIDTH 1 connect \A \sdr_a_7__core__o connect \B \io_bd [36] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139356$5650_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139357$5651 parameter \WIDTH 1 connect \A \sdr_a_8__core__o connect \B \io_bd [37] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139357$5651_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139358$5652 parameter \WIDTH 1 connect \A \sdr_a_9__core__o connect \B \io_bd [38] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139358$5652_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139359$5653 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o connect \B \io_bd [39] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139359$5653_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139360$5654 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o connect \B \io_bd [40] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139360$5654_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139361$5655 parameter \WIDTH 1 connect \A \sdr_clock__core__o connect \B \io_bd [41] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139361$5655_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139362$5656 parameter \WIDTH 1 connect \A \sdr_cke__core__o connect \B \io_bd [42] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139362$5656_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139363$5657 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o connect \B \io_bd [43] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139363$5657_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139365$5659 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o connect \B \io_bd [44] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139365$5659_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139366$5660 parameter \WIDTH 1 connect \A \sdr_we_n__core__o connect \B \io_bd [45] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139366$5660_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139367$5661 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o connect \B \io_bd [46] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139367$5661_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139368$5662 parameter \WIDTH 1 connect \A \sdr_a_10__core__o connect \B \io_bd [47] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139368$5662_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139369$5663 parameter \WIDTH 1 connect \A \sdr_a_11__core__o connect \B \io_bd [48] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139369$5663_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139370$5664 parameter \WIDTH 1 connect \A \sdr_a_12__core__o connect \B \io_bd [49] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139370$5664_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139371$5665 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o connect \B \io_bd [50] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139371$5665_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139372$5666 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i connect \B \io_bd [51] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139372$5666_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139373$5667 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o connect \B \io_bd [52] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139373$5667_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139374$5668 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe connect \B \io_bd [53] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139374$5668_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139376$5670 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i connect \B \io_bd [54] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139376$5670_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139377$5671 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o connect \B \io_bd [55] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139377$5671_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139378$5672 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe connect \B \io_bd [56] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139378$5672_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139379$5673 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i connect \B \io_bd [57] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139379$5673_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139380$5674 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o connect \B \io_bd [58] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139380$5674_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139381$5675 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe connect \B \io_bd [59] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139381$5675_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139382$5676 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i connect \B \io_bd [60] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139382$5676_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139383$5677 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o connect \B \io_bd [61] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139383$5677_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139384$5678 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe connect \B \io_bd [62] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139384$5678_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139385$5679 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i connect \B \io_bd [63] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139385$5679_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139387$5681 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o connect \B \io_bd [64] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139387$5681_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139388$5682 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe connect \B \io_bd [65] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139388$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139389$5683 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i connect \B \io_bd [66] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139389$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139390$5684 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o connect \B \io_bd [67] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139390$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139391$5685 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe connect \B \io_bd [68] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139391$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139392$5686 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i connect \B \io_bd [69] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139392$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139393$5687 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o connect \B \io_bd [70] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139393$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139394$5688 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe connect \B \io_bd [71] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139394$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139395$5689 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i connect \B \io_bd [72] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139395$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139396$5690 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o connect \B \io_bd [73] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139396$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139399$5693 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe connect \B \io_bd [74] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139399$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139400$5694 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [75] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139400$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139401$5695 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [76] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139401$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139402$5696 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [77] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139402$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139403$5697 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [78] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139403$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139404$5698 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [79] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139404$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139405$5699 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [80] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139405$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139406$5700 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [81] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139406$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139407$5701 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [82] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139407$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139408$5702 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [83] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139408$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139410$5704 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [84] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139410$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139411$5705 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [85] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139411$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139412$5706 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [86] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139412$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139413$5707 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [87] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139413$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139414$5708 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [88] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139414$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139415$5709 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [89] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139415$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139416$5710 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [90] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139416$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139417$5711 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [91] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139417$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139418$5712 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [92] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139418$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139419$5713 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [93] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139419$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139421$5715 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [94] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139421$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139422$5716 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [95] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139422$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139423$5717 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [96] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139423$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139424$5718 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [97] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139424$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139425$5719 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [98] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139425$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139426$5720 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [99] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139426$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139427$5721 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [100] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139427$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139428$5722 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [101] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139428$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139429$5723 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [102] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139429$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139430$5724 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [103] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139430$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139432$5726 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [104] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139432$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139433$5727 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [105] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139433$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139434$5728 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [106] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139434$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139435$5729 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [107] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139435$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139436$5730 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [108] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139436$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139437$5731 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [109] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139437$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139438$5732 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [110] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139438$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139439$5733 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [111] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139439$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139440$5734 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [112] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139440$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139441$5735 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [113] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139441$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139443$5737 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [114] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139443$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139444$5738 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [115] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139444$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139445$5739 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [116] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139445$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139446$5740 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [117] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139446$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139447$5741 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [118] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139447$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139448$5742 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [119] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139448$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139449$5743 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [120] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139449$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139450$5744 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [121] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139450$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139451$5745 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [122] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139451$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139452$5746 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i connect \B \io_bd [123] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139452$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139454$5748 parameter \WIDTH 1 connect \A \mtwi_sda__core__o connect \B \io_bd [124] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139454$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139455$5749 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe connect \B \io_bd [125] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139455$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139456$5750 parameter \WIDTH 1 connect \A \mtwi_scl__core__o connect \B \io_bd [126] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139456$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" cell $mux $ternary$libresoc.v:139457$5751 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [127] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139457$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" cell $mux $ternary$libresoc.v:139458$5752 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [128] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139458$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" cell $mux $ternary$libresoc.v:139459$5753 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [129] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139459$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139548$5843 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [0] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139548$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139549$5844 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [1] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139549$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139550$5845 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [2] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139550$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" cell $mux $ternary$libresoc.v:139551$5846 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [3] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139551$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" cell $mux $ternary$libresoc.v:139553$5848 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o connect \B \io_bd [4] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139553$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139554$5849 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i connect \B \io_bd [5] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139554$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139555$5850 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o connect \B \io_bd [6] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139555$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139556$5851 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe connect \B \io_bd [7] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139556$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139557$5852 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i connect \B \io_bd [8] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139557$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139558$5853 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o connect \B \io_bd [9] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139558$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139559$5854 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe connect \B \io_bd [10] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139559$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139560$5855 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i connect \B \io_bd [11] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139560$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139561$5856 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o connect \B \io_bd [12] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139561$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139562$5857 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe connect \B \io_bd [13] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139562$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139564$5859 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i connect \B \io_bd [14] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139564$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139565$5860 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o connect \B \io_bd [15] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139565$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139566$5861 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe connect \B \io_bd [16] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139566$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139567$5862 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i connect \B \io_bd [17] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139567$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139568$5863 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o connect \B \io_bd [18] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139568$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139569$5864 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe connect \B \io_bd [19] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139569$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139570$5865 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i connect \B \io_bd [20] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139570$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" cell $mux $ternary$libresoc.v:139571$5866 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o connect \B \io_bd [21] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139571$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" cell $mux $ternary$libresoc.v:139572$5867 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe connect \B \io_bd [22] connect \S \io_bd2io connect \Y $ternary$libresoc.v:139572$5867_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" cell $mux $ternary$libresoc.v:139573$5868 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i connect \B \io_bd [23] connect \S \io_bd2core connect \Y $ternary$libresoc.v:139573$5868_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:139648.8-139660.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms connect \capture \_fsm_capture connect \isdr \_fsm_isdr connect \isir \_fsm_isir connect \negjtag_clk \negjtag_clk connect \negjtag_rst \negjtag_rst connect \posjtag_clk \posjtag_clk connect \posjtag_rst \posjtag_rst connect \shift \_fsm_shift connect \update \_fsm_update end attribute \module_not_derived 1 attribute \src "libresoc.v:139661.12-139671.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo connect \capture \_fsm_capture connect \id_bypass \_idblock_id_bypass connect \posjtag_clk \posjtag_clk connect \posjtag_rst \posjtag_rst connect \select_id \_idblock_select_id connect \shift \_fsm_shift connect \update \_fsm_update end attribute \module_not_derived 1 attribute \src "libresoc.v:139672.12-139682.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture connect \ir \_irblock_ir connect \isir \_fsm_isir connect \posjtag_clk \posjtag_clk connect \posjtag_rst \posjtag_rst connect \shift \_fsm_shift connect \tdo \_irblock_tdo connect \update \_fsm_update end attribute \src "libresoc.v:138052.7-138052.20" process $proc$libresoc.v:138052$6064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:138562.13-138562.32" process $proc$libresoc.v:138562$6065 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end attribute \src "libresoc.v:138567.14-138567.46" process $proc$libresoc.v:138567$6066 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end attribute \src "libresoc.v:138581.7-138581.29" process $proc$libresoc.v:138581$6067 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end attribute \src "libresoc.v:138589.13-138589.36" process $proc$libresoc.v:138589$6068 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end attribute \src "libresoc.v:138597.7-138597.37" process $proc$libresoc.v:138597$6069 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end attribute \src "libresoc.v:138601.7-138601.42" process $proc$libresoc.v:138601$6070 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end attribute \src "libresoc.v:138605.14-138605.51" process $proc$libresoc.v:138605$6071 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end attribute \src "libresoc.v:138611.13-138611.35" process $proc$libresoc.v:138611$6072 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end attribute \src "libresoc.v:138619.14-138619.52" process $proc$libresoc.v:138619$6073 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end attribute \src "libresoc.v:138627.7-138627.37" process $proc$libresoc.v:138627$6074 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end attribute \src "libresoc.v:138631.7-138631.42" process $proc$libresoc.v:138631$6075 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end attribute \src "libresoc.v:138647.13-138647.29" process $proc$libresoc.v:138647$6076 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end attribute \src "libresoc.v:138649.13-138649.35" process $proc$libresoc.v:138649$6077 assign { } { } assign $0\fsm_state$455[2:0]$6078 3'000 sync always sync init update \fsm_state$455 $0\fsm_state$455[2:0]$6078 end attribute \src "libresoc.v:138847.15-138847.61" process $proc$libresoc.v:138847$6079 assign { } { } assign $1\io_bd[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_bd $1\io_bd[129:0] end attribute \src "libresoc.v:138859.15-138859.61" process $proc$libresoc.v:138859$6080 assign { } { } assign $1\io_sr[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \io_sr $1\io_sr[129:0] end attribute \src "libresoc.v:138868.14-138868.41" process $proc$libresoc.v:138868$6081 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end attribute \src "libresoc.v:138877.14-138877.51" process $proc$libresoc.v:138877$6082 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end attribute \src "libresoc.v:138891.7-138891.32" process $proc$libresoc.v:138891$6083 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end attribute \src "libresoc.v:138899.14-138899.47" process $proc$libresoc.v:138899$6084 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end attribute \src "libresoc.v:138907.7-138907.40" process $proc$libresoc.v:138907$6085 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end attribute \src "libresoc.v:138911.7-138911.45" process $proc$libresoc.v:138911$6086 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end attribute \src "libresoc.v:138915.14-138915.54" process $proc$libresoc.v:138915$6087 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end attribute \src "libresoc.v:138921.13-138921.38" process $proc$libresoc.v:138921$6088 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end attribute \src "libresoc.v:138929.14-138929.55" process $proc$libresoc.v:138929$6089 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end attribute \src "libresoc.v:138937.7-138937.40" process $proc$libresoc.v:138937$6090 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end attribute \src "libresoc.v:138941.7-138941.45" process $proc$libresoc.v:138941$6091 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end attribute \src "libresoc.v:139275.7-139275.21" process $proc$libresoc.v:139275$6092 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end attribute \src "libresoc.v:139283.13-139283.27" process $proc$libresoc.v:139283$6093 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end attribute \src "libresoc.v:139291.7-139291.29" process $proc$libresoc.v:139291$6094 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end attribute \src "libresoc.v:139295.7-139295.34" process $proc$libresoc.v:139295$6095 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end attribute \src "libresoc.v:139305.7-139305.21" process $proc$libresoc.v:139305$6096 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end attribute \src "libresoc.v:139313.13-139313.27" process $proc$libresoc.v:139313$6097 assign { } { } assign $1\sr5_reg[2:0] 3'000 sync always sync init update \sr5_reg $1\sr5_reg[2:0] end attribute \src "libresoc.v:139321.7-139321.29" process $proc$libresoc.v:139321$6098 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end attribute \src "libresoc.v:139325.7-139325.34" process $proc$libresoc.v:139325$6099 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end attribute \src "libresoc.v:139330.7-139330.26" process $proc$libresoc.v:139330$6100 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end attribute \src "libresoc.v:139335.7-139335.26" process $proc$libresoc.v:139335$6101 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end attribute \src "libresoc.v:139339.7-139339.24" process $proc$libresoc.v:139339$6102 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end attribute \src "libresoc.v:139574.3-139575.41" process $proc$libresoc.v:139574$5869 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end attribute \src "libresoc.v:139576.3-139577.41" process $proc$libresoc.v:139576$5870 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end attribute \src "libresoc.v:139578.3-139579.37" process $proc$libresoc.v:139578$5871 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end attribute \src "libresoc.v:139580.3-139581.45" process $proc$libresoc.v:139580$5872 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end attribute \src "libresoc.v:139582.3-139583.35" process $proc$libresoc.v:139582$5873 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end attribute \src "libresoc.v:139584.3-139585.45" process $proc$libresoc.v:139584$5874 assign { } { } assign $0\fsm_state$455[2:0]$5875 \fsm_state$455$next sync posedge \clk update \fsm_state$455 $0\fsm_state$455[2:0]$5875 end attribute \src "libresoc.v:139586.3-139587.41" process $proc$libresoc.v:139586$5876 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end attribute \src "libresoc.v:139588.3-139589.51" process $proc$libresoc.v:139588$5877 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end attribute \src "libresoc.v:139590.3-139591.45" process $proc$libresoc.v:139590$5878 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end attribute \src "libresoc.v:139592.3-139593.35" process $proc$libresoc.v:139592$5879 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end attribute \src "libresoc.v:139594.3-139595.41" process $proc$libresoc.v:139594$5880 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end attribute \src "libresoc.v:139596.3-139597.31" process $proc$libresoc.v:139596$5881 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end attribute \src "libresoc.v:139598.3-139599.31" process $proc$libresoc.v:139598$5882 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end attribute \src "libresoc.v:139600.3-139601.57" process $proc$libresoc.v:139600$5883 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end attribute \src "libresoc.v:139602.3-139603.47" process $proc$libresoc.v:139602$5884 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end attribute \src "libresoc.v:139604.3-139605.47" process $proc$libresoc.v:139604$5885 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end attribute \src "libresoc.v:139606.3-139607.47" process $proc$libresoc.v:139606$5886 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end attribute \src "libresoc.v:139608.3-139609.73" process $proc$libresoc.v:139608$5887 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end attribute \src "libresoc.v:139610.3-139611.63" process $proc$libresoc.v:139610$5888 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end attribute \src "libresoc.v:139612.3-139613.47" process $proc$libresoc.v:139612$5889 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end attribute \src "libresoc.v:139614.3-139615.47" process $proc$libresoc.v:139614$5890 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end attribute \src "libresoc.v:139616.3-139617.73" process $proc$libresoc.v:139616$5891 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end attribute \src "libresoc.v:139618.3-139619.63" process $proc$libresoc.v:139618$5892 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end attribute \src "libresoc.v:139620.3-139621.53" process $proc$libresoc.v:139620$5893 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end attribute \src "libresoc.v:139622.3-139623.53" process $proc$libresoc.v:139622$5894 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end attribute \src "libresoc.v:139624.3-139625.79" process $proc$libresoc.v:139624$5895 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end attribute \src "libresoc.v:139626.3-139627.69" process $proc$libresoc.v:139626$5896 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end attribute \src "libresoc.v:139628.3-139629.53" process $proc$libresoc.v:139628$5897 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end attribute \src "libresoc.v:139630.3-139631.53" process $proc$libresoc.v:139630$5898 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end attribute \src "libresoc.v:139632.3-139633.79" process $proc$libresoc.v:139632$5899 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end attribute \src "libresoc.v:139634.3-139635.69" process $proc$libresoc.v:139634$5900 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end attribute \src "libresoc.v:139636.3-139637.31" process $proc$libresoc.v:139636$5901 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end attribute \src "libresoc.v:139638.3-139639.31" process $proc$libresoc.v:139638$5902 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end attribute \src "libresoc.v:139640.3-139641.57" process $proc$libresoc.v:139640$5903 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end attribute \src "libresoc.v:139642.3-139643.47" process $proc$libresoc.v:139642$5904 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end attribute \src "libresoc.v:139644.3-139645.27" process $proc$libresoc.v:139644$5905 assign { } { } assign $0\io_bd[129:0] \io_bd$next sync negedge \negjtag_clk update \io_bd $0\io_bd[129:0] end attribute \src "libresoc.v:139646.3-139647.27" process $proc$libresoc.v:139646$5906 assign { } { } assign $0\io_sr[129:0] \io_sr$next sync posedge \posjtag_clk update \io_sr $0\io_sr[129:0] end attribute \src "libresoc.v:139683.3-139698.6" process $proc$libresoc.v:139683$5907 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] attribute \src "libresoc.v:139684.5-139684.29" switch \initial attribute \src "libresoc.v:139684.9-139684.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" switch { \$321 \_idblock_select_id \_fsm_isir } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\TAP_tdo[0:0] \_irblock_tdo attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $1\TAP_tdo[0:0] \io_sr [129] case assign $1\TAP_tdo[0:0] 1'0 end sync always update \TAP_tdo $0\TAP_tdo[0:0] end attribute \src "libresoc.v:139699.3-139707.6" process $proc$libresoc.v:139699$5908 assign { } { } assign { } { } assign $0\sr0_update_core$next[0:0]$5909 $1\sr0_update_core$next[0:0]$5910 attribute \src "libresoc.v:139700.5-139700.29" switch \initial attribute \src "libresoc.v:139700.9-139700.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr0_update_core$next[0:0]$5910 1'0 case assign $1\sr0_update_core$next[0:0]$5910 \sr0_update end sync always update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5909 end attribute \src "libresoc.v:139708.3-139716.6" process $proc$libresoc.v:139708$5911 assign { } { } assign { } { } assign $0\sr0_update_core_prev$next[0:0]$5912 $1\sr0_update_core_prev$next[0:0]$5913 attribute \src "libresoc.v:139709.5-139709.29" switch \initial attribute \src "libresoc.v:139709.9-139709.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr0_update_core_prev$next[0:0]$5913 1'0 case assign $1\sr0_update_core_prev$next[0:0]$5913 \sr0_update_core end sync always update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5912 end attribute \src "libresoc.v:139717.3-139733.6" process $proc$libresoc.v:139717$5914 assign { } { } assign { } { } assign $0\sr0__oe$next[0:0]$5915 $2\sr0__oe$next[0:0]$5917 attribute \src "libresoc.v:139718.5-139718.29" switch \initial attribute \src "libresoc.v:139718.9-139718.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" switch \$339 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr0__oe$next[0:0]$5916 \sr0_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\sr0__oe$next[0:0]$5916 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sr0__oe$next[0:0]$5917 1'0 case assign $2\sr0__oe$next[0:0]$5917 $1\sr0__oe$next[0:0]$5916 end sync always update \sr0__oe$next $0\sr0__oe$next[0:0]$5915 end attribute \src "libresoc.v:139734.3-139754.6" process $proc$libresoc.v:139734$5918 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr0_reg$next[2:0]$5919 $3\sr0_reg$next[2:0]$5922 attribute \src "libresoc.v:139735.5-139735.29" switch \initial attribute \src "libresoc.v:139735.9-139735.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" switch \sr0_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr0_reg$next[2:0]$5920 { \TAP_bus__tdi \sr0_reg [2:1] } case assign $1\sr0_reg$next[2:0]$5920 \sr0_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sr0_reg$next[2:0]$5921 \sr0__i case assign $2\sr0_reg$next[2:0]$5921 $1\sr0_reg$next[2:0]$5920 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\sr0_reg$next[2:0]$5922 3'000 case assign $3\sr0_reg$next[2:0]$5922 $2\sr0_reg$next[2:0]$5921 end sync always update \sr0_reg$next $0\sr0_reg$next[2:0]$5919 end attribute \src "libresoc.v:139755.3-139763.6" process $proc$libresoc.v:139755$5923 assign { } { } assign { } { } assign $0\jtag_wb_addrsr_update_core$next[0:0]$5924 $1\jtag_wb_addrsr_update_core$next[0:0]$5925 attribute \src "libresoc.v:139756.5-139756.29" switch \initial attribute \src "libresoc.v:139756.9-139756.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_addrsr_update_core$next[0:0]$5925 1'0 case assign $1\jtag_wb_addrsr_update_core$next[0:0]$5925 \jtag_wb_addrsr_update end sync always update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5924 end attribute \src "libresoc.v:139764.3-139772.6" process $proc$libresoc.v:139764$5926 assign { } { } assign { } { } assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 attribute \src "libresoc.v:139765.5-139765.29" switch \initial attribute \src "libresoc.v:139765.9-139765.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 1'0 case assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5928 \jtag_wb_addrsr_update_core end sync always update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5927 end attribute \src "libresoc.v:139773.3-139789.6" process $proc$libresoc.v:139773$5929 assign { } { } assign { } { } assign $0\jtag_wb_addrsr__oe$next[0:0]$5930 $2\jtag_wb_addrsr__oe$next[0:0]$5932 attribute \src "libresoc.v:139774.5-139774.29" switch \initial attribute \src "libresoc.v:139774.9-139774.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" switch \$357 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_addrsr__oe$next[0:0]$5931 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\jtag_wb_addrsr__oe$next[0:0]$5931 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\jtag_wb_addrsr__oe$next[0:0]$5932 1'0 case assign $2\jtag_wb_addrsr__oe$next[0:0]$5932 $1\jtag_wb_addrsr__oe$next[0:0]$5931 end sync always update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5930 end attribute \src "libresoc.v:139790.3-139810.6" process $proc$libresoc.v:139790$5933 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_addrsr_reg$next[28:0]$5934 $3\jtag_wb_addrsr_reg$next[28:0]$5937 attribute \src "libresoc.v:139791.5-139791.29" switch \initial attribute \src "libresoc.v:139791.9-139791.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" switch \jtag_wb_addrsr_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_addrsr_reg$next[28:0]$5935 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case assign $1\jtag_wb_addrsr_reg$next[28:0]$5935 \jtag_wb_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\jtag_wb_addrsr_reg$next[28:0]$5936 \jtag_wb_addrsr__i case assign $2\jtag_wb_addrsr_reg$next[28:0]$5936 $1\jtag_wb_addrsr_reg$next[28:0]$5935 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\jtag_wb_addrsr_reg$next[28:0]$5937 29'00000000000000000000000000000 case assign $3\jtag_wb_addrsr_reg$next[28:0]$5937 $2\jtag_wb_addrsr_reg$next[28:0]$5936 end sync always update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5934 end attribute \src "libresoc.v:139811.3-139819.6" process $proc$libresoc.v:139811$5938 assign { } { } assign { } { } assign $0\jtag_wb_datasr_update_core$next[0:0]$5939 $1\jtag_wb_datasr_update_core$next[0:0]$5940 attribute \src "libresoc.v:139812.5-139812.29" switch \initial attribute \src "libresoc.v:139812.9-139812.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_datasr_update_core$next[0:0]$5940 1'0 case assign $1\jtag_wb_datasr_update_core$next[0:0]$5940 \jtag_wb_datasr_update end sync always update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5939 end attribute \src "libresoc.v:139820.3-139828.6" process $proc$libresoc.v:139820$5941 assign { } { } assign { } { } assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 attribute \src "libresoc.v:139821.5-139821.29" switch \initial attribute \src "libresoc.v:139821.9-139821.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 1'0 case assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5943 \jtag_wb_datasr_update_core end sync always update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5942 end attribute \src "libresoc.v:139829.3-139845.6" process $proc$libresoc.v:139829$5944 assign { } { } assign { } { } assign $0\jtag_wb_datasr__oe$next[1:0]$5945 $2\jtag_wb_datasr__oe$next[1:0]$5947 attribute \src "libresoc.v:139830.5-139830.29" switch \initial attribute \src "libresoc.v:139830.9-139830.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" switch \$377 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_datasr__oe$next[1:0]$5946 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\jtag_wb_datasr__oe$next[1:0]$5946 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\jtag_wb_datasr__oe$next[1:0]$5947 2'00 case assign $2\jtag_wb_datasr__oe$next[1:0]$5947 $1\jtag_wb_datasr__oe$next[1:0]$5946 end sync always update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5945 end attribute \src "libresoc.v:139846.3-139866.6" process $proc$libresoc.v:139846$5948 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_datasr_reg$next[63:0]$5949 $3\jtag_wb_datasr_reg$next[63:0]$5952 attribute \src "libresoc.v:139847.5-139847.29" switch \initial attribute \src "libresoc.v:139847.9-139847.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" switch \jtag_wb_datasr_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_wb_datasr_reg$next[63:0]$5950 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case assign $1\jtag_wb_datasr_reg$next[63:0]$5950 \jtag_wb_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\jtag_wb_datasr_reg$next[63:0]$5951 \jtag_wb_datasr__i case assign $2\jtag_wb_datasr_reg$next[63:0]$5951 $1\jtag_wb_datasr_reg$next[63:0]$5950 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\jtag_wb_datasr_reg$next[63:0]$5952 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\jtag_wb_datasr_reg$next[63:0]$5952 $2\jtag_wb_datasr_reg$next[63:0]$5951 end sync always update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5949 end attribute \src "libresoc.v:139867.3-139875.6" process $proc$libresoc.v:139867$5953 assign { } { } assign { } { } assign $0\dmi0_addrsr_update_core$next[0:0]$5954 $1\dmi0_addrsr_update_core$next[0:0]$5955 attribute \src "libresoc.v:139868.5-139868.29" switch \initial attribute \src "libresoc.v:139868.9-139868.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_addrsr_update_core$next[0:0]$5955 1'0 case assign $1\dmi0_addrsr_update_core$next[0:0]$5955 \dmi0_addrsr_update end sync always update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5954 end attribute \src "libresoc.v:139876.3-139884.6" process $proc$libresoc.v:139876$5956 assign { } { } assign { } { } assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 attribute \src "libresoc.v:139877.5-139877.29" switch \initial attribute \src "libresoc.v:139877.9-139877.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 1'0 case assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5958 \dmi0_addrsr_update_core end sync always update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5957 end attribute \src "libresoc.v:139885.3-139901.6" process $proc$libresoc.v:139885$5959 assign { } { } assign { } { } assign $0\dmi0_addrsr__oe$next[0:0]$5960 $2\dmi0_addrsr__oe$next[0:0]$5962 attribute \src "libresoc.v:139886.5-139886.29" switch \initial attribute \src "libresoc.v:139886.9-139886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" switch \$395 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_addrsr__oe$next[0:0]$5961 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\dmi0_addrsr__oe$next[0:0]$5961 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dmi0_addrsr__oe$next[0:0]$5962 1'0 case assign $2\dmi0_addrsr__oe$next[0:0]$5962 $1\dmi0_addrsr__oe$next[0:0]$5961 end sync always update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5960 end attribute \src "libresoc.v:139902.3-139922.6" process $proc$libresoc.v:139902$5963 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\dmi0_addrsr_reg$next[7:0]$5964 $3\dmi0_addrsr_reg$next[7:0]$5967 attribute \src "libresoc.v:139903.5-139903.29" switch \initial attribute \src "libresoc.v:139903.9-139903.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" switch \dmi0_addrsr_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_addrsr_reg$next[7:0]$5965 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case assign $1\dmi0_addrsr_reg$next[7:0]$5965 \dmi0_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dmi0_addrsr_reg$next[7:0]$5966 \dmi0_addrsr__i case assign $2\dmi0_addrsr_reg$next[7:0]$5966 $1\dmi0_addrsr_reg$next[7:0]$5965 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dmi0_addrsr_reg$next[7:0]$5967 8'00000000 case assign $3\dmi0_addrsr_reg$next[7:0]$5967 $2\dmi0_addrsr_reg$next[7:0]$5966 end sync always update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5964 end attribute \src "libresoc.v:139923.3-139931.6" process $proc$libresoc.v:139923$5968 assign { } { } assign { } { } assign $0\dmi0_datasr_update_core$next[0:0]$5969 $1\dmi0_datasr_update_core$next[0:0]$5970 attribute \src "libresoc.v:139924.5-139924.29" switch \initial attribute \src "libresoc.v:139924.9-139924.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_datasr_update_core$next[0:0]$5970 1'0 case assign $1\dmi0_datasr_update_core$next[0:0]$5970 \dmi0_datasr_update end sync always update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5969 end attribute \src "libresoc.v:139932.3-139940.6" process $proc$libresoc.v:139932$5971 assign { } { } assign { } { } assign $0\dmi0_datasr_update_core_prev$next[0:0]$5972 $1\dmi0_datasr_update_core_prev$next[0:0]$5973 attribute \src "libresoc.v:139933.5-139933.29" switch \initial attribute \src "libresoc.v:139933.9-139933.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_datasr_update_core_prev$next[0:0]$5973 1'0 case assign $1\dmi0_datasr_update_core_prev$next[0:0]$5973 \dmi0_datasr_update_core end sync always update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5972 end attribute \src "libresoc.v:139941.3-139957.6" process $proc$libresoc.v:139941$5974 assign { } { } assign { } { } assign $0\dmi0_datasr__oe$next[1:0]$5975 $2\dmi0_datasr__oe$next[1:0]$5977 attribute \src "libresoc.v:139942.5-139942.29" switch \initial attribute \src "libresoc.v:139942.9-139942.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" switch \$415 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_datasr__oe$next[1:0]$5976 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\dmi0_datasr__oe$next[1:0]$5976 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dmi0_datasr__oe$next[1:0]$5977 2'00 case assign $2\dmi0_datasr__oe$next[1:0]$5977 $1\dmi0_datasr__oe$next[1:0]$5976 end sync always update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5975 end attribute \src "libresoc.v:139958.3-139978.6" process $proc$libresoc.v:139958$5978 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\dmi0_datasr_reg$next[63:0]$5979 $3\dmi0_datasr_reg$next[63:0]$5982 attribute \src "libresoc.v:139959.5-139959.29" switch \initial attribute \src "libresoc.v:139959.9-139959.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" switch \dmi0_datasr_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dmi0_datasr_reg$next[63:0]$5980 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case assign $1\dmi0_datasr_reg$next[63:0]$5980 \dmi0_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dmi0_datasr_reg$next[63:0]$5981 \dmi0_datasr__i case assign $2\dmi0_datasr_reg$next[63:0]$5981 $1\dmi0_datasr_reg$next[63:0]$5980 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dmi0_datasr_reg$next[63:0]$5982 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\dmi0_datasr_reg$next[63:0]$5982 $2\dmi0_datasr_reg$next[63:0]$5981 end sync always update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5979 end attribute \src "libresoc.v:139979.3-139987.6" process $proc$libresoc.v:139979$5983 assign { } { } assign { } { } assign $0\sr5_update_core$next[0:0]$5984 $1\sr5_update_core$next[0:0]$5985 attribute \src "libresoc.v:139980.5-139980.29" switch \initial attribute \src "libresoc.v:139980.9-139980.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr5_update_core$next[0:0]$5985 1'0 case assign $1\sr5_update_core$next[0:0]$5985 \sr5_update end sync always update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5984 end attribute \src "libresoc.v:139988.3-139996.6" process $proc$libresoc.v:139988$5986 assign { } { } assign { } { } assign $0\sr5_update_core_prev$next[0:0]$5987 $1\sr5_update_core_prev$next[0:0]$5988 attribute \src "libresoc.v:139989.5-139989.29" switch \initial attribute \src "libresoc.v:139989.9-139989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr5_update_core_prev$next[0:0]$5988 1'0 case assign $1\sr5_update_core_prev$next[0:0]$5988 \sr5_update_core end sync always update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5987 end attribute \src "libresoc.v:139997.3-140013.6" process $proc$libresoc.v:139997$5989 assign { } { } assign { } { } assign $0\sr5__oe$next[0:0]$5990 $2\sr5__oe$next[0:0]$5992 attribute \src "libresoc.v:139998.5-139998.29" switch \initial attribute \src "libresoc.v:139998.9-139998.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" switch \$433 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr5__oe$next[0:0]$5991 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\sr5__oe$next[0:0]$5991 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sr5__oe$next[0:0]$5992 1'0 case assign $2\sr5__oe$next[0:0]$5992 $1\sr5__oe$next[0:0]$5991 end sync always update \sr5__oe$next $0\sr5__oe$next[0:0]$5990 end attribute \src "libresoc.v:140014.3-140034.6" process $proc$libresoc.v:140014$5993 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr5_reg$next[2:0]$5994 $3\sr5_reg$next[2:0]$5997 attribute \src "libresoc.v:140015.5-140015.29" switch \initial attribute \src "libresoc.v:140015.9-140015.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" switch \sr5_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr5_reg$next[2:0]$5995 { \TAP_bus__tdi \sr5_reg [2:1] } case assign $1\sr5_reg$next[2:0]$5995 \sr5_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sr5_reg$next[2:0]$5996 \sr5__i case assign $2\sr5_reg$next[2:0]$5996 $1\sr5_reg$next[2:0]$5995 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\sr5_reg$next[2:0]$5997 3'000 case assign $3\sr5_reg$next[2:0]$5997 $2\sr5_reg$next[2:0]$5996 end sync always update \sr5_reg$next $0\sr5_reg$next[2:0]$5994 end attribute \src "libresoc.v:140035.3-140061.6" process $proc$libresoc.v:140035$5998 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] attribute \src "libresoc.v:140036.5-140036.29" switch \initial attribute \src "libresoc.v:140036.9-140036.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } attribute \src "libresoc.v:0.0-0.0" case 6'-----1 assign { } { } assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] attribute \src "libresoc.v:0.0-0.0" case 6'----1- assign { } { } assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] attribute \src "libresoc.v:0.0-0.0" case 6'---1-- assign { } { } assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] attribute \src "libresoc.v:0.0-0.0" case 6'--1--- assign { } { } assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] attribute \src "libresoc.v:0.0-0.0" case 6'-1---- assign { } { } assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] attribute \src "libresoc.v:0.0-0.0" case 6'1----- assign { } { } assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\TAP_bus__tdo[0:0] \TAP_tdo end sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end attribute \src "libresoc.v:140062.3-140106.6" process $proc$libresoc.v:140062$5999 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb__adr$next[28:0]$6000 $4\jtag_wb__adr$next[28:0]$6004 attribute \src "libresoc.v:140063.5-140063.29" switch \initial attribute \src "libresoc.v:140063.9-140063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\jtag_wb__adr$next[28:0]$6001 $2\jtag_wb__adr$next[28:0]$6002 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $2\jtag_wb__adr$next[28:0]$6002 \jtag_wb_addrsr__o attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $2\jtag_wb__adr$next[28:0]$6002 \$447 [28:0] case assign $2\jtag_wb__adr$next[28:0]$6002 \jtag_wb__adr end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\jtag_wb__adr$next[28:0]$6001 $3\jtag_wb__adr$next[28:0]$6003 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\jtag_wb__adr$next[28:0]$6003 \$450 [28:0] case assign $3\jtag_wb__adr$next[28:0]$6003 \jtag_wb__adr end case assign $1\jtag_wb__adr$next[28:0]$6001 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\jtag_wb__adr$next[28:0]$6004 29'00000000000000000000000000000 case assign $4\jtag_wb__adr$next[28:0]$6004 $1\jtag_wb__adr$next[28:0]$6001 end sync always update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6000 end attribute \src "libresoc.v:140107.3-140159.6" process $proc$libresoc.v:140107$6005 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$next[2:0]$6006 $5\fsm_state$next[2:0]$6011 attribute \src "libresoc.v:140108.5-140108.29" switch \initial attribute \src "libresoc.v:140108.9-140108.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fsm_state$next[2:0]$6007 $2\fsm_state$next[2:0]$6008 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $2\fsm_state$next[2:0]$6008 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $2\fsm_state$next[2:0]$6008 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $2\fsm_state$next[2:0]$6008 3'010 case assign $2\fsm_state$next[2:0]$6008 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\fsm_state$next[2:0]$6007 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\fsm_state$next[2:0]$6007 $3\fsm_state$next[2:0]$6009 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fsm_state$next[2:0]$6009 3'000 case assign $3\fsm_state$next[2:0]$6009 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\fsm_state$next[2:0]$6007 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\fsm_state$next[2:0]$6007 $4\fsm_state$next[2:0]$6010 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\fsm_state$next[2:0]$6010 3'001 case assign $4\fsm_state$next[2:0]$6010 \fsm_state end case assign $1\fsm_state$next[2:0]$6007 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\fsm_state$next[2:0]$6011 3'000 case assign $5\fsm_state$next[2:0]$6011 $1\fsm_state$next[2:0]$6007 end sync always update \fsm_state$next $0\fsm_state$next[2:0]$6006 end attribute \src "libresoc.v:140160.3-140186.6" process $proc$libresoc.v:140160$6012 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb__dat_w$next[63:0]$6013 $3\jtag_wb__dat_w$next[63:0]$6016 attribute \src "libresoc.v:140161.5-140161.29" switch \initial attribute \src "libresoc.v:140161.9-140161.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\jtag_wb__dat_w$next[63:0]$6014 $2\jtag_wb__dat_w$next[63:0]$6015 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb_datasr__o case assign $2\jtag_wb__dat_w$next[63:0]$6015 \jtag_wb__dat_w end case assign $1\jtag_wb__dat_w$next[63:0]$6014 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\jtag_wb__dat_w$next[63:0]$6016 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\jtag_wb__dat_w$next[63:0]$6016 $1\jtag_wb__dat_w$next[63:0]$6014 end sync always update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6013 end attribute \src "libresoc.v:140187.3-140215.6" process $proc$libresoc.v:140187$6017 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_datasr__i$next[63:0]$6018 $3\jtag_wb_datasr__i$next[63:0]$6021 attribute \src "libresoc.v:140188.5-140188.29" switch \initial attribute \src "libresoc.v:140188.9-140188.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\jtag_wb_datasr__i$next[63:0]$6019 $2\jtag_wb_datasr__i$next[63:0]$6020 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\jtag_wb_datasr__i$next[63:0]$6020 \jtag_wb__dat_r case assign $2\jtag_wb_datasr__i$next[63:0]$6020 \jtag_wb_datasr__i end case assign $1\jtag_wb_datasr__i$next[63:0]$6019 \jtag_wb_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\jtag_wb_datasr__i$next[63:0]$6021 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\jtag_wb_datasr__i$next[63:0]$6021 $1\jtag_wb_datasr__i$next[63:0]$6019 end sync always update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6018 end attribute \src "libresoc.v:140216.3-140260.6" process $proc$libresoc.v:140216$6022 assign { } { } assign { } { } assign { } { } assign $0\dmi0__addr_i$next[3:0]$6023 $4\dmi0__addr_i$next[3:0]$6027 attribute \src "libresoc.v:140217.5-140217.29" switch \initial attribute \src "libresoc.v:140217.9-140217.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dmi0__addr_i$next[3:0]$6024 $2\dmi0__addr_i$next[3:0]$6025 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $2\dmi0__addr_i$next[3:0]$6025 \dmi0_addrsr__o [3:0] attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $2\dmi0__addr_i$next[3:0]$6025 \$464 [3:0] case assign $2\dmi0__addr_i$next[3:0]$6025 \dmi0__addr_i end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\dmi0__addr_i$next[3:0]$6024 $3\dmi0__addr_i$next[3:0]$6026 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dmi0__addr_i$next[3:0]$6026 \$467 [3:0] case assign $3\dmi0__addr_i$next[3:0]$6026 \dmi0__addr_i end case assign $1\dmi0__addr_i$next[3:0]$6024 \dmi0__addr_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\dmi0__addr_i$next[3:0]$6027 4'0000 case assign $4\dmi0__addr_i$next[3:0]$6027 $1\dmi0__addr_i$next[3:0]$6024 end sync always update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6023 end attribute \src "libresoc.v:140261.3-140313.6" process $proc$libresoc.v:140261$6028 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$455$next[2:0]$6029 $5\fsm_state$455$next[2:0]$6034 attribute \src "libresoc.v:140262.5-140262.29" switch \initial attribute \src "libresoc.v:140262.9-140262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fsm_state$455$next[2:0]$6030 $2\fsm_state$455$next[2:0]$6031 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $2\fsm_state$455$next[2:0]$6031 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $2\fsm_state$455$next[2:0]$6031 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $2\fsm_state$455$next[2:0]$6031 3'010 case assign $2\fsm_state$455$next[2:0]$6031 \fsm_state$455 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\fsm_state$455$next[2:0]$6030 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\fsm_state$455$next[2:0]$6030 $3\fsm_state$455$next[2:0]$6032 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fsm_state$455$next[2:0]$6032 3'000 case assign $3\fsm_state$455$next[2:0]$6032 \fsm_state$455 end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\fsm_state$455$next[2:0]$6030 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\fsm_state$455$next[2:0]$6030 $4\fsm_state$455$next[2:0]$6033 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\fsm_state$455$next[2:0]$6033 3'001 case assign $4\fsm_state$455$next[2:0]$6033 \fsm_state$455 end case assign $1\fsm_state$455$next[2:0]$6030 \fsm_state$455 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\fsm_state$455$next[2:0]$6034 3'000 case assign $5\fsm_state$455$next[2:0]$6034 $1\fsm_state$455$next[2:0]$6030 end sync always update \fsm_state$455$next $0\fsm_state$455$next[2:0]$6029 end attribute \src "libresoc.v:140314.3-140340.6" process $proc$libresoc.v:140314$6035 assign { } { } assign { } { } assign { } { } assign $0\dmi0__din$next[63:0]$6036 $3\dmi0__din$next[63:0]$6039 attribute \src "libresoc.v:140315.5-140315.29" switch \initial attribute \src "libresoc.v:140315.9-140315.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dmi0__din$next[63:0]$6037 $2\dmi0__din$next[63:0]$6038 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign $2\dmi0__din$next[63:0]$6038 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign $2\dmi0__din$next[63:0]$6038 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $2\dmi0__din$next[63:0]$6038 \dmi0_datasr__o case assign $2\dmi0__din$next[63:0]$6038 \dmi0__din end case assign $1\dmi0__din$next[63:0]$6037 \dmi0__din end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dmi0__din$next[63:0]$6039 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\dmi0__din$next[63:0]$6039 $1\dmi0__din$next[63:0]$6037 end sync always update \dmi0__din$next $0\dmi0__din$next[63:0]$6036 end attribute \src "libresoc.v:140341.3-140369.6" process $proc$libresoc.v:140341$6040 assign { } { } assign { } { } assign { } { } assign $0\dmi0_datasr__i$next[63:0]$6041 $3\dmi0_datasr__i$next[63:0]$6044 attribute \src "libresoc.v:140342.5-140342.29" switch \initial attribute \src "libresoc.v:140342.9-140342.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\dmi0_datasr__i$next[63:0]$6042 $2\dmi0_datasr__i$next[63:0]$6043 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dmi0_datasr__i$next[63:0]$6043 \dmi0__dout case assign $2\dmi0_datasr__i$next[63:0]$6043 \dmi0_datasr__i end case assign $1\dmi0_datasr__i$next[63:0]$6042 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dmi0_datasr__i$next[63:0]$6044 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\dmi0_datasr__i$next[63:0]$6044 $1\dmi0_datasr__i$next[63:0]$6042 end sync always update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6041 end attribute \src "libresoc.v:140370.3-140390.6" process $proc$libresoc.v:140370$6045 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\wb_dcache_en$next[0:0]$6046 $2\wb_dcache_en$next[0:0]$6052 assign $0\wb_icache_en$next[0:0]$6047 $2\wb_icache_en$next[0:0]$6053 assign $0\wb_sram_en$next[0:0]$6048 $2\wb_sram_en$next[0:0]$6054 attribute \src "libresoc.v:140371.5-140371.29" switch \initial attribute \src "libresoc.v:140371.9-140371.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:106" switch \sr5__oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { $1\wb_sram_en$next[0:0]$6051 $1\wb_dcache_en$next[0:0]$6049 $1\wb_icache_en$next[0:0]$6050 } \sr5__o case assign $1\wb_dcache_en$next[0:0]$6049 \wb_dcache_en assign $1\wb_icache_en$next[0:0]$6050 \wb_icache_en assign $1\wb_sram_en$next[0:0]$6051 \wb_sram_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign $2\wb_icache_en$next[0:0]$6053 1'1 assign $2\wb_dcache_en$next[0:0]$6052 1'1 assign $2\wb_sram_en$next[0:0]$6054 1'1 case assign $2\wb_dcache_en$next[0:0]$6052 $1\wb_dcache_en$next[0:0]$6049 assign $2\wb_icache_en$next[0:0]$6053 $1\wb_icache_en$next[0:0]$6050 assign $2\wb_sram_en$next[0:0]$6054 $1\wb_sram_en$next[0:0]$6051 end sync always update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6046 update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6047 update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6048 end attribute \src "libresoc.v:140391.3-140400.6" process $proc$libresoc.v:140391$6055 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] attribute \src "libresoc.v:140392.5-140392.29" switch \initial attribute \src "libresoc.v:140392.9-140392.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:109" switch \sr5__ie attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sr5__i[2:0] { \wb_sram_en \wb_dcache_en \wb_icache_en } case assign $1\sr5__i[2:0] 3'000 end sync always update \sr5__i $0\sr5__i[2:0] end attribute \src "libresoc.v:140401.3-140418.6" process $proc$libresoc.v:140401$6056 assign { } { } assign { } { } assign { } { } assign $0\io_sr$next[129:0]$6057 $2\io_sr$next[129:0]$6059 attribute \src "libresoc.v:140402.5-140402.29" switch \initial attribute \src "libresoc.v:140402.9-140402.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\io_sr$next[129:0]$6058 { \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $1\io_sr$next[129:0]$6058 { \io_sr [128:0] \TAP_bus__tdi } case assign $1\io_sr$next[129:0]$6058 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\io_sr$next[129:0]$6059 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case assign $2\io_sr$next[129:0]$6059 $1\io_sr$next[129:0]$6058 end sync always update \io_sr$next $0\io_sr$next[129:0]$6057 end attribute \src "libresoc.v:140419.3-140439.6" process $proc$libresoc.v:140419$6060 assign { } { } assign { } { } assign { } { } assign $0\io_bd$next[129:0]$6061 $2\io_bd$next[129:0]$6063 attribute \src "libresoc.v:140420.5-140420.29" switch \initial attribute \src "libresoc.v:140420.9-140420.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign $1\io_bd$next[129:0]$6062 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign $1\io_bd$next[129:0]$6062 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $1\io_bd$next[129:0]$6062 \io_sr case assign $1\io_bd$next[129:0]$6062 \io_bd end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\io_bd$next[129:0]$6063 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case assign $2\io_bd$next[129:0]$6063 $1\io_bd$next[129:0]$6062 end sync always update \io_bd$next $0\io_bd$next[129:0]$6061 end connect \$9 $eq$libresoc.v:139342$5636_Y connect \$99 $ternary$libresoc.v:139343$5637_Y connect \$101 $ternary$libresoc.v:139344$5638_Y connect \$103 $ternary$libresoc.v:139345$5639_Y connect \$105 $ternary$libresoc.v:139346$5640_Y connect \$107 $ternary$libresoc.v:139347$5641_Y connect \$109 $ternary$libresoc.v:139348$5642_Y connect \$111 $ternary$libresoc.v:139349$5643_Y connect \$113 $ternary$libresoc.v:139350$5644_Y connect \$115 $ternary$libresoc.v:139351$5645_Y connect \$117 $ternary$libresoc.v:139352$5646_Y connect \$11 $eq$libresoc.v:139353$5647_Y connect \$119 $ternary$libresoc.v:139354$5648_Y connect \$121 $ternary$libresoc.v:139355$5649_Y connect \$123 $ternary$libresoc.v:139356$5650_Y connect \$125 $ternary$libresoc.v:139357$5651_Y connect \$127 $ternary$libresoc.v:139358$5652_Y connect \$129 $ternary$libresoc.v:139359$5653_Y connect \$131 $ternary$libresoc.v:139360$5654_Y connect \$133 $ternary$libresoc.v:139361$5655_Y connect \$135 $ternary$libresoc.v:139362$5656_Y connect \$137 $ternary$libresoc.v:139363$5657_Y connect \$13 $eq$libresoc.v:139364$5658_Y connect \$139 $ternary$libresoc.v:139365$5659_Y connect \$141 $ternary$libresoc.v:139366$5660_Y connect \$143 $ternary$libresoc.v:139367$5661_Y connect \$145 $ternary$libresoc.v:139368$5662_Y connect \$147 $ternary$libresoc.v:139369$5663_Y connect \$149 $ternary$libresoc.v:139370$5664_Y connect \$151 $ternary$libresoc.v:139371$5665_Y connect \$153 $ternary$libresoc.v:139372$5666_Y connect \$155 $ternary$libresoc.v:139373$5667_Y connect \$157 $ternary$libresoc.v:139374$5668_Y connect \$15 $or$libresoc.v:139375$5669_Y connect \$159 $ternary$libresoc.v:139376$5670_Y connect \$161 $ternary$libresoc.v:139377$5671_Y connect \$163 $ternary$libresoc.v:139378$5672_Y connect \$165 $ternary$libresoc.v:139379$5673_Y connect \$167 $ternary$libresoc.v:139380$5674_Y connect \$169 $ternary$libresoc.v:139381$5675_Y connect \$171 $ternary$libresoc.v:139382$5676_Y connect \$173 $ternary$libresoc.v:139383$5677_Y connect \$175 $ternary$libresoc.v:139384$5678_Y connect \$177 $ternary$libresoc.v:139385$5679_Y connect \$17 $and$libresoc.v:139386$5680_Y connect \$179 $ternary$libresoc.v:139387$5681_Y connect \$181 $ternary$libresoc.v:139388$5682_Y connect \$183 $ternary$libresoc.v:139389$5683_Y connect \$185 $ternary$libresoc.v:139390$5684_Y connect \$187 $ternary$libresoc.v:139391$5685_Y connect \$189 $ternary$libresoc.v:139392$5686_Y connect \$191 $ternary$libresoc.v:139393$5687_Y connect \$193 $ternary$libresoc.v:139394$5688_Y connect \$195 $ternary$libresoc.v:139395$5689_Y connect \$197 $ternary$libresoc.v:139396$5690_Y connect \$1 $eq$libresoc.v:139397$5691_Y connect \$19 $eq$libresoc.v:139398$5692_Y connect \$199 $ternary$libresoc.v:139399$5693_Y connect \$201 $ternary$libresoc.v:139400$5694_Y connect \$203 $ternary$libresoc.v:139401$5695_Y connect \$205 $ternary$libresoc.v:139402$5696_Y connect \$207 $ternary$libresoc.v:139403$5697_Y connect \$209 $ternary$libresoc.v:139404$5698_Y connect \$211 $ternary$libresoc.v:139405$5699_Y connect \$213 $ternary$libresoc.v:139406$5700_Y connect \$215 $ternary$libresoc.v:139407$5701_Y connect \$217 $ternary$libresoc.v:139408$5702_Y connect \$21 $eq$libresoc.v:139409$5703_Y connect \$219 $ternary$libresoc.v:139410$5704_Y connect \$221 $ternary$libresoc.v:139411$5705_Y connect \$223 $ternary$libresoc.v:139412$5706_Y connect \$225 $ternary$libresoc.v:139413$5707_Y connect \$227 $ternary$libresoc.v:139414$5708_Y connect \$229 $ternary$libresoc.v:139415$5709_Y connect \$231 $ternary$libresoc.v:139416$5710_Y connect \$233 $ternary$libresoc.v:139417$5711_Y connect \$235 $ternary$libresoc.v:139418$5712_Y connect \$237 $ternary$libresoc.v:139419$5713_Y connect \$23 $or$libresoc.v:139420$5714_Y connect \$239 $ternary$libresoc.v:139421$5715_Y connect \$241 $ternary$libresoc.v:139422$5716_Y connect \$243 $ternary$libresoc.v:139423$5717_Y connect \$245 $ternary$libresoc.v:139424$5718_Y connect \$247 $ternary$libresoc.v:139425$5719_Y connect \$249 $ternary$libresoc.v:139426$5720_Y connect \$251 $ternary$libresoc.v:139427$5721_Y connect \$253 $ternary$libresoc.v:139428$5722_Y connect \$255 $ternary$libresoc.v:139429$5723_Y connect \$257 $ternary$libresoc.v:139430$5724_Y connect \$25 $eq$libresoc.v:139431$5725_Y connect \$259 $ternary$libresoc.v:139432$5726_Y connect \$261 $ternary$libresoc.v:139433$5727_Y connect \$263 $ternary$libresoc.v:139434$5728_Y connect \$265 $ternary$libresoc.v:139435$5729_Y connect \$267 $ternary$libresoc.v:139436$5730_Y connect \$269 $ternary$libresoc.v:139437$5731_Y connect \$271 $ternary$libresoc.v:139438$5732_Y connect \$273 $ternary$libresoc.v:139439$5733_Y connect \$275 $ternary$libresoc.v:139440$5734_Y connect \$277 $ternary$libresoc.v:139441$5735_Y connect \$27 $or$libresoc.v:139442$5736_Y connect \$279 $ternary$libresoc.v:139443$5737_Y connect \$281 $ternary$libresoc.v:139444$5738_Y connect \$283 $ternary$libresoc.v:139445$5739_Y connect \$285 $ternary$libresoc.v:139446$5740_Y connect \$287 $ternary$libresoc.v:139447$5741_Y connect \$289 $ternary$libresoc.v:139448$5742_Y connect \$291 $ternary$libresoc.v:139449$5743_Y connect \$293 $ternary$libresoc.v:139450$5744_Y connect \$295 $ternary$libresoc.v:139451$5745_Y connect \$297 $ternary$libresoc.v:139452$5746_Y connect \$29 $and$libresoc.v:139453$5747_Y connect \$299 $ternary$libresoc.v:139454$5748_Y connect \$301 $ternary$libresoc.v:139455$5749_Y connect \$303 $ternary$libresoc.v:139456$5750_Y connect \$305 $ternary$libresoc.v:139457$5751_Y connect \$307 $ternary$libresoc.v:139458$5752_Y connect \$309 $ternary$libresoc.v:139459$5753_Y connect \$311 $eq$libresoc.v:139460$5754_Y connect \$313 $eq$libresoc.v:139461$5755_Y connect \$315 $or$libresoc.v:139462$5756_Y connect \$317 $eq$libresoc.v:139463$5757_Y connect \$31 $and$libresoc.v:139464$5758_Y connect \$319 $or$libresoc.v:139465$5759_Y connect \$321 $and$libresoc.v:139466$5760_Y connect \$323 $eq$libresoc.v:139467$5761_Y connect \$325 $ne$libresoc.v:139468$5762_Y connect \$327 $and$libresoc.v:139469$5763_Y connect \$329 $ne$libresoc.v:139470$5764_Y connect \$331 $and$libresoc.v:139471$5765_Y connect \$333 $ne$libresoc.v:139472$5766_Y connect \$335 $and$libresoc.v:139473$5767_Y connect \$337 $not$libresoc.v:139474$5768_Y connect \$33 $eq$libresoc.v:139475$5769_Y connect \$339 $and$libresoc.v:139476$5770_Y connect \$341 $eq$libresoc.v:139477$5771_Y connect \$343 $ne$libresoc.v:139478$5772_Y connect \$345 $and$libresoc.v:139479$5773_Y connect \$347 $ne$libresoc.v:139480$5774_Y connect \$349 $and$libresoc.v:139481$5775_Y connect \$351 $ne$libresoc.v:139482$5776_Y connect \$353 $and$libresoc.v:139483$5777_Y connect \$355 $not$libresoc.v:139484$5778_Y connect \$357 $and$libresoc.v:139485$5779_Y connect \$35 $eq$libresoc.v:139486$5780_Y connect \$359 $eq$libresoc.v:139487$5781_Y connect \$361 $eq$libresoc.v:139488$5782_Y connect \$363 $ne$libresoc.v:139489$5783_Y connect \$365 $and$libresoc.v:139490$5784_Y connect \$367 $ne$libresoc.v:139491$5785_Y connect \$369 $and$libresoc.v:139492$5786_Y connect \$371 $ne$libresoc.v:139493$5787_Y connect \$373 $and$libresoc.v:139494$5788_Y connect \$375 $not$libresoc.v:139495$5789_Y connect \$377 $and$libresoc.v:139496$5790_Y connect \$37 $or$libresoc.v:139497$5791_Y connect \$379 $eq$libresoc.v:139498$5792_Y connect \$381 $ne$libresoc.v:139499$5793_Y connect \$383 $and$libresoc.v:139500$5794_Y connect \$385 $ne$libresoc.v:139501$5795_Y connect \$387 $and$libresoc.v:139502$5796_Y connect \$389 $ne$libresoc.v:139503$5797_Y connect \$391 $and$libresoc.v:139504$5798_Y connect \$393 $not$libresoc.v:139505$5799_Y connect \$395 $and$libresoc.v:139506$5800_Y connect \$397 $eq$libresoc.v:139507$5801_Y connect \$3 $eq$libresoc.v:139508$5802_Y connect \$39 $eq$libresoc.v:139509$5803_Y connect \$399 $eq$libresoc.v:139510$5804_Y connect \$401 $ne$libresoc.v:139511$5805_Y connect \$403 $and$libresoc.v:139512$5806_Y connect \$405 $ne$libresoc.v:139513$5807_Y connect \$407 $and$libresoc.v:139514$5808_Y connect \$409 $ne$libresoc.v:139515$5809_Y connect \$411 $and$libresoc.v:139516$5810_Y connect \$413 $not$libresoc.v:139517$5811_Y connect \$415 $and$libresoc.v:139518$5812_Y connect \$417 $eq$libresoc.v:139519$5813_Y connect \$41 $or$libresoc.v:139520$5814_Y connect \$419 $ne$libresoc.v:139521$5815_Y connect \$421 $and$libresoc.v:139522$5816_Y connect \$423 $ne$libresoc.v:139523$5817_Y connect \$425 $and$libresoc.v:139524$5818_Y connect \$427 $ne$libresoc.v:139525$5819_Y connect \$429 $and$libresoc.v:139526$5820_Y connect \$431 $not$libresoc.v:139527$5821_Y connect \$433 $and$libresoc.v:139528$5822_Y connect \$436 $eq$libresoc.v:139529$5823_Y connect \$435 $not$libresoc.v:139530$5824_Y connect \$43 $and$libresoc.v:139531$5825_Y connect \$439 $eq$libresoc.v:139532$5826_Y connect \$441 $eq$libresoc.v:139533$5827_Y connect \$443 $or$libresoc.v:139534$5828_Y connect \$445 $eq$libresoc.v:139535$5829_Y connect \$448 $add$libresoc.v:139536$5830_Y connect \$451 $add$libresoc.v:139537$5831_Y connect \$453 $pos$libresoc.v:139538$5833_Y connect \$456 $eq$libresoc.v:139539$5834_Y connect \$458 $eq$libresoc.v:139540$5835_Y connect \$45 $and$libresoc.v:139541$5836_Y connect \$460 $or$libresoc.v:139542$5837_Y connect \$462 $eq$libresoc.v:139543$5838_Y connect \$465 $add$libresoc.v:139544$5839_Y connect \$468 $add$libresoc.v:139545$5840_Y connect \$47 $eq$libresoc.v:139546$5841_Y connect \$49 $eq$libresoc.v:139547$5842_Y connect \$51 $ternary$libresoc.v:139548$5843_Y connect \$53 $ternary$libresoc.v:139549$5844_Y connect \$55 $ternary$libresoc.v:139550$5845_Y connect \$57 $ternary$libresoc.v:139551$5846_Y connect \$5 $or$libresoc.v:139552$5847_Y connect \$59 $ternary$libresoc.v:139553$5848_Y connect \$61 $ternary$libresoc.v:139554$5849_Y connect \$63 $ternary$libresoc.v:139555$5850_Y connect \$65 $ternary$libresoc.v:139556$5851_Y connect \$67 $ternary$libresoc.v:139557$5852_Y connect \$69 $ternary$libresoc.v:139558$5853_Y connect \$71 $ternary$libresoc.v:139559$5854_Y connect \$73 $ternary$libresoc.v:139560$5855_Y connect \$75 $ternary$libresoc.v:139561$5856_Y connect \$77 $ternary$libresoc.v:139562$5857_Y connect \$7 $and$libresoc.v:139563$5858_Y connect \$79 $ternary$libresoc.v:139564$5859_Y connect \$81 $ternary$libresoc.v:139565$5860_Y connect \$83 $ternary$libresoc.v:139566$5861_Y connect \$85 $ternary$libresoc.v:139567$5862_Y connect \$87 $ternary$libresoc.v:139568$5863_Y connect \$89 $ternary$libresoc.v:139569$5864_Y connect \$91 $ternary$libresoc.v:139570$5865_Y connect \$93 $ternary$libresoc.v:139571$5866_Y connect \$95 $ternary$libresoc.v:139572$5867_Y connect \$97 $ternary$libresoc.v:139573$5868_Y connect \$447 \$448 connect \$450 \$451 connect \$464 \$465 connect \$467 \$468 connect \sr5__ie 1'0 connect \sr0__i \sr0__o connect \dmi0__we_i \$462 connect \dmi0__req_i \$460 connect \dmi0_addrsr__i \$453 connect \jtag_wb__we \$445 connect \jtag_wb__stb \$443 connect \jtag_wb__cyc \$435 connect \jtag_wb__sel 1'1 connect \jtag_wb_addrsr__i \jtag_wb__adr connect \sr5_update \$429 connect \sr5_shift \$425 connect \sr5_capture \$421 connect \sr5_isir \$417 connect \sr5__o \sr5_reg connect \dmi0_datasr_update \$411 connect \dmi0_datasr_shift \$407 connect \dmi0_datasr_capture \$403 connect \dmi0_datasr_isir { \$399 \$397 } connect \dmi0_datasr__o \dmi0_datasr_reg connect \dmi0_addrsr_update \$391 connect \dmi0_addrsr_shift \$387 connect \dmi0_addrsr_capture \$383 connect \dmi0_addrsr_isir \$379 connect \dmi0_addrsr__o \dmi0_addrsr_reg connect \jtag_wb_datasr_update \$373 connect \jtag_wb_datasr_shift \$369 connect \jtag_wb_datasr_capture \$365 connect \jtag_wb_datasr_isir { \$361 \$359 } connect \jtag_wb_datasr__o \jtag_wb_datasr_reg connect \jtag_wb_addrsr_update \$353 connect \jtag_wb_addrsr_shift \$349 connect \jtag_wb_addrsr_capture \$345 connect \jtag_wb_addrsr_isir \$341 connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg connect \sr0_update \$335 connect \sr0_shift \$331 connect \sr0_capture \$327 connect \sr0_isir \$323 connect \sr0__o \sr0_reg connect \eint_2__core__i \$309 connect \eint_1__core__i \$307 connect \eint_0__core__i \$305 connect \mtwi_scl__pad__o \$303 connect \mtwi_sda__pad__oe \$301 connect \mtwi_sda__pad__o \$299 connect \mtwi_sda__core__i \$297 connect \gpio_s7__pad__oe \$295 connect \gpio_s7__pad__o \$293 connect \gpio_s7__core__i \$291 connect \gpio_s6__pad__oe \$289 connect \gpio_s6__pad__o \$287 connect \gpio_s6__core__i \$285 connect \gpio_s5__pad__oe \$283 connect \gpio_s5__pad__o \$281 connect \gpio_s5__core__i \$279 connect \gpio_s4__pad__oe \$277 connect \gpio_s4__pad__o \$275 connect \gpio_s4__core__i \$273 connect \gpio_s3__pad__oe \$271 connect \gpio_s3__pad__o \$269 connect \gpio_s3__core__i \$267 connect \gpio_s2__pad__oe \$265 connect \gpio_s2__pad__o \$263 connect \gpio_s2__core__i \$261 connect \gpio_s1__pad__oe \$259 connect \gpio_s1__pad__o \$257 connect \gpio_s1__core__i \$255 connect \gpio_s0__pad__oe \$253 connect \gpio_s0__pad__o \$251 connect \gpio_s0__core__i \$249 connect \gpio_e15__pad__oe \$247 connect \gpio_e15__pad__o \$245 connect \gpio_e15__core__i \$243 connect \gpio_e14__pad__oe \$241 connect \gpio_e14__pad__o \$239 connect \gpio_e14__core__i \$237 connect \gpio_e13__pad__oe \$235 connect \gpio_e13__pad__o \$233 connect \gpio_e13__core__i \$231 connect \gpio_e12__pad__oe \$229 connect \gpio_e12__pad__o \$227 connect \gpio_e12__core__i \$225 connect \gpio_e11__pad__oe \$223 connect \gpio_e11__pad__o \$221 connect \gpio_e11__core__i \$219 connect \gpio_e10__pad__oe \$217 connect \gpio_e10__pad__o \$215 connect \gpio_e10__core__i \$213 connect \gpio_e9__pad__oe \$211 connect \gpio_e9__pad__o \$209 connect \gpio_e9__core__i \$207 connect \gpio_e8__pad__oe \$205 connect \gpio_e8__pad__o \$203 connect \gpio_e8__core__i \$201 connect \sdr_dq_15__pad__oe \$199 connect \sdr_dq_15__pad__o \$197 connect \sdr_dq_15__core__i \$195 connect \sdr_dq_14__pad__oe \$193 connect \sdr_dq_14__pad__o \$191 connect \sdr_dq_14__core__i \$189 connect \sdr_dq_13__pad__oe \$187 connect \sdr_dq_13__pad__o \$185 connect \sdr_dq_13__core__i \$183 connect \sdr_dq_12__pad__oe \$181 connect \sdr_dq_12__pad__o \$179 connect \sdr_dq_12__core__i \$177 connect \sdr_dq_11__pad__oe \$175 connect \sdr_dq_11__pad__o \$173 connect \sdr_dq_11__core__i \$171 connect \sdr_dq_10__pad__oe \$169 connect \sdr_dq_10__pad__o \$167 connect \sdr_dq_10__core__i \$165 connect \sdr_dq_9__pad__oe \$163 connect \sdr_dq_9__pad__o \$161 connect \sdr_dq_9__core__i \$159 connect \sdr_dq_8__pad__oe \$157 connect \sdr_dq_8__pad__o \$155 connect \sdr_dq_8__core__i \$153 connect \sdr_dm_1__pad__o \$151 connect \sdr_a_12__pad__o \$149 connect \sdr_a_11__pad__o \$147 connect \sdr_a_10__pad__o \$145 connect \sdr_cs_n__pad__o \$143 connect \sdr_we_n__pad__o \$141 connect \sdr_cas_n__pad__o \$139 connect \sdr_ras_n__pad__o \$137 connect \sdr_cke__pad__o \$135 connect \sdr_clock__pad__o \$133 connect \sdr_ba_1__pad__o \$131 connect \sdr_ba_0__pad__o \$129 connect \sdr_a_9__pad__o \$127 connect \sdr_a_8__pad__o \$125 connect \sdr_a_7__pad__o \$123 connect \sdr_a_6__pad__o \$121 connect \sdr_a_5__pad__o \$119 connect \sdr_a_4__pad__o \$117 connect \sdr_a_3__pad__o \$115 connect \sdr_a_2__pad__o \$113 connect \sdr_a_1__pad__o \$111 connect \sdr_a_0__pad__o \$109 connect \sdr_dq_7__pad__oe \$107 connect \sdr_dq_7__pad__o \$105 connect \sdr_dq_7__core__i \$103 connect \sdr_dq_6__pad__oe \$101 connect \sdr_dq_6__pad__o \$99 connect \sdr_dq_6__core__i \$97 connect \sdr_dq_5__pad__oe \$95 connect \sdr_dq_5__pad__o \$93 connect \sdr_dq_5__core__i \$91 connect \sdr_dq_4__pad__oe \$89 connect \sdr_dq_4__pad__o \$87 connect \sdr_dq_4__core__i \$85 connect \sdr_dq_3__pad__oe \$83 connect \sdr_dq_3__pad__o \$81 connect \sdr_dq_3__core__i \$79 connect \sdr_dq_2__pad__oe \$77 connect \sdr_dq_2__pad__o \$75 connect \sdr_dq_2__core__i \$73 connect \sdr_dq_1__pad__oe \$71 connect \sdr_dq_1__pad__o \$69 connect \sdr_dq_1__core__i \$67 connect \sdr_dq_0__pad__oe \$65 connect \sdr_dq_0__pad__o \$63 connect \sdr_dq_0__core__i \$61 connect \sdr_dm_0__pad__o \$59 connect \mspi0_miso__core__i \$57 connect \mspi0_mosi__pad__o \$55 connect \mspi0_cs_n__pad__o \$53 connect \mspi0_clk__pad__o \$51 connect \io_bd2core \$49 connect \io_bd2io \$47 connect \io_update \$45 connect \io_shift \$31 connect \io_capture \$17 connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end attribute \src "libresoc.v:140625.1-140814.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 31 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 45 output 28 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 22 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 input 27 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 output 30 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 24 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 8 output 26 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 25 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 29 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 input 6 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 7 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire output 16 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire output 2 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 input 5 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 8 \ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 9 \ldst_port0_exc_$signal$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 10 \ldst_port0_exc_$signal$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 11 \ldst_port0_exc_$signal$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 12 \ldst_port0_exc_$signal$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 13 \ldst_port0_exc_$signal$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 14 \ldst_port0_exc_$signal$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 15 \ldst_port0_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire input 3 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 4 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 17 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 18 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 48 \pimem_ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pimem_ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire \pimem_ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire \pimem_ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 \pimem_ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \pimem_ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire \pimem_ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire \pimem_ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pimem_ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pimem_ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \pimem_ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \pimem_ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 \pimem_m_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" wire \pimem_m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 \pimem_x_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" wire \pimem_x_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" wire \pimem_x_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" wire width 8 \pimem_x_mask_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" wire width 64 \pimem_x_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" wire \pimem_x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire \pimem_x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 attribute \src "libresoc.v:140730.12-140764.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \ldst_port0_addr_i \ldst_port0_addr_i connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \ldst_port0_busy_o connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o connect \ldst_port0_data_len \ldst_port0_data_len connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \ldst_port0_st_data_i connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:140765.9-140787.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dbus__ack \dbus__ack connect \dbus__adr \dbus__adr connect \dbus__cyc \dbus__cyc connect \dbus__dat_r \dbus__dat_r connect \dbus__dat_w \dbus__dat_w connect \dbus__err \dbus__err connect \dbus__sel \dbus__sel connect \dbus__stb \dbus__stb connect \dbus__we \dbus__we connect \m_ld_data_o \pimem_m_ld_data_o connect \m_valid_i \pimem_m_valid_i connect \wb_dcache_en \wb_dcache_en connect \x_addr_i \pimem_x_addr_i connect \x_busy_o \pimem_x_busy_o connect \x_ld_i \pimem_x_ld_i connect \x_mask_i \pimem_x_mask_i connect \x_st_data_i \pimem_x_st_data_i connect \x_st_i \pimem_x_st_i connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:140788.9-140812.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o connect \ldst_port0_data_len \pimem_ldst_port0_data_len connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok connect \m_ld_data_o \pimem_m_ld_data_o connect \m_valid_i \pimem_m_valid_i connect \x_addr_i \pimem_x_addr_i connect \x_busy_o \pimem_x_busy_o connect \x_ld_i \pimem_x_ld_i connect \x_mask_i \pimem_x_mask_i connect \x_st_data_i \pimem_x_st_data_i connect \x_st_i \pimem_x_st_i connect \x_valid_i \pimem_x_valid_i end connect \pimem_ldst_port0_exc_$signal 1'0 end attribute \src "libresoc.v:140818.1-141226.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 attribute \src "libresoc.v:141081.3-141095.6" wire $0\idx_l$23$next[0:0]$6142 attribute \src "libresoc.v:140981.3-140982.35" wire $0\idx_l$23[0:0]$6109 attribute \src "libresoc.v:140839.7-140839.24" wire $0\idx_l$23[0:0]$6164 attribute \src "libresoc.v:141136.3-141145.6" wire $0\idx_l_r_idx_l[0:0] attribute \src "libresoc.v:141126.3-141135.6" wire $0\idx_l_s_idx_l[0:0] attribute \src "libresoc.v:140819.7-140819.20" wire $0\initial[0:0] attribute \src "libresoc.v:141002.3-141011.6" wire width 48 $0\ldst_port0_addr_i$12[47:0]$6111 attribute \src "libresoc.v:141012.3-141021.6" wire $0\ldst_port0_addr_i_ok$13[0:0]$6114 attribute \src "libresoc.v:141054.3-141063.6" wire $0\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:141044.3-141053.6" wire $0\ldst_port0_busy_o[0:0] attribute \src "libresoc.v:141116.3-141125.6" wire $0\ldst_port0_cache_paradox[0:0] attribute \src "libresoc.v:141191.3-141200.6" wire width 4 $0\ldst_port0_data_len$11[3:0]$6159 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$1[0:0]$6126 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$2[0:0]$6127 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$3[0:0]$6128 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$4[0:0]$6129 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$5[0:0]$6130 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$6[0:0]$6131 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal$7[0:0]$6132 attribute \src "libresoc.v:141064.3-141080.6" wire $0\ldst_port0_exc_$signal[0:0]$6125 attribute \src "libresoc.v:141201.3-141210.6" wire $0\ldst_port0_go_die_i[0:0] attribute \src "libresoc.v:141171.3-141180.6" wire $0\ldst_port0_is_ld_i$8[0:0]$6153 attribute \src "libresoc.v:141181.3-141190.6" wire $0\ldst_port0_is_st_i$9[0:0]$6156 attribute \src "libresoc.v:141033.3-141043.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] attribute \src "libresoc.v:141033.3-141043.6" wire $0\ldst_port0_ld_data_o_ok[0:0] attribute \src "libresoc.v:141106.3-141115.6" wire $0\ldst_port0_ldst_error[0:0] attribute \src "libresoc.v:141096.3-141105.6" wire $0\ldst_port0_mmu_done[0:0] attribute \src "libresoc.v:141022.3-141032.6" wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6117 attribute \src "libresoc.v:141022.3-141032.6" wire $0\ldst_port0_st_data_i_ok$17[0:0]$6118 attribute \src "libresoc.v:140979.3-140980.36" wire $0\reset_delay[0:0] attribute \src "libresoc.v:141161.3-141170.6" wire $0\reset_l_r_reset[0:0] attribute \src "libresoc.v:141146.3-141160.6" wire $0\reset_l_s_reset[0:0] attribute \src "libresoc.v:141081.3-141095.6" wire $1\idx_l$23$next[0:0]$6143 attribute \src "libresoc.v:141136.3-141145.6" wire $1\idx_l_r_idx_l[0:0] attribute \src "libresoc.v:141126.3-141135.6" wire $1\idx_l_s_idx_l[0:0] attribute \src "libresoc.v:141002.3-141011.6" wire width 48 $1\ldst_port0_addr_i$12[47:0]$6112 attribute \src "libresoc.v:141012.3-141021.6" wire $1\ldst_port0_addr_i_ok$13[0:0]$6115 attribute \src "libresoc.v:141054.3-141063.6" wire $1\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:141044.3-141053.6" wire $1\ldst_port0_busy_o[0:0] attribute \src "libresoc.v:141116.3-141125.6" wire $1\ldst_port0_cache_paradox[0:0] attribute \src "libresoc.v:141191.3-141200.6" wire width 4 $1\ldst_port0_data_len$11[3:0]$6160 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$1[0:0]$6134 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$2[0:0]$6135 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$3[0:0]$6136 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$4[0:0]$6137 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$5[0:0]$6138 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$6[0:0]$6139 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal$7[0:0]$6140 attribute \src "libresoc.v:141064.3-141080.6" wire $1\ldst_port0_exc_$signal[0:0]$6133 attribute \src "libresoc.v:141201.3-141210.6" wire $1\ldst_port0_go_die_i[0:0] attribute \src "libresoc.v:141171.3-141180.6" wire $1\ldst_port0_is_ld_i$8[0:0]$6154 attribute \src "libresoc.v:141181.3-141190.6" wire $1\ldst_port0_is_st_i$9[0:0]$6157 attribute \src "libresoc.v:141033.3-141043.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] attribute \src "libresoc.v:141033.3-141043.6" wire $1\ldst_port0_ld_data_o_ok[0:0] attribute \src "libresoc.v:141106.3-141115.6" wire $1\ldst_port0_ldst_error[0:0] attribute \src "libresoc.v:141096.3-141105.6" wire $1\ldst_port0_mmu_done[0:0] attribute \src "libresoc.v:141022.3-141032.6" wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6119 attribute \src "libresoc.v:141022.3-141032.6" wire $1\ldst_port0_st_data_i_ok$17[0:0]$6120 attribute \src "libresoc.v:140966.7-140966.25" wire $1\reset_delay[0:0] attribute \src "libresoc.v:141161.3-141170.6" wire $1\reset_l_r_reset[0:0] attribute \src "libresoc.v:141146.3-141160.6" wire $1\reset_l_s_reset[0:0] attribute \src "libresoc.v:141081.3-141095.6" wire $2\idx_l$23$next[0:0]$6144 attribute \src "libresoc.v:141146.3-141160.6" wire $2\reset_l_s_reset[0:0] attribute \src "libresoc.v:140977.18-140977.103" wire $not$libresoc.v:140977$6105_Y attribute \src "libresoc.v:140978.18-140978.118" wire $not$libresoc.v:140978$6106_Y attribute \src "libresoc.v:140975.18-140975.134" wire $or$libresoc.v:140975$6103_Y attribute \src "libresoc.v:140976.18-140976.120" wire $ternary$libresoc.v:140976$6104_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 33 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \idx_l_q_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l attribute \src "libresoc.v:140819.7-140819.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 input 6 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 48 output 25 \ldst_port0_addr_i$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 7 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \ldst_port0_addr_i_ok$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire output 16 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire input 27 \ldst_port0_addr_ok_o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire output 2 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire input 23 \ldst_port0_busy_o$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" wire \ldst_port0_cache_paradox attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" wire \ldst_port0_cache_paradox$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 input 5 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 output 24 \ldst_port0_data_len$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 8 \ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 9 \ldst_port0_exc_$signal$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 32 \ldst_port0_exc_$signal$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 10 \ldst_port0_exc_$signal$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 11 \ldst_port0_exc_$signal$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \ldst_port0_exc_$signal$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \ldst_port0_exc_$signal$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \ldst_port0_exc_$signal$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \ldst_port0_exc_$signal$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \ldst_port0_exc_$signal$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \ldst_port0_exc_$signal$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \ldst_port0_exc_$signal$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 12 \ldst_port0_exc_$signal$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 13 \ldst_port0_exc_$signal$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 14 \ldst_port0_exc_$signal$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 15 \ldst_port0_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" wire \ldst_port0_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" wire \ldst_port0_go_die_i$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire input 3 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire output 21 \ldst_port0_is_ld_i$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 4 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire output 22 \ldst_port0_is_st_i$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 17 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 28 \ldst_port0_ld_data_o$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 18 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 29 \ldst_port0_ld_data_o_ok$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" wire \ldst_port0_ldst_error attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" wire \ldst_port0_ldst_error$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" wire \ldst_port0_mmu_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" wire \ldst_port0_mmu_done$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 31 \ldst_port0_st_data_i$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \ldst_port0_st_data_i_ok$17 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire \pick_i attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire \pick_n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire \pick_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" wire \reset_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" wire \reset_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \reset_l_q_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \reset_l_r_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" cell $not $not$libresoc.v:140977$6105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n connect \Y $not$libresoc.v:140977$6105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" cell $not $not$libresoc.v:140978$6106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 connect \Y $not$libresoc.v:140978$6106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" cell $or $or$libresoc.v:140975$6103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i connect \Y $or$libresoc.v:140975$6103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:140976$6104 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l connect \Y $ternary$libresoc.v:140976$6104_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:140983.9-140989.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_idx_l \idx_l_q_idx_l connect \r_idx_l \idx_l_r_idx_l connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 attribute \src "libresoc.v:140990.8-140994.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 attribute \src "libresoc.v:140995.17-141001.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_reset \reset_l_q_reset connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end attribute \src "libresoc.v:140819.7-140819.20" process $proc$libresoc.v:140819$6162 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:140839.7-140839.24" process $proc$libresoc.v:140839$6163 assign { } { } assign $0\idx_l$23[0:0]$6164 1'0 sync always sync init update \idx_l$23 $0\idx_l$23[0:0]$6164 end attribute \src "libresoc.v:140966.7-140966.25" process $proc$libresoc.v:140966$6165 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end attribute \src "libresoc.v:140979.3-140980.36" process $proc$libresoc.v:140979$6107 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end attribute \src "libresoc.v:140981.3-140982.35" process $proc$libresoc.v:140981$6108 assign { } { } assign $0\idx_l$23[0:0]$6109 \idx_l$23$next sync posedge \coresync_clk update \idx_l$23 $0\idx_l$23[0:0]$6109 end attribute \src "libresoc.v:141002.3-141011.6" process $proc$libresoc.v:141002$6110 assign { } { } assign { } { } assign $0\ldst_port0_addr_i$12[47:0]$6111 $1\ldst_port0_addr_i$12[47:0]$6112 attribute \src "libresoc.v:141003.5-141003.29" switch \initial attribute \src "libresoc.v:141003.9-141003.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_addr_i$12[47:0]$6112 \$32 [47:0] case assign $1\ldst_port0_addr_i$12[47:0]$6112 48'000000000000000000000000000000000000000000000000 end sync always update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6111 end attribute \src "libresoc.v:141012.3-141021.6" process $proc$libresoc.v:141012$6113 assign { } { } assign { } { } assign $0\ldst_port0_addr_i_ok$13[0:0]$6114 $1\ldst_port0_addr_i_ok$13[0:0]$6115 attribute \src "libresoc.v:141013.5-141013.29" switch \initial attribute \src "libresoc.v:141013.9-141013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_addr_i_ok$13[0:0]$6115 \ldst_port0_addr_i_ok case assign $1\ldst_port0_addr_i_ok$13[0:0]$6115 1'0 end sync always update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6114 end attribute \src "libresoc.v:141022.3-141032.6" process $proc$libresoc.v:141022$6116 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_st_data_i$18[63:0]$6117 $1\ldst_port0_st_data_i$18[63:0]$6119 assign $0\ldst_port0_st_data_i_ok$17[0:0]$6118 $1\ldst_port0_st_data_i_ok$17[0:0]$6120 attribute \src "libresoc.v:141023.5-141023.29" switch \initial attribute \src "libresoc.v:141023.9-141023.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6120 $1\ldst_port0_st_data_i$18[63:0]$6119 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case assign $1\ldst_port0_st_data_i$18[63:0]$6119 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\ldst_port0_st_data_i_ok$17[0:0]$6120 1'0 end sync always update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6117 update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6118 end attribute \src "libresoc.v:141033.3-141043.6" process $proc$libresoc.v:141033$6121 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] attribute \src "libresoc.v:141034.5-141034.29" switch \initial attribute \src "libresoc.v:141034.9-141034.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } case assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 end sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end attribute \src "libresoc.v:141044.3-141053.6" process $proc$libresoc.v:141044$6122 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] attribute \src "libresoc.v:141045.5-141045.29" switch \initial attribute \src "libresoc.v:141045.9-141045.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 case assign $1\ldst_port0_busy_o[0:0] 1'0 end sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end attribute \src "libresoc.v:141054.3-141063.6" process $proc$libresoc.v:141054$6123 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:141055.5-141055.29" switch \initial attribute \src "libresoc.v:141055.9-141055.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 case assign $1\ldst_port0_addr_ok_o[0:0] 1'0 end sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end attribute \src "libresoc.v:141064.3-141080.6" process $proc$libresoc.v:141064$6124 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_exc_$signal[0:0]$6125 $1\ldst_port0_exc_$signal[0:0]$6133 assign $0\ldst_port0_exc_$signal$1[0:0]$6126 $1\ldst_port0_exc_$signal$1[0:0]$6134 assign $0\ldst_port0_exc_$signal$2[0:0]$6127 $1\ldst_port0_exc_$signal$2[0:0]$6135 assign $0\ldst_port0_exc_$signal$3[0:0]$6128 $1\ldst_port0_exc_$signal$3[0:0]$6136 assign $0\ldst_port0_exc_$signal$4[0:0]$6129 $1\ldst_port0_exc_$signal$4[0:0]$6137 assign $0\ldst_port0_exc_$signal$5[0:0]$6130 $1\ldst_port0_exc_$signal$5[0:0]$6138 assign $0\ldst_port0_exc_$signal$6[0:0]$6131 $1\ldst_port0_exc_$signal$6[0:0]$6139 assign $0\ldst_port0_exc_$signal$7[0:0]$6132 $1\ldst_port0_exc_$signal$7[0:0]$6140 attribute \src "libresoc.v:141065.5-141065.29" switch \initial attribute \src "libresoc.v:141065.9-141065.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\ldst_port0_exc_$signal$7[0:0]$6140 $1\ldst_port0_exc_$signal$6[0:0]$6139 $1\ldst_port0_exc_$signal$5[0:0]$6138 $1\ldst_port0_exc_$signal$4[0:0]$6137 $1\ldst_port0_exc_$signal$3[0:0]$6136 $1\ldst_port0_exc_$signal$2[0:0]$6135 $1\ldst_port0_exc_$signal$1[0:0]$6134 $1\ldst_port0_exc_$signal[0:0]$6133 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case assign $1\ldst_port0_exc_$signal[0:0]$6133 1'0 assign $1\ldst_port0_exc_$signal$1[0:0]$6134 1'0 assign $1\ldst_port0_exc_$signal$2[0:0]$6135 1'0 assign $1\ldst_port0_exc_$signal$3[0:0]$6136 1'0 assign $1\ldst_port0_exc_$signal$4[0:0]$6137 1'0 assign $1\ldst_port0_exc_$signal$5[0:0]$6138 1'0 assign $1\ldst_port0_exc_$signal$6[0:0]$6139 1'0 assign $1\ldst_port0_exc_$signal$7[0:0]$6140 1'0 end sync always update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6125 update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6126 update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6127 update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6128 update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6129 update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6130 update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6131 update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6132 end attribute \src "libresoc.v:141081.3-141095.6" process $proc$libresoc.v:141081$6141 assign { } { } assign { } { } assign { } { } assign $0\idx_l$23$next[0:0]$6142 $2\idx_l$23$next[0:0]$6144 attribute \src "libresoc.v:141082.5-141082.29" switch \initial attribute \src "libresoc.v:141082.9-141082.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\idx_l$23$next[0:0]$6143 \pick_o case assign $1\idx_l$23$next[0:0]$6143 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\idx_l$23$next[0:0]$6144 1'0 case assign $2\idx_l$23$next[0:0]$6144 $1\idx_l$23$next[0:0]$6143 end sync always update \idx_l$23$next $0\idx_l$23$next[0:0]$6142 end attribute \src "libresoc.v:141096.3-141105.6" process $proc$libresoc.v:141096$6145 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] attribute \src "libresoc.v:141097.5-141097.29" switch \initial attribute \src "libresoc.v:141097.9-141097.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 case assign $1\ldst_port0_mmu_done[0:0] 1'0 end sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end attribute \src "libresoc.v:141106.3-141115.6" process $proc$libresoc.v:141106$6146 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] attribute \src "libresoc.v:141107.5-141107.29" switch \initial attribute \src "libresoc.v:141107.9-141107.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 case assign $1\ldst_port0_ldst_error[0:0] 1'0 end sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end attribute \src "libresoc.v:141116.3-141125.6" process $proc$libresoc.v:141116$6147 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] attribute \src "libresoc.v:141117.5-141117.29" switch \initial attribute \src "libresoc.v:141117.9-141117.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 case assign $1\ldst_port0_cache_paradox[0:0] 1'0 end sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end attribute \src "libresoc.v:141126.3-141135.6" process $proc$libresoc.v:141126$6148 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] attribute \src "libresoc.v:141127.5-141127.29" switch \initial attribute \src "libresoc.v:141127.9-141127.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" switch \$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\idx_l_s_idx_l[0:0] 1'1 case assign $1\idx_l_s_idx_l[0:0] 1'0 end sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end attribute \src "libresoc.v:141136.3-141145.6" process $proc$libresoc.v:141136$6149 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] attribute \src "libresoc.v:141137.5-141137.29" switch \initial attribute \src "libresoc.v:141137.9-141137.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\idx_l_r_idx_l[0:0] 1'1 case assign $1\idx_l_r_idx_l[0:0] 1'1 end sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end attribute \src "libresoc.v:141146.3-141160.6" process $proc$libresoc.v:141146$6150 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] attribute \src "libresoc.v:141147.5-141147.29" switch \initial attribute \src "libresoc.v:141147.9-141147.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" switch \$28 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reset_l_s_reset[0:0] 1'1 case assign $2\reset_l_s_reset[0:0] 1'0 end case assign $1\reset_l_s_reset[0:0] 1'0 end sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end attribute \src "libresoc.v:141161.3-141170.6" process $proc$libresoc.v:141161$6151 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] attribute \src "libresoc.v:141162.5-141162.29" switch \initial attribute \src "libresoc.v:141162.9-141162.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reset_l_r_reset[0:0] 1'1 case assign $1\reset_l_r_reset[0:0] 1'0 end sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end attribute \src "libresoc.v:141171.3-141180.6" process $proc$libresoc.v:141171$6152 assign { } { } assign { } { } assign $0\ldst_port0_is_ld_i$8[0:0]$6153 $1\ldst_port0_is_ld_i$8[0:0]$6154 attribute \src "libresoc.v:141172.5-141172.29" switch \initial attribute \src "libresoc.v:141172.9-141172.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_is_ld_i$8[0:0]$6154 \ldst_port0_is_ld_i case assign $1\ldst_port0_is_ld_i$8[0:0]$6154 1'0 end sync always update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6153 end attribute \src "libresoc.v:141181.3-141190.6" process $proc$libresoc.v:141181$6155 assign { } { } assign { } { } assign $0\ldst_port0_is_st_i$9[0:0]$6156 $1\ldst_port0_is_st_i$9[0:0]$6157 attribute \src "libresoc.v:141182.5-141182.29" switch \initial attribute \src "libresoc.v:141182.9-141182.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_is_st_i$9[0:0]$6157 \ldst_port0_is_st_i case assign $1\ldst_port0_is_st_i$9[0:0]$6157 1'0 end sync always update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6156 end attribute \src "libresoc.v:141191.3-141200.6" process $proc$libresoc.v:141191$6158 assign { } { } assign { } { } assign $0\ldst_port0_data_len$11[3:0]$6159 $1\ldst_port0_data_len$11[3:0]$6160 attribute \src "libresoc.v:141192.5-141192.29" switch \initial attribute \src "libresoc.v:141192.9-141192.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_data_len$11[3:0]$6160 \ldst_port0_data_len case assign $1\ldst_port0_data_len$11[3:0]$6160 4'0000 end sync always update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6159 end attribute \src "libresoc.v:141201.3-141210.6" process $proc$libresoc.v:141201$6161 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] attribute \src "libresoc.v:141202.5-141202.29" switch \initial attribute \src "libresoc.v:141202.9-141202.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 case assign $1\ldst_port0_go_die_i[0:0] 1'0 end sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end connect \$20 $or$libresoc.v:140975$6103_Y connect \$24 $ternary$libresoc.v:140976$6104_Y connect \$26 $not$libresoc.v:140977$6105_Y connect \$28 $not$libresoc.v:140978$6106_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 connect \ldst_port0_exc_$signal$33 1'0 connect \ldst_port0_exc_$signal$34 1'0 connect \ldst_port0_exc_$signal$35 1'0 connect \ldst_port0_exc_$signal$36 1'0 connect \ldst_port0_exc_$signal$37 1'0 connect \ldst_port0_exc_$signal$38 1'0 connect \ldst_port0_exc_$signal$39 1'0 connect \ldst_port0_mmu_done$40 1'0 connect \ldst_port0_ldst_error$41 1'0 connect \ldst_port0_cache_paradox$42 1'0 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end attribute \src "libresoc.v:141230.1-141288.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active attribute \src "libresoc.v:141231.7-141231.20" wire $0\initial[0:0] attribute \src "libresoc.v:141276.3-141284.6" wire $0\q_int$next[0:0]$6176 attribute \src "libresoc.v:141274.3-141275.27" wire $0\q_int[0:0] attribute \src "libresoc.v:141276.3-141284.6" wire $1\q_int$next[0:0]$6177 attribute \src "libresoc.v:141253.7-141253.19" wire $1\q_int[0:0] attribute \src "libresoc.v:141266.17-141266.96" wire $and$libresoc.v:141266$6166_Y attribute \src "libresoc.v:141271.17-141271.96" wire $and$libresoc.v:141271$6171_Y attribute \src "libresoc.v:141268.18-141268.99" wire $not$libresoc.v:141268$6168_Y attribute \src "libresoc.v:141270.17-141270.98" wire $not$libresoc.v:141270$6170_Y attribute \src "libresoc.v:141273.17-141273.98" wire $not$libresoc.v:141273$6173_Y attribute \src "libresoc.v:141267.18-141267.104" wire $or$libresoc.v:141267$6167_Y attribute \src "libresoc.v:141269.18-141269.105" wire $or$libresoc.v:141269$6169_Y attribute \src "libresoc.v:141272.17-141272.103" wire $or$libresoc.v:141272$6172_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:141231.7-141231.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 2 \r_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:141266$6166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:141266$6166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:141271$6171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:141271$6171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:141268$6168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active connect \Y $not$libresoc.v:141268$6168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:141270$6170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active connect \Y $not$libresoc.v:141270$6170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:141273$6173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active connect \Y $not$libresoc.v:141273$6173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:141267$6167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active connect \Y $or$libresoc.v:141267$6167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:141269$6169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int connect \Y $or$libresoc.v:141269$6169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:141272$6172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active connect \Y $or$libresoc.v:141272$6172_Y end attribute \src "libresoc.v:141231.7-141231.20" process $proc$libresoc.v:141231$6178 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:141253.7-141253.19" process $proc$libresoc.v:141253$6179 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:141274.3-141275.27" process $proc$libresoc.v:141274$6174 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:141276.3-141284.6" process $proc$libresoc.v:141276$6175 assign { } { } assign { } { } assign $0\q_int$next[0:0]$6176 $1\q_int$next[0:0]$6177 attribute \src "libresoc.v:141277.5-141277.29" switch \initial attribute \src "libresoc.v:141277.9-141277.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$6177 1'0 case assign $1\q_int$next[0:0]$6177 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$6176 end connect \$9 $and$libresoc.v:141266$6166_Y connect \$11 $or$libresoc.v:141267$6167_Y connect \$13 $not$libresoc.v:141268$6168_Y connect \$15 $or$libresoc.v:141269$6169_Y connect \$1 $not$libresoc.v:141270$6170_Y connect \$3 $and$libresoc.v:141271$6171_Y connect \$5 $or$libresoc.v:141272$6172_Y connect \$7 $not$libresoc.v:141273$6173_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end attribute \src "libresoc.v:141292.1-142655.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 attribute \src "libresoc.v:142310.3-142318.6" wire $0\adr_l_r_adr$next[0:0]$6322 attribute \src "libresoc.v:142192.3-142193.39" wire $0\adr_l_r_adr[0:0] attribute \src "libresoc.v:142138.3-142139.21" wire $0\alu_ok[0:0] attribute \src "libresoc.v:142475.3-142484.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:142485.3-142494.6" wire width 64 $0\dest2_o[63:0] attribute \src "libresoc.v:142465.3-142474.6" wire width 64 $0\ea_r$next[63:0]$6410 attribute \src "libresoc.v:142140.3-142141.25" wire width 64 $0\ea_r[63:0] attribute \src "libresoc.v:141293.7-141293.20" wire $0\initial[0:0] attribute \src "libresoc.v:142540.3-142559.6" wire width 64 $0\ldd_o[63:0] attribute \src "libresoc.v:142504.3-142527.6" wire width 64 $0\lddata_r[63:0] attribute \src "libresoc.v:142407.3-142416.6" wire width 64 $0\ldo_r$next[63:0]$6395 attribute \src "libresoc.v:142148.3-142149.27" wire width 64 $0\ldo_r[63:0] attribute \src "libresoc.v:142136.3-142137.33" wire width 96 $0\ldst_port0_addr_i[95:0] attribute \src "libresoc.v:142495.3-142503.6" wire $0\ldst_port0_addr_i_ok$next[0:0]$6415 attribute \src "libresoc.v:142134.3-142135.57" wire $0\ldst_port0_addr_i_ok[0:0] attribute \src "libresoc.v:142584.3-142595.6" wire width 64 $0\ldst_port0_st_data_i[63:0] attribute \src "libresoc.v:142355.3-142363.6" wire $0\lsd_l_r_lsd$next[0:0]$6337 attribute \src "libresoc.v:142182.3-142183.39" wire $0\lsd_l_r_lsd[0:0] attribute \src "libresoc.v:142283.3-142291.6" wire $0\opc_l_r_opc$next[0:0]$6313 attribute \src "libresoc.v:142198.3-142199.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:142274.3-142282.6" wire $0\opc_l_s_opc$next[0:0]$6310 attribute \src "libresoc.v:142200.3-142201.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__byte_reverse$next[0:0]$6340 attribute \src "libresoc.v:142174.3-142175.57" wire $0\oper_r__byte_reverse[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 4 $0\oper_r__data_len$next[3:0]$6341 attribute \src "libresoc.v:142172.3-142173.49" wire width 4 $0\oper_r__data_len[3:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 14 $0\oper_r__fn_unit$next[13:0]$6342 attribute \src "libresoc.v:142152.3-142153.47" wire width 14 $0\oper_r__fn_unit[13:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $0\oper_r__imm_data__data$next[63:0]$6343 attribute \src "libresoc.v:142154.3-142155.61" wire width 64 $0\oper_r__imm_data__data[63:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__imm_data__ok$next[0:0]$6344 attribute \src "libresoc.v:142156.3-142157.57" wire $0\oper_r__imm_data__ok[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 32 $0\oper_r__insn$next[31:0]$6345 attribute \src "libresoc.v:142180.3-142181.41" wire width 32 $0\oper_r__insn[31:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 7 $0\oper_r__insn_type$next[6:0]$6346 attribute \src "libresoc.v:142150.3-142151.51" wire width 7 $0\oper_r__insn_type[6:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__is_32bit$next[0:0]$6347 attribute \src "libresoc.v:142168.3-142169.49" wire $0\oper_r__is_32bit[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__is_signed$next[0:0]$6348 attribute \src "libresoc.v:142170.3-142171.51" wire $0\oper_r__is_signed[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 2 $0\oper_r__ldst_mode$next[1:0]$6349 attribute \src "libresoc.v:142178.3-142179.51" wire width 2 $0\oper_r__ldst_mode[1:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__oe__oe$next[0:0]$6350 attribute \src "libresoc.v:142164.3-142165.45" wire $0\oper_r__oe__oe[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__oe__ok$next[0:0]$6351 attribute \src "libresoc.v:142166.3-142167.45" wire $0\oper_r__oe__ok[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__rc__ok$next[0:0]$6352 attribute \src "libresoc.v:142162.3-142163.45" wire $0\oper_r__rc__ok[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__rc__rc$next[0:0]$6353 attribute \src "libresoc.v:142160.3-142161.45" wire $0\oper_r__rc__rc[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__sign_extend$next[0:0]$6354 attribute \src "libresoc.v:142176.3-142177.55" wire $0\oper_r__sign_extend[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $0\oper_r__zero_a$next[0:0]$6355 attribute \src "libresoc.v:142158.3-142159.45" wire $0\oper_r__zero_a[0:0] attribute \src "libresoc.v:142202.3-142203.28" wire $0\p_st_go[0:0] attribute \src "libresoc.v:142528.3-142539.6" wire width 64 $0\revnorev[63:0] attribute \src "libresoc.v:142301.3-142309.6" wire width 3 $0\src_l_r_src$next[2:0]$6319 attribute \src "libresoc.v:142194.3-142195.39" wire width 3 $0\src_l_r_src[2:0] attribute \src "libresoc.v:142292.3-142300.6" wire width 3 $0\src_l_s_src$next[2:0]$6316 attribute \src "libresoc.v:142196.3-142197.39" wire width 3 $0\src_l_s_src[2:0] attribute \src "libresoc.v:142417.3-142432.6" wire width 64 $0\src_r0$next[63:0]$6398 attribute \src "libresoc.v:142146.3-142147.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:142433.3-142448.6" wire width 64 $0\src_r1$next[63:0]$6402 attribute \src "libresoc.v:142144.3-142145.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:142449.3-142464.6" wire width 64 $0\src_r2$next[63:0]$6406 attribute \src "libresoc.v:142142.3-142143.29" wire width 64 $0\src_r2[63:0] attribute \src "libresoc.v:142560.3-142583.6" wire width 64 $0\stdata_r[63:0] attribute \src "libresoc.v:142346.3-142354.6" wire $0\sto_l_r_sto$next[0:0]$6334 attribute \src "libresoc.v:142184.3-142185.39" wire $0\sto_l_r_sto[0:0] attribute \src "libresoc.v:142337.3-142345.6" wire $0\upd_l_r_upd$next[0:0]$6331 attribute \src "libresoc.v:142186.3-142187.39" wire $0\upd_l_r_upd[0:0] attribute \src "libresoc.v:142328.3-142336.6" wire $0\upd_l_s_upd$next[0:0]$6328 attribute \src "libresoc.v:142188.3-142189.39" wire $0\upd_l_s_upd[0:0] attribute \src "libresoc.v:142319.3-142327.6" wire $0\wri_l_r_wri$next[0:0]$6325 attribute \src "libresoc.v:142190.3-142191.39" wire $0\wri_l_r_wri[0:0] attribute \src "libresoc.v:142310.3-142318.6" wire $1\adr_l_r_adr$next[0:0]$6323 attribute \src "libresoc.v:141489.7-141489.25" wire $1\adr_l_r_adr[0:0] attribute \src "libresoc.v:141503.7-141503.20" wire $1\alu_ok[0:0] attribute \src "libresoc.v:142475.3-142484.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:142485.3-142494.6" wire width 64 $1\dest2_o[63:0] attribute \src "libresoc.v:142465.3-142474.6" wire width 64 $1\ea_r$next[63:0]$6411 attribute \src "libresoc.v:141549.14-141549.41" wire width 64 $1\ea_r[63:0] attribute \src "libresoc.v:142540.3-142559.6" wire width 64 $1\ldd_o[63:0] attribute \src "libresoc.v:142504.3-142527.6" wire width 64 $1\lddata_r[63:0] attribute \src "libresoc.v:142407.3-142416.6" wire width 64 $1\ldo_r$next[63:0]$6396 attribute \src "libresoc.v:141579.14-141579.42" wire width 64 $1\ldo_r[63:0] attribute \src "libresoc.v:141584.14-141584.62" wire width 96 $1\ldst_port0_addr_i[95:0] attribute \src "libresoc.v:142495.3-142503.6" wire $1\ldst_port0_addr_i_ok$next[0:0]$6416 attribute \src "libresoc.v:141589.7-141589.34" wire $1\ldst_port0_addr_i_ok[0:0] attribute \src "libresoc.v:142584.3-142595.6" wire width 64 $1\ldst_port0_st_data_i[63:0] attribute \src "libresoc.v:142355.3-142363.6" wire $1\lsd_l_r_lsd$next[0:0]$6338 attribute \src "libresoc.v:141638.7-141638.25" wire $1\lsd_l_r_lsd[0:0] attribute \src "libresoc.v:142283.3-142291.6" wire $1\opc_l_r_opc$next[0:0]$6314 attribute \src "libresoc.v:141652.7-141652.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:142274.3-142282.6" wire $1\opc_l_s_opc$next[0:0]$6311 attribute \src "libresoc.v:141656.7-141656.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__byte_reverse$next[0:0]$6356 attribute \src "libresoc.v:141787.7-141787.34" wire $1\oper_r__byte_reverse[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 4 $1\oper_r__data_len$next[3:0]$6357 attribute \src "libresoc.v:141791.13-141791.36" wire width 4 $1\oper_r__data_len[3:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 14 $1\oper_r__fn_unit$next[13:0]$6358 attribute \src "libresoc.v:141810.14-141810.40" wire width 14 $1\oper_r__fn_unit[13:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $1\oper_r__imm_data__data$next[63:0]$6359 attribute \src "libresoc.v:141814.14-141814.59" wire width 64 $1\oper_r__imm_data__data[63:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__imm_data__ok$next[0:0]$6360 attribute \src "libresoc.v:141818.7-141818.34" wire $1\oper_r__imm_data__ok[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 32 $1\oper_r__insn$next[31:0]$6361 attribute \src "libresoc.v:141822.14-141822.34" wire width 32 $1\oper_r__insn[31:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 7 $1\oper_r__insn_type$next[6:0]$6362 attribute \src "libresoc.v:141901.13-141901.38" wire width 7 $1\oper_r__insn_type[6:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__is_32bit$next[0:0]$6363 attribute \src "libresoc.v:141905.7-141905.30" wire $1\oper_r__is_32bit[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__is_signed$next[0:0]$6364 attribute \src "libresoc.v:141909.7-141909.31" wire $1\oper_r__is_signed[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 2 $1\oper_r__ldst_mode$next[1:0]$6365 attribute \src "libresoc.v:141918.13-141918.37" wire width 2 $1\oper_r__ldst_mode[1:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__oe__oe$next[0:0]$6366 attribute \src "libresoc.v:141922.7-141922.28" wire $1\oper_r__oe__oe[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__oe__ok$next[0:0]$6367 attribute \src "libresoc.v:141926.7-141926.28" wire $1\oper_r__oe__ok[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__rc__ok$next[0:0]$6368 attribute \src "libresoc.v:141930.7-141930.28" wire $1\oper_r__rc__ok[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__rc__rc$next[0:0]$6369 attribute \src "libresoc.v:141934.7-141934.28" wire $1\oper_r__rc__rc[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__sign_extend$next[0:0]$6370 attribute \src "libresoc.v:141938.7-141938.33" wire $1\oper_r__sign_extend[0:0] attribute \src "libresoc.v:142364.3-142406.6" wire $1\oper_r__zero_a$next[0:0]$6371 attribute \src "libresoc.v:141942.7-141942.28" wire $1\oper_r__zero_a[0:0] attribute \src "libresoc.v:141946.7-141946.21" wire $1\p_st_go[0:0] attribute \src "libresoc.v:142528.3-142539.6" wire width 64 $1\revnorev[63:0] attribute \src "libresoc.v:142301.3-142309.6" wire width 3 $1\src_l_r_src$next[2:0]$6320 attribute \src "libresoc.v:141988.13-141988.31" wire width 3 $1\src_l_r_src[2:0] attribute \src "libresoc.v:142292.3-142300.6" wire width 3 $1\src_l_s_src$next[2:0]$6317 attribute \src "libresoc.v:141992.13-141992.31" wire width 3 $1\src_l_s_src[2:0] attribute \src "libresoc.v:142417.3-142432.6" wire width 64 $1\src_r0$next[63:0]$6399 attribute \src "libresoc.v:141996.14-141996.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:142433.3-142448.6" wire width 64 $1\src_r1$next[63:0]$6403 attribute \src "libresoc.v:142000.14-142000.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:142449.3-142464.6" wire width 64 $1\src_r2$next[63:0]$6407 attribute \src "libresoc.v:142004.14-142004.43" wire width 64 $1\src_r2[63:0] attribute \src "libresoc.v:142560.3-142583.6" wire width 64 $1\stdata_r[63:0] attribute \src "libresoc.v:142346.3-142354.6" wire $1\sto_l_r_sto$next[0:0]$6335 attribute \src "libresoc.v:142014.7-142014.25" wire $1\sto_l_r_sto[0:0] attribute \src "libresoc.v:142337.3-142345.6" wire $1\upd_l_r_upd$next[0:0]$6332 attribute \src "libresoc.v:142024.7-142024.25" wire $1\upd_l_r_upd[0:0] attribute \src "libresoc.v:142328.3-142336.6" wire $1\upd_l_s_upd$next[0:0]$6329 attribute \src "libresoc.v:142028.7-142028.25" wire $1\upd_l_s_upd[0:0] attribute \src "libresoc.v:142319.3-142327.6" wire $1\wri_l_r_wri$next[0:0]$6326 attribute \src "libresoc.v:142038.7-142038.25" wire $1\wri_l_r_wri[0:0] attribute \src "libresoc.v:142540.3-142559.6" wire width 64 $2\ldd_o[63:0] attribute \src "libresoc.v:142504.3-142527.6" wire width 64 $2\lddata_r[63:0] attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__byte_reverse$next[0:0]$6372 attribute \src "libresoc.v:142364.3-142406.6" wire width 4 $2\oper_r__data_len$next[3:0]$6373 attribute \src "libresoc.v:142364.3-142406.6" wire width 14 $2\oper_r__fn_unit$next[13:0]$6374 attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $2\oper_r__imm_data__data$next[63:0]$6375 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__imm_data__ok$next[0:0]$6376 attribute \src "libresoc.v:142364.3-142406.6" wire width 32 $2\oper_r__insn$next[31:0]$6377 attribute \src "libresoc.v:142364.3-142406.6" wire width 7 $2\oper_r__insn_type$next[6:0]$6378 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__is_32bit$next[0:0]$6379 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__is_signed$next[0:0]$6380 attribute \src "libresoc.v:142364.3-142406.6" wire width 2 $2\oper_r__ldst_mode$next[1:0]$6381 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__oe__oe$next[0:0]$6382 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__oe__ok$next[0:0]$6383 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__rc__ok$next[0:0]$6384 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__rc__rc$next[0:0]$6385 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__sign_extend$next[0:0]$6386 attribute \src "libresoc.v:142364.3-142406.6" wire $2\oper_r__zero_a$next[0:0]$6387 attribute \src "libresoc.v:142417.3-142432.6" wire width 64 $2\src_r0$next[63:0]$6400 attribute \src "libresoc.v:142433.3-142448.6" wire width 64 $2\src_r1$next[63:0]$6404 attribute \src "libresoc.v:142449.3-142464.6" wire width 64 $2\src_r2$next[63:0]$6408 attribute \src "libresoc.v:142560.3-142583.6" wire width 64 $2\stdata_r[63:0] attribute \src "libresoc.v:142364.3-142406.6" wire width 64 $3\oper_r__imm_data__data$next[63:0]$6388 attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__imm_data__ok$next[0:0]$6389 attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__oe__oe$next[0:0]$6390 attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__oe__ok$next[0:0]$6391 attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__rc__ok$next[0:0]$6392 attribute \src "libresoc.v:142364.3-142406.6" wire $3\oper_r__rc__rc$next[0:0]$6393 attribute \src "libresoc.v:142120.18-142120.124" wire width 65 $add$libresoc.v:142120$6260_Y attribute \src "libresoc.v:142043.19-142043.118" wire $and$libresoc.v:142043$6180_Y attribute \src "libresoc.v:142044.19-142044.125" wire $and$libresoc.v:142044$6181_Y attribute \src "libresoc.v:142045.19-142045.120" wire $and$libresoc.v:142045$6182_Y attribute \src "libresoc.v:142046.19-142046.125" wire $and$libresoc.v:142046$6183_Y attribute \src "libresoc.v:142047.19-142047.118" wire $and$libresoc.v:142047$6184_Y attribute \src "libresoc.v:142049.19-142049.119" wire $and$libresoc.v:142049$6186_Y attribute \src "libresoc.v:142050.19-142050.123" wire $and$libresoc.v:142050$6187_Y attribute \src "libresoc.v:142051.19-142051.123" wire $and$libresoc.v:142051$6188_Y attribute \src "libresoc.v:142052.19-142052.120" wire $and$libresoc.v:142052$6189_Y attribute \src "libresoc.v:142053.19-142053.123" wire $and$libresoc.v:142053$6190_Y attribute \src "libresoc.v:142054.19-142054.119" wire $and$libresoc.v:142054$6191_Y attribute \src "libresoc.v:142055.19-142055.123" wire $and$libresoc.v:142055$6192_Y attribute \src "libresoc.v:142056.19-142056.125" wire $and$libresoc.v:142056$6193_Y attribute \src "libresoc.v:142058.19-142058.116" wire $and$libresoc.v:142058$6195_Y attribute \src "libresoc.v:142060.19-142060.120" wire $and$libresoc.v:142060$6197_Y attribute \src "libresoc.v:142061.19-142061.123" wire $and$libresoc.v:142061$6198_Y attribute \src "libresoc.v:142065.19-142065.125" wire $and$libresoc.v:142065$6202_Y attribute \src "libresoc.v:142066.19-142066.123" wire $and$libresoc.v:142066$6203_Y attribute \src "libresoc.v:142071.19-142071.116" wire $and$libresoc.v:142071$6208_Y attribute \src "libresoc.v:142073.19-142073.116" wire $and$libresoc.v:142073$6210_Y attribute \src "libresoc.v:142076.19-142076.118" wire $and$libresoc.v:142076$6213_Y attribute \src "libresoc.v:142078.19-142078.125" wire $and$libresoc.v:142078$6215_Y attribute \src "libresoc.v:142081.19-142081.160" wire width 3 $and$libresoc.v:142081$6218_Y attribute \src "libresoc.v:142082.19-142082.122" wire $and$libresoc.v:142082$6219_Y attribute \src "libresoc.v:142083.19-142083.122" wire $and$libresoc.v:142083$6220_Y attribute \src "libresoc.v:142085.19-142085.122" wire $and$libresoc.v:142085$6223_Y attribute \src "libresoc.v:142097.18-142097.123" wire $and$libresoc.v:142097$6237_Y attribute \src "libresoc.v:142098.18-142098.123" wire $and$libresoc.v:142098$6238_Y attribute \src "libresoc.v:142100.18-142100.114" wire $and$libresoc.v:142100$6240_Y attribute \src "libresoc.v:142102.18-142102.113" wire $and$libresoc.v:142102$6242_Y attribute \src "libresoc.v:142105.18-142105.113" wire $and$libresoc.v:142105$6245_Y attribute \src "libresoc.v:142109.18-142109.113" wire $and$libresoc.v:142109$6249_Y attribute \src "libresoc.v:142112.18-142112.119" wire $and$libresoc.v:142112$6252_Y attribute \src "libresoc.v:142121.18-142121.150" wire width 3 $and$libresoc.v:142121$6261_Y attribute \src "libresoc.v:142123.18-142123.113" wire width 3 $and$libresoc.v:142123$6263_Y attribute \src "libresoc.v:142125.18-142125.113" wire width 3 $and$libresoc.v:142125$6265_Y attribute \src "libresoc.v:142126.18-142126.127" wire $and$libresoc.v:142126$6266_Y attribute \src "libresoc.v:142127.18-142127.117" wire $and$libresoc.v:142127$6267_Y attribute \src "libresoc.v:142132.18-142132.117" wire $and$libresoc.v:142132$6272_Y attribute \src "libresoc.v:142057.19-142057.127" wire $eq$libresoc.v:142057$6194_Y attribute \src "libresoc.v:142077.19-142077.127" wire $eq$libresoc.v:142077$6214_Y attribute \src "libresoc.v:142079.19-142079.127" wire $eq$libresoc.v:142079$6216_Y attribute \src "libresoc.v:142090.19-142090.126" wire $eq$libresoc.v:142090$6229_Y attribute \src "libresoc.v:142095.18-142095.127" wire $eq$libresoc.v:142095$6235_Y attribute \src "libresoc.v:142096.18-142096.127" wire $eq$libresoc.v:142096$6236_Y attribute \src "libresoc.v:142104.18-142104.126" wire $eq$libresoc.v:142104$6244_Y attribute \src "libresoc.v:142108.18-142108.126" wire $eq$libresoc.v:142108$6248_Y attribute \src "libresoc.v:142084.19-142084.110" wire width 96 $extend$libresoc.v:142084$6221_Y attribute \src "libresoc.v:142086.19-142086.116" wire width 64 $extend$libresoc.v:142086$6224_Y attribute \src "libresoc.v:142091.19-142091.102" wire width 64 $extend$libresoc.v:142091$6230_Y attribute \src "libresoc.v:142069.19-142069.109" wire $not$libresoc.v:142069$6206_Y attribute \src "libresoc.v:142074.19-142074.121" wire $not$libresoc.v:142074$6211_Y attribute \src "libresoc.v:142099.18-142099.112" wire $not$libresoc.v:142099$6239_Y attribute \src "libresoc.v:142101.18-142101.110" wire $not$libresoc.v:142101$6241_Y attribute \src "libresoc.v:142103.18-142103.120" wire $not$libresoc.v:142103$6243_Y attribute \src "libresoc.v:142107.18-142107.120" wire $not$libresoc.v:142107$6247_Y attribute \src "libresoc.v:142122.18-142122.143" wire width 2 $not$libresoc.v:142122$6262_Y attribute \src "libresoc.v:142124.18-142124.115" wire width 3 $not$libresoc.v:142124$6264_Y attribute \src "libresoc.v:142131.18-142131.107" wire $not$libresoc.v:142131$6271_Y attribute \src "libresoc.v:142133.18-142133.118" wire $not$libresoc.v:142133$6273_Y attribute \src "libresoc.v:142048.18-142048.124" wire $or$libresoc.v:142048$6185_Y attribute \src "libresoc.v:142059.18-142059.129" wire $or$libresoc.v:142059$6196_Y attribute \src "libresoc.v:142062.19-142062.123" wire $or$libresoc.v:142062$6199_Y attribute \src "libresoc.v:142063.19-142063.125" wire $or$libresoc.v:142063$6200_Y attribute \src "libresoc.v:142064.19-142064.125" wire $or$libresoc.v:142064$6201_Y attribute \src "libresoc.v:142067.19-142067.132" wire $or$libresoc.v:142067$6204_Y attribute \src "libresoc.v:142068.19-142068.126" wire $or$libresoc.v:142068$6205_Y attribute \src "libresoc.v:142070.18-142070.129" wire $or$libresoc.v:142070$6207_Y attribute \src "libresoc.v:142072.19-142072.125" wire $or$libresoc.v:142072$6209_Y attribute \src "libresoc.v:142075.19-142075.119" wire $or$libresoc.v:142075$6212_Y attribute \src "libresoc.v:142080.18-142080.126" wire $or$libresoc.v:142080$6217_Y attribute \src "libresoc.v:142088.18-142088.156" wire width 3 $or$libresoc.v:142088$6227_Y attribute \src "libresoc.v:142094.18-142094.126" wire $or$libresoc.v:142094$6234_Y attribute \src "libresoc.v:142106.18-142106.116" wire $or$libresoc.v:142106$6246_Y attribute \src "libresoc.v:142110.18-142110.116" wire $or$libresoc.v:142110$6250_Y attribute \src "libresoc.v:142111.18-142111.127" wire width 2 $or$libresoc.v:142111$6251_Y attribute \src "libresoc.v:142113.18-142113.118" wire $or$libresoc.v:142113$6253_Y attribute \src "libresoc.v:142114.18-142114.118" wire $or$libresoc.v:142114$6254_Y attribute \src "libresoc.v:142115.18-142115.114" wire $or$libresoc.v:142115$6255_Y attribute \src "libresoc.v:142128.17-142128.124" wire $or$libresoc.v:142128$6268_Y attribute \src "libresoc.v:142129.18-142129.132" wire $or$libresoc.v:142129$6269_Y attribute \src "libresoc.v:142130.18-142130.134" wire $or$libresoc.v:142130$6270_Y attribute \src "libresoc.v:142084.19-142084.110" wire width 96 $pos$libresoc.v:142084$6222_Y attribute \src "libresoc.v:142086.19-142086.116" wire width 64 $pos$libresoc.v:142086$6225_Y attribute \src "libresoc.v:142087.19-142087.148" wire width 64 $pos$libresoc.v:142087$6226_Y attribute \src "libresoc.v:142089.19-142089.206" wire width 64 $pos$libresoc.v:142089$6228_Y attribute \src "libresoc.v:142091.19-142091.102" wire width 64 $pos$libresoc.v:142091$6231_Y attribute \src "libresoc.v:142092.19-142092.120" wire width 64 $pos$libresoc.v:142092$6232_Y attribute \src "libresoc.v:142093.19-142093.150" wire width 64 $pos$libresoc.v:142093$6233_Y attribute \src "libresoc.v:142116.18-142116.107" wire width 64 $ternary$libresoc.v:142116$6256_Y attribute \src "libresoc.v:142117.18-142117.112" wire width 64 $ternary$libresoc.v:142117$6257_Y attribute \src "libresoc.v:142118.18-142118.147" wire width 64 $ternary$libresoc.v:142118$6258_Y attribute \src "libresoc.v:142119.18-142119.155" wire width 64 $ternary$libresoc.v:142119$6259_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" wire \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" wire \$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" wire \$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" wire \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" wire \$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" wire \$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" wire \$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" wire \$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" wire \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" wire \$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" wire \$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" wire \$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" wire \$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" wire \$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" wire \$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" wire \$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" wire \$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" wire \$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" wire \$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" wire \$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" wire \$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" wire \$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" wire \$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" wire \$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" wire \$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" wire \$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" wire \$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" wire \$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" wire \$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" wire \$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" wire \$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" wire width 3 \$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" wire \$167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" wire width 3 \$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" wire \$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" wire \$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" wire width 96 \$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" wire \$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" wire width 3 \$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$186 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" wire \$192 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$194 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$196 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" wire width 64 \$198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" wire width 2 \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" wire width 2 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" wire \$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" wire width 64 \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" wire width 64 \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" wire width 65 \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" wire width 65 \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" wire width 3 \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" wire width 2 \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" wire width 3 \$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" wire width 3 \$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" wire width 3 \$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" wire \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" wire \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" wire \$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" wire \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" wire \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" wire \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" wire \addr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" wire width 64 \addr_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \adr_l_q_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \adr_l_r_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \adr_l_r_adr$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \adr_l_s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" wire width 64 \alu_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" wire \alu_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 53 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 4 \cu_ad__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 23 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 22 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 26 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 25 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 24 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 5 \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 2 \cu_st__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 input 31 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 output 30 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 2 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 33 \ea attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ea_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ea_r$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 attribute \src "libresoc.v:141293.7-141293.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" wire \ld_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" wire width 64 \ldd_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" wire width 64 \ldd_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" wire width 64 \lddata_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ldo_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \ldo_r$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 output 38 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 96 \ldst_port0_addr_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \ldst_port0_addr_i_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire input 48 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire input 34 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 output 37 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 40 \ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 41 \ldst_port0_exc_$signal$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 42 \ldst_port0_exc_$signal$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 43 \ldst_port0_exc_$signal$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 44 \ldst_port0_exc_$signal$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 45 \ldst_port0_exc_$signal$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 46 \ldst_port0_exc_$signal$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 47 \ldst_port0_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire output 35 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire output 36 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 49 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 50 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 51 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 52 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" wire \load_mem_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \lod_l_qn_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \lod_l_r_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \lod_l_s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \lsd_l_q_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \lsd_l_r_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \lsd_l_r_lsd$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \lsd_l_s_lsd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 32 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" wire \op_is_ld attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" wire \op_is_st attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 7 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_ldst_ldst0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 21 \oper_i_ldst_ldst0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \oper_i_ldst_ldst0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \oper_i_ldst_ldst0__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 20 \oper_i_ldst_ldst0__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \oper_i_ldst_ldst0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \oper_i_ldst_ldst0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \oper_i_ldst_ldst0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \oper_i_ldst_ldst0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \oper_i_ldst_ldst0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__byte_reverse$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \oper_r__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \oper_r__data_len$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \oper_r__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \oper_r__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \oper_r__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \oper_r__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \oper_r__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \oper_r__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \oper_r__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \oper_r__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__is_signed$next attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \oper_r__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \oper_r__ldst_mode$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__sign_extend$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__zero_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" wire \p_st_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" wire \p_st_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" wire \rd_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" wire \rda_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" wire \reset_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" wire \reset_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" wire \reset_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" wire \reset_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" wire \reset_u attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" wire \reset_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" wire width 64 \revnorev attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rst_l_q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 29 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" wire width 64 \src1_or_z attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 27 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" wire width 64 \src2_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 28 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" wire \st_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" wire width 64 \stdata_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \sto_l_q_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \sto_l_r_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \sto_l_r_sto$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \sto_l_s_sto attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" wire \stwd_mem_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \upd_l_q_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \upd_l_r_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \upd_l_r_upd$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \upd_l_s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \upd_l_s_upd$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" wire \wr_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \wri_l_q_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \wri_l_r_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \wri_l_r_wri$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" cell $add $add$libresoc.v:142120$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm connect \Y $add$libresoc.v:142120$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" cell $and $and$libresoc.v:142043$6180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 connect \Y $and$libresoc.v:142043$6180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" cell $and $and$libresoc.v:142044$6181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr connect \Y $and$libresoc.v:142044$6181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" cell $and $and$libresoc.v:142045$6182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o connect \Y $and$libresoc.v:142045$6182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" cell $and $and$libresoc.v:142046$6183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o connect \Y $and$libresoc.v:142046$6183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" cell $and $and$libresoc.v:142047$6184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done connect \Y $and$libresoc.v:142047$6184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" cell $and $and$libresoc.v:142049$6186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st connect \Y $and$libresoc.v:142049$6186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" cell $and $and$libresoc.v:142050$6187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i connect \Y $and$libresoc.v:142050$6187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" cell $and $and$libresoc.v:142051$6188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri connect \Y $and$libresoc.v:142051$6188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" cell $and $and$libresoc.v:142052$6189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o connect \Y $and$libresoc.v:142052$6189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" cell $and $and$libresoc.v:142053$6190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod connect \Y $and$libresoc.v:142053$6190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" cell $and $and$libresoc.v:142054$6191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld connect \Y $and$libresoc.v:142054$6191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" cell $and $and$libresoc.v:142055$6192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i connect \Y $and$libresoc.v:142055$6192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" cell $and $and$libresoc.v:142056$6193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o connect \Y $and$libresoc.v:142056$6193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" cell $and $and$libresoc.v:142058$6195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 connect \Y $and$libresoc.v:142058$6195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" cell $and $and$libresoc.v:142060$6197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid connect \Y $and$libresoc.v:142060$6197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" cell $and $and$libresoc.v:142061$6198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i connect \Y $and$libresoc.v:142061$6198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" cell $and $and$libresoc.v:142065$6202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o connect \Y $and$libresoc.v:142065$6202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" cell $and $and$libresoc.v:142066$6203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i connect \Y $and$libresoc.v:142066$6203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" cell $and $and$libresoc.v:142071$6208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 connect \Y $and$libresoc.v:142071$6208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" cell $and $and$libresoc.v:142073$6210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 connect \Y $and$libresoc.v:142073$6210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" cell $and $and$libresoc.v:142076$6213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 connect \Y $and$libresoc.v:142076$6213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" cell $and $and$libresoc.v:142078$6215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] connect \Y $and$libresoc.v:142078$6215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" cell $and $and$libresoc.v:142081$6218 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } connect \Y $and$libresoc.v:142081$6218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" cell $and $and$libresoc.v:142082$6219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o connect \Y $and$libresoc.v:142082$6219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" cell $and $and$libresoc.v:142083$6220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o connect \Y $and$libresoc.v:142083$6220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" cell $and $and$libresoc.v:142085$6223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd connect \Y $and$libresoc.v:142085$6223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" cell $and $and$libresoc.v:142097$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i connect \Y $and$libresoc.v:142097$6237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" cell $and $and$libresoc.v:142098$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i connect \Y $and$libresoc.v:142098$6238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" cell $and $and$libresoc.v:142100$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 connect \Y $and$libresoc.v:142100$6240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" cell $and $and$libresoc.v:142102$6242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 connect \Y $and$libresoc.v:142102$6242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" cell $and $and$libresoc.v:142105$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 connect \Y $and$libresoc.v:142105$6245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" cell $and $and$libresoc.v:142109$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 connect \Y $and$libresoc.v:142109$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" cell $and $and$libresoc.v:142112$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st connect \Y $and$libresoc.v:142112$6252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" cell $and $and$libresoc.v:142121$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:142121$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" cell $and $and$libresoc.v:142123$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 connect \Y $and$libresoc.v:142123$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" cell $and $and$libresoc.v:142125$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 connect \Y $and$libresoc.v:142125$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" cell $and $and$libresoc.v:142126$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:142126$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" cell $and $and$libresoc.v:142127$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st connect \Y $and$libresoc.v:142127$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" cell $and $and$libresoc.v:142132$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 connect \Y $and$libresoc.v:142132$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" cell $eq $eq$libresoc.v:142057$6194 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 connect \Y $eq$libresoc.v:142057$6194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" cell $eq $eq$libresoc.v:142077$6214 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 connect \Y $eq$libresoc.v:142077$6214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" cell $eq $eq$libresoc.v:142079$6216 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 connect \Y $eq$libresoc.v:142079$6216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" cell $eq $eq$libresoc.v:142090$6229 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 connect \Y $eq$libresoc.v:142090$6229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" cell $eq $eq$libresoc.v:142095$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 connect \Y $eq$libresoc.v:142095$6235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" cell $eq $eq$libresoc.v:142096$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 connect \Y $eq$libresoc.v:142096$6236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" cell $eq $eq$libresoc.v:142104$6244 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 connect \Y $eq$libresoc.v:142104$6244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" cell $eq $eq$libresoc.v:142108$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 connect \Y $eq$libresoc.v:142108$6248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" cell $pos $extend$libresoc.v:142084$6221 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r connect \Y $extend$libresoc.v:142084$6221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $extend$libresoc.v:142086$6224 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] connect \Y $extend$libresoc.v:142086$6224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $extend$libresoc.v:142091$6230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] connect \Y $extend$libresoc.v:142091$6230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" cell $not $not$libresoc.v:142069$6206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 connect \Y $not$libresoc.v:142069$6206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" cell $not $not$libresoc.v:142074$6211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \Y $not$libresoc.v:142074$6211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" cell $not $not$libresoc.v:142099$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid connect \Y $not$libresoc.v:142099$6239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" cell $not $not$libresoc.v:142101$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any connect \Y $not$libresoc.v:142101$6241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" cell $not $not$libresoc.v:142103$6243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \Y $not$libresoc.v:142103$6243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" cell $not $not$libresoc.v:142107$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \Y $not$libresoc.v:142107$6247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" cell $not $not$libresoc.v:142122$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } connect \Y $not$libresoc.v:142122$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" cell $not $not$libresoc.v:142124$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:142124$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" cell $not $not$libresoc.v:142131$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 connect \Y $not$libresoc.v:142131$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" cell $not $not$libresoc.v:142133$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] connect \Y $not$libresoc.v:142133$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" cell $or $or$libresoc.v:142048$6185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i connect \Y $or$libresoc.v:142048$6185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" cell $or $or$libresoc.v:142059$6196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i connect \Y $or$libresoc.v:142059$6196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" cell $or $or$libresoc.v:142062$6199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go connect \Y $or$libresoc.v:142062$6199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" cell $or $or$libresoc.v:142063$6200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] connect \Y $or$libresoc.v:142063$6200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" cell $or $or$libresoc.v:142064$6201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] connect \Y $or$libresoc.v:142064$6201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" cell $or $or$libresoc.v:142067$6204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] connect \Y $or$libresoc.v:142067$6204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" cell $or $or$libresoc.v:142068$6205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] connect \Y $or$libresoc.v:142068$6205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" cell $or $or$libresoc.v:142070$6207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i connect \Y $or$libresoc.v:142070$6207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" cell $or $or$libresoc.v:142072$6209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st connect \Y $or$libresoc.v:142072$6209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" cell $or $or$libresoc.v:142075$6212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld connect \Y $or$libresoc.v:142075$6212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" cell $or $or$libresoc.v:142080$6217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:142080$6217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" cell $or $or$libresoc.v:142088$6227 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:142088$6227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" cell $or $or$libresoc.v:142094$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:142094$6234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" cell $or $or$libresoc.v:142106$6246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 connect \Y $or$libresoc.v:142106$6246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" cell $or $or$libresoc.v:142110$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 connect \Y $or$libresoc.v:142110$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" cell $or $or$libresoc.v:142111$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } connect \Y $or$libresoc.v:142111$6251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" cell $or $or$libresoc.v:142113$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go connect \Y $or$libresoc.v:142113$6253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" cell $or $or$libresoc.v:142114$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go connect \Y $or$libresoc.v:142114$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" cell $or $or$libresoc.v:142115$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok connect \Y $or$libresoc.v:142115$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" cell $or $or$libresoc.v:142128$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:142128$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" cell $or $or$libresoc.v:142129$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] connect \Y $or$libresoc.v:142129$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" cell $or $or$libresoc.v:142130$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] connect \Y $or$libresoc.v:142130$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" cell $pos $pos$libresoc.v:142084$6222 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 connect \A $extend$libresoc.v:142084$6221_Y connect \Y $pos$libresoc.v:142084$6222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $pos$libresoc.v:142086$6225 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:142086$6224_Y connect \Y $pos$libresoc.v:142086$6225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $pos$libresoc.v:142087$6226 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } connect \Y $pos$libresoc.v:142087$6226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $pos$libresoc.v:142089$6228 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } connect \Y $pos$libresoc.v:142089$6228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $pos$libresoc.v:142091$6231 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:142091$6230_Y connect \Y $pos$libresoc.v:142091$6231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $pos$libresoc.v:142092$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } connect \Y $pos$libresoc.v:142092$6232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" cell $pos $pos$libresoc.v:142093$6233 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } connect \Y $pos$libresoc.v:142093$6233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:142116$6256 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok connect \Y $ternary$libresoc.v:142116$6256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:142117$6257 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu connect \Y $ternary$libresoc.v:142117$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" cell $mux $ternary$libresoc.v:142118$6258 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a connect \Y $ternary$libresoc.v:142118$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" cell $mux $ternary$libresoc.v:142119$6259 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok connect \Y $ternary$libresoc.v:142119$6259_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:142204.9-142210.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_adr \adr_l_q_adr connect \r_adr \adr_l_r_adr connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 attribute \src "libresoc.v:142211.15-142217.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:142218.9-142224.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \qn_lod \lod_l_qn_lod connect \r_lod \lod_l_r_lod connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 attribute \src "libresoc.v:142225.9-142231.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_lsd \lsd_l_q_lsd connect \r_lsd \lsd_l_r_lsd connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 attribute \src "libresoc.v:142232.15-142238.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:142239.15-142245.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rst \rst_l_q_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:142246.15-142252.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \module_not_derived 1 attribute \src "libresoc.v:142253.9-142259.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_sto \sto_l_q_sto connect \r_sto \sto_l_r_sto connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 attribute \src "libresoc.v:142260.9-142266.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_upd \upd_l_q_upd connect \r_upd \upd_l_r_upd connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 attribute \src "libresoc.v:142267.9-142273.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_wri \wri_l_q_wri connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end attribute \src "libresoc.v:141293.7-141293.20" process $proc$libresoc.v:141293$6422 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:141489.7-141489.25" process $proc$libresoc.v:141489$6423 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end attribute \src "libresoc.v:141503.7-141503.20" process $proc$libresoc.v:141503$6424 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end attribute \src "libresoc.v:141549.14-141549.41" process $proc$libresoc.v:141549$6425 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end attribute \src "libresoc.v:141579.14-141579.42" process $proc$libresoc.v:141579$6426 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end attribute \src "libresoc.v:141584.14-141584.62" process $proc$libresoc.v:141584$6427 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end attribute \src "libresoc.v:141589.7-141589.34" process $proc$libresoc.v:141589$6428 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end attribute \src "libresoc.v:141638.7-141638.25" process $proc$libresoc.v:141638$6429 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end attribute \src "libresoc.v:141652.7-141652.25" process $proc$libresoc.v:141652$6430 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:141656.7-141656.25" process $proc$libresoc.v:141656$6431 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:141787.7-141787.34" process $proc$libresoc.v:141787$6432 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end attribute \src "libresoc.v:141791.13-141791.36" process $proc$libresoc.v:141791$6433 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end attribute \src "libresoc.v:141810.14-141810.40" process $proc$libresoc.v:141810$6434 assign { } { } assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end attribute \src "libresoc.v:141814.14-141814.59" process $proc$libresoc.v:141814$6435 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end attribute \src "libresoc.v:141818.7-141818.34" process $proc$libresoc.v:141818$6436 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end attribute \src "libresoc.v:141822.14-141822.34" process $proc$libresoc.v:141822$6437 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end attribute \src "libresoc.v:141901.13-141901.38" process $proc$libresoc.v:141901$6438 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end attribute \src "libresoc.v:141905.7-141905.30" process $proc$libresoc.v:141905$6439 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end attribute \src "libresoc.v:141909.7-141909.31" process $proc$libresoc.v:141909$6440 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end attribute \src "libresoc.v:141918.13-141918.37" process $proc$libresoc.v:141918$6441 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end attribute \src "libresoc.v:141922.7-141922.28" process $proc$libresoc.v:141922$6442 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end attribute \src "libresoc.v:141926.7-141926.28" process $proc$libresoc.v:141926$6443 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end attribute \src "libresoc.v:141930.7-141930.28" process $proc$libresoc.v:141930$6444 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end attribute \src "libresoc.v:141934.7-141934.28" process $proc$libresoc.v:141934$6445 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end attribute \src "libresoc.v:141938.7-141938.33" process $proc$libresoc.v:141938$6446 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end attribute \src "libresoc.v:141942.7-141942.28" process $proc$libresoc.v:141942$6447 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end attribute \src "libresoc.v:141946.7-141946.21" process $proc$libresoc.v:141946$6448 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end attribute \src "libresoc.v:141988.13-141988.31" process $proc$libresoc.v:141988$6449 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end attribute \src "libresoc.v:141992.13-141992.31" process $proc$libresoc.v:141992$6450 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end attribute \src "libresoc.v:141996.14-141996.43" process $proc$libresoc.v:141996$6451 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:142000.14-142000.43" process $proc$libresoc.v:142000$6452 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:142004.14-142004.43" process $proc$libresoc.v:142004$6453 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end attribute \src "libresoc.v:142014.7-142014.25" process $proc$libresoc.v:142014$6454 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end attribute \src "libresoc.v:142024.7-142024.25" process $proc$libresoc.v:142024$6455 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end attribute \src "libresoc.v:142028.7-142028.25" process $proc$libresoc.v:142028$6456 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end attribute \src "libresoc.v:142038.7-142038.25" process $proc$libresoc.v:142038$6457 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end attribute \src "libresoc.v:142134.3-142135.57" process $proc$libresoc.v:142134$6274 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end attribute \src "libresoc.v:142136.3-142137.33" process $proc$libresoc.v:142136$6275 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end attribute \src "libresoc.v:142138.3-142139.21" process $proc$libresoc.v:142138$6276 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end attribute \src "libresoc.v:142140.3-142141.25" process $proc$libresoc.v:142140$6277 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end attribute \src "libresoc.v:142142.3-142143.29" process $proc$libresoc.v:142142$6278 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end attribute \src "libresoc.v:142144.3-142145.29" process $proc$libresoc.v:142144$6279 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:142146.3-142147.29" process $proc$libresoc.v:142146$6280 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:142148.3-142149.27" process $proc$libresoc.v:142148$6281 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end attribute \src "libresoc.v:142150.3-142151.51" process $proc$libresoc.v:142150$6282 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end attribute \src "libresoc.v:142152.3-142153.47" process $proc$libresoc.v:142152$6283 assign { } { } assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end attribute \src "libresoc.v:142154.3-142155.61" process $proc$libresoc.v:142154$6284 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end attribute \src "libresoc.v:142156.3-142157.57" process $proc$libresoc.v:142156$6285 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end attribute \src "libresoc.v:142158.3-142159.45" process $proc$libresoc.v:142158$6286 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end attribute \src "libresoc.v:142160.3-142161.45" process $proc$libresoc.v:142160$6287 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end attribute \src "libresoc.v:142162.3-142163.45" process $proc$libresoc.v:142162$6288 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end attribute \src "libresoc.v:142164.3-142165.45" process $proc$libresoc.v:142164$6289 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end attribute \src "libresoc.v:142166.3-142167.45" process $proc$libresoc.v:142166$6290 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end attribute \src "libresoc.v:142168.3-142169.49" process $proc$libresoc.v:142168$6291 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end attribute \src "libresoc.v:142170.3-142171.51" process $proc$libresoc.v:142170$6292 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end attribute \src "libresoc.v:142172.3-142173.49" process $proc$libresoc.v:142172$6293 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end attribute \src "libresoc.v:142174.3-142175.57" process $proc$libresoc.v:142174$6294 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end attribute \src "libresoc.v:142176.3-142177.55" process $proc$libresoc.v:142176$6295 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end attribute \src "libresoc.v:142178.3-142179.51" process $proc$libresoc.v:142178$6296 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end attribute \src "libresoc.v:142180.3-142181.41" process $proc$libresoc.v:142180$6297 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end attribute \src "libresoc.v:142182.3-142183.39" process $proc$libresoc.v:142182$6298 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end attribute \src "libresoc.v:142184.3-142185.39" process $proc$libresoc.v:142184$6299 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end attribute \src "libresoc.v:142186.3-142187.39" process $proc$libresoc.v:142186$6300 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end attribute \src "libresoc.v:142188.3-142189.39" process $proc$libresoc.v:142188$6301 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end attribute \src "libresoc.v:142190.3-142191.39" process $proc$libresoc.v:142190$6302 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end attribute \src "libresoc.v:142192.3-142193.39" process $proc$libresoc.v:142192$6303 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end attribute \src "libresoc.v:142194.3-142195.39" process $proc$libresoc.v:142194$6304 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end attribute \src "libresoc.v:142196.3-142197.39" process $proc$libresoc.v:142196$6305 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end attribute \src "libresoc.v:142198.3-142199.39" process $proc$libresoc.v:142198$6306 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:142200.3-142201.39" process $proc$libresoc.v:142200$6307 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:142202.3-142203.28" process $proc$libresoc.v:142202$6308 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end attribute \src "libresoc.v:142274.3-142282.6" process $proc$libresoc.v:142274$6309 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$6310 $1\opc_l_s_opc$next[0:0]$6311 attribute \src "libresoc.v:142275.5-142275.29" switch \initial attribute \src "libresoc.v:142275.9-142275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$6311 1'0 case assign $1\opc_l_s_opc$next[0:0]$6311 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6310 end attribute \src "libresoc.v:142283.3-142291.6" process $proc$libresoc.v:142283$6312 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$6313 $1\opc_l_r_opc$next[0:0]$6314 attribute \src "libresoc.v:142284.5-142284.29" switch \initial attribute \src "libresoc.v:142284.9-142284.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$6314 1'1 case assign $1\opc_l_r_opc$next[0:0]$6314 \reset_o end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6313 end attribute \src "libresoc.v:142292.3-142300.6" process $proc$libresoc.v:142292$6315 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$6316 $1\src_l_s_src$next[2:0]$6317 attribute \src "libresoc.v:142293.5-142293.29" switch \initial attribute \src "libresoc.v:142293.9-142293.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[2:0]$6317 3'000 case assign $1\src_l_s_src$next[2:0]$6317 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6316 end attribute \src "libresoc.v:142301.3-142309.6" process $proc$libresoc.v:142301$6318 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$6319 $1\src_l_r_src$next[2:0]$6320 attribute \src "libresoc.v:142302.5-142302.29" switch \initial attribute \src "libresoc.v:142302.9-142302.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[2:0]$6320 3'111 case assign $1\src_l_r_src$next[2:0]$6320 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6319 end attribute \src "libresoc.v:142310.3-142318.6" process $proc$libresoc.v:142310$6321 assign { } { } assign { } { } assign $0\adr_l_r_adr$next[0:0]$6322 $1\adr_l_r_adr$next[0:0]$6323 attribute \src "libresoc.v:142311.5-142311.29" switch \initial attribute \src "libresoc.v:142311.9-142311.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\adr_l_r_adr$next[0:0]$6323 1'1 case assign $1\adr_l_r_adr$next[0:0]$6323 \reset_a end sync always update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6322 end attribute \src "libresoc.v:142319.3-142327.6" process $proc$libresoc.v:142319$6324 assign { } { } assign { } { } assign $0\wri_l_r_wri$next[0:0]$6325 $1\wri_l_r_wri$next[0:0]$6326 attribute \src "libresoc.v:142320.5-142320.29" switch \initial attribute \src "libresoc.v:142320.9-142320.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\wri_l_r_wri$next[0:0]$6326 1'1 case assign $1\wri_l_r_wri$next[0:0]$6326 \$38 [0] end sync always update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6325 end attribute \src "libresoc.v:142328.3-142336.6" process $proc$libresoc.v:142328$6327 assign { } { } assign { } { } assign $0\upd_l_s_upd$next[0:0]$6328 $1\upd_l_s_upd$next[0:0]$6329 attribute \src "libresoc.v:142329.5-142329.29" switch \initial attribute \src "libresoc.v:142329.9-142329.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\upd_l_s_upd$next[0:0]$6329 1'0 case assign $1\upd_l_s_upd$next[0:0]$6329 \reset_i end sync always update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6328 end attribute \src "libresoc.v:142337.3-142345.6" process $proc$libresoc.v:142337$6330 assign { } { } assign { } { } assign $0\upd_l_r_upd$next[0:0]$6331 $1\upd_l_r_upd$next[0:0]$6332 attribute \src "libresoc.v:142338.5-142338.29" switch \initial attribute \src "libresoc.v:142338.9-142338.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\upd_l_r_upd$next[0:0]$6332 1'1 case assign $1\upd_l_r_upd$next[0:0]$6332 \reset_u end sync always update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6331 end attribute \src "libresoc.v:142346.3-142354.6" process $proc$libresoc.v:142346$6333 assign { } { } assign { } { } assign $0\sto_l_r_sto$next[0:0]$6334 $1\sto_l_r_sto$next[0:0]$6335 attribute \src "libresoc.v:142347.5-142347.29" switch \initial attribute \src "libresoc.v:142347.9-142347.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sto_l_r_sto$next[0:0]$6335 1'1 case assign $1\sto_l_r_sto$next[0:0]$6335 \$59 end sync always update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6334 end attribute \src "libresoc.v:142355.3-142363.6" process $proc$libresoc.v:142355$6336 assign { } { } assign { } { } assign $0\lsd_l_r_lsd$next[0:0]$6337 $1\lsd_l_r_lsd$next[0:0]$6338 attribute \src "libresoc.v:142356.5-142356.29" switch \initial attribute \src "libresoc.v:142356.9-142356.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\lsd_l_r_lsd$next[0:0]$6338 1'1 case assign $1\lsd_l_r_lsd$next[0:0]$6338 \$63 end sync always update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6337 end attribute \src "libresoc.v:142364.3-142406.6" process $proc$libresoc.v:142364$6339 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\oper_r__byte_reverse$next[0:0]$6340 $2\oper_r__byte_reverse$next[0:0]$6372 assign $0\oper_r__data_len$next[3:0]$6341 $2\oper_r__data_len$next[3:0]$6373 assign $0\oper_r__fn_unit$next[13:0]$6342 $2\oper_r__fn_unit$next[13:0]$6374 assign { } { } assign { } { } assign $0\oper_r__insn$next[31:0]$6345 $2\oper_r__insn$next[31:0]$6377 assign $0\oper_r__insn_type$next[6:0]$6346 $2\oper_r__insn_type$next[6:0]$6378 assign $0\oper_r__is_32bit$next[0:0]$6347 $2\oper_r__is_32bit$next[0:0]$6379 assign $0\oper_r__is_signed$next[0:0]$6348 $2\oper_r__is_signed$next[0:0]$6380 assign $0\oper_r__ldst_mode$next[1:0]$6349 $2\oper_r__ldst_mode$next[1:0]$6381 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\oper_r__sign_extend$next[0:0]$6354 $2\oper_r__sign_extend$next[0:0]$6386 assign $0\oper_r__zero_a$next[0:0]$6355 $2\oper_r__zero_a$next[0:0]$6387 assign $0\oper_r__imm_data__data$next[63:0]$6343 $3\oper_r__imm_data__data$next[63:0]$6388 assign $0\oper_r__imm_data__ok$next[0:0]$6344 $3\oper_r__imm_data__ok$next[0:0]$6389 assign $0\oper_r__oe__oe$next[0:0]$6350 $3\oper_r__oe__oe$next[0:0]$6390 assign $0\oper_r__oe__ok$next[0:0]$6351 $3\oper_r__oe__ok$next[0:0]$6391 assign $0\oper_r__rc__ok$next[0:0]$6352 $3\oper_r__rc__ok$next[0:0]$6392 assign $0\oper_r__rc__rc$next[0:0]$6353 $3\oper_r__rc__rc$next[0:0]$6393 attribute \src "libresoc.v:142365.5-142365.29" switch \initial attribute \src "libresoc.v:142365.9-142365.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\oper_r__insn$next[31:0]$6361 $1\oper_r__ldst_mode$next[1:0]$6365 $1\oper_r__sign_extend$next[0:0]$6370 $1\oper_r__byte_reverse$next[0:0]$6356 $1\oper_r__data_len$next[3:0]$6357 $1\oper_r__is_signed$next[0:0]$6364 $1\oper_r__is_32bit$next[0:0]$6363 $1\oper_r__oe__ok$next[0:0]$6367 $1\oper_r__oe__oe$next[0:0]$6366 $1\oper_r__rc__ok$next[0:0]$6368 $1\oper_r__rc__rc$next[0:0]$6369 $1\oper_r__zero_a$next[0:0]$6371 $1\oper_r__imm_data__ok$next[0:0]$6360 $1\oper_r__imm_data__data$next[63:0]$6359 $1\oper_r__fn_unit$next[13:0]$6358 $1\oper_r__insn_type$next[6:0]$6362 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case assign $1\oper_r__byte_reverse$next[0:0]$6356 \oper_r__byte_reverse assign $1\oper_r__data_len$next[3:0]$6357 \oper_r__data_len assign $1\oper_r__fn_unit$next[13:0]$6358 \oper_r__fn_unit assign $1\oper_r__imm_data__data$next[63:0]$6359 \oper_r__imm_data__data assign $1\oper_r__imm_data__ok$next[0:0]$6360 \oper_r__imm_data__ok assign $1\oper_r__insn$next[31:0]$6361 \oper_r__insn assign $1\oper_r__insn_type$next[6:0]$6362 \oper_r__insn_type assign $1\oper_r__is_32bit$next[0:0]$6363 \oper_r__is_32bit assign $1\oper_r__is_signed$next[0:0]$6364 \oper_r__is_signed assign $1\oper_r__ldst_mode$next[1:0]$6365 \oper_r__ldst_mode assign $1\oper_r__oe__oe$next[0:0]$6366 \oper_r__oe__oe assign $1\oper_r__oe__ok$next[0:0]$6367 \oper_r__oe__ok assign $1\oper_r__rc__ok$next[0:0]$6368 \oper_r__rc__ok assign $1\oper_r__rc__rc$next[0:0]$6369 \oper_r__rc__rc assign $1\oper_r__sign_extend$next[0:0]$6370 \oper_r__sign_extend assign $1\oper_r__zero_a$next[0:0]$6371 \oper_r__zero_a end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $2\oper_r__insn$next[31:0]$6377 $2\oper_r__ldst_mode$next[1:0]$6381 $2\oper_r__sign_extend$next[0:0]$6386 $2\oper_r__byte_reverse$next[0:0]$6372 $2\oper_r__data_len$next[3:0]$6373 $2\oper_r__is_signed$next[0:0]$6380 $2\oper_r__is_32bit$next[0:0]$6379 $2\oper_r__oe__ok$next[0:0]$6383 $2\oper_r__oe__oe$next[0:0]$6382 $2\oper_r__rc__ok$next[0:0]$6384 $2\oper_r__rc__rc$next[0:0]$6385 $2\oper_r__zero_a$next[0:0]$6387 $2\oper_r__imm_data__ok$next[0:0]$6376 $2\oper_r__imm_data__data$next[63:0]$6375 $2\oper_r__fn_unit$next[13:0]$6374 $2\oper_r__insn_type$next[6:0]$6378 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case assign $2\oper_r__byte_reverse$next[0:0]$6372 $1\oper_r__byte_reverse$next[0:0]$6356 assign $2\oper_r__data_len$next[3:0]$6373 $1\oper_r__data_len$next[3:0]$6357 assign $2\oper_r__fn_unit$next[13:0]$6374 $1\oper_r__fn_unit$next[13:0]$6358 assign $2\oper_r__imm_data__data$next[63:0]$6375 $1\oper_r__imm_data__data$next[63:0]$6359 assign $2\oper_r__imm_data__ok$next[0:0]$6376 $1\oper_r__imm_data__ok$next[0:0]$6360 assign $2\oper_r__insn$next[31:0]$6377 $1\oper_r__insn$next[31:0]$6361 assign $2\oper_r__insn_type$next[6:0]$6378 $1\oper_r__insn_type$next[6:0]$6362 assign $2\oper_r__is_32bit$next[0:0]$6379 $1\oper_r__is_32bit$next[0:0]$6363 assign $2\oper_r__is_signed$next[0:0]$6380 $1\oper_r__is_signed$next[0:0]$6364 assign $2\oper_r__ldst_mode$next[1:0]$6381 $1\oper_r__ldst_mode$next[1:0]$6365 assign $2\oper_r__oe__oe$next[0:0]$6382 $1\oper_r__oe__oe$next[0:0]$6366 assign $2\oper_r__oe__ok$next[0:0]$6383 $1\oper_r__oe__ok$next[0:0]$6367 assign $2\oper_r__rc__ok$next[0:0]$6384 $1\oper_r__rc__ok$next[0:0]$6368 assign $2\oper_r__rc__rc$next[0:0]$6385 $1\oper_r__rc__rc$next[0:0]$6369 assign $2\oper_r__sign_extend$next[0:0]$6386 $1\oper_r__sign_extend$next[0:0]$6370 assign $2\oper_r__zero_a$next[0:0]$6387 $1\oper_r__zero_a$next[0:0]$6371 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $3\oper_r__imm_data__data$next[63:0]$6388 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\oper_r__imm_data__ok$next[0:0]$6389 1'0 assign $3\oper_r__rc__rc$next[0:0]$6393 1'0 assign $3\oper_r__rc__ok$next[0:0]$6392 1'0 assign $3\oper_r__oe__oe$next[0:0]$6390 1'0 assign $3\oper_r__oe__ok$next[0:0]$6391 1'0 case assign $3\oper_r__imm_data__data$next[63:0]$6388 $2\oper_r__imm_data__data$next[63:0]$6375 assign $3\oper_r__imm_data__ok$next[0:0]$6389 $2\oper_r__imm_data__ok$next[0:0]$6376 assign $3\oper_r__oe__oe$next[0:0]$6390 $2\oper_r__oe__oe$next[0:0]$6382 assign $3\oper_r__oe__ok$next[0:0]$6391 $2\oper_r__oe__ok$next[0:0]$6383 assign $3\oper_r__rc__ok$next[0:0]$6392 $2\oper_r__rc__ok$next[0:0]$6384 assign $3\oper_r__rc__rc$next[0:0]$6393 $2\oper_r__rc__rc$next[0:0]$6385 end sync always update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6340 update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6341 update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6342 update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6343 update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6344 update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6345 update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6346 update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6347 update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6348 update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6349 update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6350 update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6351 update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6352 update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6353 update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6354 update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6355 end attribute \src "libresoc.v:142407.3-142416.6" process $proc$libresoc.v:142407$6394 assign { } { } assign { } { } assign $0\ldo_r$next[63:0]$6395 $1\ldo_r$next[63:0]$6396 attribute \src "libresoc.v:142408.5-142408.29" switch \initial attribute \src "libresoc.v:142408.9-142408.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \ld_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldo_r$next[63:0]$6396 \ldd_o case assign $1\ldo_r$next[63:0]$6396 \ldo_r end sync always update \ldo_r$next $0\ldo_r$next[63:0]$6395 end attribute \src "libresoc.v:142417.3-142432.6" process $proc$libresoc.v:142417$6397 assign { } { } assign { } { } assign { } { } assign $0\src_r0$next[63:0]$6398 $2\src_r0$next[63:0]$6400 attribute \src "libresoc.v:142418.5-142418.29" switch \initial attribute \src "libresoc.v:142418.9-142418.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" switch \cu_rd__go_i [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$6399 \src1_i case assign $1\src_r0$next[63:0]$6399 \src_r0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src_r0$next[63:0]$6400 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $2\src_r0$next[63:0]$6400 $1\src_r0$next[63:0]$6399 end sync always update \src_r0$next $0\src_r0$next[63:0]$6398 end attribute \src "libresoc.v:142433.3-142448.6" process $proc$libresoc.v:142433$6401 assign { } { } assign { } { } assign { } { } assign $0\src_r1$next[63:0]$6402 $2\src_r1$next[63:0]$6404 attribute \src "libresoc.v:142434.5-142434.29" switch \initial attribute \src "libresoc.v:142434.9-142434.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" switch \cu_rd__go_i [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$6403 \src2_i case assign $1\src_r1$next[63:0]$6403 \src_r1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src_r1$next[63:0]$6404 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $2\src_r1$next[63:0]$6404 $1\src_r1$next[63:0]$6403 end sync always update \src_r1$next $0\src_r1$next[63:0]$6402 end attribute \src "libresoc.v:142449.3-142464.6" process $proc$libresoc.v:142449$6405 assign { } { } assign { } { } assign { } { } assign $0\src_r2$next[63:0]$6406 $2\src_r2$next[63:0]$6408 attribute \src "libresoc.v:142450.5-142450.29" switch \initial attribute \src "libresoc.v:142450.9-142450.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" switch \cu_rd__go_i [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[63:0]$6407 \src3_i case assign $1\src_r2$next[63:0]$6407 \src_r2 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src_r2$next[63:0]$6408 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $2\src_r2$next[63:0]$6408 $1\src_r2$next[63:0]$6407 end sync always update \src_r2$next $0\src_r2$next[63:0]$6406 end attribute \src "libresoc.v:142465.3-142474.6" process $proc$libresoc.v:142465$6409 assign { } { } assign { } { } assign $0\ea_r$next[63:0]$6410 $1\ea_r$next[63:0]$6411 attribute \src "libresoc.v:142466.5-142466.29" switch \initial attribute \src "libresoc.v:142466.9-142466.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \alu_l_q_alu attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ea_r$next[63:0]$6411 \alu_o case assign $1\ea_r$next[63:0]$6411 \ea_r end sync always update \ea_r$next $0\ea_r$next[63:0]$6410 end attribute \src "libresoc.v:142475.3-142484.6" process $proc$libresoc.v:142475$6412 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:142476.5-142476.29" switch \initial attribute \src "libresoc.v:142476.9-142476.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" switch \cu_wr__go_i [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \ldd_r case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:142485.3-142494.6" process $proc$libresoc.v:142485$6413 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] attribute \src "libresoc.v:142486.5-142486.29" switch \initial attribute \src "libresoc.v:142486.9-142486.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" switch \$164 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[63:0] \addr_r case assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest2_o $0\dest2_o[63:0] end attribute \src "libresoc.v:142495.3-142503.6" process $proc$libresoc.v:142495$6414 assign { } { } assign { } { } assign $0\ldst_port0_addr_i_ok$next[0:0]$6415 $1\ldst_port0_addr_i_ok$next[0:0]$6416 attribute \src "libresoc.v:142496.5-142496.29" switch \initial attribute \src "libresoc.v:142496.9-142496.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_addr_i_ok$next[0:0]$6416 1'0 case assign $1\ldst_port0_addr_i_ok$next[0:0]$6416 \$177 end sync always update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6415 end attribute \src "libresoc.v:142504.3-142527.6" process $proc$libresoc.v:142504$6417 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] attribute \src "libresoc.v:142505.5-142505.29" switch \initial attribute \src "libresoc.v:142505.9-142505.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\lddata_r[63:0] $2\lddata_r[63:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" switch \oper_r__data_len attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $2\lddata_r[63:0] \$186 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $2\lddata_r[63:0] \$188 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $2\lddata_r[63:0] \$190 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } case assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \lddata_r $0\lddata_r[63:0] end attribute \src "libresoc.v:142528.3-142539.6" process $proc$libresoc.v:142528$6418 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] attribute \src "libresoc.v:142529.5-142529.29" switch \initial attribute \src "libresoc.v:142529.9-142529.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\revnorev[63:0] \lddata_r attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\revnorev[63:0] \ldst_port0_ld_data_o end sync always update \revnorev $0\revnorev[63:0] end attribute \src "libresoc.v:142540.3-142559.6" process $proc$libresoc.v:142540$6419 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] attribute \src "libresoc.v:142541.5-142541.29" switch \initial attribute \src "libresoc.v:142541.9-142541.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" switch \oper_r__sign_extend attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldd_o[63:0] $2\ldd_o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ldd_o[63:0] \revnorev end sync always update \ldd_o $0\ldd_o[63:0] end attribute \src "libresoc.v:142560.3-142583.6" process $proc$libresoc.v:142560$6420 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] attribute \src "libresoc.v:142561.5-142561.29" switch \initial attribute \src "libresoc.v:142561.9-142561.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\stdata_r[63:0] $2\stdata_r[63:0] attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" switch \oper_r__data_len attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $2\stdata_r[63:0] \$194 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $2\stdata_r[63:0] \$196 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $2\stdata_r[63:0] \$198 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } case assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \stdata_r $0\stdata_r[63:0] end attribute \src "libresoc.v:142584.3-142595.6" process $proc$libresoc.v:142584$6421 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] attribute \src "libresoc.v:142585.5-142585.29" switch \initial attribute \src "libresoc.v:142585.9-142585.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_st_data_i[63:0] \stdata_r attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ldst_port0_st_data_i[63:0] \src_r2 end sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end connect \$100 $and$libresoc.v:142043$6180_Y connect \$102 $and$libresoc.v:142044$6181_Y connect \$104 $and$libresoc.v:142045$6182_Y connect \$106 $and$libresoc.v:142046$6183_Y connect \$108 $and$libresoc.v:142047$6184_Y connect \$10 $or$libresoc.v:142048$6185_Y connect \$110 $and$libresoc.v:142049$6186_Y connect \$112 $and$libresoc.v:142050$6187_Y connect \$114 $and$libresoc.v:142051$6188_Y connect \$116 $and$libresoc.v:142052$6189_Y connect \$118 $and$libresoc.v:142053$6190_Y connect \$120 $and$libresoc.v:142054$6191_Y connect \$122 $and$libresoc.v:142055$6192_Y connect \$124 $and$libresoc.v:142056$6193_Y connect \$126 $eq$libresoc.v:142057$6194_Y connect \$128 $and$libresoc.v:142058$6195_Y connect \$12 $or$libresoc.v:142059$6196_Y connect \$130 $and$libresoc.v:142060$6197_Y connect \$132 $and$libresoc.v:142061$6198_Y connect \$134 $or$libresoc.v:142062$6199_Y connect \$136 $or$libresoc.v:142063$6200_Y connect \$138 $or$libresoc.v:142064$6201_Y connect \$140 $and$libresoc.v:142065$6202_Y connect \$142 $and$libresoc.v:142066$6203_Y connect \$145 $or$libresoc.v:142067$6204_Y connect \$147 $or$libresoc.v:142068$6205_Y connect \$144 $not$libresoc.v:142069$6206_Y connect \$14 $or$libresoc.v:142070$6207_Y connect \$150 $and$libresoc.v:142071$6208_Y connect \$152 $or$libresoc.v:142072$6209_Y connect \$154 $and$libresoc.v:142073$6210_Y connect \$156 $not$libresoc.v:142074$6211_Y connect \$158 $or$libresoc.v:142075$6212_Y connect \$160 $and$libresoc.v:142076$6213_Y connect \$162 $eq$libresoc.v:142077$6214_Y connect \$164 $and$libresoc.v:142078$6215_Y connect \$167 $eq$libresoc.v:142079$6216_Y connect \$16 $or$libresoc.v:142080$6217_Y connect \$169 $and$libresoc.v:142081$6218_Y connect \$171 $and$libresoc.v:142082$6219_Y connect \$173 $and$libresoc.v:142083$6220_Y connect \$175 $pos$libresoc.v:142084$6222_Y connect \$177 $and$libresoc.v:142085$6223_Y connect \$186 $pos$libresoc.v:142086$6225_Y connect \$188 $pos$libresoc.v:142087$6226_Y connect \$18 $or$libresoc.v:142088$6227_Y connect \$190 $pos$libresoc.v:142089$6228_Y connect \$192 $eq$libresoc.v:142090$6229_Y connect \$194 $pos$libresoc.v:142091$6231_Y connect \$196 $pos$libresoc.v:142092$6232_Y connect \$198 $pos$libresoc.v:142093$6233_Y connect \$20 $or$libresoc.v:142094$6234_Y connect \$22 $eq$libresoc.v:142095$6235_Y connect \$24 $eq$libresoc.v:142096$6236_Y connect \$26 $and$libresoc.v:142097$6237_Y connect \$28 $and$libresoc.v:142098$6238_Y connect \$30 $not$libresoc.v:142099$6239_Y connect \$32 $and$libresoc.v:142100$6240_Y connect \$34 $not$libresoc.v:142101$6241_Y connect \$36 $and$libresoc.v:142102$6242_Y connect \$39 $not$libresoc.v:142103$6243_Y connect \$41 $eq$libresoc.v:142104$6244_Y connect \$43 $and$libresoc.v:142105$6245_Y connect \$45 $or$libresoc.v:142106$6246_Y connect \$47 $not$libresoc.v:142107$6247_Y connect \$49 $eq$libresoc.v:142108$6248_Y connect \$51 $and$libresoc.v:142109$6249_Y connect \$53 $or$libresoc.v:142110$6250_Y connect \$55 $or$libresoc.v:142111$6251_Y connect \$57 $and$libresoc.v:142112$6252_Y connect \$59 $or$libresoc.v:142113$6253_Y connect \$61 $or$libresoc.v:142114$6254_Y connect \$63 $or$libresoc.v:142115$6255_Y connect \$65 $ternary$libresoc.v:142116$6256_Y connect \$67 $ternary$libresoc.v:142117$6257_Y connect \$69 $ternary$libresoc.v:142118$6258_Y connect \$71 $ternary$libresoc.v:142119$6259_Y connect \$74 $add$libresoc.v:142120$6260_Y connect \$76 $and$libresoc.v:142121$6261_Y connect \$78 $not$libresoc.v:142122$6262_Y connect \$80 $and$libresoc.v:142123$6263_Y connect \$82 $not$libresoc.v:142124$6264_Y connect \$84 $and$libresoc.v:142125$6265_Y connect \$86 $and$libresoc.v:142126$6266_Y connect \$88 $and$libresoc.v:142127$6267_Y connect \$8 $or$libresoc.v:142128$6268_Y connect \$90 $or$libresoc.v:142129$6269_Y connect \$93 $or$libresoc.v:142130$6270_Y connect \$92 $not$libresoc.v:142131$6271_Y connect \$96 $and$libresoc.v:142132$6272_Y connect \$98 $not$libresoc.v:142133$6273_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \ldst_port0_st_data_i_ok \cu_st__go_i connect \ld_ok \ldst_port0_ld_data_o_ok connect \addr_ok \ldst_port0_addr_ok_o connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } connect \ldst_port0_addr_i$next \$175 connect \ldst_port0_data_len \oper_r__data_len connect \ldst_port0_is_st_i \$173 connect \ldst_port0_is_ld_i \$171 connect \cu_wrmask_o \$169 [1:0] connect \ea \dest2_o connect \o \dest1_o connect \cu_done_o \$160 connect \wr_reset \$154 connect \wr_any \$138 connect \cu_wr__rel_o [1] \$132 connect \cu_wr__rel_o [0] \$122 connect \cu_st__rel_o \$112 connect \cu_ad__rel_o \$104 connect \rd_done \$100 connect \alu_valid \$96 connect \rda_any \$90 connect \cu_rd__rel_o [2] \$88 connect \cu_rd__rel_o [1:0] \$84 [1:0] connect \cu_busy_o \opc_l_q_opc connect \alu_ok$next \alu_valid connect \alu_o \$74 [63:0] connect \src2_or_imm \$71 connect \src1_or_z \$69 connect \addr_r \$67 connect \ldd_r \$65 connect \rst_l_r_rst \cu_issue_i connect \rst_l_s_rst \addr_ok connect \lsd_l_s_lsd \cu_issue_i connect \sto_l_s_sto \$57 connect \wri_l_s_wri \cu_issue_i connect \lod_l_r_lod \ld_ok connect \lod_l_s_lod \reset_i connect \adr_l_s_adr \reset_i connect \alu_l_r_alu \$36 connect \alu_l_s_alu \reset_i connect \st_o \op_is_st connect \ld_o \op_is_ld connect \stwd_mem_o \$28 connect \load_mem_o \$26 connect \op_is_ld \$24 connect \op_is_st \$22 connect \p_st_go$next \cu_st__go_i connect \reset_a \$20 connect \reset_r \$18 connect \reset_s \$16 connect \reset_u \$14 connect \reset_w \$12 connect \reset_o \$10 connect \reset_i \$8 end attribute \src "libresoc.v:142659.1-143246.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask attribute \src "libresoc.v:142660.7-142660.20" wire $0\initial[0:0] attribute \src "libresoc.v:142858.3-143245.6" wire width 64 $0\mask[63:0] attribute \src "libresoc.v:142858.3-143245.6" wire $10\mask[9:9] attribute \src "libresoc.v:142858.3-143245.6" wire $11\mask[10:10] attribute \src "libresoc.v:142858.3-143245.6" wire $12\mask[11:11] attribute \src "libresoc.v:142858.3-143245.6" wire $13\mask[12:12] attribute \src "libresoc.v:142858.3-143245.6" wire $14\mask[13:13] attribute \src "libresoc.v:142858.3-143245.6" wire $15\mask[14:14] attribute \src "libresoc.v:142858.3-143245.6" wire $16\mask[15:15] attribute \src "libresoc.v:142858.3-143245.6" wire $17\mask[16:16] attribute \src "libresoc.v:142858.3-143245.6" wire $18\mask[17:17] attribute \src "libresoc.v:142858.3-143245.6" wire $19\mask[18:18] attribute \src "libresoc.v:142858.3-143245.6" wire $1\mask[0:0] attribute \src "libresoc.v:142858.3-143245.6" wire $20\mask[19:19] attribute \src "libresoc.v:142858.3-143245.6" wire $21\mask[20:20] attribute \src "libresoc.v:142858.3-143245.6" wire $22\mask[21:21] attribute \src "libresoc.v:142858.3-143245.6" wire $23\mask[22:22] attribute \src "libresoc.v:142858.3-143245.6" wire $24\mask[23:23] attribute \src "libresoc.v:142858.3-143245.6" wire $25\mask[24:24] attribute \src "libresoc.v:142858.3-143245.6" wire $26\mask[25:25] attribute \src "libresoc.v:142858.3-143245.6" wire $27\mask[26:26] attribute \src "libresoc.v:142858.3-143245.6" wire $28\mask[27:27] attribute \src "libresoc.v:142858.3-143245.6" wire $29\mask[28:28] attribute \src "libresoc.v:142858.3-143245.6" wire $2\mask[1:1] attribute \src "libresoc.v:142858.3-143245.6" wire $30\mask[29:29] attribute \src "libresoc.v:142858.3-143245.6" wire $31\mask[30:30] attribute \src "libresoc.v:142858.3-143245.6" wire $32\mask[31:31] attribute \src "libresoc.v:142858.3-143245.6" wire $33\mask[32:32] attribute \src "libresoc.v:142858.3-143245.6" wire $34\mask[33:33] attribute \src "libresoc.v:142858.3-143245.6" wire $35\mask[34:34] attribute \src "libresoc.v:142858.3-143245.6" wire $36\mask[35:35] attribute \src "libresoc.v:142858.3-143245.6" wire $37\mask[36:36] attribute \src "libresoc.v:142858.3-143245.6" wire $38\mask[37:37] attribute \src "libresoc.v:142858.3-143245.6" wire $39\mask[38:38] attribute \src "libresoc.v:142858.3-143245.6" wire $3\mask[2:2] attribute \src "libresoc.v:142858.3-143245.6" wire $40\mask[39:39] attribute \src "libresoc.v:142858.3-143245.6" wire $41\mask[40:40] attribute \src "libresoc.v:142858.3-143245.6" wire $42\mask[41:41] attribute \src "libresoc.v:142858.3-143245.6" wire $43\mask[42:42] attribute \src "libresoc.v:142858.3-143245.6" wire $44\mask[43:43] attribute \src "libresoc.v:142858.3-143245.6" wire $45\mask[44:44] attribute \src "libresoc.v:142858.3-143245.6" wire $46\mask[45:45] attribute \src "libresoc.v:142858.3-143245.6" wire $47\mask[46:46] attribute \src "libresoc.v:142858.3-143245.6" wire $48\mask[47:47] attribute \src "libresoc.v:142858.3-143245.6" wire $49\mask[48:48] attribute \src "libresoc.v:142858.3-143245.6" wire $4\mask[3:3] attribute \src "libresoc.v:142858.3-143245.6" wire $50\mask[49:49] attribute \src "libresoc.v:142858.3-143245.6" wire $51\mask[50:50] attribute \src "libresoc.v:142858.3-143245.6" wire $52\mask[51:51] attribute \src "libresoc.v:142858.3-143245.6" wire $53\mask[52:52] attribute \src "libresoc.v:142858.3-143245.6" wire $54\mask[53:53] attribute \src "libresoc.v:142858.3-143245.6" wire $55\mask[54:54] attribute \src "libresoc.v:142858.3-143245.6" wire $56\mask[55:55] attribute \src "libresoc.v:142858.3-143245.6" wire $57\mask[56:56] attribute \src "libresoc.v:142858.3-143245.6" wire $58\mask[57:57] attribute \src "libresoc.v:142858.3-143245.6" wire $59\mask[58:58] attribute \src "libresoc.v:142858.3-143245.6" wire $5\mask[4:4] attribute \src "libresoc.v:142858.3-143245.6" wire $60\mask[59:59] attribute \src "libresoc.v:142858.3-143245.6" wire $61\mask[60:60] attribute \src "libresoc.v:142858.3-143245.6" wire $62\mask[61:61] attribute \src "libresoc.v:142858.3-143245.6" wire $63\mask[62:62] attribute \src "libresoc.v:142858.3-143245.6" wire $64\mask[63:63] attribute \src "libresoc.v:142858.3-143245.6" wire $6\mask[5:5] attribute \src "libresoc.v:142858.3-143245.6" wire $7\mask[6:6] attribute \src "libresoc.v:142858.3-143245.6" wire $8\mask[7:7] attribute \src "libresoc.v:142858.3-143245.6" wire $9\mask[8:8] attribute \src "libresoc.v:142794.17-142794.96" wire $gt$libresoc.v:142794$6458_Y attribute \src "libresoc.v:142795.18-142795.98" wire $gt$libresoc.v:142795$6459_Y attribute \src "libresoc.v:142796.19-142796.99" wire $gt$libresoc.v:142796$6460_Y attribute \src "libresoc.v:142797.19-142797.99" wire $gt$libresoc.v:142797$6461_Y attribute \src "libresoc.v:142798.19-142798.99" wire $gt$libresoc.v:142798$6462_Y attribute \src "libresoc.v:142799.19-142799.99" wire $gt$libresoc.v:142799$6463_Y attribute \src "libresoc.v:142800.19-142800.99" wire $gt$libresoc.v:142800$6464_Y attribute \src "libresoc.v:142801.19-142801.99" wire $gt$libresoc.v:142801$6465_Y attribute \src "libresoc.v:142802.19-142802.99" wire $gt$libresoc.v:142802$6466_Y attribute \src "libresoc.v:142803.19-142803.99" wire $gt$libresoc.v:142803$6467_Y attribute \src "libresoc.v:142804.19-142804.99" wire $gt$libresoc.v:142804$6468_Y attribute \src "libresoc.v:142805.18-142805.97" wire $gt$libresoc.v:142805$6469_Y attribute \src "libresoc.v:142806.19-142806.99" wire $gt$libresoc.v:142806$6470_Y attribute \src "libresoc.v:142807.19-142807.99" wire $gt$libresoc.v:142807$6471_Y attribute \src "libresoc.v:142808.19-142808.99" wire $gt$libresoc.v:142808$6472_Y attribute \src "libresoc.v:142809.19-142809.99" wire $gt$libresoc.v:142809$6473_Y attribute \src "libresoc.v:142810.19-142810.99" wire $gt$libresoc.v:142810$6474_Y attribute \src "libresoc.v:142811.18-142811.97" wire $gt$libresoc.v:142811$6475_Y attribute \src "libresoc.v:142812.18-142812.97" wire $gt$libresoc.v:142812$6476_Y attribute \src "libresoc.v:142813.18-142813.97" wire $gt$libresoc.v:142813$6477_Y attribute \src "libresoc.v:142814.17-142814.96" wire $gt$libresoc.v:142814$6478_Y attribute \src "libresoc.v:142815.18-142815.97" wire $gt$libresoc.v:142815$6479_Y attribute \src "libresoc.v:142816.18-142816.97" wire $gt$libresoc.v:142816$6480_Y attribute \src "libresoc.v:142817.18-142817.97" wire $gt$libresoc.v:142817$6481_Y attribute \src "libresoc.v:142818.18-142818.97" wire $gt$libresoc.v:142818$6482_Y attribute \src "libresoc.v:142819.18-142819.97" wire $gt$libresoc.v:142819$6483_Y attribute \src "libresoc.v:142820.18-142820.97" wire $gt$libresoc.v:142820$6484_Y attribute \src "libresoc.v:142821.18-142821.97" wire $gt$libresoc.v:142821$6485_Y attribute \src "libresoc.v:142822.18-142822.98" wire $gt$libresoc.v:142822$6486_Y attribute \src "libresoc.v:142823.18-142823.98" wire $gt$libresoc.v:142823$6487_Y attribute \src "libresoc.v:142824.18-142824.98" wire $gt$libresoc.v:142824$6488_Y attribute \src "libresoc.v:142825.17-142825.96" wire $gt$libresoc.v:142825$6489_Y attribute \src "libresoc.v:142826.18-142826.98" wire $gt$libresoc.v:142826$6490_Y attribute \src "libresoc.v:142827.18-142827.98" wire $gt$libresoc.v:142827$6491_Y attribute \src "libresoc.v:142828.18-142828.98" wire $gt$libresoc.v:142828$6492_Y attribute \src "libresoc.v:142829.18-142829.98" wire $gt$libresoc.v:142829$6493_Y attribute \src "libresoc.v:142830.18-142830.98" wire $gt$libresoc.v:142830$6494_Y attribute \src "libresoc.v:142831.18-142831.98" wire $gt$libresoc.v:142831$6495_Y attribute \src "libresoc.v:142832.18-142832.98" wire $gt$libresoc.v:142832$6496_Y attribute \src "libresoc.v:142833.18-142833.98" wire $gt$libresoc.v:142833$6497_Y attribute \src "libresoc.v:142834.18-142834.98" wire $gt$libresoc.v:142834$6498_Y attribute \src "libresoc.v:142835.18-142835.98" wire $gt$libresoc.v:142835$6499_Y attribute \src "libresoc.v:142836.17-142836.96" wire $gt$libresoc.v:142836$6500_Y attribute \src "libresoc.v:142837.18-142837.98" wire $gt$libresoc.v:142837$6501_Y attribute \src "libresoc.v:142838.18-142838.98" wire $gt$libresoc.v:142838$6502_Y attribute \src "libresoc.v:142839.18-142839.98" wire $gt$libresoc.v:142839$6503_Y attribute \src "libresoc.v:142840.18-142840.98" wire $gt$libresoc.v:142840$6504_Y attribute \src "libresoc.v:142841.18-142841.98" wire $gt$libresoc.v:142841$6505_Y attribute \src "libresoc.v:142842.18-142842.98" wire $gt$libresoc.v:142842$6506_Y attribute \src "libresoc.v:142843.18-142843.98" wire $gt$libresoc.v:142843$6507_Y attribute \src "libresoc.v:142844.18-142844.98" wire $gt$libresoc.v:142844$6508_Y attribute \src "libresoc.v:142845.18-142845.98" wire $gt$libresoc.v:142845$6509_Y attribute \src "libresoc.v:142846.18-142846.98" wire $gt$libresoc.v:142846$6510_Y attribute \src "libresoc.v:142847.17-142847.96" wire $gt$libresoc.v:142847$6511_Y attribute \src "libresoc.v:142848.18-142848.98" wire $gt$libresoc.v:142848$6512_Y attribute \src "libresoc.v:142849.18-142849.98" wire $gt$libresoc.v:142849$6513_Y attribute \src "libresoc.v:142850.18-142850.98" wire $gt$libresoc.v:142850$6514_Y attribute \src "libresoc.v:142851.18-142851.98" wire $gt$libresoc.v:142851$6515_Y attribute \src "libresoc.v:142852.18-142852.98" wire $gt$libresoc.v:142852$6516_Y attribute \src "libresoc.v:142853.18-142853.98" wire $gt$libresoc.v:142853$6517_Y attribute \src "libresoc.v:142854.18-142854.98" wire $gt$libresoc.v:142854$6518_Y attribute \src "libresoc.v:142855.18-142855.98" wire $gt$libresoc.v:142855$6519_Y attribute \src "libresoc.v:142856.18-142856.98" wire $gt$libresoc.v:142856$6520_Y attribute \src "libresoc.v:142857.18-142857.98" wire $gt$libresoc.v:142857$6521_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$113 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$35 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$95 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 attribute \src "libresoc.v:142660.7-142660.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142794$6458 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 connect \Y $gt$libresoc.v:142794$6458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142795$6459 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 connect \Y $gt$libresoc.v:142795$6459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142796$6460 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 connect \Y $gt$libresoc.v:142796$6460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142797$6461 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 connect \Y $gt$libresoc.v:142797$6461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142798$6462 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 connect \Y $gt$libresoc.v:142798$6462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142799$6463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 connect \Y $gt$libresoc.v:142799$6463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142800$6464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 connect \Y $gt$libresoc.v:142800$6464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142801$6465 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 connect \Y $gt$libresoc.v:142801$6465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142802$6466 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 connect \Y $gt$libresoc.v:142802$6466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142803$6467 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 connect \Y $gt$libresoc.v:142803$6467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142804$6468 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 connect \Y $gt$libresoc.v:142804$6468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142805$6469 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 connect \Y $gt$libresoc.v:142805$6469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142806$6470 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 connect \Y $gt$libresoc.v:142806$6470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142807$6471 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 connect \Y $gt$libresoc.v:142807$6471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142808$6472 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 connect \Y $gt$libresoc.v:142808$6472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142809$6473 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 connect \Y $gt$libresoc.v:142809$6473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142810$6474 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 connect \Y $gt$libresoc.v:142810$6474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142811$6475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 connect \Y $gt$libresoc.v:142811$6475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142812$6476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 connect \Y $gt$libresoc.v:142812$6476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142813$6477 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 connect \Y $gt$libresoc.v:142813$6477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142814$6478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 connect \Y $gt$libresoc.v:142814$6478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142815$6479 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 connect \Y $gt$libresoc.v:142815$6479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142816$6480 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 connect \Y $gt$libresoc.v:142816$6480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142817$6481 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 connect \Y $gt$libresoc.v:142817$6481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142818$6482 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 connect \Y $gt$libresoc.v:142818$6482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142819$6483 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 connect \Y $gt$libresoc.v:142819$6483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142820$6484 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 connect \Y $gt$libresoc.v:142820$6484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142821$6485 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 connect \Y $gt$libresoc.v:142821$6485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142822$6486 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 connect \Y $gt$libresoc.v:142822$6486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142823$6487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 connect \Y $gt$libresoc.v:142823$6487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142824$6488 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 connect \Y $gt$libresoc.v:142824$6488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142825$6489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 connect \Y $gt$libresoc.v:142825$6489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142826$6490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 connect \Y $gt$libresoc.v:142826$6490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142827$6491 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 connect \Y $gt$libresoc.v:142827$6491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142828$6492 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 connect \Y $gt$libresoc.v:142828$6492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142829$6493 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 connect \Y $gt$libresoc.v:142829$6493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142830$6494 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 connect \Y $gt$libresoc.v:142830$6494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142831$6495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 connect \Y $gt$libresoc.v:142831$6495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142832$6496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 connect \Y $gt$libresoc.v:142832$6496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142833$6497 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 connect \Y $gt$libresoc.v:142833$6497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142834$6498 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 connect \Y $gt$libresoc.v:142834$6498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142835$6499 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 connect \Y $gt$libresoc.v:142835$6499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142836$6500 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 connect \Y $gt$libresoc.v:142836$6500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142837$6501 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 connect \Y $gt$libresoc.v:142837$6501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142838$6502 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 connect \Y $gt$libresoc.v:142838$6502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142839$6503 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 connect \Y $gt$libresoc.v:142839$6503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142840$6504 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 connect \Y $gt$libresoc.v:142840$6504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142841$6505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 connect \Y $gt$libresoc.v:142841$6505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142842$6506 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 connect \Y $gt$libresoc.v:142842$6506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142843$6507 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 connect \Y $gt$libresoc.v:142843$6507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142844$6508 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 connect \Y $gt$libresoc.v:142844$6508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142845$6509 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 connect \Y $gt$libresoc.v:142845$6509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142846$6510 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 connect \Y $gt$libresoc.v:142846$6510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142847$6511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 connect \Y $gt$libresoc.v:142847$6511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142848$6512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 connect \Y $gt$libresoc.v:142848$6512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142849$6513 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 connect \Y $gt$libresoc.v:142849$6513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142850$6514 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 connect \Y $gt$libresoc.v:142850$6514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142851$6515 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 connect \Y $gt$libresoc.v:142851$6515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142852$6516 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 connect \Y $gt$libresoc.v:142852$6516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142853$6517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 connect \Y $gt$libresoc.v:142853$6517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142854$6518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 connect \Y $gt$libresoc.v:142854$6518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142855$6519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 connect \Y $gt$libresoc.v:142855$6519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142856$6520 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 connect \Y $gt$libresoc.v:142856$6520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:142857$6521 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 connect \Y $gt$libresoc.v:142857$6521_Y end attribute \src "libresoc.v:142660.7-142660.20" process $proc$libresoc.v:142660$6523 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:142858.3-143245.6" process $proc$libresoc.v:142858$6522 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] assign $0\mask[63:0] [1] $2\mask[1:1] assign $0\mask[63:0] [2] $3\mask[2:2] assign $0\mask[63:0] [3] $4\mask[3:3] assign $0\mask[63:0] [4] $5\mask[4:4] assign $0\mask[63:0] [5] $6\mask[5:5] assign $0\mask[63:0] [6] $7\mask[6:6] assign $0\mask[63:0] [7] $8\mask[7:7] assign $0\mask[63:0] [8] $9\mask[8:8] assign $0\mask[63:0] [9] $10\mask[9:9] assign $0\mask[63:0] [10] $11\mask[10:10] assign $0\mask[63:0] [11] $12\mask[11:11] assign $0\mask[63:0] [12] $13\mask[12:12] assign $0\mask[63:0] [13] $14\mask[13:13] assign $0\mask[63:0] [14] $15\mask[14:14] assign $0\mask[63:0] [15] $16\mask[15:15] assign $0\mask[63:0] [16] $17\mask[16:16] assign $0\mask[63:0] [17] $18\mask[17:17] assign $0\mask[63:0] [18] $19\mask[18:18] assign $0\mask[63:0] [19] $20\mask[19:19] assign $0\mask[63:0] [20] $21\mask[20:20] assign $0\mask[63:0] [21] $22\mask[21:21] assign $0\mask[63:0] [22] $23\mask[22:22] assign $0\mask[63:0] [23] $24\mask[23:23] assign $0\mask[63:0] [24] $25\mask[24:24] assign $0\mask[63:0] [25] $26\mask[25:25] assign $0\mask[63:0] [26] $27\mask[26:26] assign $0\mask[63:0] [27] $28\mask[27:27] assign $0\mask[63:0] [28] $29\mask[28:28] assign $0\mask[63:0] [29] $30\mask[29:29] assign $0\mask[63:0] [30] $31\mask[30:30] assign $0\mask[63:0] [31] $32\mask[31:31] assign $0\mask[63:0] [32] $33\mask[32:32] assign $0\mask[63:0] [33] $34\mask[33:33] assign $0\mask[63:0] [34] $35\mask[34:34] assign $0\mask[63:0] [35] $36\mask[35:35] assign $0\mask[63:0] [36] $37\mask[36:36] assign $0\mask[63:0] [37] $38\mask[37:37] assign $0\mask[63:0] [38] $39\mask[38:38] assign $0\mask[63:0] [39] $40\mask[39:39] assign $0\mask[63:0] [40] $41\mask[40:40] assign $0\mask[63:0] [41] $42\mask[41:41] assign $0\mask[63:0] [42] $43\mask[42:42] assign $0\mask[63:0] [43] $44\mask[43:43] assign $0\mask[63:0] [44] $45\mask[44:44] assign $0\mask[63:0] [45] $46\mask[45:45] assign $0\mask[63:0] [46] $47\mask[46:46] assign $0\mask[63:0] [47] $48\mask[47:47] assign $0\mask[63:0] [48] $49\mask[48:48] assign $0\mask[63:0] [49] $50\mask[49:49] assign $0\mask[63:0] [50] $51\mask[50:50] assign $0\mask[63:0] [51] $52\mask[51:51] assign $0\mask[63:0] [52] $53\mask[52:52] assign $0\mask[63:0] [53] $54\mask[53:53] assign $0\mask[63:0] [54] $55\mask[54:54] assign $0\mask[63:0] [55] $56\mask[55:55] assign $0\mask[63:0] [56] $57\mask[56:56] assign $0\mask[63:0] [57] $58\mask[57:57] assign $0\mask[63:0] [58] $59\mask[58:58] assign $0\mask[63:0] [59] $60\mask[59:59] assign $0\mask[63:0] [60] $61\mask[60:60] assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] attribute \src "libresoc.v:142859.5-142859.29" switch \initial attribute \src "libresoc.v:142859.9-142859.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\mask[0:0] 1'1 case assign $1\mask[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\mask[1:1] 1'1 case assign $2\mask[1:1] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\mask[2:2] 1'1 case assign $3\mask[2:2] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\mask[3:3] 1'1 case assign $4\mask[3:3] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\mask[4:4] 1'1 case assign $5\mask[4:4] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\mask[5:5] 1'1 case assign $6\mask[5:5] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\mask[6:6] 1'1 case assign $7\mask[6:6] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\mask[7:7] 1'1 case assign $8\mask[7:7] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\mask[8:8] 1'1 case assign $9\mask[8:8] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $10\mask[9:9] 1'1 case assign $10\mask[9:9] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $11\mask[10:10] 1'1 case assign $11\mask[10:10] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $12\mask[11:11] 1'1 case assign $12\mask[11:11] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $13\mask[12:12] 1'1 case assign $13\mask[12:12] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $14\mask[13:13] 1'1 case assign $14\mask[13:13] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $15\mask[14:14] 1'1 case assign $15\mask[14:14] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $16\mask[15:15] 1'1 case assign $16\mask[15:15] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $17\mask[16:16] 1'1 case assign $17\mask[16:16] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$35 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $18\mask[17:17] 1'1 case assign $18\mask[17:17] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $19\mask[18:18] 1'1 case assign $19\mask[18:18] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $20\mask[19:19] 1'1 case assign $20\mask[19:19] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $21\mask[20:20] 1'1 case assign $21\mask[20:20] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $22\mask[21:21] 1'1 case assign $22\mask[21:21] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $23\mask[22:22] 1'1 case assign $23\mask[22:22] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$47 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $24\mask[23:23] 1'1 case assign $24\mask[23:23] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $25\mask[24:24] 1'1 case assign $25\mask[24:24] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$51 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $26\mask[25:25] 1'1 case assign $26\mask[25:25] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $27\mask[26:26] 1'1 case assign $27\mask[26:26] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $28\mask[27:27] 1'1 case assign $28\mask[27:27] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $29\mask[28:28] 1'1 case assign $29\mask[28:28] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $30\mask[29:29] 1'1 case assign $30\mask[29:29] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $31\mask[30:30] 1'1 case assign $31\mask[30:30] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $32\mask[31:31] 1'1 case assign $32\mask[31:31] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$65 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $33\mask[32:32] 1'1 case assign $33\mask[32:32] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $34\mask[33:33] 1'1 case assign $34\mask[33:33] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $35\mask[34:34] 1'1 case assign $35\mask[34:34] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $36\mask[35:35] 1'1 case assign $36\mask[35:35] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $37\mask[36:36] 1'1 case assign $37\mask[36:36] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$75 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $38\mask[37:37] 1'1 case assign $38\mask[37:37] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $39\mask[38:38] 1'1 case assign $39\mask[38:38] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$79 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $40\mask[39:39] 1'1 case assign $40\mask[39:39] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $41\mask[40:40] 1'1 case assign $41\mask[40:40] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $42\mask[41:41] 1'1 case assign $42\mask[41:41] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $43\mask[42:42] 1'1 case assign $43\mask[42:42] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $44\mask[43:43] 1'1 case assign $44\mask[43:43] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$89 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $45\mask[44:44] 1'1 case assign $45\mask[44:44] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$91 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $46\mask[45:45] 1'1 case assign $46\mask[45:45] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $47\mask[46:46] 1'1 case assign $47\mask[46:46] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $48\mask[47:47] 1'1 case assign $48\mask[47:47] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$97 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $49\mask[48:48] 1'1 case assign $49\mask[48:48] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$99 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $50\mask[49:49] 1'1 case assign $50\mask[49:49] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $51\mask[50:50] 1'1 case assign $51\mask[50:50] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $52\mask[51:51] 1'1 case assign $52\mask[51:51] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $53\mask[52:52] 1'1 case assign $53\mask[52:52] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$107 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $54\mask[53:53] 1'1 case assign $54\mask[53:53] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $55\mask[54:54] 1'1 case assign $55\mask[54:54] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $56\mask[55:55] 1'1 case assign $56\mask[55:55] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $57\mask[56:56] 1'1 case assign $57\mask[56:56] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $58\mask[57:57] 1'1 case assign $58\mask[57:57] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $59\mask[58:58] 1'1 case assign $59\mask[58:58] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $60\mask[59:59] 1'1 case assign $60\mask[59:59] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $61\mask[60:60] 1'1 case assign $61\mask[60:60] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $62\mask[61:61] 1'1 case assign $62\mask[61:61] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$125 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $63\mask[62:62] 1'1 case assign $63\mask[62:62] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $64\mask[63:63] 1'1 case assign $64\mask[63:63] 1'0 end sync always update \mask $0\mask[63:0] end connect \$9 $gt$libresoc.v:142794$6458_Y connect \$99 $gt$libresoc.v:142795$6459_Y connect \$101 $gt$libresoc.v:142796$6460_Y connect \$103 $gt$libresoc.v:142797$6461_Y connect \$105 $gt$libresoc.v:142798$6462_Y connect \$107 $gt$libresoc.v:142799$6463_Y connect \$109 $gt$libresoc.v:142800$6464_Y connect \$111 $gt$libresoc.v:142801$6465_Y connect \$113 $gt$libresoc.v:142802$6466_Y connect \$115 $gt$libresoc.v:142803$6467_Y connect \$117 $gt$libresoc.v:142804$6468_Y connect \$11 $gt$libresoc.v:142805$6469_Y connect \$119 $gt$libresoc.v:142806$6470_Y connect \$121 $gt$libresoc.v:142807$6471_Y connect \$123 $gt$libresoc.v:142808$6472_Y connect \$125 $gt$libresoc.v:142809$6473_Y connect \$127 $gt$libresoc.v:142810$6474_Y connect \$13 $gt$libresoc.v:142811$6475_Y connect \$15 $gt$libresoc.v:142812$6476_Y connect \$17 $gt$libresoc.v:142813$6477_Y connect \$1 $gt$libresoc.v:142814$6478_Y connect \$19 $gt$libresoc.v:142815$6479_Y connect \$21 $gt$libresoc.v:142816$6480_Y connect \$23 $gt$libresoc.v:142817$6481_Y connect \$25 $gt$libresoc.v:142818$6482_Y connect \$27 $gt$libresoc.v:142819$6483_Y connect \$29 $gt$libresoc.v:142820$6484_Y connect \$31 $gt$libresoc.v:142821$6485_Y connect \$33 $gt$libresoc.v:142822$6486_Y connect \$35 $gt$libresoc.v:142823$6487_Y connect \$37 $gt$libresoc.v:142824$6488_Y connect \$3 $gt$libresoc.v:142825$6489_Y connect \$39 $gt$libresoc.v:142826$6490_Y connect \$41 $gt$libresoc.v:142827$6491_Y connect \$43 $gt$libresoc.v:142828$6492_Y connect \$45 $gt$libresoc.v:142829$6493_Y connect \$47 $gt$libresoc.v:142830$6494_Y connect \$49 $gt$libresoc.v:142831$6495_Y connect \$51 $gt$libresoc.v:142832$6496_Y connect \$53 $gt$libresoc.v:142833$6497_Y connect \$55 $gt$libresoc.v:142834$6498_Y connect \$57 $gt$libresoc.v:142835$6499_Y connect \$5 $gt$libresoc.v:142836$6500_Y connect \$59 $gt$libresoc.v:142837$6501_Y connect \$61 $gt$libresoc.v:142838$6502_Y connect \$63 $gt$libresoc.v:142839$6503_Y connect \$65 $gt$libresoc.v:142840$6504_Y connect \$67 $gt$libresoc.v:142841$6505_Y connect \$69 $gt$libresoc.v:142842$6506_Y connect \$71 $gt$libresoc.v:142843$6507_Y connect \$73 $gt$libresoc.v:142844$6508_Y connect \$75 $gt$libresoc.v:142845$6509_Y connect \$77 $gt$libresoc.v:142846$6510_Y connect \$7 $gt$libresoc.v:142847$6511_Y connect \$79 $gt$libresoc.v:142848$6512_Y connect \$81 $gt$libresoc.v:142849$6513_Y connect \$83 $gt$libresoc.v:142850$6514_Y connect \$85 $gt$libresoc.v:142851$6515_Y connect \$87 $gt$libresoc.v:142852$6516_Y connect \$89 $gt$libresoc.v:142853$6517_Y connect \$91 $gt$libresoc.v:142854$6518_Y connect \$93 $gt$libresoc.v:142855$6519_Y connect \$95 $gt$libresoc.v:142856$6520_Y connect \$97 $gt$libresoc.v:142857$6521_Y end attribute \src "libresoc.v:143250.1-143279.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp attribute \src "libresoc.v:143274.17-143274.101" wire width 64 $extend$libresoc.v:143274$6527_Y attribute \src "libresoc.v:143274.17-143274.101" wire width 64 $pos$libresoc.v:143274$6528_Y attribute \src "libresoc.v:143271.17-143271.111" wire width 20 $sshl$libresoc.v:143271$6524_Y attribute \src "libresoc.v:143273.17-143273.113" wire width 32 $sshl$libresoc.v:143273$6526_Y attribute \src "libresoc.v:143272.17-143272.107" wire width 21 $sub$libresoc.v:143272$6525_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 20 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" wire width 64 \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" wire width 32 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" wire width 4 input 1 \addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" wire width 17 \binlen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" wire width 4 input 4 \len_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" wire width 64 output 2 \lexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" cell $pos $extend$libresoc.v:143274$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 connect \Y $extend$libresoc.v:143274$6527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" cell $pos $pos$libresoc.v:143274$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:143274$6527_Y connect \Y $pos$libresoc.v:143274$6528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" cell $sshl $sshl$libresoc.v:143271$6524 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i connect \Y $sshl$libresoc.v:143271$6524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" cell $sshl $sshl$libresoc.v:143273$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i connect \Y $sshl$libresoc.v:143273$6526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" cell $sub $sub$libresoc.v:143272$6525 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 connect \Y $sub$libresoc.v:143272$6525_Y end connect \$2 $sshl$libresoc.v:143271$6524_Y connect \$4 $sub$libresoc.v:143272$6525_Y connect \$7 $sshl$libresoc.v:143273$6526_Y connect \$6 $pos$libresoc.v:143274$6528_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end attribute \src "libresoc.v:143283.1-143341.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l attribute \src "libresoc.v:143284.7-143284.20" wire $0\initial[0:0] attribute \src "libresoc.v:143329.3-143337.6" wire $0\q_int$next[0:0]$6539 attribute \src "libresoc.v:143327.3-143328.27" wire $0\q_int[0:0] attribute \src "libresoc.v:143329.3-143337.6" wire $1\q_int$next[0:0]$6540 attribute \src "libresoc.v:143306.7-143306.19" wire $1\q_int[0:0] attribute \src "libresoc.v:143319.17-143319.96" wire $and$libresoc.v:143319$6529_Y attribute \src "libresoc.v:143324.17-143324.96" wire $and$libresoc.v:143324$6534_Y attribute \src "libresoc.v:143321.18-143321.93" wire $not$libresoc.v:143321$6531_Y attribute \src "libresoc.v:143323.17-143323.92" wire $not$libresoc.v:143323$6533_Y attribute \src "libresoc.v:143326.17-143326.92" wire $not$libresoc.v:143326$6536_Y attribute \src "libresoc.v:143320.18-143320.98" wire $or$libresoc.v:143320$6530_Y attribute \src "libresoc.v:143322.18-143322.99" wire $or$libresoc.v:143322$6532_Y attribute \src "libresoc.v:143325.17-143325.97" wire $or$libresoc.v:143325$6535_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:143284.7-143284.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire output 4 \qn_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:143319$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:143319$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:143324$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:143324$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:143321$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod connect \Y $not$libresoc.v:143321$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:143323$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod connect \Y $not$libresoc.v:143323$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:143326$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod connect \Y $not$libresoc.v:143326$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:143320$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod connect \Y $or$libresoc.v:143320$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:143322$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int connect \Y $or$libresoc.v:143322$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:143325$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod connect \Y $or$libresoc.v:143325$6535_Y end attribute \src "libresoc.v:143284.7-143284.20" process $proc$libresoc.v:143284$6541 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:143306.7-143306.19" process $proc$libresoc.v:143306$6542 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:143327.3-143328.27" process $proc$libresoc.v:143327$6537 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:143329.3-143337.6" process $proc$libresoc.v:143329$6538 assign { } { } assign { } { } assign $0\q_int$next[0:0]$6539 $1\q_int$next[0:0]$6540 attribute \src "libresoc.v:143330.5-143330.29" switch \initial attribute \src "libresoc.v:143330.9-143330.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$6540 1'0 case assign $1\q_int$next[0:0]$6540 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$6539 end connect \$9 $and$libresoc.v:143319$6529_Y connect \$11 $or$libresoc.v:143320$6530_Y connect \$13 $not$libresoc.v:143321$6531_Y connect \$15 $or$libresoc.v:143322$6532_Y connect \$1 $not$libresoc.v:143323$6533_Y connect \$3 $and$libresoc.v:143324$6534_Y connect \$5 $or$libresoc.v:143325$6535_Y connect \$7 $not$libresoc.v:143326$6536_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end attribute \src "libresoc.v:143345.1-144465.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 attribute \src "libresoc.v:144090.3-144091.24" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:144088.3-144089.44" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:144395.3-144403.6" wire $0\alu_l_r_alu$next[0:0]$6743 attribute \src "libresoc.v:144012.3-144013.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6672 attribute \src "libresoc.v:144062.3-144063.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 attribute \src "libresoc.v:144032.3-144033.81" wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 attribute \src "libresoc.v:144034.3-144035.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 attribute \src "libresoc.v:144036.3-144037.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 attribute \src "libresoc.v:144050.3-144051.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6677 attribute \src "libresoc.v:144064.3-144065.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 attribute \src "libresoc.v:144030.3-144031.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 attribute \src "libresoc.v:144046.3-144047.85" wire $0\alu_logical0_logical_op__invert_in[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 attribute \src "libresoc.v:144052.3-144053.87" wire $0\alu_logical0_logical_op__invert_out[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 attribute \src "libresoc.v:144058.3-144059.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 attribute \src "libresoc.v:144060.3-144061.85" wire $0\alu_logical0_logical_op__is_signed[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 attribute \src "libresoc.v:144042.3-144043.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 attribute \src "libresoc.v:144044.3-144045.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 attribute \src "libresoc.v:144056.3-144057.91" wire $0\alu_logical0_logical_op__output_carry[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 attribute \src "libresoc.v:144040.3-144041.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 attribute \src "libresoc.v:144038.3-144039.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 attribute \src "libresoc.v:144054.3-144055.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 attribute \src "libresoc.v:144048.3-144049.79" wire $0\alu_logical0_logical_op__zero_a[0:0] attribute \src "libresoc.v:144386.3-144394.6" wire $0\alui_l_r_alui$next[0:0]$6740 attribute \src "libresoc.v:144014.3-144015.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:144312.3-144333.6" wire width 64 $0\data_r0__o$next[63:0]$6715 attribute \src "libresoc.v:144026.3-144027.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:144312.3-144333.6" wire $0\data_r0__o_ok$next[0:0]$6716 attribute \src "libresoc.v:144028.3-144029.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:144334.3-144355.6" wire width 4 $0\data_r1__cr_a$next[3:0]$6723 attribute \src "libresoc.v:144022.3-144023.43" wire width 4 $0\data_r1__cr_a[3:0] attribute \src "libresoc.v:144334.3-144355.6" wire $0\data_r1__cr_a_ok$next[0:0]$6724 attribute \src "libresoc.v:144024.3-144025.49" wire $0\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:144404.3-144413.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:144414.3-144423.6" wire width 4 $0\dest2_o[3:0] attribute \src "libresoc.v:143346.7-143346.20" wire $0\initial[0:0] attribute \src "libresoc.v:144228.3-144236.6" wire $0\opc_l_r_opc$next[0:0]$6657 attribute \src "libresoc.v:144074.3-144075.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:144219.3-144227.6" wire $0\opc_l_s_opc$next[0:0]$6654 attribute \src "libresoc.v:144076.3-144077.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:144424.3-144432.6" wire width 2 $0\prev_wr_go$next[1:0]$6748 attribute \src "libresoc.v:144086.3-144087.37" wire width 2 $0\prev_wr_go[1:0] attribute \src "libresoc.v:144173.3-144182.6" wire $0\req_done[0:0] attribute \src "libresoc.v:144264.3-144272.6" wire width 2 $0\req_l_r_req$next[1:0]$6669 attribute \src "libresoc.v:144066.3-144067.39" wire width 2 $0\req_l_r_req[1:0] attribute \src "libresoc.v:144255.3-144263.6" wire width 2 $0\req_l_s_req$next[1:0]$6666 attribute \src "libresoc.v:144068.3-144069.39" wire width 2 $0\req_l_s_req[1:0] attribute \src "libresoc.v:144192.3-144200.6" wire $0\rok_l_r_rdok$next[0:0]$6645 attribute \src "libresoc.v:144082.3-144083.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:144183.3-144191.6" wire $0\rok_l_s_rdok$next[0:0]$6642 attribute \src "libresoc.v:144084.3-144085.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:144210.3-144218.6" wire $0\rst_l_r_rst$next[0:0]$6651 attribute \src "libresoc.v:144078.3-144079.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:144201.3-144209.6" wire $0\rst_l_s_rst$next[0:0]$6648 attribute \src "libresoc.v:144080.3-144081.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:144246.3-144254.6" wire width 3 $0\src_l_r_src$next[2:0]$6663 attribute \src "libresoc.v:144070.3-144071.39" wire width 3 $0\src_l_r_src[2:0] attribute \src "libresoc.v:144237.3-144245.6" wire width 3 $0\src_l_s_src$next[2:0]$6660 attribute \src "libresoc.v:144072.3-144073.39" wire width 3 $0\src_l_s_src[2:0] attribute \src "libresoc.v:144356.3-144365.6" wire width 64 $0\src_r0$next[63:0]$6731 attribute \src "libresoc.v:144020.3-144021.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:144366.3-144375.6" wire width 64 $0\src_r1$next[63:0]$6734 attribute \src "libresoc.v:144018.3-144019.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:144376.3-144385.6" wire $0\src_r2$next[0:0]$6737 attribute \src "libresoc.v:144016.3-144017.29" wire $0\src_r2[0:0] attribute \src "libresoc.v:143464.7-143464.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:143474.7-143474.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:144395.3-144403.6" wire $1\alu_l_r_alu$next[0:0]$6744 attribute \src "libresoc.v:143482.7-143482.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 attribute \src "libresoc.v:143490.13-143490.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 attribute \src "libresoc.v:143509.14-143509.57" wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 attribute \src "libresoc.v:143513.14-143513.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 attribute \src "libresoc.v:143517.7-143517.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 attribute \src "libresoc.v:143525.13-143525.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6695 attribute \src "libresoc.v:143529.14-143529.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 attribute \src "libresoc.v:143608.13-143608.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 attribute \src "libresoc.v:143612.7-143612.48" wire $1\alu_logical0_logical_op__invert_in[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 attribute \src "libresoc.v:143616.7-143616.49" wire $1\alu_logical0_logical_op__invert_out[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 attribute \src "libresoc.v:143620.7-143620.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 attribute \src "libresoc.v:143624.7-143624.48" wire $1\alu_logical0_logical_op__is_signed[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 attribute \src "libresoc.v:143628.7-143628.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 attribute \src "libresoc.v:143632.7-143632.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 attribute \src "libresoc.v:143636.7-143636.51" wire $1\alu_logical0_logical_op__output_carry[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 attribute \src "libresoc.v:143640.7-143640.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 attribute \src "libresoc.v:143644.7-143644.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 attribute \src "libresoc.v:143648.7-143648.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 attribute \src "libresoc.v:143652.7-143652.45" wire $1\alu_logical0_logical_op__zero_a[0:0] attribute \src "libresoc.v:144386.3-144394.6" wire $1\alui_l_r_alui$next[0:0]$6741 attribute \src "libresoc.v:143678.7-143678.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:144312.3-144333.6" wire width 64 $1\data_r0__o$next[63:0]$6717 attribute \src "libresoc.v:143712.14-143712.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:144312.3-144333.6" wire $1\data_r0__o_ok$next[0:0]$6718 attribute \src "libresoc.v:143716.7-143716.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:144334.3-144355.6" wire width 4 $1\data_r1__cr_a$next[3:0]$6725 attribute \src "libresoc.v:143720.13-143720.33" wire width 4 $1\data_r1__cr_a[3:0] attribute \src "libresoc.v:144334.3-144355.6" wire $1\data_r1__cr_a_ok$next[0:0]$6726 attribute \src "libresoc.v:143724.7-143724.30" wire $1\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:144404.3-144413.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:144414.3-144423.6" wire width 4 $1\dest2_o[3:0] attribute \src "libresoc.v:144228.3-144236.6" wire $1\opc_l_r_opc$next[0:0]$6658 attribute \src "libresoc.v:143738.7-143738.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:144219.3-144227.6" wire $1\opc_l_s_opc$next[0:0]$6655 attribute \src "libresoc.v:143742.7-143742.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:144424.3-144432.6" wire width 2 $1\prev_wr_go$next[1:0]$6749 attribute \src "libresoc.v:143876.13-143876.30" wire width 2 $1\prev_wr_go[1:0] attribute \src "libresoc.v:144173.3-144182.6" wire $1\req_done[0:0] attribute \src "libresoc.v:144264.3-144272.6" wire width 2 $1\req_l_r_req$next[1:0]$6670 attribute \src "libresoc.v:143884.13-143884.31" wire width 2 $1\req_l_r_req[1:0] attribute \src "libresoc.v:144255.3-144263.6" wire width 2 $1\req_l_s_req$next[1:0]$6667 attribute \src "libresoc.v:143888.13-143888.31" wire width 2 $1\req_l_s_req[1:0] attribute \src "libresoc.v:144192.3-144200.6" wire $1\rok_l_r_rdok$next[0:0]$6646 attribute \src "libresoc.v:143900.7-143900.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:144183.3-144191.6" wire $1\rok_l_s_rdok$next[0:0]$6643 attribute \src "libresoc.v:143904.7-143904.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:144210.3-144218.6" wire $1\rst_l_r_rst$next[0:0]$6652 attribute \src "libresoc.v:143908.7-143908.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:144201.3-144209.6" wire $1\rst_l_s_rst$next[0:0]$6649 attribute \src "libresoc.v:143912.7-143912.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:144246.3-144254.6" wire width 3 $1\src_l_r_src$next[2:0]$6664 attribute \src "libresoc.v:143926.13-143926.31" wire width 3 $1\src_l_r_src[2:0] attribute \src "libresoc.v:144237.3-144245.6" wire width 3 $1\src_l_s_src$next[2:0]$6661 attribute \src "libresoc.v:143930.13-143930.31" wire width 3 $1\src_l_s_src[2:0] attribute \src "libresoc.v:144356.3-144365.6" wire width 64 $1\src_r0$next[63:0]$6732 attribute \src "libresoc.v:143938.14-143938.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:144366.3-144375.6" wire width 64 $1\src_r1$next[63:0]$6735 attribute \src "libresoc.v:143942.14-143942.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:144376.3-144385.6" wire $1\src_r2$next[0:0]$6738 attribute \src "libresoc.v:143946.7-143946.20" wire $1\src_r2[0:0] attribute \src "libresoc.v:144273.3-144311.6" wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 attribute \src "libresoc.v:144273.3-144311.6" wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 attribute \src "libresoc.v:144312.3-144333.6" wire width 64 $2\data_r0__o$next[63:0]$6719 attribute \src "libresoc.v:144312.3-144333.6" wire $2\data_r0__o_ok$next[0:0]$6720 attribute \src "libresoc.v:144334.3-144355.6" wire width 4 $2\data_r1__cr_a$next[3:0]$6727 attribute \src "libresoc.v:144334.3-144355.6" wire $2\data_r1__cr_a_ok$next[0:0]$6728 attribute \src "libresoc.v:144312.3-144333.6" wire $3\data_r0__o_ok$next[0:0]$6721 attribute \src "libresoc.v:144334.3-144355.6" wire $3\data_r1__cr_a_ok$next[0:0]$6729 attribute \src "libresoc.v:143955.17-143955.109" wire $and$libresoc.v:143955$6543_Y attribute \src "libresoc.v:143956.18-143956.130" wire width 3 $and$libresoc.v:143956$6544_Y attribute \src "libresoc.v:143958.19-143958.114" wire width 3 $and$libresoc.v:143958$6546_Y attribute \src "libresoc.v:143959.19-143959.125" wire $and$libresoc.v:143959$6547_Y attribute \src "libresoc.v:143960.19-143960.125" wire $and$libresoc.v:143960$6548_Y attribute \src "libresoc.v:143961.19-143961.133" wire width 2 $and$libresoc.v:143961$6549_Y attribute \src "libresoc.v:143962.19-143962.121" wire width 2 $and$libresoc.v:143962$6550_Y attribute \src "libresoc.v:143963.19-143963.127" wire $and$libresoc.v:143963$6551_Y attribute \src "libresoc.v:143964.19-143964.127" wire $and$libresoc.v:143964$6552_Y attribute \src "libresoc.v:143966.18-143966.98" wire $and$libresoc.v:143966$6554_Y attribute \src "libresoc.v:143968.18-143968.100" wire $and$libresoc.v:143968$6556_Y attribute \src "libresoc.v:143969.17-143969.123" wire $and$libresoc.v:143969$6557_Y attribute \src "libresoc.v:143970.18-143970.138" wire width 2 $and$libresoc.v:143970$6558_Y attribute \src "libresoc.v:143972.18-143972.119" wire width 2 $and$libresoc.v:143972$6560_Y attribute \src "libresoc.v:143975.18-143975.116" wire $and$libresoc.v:143975$6563_Y attribute \src "libresoc.v:143980.18-143980.113" wire $and$libresoc.v:143980$6568_Y attribute \src "libresoc.v:143981.18-143981.125" wire width 2 $and$libresoc.v:143981$6569_Y attribute \src "libresoc.v:143983.18-143983.112" wire $and$libresoc.v:143983$6571_Y attribute \src "libresoc.v:143986.18-143986.130" wire $and$libresoc.v:143986$6574_Y attribute \src "libresoc.v:143987.18-143987.130" wire $and$libresoc.v:143987$6575_Y attribute \src "libresoc.v:143988.18-143988.117" wire $and$libresoc.v:143988$6576_Y attribute \src "libresoc.v:143993.18-143993.134" wire $and$libresoc.v:143993$6581_Y attribute \src "libresoc.v:143994.18-143994.124" wire width 2 $and$libresoc.v:143994$6582_Y attribute \src "libresoc.v:143997.18-143997.116" wire $and$libresoc.v:143997$6585_Y attribute \src "libresoc.v:143998.18-143998.119" wire $and$libresoc.v:143998$6586_Y attribute \src "libresoc.v:144007.18-144007.138" wire $and$libresoc.v:144007$6595_Y attribute \src "libresoc.v:144008.18-144008.136" wire $and$libresoc.v:144008$6596_Y attribute \src "libresoc.v:144009.18-144009.149" wire width 3 $and$libresoc.v:144009$6597_Y attribute \src "libresoc.v:143982.18-143982.113" wire $eq$libresoc.v:143982$6570_Y attribute \src "libresoc.v:143984.18-143984.119" wire $eq$libresoc.v:143984$6572_Y attribute \src "libresoc.v:143957.19-143957.115" wire width 3 $not$libresoc.v:143957$6545_Y attribute \src "libresoc.v:143965.18-143965.97" wire $not$libresoc.v:143965$6553_Y attribute \src "libresoc.v:143967.18-143967.99" wire $not$libresoc.v:143967$6555_Y attribute \src "libresoc.v:143971.18-143971.113" wire width 2 $not$libresoc.v:143971$6559_Y attribute \src "libresoc.v:143974.18-143974.106" wire $not$libresoc.v:143974$6562_Y attribute \src "libresoc.v:143979.18-143979.124" wire $not$libresoc.v:143979$6567_Y attribute \src "libresoc.v:143985.17-143985.113" wire width 3 $not$libresoc.v:143985$6573_Y attribute \src "libresoc.v:144010.18-144010.133" wire $not$libresoc.v:144010$6598_Y attribute \src "libresoc.v:144011.18-144011.139" wire $not$libresoc.v:144011$6599_Y attribute \src "libresoc.v:143978.18-143978.112" wire $or$libresoc.v:143978$6566_Y attribute \src "libresoc.v:143989.18-143989.122" wire $or$libresoc.v:143989$6577_Y attribute \src "libresoc.v:143990.18-143990.124" wire $or$libresoc.v:143990$6578_Y attribute \src "libresoc.v:143991.18-143991.142" wire width 2 $or$libresoc.v:143991$6579_Y attribute \src "libresoc.v:143992.18-143992.155" wire width 3 $or$libresoc.v:143992$6580_Y attribute \src "libresoc.v:143995.18-143995.120" wire width 2 $or$libresoc.v:143995$6583_Y attribute \src "libresoc.v:143996.17-143996.117" wire width 3 $or$libresoc.v:143996$6584_Y attribute \src "libresoc.v:144002.17-144002.104" wire $reduce_and$libresoc.v:144002$6590_Y attribute \src "libresoc.v:143973.18-143973.106" wire $reduce_or$libresoc.v:143973$6561_Y attribute \src "libresoc.v:143976.18-143976.113" wire $reduce_or$libresoc.v:143976$6564_Y attribute \src "libresoc.v:143977.18-143977.112" wire $reduce_or$libresoc.v:143977$6565_Y attribute \src "libresoc.v:143999.18-143999.162" wire $ternary$libresoc.v:143999$6587_Y attribute \src "libresoc.v:144000.18-144000.163" wire width 64 $ternary$libresoc.v:144000$6588_Y attribute \src "libresoc.v:144001.18-144001.168" wire $ternary$libresoc.v:144001$6589_Y attribute \src "libresoc.v:144003.18-144003.188" wire width 64 $ternary$libresoc.v:144003$6591_Y attribute \src "libresoc.v:144004.18-144004.115" wire width 64 $ternary$libresoc.v:144004$6592_Y attribute \src "libresoc.v:144005.18-144005.125" wire width 64 $ternary$libresoc.v:144005$6593_Y attribute \src "libresoc.v:144006.18-144006.118" wire $ternary$libresoc.v:144006$6594_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 2 \$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 2 \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 2 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 2 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 2 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 2 \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 2 \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 3 \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 2 \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 2 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_logical0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_logical0_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_logical0_logical_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_logical0_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_logical0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_logical0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_logical0_logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_logical0_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_logical0_logical_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_logical0_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_logical0_logical_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_logical0_logical_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_logical0_logical_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_logical0_logical_op__zero_a$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_logical0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_logical0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_logical0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_logical0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_logical0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_logical0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_logical0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_logical0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 2 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 21 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 20 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 24 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 23 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 22 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 input 30 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 2 output 29 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 2 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o attribute \src "libresoc.v:143346.7-143346.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 18 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \oper_i_alu_logical0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 12 \oper_i_alu_logical0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 19 \oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \oper_i_alu_logical0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \oper_i_alu_logical0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \oper_i_alu_logical0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \oper_i_alu_logical0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \oper_i_alu_logical0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \oper_i_alu_logical0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 2 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 2 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 2 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 2 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:143955$6543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 connect \Y $and$libresoc.v:143955$6543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:143956$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } connect \Y $and$libresoc.v:143956$6544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:143958$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 connect \Y $and$libresoc.v:143958$6546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:143959$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:143959$6547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:143960$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:143960$6548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:143961$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } connect \Y $and$libresoc.v:143961$6549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:143962$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:143962$6550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:143963$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:143963$6551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:143964$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:143964$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:143966$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 connect \Y $and$libresoc.v:143966$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:143968$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 connect \Y $and$libresoc.v:143968$6556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:143969$6557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:143969$6557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:143970$6558 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:143970$6558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:143972$6560 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 connect \Y $and$libresoc.v:143972$6560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:143975$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 connect \Y $and$libresoc.v:143975$6563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:143980$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 connect \Y $and$libresoc.v:143980$6568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:143981$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:143981$6569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:143983$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 connect \Y $and$libresoc.v:143983$6571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:143986$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i connect \Y $and$libresoc.v:143986$6574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:143987$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o connect \Y $and$libresoc.v:143987$6575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:143988$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o connect \Y $and$libresoc.v:143988$6576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:143993$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:143993$6581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:143994$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:143994$6582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:143997$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:143997$6585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:143998$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:143998$6586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:144007$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:144007$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:144008$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:144008$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:144009$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:144009$6597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:143982$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 connect \Y $eq$libresoc.v:143982$6570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:143984$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:143984$6572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:143957$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:143957$6545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:143965$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:143965$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:143967$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:143967$6555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:143971$6559 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:143971$6559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:143974$6562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 connect \Y $not$libresoc.v:143974$6562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:143979$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i connect \Y $not$libresoc.v:143979$6567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:143985$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:143985$6573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:144010$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a connect \Y $not$libresoc.v:144010$6598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:144011$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok connect \Y $not$libresoc.v:144011$6599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:143978$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 connect \Y $or$libresoc.v:143978$6566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:143989$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:143989$6577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:143990$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:143990$6578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:143991$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:143991$6579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:143992$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:143992$6580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:143995$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:143995$6583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:143996$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:143996$6584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:144002$6590 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 connect \Y $reduce_and$libresoc.v:144002$6590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:143973$6561 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 connect \Y $reduce_or$libresoc.v:143973$6561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:143976$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:143976$6564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:143977$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:143977$6565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:143999$6587 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a connect \Y $ternary$libresoc.v:143999$6587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:144000$6588 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a connect \Y $ternary$libresoc.v:144000$6588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:144001$6589 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok connect \Y $ternary$libresoc.v:144001$6589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:144003$6591 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok connect \Y $ternary$libresoc.v:144003$6591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:144004$6592 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel connect \Y $ternary$libresoc.v:144004$6592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:144005$6593 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 connect \Y $ternary$libresoc.v:144005$6593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:144006$6594 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:144006$6594_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:144092.14-144098.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:144099.16-144131.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \alu_logical0_cr_a connect \cr_a_ok \cr_a_ok connect \logical_op__data_len \alu_logical0_logical_op__data_len connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok connect \logical_op__input_carry \alu_logical0_logical_op__input_carry connect \logical_op__insn \alu_logical0_logical_op__insn connect \logical_op__insn_type \alu_logical0_logical_op__insn_type connect \logical_op__invert_in \alu_logical0_logical_op__invert_in connect \logical_op__invert_out \alu_logical0_logical_op__invert_out connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit connect \logical_op__is_signed \alu_logical0_logical_op__is_signed connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok connect \logical_op__output_carry \alu_logical0_logical_op__output_carry connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 connect \logical_op__zero_a \alu_logical0_logical_op__zero_a connect \n_ready_i \alu_logical0_n_ready_i connect \n_valid_o \alu_logical0_n_valid_o connect \o \alu_logical0_o connect \o_ok \o_ok connect \p_ready_o \alu_logical0_p_ready_o connect \p_valid_i \alu_logical0_p_valid_i connect \ra \alu_logical0_ra connect \rb \alu_logical0_rb connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 attribute \src "libresoc.v:144132.15-144138.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:144139.14-144145.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:144146.14-144152.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:144153.14-144159.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:144160.14-144165.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:144166.14-144172.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:143346.7-143346.20" process $proc$libresoc.v:143346$6750 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:143464.7-143464.24" process $proc$libresoc.v:143464$6751 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:143474.7-143474.26" process $proc$libresoc.v:143474$6752 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:143482.7-143482.25" process $proc$libresoc.v:143482$6753 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:143490.13-143490.53" process $proc$libresoc.v:143490$6754 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end attribute \src "libresoc.v:143509.14-143509.57" process $proc$libresoc.v:143509$6755 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end attribute \src "libresoc.v:143513.14-143513.76" process $proc$libresoc.v:143513$6756 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:143517.7-143517.51" process $proc$libresoc.v:143517$6757 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:143525.13-143525.56" process $proc$libresoc.v:143525$6758 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end attribute \src "libresoc.v:143529.14-143529.51" process $proc$libresoc.v:143529$6759 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end attribute \src "libresoc.v:143608.13-143608.55" process $proc$libresoc.v:143608$6760 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end attribute \src "libresoc.v:143612.7-143612.48" process $proc$libresoc.v:143612$6761 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end attribute \src "libresoc.v:143616.7-143616.49" process $proc$libresoc.v:143616$6762 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end attribute \src "libresoc.v:143620.7-143620.47" process $proc$libresoc.v:143620$6763 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end attribute \src "libresoc.v:143624.7-143624.48" process $proc$libresoc.v:143624$6764 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end attribute \src "libresoc.v:143628.7-143628.45" process $proc$libresoc.v:143628$6765 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end attribute \src "libresoc.v:143632.7-143632.45" process $proc$libresoc.v:143632$6766 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end attribute \src "libresoc.v:143636.7-143636.51" process $proc$libresoc.v:143636$6767 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end attribute \src "libresoc.v:143640.7-143640.45" process $proc$libresoc.v:143640$6768 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end attribute \src "libresoc.v:143644.7-143644.45" process $proc$libresoc.v:143644$6769 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end attribute \src "libresoc.v:143648.7-143648.48" process $proc$libresoc.v:143648$6770 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end attribute \src "libresoc.v:143652.7-143652.45" process $proc$libresoc.v:143652$6771 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end attribute \src "libresoc.v:143678.7-143678.27" process $proc$libresoc.v:143678$6772 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:143712.14-143712.47" process $proc$libresoc.v:143712$6773 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:143716.7-143716.27" process $proc$libresoc.v:143716$6774 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:143720.13-143720.33" process $proc$libresoc.v:143720$6775 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end attribute \src "libresoc.v:143724.7-143724.30" process $proc$libresoc.v:143724$6776 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:143738.7-143738.25" process $proc$libresoc.v:143738$6777 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:143742.7-143742.25" process $proc$libresoc.v:143742$6778 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:143876.13-143876.30" process $proc$libresoc.v:143876$6779 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end attribute \src "libresoc.v:143884.13-143884.31" process $proc$libresoc.v:143884$6780 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end attribute \src "libresoc.v:143888.13-143888.31" process $proc$libresoc.v:143888$6781 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end attribute \src "libresoc.v:143900.7-143900.26" process $proc$libresoc.v:143900$6782 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:143904.7-143904.26" process $proc$libresoc.v:143904$6783 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:143908.7-143908.25" process $proc$libresoc.v:143908$6784 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:143912.7-143912.25" process $proc$libresoc.v:143912$6785 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:143926.13-143926.31" process $proc$libresoc.v:143926$6786 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end attribute \src "libresoc.v:143930.13-143930.31" process $proc$libresoc.v:143930$6787 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end attribute \src "libresoc.v:143938.14-143938.43" process $proc$libresoc.v:143938$6788 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:143942.14-143942.43" process $proc$libresoc.v:143942$6789 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:143946.7-143946.20" process $proc$libresoc.v:143946$6790 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end attribute \src "libresoc.v:144012.3-144013.39" process $proc$libresoc.v:144012$6600 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:144014.3-144015.43" process $proc$libresoc.v:144014$6601 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:144016.3-144017.29" process $proc$libresoc.v:144016$6602 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end attribute \src "libresoc.v:144018.3-144019.29" process $proc$libresoc.v:144018$6603 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:144020.3-144021.29" process $proc$libresoc.v:144020$6604 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:144022.3-144023.43" process $proc$libresoc.v:144022$6605 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end attribute \src "libresoc.v:144024.3-144025.49" process $proc$libresoc.v:144024$6606 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:144026.3-144027.37" process $proc$libresoc.v:144026$6607 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:144028.3-144029.43" process $proc$libresoc.v:144028$6608 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:144030.3-144031.85" process $proc$libresoc.v:144030$6609 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end attribute \src "libresoc.v:144032.3-144033.81" process $proc$libresoc.v:144032$6610 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end attribute \src "libresoc.v:144034.3-144035.95" process $proc$libresoc.v:144034$6611 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:144036.3-144037.91" process $proc$libresoc.v:144036$6612 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:144038.3-144039.79" process $proc$libresoc.v:144038$6613 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end attribute \src "libresoc.v:144040.3-144041.79" process $proc$libresoc.v:144040$6614 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end attribute \src "libresoc.v:144042.3-144043.79" process $proc$libresoc.v:144042$6615 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end attribute \src "libresoc.v:144044.3-144045.79" process $proc$libresoc.v:144044$6616 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end attribute \src "libresoc.v:144046.3-144047.85" process $proc$libresoc.v:144046$6617 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end attribute \src "libresoc.v:144048.3-144049.79" process $proc$libresoc.v:144048$6618 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end attribute \src "libresoc.v:144050.3-144051.89" process $proc$libresoc.v:144050$6619 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end attribute \src "libresoc.v:144052.3-144053.87" process $proc$libresoc.v:144052$6620 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end attribute \src "libresoc.v:144054.3-144055.85" process $proc$libresoc.v:144054$6621 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end attribute \src "libresoc.v:144056.3-144057.91" process $proc$libresoc.v:144056$6622 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end attribute \src "libresoc.v:144058.3-144059.83" process $proc$libresoc.v:144058$6623 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end attribute \src "libresoc.v:144060.3-144061.85" process $proc$libresoc.v:144060$6624 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end attribute \src "libresoc.v:144062.3-144063.83" process $proc$libresoc.v:144062$6625 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end attribute \src "libresoc.v:144064.3-144065.75" process $proc$libresoc.v:144064$6626 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end attribute \src "libresoc.v:144066.3-144067.39" process $proc$libresoc.v:144066$6627 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end attribute \src "libresoc.v:144068.3-144069.39" process $proc$libresoc.v:144068$6628 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end attribute \src "libresoc.v:144070.3-144071.39" process $proc$libresoc.v:144070$6629 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end attribute \src "libresoc.v:144072.3-144073.39" process $proc$libresoc.v:144072$6630 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end attribute \src "libresoc.v:144074.3-144075.39" process $proc$libresoc.v:144074$6631 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:144076.3-144077.39" process $proc$libresoc.v:144076$6632 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:144078.3-144079.39" process $proc$libresoc.v:144078$6633 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:144080.3-144081.39" process $proc$libresoc.v:144080$6634 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:144082.3-144083.41" process $proc$libresoc.v:144082$6635 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:144084.3-144085.41" process $proc$libresoc.v:144084$6636 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:144086.3-144087.37" process $proc$libresoc.v:144086$6637 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end attribute \src "libresoc.v:144088.3-144089.44" process $proc$libresoc.v:144088$6638 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:144090.3-144091.24" process $proc$libresoc.v:144090$6639 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:144173.3-144182.6" process $proc$libresoc.v:144173$6640 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:144174.5-144174.29" switch \initial attribute \src "libresoc.v:144174.9-144174.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$45 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:144183.3-144191.6" process $proc$libresoc.v:144183$6641 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$6642 $1\rok_l_s_rdok$next[0:0]$6643 attribute \src "libresoc.v:144184.5-144184.29" switch \initial attribute \src "libresoc.v:144184.9-144184.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$6643 1'0 case assign $1\rok_l_s_rdok$next[0:0]$6643 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6642 end attribute \src "libresoc.v:144192.3-144200.6" process $proc$libresoc.v:144192$6644 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$6645 $1\rok_l_r_rdok$next[0:0]$6646 attribute \src "libresoc.v:144193.5-144193.29" switch \initial attribute \src "libresoc.v:144193.9-144193.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$6646 1'1 case assign $1\rok_l_r_rdok$next[0:0]$6646 \$63 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6645 end attribute \src "libresoc.v:144201.3-144209.6" process $proc$libresoc.v:144201$6647 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$6648 $1\rst_l_s_rst$next[0:0]$6649 attribute \src "libresoc.v:144202.5-144202.29" switch \initial attribute \src "libresoc.v:144202.9-144202.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$6649 1'0 case assign $1\rst_l_s_rst$next[0:0]$6649 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6648 end attribute \src "libresoc.v:144210.3-144218.6" process $proc$libresoc.v:144210$6650 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$6651 $1\rst_l_r_rst$next[0:0]$6652 attribute \src "libresoc.v:144211.5-144211.29" switch \initial attribute \src "libresoc.v:144211.9-144211.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$6652 1'1 case assign $1\rst_l_r_rst$next[0:0]$6652 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6651 end attribute \src "libresoc.v:144219.3-144227.6" process $proc$libresoc.v:144219$6653 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$6654 $1\opc_l_s_opc$next[0:0]$6655 attribute \src "libresoc.v:144220.5-144220.29" switch \initial attribute \src "libresoc.v:144220.9-144220.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$6655 1'0 case assign $1\opc_l_s_opc$next[0:0]$6655 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6654 end attribute \src "libresoc.v:144228.3-144236.6" process $proc$libresoc.v:144228$6656 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$6657 $1\opc_l_r_opc$next[0:0]$6658 attribute \src "libresoc.v:144229.5-144229.29" switch \initial attribute \src "libresoc.v:144229.9-144229.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$6658 1'1 case assign $1\opc_l_r_opc$next[0:0]$6658 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6657 end attribute \src "libresoc.v:144237.3-144245.6" process $proc$libresoc.v:144237$6659 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$6660 $1\src_l_s_src$next[2:0]$6661 attribute \src "libresoc.v:144238.5-144238.29" switch \initial attribute \src "libresoc.v:144238.9-144238.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[2:0]$6661 3'000 case assign $1\src_l_s_src$next[2:0]$6661 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6660 end attribute \src "libresoc.v:144246.3-144254.6" process $proc$libresoc.v:144246$6662 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$6663 $1\src_l_r_src$next[2:0]$6664 attribute \src "libresoc.v:144247.5-144247.29" switch \initial attribute \src "libresoc.v:144247.9-144247.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[2:0]$6664 3'111 case assign $1\src_l_r_src$next[2:0]$6664 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6663 end attribute \src "libresoc.v:144255.3-144263.6" process $proc$libresoc.v:144255$6665 assign { } { } assign { } { } assign $0\req_l_s_req$next[1:0]$6666 $1\req_l_s_req$next[1:0]$6667 attribute \src "libresoc.v:144256.5-144256.29" switch \initial attribute \src "libresoc.v:144256.9-144256.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[1:0]$6667 2'00 case assign $1\req_l_s_req$next[1:0]$6667 \$65 end sync always update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6666 end attribute \src "libresoc.v:144264.3-144272.6" process $proc$libresoc.v:144264$6668 assign { } { } assign { } { } assign $0\req_l_r_req$next[1:0]$6669 $1\req_l_r_req$next[1:0]$6670 attribute \src "libresoc.v:144265.5-144265.29" switch \initial attribute \src "libresoc.v:144265.9-144265.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[1:0]$6670 2'11 case assign $1\req_l_r_req$next[1:0]$6670 \$67 end sync always update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6669 end attribute \src "libresoc.v:144273.3-144311.6" process $proc$libresoc.v:144273$6671 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_logical0_logical_op__data_len$next[3:0]$6672 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 assign { } { } assign { } { } assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 assign $0\alu_logical0_logical_op__insn$next[31:0]$6677 $1\alu_logical0_logical_op__insn$next[31:0]$6695 assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 assign { } { } assign { } { } assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 assign { } { } assign { } { } assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 attribute \src "libresoc.v:144274.5-144274.29" switch \initial attribute \src "libresoc.v:144274.9-144274.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_logical0_logical_op__insn$next[31:0]$6695 $1\alu_logical0_logical_op__data_len$next[3:0]$6690 $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case assign $1\alu_logical0_logical_op__data_len$next[3:0]$6690 \alu_logical0_logical_op__data_len assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6691 \alu_logical0_logical_op__fn_unit assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 \alu_logical0_logical_op__imm_data__data assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 \alu_logical0_logical_op__imm_data__ok assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6694 \alu_logical0_logical_op__input_carry assign $1\alu_logical0_logical_op__insn$next[31:0]$6695 \alu_logical0_logical_op__insn assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6696 \alu_logical0_logical_op__insn_type assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6697 \alu_logical0_logical_op__invert_in assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6698 \alu_logical0_logical_op__invert_out assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6699 \alu_logical0_logical_op__is_32bit assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6700 \alu_logical0_logical_op__is_signed assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 \alu_logical0_logical_op__oe__oe assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 \alu_logical0_logical_op__oe__ok assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6703 \alu_logical0_logical_op__output_carry assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 \alu_logical0_logical_op__rc__ok assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 \alu_logical0_logical_op__rc__rc assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6706 \alu_logical0_logical_op__write_cr0 assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6707 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 1'0 assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 1'0 assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 1'0 assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 1'0 assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 1'0 case assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6708 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6692 assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6709 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6693 assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6710 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6701 assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6711 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6702 assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6712 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6704 assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6713 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6705 end sync always update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6672 update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6673 update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6674 update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6675 update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6676 update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6677 update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6678 update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6679 update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6680 update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6681 update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6682 update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6683 update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6684 update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6685 update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6686 update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6687 update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6688 update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6689 end attribute \src "libresoc.v:144312.3-144333.6" process $proc$libresoc.v:144312$6714 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$6715 $2\data_r0__o$next[63:0]$6719 assign { } { } assign $0\data_r0__o_ok$next[0:0]$6716 $3\data_r0__o_ok$next[0:0]$6721 attribute \src "libresoc.v:144313.5-144313.29" switch \initial attribute \src "libresoc.v:144313.9-144313.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$6718 $1\data_r0__o$next[63:0]$6717 } { \o_ok \alu_logical0_o } case assign $1\data_r0__o$next[63:0]$6717 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$6718 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$6720 $2\data_r0__o$next[63:0]$6719 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$6719 $1\data_r0__o$next[63:0]$6717 assign $2\data_r0__o_ok$next[0:0]$6720 $1\data_r0__o_ok$next[0:0]$6718 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$6721 1'0 case assign $3\data_r0__o_ok$next[0:0]$6721 $2\data_r0__o_ok$next[0:0]$6720 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$6715 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6716 end attribute \src "libresoc.v:144334.3-144355.6" process $proc$libresoc.v:144334$6722 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__cr_a$next[3:0]$6723 $2\data_r1__cr_a$next[3:0]$6727 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$6724 $3\data_r1__cr_a_ok$next[0:0]$6729 attribute \src "libresoc.v:144335.5-144335.29" switch \initial attribute \src "libresoc.v:144335.9-144335.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__cr_a_ok$next[0:0]$6726 $1\data_r1__cr_a$next[3:0]$6725 } { \cr_a_ok \alu_logical0_cr_a } case assign $1\data_r1__cr_a$next[3:0]$6725 \data_r1__cr_a assign $1\data_r1__cr_a_ok$next[0:0]$6726 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__cr_a_ok$next[0:0]$6728 $2\data_r1__cr_a$next[3:0]$6727 } 5'00000 case assign $2\data_r1__cr_a$next[3:0]$6727 $1\data_r1__cr_a$next[3:0]$6725 assign $2\data_r1__cr_a_ok$next[0:0]$6728 $1\data_r1__cr_a_ok$next[0:0]$6726 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__cr_a_ok$next[0:0]$6729 1'0 case assign $3\data_r1__cr_a_ok$next[0:0]$6729 $2\data_r1__cr_a_ok$next[0:0]$6728 end sync always update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6723 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6724 end attribute \src "libresoc.v:144356.3-144365.6" process $proc$libresoc.v:144356$6730 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$6731 $1\src_r0$next[63:0]$6732 attribute \src "libresoc.v:144357.5-144357.29" switch \initial attribute \src "libresoc.v:144357.9-144357.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$6732 \src_or_imm case assign $1\src_r0$next[63:0]$6732 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$6731 end attribute \src "libresoc.v:144366.3-144375.6" process $proc$libresoc.v:144366$6733 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$6734 $1\src_r1$next[63:0]$6735 attribute \src "libresoc.v:144367.5-144367.29" switch \initial attribute \src "libresoc.v:144367.9-144367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$6735 \src_or_imm$80 case assign $1\src_r1$next[63:0]$6735 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$6734 end attribute \src "libresoc.v:144376.3-144385.6" process $proc$libresoc.v:144376$6736 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$6737 $1\src_r2$next[0:0]$6738 attribute \src "libresoc.v:144377.5-144377.29" switch \initial attribute \src "libresoc.v:144377.9-144377.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[0:0]$6738 \src3_i case assign $1\src_r2$next[0:0]$6738 \src_r2 end sync always update \src_r2$next $0\src_r2$next[0:0]$6737 end attribute \src "libresoc.v:144386.3-144394.6" process $proc$libresoc.v:144386$6739 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$6740 $1\alui_l_r_alui$next[0:0]$6741 attribute \src "libresoc.v:144387.5-144387.29" switch \initial attribute \src "libresoc.v:144387.9-144387.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$6741 1'1 case assign $1\alui_l_r_alui$next[0:0]$6741 \$89 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6740 end attribute \src "libresoc.v:144395.3-144403.6" process $proc$libresoc.v:144395$6742 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$6743 $1\alu_l_r_alu$next[0:0]$6744 attribute \src "libresoc.v:144396.5-144396.29" switch \initial attribute \src "libresoc.v:144396.9-144396.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$6744 1'1 case assign $1\alu_l_r_alu$next[0:0]$6744 \$91 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6743 end attribute \src "libresoc.v:144404.3-144413.6" process $proc$libresoc.v:144404$6745 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:144405.5-144405.29" switch \initial attribute \src "libresoc.v:144405.9-144405.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:144414.3-144423.6" process $proc$libresoc.v:144414$6746 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] attribute \src "libresoc.v:144415.5-144415.29" switch \initial attribute \src "libresoc.v:144415.9-144415.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[3:0] \data_r1__cr_a case assign $1\dest2_o[3:0] 4'0000 end sync always update \dest2_o $0\dest2_o[3:0] end attribute \src "libresoc.v:144424.3-144432.6" process $proc$libresoc.v:144424$6747 assign { } { } assign { } { } assign $0\prev_wr_go$next[1:0]$6748 $1\prev_wr_go$next[1:0]$6749 attribute \src "libresoc.v:144425.5-144425.29" switch \initial attribute \src "libresoc.v:144425.9-144425.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[1:0]$6749 2'00 case assign $1\prev_wr_go$next[1:0]$6749 \$19 end sync always update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6748 end connect \$9 $and$libresoc.v:143955$6543_Y connect \$99 $and$libresoc.v:143956$6544_Y connect \$101 $not$libresoc.v:143957$6545_Y connect \$103 $and$libresoc.v:143958$6546_Y connect \$105 $and$libresoc.v:143959$6547_Y connect \$107 $and$libresoc.v:143960$6548_Y connect \$109 $and$libresoc.v:143961$6549_Y connect \$111 $and$libresoc.v:143962$6550_Y connect \$113 $and$libresoc.v:143963$6551_Y connect \$115 $and$libresoc.v:143964$6552_Y connect \$11 $not$libresoc.v:143965$6553_Y connect \$13 $and$libresoc.v:143966$6554_Y connect \$15 $not$libresoc.v:143967$6555_Y connect \$17 $and$libresoc.v:143968$6556_Y connect \$1 $and$libresoc.v:143969$6557_Y connect \$19 $and$libresoc.v:143970$6558_Y connect \$23 $not$libresoc.v:143971$6559_Y connect \$25 $and$libresoc.v:143972$6560_Y connect \$22 $reduce_or$libresoc.v:143973$6561_Y connect \$21 $not$libresoc.v:143974$6562_Y connect \$29 $and$libresoc.v:143975$6563_Y connect \$31 $reduce_or$libresoc.v:143976$6564_Y connect \$33 $reduce_or$libresoc.v:143977$6565_Y connect \$35 $or$libresoc.v:143978$6566_Y connect \$37 $not$libresoc.v:143979$6567_Y connect \$39 $and$libresoc.v:143980$6568_Y connect \$41 $and$libresoc.v:143981$6569_Y connect \$43 $eq$libresoc.v:143982$6570_Y connect \$45 $and$libresoc.v:143983$6571_Y connect \$47 $eq$libresoc.v:143984$6572_Y connect \$4 $not$libresoc.v:143985$6573_Y connect \$49 $and$libresoc.v:143986$6574_Y connect \$51 $and$libresoc.v:143987$6575_Y connect \$53 $and$libresoc.v:143988$6576_Y connect \$55 $or$libresoc.v:143989$6577_Y connect \$57 $or$libresoc.v:143990$6578_Y connect \$59 $or$libresoc.v:143991$6579_Y connect \$61 $or$libresoc.v:143992$6580_Y connect \$63 $and$libresoc.v:143993$6581_Y connect \$65 $and$libresoc.v:143994$6582_Y connect \$67 $or$libresoc.v:143995$6583_Y connect \$6 $or$libresoc.v:143996$6584_Y connect \$69 $and$libresoc.v:143997$6585_Y connect \$71 $and$libresoc.v:143998$6586_Y connect \$73 $ternary$libresoc.v:143999$6587_Y connect \$75 $ternary$libresoc.v:144000$6588_Y connect \$78 $ternary$libresoc.v:144001$6589_Y connect \$3 $reduce_and$libresoc.v:144002$6590_Y connect \$81 $ternary$libresoc.v:144003$6591_Y connect \$83 $ternary$libresoc.v:144004$6592_Y connect \$85 $ternary$libresoc.v:144005$6593_Y connect \$87 $ternary$libresoc.v:144006$6594_Y connect \$89 $and$libresoc.v:144007$6595_Y connect \$91 $and$libresoc.v:144008$6596_Y connect \$93 $and$libresoc.v:144009$6597_Y connect \$95 $not$libresoc.v:144010$6598_Y connect \$97 $not$libresoc.v:144011$6599_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 connect \cu_rd__rel_o \$103 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_logical0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_logical0_p_valid_i \alui_l_q_alui connect \alu_logical0_xer_so \$87 connect \alu_logical0_rb \$85 connect \alu_logical0_ra \$83 connect \src_or_imm$80 \$81 connect \src_sel$77 \$78 connect \src_or_imm \$75 connect \src_sel \$73 connect \cu_wrmask_o { \$71 \$69 } connect \reset_r \$61 connect \reset_w \$59 connect \rst_r \$57 connect \reset \$55 connect \wr_any \$35 connect \cu_done_o \$29 connect \alu_pulsem { \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$17 connect \alu_done_dly$next \alu_done connect \alu_done \alu_logical0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$13 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end attribute \src "libresoc.v:144469.1-145860.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 attribute \src "libresoc.v:145799.3-145817.6" wire width 4 $0\cr_a$next[3:0]$6875 attribute \src "libresoc.v:145559.3-145560.25" wire width 4 $0\cr_a[3:0] attribute \src "libresoc.v:145799.3-145817.6" wire $0\cr_a_ok$next[0:0]$6876 attribute \src "libresoc.v:145561.3-145562.31" wire $0\cr_a_ok[0:0] attribute \src "libresoc.v:144470.7-144470.20" wire $0\initial[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 4 $0\logical_op__data_len$next[3:0]$6826 attribute \src "libresoc.v:145599.3-145600.57" wire width 4 $0\logical_op__data_len[3:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 14 $0\logical_op__fn_unit$next[13:0]$6827 attribute \src "libresoc.v:145569.3-145570.55" wire width 14 $0\logical_op__fn_unit[13:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 64 $0\logical_op__imm_data__data$next[63:0]$6828 attribute \src "libresoc.v:145571.3-145572.69" wire width 64 $0\logical_op__imm_data__data[63:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__imm_data__ok$next[0:0]$6829 attribute \src "libresoc.v:145573.3-145574.65" wire $0\logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 2 $0\logical_op__input_carry$next[1:0]$6830 attribute \src "libresoc.v:145587.3-145588.63" wire width 2 $0\logical_op__input_carry[1:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 32 $0\logical_op__insn$next[31:0]$6831 attribute \src "libresoc.v:145601.3-145602.49" wire width 32 $0\logical_op__insn[31:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 7 $0\logical_op__insn_type$next[6:0]$6832 attribute \src "libresoc.v:145567.3-145568.59" wire width 7 $0\logical_op__insn_type[6:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__invert_in$next[0:0]$6833 attribute \src "libresoc.v:145583.3-145584.59" wire $0\logical_op__invert_in[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__invert_out$next[0:0]$6834 attribute \src "libresoc.v:145589.3-145590.61" wire $0\logical_op__invert_out[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__is_32bit$next[0:0]$6835 attribute \src "libresoc.v:145595.3-145596.57" wire $0\logical_op__is_32bit[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__is_signed$next[0:0]$6836 attribute \src "libresoc.v:145597.3-145598.59" wire $0\logical_op__is_signed[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__oe__oe$next[0:0]$6837 attribute \src "libresoc.v:145579.3-145580.53" wire $0\logical_op__oe__oe[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__oe__ok$next[0:0]$6838 attribute \src "libresoc.v:145581.3-145582.53" wire $0\logical_op__oe__ok[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__output_carry$next[0:0]$6839 attribute \src "libresoc.v:145593.3-145594.65" wire $0\logical_op__output_carry[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__rc__ok$next[0:0]$6840 attribute \src "libresoc.v:145577.3-145578.53" wire $0\logical_op__rc__ok[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__rc__rc$next[0:0]$6841 attribute \src "libresoc.v:145575.3-145576.53" wire $0\logical_op__rc__rc[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__write_cr0$next[0:0]$6842 attribute \src "libresoc.v:145591.3-145592.59" wire $0\logical_op__write_cr0[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $0\logical_op__zero_a$next[0:0]$6843 attribute \src "libresoc.v:145585.3-145586.53" wire $0\logical_op__zero_a[0:0] attribute \src "libresoc.v:145725.3-145737.6" wire width 2 $0\muxid$next[1:0]$6823 attribute \src "libresoc.v:145603.3-145604.27" wire width 2 $0\muxid[1:0] attribute \src "libresoc.v:145780.3-145798.6" wire width 64 $0\o$next[63:0]$6869 attribute \src "libresoc.v:145563.3-145564.19" wire width 64 $0\o[63:0] attribute \src "libresoc.v:145780.3-145798.6" wire $0\o_ok$next[0:0]$6870 attribute \src "libresoc.v:145565.3-145566.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:145707.3-145724.6" wire $0\r_busy$next[0:0]$6819 attribute \src "libresoc.v:145605.3-145606.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:145818.3-145836.6" wire $0\xer_so$next[0:0]$6881 attribute \src "libresoc.v:145555.3-145556.29" wire $0\xer_so[0:0] attribute \src "libresoc.v:145818.3-145836.6" wire $0\xer_so_ok$next[0:0]$6882 attribute \src "libresoc.v:145557.3-145558.35" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:145799.3-145817.6" wire width 4 $1\cr_a$next[3:0]$6877 attribute \src "libresoc.v:144479.13-144479.24" wire width 4 $1\cr_a[3:0] attribute \src "libresoc.v:145799.3-145817.6" wire $1\cr_a_ok$next[0:0]$6878 attribute \src "libresoc.v:144488.7-144488.21" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 4 $1\logical_op__data_len$next[3:0]$6844 attribute \src "libresoc.v:144773.13-144773.40" wire width 4 $1\logical_op__data_len[3:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 14 $1\logical_op__fn_unit$next[13:0]$6845 attribute \src "libresoc.v:144797.14-144797.44" wire width 14 $1\logical_op__fn_unit[13:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 64 $1\logical_op__imm_data__data$next[63:0]$6846 attribute \src "libresoc.v:144836.14-144836.63" wire width 64 $1\logical_op__imm_data__data[63:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__imm_data__ok$next[0:0]$6847 attribute \src "libresoc.v:144845.7-144845.38" wire $1\logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 2 $1\logical_op__input_carry$next[1:0]$6848 attribute \src "libresoc.v:144858.13-144858.43" wire width 2 $1\logical_op__input_carry[1:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 32 $1\logical_op__insn$next[31:0]$6849 attribute \src "libresoc.v:144875.14-144875.38" wire width 32 $1\logical_op__insn[31:0] attribute \src "libresoc.v:145738.3-145779.6" wire width 7 $1\logical_op__insn_type$next[6:0]$6850 attribute \src "libresoc.v:144959.13-144959.42" wire width 7 $1\logical_op__insn_type[6:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__invert_in$next[0:0]$6851 attribute \src "libresoc.v:145118.7-145118.35" wire $1\logical_op__invert_in[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__invert_out$next[0:0]$6852 attribute \src "libresoc.v:145127.7-145127.36" wire $1\logical_op__invert_out[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__is_32bit$next[0:0]$6853 attribute \src "libresoc.v:145136.7-145136.34" wire $1\logical_op__is_32bit[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__is_signed$next[0:0]$6854 attribute \src "libresoc.v:145145.7-145145.35" wire $1\logical_op__is_signed[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__oe__oe$next[0:0]$6855 attribute \src "libresoc.v:145154.7-145154.32" wire $1\logical_op__oe__oe[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__oe__ok$next[0:0]$6856 attribute \src "libresoc.v:145163.7-145163.32" wire $1\logical_op__oe__ok[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__output_carry$next[0:0]$6857 attribute \src "libresoc.v:145172.7-145172.38" wire $1\logical_op__output_carry[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__rc__ok$next[0:0]$6858 attribute \src "libresoc.v:145181.7-145181.32" wire $1\logical_op__rc__ok[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__rc__rc$next[0:0]$6859 attribute \src "libresoc.v:145190.7-145190.32" wire $1\logical_op__rc__rc[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__write_cr0$next[0:0]$6860 attribute \src "libresoc.v:145199.7-145199.35" wire $1\logical_op__write_cr0[0:0] attribute \src "libresoc.v:145738.3-145779.6" wire $1\logical_op__zero_a$next[0:0]$6861 attribute \src "libresoc.v:145208.7-145208.32" wire $1\logical_op__zero_a[0:0] attribute \src "libresoc.v:145725.3-145737.6" wire width 2 $1\muxid$next[1:0]$6824 attribute \src "libresoc.v:145493.13-145493.25" wire width 2 $1\muxid[1:0] attribute \src "libresoc.v:145780.3-145798.6" wire width 64 $1\o$next[63:0]$6871 attribute \src "libresoc.v:145508.14-145508.38" wire width 64 $1\o[63:0] attribute \src "libresoc.v:145780.3-145798.6" wire $1\o_ok$next[0:0]$6872 attribute \src "libresoc.v:145515.7-145515.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:145707.3-145724.6" wire $1\r_busy$next[0:0]$6820 attribute \src "libresoc.v:145529.7-145529.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:145818.3-145836.6" wire $1\xer_so$next[0:0]$6883 attribute \src "libresoc.v:145538.7-145538.20" wire $1\xer_so[0:0] attribute \src "libresoc.v:145818.3-145836.6" wire $1\xer_so_ok$next[0:0]$6884 attribute \src "libresoc.v:145547.7-145547.23" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:145799.3-145817.6" wire $2\cr_a_ok$next[0:0]$6879 attribute \src "libresoc.v:145738.3-145779.6" wire width 64 $2\logical_op__imm_data__data$next[63:0]$6862 attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__imm_data__ok$next[0:0]$6863 attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__oe__oe$next[0:0]$6864 attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__oe__ok$next[0:0]$6865 attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__rc__ok$next[0:0]$6866 attribute \src "libresoc.v:145738.3-145779.6" wire $2\logical_op__rc__rc$next[0:0]$6867 attribute \src "libresoc.v:145780.3-145798.6" wire $2\o_ok$next[0:0]$6873 attribute \src "libresoc.v:145707.3-145724.6" wire $2\r_busy$next[0:0]$6821 attribute \src "libresoc.v:145818.3-145836.6" wire $2\xer_so_ok$next[0:0]$6885 attribute \src "libresoc.v:145554.18-145554.118" wire $and$libresoc.v:145554$6791_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 53 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "libresoc.v:144470.7-144470.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len$38 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_logical_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__imm_data__ok$25 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_logical_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_logical_op__insn$39 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__zero_a$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 48 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 6 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 33 \logical_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 34 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 35 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 15 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 42 \logical_op__input_carry$12 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 49 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 32 \logical_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 40 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 43 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 46 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 47 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 38 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 39 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 45 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 37 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 36 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 44 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 41 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \main_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \main_logical_op__data_len$60 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_logical_op__fn_unit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_logical_op__imm_data__data$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__imm_data__ok$47 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \main_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \main_logical_op__input_carry$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_logical_op__insn$61 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_logical_op__insn_type$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__invert_in$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__invert_out$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__is_32bit$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__is_signed$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__oe__oe$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__oe__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__output_carry$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__rc__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__rc__rc$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__write_cr0$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_logical_op__zero_a$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_so$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 31 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 23 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 30 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 29 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 50 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 51 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 52 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:145554$6791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o connect \Y $and$libresoc.v:145554$6791_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:145607.14-145652.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 connect \logical_op__fn_unit \input_logical_op__fn_unit connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 connect \logical_op__imm_data__data \input_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 connect \logical_op__input_carry \input_logical_op__input_carry connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 connect \logical_op__insn \input_logical_op__insn connect \logical_op__insn$19 \input_logical_op__insn$39 connect \logical_op__insn_type \input_logical_op__insn_type connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 connect \logical_op__invert_in \input_logical_op__invert_in connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 connect \logical_op__invert_out \input_logical_op__invert_out connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 connect \logical_op__is_32bit \input_logical_op__is_32bit connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 connect \logical_op__is_signed \input_logical_op__is_signed connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 connect \logical_op__oe__oe \input_logical_op__oe__oe connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 connect \logical_op__oe__ok \input_logical_op__oe__ok connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 connect \logical_op__output_carry \input_logical_op__output_carry connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 connect \logical_op__rc__ok \input_logical_op__rc__ok connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 connect \logical_op__rc__rc \input_logical_op__rc__rc connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 connect \logical_op__write_cr0 \input_logical_op__write_cr0 connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 connect \logical_op__zero_a \input_logical_op__zero_a connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 connect \ra \input_ra connect \ra$20 \input_ra$40 connect \rb \input_rb connect \rb$21 \input_rb$41 connect \xer_so \input_xer_so connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 attribute \src "libresoc.v:145653.13-145698.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 connect \logical_op__fn_unit \main_logical_op__fn_unit connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 connect \logical_op__imm_data__data \main_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 connect \logical_op__input_carry \main_logical_op__input_carry connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 connect \logical_op__insn \main_logical_op__insn connect \logical_op__insn$19 \main_logical_op__insn$61 connect \logical_op__insn_type \main_logical_op__insn_type connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 connect \logical_op__invert_in \main_logical_op__invert_in connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 connect \logical_op__invert_out \main_logical_op__invert_out connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 connect \logical_op__is_32bit \main_logical_op__is_32bit connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 connect \logical_op__is_signed \main_logical_op__is_signed connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 connect \logical_op__oe__oe \main_logical_op__oe__oe connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 connect \logical_op__oe__ok \main_logical_op__oe__ok connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 connect \logical_op__output_carry \main_logical_op__output_carry connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 connect \logical_op__rc__ok \main_logical_op__rc__ok connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 connect \logical_op__rc__rc \main_logical_op__rc__rc connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 connect \logical_op__write_cr0 \main_logical_op__write_cr0 connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 connect \logical_op__zero_a \main_logical_op__zero_a connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 connect \muxid \main_muxid connect \muxid$1 \main_muxid$43 connect \o \main_o connect \o_ok \main_o_ok connect \ra \main_ra connect \rb \main_rb connect \xer_so \main_xer_so connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 attribute \src "libresoc.v:145699.10-145702.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:145703.10-145706.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:144470.7-144470.20" process $proc$libresoc.v:144470$6886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:144479.13-144479.24" process $proc$libresoc.v:144479$6887 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end attribute \src "libresoc.v:144488.7-144488.21" process $proc$libresoc.v:144488$6888 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end attribute \src "libresoc.v:144773.13-144773.40" process $proc$libresoc.v:144773$6889 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end attribute \src "libresoc.v:144797.14-144797.44" process $proc$libresoc.v:144797$6890 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end attribute \src "libresoc.v:144836.14-144836.63" process $proc$libresoc.v:144836$6891 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:144845.7-144845.38" process $proc$libresoc.v:144845$6892 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:144858.13-144858.43" process $proc$libresoc.v:144858$6893 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end attribute \src "libresoc.v:144875.14-144875.38" process $proc$libresoc.v:144875$6894 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end attribute \src "libresoc.v:144959.13-144959.42" process $proc$libresoc.v:144959$6895 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end attribute \src "libresoc.v:145118.7-145118.35" process $proc$libresoc.v:145118$6896 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end attribute \src "libresoc.v:145127.7-145127.36" process $proc$libresoc.v:145127$6897 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end attribute \src "libresoc.v:145136.7-145136.34" process $proc$libresoc.v:145136$6898 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end attribute \src "libresoc.v:145145.7-145145.35" process $proc$libresoc.v:145145$6899 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end attribute \src "libresoc.v:145154.7-145154.32" process $proc$libresoc.v:145154$6900 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end attribute \src "libresoc.v:145163.7-145163.32" process $proc$libresoc.v:145163$6901 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end attribute \src "libresoc.v:145172.7-145172.38" process $proc$libresoc.v:145172$6902 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end attribute \src "libresoc.v:145181.7-145181.32" process $proc$libresoc.v:145181$6903 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end attribute \src "libresoc.v:145190.7-145190.32" process $proc$libresoc.v:145190$6904 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end attribute \src "libresoc.v:145199.7-145199.35" process $proc$libresoc.v:145199$6905 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end attribute \src "libresoc.v:145208.7-145208.32" process $proc$libresoc.v:145208$6906 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end attribute \src "libresoc.v:145493.13-145493.25" process $proc$libresoc.v:145493$6907 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end attribute \src "libresoc.v:145508.14-145508.38" process $proc$libresoc.v:145508$6908 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end attribute \src "libresoc.v:145515.7-145515.18" process $proc$libresoc.v:145515$6909 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:145529.7-145529.20" process $proc$libresoc.v:145529$6910 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:145538.7-145538.20" process $proc$libresoc.v:145538$6911 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end attribute \src "libresoc.v:145547.7-145547.23" process $proc$libresoc.v:145547$6912 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end attribute \src "libresoc.v:145555.3-145556.29" process $proc$libresoc.v:145555$6792 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end attribute \src "libresoc.v:145557.3-145558.35" process $proc$libresoc.v:145557$6793 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:145559.3-145560.25" process $proc$libresoc.v:145559$6794 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end attribute \src "libresoc.v:145561.3-145562.31" process $proc$libresoc.v:145561$6795 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end attribute \src "libresoc.v:145563.3-145564.19" process $proc$libresoc.v:145563$6796 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end attribute \src "libresoc.v:145565.3-145566.25" process $proc$libresoc.v:145565$6797 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:145567.3-145568.59" process $proc$libresoc.v:145567$6798 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end attribute \src "libresoc.v:145569.3-145570.55" process $proc$libresoc.v:145569$6799 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end attribute \src "libresoc.v:145571.3-145572.69" process $proc$libresoc.v:145571$6800 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:145573.3-145574.65" process $proc$libresoc.v:145573$6801 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:145575.3-145576.53" process $proc$libresoc.v:145575$6802 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end attribute \src "libresoc.v:145577.3-145578.53" process $proc$libresoc.v:145577$6803 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end attribute \src "libresoc.v:145579.3-145580.53" process $proc$libresoc.v:145579$6804 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end attribute \src "libresoc.v:145581.3-145582.53" process $proc$libresoc.v:145581$6805 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end attribute \src "libresoc.v:145583.3-145584.59" process $proc$libresoc.v:145583$6806 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end attribute \src "libresoc.v:145585.3-145586.53" process $proc$libresoc.v:145585$6807 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end attribute \src "libresoc.v:145587.3-145588.63" process $proc$libresoc.v:145587$6808 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end attribute \src "libresoc.v:145589.3-145590.61" process $proc$libresoc.v:145589$6809 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end attribute \src "libresoc.v:145591.3-145592.59" process $proc$libresoc.v:145591$6810 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end attribute \src "libresoc.v:145593.3-145594.65" process $proc$libresoc.v:145593$6811 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end attribute \src "libresoc.v:145595.3-145596.57" process $proc$libresoc.v:145595$6812 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end attribute \src "libresoc.v:145597.3-145598.59" process $proc$libresoc.v:145597$6813 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end attribute \src "libresoc.v:145599.3-145600.57" process $proc$libresoc.v:145599$6814 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end attribute \src "libresoc.v:145601.3-145602.49" process $proc$libresoc.v:145601$6815 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end attribute \src "libresoc.v:145603.3-145604.27" process $proc$libresoc.v:145603$6816 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end attribute \src "libresoc.v:145605.3-145606.29" process $proc$libresoc.v:145605$6817 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:145707.3-145724.6" process $proc$libresoc.v:145707$6818 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$6819 $2\r_busy$next[0:0]$6821 attribute \src "libresoc.v:145708.5-145708.29" switch \initial attribute \src "libresoc.v:145708.9-145708.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$6820 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$6820 1'0 case assign $1\r_busy$next[0:0]$6820 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$6821 1'0 case assign $2\r_busy$next[0:0]$6821 $1\r_busy$next[0:0]$6820 end sync always update \r_busy$next $0\r_busy$next[0:0]$6819 end attribute \src "libresoc.v:145725.3-145737.6" process $proc$libresoc.v:145725$6822 assign { } { } assign { } { } assign $0\muxid$next[1:0]$6823 $1\muxid$next[1:0]$6824 attribute \src "libresoc.v:145726.5-145726.29" switch \initial attribute \src "libresoc.v:145726.9-145726.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$next[1:0]$6824 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$next[1:0]$6824 \muxid$66 case assign $1\muxid$next[1:0]$6824 \muxid end sync always update \muxid$next $0\muxid$next[1:0]$6823 end attribute \src "libresoc.v:145738.3-145779.6" process $proc$libresoc.v:145738$6825 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\logical_op__data_len$next[3:0]$6826 $1\logical_op__data_len$next[3:0]$6844 assign $0\logical_op__fn_unit$next[13:0]$6827 $1\logical_op__fn_unit$next[13:0]$6845 assign { } { } assign { } { } assign $0\logical_op__input_carry$next[1:0]$6830 $1\logical_op__input_carry$next[1:0]$6848 assign $0\logical_op__insn$next[31:0]$6831 $1\logical_op__insn$next[31:0]$6849 assign $0\logical_op__insn_type$next[6:0]$6832 $1\logical_op__insn_type$next[6:0]$6850 assign $0\logical_op__invert_in$next[0:0]$6833 $1\logical_op__invert_in$next[0:0]$6851 assign $0\logical_op__invert_out$next[0:0]$6834 $1\logical_op__invert_out$next[0:0]$6852 assign $0\logical_op__is_32bit$next[0:0]$6835 $1\logical_op__is_32bit$next[0:0]$6853 assign $0\logical_op__is_signed$next[0:0]$6836 $1\logical_op__is_signed$next[0:0]$6854 assign { } { } assign { } { } assign $0\logical_op__output_carry$next[0:0]$6839 $1\logical_op__output_carry$next[0:0]$6857 assign { } { } assign { } { } assign $0\logical_op__write_cr0$next[0:0]$6842 $1\logical_op__write_cr0$next[0:0]$6860 assign $0\logical_op__zero_a$next[0:0]$6843 $1\logical_op__zero_a$next[0:0]$6861 assign $0\logical_op__imm_data__data$next[63:0]$6828 $2\logical_op__imm_data__data$next[63:0]$6862 assign $0\logical_op__imm_data__ok$next[0:0]$6829 $2\logical_op__imm_data__ok$next[0:0]$6863 assign $0\logical_op__oe__oe$next[0:0]$6837 $2\logical_op__oe__oe$next[0:0]$6864 assign $0\logical_op__oe__ok$next[0:0]$6838 $2\logical_op__oe__ok$next[0:0]$6865 assign $0\logical_op__rc__ok$next[0:0]$6840 $2\logical_op__rc__ok$next[0:0]$6866 assign $0\logical_op__rc__rc$next[0:0]$6841 $2\logical_op__rc__rc$next[0:0]$6867 attribute \src "libresoc.v:145739.5-145739.29" switch \initial attribute \src "libresoc.v:145739.9-145739.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$next[31:0]$6849 $1\logical_op__data_len$next[3:0]$6844 $1\logical_op__is_signed$next[0:0]$6854 $1\logical_op__is_32bit$next[0:0]$6853 $1\logical_op__output_carry$next[0:0]$6857 $1\logical_op__write_cr0$next[0:0]$6860 $1\logical_op__invert_out$next[0:0]$6852 $1\logical_op__input_carry$next[1:0]$6848 $1\logical_op__zero_a$next[0:0]$6861 $1\logical_op__invert_in$next[0:0]$6851 $1\logical_op__oe__ok$next[0:0]$6856 $1\logical_op__oe__oe$next[0:0]$6855 $1\logical_op__rc__ok$next[0:0]$6858 $1\logical_op__rc__rc$next[0:0]$6859 $1\logical_op__imm_data__ok$next[0:0]$6847 $1\logical_op__imm_data__data$next[63:0]$6846 $1\logical_op__fn_unit$next[13:0]$6845 $1\logical_op__insn_type$next[6:0]$6850 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$next[31:0]$6849 $1\logical_op__data_len$next[3:0]$6844 $1\logical_op__is_signed$next[0:0]$6854 $1\logical_op__is_32bit$next[0:0]$6853 $1\logical_op__output_carry$next[0:0]$6857 $1\logical_op__write_cr0$next[0:0]$6860 $1\logical_op__invert_out$next[0:0]$6852 $1\logical_op__input_carry$next[1:0]$6848 $1\logical_op__zero_a$next[0:0]$6861 $1\logical_op__invert_in$next[0:0]$6851 $1\logical_op__oe__ok$next[0:0]$6856 $1\logical_op__oe__oe$next[0:0]$6855 $1\logical_op__rc__ok$next[0:0]$6858 $1\logical_op__rc__rc$next[0:0]$6859 $1\logical_op__imm_data__ok$next[0:0]$6847 $1\logical_op__imm_data__data$next[63:0]$6846 $1\logical_op__fn_unit$next[13:0]$6845 $1\logical_op__insn_type$next[6:0]$6850 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case assign $1\logical_op__data_len$next[3:0]$6844 \logical_op__data_len assign $1\logical_op__fn_unit$next[13:0]$6845 \logical_op__fn_unit assign $1\logical_op__imm_data__data$next[63:0]$6846 \logical_op__imm_data__data assign $1\logical_op__imm_data__ok$next[0:0]$6847 \logical_op__imm_data__ok assign $1\logical_op__input_carry$next[1:0]$6848 \logical_op__input_carry assign $1\logical_op__insn$next[31:0]$6849 \logical_op__insn assign $1\logical_op__insn_type$next[6:0]$6850 \logical_op__insn_type assign $1\logical_op__invert_in$next[0:0]$6851 \logical_op__invert_in assign $1\logical_op__invert_out$next[0:0]$6852 \logical_op__invert_out assign $1\logical_op__is_32bit$next[0:0]$6853 \logical_op__is_32bit assign $1\logical_op__is_signed$next[0:0]$6854 \logical_op__is_signed assign $1\logical_op__oe__oe$next[0:0]$6855 \logical_op__oe__oe assign $1\logical_op__oe__ok$next[0:0]$6856 \logical_op__oe__ok assign $1\logical_op__output_carry$next[0:0]$6857 \logical_op__output_carry assign $1\logical_op__rc__ok$next[0:0]$6858 \logical_op__rc__ok assign $1\logical_op__rc__rc$next[0:0]$6859 \logical_op__rc__rc assign $1\logical_op__write_cr0$next[0:0]$6860 \logical_op__write_cr0 assign $1\logical_op__zero_a$next[0:0]$6861 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\logical_op__imm_data__data$next[63:0]$6862 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\logical_op__imm_data__ok$next[0:0]$6863 1'0 assign $2\logical_op__rc__rc$next[0:0]$6867 1'0 assign $2\logical_op__rc__ok$next[0:0]$6866 1'0 assign $2\logical_op__oe__oe$next[0:0]$6864 1'0 assign $2\logical_op__oe__ok$next[0:0]$6865 1'0 case assign $2\logical_op__imm_data__data$next[63:0]$6862 $1\logical_op__imm_data__data$next[63:0]$6846 assign $2\logical_op__imm_data__ok$next[0:0]$6863 $1\logical_op__imm_data__ok$next[0:0]$6847 assign $2\logical_op__oe__oe$next[0:0]$6864 $1\logical_op__oe__oe$next[0:0]$6855 assign $2\logical_op__oe__ok$next[0:0]$6865 $1\logical_op__oe__ok$next[0:0]$6856 assign $2\logical_op__rc__ok$next[0:0]$6866 $1\logical_op__rc__ok$next[0:0]$6858 assign $2\logical_op__rc__rc$next[0:0]$6867 $1\logical_op__rc__rc$next[0:0]$6859 end sync always update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6826 update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6827 update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6828 update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6829 update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6830 update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6831 update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6832 update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6833 update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6834 update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6835 update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6836 update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6837 update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6838 update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6839 update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6840 update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6841 update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6842 update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6843 end attribute \src "libresoc.v:145780.3-145798.6" process $proc$libresoc.v:145780$6868 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$next[63:0]$6869 $1\o$next[63:0]$6871 assign { } { } assign $0\o_ok$next[0:0]$6870 $2\o_ok$next[0:0]$6873 attribute \src "libresoc.v:145781.5-145781.29" switch \initial attribute \src "libresoc.v:145781.9-145781.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$6872 $1\o$next[63:0]$6871 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$6872 $1\o$next[63:0]$6871 } { \o_ok$86 \o$85 } case assign $1\o$next[63:0]$6871 \o assign $1\o_ok$next[0:0]$6872 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$6873 1'0 case assign $2\o_ok$next[0:0]$6873 $1\o_ok$next[0:0]$6872 end sync always update \o$next $0\o$next[63:0]$6869 update \o_ok$next $0\o_ok$next[0:0]$6870 end attribute \src "libresoc.v:145799.3-145817.6" process $proc$libresoc.v:145799$6874 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$next[3:0]$6875 $1\cr_a$next[3:0]$6877 assign { } { } assign $0\cr_a_ok$next[0:0]$6876 $2\cr_a_ok$next[0:0]$6879 attribute \src "libresoc.v:145800.5-145800.29" switch \initial attribute \src "libresoc.v:145800.9-145800.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$6878 $1\cr_a$next[3:0]$6877 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$6878 $1\cr_a$next[3:0]$6877 } { \cr_a_ok$88 \cr_a$87 } case assign $1\cr_a$next[3:0]$6877 \cr_a assign $1\cr_a_ok$next[0:0]$6878 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$next[0:0]$6879 1'0 case assign $2\cr_a_ok$next[0:0]$6879 $1\cr_a_ok$next[0:0]$6878 end sync always update \cr_a$next $0\cr_a$next[3:0]$6875 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6876 end attribute \src "libresoc.v:145818.3-145836.6" process $proc$libresoc.v:145818$6880 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_so$next[0:0]$6881 $1\xer_so$next[0:0]$6883 assign { } { } assign $0\xer_so_ok$next[0:0]$6882 $2\xer_so_ok$next[0:0]$6885 attribute \src "libresoc.v:145819.5-145819.29" switch \initial attribute \src "libresoc.v:145819.9-145819.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$6884 $1\xer_so$next[0:0]$6883 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$6884 $1\xer_so$next[0:0]$6883 } { \xer_so_ok$92 \xer_so$91 } case assign $1\xer_so$next[0:0]$6883 \xer_so assign $1\xer_so_ok$next[0:0]$6884 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so_ok$next[0:0]$6885 1'0 case assign $2\xer_so_ok$next[0:0]$6885 $1\xer_so_ok$next[0:0]$6884 end sync always update \xer_so$next $0\xer_so$next[0:0]$6881 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6882 end connect \$64 $and$libresoc.v:145554$6791_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } connect { \cr_a_ok$88 \cr_a$87 } 5'00000 connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } connect \muxid$66 \main_muxid$43 connect \p_valid_i_p_ready_o \$64 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$63 \p_valid_i connect \main_xer_so \input_xer_so$42 connect \main_rb \input_rb$41 connect \main_ra \input_ra$40 connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } connect \main_muxid \input_muxid$21 connect \input_xer_so \xer_so$20 connect \input_rb \rb connect \input_ra \ra connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end attribute \src "libresoc.v:145864.1-146897.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 attribute \src "libresoc.v:146864.3-146882.6" wire width 4 $0\cr_a$22$next[3:0]$7018 attribute \src "libresoc.v:146668.3-146669.33" wire width 4 $0\cr_a$22[3:0]$6915 attribute \src "libresoc.v:145876.13-145876.29" wire width 4 $0\cr_a$22[3:0]$7025 attribute \src "libresoc.v:146864.3-146882.6" wire $0\cr_a_ok$23$next[0:0]$7019 attribute \src "libresoc.v:146670.3-146671.39" wire $0\cr_a_ok$23[0:0]$6917 attribute \src "libresoc.v:145885.7-145885.26" wire $0\cr_a_ok$23[0:0]$7027 attribute \src "libresoc.v:145865.7-145865.20" wire $0\initial[0:0] attribute \src "libresoc.v:146803.3-146844.6" wire width 4 $0\logical_op__data_len$18$next[3:0]$6969 attribute \src "libresoc.v:146708.3-146709.65" wire width 4 $0\logical_op__data_len$18[3:0]$6955 attribute \src "libresoc.v:145896.13-145896.45" wire width 4 $0\logical_op__data_len$18[3:0]$7029 attribute \src "libresoc.v:146803.3-146844.6" wire width 14 $0\logical_op__fn_unit$3$next[13:0]$6970 attribute \src "libresoc.v:146678.3-146679.61" wire width 14 $0\logical_op__fn_unit$3[13:0]$6925 attribute \src "libresoc.v:145935.14-145935.48" wire width 14 $0\logical_op__fn_unit$3[13:0]$7031 attribute \src "libresoc.v:146803.3-146844.6" wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6971 attribute \src "libresoc.v:146680.3-146681.75" wire width 64 $0\logical_op__imm_data__data$4[63:0]$6927 attribute \src "libresoc.v:145959.14-145959.67" wire width 64 $0\logical_op__imm_data__data$4[63:0]$7033 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__imm_data__ok$5$next[0:0]$6972 attribute \src "libresoc.v:146682.3-146683.71" wire $0\logical_op__imm_data__ok$5[0:0]$6929 attribute \src "libresoc.v:145968.7-145968.42" wire $0\logical_op__imm_data__ok$5[0:0]$7035 attribute \src "libresoc.v:146803.3-146844.6" wire width 2 $0\logical_op__input_carry$12$next[1:0]$6973 attribute \src "libresoc.v:146696.3-146697.71" wire width 2 $0\logical_op__input_carry$12[1:0]$6943 attribute \src "libresoc.v:145985.13-145985.48" wire width 2 $0\logical_op__input_carry$12[1:0]$7037 attribute \src "libresoc.v:146803.3-146844.6" wire width 32 $0\logical_op__insn$19$next[31:0]$6974 attribute \src "libresoc.v:146710.3-146711.57" wire width 32 $0\logical_op__insn$19[31:0]$6957 attribute \src "libresoc.v:145998.14-145998.43" wire width 32 $0\logical_op__insn$19[31:0]$7039 attribute \src "libresoc.v:146803.3-146844.6" wire width 7 $0\logical_op__insn_type$2$next[6:0]$6975 attribute \src "libresoc.v:146676.3-146677.65" wire width 7 $0\logical_op__insn_type$2[6:0]$6923 attribute \src "libresoc.v:146157.13-146157.46" wire width 7 $0\logical_op__insn_type$2[6:0]$7041 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__invert_in$10$next[0:0]$6976 attribute \src "libresoc.v:146692.3-146693.67" wire $0\logical_op__invert_in$10[0:0]$6939 attribute \src "libresoc.v:146241.7-146241.40" wire $0\logical_op__invert_in$10[0:0]$7043 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__invert_out$13$next[0:0]$6977 attribute \src "libresoc.v:146698.3-146699.69" wire $0\logical_op__invert_out$13[0:0]$6945 attribute \src "libresoc.v:146250.7-146250.41" wire $0\logical_op__invert_out$13[0:0]$7045 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__is_32bit$16$next[0:0]$6978 attribute \src "libresoc.v:146704.3-146705.65" wire $0\logical_op__is_32bit$16[0:0]$6951 attribute \src "libresoc.v:146259.7-146259.39" wire $0\logical_op__is_32bit$16[0:0]$7047 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__is_signed$17$next[0:0]$6979 attribute \src "libresoc.v:146706.3-146707.67" wire $0\logical_op__is_signed$17[0:0]$6953 attribute \src "libresoc.v:146268.7-146268.40" wire $0\logical_op__is_signed$17[0:0]$7049 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__oe__oe$8$next[0:0]$6980 attribute \src "libresoc.v:146688.3-146689.59" wire $0\logical_op__oe__oe$8[0:0]$6935 attribute \src "libresoc.v:146279.7-146279.36" wire $0\logical_op__oe__oe$8[0:0]$7051 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__oe__ok$9$next[0:0]$6981 attribute \src "libresoc.v:146690.3-146691.59" wire $0\logical_op__oe__ok$9[0:0]$6937 attribute \src "libresoc.v:146288.7-146288.36" wire $0\logical_op__oe__ok$9[0:0]$7053 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__output_carry$15$next[0:0]$6982 attribute \src "libresoc.v:146702.3-146703.73" wire $0\logical_op__output_carry$15[0:0]$6949 attribute \src "libresoc.v:146295.7-146295.43" wire $0\logical_op__output_carry$15[0:0]$7055 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__rc__ok$7$next[0:0]$6983 attribute \src "libresoc.v:146686.3-146687.59" wire $0\logical_op__rc__ok$7[0:0]$6933 attribute \src "libresoc.v:146306.7-146306.36" wire $0\logical_op__rc__ok$7[0:0]$7057 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__rc__rc$6$next[0:0]$6984 attribute \src "libresoc.v:146684.3-146685.59" wire $0\logical_op__rc__rc$6[0:0]$6931 attribute \src "libresoc.v:146315.7-146315.36" wire $0\logical_op__rc__rc$6[0:0]$7059 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__write_cr0$14$next[0:0]$6985 attribute \src "libresoc.v:146700.3-146701.67" wire $0\logical_op__write_cr0$14[0:0]$6947 attribute \src "libresoc.v:146322.7-146322.40" wire $0\logical_op__write_cr0$14[0:0]$7061 attribute \src "libresoc.v:146803.3-146844.6" wire $0\logical_op__zero_a$11$next[0:0]$6986 attribute \src "libresoc.v:146694.3-146695.61" wire $0\logical_op__zero_a$11[0:0]$6941 attribute \src "libresoc.v:146331.7-146331.37" wire $0\logical_op__zero_a$11[0:0]$7063 attribute \src "libresoc.v:146790.3-146802.6" wire width 2 $0\muxid$1$next[1:0]$6966 attribute \src "libresoc.v:146712.3-146713.33" wire width 2 $0\muxid$1[1:0]$6959 attribute \src "libresoc.v:146340.13-146340.29" wire width 2 $0\muxid$1[1:0]$7065 attribute \src "libresoc.v:146845.3-146863.6" wire width 64 $0\o$20$next[63:0]$7012 attribute \src "libresoc.v:146672.3-146673.27" wire width 64 $0\o$20[63:0]$6919 attribute \src "libresoc.v:146355.14-146355.43" wire width 64 $0\o$20[63:0]$7067 attribute \src "libresoc.v:146845.3-146863.6" wire $0\o_ok$21$next[0:0]$7013 attribute \src "libresoc.v:146674.3-146675.33" wire $0\o_ok$21[0:0]$6921 attribute \src "libresoc.v:146364.7-146364.23" wire $0\o_ok$21[0:0]$7069 attribute \src "libresoc.v:146772.3-146789.6" wire $0\r_busy$next[0:0]$6962 attribute \src "libresoc.v:146714.3-146715.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:146864.3-146882.6" wire width 4 $1\cr_a$22$next[3:0]$7020 attribute \src "libresoc.v:146864.3-146882.6" wire $1\cr_a_ok$23$next[0:0]$7021 attribute \src "libresoc.v:146803.3-146844.6" wire width 4 $1\logical_op__data_len$18$next[3:0]$6987 attribute \src "libresoc.v:146803.3-146844.6" wire width 14 $1\logical_op__fn_unit$3$next[13:0]$6988 attribute \src "libresoc.v:146803.3-146844.6" wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6989 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__imm_data__ok$5$next[0:0]$6990 attribute \src "libresoc.v:146803.3-146844.6" wire width 2 $1\logical_op__input_carry$12$next[1:0]$6991 attribute \src "libresoc.v:146803.3-146844.6" wire width 32 $1\logical_op__insn$19$next[31:0]$6992 attribute \src "libresoc.v:146803.3-146844.6" wire width 7 $1\logical_op__insn_type$2$next[6:0]$6993 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__invert_in$10$next[0:0]$6994 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__invert_out$13$next[0:0]$6995 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__is_32bit$16$next[0:0]$6996 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__is_signed$17$next[0:0]$6997 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__oe__oe$8$next[0:0]$6998 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__oe__ok$9$next[0:0]$6999 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__output_carry$15$next[0:0]$7000 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__rc__ok$7$next[0:0]$7001 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__rc__rc$6$next[0:0]$7002 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__write_cr0$14$next[0:0]$7003 attribute \src "libresoc.v:146803.3-146844.6" wire $1\logical_op__zero_a$11$next[0:0]$7004 attribute \src "libresoc.v:146790.3-146802.6" wire width 2 $1\muxid$1$next[1:0]$6967 attribute \src "libresoc.v:146845.3-146863.6" wire width 64 $1\o$20$next[63:0]$7014 attribute \src "libresoc.v:146845.3-146863.6" wire $1\o_ok$21$next[0:0]$7015 attribute \src "libresoc.v:146772.3-146789.6" wire $1\r_busy$next[0:0]$6963 attribute \src "libresoc.v:146658.7-146658.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:146864.3-146882.6" wire $2\cr_a_ok$23$next[0:0]$7022 attribute \src "libresoc.v:146803.3-146844.6" wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7005 attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__imm_data__ok$5$next[0:0]$7006 attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__oe__oe$8$next[0:0]$7007 attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__oe__ok$9$next[0:0]$7008 attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__rc__ok$7$next[0:0]$7009 attribute \src "libresoc.v:146803.3-146844.6" wire $2\logical_op__rc__rc$6$next[0:0]$7010 attribute \src "libresoc.v:146845.3-146863.6" wire $2\o_ok$21$next[0:0]$7016 attribute \src "libresoc.v:146772.3-146789.6" wire $2\r_busy$next[0:0]$6964 attribute \src "libresoc.v:146667.18-146667.118" wire $and$libresoc.v:146667$6913_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 54 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 52 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$22$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 53 \cr_a_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$23$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$73 attribute \src "libresoc.v:145865.7-145865.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 48 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 33 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 34 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$55 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 15 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 42 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$12$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 49 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$69 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 32 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 43 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 46 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 47 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 45 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 44 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 41 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 31 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 30 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 29 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 23 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 50 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$20$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 24 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 51 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$21$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len$41 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_logical_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_logical_op__imm_data__data$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__imm_data__ok$28 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_logical_op__input_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_logical_op__insn$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__invert_in$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__invert_out$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__is_32bit$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__is_signed$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__oe__oe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__oe__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__output_carry$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__rc__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__rc__rc$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__write_cr0$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__zero_a$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 27 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 28 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:146667$6913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o connect \Y $and$libresoc.v:146667$6913_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:146716.10-146719.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:146720.15-146767.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 connect \cr_a_ok \output_cr_a_ok connect \logical_op__data_len \output_logical_op__data_len connect \logical_op__data_len$18 \output_logical_op__data_len$41 connect \logical_op__fn_unit \output_logical_op__fn_unit connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 connect \logical_op__imm_data__data \output_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 connect \logical_op__input_carry \output_logical_op__input_carry connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 connect \logical_op__insn \output_logical_op__insn connect \logical_op__insn$19 \output_logical_op__insn$42 connect \logical_op__insn_type \output_logical_op__insn_type connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 connect \logical_op__invert_in \output_logical_op__invert_in connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 connect \logical_op__invert_out \output_logical_op__invert_out connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 connect \logical_op__is_32bit \output_logical_op__is_32bit connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 connect \logical_op__is_signed \output_logical_op__is_signed connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 connect \logical_op__oe__oe \output_logical_op__oe__oe connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 connect \logical_op__oe__ok \output_logical_op__oe__ok connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 connect \logical_op__output_carry \output_logical_op__output_carry connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 connect \logical_op__rc__ok \output_logical_op__rc__ok connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 connect \logical_op__rc__rc \output_logical_op__rc__rc connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 connect \logical_op__write_cr0 \output_logical_op__write_cr0 connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 connect \logical_op__zero_a \output_logical_op__zero_a connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 connect \muxid \output_muxid connect \muxid$1 \output_muxid$24 connect \o \output_o connect \o$20 \output_o$43 connect \o_ok \output_o_ok connect \o_ok$21 \output_o_ok$44 connect \xer_so \output_xer_so end attribute \module_not_derived 1 attribute \src "libresoc.v:146768.10-146771.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:145865.7-145865.20" process $proc$libresoc.v:145865$7023 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:145876.13-145876.29" process $proc$libresoc.v:145876$7024 assign { } { } assign $0\cr_a$22[3:0]$7025 4'0000 sync always sync init update \cr_a$22 $0\cr_a$22[3:0]$7025 end attribute \src "libresoc.v:145885.7-145885.26" process $proc$libresoc.v:145885$7026 assign { } { } assign $0\cr_a_ok$23[0:0]$7027 1'0 sync always sync init update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7027 end attribute \src "libresoc.v:145896.13-145896.45" process $proc$libresoc.v:145896$7028 assign { } { } assign $0\logical_op__data_len$18[3:0]$7029 4'0000 sync always sync init update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7029 end attribute \src "libresoc.v:145935.14-145935.48" process $proc$libresoc.v:145935$7030 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$7031 14'00000000000000 sync always sync init update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7031 end attribute \src "libresoc.v:145959.14-145959.67" process $proc$libresoc.v:145959$7032 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$7033 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7033 end attribute \src "libresoc.v:145968.7-145968.42" process $proc$libresoc.v:145968$7034 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$7035 1'0 sync always sync init update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7035 end attribute \src "libresoc.v:145985.13-145985.48" process $proc$libresoc.v:145985$7036 assign { } { } assign $0\logical_op__input_carry$12[1:0]$7037 2'00 sync always sync init update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7037 end attribute \src "libresoc.v:145998.14-145998.43" process $proc$libresoc.v:145998$7038 assign { } { } assign $0\logical_op__insn$19[31:0]$7039 0 sync always sync init update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7039 end attribute \src "libresoc.v:146157.13-146157.46" process $proc$libresoc.v:146157$7040 assign { } { } assign $0\logical_op__insn_type$2[6:0]$7041 7'0000000 sync always sync init update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7041 end attribute \src "libresoc.v:146241.7-146241.40" process $proc$libresoc.v:146241$7042 assign { } { } assign $0\logical_op__invert_in$10[0:0]$7043 1'0 sync always sync init update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7043 end attribute \src "libresoc.v:146250.7-146250.41" process $proc$libresoc.v:146250$7044 assign { } { } assign $0\logical_op__invert_out$13[0:0]$7045 1'0 sync always sync init update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7045 end attribute \src "libresoc.v:146259.7-146259.39" process $proc$libresoc.v:146259$7046 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$7047 1'0 sync always sync init update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7047 end attribute \src "libresoc.v:146268.7-146268.40" process $proc$libresoc.v:146268$7048 assign { } { } assign $0\logical_op__is_signed$17[0:0]$7049 1'0 sync always sync init update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7049 end attribute \src "libresoc.v:146279.7-146279.36" process $proc$libresoc.v:146279$7050 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$7051 1'0 sync always sync init update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7051 end attribute \src "libresoc.v:146288.7-146288.36" process $proc$libresoc.v:146288$7052 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$7053 1'0 sync always sync init update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7053 end attribute \src "libresoc.v:146295.7-146295.43" process $proc$libresoc.v:146295$7054 assign { } { } assign $0\logical_op__output_carry$15[0:0]$7055 1'0 sync always sync init update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7055 end attribute \src "libresoc.v:146306.7-146306.36" process $proc$libresoc.v:146306$7056 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$7057 1'0 sync always sync init update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7057 end attribute \src "libresoc.v:146315.7-146315.36" process $proc$libresoc.v:146315$7058 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$7059 1'0 sync always sync init update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7059 end attribute \src "libresoc.v:146322.7-146322.40" process $proc$libresoc.v:146322$7060 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$7061 1'0 sync always sync init update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7061 end attribute \src "libresoc.v:146331.7-146331.37" process $proc$libresoc.v:146331$7062 assign { } { } assign $0\logical_op__zero_a$11[0:0]$7063 1'0 sync always sync init update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7063 end attribute \src "libresoc.v:146340.13-146340.29" process $proc$libresoc.v:146340$7064 assign { } { } assign $0\muxid$1[1:0]$7065 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$7065 end attribute \src "libresoc.v:146355.14-146355.43" process $proc$libresoc.v:146355$7066 assign { } { } assign $0\o$20[63:0]$7067 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$20 $0\o$20[63:0]$7067 end attribute \src "libresoc.v:146364.7-146364.23" process $proc$libresoc.v:146364$7068 assign { } { } assign $0\o_ok$21[0:0]$7069 1'0 sync always sync init update \o_ok$21 $0\o_ok$21[0:0]$7069 end attribute \src "libresoc.v:146658.7-146658.20" process $proc$libresoc.v:146658$7070 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:146668.3-146669.33" process $proc$libresoc.v:146668$6914 assign { } { } assign $0\cr_a$22[3:0]$6915 \cr_a$22$next sync posedge \coresync_clk update \cr_a$22 $0\cr_a$22[3:0]$6915 end attribute \src "libresoc.v:146670.3-146671.39" process $proc$libresoc.v:146670$6916 assign { } { } assign $0\cr_a_ok$23[0:0]$6917 \cr_a_ok$23$next sync posedge \coresync_clk update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6917 end attribute \src "libresoc.v:146672.3-146673.27" process $proc$libresoc.v:146672$6918 assign { } { } assign $0\o$20[63:0]$6919 \o$20$next sync posedge \coresync_clk update \o$20 $0\o$20[63:0]$6919 end attribute \src "libresoc.v:146674.3-146675.33" process $proc$libresoc.v:146674$6920 assign { } { } assign $0\o_ok$21[0:0]$6921 \o_ok$21$next sync posedge \coresync_clk update \o_ok$21 $0\o_ok$21[0:0]$6921 end attribute \src "libresoc.v:146676.3-146677.65" process $proc$libresoc.v:146676$6922 assign { } { } assign $0\logical_op__insn_type$2[6:0]$6923 \logical_op__insn_type$2$next sync posedge \coresync_clk update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6923 end attribute \src "libresoc.v:146678.3-146679.61" process $proc$libresoc.v:146678$6924 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$6925 \logical_op__fn_unit$3$next sync posedge \coresync_clk update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6925 end attribute \src "libresoc.v:146680.3-146681.75" process $proc$libresoc.v:146680$6926 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$6927 \logical_op__imm_data__data$4$next sync posedge \coresync_clk update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6927 end attribute \src "libresoc.v:146682.3-146683.71" process $proc$libresoc.v:146682$6928 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$6929 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6929 end attribute \src "libresoc.v:146684.3-146685.59" process $proc$libresoc.v:146684$6930 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$6931 \logical_op__rc__rc$6$next sync posedge \coresync_clk update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6931 end attribute \src "libresoc.v:146686.3-146687.59" process $proc$libresoc.v:146686$6932 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$6933 \logical_op__rc__ok$7$next sync posedge \coresync_clk update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6933 end attribute \src "libresoc.v:146688.3-146689.59" process $proc$libresoc.v:146688$6934 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$6935 \logical_op__oe__oe$8$next sync posedge \coresync_clk update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6935 end attribute \src "libresoc.v:146690.3-146691.59" process $proc$libresoc.v:146690$6936 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$6937 \logical_op__oe__ok$9$next sync posedge \coresync_clk update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6937 end attribute \src "libresoc.v:146692.3-146693.67" process $proc$libresoc.v:146692$6938 assign { } { } assign $0\logical_op__invert_in$10[0:0]$6939 \logical_op__invert_in$10$next sync posedge \coresync_clk update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6939 end attribute \src "libresoc.v:146694.3-146695.61" process $proc$libresoc.v:146694$6940 assign { } { } assign $0\logical_op__zero_a$11[0:0]$6941 \logical_op__zero_a$11$next sync posedge \coresync_clk update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6941 end attribute \src "libresoc.v:146696.3-146697.71" process $proc$libresoc.v:146696$6942 assign { } { } assign $0\logical_op__input_carry$12[1:0]$6943 \logical_op__input_carry$12$next sync posedge \coresync_clk update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6943 end attribute \src "libresoc.v:146698.3-146699.69" process $proc$libresoc.v:146698$6944 assign { } { } assign $0\logical_op__invert_out$13[0:0]$6945 \logical_op__invert_out$13$next sync posedge \coresync_clk update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6945 end attribute \src "libresoc.v:146700.3-146701.67" process $proc$libresoc.v:146700$6946 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$6947 \logical_op__write_cr0$14$next sync posedge \coresync_clk update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6947 end attribute \src "libresoc.v:146702.3-146703.73" process $proc$libresoc.v:146702$6948 assign { } { } assign $0\logical_op__output_carry$15[0:0]$6949 \logical_op__output_carry$15$next sync posedge \coresync_clk update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6949 end attribute \src "libresoc.v:146704.3-146705.65" process $proc$libresoc.v:146704$6950 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$6951 \logical_op__is_32bit$16$next sync posedge \coresync_clk update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6951 end attribute \src "libresoc.v:146706.3-146707.67" process $proc$libresoc.v:146706$6952 assign { } { } assign $0\logical_op__is_signed$17[0:0]$6953 \logical_op__is_signed$17$next sync posedge \coresync_clk update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6953 end attribute \src "libresoc.v:146708.3-146709.65" process $proc$libresoc.v:146708$6954 assign { } { } assign $0\logical_op__data_len$18[3:0]$6955 \logical_op__data_len$18$next sync posedge \coresync_clk update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6955 end attribute \src "libresoc.v:146710.3-146711.57" process $proc$libresoc.v:146710$6956 assign { } { } assign $0\logical_op__insn$19[31:0]$6957 \logical_op__insn$19$next sync posedge \coresync_clk update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6957 end attribute \src "libresoc.v:146712.3-146713.33" process $proc$libresoc.v:146712$6958 assign { } { } assign $0\muxid$1[1:0]$6959 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$6959 end attribute \src "libresoc.v:146714.3-146715.29" process $proc$libresoc.v:146714$6960 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:146772.3-146789.6" process $proc$libresoc.v:146772$6961 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$6962 $2\r_busy$next[0:0]$6964 attribute \src "libresoc.v:146773.5-146773.29" switch \initial attribute \src "libresoc.v:146773.9-146773.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$6963 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$6963 1'0 case assign $1\r_busy$next[0:0]$6963 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$6964 1'0 case assign $2\r_busy$next[0:0]$6964 $1\r_busy$next[0:0]$6963 end sync always update \r_busy$next $0\r_busy$next[0:0]$6962 end attribute \src "libresoc.v:146790.3-146802.6" process $proc$libresoc.v:146790$6965 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$6966 $1\muxid$1$next[1:0]$6967 attribute \src "libresoc.v:146791.5-146791.29" switch \initial attribute \src "libresoc.v:146791.9-146791.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$6967 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$6967 \muxid$51 case assign $1\muxid$1$next[1:0]$6967 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$6966 end attribute \src "libresoc.v:146803.3-146844.6" process $proc$libresoc.v:146803$6968 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\logical_op__data_len$18$next[3:0]$6969 $1\logical_op__data_len$18$next[3:0]$6987 assign $0\logical_op__fn_unit$3$next[13:0]$6970 $1\logical_op__fn_unit$3$next[13:0]$6988 assign { } { } assign { } { } assign $0\logical_op__input_carry$12$next[1:0]$6973 $1\logical_op__input_carry$12$next[1:0]$6991 assign $0\logical_op__insn$19$next[31:0]$6974 $1\logical_op__insn$19$next[31:0]$6992 assign $0\logical_op__insn_type$2$next[6:0]$6975 $1\logical_op__insn_type$2$next[6:0]$6993 assign $0\logical_op__invert_in$10$next[0:0]$6976 $1\logical_op__invert_in$10$next[0:0]$6994 assign $0\logical_op__invert_out$13$next[0:0]$6977 $1\logical_op__invert_out$13$next[0:0]$6995 assign $0\logical_op__is_32bit$16$next[0:0]$6978 $1\logical_op__is_32bit$16$next[0:0]$6996 assign $0\logical_op__is_signed$17$next[0:0]$6979 $1\logical_op__is_signed$17$next[0:0]$6997 assign { } { } assign { } { } assign $0\logical_op__output_carry$15$next[0:0]$6982 $1\logical_op__output_carry$15$next[0:0]$7000 assign { } { } assign { } { } assign $0\logical_op__write_cr0$14$next[0:0]$6985 $1\logical_op__write_cr0$14$next[0:0]$7003 assign $0\logical_op__zero_a$11$next[0:0]$6986 $1\logical_op__zero_a$11$next[0:0]$7004 assign $0\logical_op__imm_data__data$4$next[63:0]$6971 $2\logical_op__imm_data__data$4$next[63:0]$7005 assign $0\logical_op__imm_data__ok$5$next[0:0]$6972 $2\logical_op__imm_data__ok$5$next[0:0]$7006 assign $0\logical_op__oe__oe$8$next[0:0]$6980 $2\logical_op__oe__oe$8$next[0:0]$7007 assign $0\logical_op__oe__ok$9$next[0:0]$6981 $2\logical_op__oe__ok$9$next[0:0]$7008 assign $0\logical_op__rc__ok$7$next[0:0]$6983 $2\logical_op__rc__ok$7$next[0:0]$7009 assign $0\logical_op__rc__rc$6$next[0:0]$6984 $2\logical_op__rc__rc$6$next[0:0]$7010 attribute \src "libresoc.v:146804.5-146804.29" switch \initial attribute \src "libresoc.v:146804.9-146804.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$19$next[31:0]$6992 $1\logical_op__data_len$18$next[3:0]$6987 $1\logical_op__is_signed$17$next[0:0]$6997 $1\logical_op__is_32bit$16$next[0:0]$6996 $1\logical_op__output_carry$15$next[0:0]$7000 $1\logical_op__write_cr0$14$next[0:0]$7003 $1\logical_op__invert_out$13$next[0:0]$6995 $1\logical_op__input_carry$12$next[1:0]$6991 $1\logical_op__zero_a$11$next[0:0]$7004 $1\logical_op__invert_in$10$next[0:0]$6994 $1\logical_op__oe__ok$9$next[0:0]$6999 $1\logical_op__oe__oe$8$next[0:0]$6998 $1\logical_op__rc__ok$7$next[0:0]$7001 $1\logical_op__rc__rc$6$next[0:0]$7002 $1\logical_op__imm_data__ok$5$next[0:0]$6990 $1\logical_op__imm_data__data$4$next[63:0]$6989 $1\logical_op__fn_unit$3$next[13:0]$6988 $1\logical_op__insn_type$2$next[6:0]$6993 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$19$next[31:0]$6992 $1\logical_op__data_len$18$next[3:0]$6987 $1\logical_op__is_signed$17$next[0:0]$6997 $1\logical_op__is_32bit$16$next[0:0]$6996 $1\logical_op__output_carry$15$next[0:0]$7000 $1\logical_op__write_cr0$14$next[0:0]$7003 $1\logical_op__invert_out$13$next[0:0]$6995 $1\logical_op__input_carry$12$next[1:0]$6991 $1\logical_op__zero_a$11$next[0:0]$7004 $1\logical_op__invert_in$10$next[0:0]$6994 $1\logical_op__oe__ok$9$next[0:0]$6999 $1\logical_op__oe__oe$8$next[0:0]$6998 $1\logical_op__rc__ok$7$next[0:0]$7001 $1\logical_op__rc__rc$6$next[0:0]$7002 $1\logical_op__imm_data__ok$5$next[0:0]$6990 $1\logical_op__imm_data__data$4$next[63:0]$6989 $1\logical_op__fn_unit$3$next[13:0]$6988 $1\logical_op__insn_type$2$next[6:0]$6993 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case assign $1\logical_op__data_len$18$next[3:0]$6987 \logical_op__data_len$18 assign $1\logical_op__fn_unit$3$next[13:0]$6988 \logical_op__fn_unit$3 assign $1\logical_op__imm_data__data$4$next[63:0]$6989 \logical_op__imm_data__data$4 assign $1\logical_op__imm_data__ok$5$next[0:0]$6990 \logical_op__imm_data__ok$5 assign $1\logical_op__input_carry$12$next[1:0]$6991 \logical_op__input_carry$12 assign $1\logical_op__insn$19$next[31:0]$6992 \logical_op__insn$19 assign $1\logical_op__insn_type$2$next[6:0]$6993 \logical_op__insn_type$2 assign $1\logical_op__invert_in$10$next[0:0]$6994 \logical_op__invert_in$10 assign $1\logical_op__invert_out$13$next[0:0]$6995 \logical_op__invert_out$13 assign $1\logical_op__is_32bit$16$next[0:0]$6996 \logical_op__is_32bit$16 assign $1\logical_op__is_signed$17$next[0:0]$6997 \logical_op__is_signed$17 assign $1\logical_op__oe__oe$8$next[0:0]$6998 \logical_op__oe__oe$8 assign $1\logical_op__oe__ok$9$next[0:0]$6999 \logical_op__oe__ok$9 assign $1\logical_op__output_carry$15$next[0:0]$7000 \logical_op__output_carry$15 assign $1\logical_op__rc__ok$7$next[0:0]$7001 \logical_op__rc__ok$7 assign $1\logical_op__rc__rc$6$next[0:0]$7002 \logical_op__rc__rc$6 assign $1\logical_op__write_cr0$14$next[0:0]$7003 \logical_op__write_cr0$14 assign $1\logical_op__zero_a$11$next[0:0]$7004 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\logical_op__imm_data__data$4$next[63:0]$7005 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\logical_op__imm_data__ok$5$next[0:0]$7006 1'0 assign $2\logical_op__rc__rc$6$next[0:0]$7010 1'0 assign $2\logical_op__rc__ok$7$next[0:0]$7009 1'0 assign $2\logical_op__oe__oe$8$next[0:0]$7007 1'0 assign $2\logical_op__oe__ok$9$next[0:0]$7008 1'0 case assign $2\logical_op__imm_data__data$4$next[63:0]$7005 $1\logical_op__imm_data__data$4$next[63:0]$6989 assign $2\logical_op__imm_data__ok$5$next[0:0]$7006 $1\logical_op__imm_data__ok$5$next[0:0]$6990 assign $2\logical_op__oe__oe$8$next[0:0]$7007 $1\logical_op__oe__oe$8$next[0:0]$6998 assign $2\logical_op__oe__ok$9$next[0:0]$7008 $1\logical_op__oe__ok$9$next[0:0]$6999 assign $2\logical_op__rc__ok$7$next[0:0]$7009 $1\logical_op__rc__ok$7$next[0:0]$7001 assign $2\logical_op__rc__rc$6$next[0:0]$7010 $1\logical_op__rc__rc$6$next[0:0]$7002 end sync always update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6969 update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$6970 update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6971 update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6972 update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6973 update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6974 update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6975 update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6976 update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6977 update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6978 update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6979 update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6980 update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6981 update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6982 update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6983 update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6984 update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6985 update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6986 end attribute \src "libresoc.v:146845.3-146863.6" process $proc$libresoc.v:146845$7011 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$20$next[63:0]$7012 $1\o$20$next[63:0]$7014 assign { } { } assign $0\o_ok$21$next[0:0]$7013 $2\o_ok$21$next[0:0]$7016 attribute \src "libresoc.v:146846.5-146846.29" switch \initial attribute \src "libresoc.v:146846.9-146846.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$21$next[0:0]$7015 $1\o$20$next[63:0]$7014 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$21$next[0:0]$7015 $1\o$20$next[63:0]$7014 } { \o_ok$71 \o$70 } case assign $1\o$20$next[63:0]$7014 \o$20 assign $1\o_ok$21$next[0:0]$7015 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$21$next[0:0]$7016 1'0 case assign $2\o_ok$21$next[0:0]$7016 $1\o_ok$21$next[0:0]$7015 end sync always update \o$20$next $0\o$20$next[63:0]$7012 update \o_ok$21$next $0\o_ok$21$next[0:0]$7013 end attribute \src "libresoc.v:146864.3-146882.6" process $proc$libresoc.v:146864$7017 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$22$next[3:0]$7018 $1\cr_a$22$next[3:0]$7020 assign { } { } assign $0\cr_a_ok$23$next[0:0]$7019 $2\cr_a_ok$23$next[0:0]$7022 attribute \src "libresoc.v:146865.5-146865.29" switch \initial attribute \src "libresoc.v:146865.9-146865.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$23$next[0:0]$7021 $1\cr_a$22$next[3:0]$7020 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$23$next[0:0]$7021 $1\cr_a$22$next[3:0]$7020 } { \cr_a_ok$73 \cr_a$72 } case assign $1\cr_a$22$next[3:0]$7020 \cr_a$22 assign $1\cr_a_ok$23$next[0:0]$7021 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$23$next[0:0]$7022 1'0 case assign $2\cr_a_ok$23$next[0:0]$7022 $1\cr_a_ok$23$next[0:0]$7021 end sync always update \cr_a$22$next $0\cr_a$22$next[3:0]$7018 update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7019 end connect \$49 $and$libresoc.v:146667$6913_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } connect \muxid$51 \output_muxid$24 connect \p_valid_i_p_ready_o \$49 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$48 \p_valid_i connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } connect { \output_o_ok \output_o } { \o_ok \o } connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end attribute \src "ls180.v:4.1-5943.10" attribute \cells_not_processed 1 module \ls180 attribute \src "ls180.v:5490.1-5500.4" wire width 7 $0$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1439 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1440 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5492$1_EN[31:0]$1441 attribute \src "ls180.v:5490.1-5500.4" wire width 7 $0$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1442 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1443 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5494$2_EN[31:0]$1444 attribute \src "ls180.v:5490.1-5500.4" wire width 7 $0$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1445 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1446 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5496$3_EN[31:0]$1447 attribute \src "ls180.v:5490.1-5500.4" wire width 7 $0$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1448 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1449 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $0$memwr$\mem$ls180.v:5498$4_EN[31:0]$1450 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $0$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1465 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1466 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1467 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $0$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1468 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1469 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1470 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $0$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1471 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1472 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1473 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $0$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1474 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1475 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $0$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1476 attribute \src "ls180.v:5530.1-5534.4" wire width 3 $0$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1491 attribute \src "ls180.v:5530.1-5534.4" wire width 25 $0$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1492 attribute \src "ls180.v:5530.1-5534.4" wire width 25 $0$memwr$\storage$ls180.v:5532$9_EN[24:0]$1493 attribute \src "ls180.v:5544.1-5548.4" wire width 3 $0$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1501 attribute \src "ls180.v:5544.1-5548.4" wire width 25 $0$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1502 attribute \src "ls180.v:5544.1-5548.4" wire width 25 $0$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1503 attribute \src "ls180.v:5558.1-5562.4" wire width 3 $0$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1511 attribute \src "ls180.v:5558.1-5562.4" wire width 25 $0$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1512 attribute \src "ls180.v:5558.1-5562.4" wire width 25 $0$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1513 attribute \src "ls180.v:5572.1-5576.4" wire width 3 $0$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1521 attribute \src "ls180.v:5572.1-5576.4" wire width 25 $0$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1522 attribute \src "ls180.v:5572.1-5576.4" wire width 25 $0$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1523 attribute \src "ls180.v:5587.1-5591.4" wire width 4 $0$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1531 attribute \src "ls180.v:5587.1-5591.4" wire width 10 $0$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1532 attribute \src "ls180.v:5587.1-5591.4" wire width 10 $0$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1533 attribute \src "ls180.v:5604.1-5608.4" wire width 4 $0$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1541 attribute \src "ls180.v:5604.1-5608.4" wire width 10 $0$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1542 attribute \src "ls180.v:5604.1-5608.4" wire width 10 $0$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1543 attribute \src "ls180.v:3940.1-3956.4" wire width 2 $0\array_muxed0[1:0] attribute \src "ls180.v:3957.1-3973.4" wire width 13 $0\array_muxed1[12:0] attribute \src "ls180.v:3974.1-3990.4" wire $0\array_muxed2[0:0] attribute \src "ls180.v:3991.1-4007.4" wire $0\array_muxed3[0:0] attribute \src "ls180.v:4008.1-4024.4" wire $0\array_muxed4[0:0] attribute \src "ls180.v:4025.1-4041.4" wire $0\array_muxed5[0:0] attribute \src "ls180.v:4042.1-4058.4" wire $0\array_muxed6[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\cmd_consumed[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\converter_counter[0:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\converter_counter_subfragments_next_value[0:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\converter_counter_subfragments_next_value_ce[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\converter_dat_r[31:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\converter_skip[0:0] attribute \src "ls180.v:4169.1-4274.4" wire width 16 $0\dfi_p0_rddata[15:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\dfi_p0_rddata_valid[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 40 $0\dummy[39:0] attribute \src "ls180.v:1490.1-1495.4" wire width 3 $0\eint_tmp[2:0] attribute \src "ls180.v:2894.1-2898.4" wire width 2 $0\eventmanager_pending_w[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\eventmanager_re[0:0] attribute \src "ls180.v:2883.1-2887.4" wire width 2 $0\eventmanager_status_w[1:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\eventmanager_storage[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio0_oe_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio0_oe_storage[7:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio0_out_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio0_out_storage[7:0] attribute \src "ls180.v:2962.1-2972.4" wire width 8 $0\gpio0_pads_gpio0i[7:0] attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio0_pads_gpio0o[7:0] attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio0_pads_gpio0oe[7:0] attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio0_status[7:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio1_oe_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio1_oe_storage[7:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\gpio1_out_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\gpio1_out_storage[7:0] attribute \src "ls180.v:2973.1-2983.4" wire width 8 $0\gpio1_pads_gpio1i[7:0] attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio1_pads_gpio1o[7:0] attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio1_pads_gpio1oe[7:0] attribute \src "ls180.v:4169.1-4274.4" wire width 8 $0\gpio1_status[7:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\i2c_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\i2c_storage[2:0] attribute \src "ls180.v:4165.1-4167.4" wire $0\int_rst[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_bus_errors[31:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_converter0_counter[0:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 64 $0\libresocsim_converter0_dat_r[63:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_converter0_skip[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_converter1_counter[0:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 64 $0\libresocsim_converter1_dat_r[63:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_converter1_skip[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_converter2_counter[0:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 64 $0\libresocsim_converter2_dat_r[63:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_converter2_skip[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 20 $0\libresocsim_count[19:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_en_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_en_storage[0:0] attribute \src "ls180.v:3140.1-3151.4" wire $0\libresocsim_error[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_eventmanager_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_eventmanager_storage[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\libresocsim_grant[1:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface0_bank_bus_dat_r[7:0] attribute \src "ls180.v:1523.1-1569.4" wire width 30 $0\libresocsim_interface0_converted_interface_adr[29:0] attribute \src "ls180.v:146.11-146.64" wire width 2 $0\libresocsim_interface0_converted_interface_bte[1:0] attribute \src "ls180.v:145.11-145.64" wire width 3 $0\libresocsim_interface0_converted_interface_cti[2:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_interface0_converted_interface_cyc[0:0] attribute \src "ls180.v:1511.1-1521.4" wire width 32 $0\libresocsim_interface0_converted_interface_dat_w[31:0] attribute \src "ls180.v:1523.1-1569.4" wire width 4 $0\libresocsim_interface0_converted_interface_sel[3:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_interface0_converted_interface_stb[0:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_interface0_converted_interface_we[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface1_bank_bus_dat_r[7:0] attribute \src "ls180.v:1583.1-1629.4" wire width 30 $0\libresocsim_interface1_converted_interface_adr[29:0] attribute \src "ls180.v:161.11-161.64" wire width 2 $0\libresocsim_interface1_converted_interface_bte[1:0] attribute \src "ls180.v:160.11-160.64" wire width 3 $0\libresocsim_interface1_converted_interface_cti[2:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_interface1_converted_interface_cyc[0:0] attribute \src "ls180.v:1571.1-1581.4" wire width 32 $0\libresocsim_interface1_converted_interface_dat_w[31:0] attribute \src "ls180.v:1583.1-1629.4" wire width 4 $0\libresocsim_interface1_converted_interface_sel[3:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_interface1_converted_interface_stb[0:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_interface1_converted_interface_we[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface2_bank_bus_dat_r[7:0] attribute \src "ls180.v:1643.1-1689.4" wire width 30 $0\libresocsim_interface2_converted_interface_adr[29:0] attribute \src "ls180.v:176.11-176.64" wire width 2 $0\libresocsim_interface2_converted_interface_bte[1:0] attribute \src "ls180.v:175.11-175.64" wire width 3 $0\libresocsim_interface2_converted_interface_cti[2:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_interface2_converted_interface_cyc[0:0] attribute \src "ls180.v:1631.1-1641.4" wire width 32 $0\libresocsim_interface2_converted_interface_dat_w[31:0] attribute \src "ls180.v:1643.1-1689.4" wire width 4 $0\libresocsim_interface2_converted_interface_sel[3:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_interface2_converted_interface_stb[0:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_interface2_converted_interface_we[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface3_bank_bus_dat_r[7:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface4_bank_bus_dat_r[7:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface5_bank_bus_dat_r[7:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface6_bank_bus_dat_r[7:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_interface7_bank_bus_dat_r[7:0] attribute \src "ls180.v:2984.1-3002.4" wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] attribute \src "ls180.v:3003.1-3021.4" wire width 16 $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] attribute \src "ls180.v:4169.1-4274.4" wire width 13 $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] attribute \src "ls180.v:4169.1-4274.4" wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] attribute \src "ls180.v:4169.1-4274.4" wire width 2 $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] attribute \src "ls180.v:4169.1-4274.4" wire width 16 $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] attribute \src "ls180.v:4169.1-4274.4" wire $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] attribute \src "ls180.v:121.5-121.64" wire $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] attribute \src "ls180.v:123.5-123.65" wire $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] attribute \src "ls180.v:122.5-122.65" wire $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] attribute \src "ls180.v:133.5-133.58" wire $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\libresocsim_libresoc_dbus_ack[0:0] attribute \src "ls180.v:61.5-61.41" wire $0\libresocsim_libresoc_dbus_err[0:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\libresocsim_libresoc_ibus_ack[0:0] attribute \src "ls180.v:70.5-70.41" wire $0\libresocsim_libresoc_ibus_err[0:0] attribute \src "ls180.v:1502.1-1509.4" wire width 16 $0\libresocsim_libresoc_interrupt[15:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\libresocsim_libresoc_jtag_wb_ack[0:0] attribute \src "ls180.v:101.5-101.44" wire $0\libresocsim_libresoc_jtag_wb_err[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 14 $0\libresocsim_libresocsim_adr[13:0] attribute \src "ls180.v:3026.1-3062.4" wire width 14 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\libresocsim_libresocsim_dat_w[7:0] attribute \src "ls180.v:3026.1-3062.4" wire width 8 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_libresocsim_we[0:0] attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] attribute \src "ls180.v:3026.1-3062.4" wire $0\libresocsim_libresocsim_wishbone_ack[0:0] attribute \src "ls180.v:3026.1-3062.4" wire width 32 $0\libresocsim_libresocsim_wishbone_dat_r[31:0] attribute \src "ls180.v:1065.5-1065.48" wire $0\libresocsim_libresocsim_wishbone_err[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_load_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_load_storage[31:0] attribute \src "ls180.v:3026.1-3062.4" wire width 2 $0\libresocsim_next_state[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_ram_bus_ack[0:0] attribute \src "ls180.v:192.5-192.35" wire $0\libresocsim_ram_bus_err[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_reload_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_reload_storage[31:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_reset_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_reset_storage[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_scratch_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_scratch_storage[31:0] attribute \src "ls180.v:3140.1-3151.4" wire $0\libresocsim_shared_ack[0:0] attribute \src "ls180.v:3140.1-3151.4" wire width 32 $0\libresocsim_shared_dat_r[31:0] attribute \src "ls180.v:3081.1-3089.4" wire width 6 $0\libresocsim_slave_sel[5:0] attribute \src "ls180.v:4276.1-5486.4" wire width 6 $0\libresocsim_slave_sel_r[5:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\libresocsim_state[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_update_value_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_update_value_storage[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_value[31:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\libresocsim_value_status[31:0] attribute \src "ls180.v:1692.1-1698.4" wire width 4 $0\libresocsim_we[3:0] attribute \src "ls180.v:1704.1-1709.4" wire $0\libresocsim_zero_clear[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_zero_old_trigger[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\libresocsim_zero_pending[0:0] attribute \src "ls180.v:2786.1-2832.4" wire width 30 $0\litedram_wb_adr[29:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\litedram_wb_cyc[0:0] attribute \src "ls180.v:2774.1-2784.4" wire width 16 $0\litedram_wb_dat_w[15:0] attribute \src "ls180.v:2786.1-2832.4" wire width 2 $0\litedram_wb_sel[1:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\litedram_wb_stb[0:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\litedram_wb_we[0:0] attribute \src "ls180.v:5490.1-5500.4" wire width 7 $0\memadr[6:0] attribute \src "ls180.v:5510.1-5520.4" wire width 5 $0\memadr_1[4:0] attribute \src "ls180.v:5530.1-5534.4" wire width 25 $0\memdat[24:0] attribute \src "ls180.v:5544.1-5548.4" wire width 25 $0\memdat_1[24:0] attribute \src "ls180.v:5558.1-5562.4" wire width 25 $0\memdat_2[24:0] attribute \src "ls180.v:5572.1-5576.4" wire width 25 $0\memdat_3[24:0] attribute \src "ls180.v:5587.1-5591.4" wire width 10 $0\memdat_4[9:0] attribute \src "ls180.v:5593.1-5596.4" wire width 10 $0\memdat_5[9:0] attribute \src "ls180.v:5604.1-5608.4" wire width 10 $0\memdat_6[9:0] attribute \src "ls180.v:5610.1-5613.4" wire width 10 $0\memdat_7[9:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\ram_bus_ram_bus_ack[0:0] attribute \src "ls180.v:234.5-234.31" wire $0\ram_bus_ram_bus_err[0:0] attribute \src "ls180.v:1713.1-1719.4" wire width 4 $0\ram_we[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\rddata_en[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\regs0[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\regs1[0:0] attribute \src "ls180.v:972.5-972.17" wire $0\reset[0:0] attribute \src "ls180.v:3426.1-3442.4" wire $0\rhs_array_muxed0[0:0] attribute \src "ls180.v:3647.1-3663.4" wire $0\rhs_array_muxed10[0:0] attribute \src "ls180.v:3664.1-3680.4" wire $0\rhs_array_muxed11[0:0] attribute \src "ls180.v:3732.1-3739.4" wire width 22 $0\rhs_array_muxed12[21:0] attribute \src "ls180.v:3740.1-3747.4" wire $0\rhs_array_muxed13[0:0] attribute \src "ls180.v:3748.1-3755.4" wire $0\rhs_array_muxed14[0:0] attribute \src "ls180.v:3756.1-3763.4" wire width 22 $0\rhs_array_muxed15[21:0] attribute \src "ls180.v:3764.1-3771.4" wire $0\rhs_array_muxed16[0:0] attribute \src "ls180.v:3772.1-3779.4" wire $0\rhs_array_muxed17[0:0] attribute \src "ls180.v:3780.1-3787.4" wire width 22 $0\rhs_array_muxed18[21:0] attribute \src "ls180.v:3788.1-3795.4" wire $0\rhs_array_muxed19[0:0] attribute \src "ls180.v:3443.1-3459.4" wire width 13 $0\rhs_array_muxed1[12:0] attribute \src "ls180.v:3796.1-3803.4" wire $0\rhs_array_muxed20[0:0] attribute \src "ls180.v:3804.1-3811.4" wire width 22 $0\rhs_array_muxed21[21:0] attribute \src "ls180.v:3812.1-3819.4" wire $0\rhs_array_muxed22[0:0] attribute \src "ls180.v:3820.1-3827.4" wire $0\rhs_array_muxed23[0:0] attribute \src "ls180.v:3828.1-3841.4" wire width 30 $0\rhs_array_muxed24[29:0] attribute \src "ls180.v:3842.1-3855.4" wire width 32 $0\rhs_array_muxed25[31:0] attribute \src "ls180.v:3856.1-3869.4" wire width 4 $0\rhs_array_muxed26[3:0] attribute \src "ls180.v:3870.1-3883.4" wire $0\rhs_array_muxed27[0:0] attribute \src "ls180.v:3884.1-3897.4" wire $0\rhs_array_muxed28[0:0] attribute \src "ls180.v:3898.1-3911.4" wire $0\rhs_array_muxed29[0:0] attribute \src "ls180.v:3460.1-3476.4" wire width 2 $0\rhs_array_muxed2[1:0] attribute \src "ls180.v:3912.1-3925.4" wire width 3 $0\rhs_array_muxed30[2:0] attribute \src "ls180.v:3926.1-3939.4" wire width 2 $0\rhs_array_muxed31[1:0] attribute \src "ls180.v:3477.1-3493.4" wire $0\rhs_array_muxed3[0:0] attribute \src "ls180.v:3494.1-3510.4" wire $0\rhs_array_muxed4[0:0] attribute \src "ls180.v:3511.1-3527.4" wire $0\rhs_array_muxed5[0:0] attribute \src "ls180.v:3579.1-3595.4" wire $0\rhs_array_muxed6[0:0] attribute \src "ls180.v:3596.1-3612.4" wire width 13 $0\rhs_array_muxed7[12:0] attribute \src "ls180.v:3613.1-3629.4" wire width 2 $0\rhs_array_muxed8[1:0] attribute \src "ls180.v:3630.1-3646.4" wire $0\rhs_array_muxed9[0:0] attribute \src "ls180.v:2888.1-2893.4" wire $0\rx_clear[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\rx_fifo_consume[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 5 $0\rx_fifo_level0[4:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\rx_fifo_produce[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\rx_fifo_readable[0:0] attribute \src "ls180.v:954.5-954.27" wire $0\rx_fifo_replace[0:0] attribute \src "ls180.v:2946.1-2953.4" wire width 4 $0\rx_fifo_wrport_adr[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\rx_old_trigger[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\rx_pending[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_address_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_address_storage[12:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_baddress_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_baddress_storage[1:0] attribute \src "ls180.v:1931.1-1938.4" wire $0\sdram_bankmachine0_auto_precharge[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:439.5-439.59" wire $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] attribute \src "ls180.v:422.5-422.62" wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] attribute \src "ls180.v:423.5-423.61" wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] attribute \src "ls180.v:1953.1-1960.4" wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:1920.1-1927.4" wire width 13 $0\sdram_bankmachine0_cmd_payload_a[12:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_cas[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_is_read[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_is_write[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_ras[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_payload_we[0:0] attribute \src "ls180.v:2618.1-2626.4" wire $0\sdram_bankmachine0_cmd_ready[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_cmd_valid[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_refresh_gnt[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_req_rdata_valid[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_req_wdata_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine0_row[12:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_row_close[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] attribute \src "ls180.v:1969.1-2062.4" wire $0\sdram_bankmachine0_row_open[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_row_opened[0:0] attribute \src "ls180.v:481.32-481.71" wire $0\sdram_bankmachine0_trascon_ready[0:0] attribute \src "ls180.v:479.32-479.70" wire $0\sdram_bankmachine0_trccon_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine0_twtpcon_count[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine0_twtpcon_ready[0:0] attribute \src "ls180.v:2088.1-2095.4" wire $0\sdram_bankmachine1_auto_precharge[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:521.5-521.59" wire $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] attribute \src "ls180.v:504.5-504.62" wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] attribute \src "ls180.v:505.5-505.61" wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] attribute \src "ls180.v:2110.1-2117.4" wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:2077.1-2084.4" wire width 13 $0\sdram_bankmachine1_cmd_payload_a[12:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_cas[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_is_read[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_is_write[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_ras[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_payload_we[0:0] attribute \src "ls180.v:2627.1-2635.4" wire $0\sdram_bankmachine1_cmd_ready[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_cmd_valid[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_refresh_gnt[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_req_rdata_valid[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_req_wdata_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine1_row[12:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_row_close[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] attribute \src "ls180.v:2126.1-2219.4" wire $0\sdram_bankmachine1_row_open[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_row_opened[0:0] attribute \src "ls180.v:563.32-563.71" wire $0\sdram_bankmachine1_trascon_ready[0:0] attribute \src "ls180.v:561.32-561.70" wire $0\sdram_bankmachine1_trccon_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine1_twtpcon_count[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine1_twtpcon_ready[0:0] attribute \src "ls180.v:2245.1-2252.4" wire $0\sdram_bankmachine2_auto_precharge[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:603.5-603.59" wire $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] attribute \src "ls180.v:586.5-586.62" wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] attribute \src "ls180.v:587.5-587.61" wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] attribute \src "ls180.v:2267.1-2274.4" wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:2234.1-2241.4" wire width 13 $0\sdram_bankmachine2_cmd_payload_a[12:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_cas[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_is_read[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_is_write[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_ras[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_payload_we[0:0] attribute \src "ls180.v:2636.1-2644.4" wire $0\sdram_bankmachine2_cmd_ready[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_cmd_valid[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_refresh_gnt[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_req_rdata_valid[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_req_wdata_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine2_row[12:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_row_close[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] attribute \src "ls180.v:2283.1-2376.4" wire $0\sdram_bankmachine2_row_open[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_row_opened[0:0] attribute \src "ls180.v:645.32-645.71" wire $0\sdram_bankmachine2_trascon_ready[0:0] attribute \src "ls180.v:643.32-643.70" wire $0\sdram_bankmachine2_trccon_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine2_twtpcon_count[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine2_twtpcon_ready[0:0] attribute \src "ls180.v:2402.1-2409.4" wire $0\sdram_bankmachine3_auto_precharge[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:685.5-685.59" wire $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] attribute \src "ls180.v:668.5-668.62" wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] attribute \src "ls180.v:669.5-669.61" wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] attribute \src "ls180.v:2424.1-2431.4" wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 22 $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:2391.1-2398.4" wire width 13 $0\sdram_bankmachine3_cmd_payload_a[12:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_cas[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_is_read[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_is_write[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_ras[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_payload_we[0:0] attribute \src "ls180.v:2645.1-2653.4" wire $0\sdram_bankmachine3_cmd_ready[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_cmd_valid[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_refresh_gnt[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_req_rdata_valid[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_req_wdata_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_bankmachine3_row[12:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_row_close[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] attribute \src "ls180.v:2440.1-2533.4" wire $0\sdram_bankmachine3_row_open[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_row_opened[0:0] attribute \src "ls180.v:727.32-727.71" wire $0\sdram_bankmachine3_trascon_ready[0:0] attribute \src "ls180.v:725.32-725.70" wire $0\sdram_bankmachine3_trccon_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_bankmachine3_twtpcon_count[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_bankmachine3_twtpcon_ready[0:0] attribute \src "ls180.v:2567.1-2572.4" wire $0\sdram_choose_cmd_cmd_payload_cas[0:0] attribute \src "ls180.v:2573.1-2578.4" wire $0\sdram_choose_cmd_cmd_payload_ras[0:0] attribute \src "ls180.v:2579.1-2584.4" wire $0\sdram_choose_cmd_cmd_payload_we[0:0] attribute \src "ls180.v:735.5-735.38" wire $0\sdram_choose_cmd_cmd_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_choose_cmd_grant[1:0] attribute \src "ls180.v:2553.1-2559.4" wire width 4 $0\sdram_choose_cmd_valids[3:0] attribute \src "ls180.v:733.5-733.43" wire $0\sdram_choose_cmd_want_activates[0:0] attribute \src "ls180.v:732.5-732.38" wire $0\sdram_choose_cmd_want_cmds[0:0] attribute \src "ls180.v:730.5-730.39" wire $0\sdram_choose_cmd_want_reads[0:0] attribute \src "ls180.v:731.5-731.40" wire $0\sdram_choose_cmd_want_writes[0:0] attribute \src "ls180.v:2600.1-2605.4" wire $0\sdram_choose_req_cmd_payload_cas[0:0] attribute \src "ls180.v:2606.1-2611.4" wire $0\sdram_choose_req_cmd_payload_ras[0:0] attribute \src "ls180.v:2612.1-2617.4" wire $0\sdram_choose_req_cmd_payload_we[0:0] attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_cmd_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_choose_req_grant[1:0] attribute \src "ls180.v:2586.1-2592.4" wire width 4 $0\sdram_choose_req_valids[3:0] attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_want_activates[0:0] attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_want_reads[0:0] attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_choose_req_want_writes[0:0] attribute \src "ls180.v:1875.1-1905.4" wire $0\sdram_cmd_last[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_cmd_payload_a[12:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_cmd_payload_ba[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_cmd_payload_cas[0:0] attribute \src "ls180.v:383.5-383.37" wire $0\sdram_cmd_payload_is_read[0:0] attribute \src "ls180.v:384.5-384.38" wire $0\sdram_cmd_payload_is_write[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_cmd_payload_ras[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_cmd_payload_we[0:0] attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_cmd_ready[0:0] attribute \src "ls180.v:1875.1-1905.4" wire $0\sdram_cmd_valid[0:0] attribute \src "ls180.v:319.5-319.33" wire $0\sdram_command_issue_w[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_command_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 6 $0\sdram_command_storage[5:0] attribute \src "ls180.v:368.5-368.30" wire $0\sdram_dfi_p0_act_n[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 13 $0\sdram_dfi_p0_address[12:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\sdram_dfi_p0_bank[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_cas_n[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_cs_n[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_ras_n[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_rddata_en[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_we_n[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_dfi_p0_wrdata_en[0:0] attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_en0[0:0] attribute \src "ls180.v:2658.1-2730.4" wire $0\sdram_en1[0:0] attribute \src "ls180.v:2754.1-2767.4" wire width 16 $0\sdram_interface_wdata[15:0] attribute \src "ls180.v:2754.1-2767.4" wire width 2 $0\sdram_interface_wdata_we[1:0] attribute \src "ls180.v:269.5-269.31" wire $0\sdram_inti_p0_act_n[0:0] attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_cas_n[0:0] attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_cs_n[0:0] attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_ras_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire width 16 $0\sdram_inti_p0_rddata[15:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_inti_p0_rddata_valid[0:0] attribute \src "ls180.v:1816.1-1832.4" wire $0\sdram_inti_p0_we_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_act_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire width 13 $0\sdram_master_p0_address[12:0] attribute \src "ls180.v:1758.1-1812.4" wire width 2 $0\sdram_master_p0_bank[1:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_cas_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_cke[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_cs_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_odt[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_ras_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_rddata_en[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_reset_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_we_n[0:0] attribute \src "ls180.v:1758.1-1812.4" wire width 16 $0\sdram_master_p0_wrdata[15:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_master_p0_wrdata_en[0:0] attribute \src "ls180.v:1758.1-1812.4" wire width 2 $0\sdram_master_p0_wrdata_mask[1:0] attribute \src "ls180.v:766.12-766.31" wire width 13 $0\sdram_nop_a[12:0] attribute \src "ls180.v:767.11-767.30" wire width 2 $0\sdram_nop_ba[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_postponer_count[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_postponer_req_o[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_sequencer_count[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_sequencer_counter[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_sequencer_done1[0:0] attribute \src "ls180.v:1875.1-1905.4" wire $0\sdram_sequencer_start0[0:0] attribute \src "ls180.v:1758.1-1812.4" wire width 16 $0\sdram_slave_p0_rddata[15:0] attribute \src "ls180.v:1758.1-1812.4" wire $0\sdram_slave_p0_rddata_valid[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 16 $0\sdram_status[15:0] attribute \src "ls180.v:769.5-769.26" wire $0\sdram_steerer0[0:0] attribute \src "ls180.v:770.5-770.26" wire $0\sdram_steerer1[0:0] attribute \src "ls180.v:2658.1-2730.4" wire width 2 $0\sdram_steerer_sel[1:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_storage[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_tccdcon_count[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_tccdcon_ready[0:0] attribute \src "ls180.v:774.32-774.58" wire $0\sdram_tfawcon_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 5 $0\sdram_time0[4:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\sdram_time1[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 10 $0\sdram_timer_count1[9:0] attribute \src "ls180.v:772.32-772.58" wire $0\sdram_trrdcon_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\sdram_twtrcon_count[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_twtrcon_ready[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\sdram_wrdata_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 16 $0\sdram_wrdata_storage[15:0] attribute \src "ls180.v:1969.1-2062.4" wire width 3 $0\subfragments_bankmachine0_next_state[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine0_state[2:0] attribute \src "ls180.v:2126.1-2219.4" wire width 3 $0\subfragments_bankmachine1_next_state[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine1_state[2:0] attribute \src "ls180.v:2283.1-2376.4" wire width 3 $0\subfragments_bankmachine2_next_state[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine2_state[2:0] attribute \src "ls180.v:2440.1-2533.4" wire width 3 $0\subfragments_bankmachine3_next_state[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_bankmachine3_state[2:0] attribute \src "ls180.v:1523.1-1569.4" wire $0\subfragments_converter0_next_state[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_converter0_state[0:0] attribute \src "ls180.v:1583.1-1629.4" wire $0\subfragments_converter1_next_state[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_converter1_state[0:0] attribute \src "ls180.v:1643.1-1689.4" wire $0\subfragments_converter2_next_state[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_converter2_state[0:0] attribute \src "ls180.v:1038.5-1038.32" wire $0\subfragments_locked0[0:0] attribute \src "ls180.v:1039.5-1039.32" wire $0\subfragments_locked1[0:0] attribute \src "ls180.v:1040.5-1040.32" wire $0\subfragments_locked2[0:0] attribute \src "ls180.v:1041.5-1041.32" wire $0\subfragments_locked3[0:0] attribute \src "ls180.v:2658.1-2730.4" wire width 3 $0\subfragments_multiplexer_next_state[2:0] attribute \src "ls180.v:4276.1-5486.4" wire width 3 $0\subfragments_multiplexer_state[2:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid0[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid1[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid2[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_rdata_valid3[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_new_master_wdata_ready[0:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\subfragments_next_state[0:0] attribute \src "ls180.v:1875.1-1905.4" wire width 2 $0\subfragments_refresher_next_state[1:0] attribute \src "ls180.v:4276.1-5486.4" wire width 2 $0\subfragments_refresher_state[1:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\subfragments_state[0:0] attribute \src "ls180.v:3528.1-3544.4" wire $0\t_array_muxed0[0:0] attribute \src "ls180.v:3545.1-3561.4" wire $0\t_array_muxed1[0:0] attribute \src "ls180.v:3562.1-3578.4" wire $0\t_array_muxed2[0:0] attribute \src "ls180.v:3681.1-3697.4" wire $0\t_array_muxed3[0:0] attribute \src "ls180.v:3698.1-3714.4" wire $0\t_array_muxed4[0:0] attribute \src "ls180.v:3715.1-3731.4" wire $0\t_array_muxed5[0:0] attribute \src "ls180.v:2877.1-2882.4" wire $0\tx_clear[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\tx_fifo_consume[3:0] attribute \src "ls180.v:4276.1-5486.4" wire width 5 $0\tx_fifo_level0[4:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\tx_fifo_produce[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\tx_fifo_readable[0:0] attribute \src "ls180.v:917.5-917.27" wire $0\tx_fifo_replace[0:0] attribute \src "ls180.v:900.5-900.30" wire $0\tx_fifo_sink_first[0:0] attribute \src "ls180.v:901.5-901.29" wire $0\tx_fifo_sink_last[0:0] attribute \src "ls180.v:2916.1-2923.4" wire width 4 $0\tx_fifo_wrport_adr[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\tx_old_trigger[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\tx_pending[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\uart_phy_phase_accumulator_rx[31:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\uart_phy_phase_accumulator_tx[31:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_re[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\uart_phy_rx_bitcount[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_rx_busy[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_rx_r[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\uart_phy_rx_reg[7:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_sink_ready[0:0] attribute \src "ls180.v:845.5-845.33" wire $0\uart_phy_source_first[0:0] attribute \src "ls180.v:846.5-846.32" wire $0\uart_phy_source_last[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\uart_phy_source_payload_data[7:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_source_valid[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 32 $0\uart_phy_storage[31:0] attribute \src "ls180.v:4276.1-5486.4" wire width 4 $0\uart_phy_tx_bitcount[3:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_tx_busy[0:0] attribute \src "ls180.v:4276.1-5486.4" wire width 8 $0\uart_phy_tx_reg[7:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_uart_clk_rxen[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\uart_phy_uart_clk_txen[0:0] attribute \src "ls180.v:2786.1-2832.4" wire $0\wb_sdram_ack[0:0] attribute \src "ls180.v:813.5-813.24" wire $0\wb_sdram_err[0:0] attribute \src "ls180.v:4276.1-5486.4" wire $0\wdata_consumed[0:0] attribute \src "ls180.v:5490.1-5500.4" wire width 7 $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 attribute \src "ls180.v:5490.1-5500.4" wire width 7 $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 attribute \src "ls180.v:5490.1-5500.4" wire width 7 $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 attribute \src "ls180.v:5490.1-5500.4" wire width 7 $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 attribute \src "ls180.v:5490.1-5500.4" wire width 32 $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 attribute \src "ls180.v:5510.1-5520.4" wire width 5 $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 attribute \src "ls180.v:5510.1-5520.4" wire width 32 $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 attribute \src "ls180.v:5530.1-5534.4" wire width 3 $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 attribute \src "ls180.v:5530.1-5534.4" wire width 25 $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 attribute \src "ls180.v:5530.1-5534.4" wire width 25 $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 attribute \src "ls180.v:5544.1-5548.4" wire width 3 $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 attribute \src "ls180.v:5544.1-5548.4" wire width 25 $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 attribute \src "ls180.v:5544.1-5548.4" wire width 25 $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 attribute \src "ls180.v:5558.1-5562.4" wire width 3 $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 attribute \src "ls180.v:5558.1-5562.4" wire width 25 $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 attribute \src "ls180.v:5558.1-5562.4" wire width 25 $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 attribute \src "ls180.v:5572.1-5576.4" wire width 3 $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 attribute \src "ls180.v:5572.1-5576.4" wire width 25 $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 attribute \src "ls180.v:5572.1-5576.4" wire width 25 $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 attribute \src "ls180.v:5587.1-5591.4" wire width 4 $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 attribute \src "ls180.v:5587.1-5591.4" wire width 10 $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 attribute \src "ls180.v:5587.1-5591.4" wire width 10 $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 attribute \src "ls180.v:5604.1-5608.4" wire width 4 $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 attribute \src "ls180.v:5604.1-5608.4" wire width 10 $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 attribute \src "ls180.v:5604.1-5608.4" wire width 10 $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 attribute \src "ls180.v:1375.11-1375.30" wire width 2 $1\array_muxed0[1:0] attribute \src "ls180.v:1376.12-1376.32" wire width 13 $1\array_muxed1[12:0] attribute \src "ls180.v:1377.5-1377.24" wire $1\array_muxed2[0:0] attribute \src "ls180.v:1378.5-1378.24" wire $1\array_muxed3[0:0] attribute \src "ls180.v:1379.5-1379.24" wire $1\array_muxed4[0:0] attribute \src "ls180.v:1380.5-1380.24" wire $1\array_muxed5[0:0] attribute \src "ls180.v:1381.5-1381.24" wire $1\array_muxed6[0:0] attribute \src "ls180.v:826.5-826.24" wire $1\cmd_consumed[0:0] attribute \src "ls180.v:823.5-823.29" wire $1\converter_counter[0:0] attribute \src "ls180.v:1049.5-1049.53" wire $1\converter_counter_subfragments_next_value[0:0] attribute \src "ls180.v:1050.5-1050.56" wire $1\converter_counter_subfragments_next_value_ce[0:0] attribute \src "ls180.v:825.12-825.35" wire width 32 $1\converter_dat_r[31:0] attribute \src "ls180.v:822.5-822.26" wire $1\converter_skip[0:0] attribute \src "ls180.v:257.12-257.33" wire width 16 $1\dfi_p0_rddata[15:0] attribute \src "ls180.v:258.5-258.31" wire $1\dfi_p0_rddata_valid[0:0] attribute \src "ls180.v:993.12-993.25" wire width 40 $1\dummy[39:0] attribute \src "ls180.v:991.11-991.26" wire width 3 $1\eint_tmp[2:0] attribute \src "ls180.v:881.11-881.40" wire width 2 $1\eventmanager_pending_w[1:0] attribute \src "ls180.v:883.5-883.27" wire $1\eventmanager_re[0:0] attribute \src "ls180.v:877.11-877.39" wire width 2 $1\eventmanager_status_w[1:0] attribute \src "ls180.v:882.11-882.38" wire width 2 $1\eventmanager_storage[1:0] attribute \src "ls180.v:974.5-974.23" wire $1\gpio0_oe_re[0:0] attribute \src "ls180.v:973.11-973.34" wire width 8 $1\gpio0_oe_storage[7:0] attribute \src "ls180.v:978.5-978.24" wire $1\gpio0_out_re[0:0] attribute \src "ls180.v:977.11-977.35" wire width 8 $1\gpio0_out_storage[7:0] attribute \src "ls180.v:979.11-979.35" wire width 8 $1\gpio0_pads_gpio0i[7:0] attribute \src "ls180.v:980.11-980.35" wire width 8 $1\gpio0_pads_gpio0o[7:0] attribute \src "ls180.v:981.11-981.36" wire width 8 $1\gpio0_pads_gpio0oe[7:0] attribute \src "ls180.v:975.11-975.30" wire width 8 $1\gpio0_status[7:0] attribute \src "ls180.v:983.5-983.23" wire $1\gpio1_oe_re[0:0] attribute \src "ls180.v:982.11-982.34" wire width 8 $1\gpio1_oe_storage[7:0] attribute \src "ls180.v:987.5-987.24" wire $1\gpio1_out_re[0:0] attribute \src "ls180.v:986.11-986.35" wire width 8 $1\gpio1_out_storage[7:0] attribute \src "ls180.v:988.11-988.35" wire width 8 $1\gpio1_pads_gpio1i[7:0] attribute \src "ls180.v:989.11-989.35" wire width 8 $1\gpio1_pads_gpio1o[7:0] attribute \src "ls180.v:990.11-990.36" wire width 8 $1\gpio1_pads_gpio1oe[7:0] attribute \src "ls180.v:984.11-984.30" wire width 8 $1\gpio1_status[7:0] attribute \src "ls180.v:998.5-998.18" wire $1\i2c_re[0:0] attribute \src "ls180.v:997.11-997.29" wire width 3 $1\i2c_storage[2:0] attribute \src "ls180.v:242.5-242.19" wire $1\int_rst[0:0] attribute \src "ls180.v:50.12-50.42" wire width 32 $1\libresocsim_bus_errors[31:0] attribute \src "ls180.v:149.5-149.42" wire $1\libresocsim_converter0_counter[0:0] attribute \src "ls180.v:1004.5-1004.77" wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] attribute \src "ls180.v:1005.5-1005.80" wire $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] attribute \src "ls180.v:151.12-151.48" wire width 64 $1\libresocsim_converter0_dat_r[63:0] attribute \src "ls180.v:148.5-148.39" wire $1\libresocsim_converter0_skip[0:0] attribute \src "ls180.v:164.5-164.42" wire $1\libresocsim_converter1_counter[0:0] attribute \src "ls180.v:1008.5-1008.77" wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] attribute \src "ls180.v:1009.5-1009.80" wire $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] attribute \src "ls180.v:166.12-166.48" wire width 64 $1\libresocsim_converter1_dat_r[63:0] attribute \src "ls180.v:163.5-163.39" wire $1\libresocsim_converter1_skip[0:0] attribute \src "ls180.v:179.5-179.42" wire $1\libresocsim_converter2_counter[0:0] attribute \src "ls180.v:1012.5-1012.77" wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] attribute \src "ls180.v:1013.5-1013.80" wire $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] attribute \src "ls180.v:181.12-181.48" wire width 64 $1\libresocsim_converter2_dat_r[63:0] attribute \src "ls180.v:178.5-178.39" wire $1\libresocsim_converter2_skip[0:0] attribute \src "ls180.v:1084.12-1084.43" wire width 20 $1\libresocsim_count[19:0] attribute \src "ls180.v:202.5-202.29" wire $1\libresocsim_en_re[0:0] attribute \src "ls180.v:201.5-201.34" wire $1\libresocsim_en_storage[0:0] attribute \src "ls180.v:1081.5-1081.29" wire $1\libresocsim_error[0:0] attribute \src "ls180.v:222.5-222.39" wire $1\libresocsim_eventmanager_re[0:0] attribute \src "ls180.v:221.5-221.44" wire $1\libresocsim_eventmanager_storage[0:0] attribute \src "ls180.v:1078.11-1078.35" wire width 2 $1\libresocsim_grant[1:0] attribute \src "ls180.v:1088.11-1088.55" wire width 8 $1\libresocsim_interface0_bank_bus_dat_r[7:0] attribute \src "ls180.v:137.12-137.66" wire width 30 $1\libresocsim_interface0_converted_interface_adr[29:0] attribute \src "ls180.v:141.5-141.58" wire $1\libresocsim_interface0_converted_interface_cyc[0:0] attribute \src "ls180.v:138.12-138.68" wire width 32 $1\libresocsim_interface0_converted_interface_dat_w[31:0] attribute \src "ls180.v:140.11-140.64" wire width 4 $1\libresocsim_interface0_converted_interface_sel[3:0] attribute \src "ls180.v:142.5-142.58" wire $1\libresocsim_interface0_converted_interface_stb[0:0] attribute \src "ls180.v:144.5-144.57" wire $1\libresocsim_interface0_converted_interface_we[0:0] attribute \src "ls180.v:1129.11-1129.55" wire width 8 $1\libresocsim_interface1_bank_bus_dat_r[7:0] attribute \src "ls180.v:152.12-152.66" wire width 30 $1\libresocsim_interface1_converted_interface_adr[29:0] attribute \src "ls180.v:156.5-156.58" wire $1\libresocsim_interface1_converted_interface_cyc[0:0] attribute \src "ls180.v:153.12-153.68" wire width 32 $1\libresocsim_interface1_converted_interface_dat_w[31:0] attribute \src "ls180.v:155.11-155.64" wire width 4 $1\libresocsim_interface1_converted_interface_sel[3:0] attribute \src "ls180.v:157.5-157.58" wire $1\libresocsim_interface1_converted_interface_stb[0:0] attribute \src "ls180.v:159.5-159.57" wire $1\libresocsim_interface1_converted_interface_we[0:0] attribute \src "ls180.v:1146.11-1146.55" wire width 8 $1\libresocsim_interface2_bank_bus_dat_r[7:0] attribute \src "ls180.v:167.12-167.66" wire width 30 $1\libresocsim_interface2_converted_interface_adr[29:0] attribute \src "ls180.v:171.5-171.58" wire $1\libresocsim_interface2_converted_interface_cyc[0:0] attribute \src "ls180.v:168.12-168.68" wire width 32 $1\libresocsim_interface2_converted_interface_dat_w[31:0] attribute \src "ls180.v:170.11-170.64" wire width 4 $1\libresocsim_interface2_converted_interface_sel[3:0] attribute \src "ls180.v:172.5-172.58" wire $1\libresocsim_interface2_converted_interface_stb[0:0] attribute \src "ls180.v:174.5-174.57" wire $1\libresocsim_interface2_converted_interface_we[0:0] attribute \src "ls180.v:1163.11-1163.55" wire width 8 $1\libresocsim_interface3_bank_bus_dat_r[7:0] attribute \src "ls180.v:1176.11-1176.55" wire width 8 $1\libresocsim_interface4_bank_bus_dat_r[7:0] attribute \src "ls180.v:1217.11-1217.55" wire width 8 $1\libresocsim_interface5_bank_bus_dat_r[7:0] attribute \src "ls180.v:1282.11-1282.55" wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0] attribute \src "ls180.v:1307.11-1307.55" wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0] attribute \src "ls180.v:130.12-130.65" wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] attribute \src "ls180.v:131.12-131.66" wire width 16 $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] attribute \src "ls180.v:109.12-109.66" wire width 13 $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] attribute \src "ls180.v:118.11-118.65" wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] attribute \src "ls180.v:115.5-115.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] attribute \src "ls180.v:117.5-117.60" wire $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] attribute \src "ls180.v:120.5-120.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] attribute \src "ls180.v:116.5-116.61" wire $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] attribute \src "ls180.v:119.11-119.65" wire width 2 $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] attribute \src "ls180.v:111.12-111.69" wire width 16 $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] attribute \src "ls180.v:112.5-112.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] attribute \src "ls180.v:114.5-114.62" wire $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] attribute \src "ls180.v:113.5-113.61" wire $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] attribute \src "ls180.v:132.5-132.58" wire $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] attribute \src "ls180.v:59.5-59.41" wire $1\libresocsim_libresoc_dbus_ack[0:0] attribute \src "ls180.v:68.5-68.41" wire $1\libresocsim_libresoc_ibus_ack[0:0] attribute \src "ls180.v:52.12-52.50" wire width 16 $1\libresocsim_libresoc_interrupt[15:0] attribute \src "ls180.v:99.5-99.44" wire $1\libresocsim_libresoc_jtag_wb_ack[0:0] attribute \src "ls180.v:1051.12-1051.47" wire width 14 $1\libresocsim_libresocsim_adr[13:0] attribute \src "ls180.v:1333.12-1333.71" wire width 14 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] attribute \src "ls180.v:1334.5-1334.66" wire $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] attribute \src "ls180.v:1053.11-1053.47" wire width 8 $1\libresocsim_libresocsim_dat_w[7:0] attribute \src "ls180.v:1331.11-1331.71" wire width 8 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] attribute \src "ls180.v:1332.5-1332.68" wire $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] attribute \src "ls180.v:1052.5-1052.38" wire $1\libresocsim_libresocsim_we[0:0] attribute \src "ls180.v:1335.5-1335.62" wire $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] attribute \src "ls180.v:1336.5-1336.65" wire $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] attribute \src "ls180.v:1061.5-1061.48" wire $1\libresocsim_libresocsim_wishbone_ack[0:0] attribute \src "ls180.v:1057.12-1057.58" wire width 32 $1\libresocsim_libresocsim_wishbone_dat_r[31:0] attribute \src "ls180.v:198.5-198.31" wire $1\libresocsim_load_re[0:0] attribute \src "ls180.v:197.12-197.44" wire width 32 $1\libresocsim_load_storage[31:0] attribute \src "ls180.v:1330.11-1330.40" wire width 2 $1\libresocsim_next_state[1:0] attribute \src "ls180.v:188.5-188.35" wire $1\libresocsim_ram_bus_ack[0:0] attribute \src "ls180.v:200.5-200.33" wire $1\libresocsim_reload_re[0:0] attribute \src "ls180.v:199.12-199.46" wire width 32 $1\libresocsim_reload_storage[31:0] attribute \src "ls180.v:43.5-43.32" wire $1\libresocsim_reset_re[0:0] attribute \src "ls180.v:42.5-42.37" wire $1\libresocsim_reset_storage[0:0] attribute \src "ls180.v:45.5-45.34" wire $1\libresocsim_scratch_re[0:0] attribute \src "ls180.v:44.12-44.55" wire width 32 $1\libresocsim_scratch_storage[31:0] attribute \src "ls180.v:1072.5-1072.34" wire $1\libresocsim_shared_ack[0:0] attribute \src "ls180.v:1068.12-1068.44" wire width 32 $1\libresocsim_shared_dat_r[31:0] attribute \src "ls180.v:1079.11-1079.39" wire width 6 $1\libresocsim_slave_sel[5:0] attribute \src "ls180.v:1080.11-1080.41" wire width 6 $1\libresocsim_slave_sel_r[5:0] attribute \src "ls180.v:1329.11-1329.35" wire width 2 $1\libresocsim_state[1:0] attribute \src "ls180.v:204.5-204.39" wire $1\libresocsim_update_value_re[0:0] attribute \src "ls180.v:203.5-203.44" wire $1\libresocsim_update_value_storage[0:0] attribute \src "ls180.v:223.12-223.37" wire width 32 $1\libresocsim_value[31:0] attribute \src "ls180.v:205.12-205.44" wire width 32 $1\libresocsim_value_status[31:0] attribute \src "ls180.v:195.11-195.32" wire width 4 $1\libresocsim_we[3:0] attribute \src "ls180.v:211.5-211.34" wire $1\libresocsim_zero_clear[0:0] attribute \src "ls180.v:212.5-212.40" wire $1\libresocsim_zero_old_trigger[0:0] attribute \src "ls180.v:209.5-209.36" wire $1\libresocsim_zero_pending[0:0] attribute \src "ls180.v:814.12-814.35" wire width 30 $1\litedram_wb_adr[29:0] attribute \src "ls180.v:818.5-818.27" wire $1\litedram_wb_cyc[0:0] attribute \src "ls180.v:815.12-815.37" wire width 16 $1\litedram_wb_dat_w[15:0] attribute \src "ls180.v:817.11-817.33" wire width 2 $1\litedram_wb_sel[1:0] attribute \src "ls180.v:819.5-819.27" wire $1\litedram_wb_stb[0:0] attribute \src "ls180.v:821.5-821.26" wire $1\litedram_wb_we[0:0] attribute \src "ls180.v:230.5-230.31" wire $1\ram_bus_ram_bus_ack[0:0] attribute \src "ls180.v:237.11-237.24" wire width 4 $1\ram_we[3:0] attribute \src "ls180.v:259.11-259.27" wire width 3 $1\rddata_en[2:0] attribute \src "ls180.v:1438.32-1438.44" wire $1\regs0[0:0] attribute \src "ls180.v:1439.32-1439.44" wire $1\regs1[0:0] attribute \src "ls180.v:1337.5-1337.28" wire $1\rhs_array_muxed0[0:0] attribute \src "ls180.v:1350.5-1350.29" wire $1\rhs_array_muxed10[0:0] attribute \src "ls180.v:1351.5-1351.29" wire $1\rhs_array_muxed11[0:0] attribute \src "ls180.v:1355.12-1355.37" wire width 22 $1\rhs_array_muxed12[21:0] attribute \src "ls180.v:1356.5-1356.29" wire $1\rhs_array_muxed13[0:0] attribute \src "ls180.v:1357.5-1357.29" wire $1\rhs_array_muxed14[0:0] attribute \src "ls180.v:1358.12-1358.37" wire width 22 $1\rhs_array_muxed15[21:0] attribute \src "ls180.v:1359.5-1359.29" wire $1\rhs_array_muxed16[0:0] attribute \src "ls180.v:1360.5-1360.29" wire $1\rhs_array_muxed17[0:0] attribute \src "ls180.v:1361.12-1361.37" wire width 22 $1\rhs_array_muxed18[21:0] attribute \src "ls180.v:1362.5-1362.29" wire $1\rhs_array_muxed19[0:0] attribute \src "ls180.v:1338.12-1338.36" wire width 13 $1\rhs_array_muxed1[12:0] attribute \src "ls180.v:1363.5-1363.29" wire $1\rhs_array_muxed20[0:0] attribute \src "ls180.v:1364.12-1364.37" wire width 22 $1\rhs_array_muxed21[21:0] attribute \src "ls180.v:1365.5-1365.29" wire $1\rhs_array_muxed22[0:0] attribute \src "ls180.v:1366.5-1366.29" wire $1\rhs_array_muxed23[0:0] attribute \src "ls180.v:1367.12-1367.37" wire width 30 $1\rhs_array_muxed24[29:0] attribute \src "ls180.v:1368.12-1368.37" wire width 32 $1\rhs_array_muxed25[31:0] attribute \src "ls180.v:1369.11-1369.35" wire width 4 $1\rhs_array_muxed26[3:0] attribute \src "ls180.v:1370.5-1370.29" wire $1\rhs_array_muxed27[0:0] attribute \src "ls180.v:1371.5-1371.29" wire $1\rhs_array_muxed28[0:0] attribute \src "ls180.v:1372.5-1372.29" wire $1\rhs_array_muxed29[0:0] attribute \src "ls180.v:1339.11-1339.34" wire width 2 $1\rhs_array_muxed2[1:0] attribute \src "ls180.v:1373.11-1373.35" wire width 3 $1\rhs_array_muxed30[2:0] attribute \src "ls180.v:1374.11-1374.35" wire width 2 $1\rhs_array_muxed31[1:0] attribute \src "ls180.v:1340.5-1340.28" wire $1\rhs_array_muxed3[0:0] attribute \src "ls180.v:1341.5-1341.28" wire $1\rhs_array_muxed4[0:0] attribute \src "ls180.v:1342.5-1342.28" wire $1\rhs_array_muxed5[0:0] attribute \src "ls180.v:1346.5-1346.28" wire $1\rhs_array_muxed6[0:0] attribute \src "ls180.v:1347.12-1347.36" wire width 13 $1\rhs_array_muxed7[12:0] attribute \src "ls180.v:1348.11-1348.34" wire width 2 $1\rhs_array_muxed8[1:0] attribute \src "ls180.v:1349.5-1349.28" wire $1\rhs_array_muxed9[0:0] attribute \src "ls180.v:872.5-872.20" wire $1\rx_clear[0:0] attribute \src "ls180.v:956.11-956.33" wire width 4 $1\rx_fifo_consume[3:0] attribute \src "ls180.v:953.11-953.32" wire width 5 $1\rx_fifo_level0[4:0] attribute \src "ls180.v:955.11-955.33" wire width 4 $1\rx_fifo_produce[3:0] attribute \src "ls180.v:946.5-946.28" wire $1\rx_fifo_readable[0:0] attribute \src "ls180.v:957.11-957.36" wire width 4 $1\rx_fifo_wrport_adr[3:0] attribute \src "ls180.v:873.5-873.26" wire $1\rx_old_trigger[0:0] attribute \src "ls180.v:870.5-870.22" wire $1\rx_pending[0:0] attribute \src "ls180.v:321.5-321.28" wire $1\sdram_address_re[0:0] attribute \src "ls180.v:320.12-320.41" wire width 13 $1\sdram_address_storage[12:0] attribute \src "ls180.v:323.5-323.29" wire $1\sdram_baddress_re[0:0] attribute \src "ls180.v:322.11-322.40" wire width 2 $1\sdram_baddress_storage[1:0] attribute \src "ls180.v:419.5-419.45" wire $1\sdram_bankmachine0_auto_precharge[0:0] attribute \src "ls180.v:441.11-441.65" wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:438.11-438.63" wire width 4 $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:440.11-440.65" wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:442.11-442.68" wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:465.5-465.54" wire $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] attribute \src "ls180.v:466.5-466.53" wire $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] attribute \src "ls180.v:468.12-468.69" wire width 22 $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:467.5-467.59" wire $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:463.5-463.54" wire $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:411.12-411.52" wire width 13 $1\sdram_bankmachine0_cmd_payload_a[12:0] attribute \src "ls180.v:413.5-413.46" wire $1\sdram_bankmachine0_cmd_payload_cas[0:0] attribute \src "ls180.v:416.5-416.49" wire $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:417.5-417.50" wire $1\sdram_bankmachine0_cmd_payload_is_read[0:0] attribute \src "ls180.v:418.5-418.51" wire $1\sdram_bankmachine0_cmd_payload_is_write[0:0] attribute \src "ls180.v:414.5-414.46" wire $1\sdram_bankmachine0_cmd_payload_ras[0:0] attribute \src "ls180.v:415.5-415.45" wire $1\sdram_bankmachine0_cmd_payload_we[0:0] attribute \src "ls180.v:410.5-410.40" wire $1\sdram_bankmachine0_cmd_ready[0:0] attribute \src "ls180.v:409.5-409.40" wire $1\sdram_bankmachine0_cmd_valid[0:0] attribute \src "ls180.v:408.5-408.42" wire $1\sdram_bankmachine0_refresh_gnt[0:0] attribute \src "ls180.v:406.5-406.46" wire $1\sdram_bankmachine0_req_rdata_valid[0:0] attribute \src "ls180.v:405.5-405.46" wire $1\sdram_bankmachine0_req_wdata_ready[0:0] attribute \src "ls180.v:469.12-469.42" wire width 13 $1\sdram_bankmachine0_row[12:0] attribute \src "ls180.v:473.5-473.40" wire $1\sdram_bankmachine0_row_close[0:0] attribute \src "ls180.v:474.5-474.49" wire $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] attribute \src "ls180.v:472.5-472.39" wire $1\sdram_bankmachine0_row_open[0:0] attribute \src "ls180.v:470.5-470.41" wire $1\sdram_bankmachine0_row_opened[0:0] attribute \src "ls180.v:477.11-477.50" wire width 3 $1\sdram_bankmachine0_twtpcon_count[2:0] attribute \src "ls180.v:476.32-476.71" wire $1\sdram_bankmachine0_twtpcon_ready[0:0] attribute \src "ls180.v:501.5-501.45" wire $1\sdram_bankmachine1_auto_precharge[0:0] attribute \src "ls180.v:523.11-523.65" wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:520.11-520.63" wire width 4 $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:522.11-522.65" wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:524.11-524.68" wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:547.5-547.54" wire $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] attribute \src "ls180.v:548.5-548.53" wire $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] attribute \src "ls180.v:550.12-550.69" wire width 22 $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:549.5-549.59" wire $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:545.5-545.54" wire $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:493.12-493.52" wire width 13 $1\sdram_bankmachine1_cmd_payload_a[12:0] attribute \src "ls180.v:495.5-495.46" wire $1\sdram_bankmachine1_cmd_payload_cas[0:0] attribute \src "ls180.v:498.5-498.49" wire $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:499.5-499.50" wire $1\sdram_bankmachine1_cmd_payload_is_read[0:0] attribute \src "ls180.v:500.5-500.51" wire $1\sdram_bankmachine1_cmd_payload_is_write[0:0] attribute \src "ls180.v:496.5-496.46" wire $1\sdram_bankmachine1_cmd_payload_ras[0:0] attribute \src "ls180.v:497.5-497.45" wire $1\sdram_bankmachine1_cmd_payload_we[0:0] attribute \src "ls180.v:492.5-492.40" wire $1\sdram_bankmachine1_cmd_ready[0:0] attribute \src "ls180.v:491.5-491.40" wire $1\sdram_bankmachine1_cmd_valid[0:0] attribute \src "ls180.v:490.5-490.42" wire $1\sdram_bankmachine1_refresh_gnt[0:0] attribute \src "ls180.v:488.5-488.46" wire $1\sdram_bankmachine1_req_rdata_valid[0:0] attribute \src "ls180.v:487.5-487.46" wire $1\sdram_bankmachine1_req_wdata_ready[0:0] attribute \src "ls180.v:551.12-551.42" wire width 13 $1\sdram_bankmachine1_row[12:0] attribute \src "ls180.v:555.5-555.40" wire $1\sdram_bankmachine1_row_close[0:0] attribute \src "ls180.v:556.5-556.49" wire $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] attribute \src "ls180.v:554.5-554.39" wire $1\sdram_bankmachine1_row_open[0:0] attribute \src "ls180.v:552.5-552.41" wire $1\sdram_bankmachine1_row_opened[0:0] attribute \src "ls180.v:559.11-559.50" wire width 3 $1\sdram_bankmachine1_twtpcon_count[2:0] attribute \src "ls180.v:558.32-558.71" wire $1\sdram_bankmachine1_twtpcon_ready[0:0] attribute \src "ls180.v:583.5-583.45" wire $1\sdram_bankmachine2_auto_precharge[0:0] attribute \src "ls180.v:605.11-605.65" wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:602.11-602.63" wire width 4 $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:604.11-604.65" wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:606.11-606.68" wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:629.5-629.54" wire $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] attribute \src "ls180.v:630.5-630.53" wire $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] attribute \src "ls180.v:632.12-632.69" wire width 22 $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:631.5-631.59" wire $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:627.5-627.54" wire $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:575.12-575.52" wire width 13 $1\sdram_bankmachine2_cmd_payload_a[12:0] attribute \src "ls180.v:577.5-577.46" wire $1\sdram_bankmachine2_cmd_payload_cas[0:0] attribute \src "ls180.v:580.5-580.49" wire $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:581.5-581.50" wire $1\sdram_bankmachine2_cmd_payload_is_read[0:0] attribute \src "ls180.v:582.5-582.51" wire $1\sdram_bankmachine2_cmd_payload_is_write[0:0] attribute \src "ls180.v:578.5-578.46" wire $1\sdram_bankmachine2_cmd_payload_ras[0:0] attribute \src "ls180.v:579.5-579.45" wire $1\sdram_bankmachine2_cmd_payload_we[0:0] attribute \src "ls180.v:574.5-574.40" wire $1\sdram_bankmachine2_cmd_ready[0:0] attribute \src "ls180.v:573.5-573.40" wire $1\sdram_bankmachine2_cmd_valid[0:0] attribute \src "ls180.v:572.5-572.42" wire $1\sdram_bankmachine2_refresh_gnt[0:0] attribute \src "ls180.v:570.5-570.46" wire $1\sdram_bankmachine2_req_rdata_valid[0:0] attribute \src "ls180.v:569.5-569.46" wire $1\sdram_bankmachine2_req_wdata_ready[0:0] attribute \src "ls180.v:633.12-633.42" wire width 13 $1\sdram_bankmachine2_row[12:0] attribute \src "ls180.v:637.5-637.40" wire $1\sdram_bankmachine2_row_close[0:0] attribute \src "ls180.v:638.5-638.49" wire $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] attribute \src "ls180.v:636.5-636.39" wire $1\sdram_bankmachine2_row_open[0:0] attribute \src "ls180.v:634.5-634.41" wire $1\sdram_bankmachine2_row_opened[0:0] attribute \src "ls180.v:641.11-641.50" wire width 3 $1\sdram_bankmachine2_twtpcon_count[2:0] attribute \src "ls180.v:640.32-640.71" wire $1\sdram_bankmachine2_twtpcon_ready[0:0] attribute \src "ls180.v:665.5-665.45" wire $1\sdram_bankmachine3_auto_precharge[0:0] attribute \src "ls180.v:687.11-687.65" wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] attribute \src "ls180.v:684.11-684.63" wire width 4 $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] attribute \src "ls180.v:686.11-686.65" wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] attribute \src "ls180.v:688.11-688.68" wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] attribute \src "ls180.v:711.5-711.54" wire $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] attribute \src "ls180.v:712.5-712.53" wire $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] attribute \src "ls180.v:714.12-714.69" wire width 22 $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] attribute \src "ls180.v:713.5-713.59" wire $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] attribute \src "ls180.v:709.5-709.54" wire $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] attribute \src "ls180.v:657.12-657.52" wire width 13 $1\sdram_bankmachine3_cmd_payload_a[12:0] attribute \src "ls180.v:659.5-659.46" wire $1\sdram_bankmachine3_cmd_payload_cas[0:0] attribute \src "ls180.v:662.5-662.49" wire $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] attribute \src "ls180.v:663.5-663.50" wire $1\sdram_bankmachine3_cmd_payload_is_read[0:0] attribute \src "ls180.v:664.5-664.51" wire $1\sdram_bankmachine3_cmd_payload_is_write[0:0] attribute \src "ls180.v:660.5-660.46" wire $1\sdram_bankmachine3_cmd_payload_ras[0:0] attribute \src "ls180.v:661.5-661.45" wire $1\sdram_bankmachine3_cmd_payload_we[0:0] attribute \src "ls180.v:656.5-656.40" wire $1\sdram_bankmachine3_cmd_ready[0:0] attribute \src "ls180.v:655.5-655.40" wire $1\sdram_bankmachine3_cmd_valid[0:0] attribute \src "ls180.v:654.5-654.42" wire $1\sdram_bankmachine3_refresh_gnt[0:0] attribute \src "ls180.v:652.5-652.46" wire $1\sdram_bankmachine3_req_rdata_valid[0:0] attribute \src "ls180.v:651.5-651.46" wire $1\sdram_bankmachine3_req_wdata_ready[0:0] attribute \src "ls180.v:715.12-715.42" wire width 13 $1\sdram_bankmachine3_row[12:0] attribute \src "ls180.v:719.5-719.40" wire $1\sdram_bankmachine3_row_close[0:0] attribute \src "ls180.v:720.5-720.49" wire $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] attribute \src "ls180.v:718.5-718.39" wire $1\sdram_bankmachine3_row_open[0:0] attribute \src "ls180.v:716.5-716.41" wire $1\sdram_bankmachine3_row_opened[0:0] attribute \src "ls180.v:723.11-723.50" wire width 3 $1\sdram_bankmachine3_twtpcon_count[2:0] attribute \src "ls180.v:722.32-722.71" wire $1\sdram_bankmachine3_twtpcon_ready[0:0] attribute \src "ls180.v:738.5-738.44" wire $1\sdram_choose_cmd_cmd_payload_cas[0:0] attribute \src "ls180.v:739.5-739.44" wire $1\sdram_choose_cmd_cmd_payload_ras[0:0] attribute \src "ls180.v:740.5-740.43" wire $1\sdram_choose_cmd_cmd_payload_we[0:0] attribute \src "ls180.v:746.11-746.40" wire width 2 $1\sdram_choose_cmd_grant[1:0] attribute \src "ls180.v:744.11-744.41" wire width 4 $1\sdram_choose_cmd_valids[3:0] attribute \src "ls180.v:756.5-756.44" wire $1\sdram_choose_req_cmd_payload_cas[0:0] attribute \src "ls180.v:757.5-757.44" wire $1\sdram_choose_req_cmd_payload_ras[0:0] attribute \src "ls180.v:758.5-758.43" wire $1\sdram_choose_req_cmd_payload_we[0:0] attribute \src "ls180.v:753.5-753.38" wire $1\sdram_choose_req_cmd_ready[0:0] attribute \src "ls180.v:764.11-764.40" wire width 2 $1\sdram_choose_req_grant[1:0] attribute \src "ls180.v:762.11-762.41" wire width 4 $1\sdram_choose_req_valids[3:0] attribute \src "ls180.v:751.5-751.43" wire $1\sdram_choose_req_want_activates[0:0] attribute \src "ls180.v:748.5-748.39" wire $1\sdram_choose_req_want_reads[0:0] attribute \src "ls180.v:749.5-749.40" wire $1\sdram_choose_req_want_writes[0:0] attribute \src "ls180.v:377.5-377.26" wire $1\sdram_cmd_last[0:0] attribute \src "ls180.v:378.12-378.39" wire width 13 $1\sdram_cmd_payload_a[12:0] attribute \src "ls180.v:379.11-379.38" wire width 2 $1\sdram_cmd_payload_ba[1:0] attribute \src "ls180.v:380.5-380.33" wire $1\sdram_cmd_payload_cas[0:0] attribute \src "ls180.v:381.5-381.33" wire $1\sdram_cmd_payload_ras[0:0] attribute \src "ls180.v:382.5-382.32" wire $1\sdram_cmd_payload_we[0:0] attribute \src "ls180.v:376.5-376.27" wire $1\sdram_cmd_ready[0:0] attribute \src "ls180.v:375.5-375.27" wire $1\sdram_cmd_valid[0:0] attribute \src "ls180.v:315.5-315.28" wire $1\sdram_command_re[0:0] attribute \src "ls180.v:314.11-314.39" wire width 6 $1\sdram_command_storage[5:0] attribute \src "ls180.v:359.12-359.40" wire width 13 $1\sdram_dfi_p0_address[12:0] attribute \src "ls180.v:360.11-360.35" wire width 2 $1\sdram_dfi_p0_bank[1:0] attribute \src "ls180.v:361.5-361.30" wire $1\sdram_dfi_p0_cas_n[0:0] attribute \src "ls180.v:362.5-362.29" wire $1\sdram_dfi_p0_cs_n[0:0] attribute \src "ls180.v:363.5-363.30" wire $1\sdram_dfi_p0_ras_n[0:0] attribute \src "ls180.v:372.5-372.34" wire $1\sdram_dfi_p0_rddata_en[0:0] attribute \src "ls180.v:364.5-364.29" wire $1\sdram_dfi_p0_we_n[0:0] attribute \src "ls180.v:370.5-370.34" wire $1\sdram_dfi_p0_wrdata_en[0:0] attribute \src "ls180.v:783.5-783.21" wire $1\sdram_en0[0:0] attribute \src "ls180.v:786.5-786.21" wire $1\sdram_en1[0:0] attribute \src "ls180.v:356.12-356.41" wire width 16 $1\sdram_interface_wdata[15:0] attribute \src "ls180.v:357.11-357.42" wire width 2 $1\sdram_interface_wdata_we[1:0] attribute \src "ls180.v:262.5-262.31" wire $1\sdram_inti_p0_cas_n[0:0] attribute \src "ls180.v:263.5-263.30" wire $1\sdram_inti_p0_cs_n[0:0] attribute \src "ls180.v:264.5-264.31" wire $1\sdram_inti_p0_ras_n[0:0] attribute \src "ls180.v:274.12-274.40" wire width 16 $1\sdram_inti_p0_rddata[15:0] attribute \src "ls180.v:275.5-275.38" wire $1\sdram_inti_p0_rddata_valid[0:0] attribute \src "ls180.v:265.5-265.30" wire $1\sdram_inti_p0_we_n[0:0] attribute \src "ls180.v:301.5-301.33" wire $1\sdram_master_p0_act_n[0:0] attribute \src "ls180.v:292.12-292.43" wire width 13 $1\sdram_master_p0_address[12:0] attribute \src "ls180.v:293.11-293.38" wire width 2 $1\sdram_master_p0_bank[1:0] attribute \src "ls180.v:294.5-294.33" wire $1\sdram_master_p0_cas_n[0:0] attribute \src "ls180.v:298.5-298.31" wire $1\sdram_master_p0_cke[0:0] attribute \src "ls180.v:295.5-295.32" wire $1\sdram_master_p0_cs_n[0:0] attribute \src "ls180.v:299.5-299.31" wire $1\sdram_master_p0_odt[0:0] attribute \src "ls180.v:296.5-296.33" wire $1\sdram_master_p0_ras_n[0:0] attribute \src "ls180.v:305.5-305.37" wire $1\sdram_master_p0_rddata_en[0:0] attribute \src "ls180.v:300.5-300.35" wire $1\sdram_master_p0_reset_n[0:0] attribute \src "ls180.v:297.5-297.32" wire $1\sdram_master_p0_we_n[0:0] attribute \src "ls180.v:302.12-302.42" wire width 16 $1\sdram_master_p0_wrdata[15:0] attribute \src "ls180.v:303.5-303.37" wire $1\sdram_master_p0_wrdata_en[0:0] attribute \src "ls180.v:304.11-304.45" wire width 2 $1\sdram_master_p0_wrdata_mask[1:0] attribute \src "ls180.v:393.5-393.33" wire $1\sdram_postponer_count[0:0] attribute \src "ls180.v:392.5-392.33" wire $1\sdram_postponer_req_o[0:0] attribute \src "ls180.v:313.5-313.20" wire $1\sdram_re[0:0] attribute \src "ls180.v:399.5-399.33" wire $1\sdram_sequencer_count[0:0] attribute \src "ls180.v:398.11-398.41" wire width 4 $1\sdram_sequencer_counter[3:0] attribute \src "ls180.v:397.5-397.33" wire $1\sdram_sequencer_done1[0:0] attribute \src "ls180.v:394.5-394.34" wire $1\sdram_sequencer_start0[0:0] attribute \src "ls180.v:290.12-290.41" wire width 16 $1\sdram_slave_p0_rddata[15:0] attribute \src "ls180.v:291.5-291.39" wire $1\sdram_slave_p0_rddata_valid[0:0] attribute \src "ls180.v:326.12-326.32" wire width 16 $1\sdram_status[15:0] attribute \src "ls180.v:768.11-768.35" wire width 2 $1\sdram_steerer_sel[1:0] attribute \src "ls180.v:312.11-312.31" wire width 4 $1\sdram_storage[3:0] attribute \src "ls180.v:777.5-777.31" wire $1\sdram_tccdcon_count[0:0] attribute \src "ls180.v:776.32-776.58" wire $1\sdram_tccdcon_ready[0:0] attribute \src "ls180.v:785.11-785.29" wire width 5 $1\sdram_time0[4:0] attribute \src "ls180.v:788.11-788.29" wire width 4 $1\sdram_time1[3:0] attribute \src "ls180.v:390.11-390.39" wire width 10 $1\sdram_timer_count1[9:0] attribute \src "ls180.v:780.11-780.37" wire width 3 $1\sdram_twtrcon_count[2:0] attribute \src "ls180.v:779.32-779.58" wire $1\sdram_twtrcon_ready[0:0] attribute \src "ls180.v:325.5-325.27" wire $1\sdram_wrdata_re[0:0] attribute \src "ls180.v:324.12-324.40" wire width 16 $1\sdram_wrdata_storage[15:0] attribute \src "ls180.v:1017.11-1017.54" wire width 3 $1\subfragments_bankmachine0_next_state[2:0] attribute \src "ls180.v:1016.11-1016.49" wire width 3 $1\subfragments_bankmachine0_state[2:0] attribute \src "ls180.v:1019.11-1019.54" wire width 3 $1\subfragments_bankmachine1_next_state[2:0] attribute \src "ls180.v:1018.11-1018.49" wire width 3 $1\subfragments_bankmachine1_state[2:0] attribute \src "ls180.v:1021.11-1021.54" wire width 3 $1\subfragments_bankmachine2_next_state[2:0] attribute \src "ls180.v:1020.11-1020.49" wire width 3 $1\subfragments_bankmachine2_state[2:0] attribute \src "ls180.v:1023.11-1023.54" wire width 3 $1\subfragments_bankmachine3_next_state[2:0] attribute \src "ls180.v:1022.11-1022.49" wire width 3 $1\subfragments_bankmachine3_state[2:0] attribute \src "ls180.v:1003.5-1003.46" wire $1\subfragments_converter0_next_state[0:0] attribute \src "ls180.v:1002.5-1002.41" wire $1\subfragments_converter0_state[0:0] attribute \src "ls180.v:1007.5-1007.46" wire $1\subfragments_converter1_next_state[0:0] attribute \src "ls180.v:1006.5-1006.41" wire $1\subfragments_converter1_state[0:0] attribute \src "ls180.v:1011.5-1011.46" wire $1\subfragments_converter2_next_state[0:0] attribute \src "ls180.v:1010.5-1010.41" wire $1\subfragments_converter2_state[0:0] attribute \src "ls180.v:1025.11-1025.53" wire width 3 $1\subfragments_multiplexer_next_state[2:0] attribute \src "ls180.v:1024.11-1024.48" wire width 3 $1\subfragments_multiplexer_state[2:0] attribute \src "ls180.v:1043.5-1043.48" wire $1\subfragments_new_master_rdata_valid0[0:0] attribute \src "ls180.v:1044.5-1044.48" wire $1\subfragments_new_master_rdata_valid1[0:0] attribute \src "ls180.v:1045.5-1045.48" wire $1\subfragments_new_master_rdata_valid2[0:0] attribute \src "ls180.v:1046.5-1046.48" wire $1\subfragments_new_master_rdata_valid3[0:0] attribute \src "ls180.v:1042.5-1042.47" wire $1\subfragments_new_master_wdata_ready[0:0] attribute \src "ls180.v:1048.5-1048.35" wire $1\subfragments_next_state[0:0] attribute \src "ls180.v:1015.11-1015.51" wire width 2 $1\subfragments_refresher_next_state[1:0] attribute \src "ls180.v:1014.11-1014.46" wire width 2 $1\subfragments_refresher_state[1:0] attribute \src "ls180.v:1047.5-1047.30" wire $1\subfragments_state[0:0] attribute \src "ls180.v:1343.5-1343.26" wire $1\t_array_muxed0[0:0] attribute \src "ls180.v:1344.5-1344.26" wire $1\t_array_muxed1[0:0] attribute \src "ls180.v:1345.5-1345.26" wire $1\t_array_muxed2[0:0] attribute \src "ls180.v:1352.5-1352.26" wire $1\t_array_muxed3[0:0] attribute \src "ls180.v:1353.5-1353.26" wire $1\t_array_muxed4[0:0] attribute \src "ls180.v:1354.5-1354.26" wire $1\t_array_muxed5[0:0] attribute \src "ls180.v:867.5-867.20" wire $1\tx_clear[0:0] attribute \src "ls180.v:919.11-919.33" wire width 4 $1\tx_fifo_consume[3:0] attribute \src "ls180.v:916.11-916.32" wire width 5 $1\tx_fifo_level0[4:0] attribute \src "ls180.v:918.11-918.33" wire width 4 $1\tx_fifo_produce[3:0] attribute \src "ls180.v:909.5-909.28" wire $1\tx_fifo_readable[0:0] attribute \src "ls180.v:920.11-920.36" wire width 4 $1\tx_fifo_wrport_adr[3:0] attribute \src "ls180.v:868.5-868.26" wire $1\tx_old_trigger[0:0] attribute \src "ls180.v:865.5-865.22" wire $1\tx_pending[0:0] attribute \src "ls180.v:849.12-849.49" wire width 32 $1\uart_phy_phase_accumulator_rx[31:0] attribute \src "ls180.v:839.12-839.49" wire width 32 $1\uart_phy_phase_accumulator_tx[31:0] attribute \src "ls180.v:832.5-832.23" wire $1\uart_phy_re[0:0] attribute \src "ls180.v:853.11-853.38" wire width 4 $1\uart_phy_rx_bitcount[3:0] attribute \src "ls180.v:854.5-854.28" wire $1\uart_phy_rx_busy[0:0] attribute \src "ls180.v:851.5-851.25" wire $1\uart_phy_rx_r[0:0] attribute \src "ls180.v:852.11-852.33" wire width 8 $1\uart_phy_rx_reg[7:0] attribute \src "ls180.v:834.5-834.31" wire $1\uart_phy_sink_ready[0:0] attribute \src "ls180.v:847.11-847.46" wire width 8 $1\uart_phy_source_payload_data[7:0] attribute \src "ls180.v:843.5-843.33" wire $1\uart_phy_source_valid[0:0] attribute \src "ls180.v:831.12-831.42" wire width 32 $1\uart_phy_storage[31:0] attribute \src "ls180.v:841.11-841.38" wire width 4 $1\uart_phy_tx_bitcount[3:0] attribute \src "ls180.v:842.5-842.28" wire $1\uart_phy_tx_busy[0:0] attribute \src "ls180.v:840.11-840.33" wire width 8 $1\uart_phy_tx_reg[7:0] attribute \src "ls180.v:848.5-848.34" wire $1\uart_phy_uart_clk_rxen[0:0] attribute \src "ls180.v:838.5-838.34" wire $1\uart_phy_uart_clk_txen[0:0] attribute \src "ls180.v:809.5-809.24" wire $1\wb_sdram_ack[0:0] attribute \src "ls180.v:827.5-827.26" wire $1\wdata_consumed[0:0] attribute \src "ls180.v:1552.76-1552.113" wire $add$ls180.v:1552$25_Y attribute \src "ls180.v:1612.76-1612.113" wire $add$ls180.v:1612$36_Y attribute \src "ls180.v:1672.76-1672.113" wire $add$ls180.v:1672$47_Y attribute \src "ls180.v:2815.52-2815.76" wire $add$ls180.v:2815$553_Y attribute \src "ls180.v:2915.26-2915.59" wire width 5 $add$ls180.v:2915$599_Y attribute \src "ls180.v:2945.26-2945.59" wire width 5 $add$ls180.v:2945$610_Y attribute \src "ls180.v:4352.31-4352.60" wire width 32 $add$ls180.v:4352$1260_Y attribute \src "ls180.v:4441.32-4441.62" wire width 4 $add$ls180.v:4441$1284_Y attribute \src "ls180.v:4458.55-4458.109" wire width 3 $add$ls180.v:4458$1288_Y attribute \src "ls180.v:4461.55-4461.109" wire width 3 $add$ls180.v:4461$1289_Y attribute \src "ls180.v:4465.54-4465.106" wire width 4 $add$ls180.v:4465$1294_Y attribute \src "ls180.v:4504.55-4504.109" wire width 3 $add$ls180.v:4504$1304_Y attribute \src "ls180.v:4507.55-4507.109" wire width 3 $add$ls180.v:4507$1305_Y attribute \src "ls180.v:4511.54-4511.106" wire width 4 $add$ls180.v:4511$1310_Y attribute \src "ls180.v:4550.55-4550.109" wire width 3 $add$ls180.v:4550$1320_Y attribute \src "ls180.v:4553.55-4553.109" wire width 3 $add$ls180.v:4553$1321_Y attribute \src "ls180.v:4557.54-4557.106" wire width 4 $add$ls180.v:4557$1326_Y attribute \src "ls180.v:4596.55-4596.109" wire width 3 $add$ls180.v:4596$1336_Y attribute \src "ls180.v:4599.55-4599.109" wire width 3 $add$ls180.v:4599$1337_Y attribute \src "ls180.v:4603.54-4603.106" wire width 4 $add$ls180.v:4603$1342_Y attribute \src "ls180.v:4833.29-4833.56" wire width 4 $add$ls180.v:4833$1396_Y attribute \src "ls180.v:4849.63-4849.111" wire width 33 $add$ls180.v:4849$1399_Y attribute \src "ls180.v:4862.29-4862.56" wire width 4 $add$ls180.v:4862$1403_Y attribute \src "ls180.v:4881.63-4881.111" wire width 33 $add$ls180.v:4881$1406_Y attribute \src "ls180.v:4907.23-4907.45" wire width 4 $add$ls180.v:4907$1414_Y attribute \src "ls180.v:4910.23-4910.45" wire width 4 $add$ls180.v:4910$1415_Y attribute \src "ls180.v:4914.23-4914.44" wire width 5 $add$ls180.v:4914$1420_Y attribute \src "ls180.v:4929.23-4929.45" wire width 4 $add$ls180.v:4929$1425_Y attribute \src "ls180.v:4932.23-4932.45" wire width 4 $add$ls180.v:4932$1426_Y attribute \src "ls180.v:4936.23-4936.44" wire width 5 $add$ls180.v:4936$1431_Y attribute \src "ls180.v:1546.9-1546.70" wire $and$ls180.v:1546$20_Y attribute \src "ls180.v:1564.9-1564.70" wire $and$ls180.v:1564$27_Y attribute \src "ls180.v:1606.9-1606.70" wire $and$ls180.v:1606$31_Y attribute \src "ls180.v:1624.9-1624.70" wire $and$ls180.v:1624$38_Y attribute \src "ls180.v:1666.9-1666.76" wire $and$ls180.v:1666$42_Y attribute \src "ls180.v:1684.9-1684.76" wire $and$ls180.v:1684$49_Y attribute \src "ls180.v:1694.26-1694.75" wire $and$ls180.v:1694$51_Y attribute \src "ls180.v:1694.25-1694.101" wire $and$ls180.v:1694$52_Y attribute \src "ls180.v:1694.24-1694.131" wire $and$ls180.v:1694$53_Y attribute \src "ls180.v:1695.26-1695.75" wire $and$ls180.v:1695$54_Y attribute \src "ls180.v:1695.25-1695.101" wire $and$ls180.v:1695$55_Y attribute \src "ls180.v:1695.24-1695.131" wire $and$ls180.v:1695$56_Y attribute \src "ls180.v:1696.26-1696.75" wire $and$ls180.v:1696$57_Y attribute \src "ls180.v:1696.25-1696.101" wire $and$ls180.v:1696$58_Y attribute \src "ls180.v:1696.24-1696.131" wire $and$ls180.v:1696$59_Y attribute \src "ls180.v:1697.26-1697.75" wire $and$ls180.v:1697$60_Y attribute \src "ls180.v:1697.25-1697.101" wire $and$ls180.v:1697$61_Y attribute \src "ls180.v:1697.24-1697.131" wire $and$ls180.v:1697$62_Y attribute \src "ls180.v:1706.7-1706.79" wire $and$ls180.v:1706$65_Y attribute \src "ls180.v:1711.27-1711.96" wire $and$ls180.v:1711$66_Y attribute \src "ls180.v:1715.18-1715.59" wire $and$ls180.v:1715$68_Y attribute \src "ls180.v:1715.17-1715.81" wire $and$ls180.v:1715$69_Y attribute \src "ls180.v:1715.16-1715.107" wire $and$ls180.v:1715$70_Y attribute \src "ls180.v:1716.18-1716.59" wire $and$ls180.v:1716$71_Y attribute \src "ls180.v:1716.17-1716.81" wire $and$ls180.v:1716$72_Y attribute \src "ls180.v:1716.16-1716.107" wire $and$ls180.v:1716$73_Y attribute \src "ls180.v:1717.18-1717.59" wire $and$ls180.v:1717$74_Y attribute \src "ls180.v:1717.17-1717.81" wire $and$ls180.v:1717$75_Y attribute \src "ls180.v:1717.16-1717.107" wire $and$ls180.v:1717$76_Y attribute \src "ls180.v:1718.18-1718.59" wire $and$ls180.v:1718$77_Y attribute \src "ls180.v:1718.17-1718.81" wire $and$ls180.v:1718$78_Y attribute \src "ls180.v:1718.16-1718.107" wire $and$ls180.v:1718$79_Y attribute \src "ls180.v:1835.35-1835.84" wire $and$ls180.v:1835$86_Y attribute \src "ls180.v:1836.35-1836.84" wire $and$ls180.v:1836$87_Y attribute \src "ls180.v:1874.33-1874.88" wire $and$ls180.v:1874$93_Y attribute \src "ls180.v:1928.45-1928.104" wire $and$ls180.v:1928$101_Y attribute \src "ls180.v:1928.44-1928.147" wire $and$ls180.v:1928$102_Y attribute \src "ls180.v:1929.44-1929.103" wire $and$ls180.v:1929$103_Y attribute \src "ls180.v:1929.43-1929.134" wire $and$ls180.v:1929$104_Y attribute \src "ls180.v:1930.45-1930.104" wire $and$ls180.v:1930$105_Y attribute \src "ls180.v:1930.44-1930.135" wire $and$ls180.v:1930$106_Y attribute \src "ls180.v:1933.7-1933.104" wire $and$ls180.v:1933$108_Y attribute \src "ls180.v:1962.61-1962.226" wire $and$ls180.v:1962$114_Y attribute \src "ls180.v:1963.59-1963.172" wire $and$ls180.v:1963$115_Y attribute \src "ls180.v:1987.9-1987.76" wire $and$ls180.v:1987$121_Y attribute \src "ls180.v:1999.9-1999.76" wire $and$ls180.v:1999$122_Y attribute \src "ls180.v:2049.13-2049.77" wire $and$ls180.v:2049$124_Y attribute \src "ls180.v:2085.45-2085.104" wire $and$ls180.v:2085$131_Y attribute \src "ls180.v:2085.44-2085.147" wire $and$ls180.v:2085$132_Y attribute \src "ls180.v:2086.44-2086.103" wire $and$ls180.v:2086$133_Y attribute \src "ls180.v:2086.43-2086.134" wire $and$ls180.v:2086$134_Y attribute \src "ls180.v:2087.45-2087.104" wire $and$ls180.v:2087$135_Y attribute \src "ls180.v:2087.44-2087.135" wire $and$ls180.v:2087$136_Y attribute \src "ls180.v:2090.7-2090.104" wire $and$ls180.v:2090$138_Y attribute \src "ls180.v:2119.61-2119.226" wire $and$ls180.v:2119$144_Y attribute \src "ls180.v:2120.59-2120.172" wire $and$ls180.v:2120$145_Y attribute \src "ls180.v:2144.9-2144.76" wire $and$ls180.v:2144$151_Y attribute \src "ls180.v:2156.9-2156.76" wire $and$ls180.v:2156$152_Y attribute \src "ls180.v:2206.13-2206.77" wire $and$ls180.v:2206$154_Y attribute \src "ls180.v:2242.45-2242.104" wire $and$ls180.v:2242$161_Y attribute \src "ls180.v:2242.44-2242.147" wire $and$ls180.v:2242$162_Y attribute \src "ls180.v:2243.44-2243.103" wire $and$ls180.v:2243$163_Y attribute \src "ls180.v:2243.43-2243.134" wire $and$ls180.v:2243$164_Y attribute \src "ls180.v:2244.45-2244.104" wire $and$ls180.v:2244$165_Y attribute \src "ls180.v:2244.44-2244.135" wire $and$ls180.v:2244$166_Y attribute \src "ls180.v:2247.7-2247.104" wire $and$ls180.v:2247$168_Y attribute \src "ls180.v:2276.61-2276.226" wire $and$ls180.v:2276$174_Y attribute \src "ls180.v:2277.59-2277.172" wire $and$ls180.v:2277$175_Y attribute \src "ls180.v:2301.9-2301.76" wire $and$ls180.v:2301$181_Y attribute \src "ls180.v:2313.9-2313.76" wire $and$ls180.v:2313$182_Y attribute \src "ls180.v:2363.13-2363.77" wire $and$ls180.v:2363$184_Y attribute \src "ls180.v:2399.45-2399.104" wire $and$ls180.v:2399$191_Y attribute \src "ls180.v:2399.44-2399.147" wire $and$ls180.v:2399$192_Y attribute \src "ls180.v:2400.44-2400.103" wire $and$ls180.v:2400$193_Y attribute \src "ls180.v:2400.43-2400.134" wire $and$ls180.v:2400$194_Y attribute \src "ls180.v:2401.45-2401.104" wire $and$ls180.v:2401$195_Y attribute \src "ls180.v:2401.44-2401.135" wire $and$ls180.v:2401$196_Y attribute \src "ls180.v:2404.7-2404.104" wire $and$ls180.v:2404$198_Y attribute \src "ls180.v:2433.61-2433.226" wire $and$ls180.v:2433$204_Y attribute \src "ls180.v:2434.59-2434.172" wire $and$ls180.v:2434$205_Y attribute \src "ls180.v:2458.9-2458.76" wire $and$ls180.v:2458$211_Y attribute \src "ls180.v:2470.9-2470.76" wire $and$ls180.v:2470$212_Y attribute \src "ls180.v:2520.13-2520.77" wire $and$ls180.v:2520$214_Y attribute \src "ls180.v:2535.32-2535.87" wire $and$ls180.v:2535$215_Y attribute \src "ls180.v:2535.93-2535.163" wire $and$ls180.v:2535$217_Y attribute \src "ls180.v:2535.92-2535.201" wire $and$ls180.v:2535$219_Y attribute \src "ls180.v:2535.31-2535.202" wire $and$ls180.v:2535$220_Y attribute \src "ls180.v:2536.32-2536.87" wire $and$ls180.v:2536$221_Y attribute \src "ls180.v:2536.93-2536.163" wire $and$ls180.v:2536$223_Y attribute \src "ls180.v:2536.92-2536.201" wire $and$ls180.v:2536$225_Y attribute \src "ls180.v:2536.31-2536.202" wire $and$ls180.v:2536$226_Y attribute \src "ls180.v:2537.29-2537.70" wire $and$ls180.v:2537$227_Y attribute \src "ls180.v:2538.32-2538.87" wire $and$ls180.v:2538$228_Y attribute \src "ls180.v:2538.31-2538.169" wire $and$ls180.v:2538$230_Y attribute \src "ls180.v:2540.32-2540.87" wire $and$ls180.v:2540$231_Y attribute \src "ls180.v:2540.31-2540.128" wire $and$ls180.v:2540$232_Y attribute \src "ls180.v:2541.35-2541.104" wire $and$ls180.v:2541$233_Y attribute \src "ls180.v:2541.109-2541.178" wire $and$ls180.v:2541$234_Y attribute \src "ls180.v:2541.184-2541.253" wire $and$ls180.v:2541$236_Y attribute \src "ls180.v:2541.259-2541.328" wire $and$ls180.v:2541$238_Y attribute \src "ls180.v:2542.36-2542.106" wire $and$ls180.v:2542$240_Y attribute \src "ls180.v:2542.111-2542.181" wire $and$ls180.v:2542$241_Y attribute \src "ls180.v:2542.187-2542.257" wire $and$ls180.v:2542$243_Y attribute \src "ls180.v:2542.263-2542.333" wire $and$ls180.v:2542$245_Y attribute \src "ls180.v:2549.33-2549.96" wire $and$ls180.v:2549$249_Y attribute \src "ls180.v:2549.32-2549.130" wire $and$ls180.v:2549$250_Y attribute \src "ls180.v:2549.31-2549.164" wire $and$ls180.v:2549$251_Y attribute \src "ls180.v:2555.67-2555.133" wire $and$ls180.v:2555$254_Y attribute \src "ls180.v:2555.142-2555.216" wire $and$ls180.v:2555$256_Y attribute \src "ls180.v:2555.141-2555.256" wire $and$ls180.v:2555$258_Y attribute \src "ls180.v:2555.66-2555.293" wire $and$ls180.v:2555$261_Y attribute \src "ls180.v:2555.298-2555.445" wire $and$ls180.v:2555$264_Y attribute \src "ls180.v:2555.33-2555.447" wire $and$ls180.v:2555$266_Y attribute \src "ls180.v:2556.67-2556.133" wire $and$ls180.v:2556$267_Y attribute \src "ls180.v:2556.142-2556.216" wire $and$ls180.v:2556$269_Y attribute \src "ls180.v:2556.141-2556.256" wire $and$ls180.v:2556$271_Y attribute \src "ls180.v:2556.66-2556.293" wire $and$ls180.v:2556$274_Y attribute \src "ls180.v:2556.298-2556.445" wire $and$ls180.v:2556$277_Y attribute \src "ls180.v:2556.33-2556.447" wire $and$ls180.v:2556$279_Y attribute \src "ls180.v:2557.67-2557.133" wire $and$ls180.v:2557$280_Y attribute \src "ls180.v:2557.142-2557.216" wire $and$ls180.v:2557$282_Y attribute \src "ls180.v:2557.141-2557.256" wire $and$ls180.v:2557$284_Y attribute \src "ls180.v:2557.66-2557.293" wire $and$ls180.v:2557$287_Y attribute \src "ls180.v:2557.298-2557.445" wire $and$ls180.v:2557$290_Y attribute \src "ls180.v:2557.33-2557.447" wire $and$ls180.v:2557$292_Y attribute \src "ls180.v:2558.67-2558.133" wire $and$ls180.v:2558$293_Y attribute \src "ls180.v:2558.142-2558.216" wire $and$ls180.v:2558$295_Y attribute \src "ls180.v:2558.141-2558.256" wire $and$ls180.v:2558$297_Y attribute \src "ls180.v:2558.66-2558.293" wire $and$ls180.v:2558$300_Y attribute \src "ls180.v:2558.298-2558.445" wire $and$ls180.v:2558$303_Y attribute \src "ls180.v:2558.33-2558.447" wire $and$ls180.v:2558$305_Y attribute \src "ls180.v:2588.67-2588.133" wire $and$ls180.v:2588$312_Y attribute \src "ls180.v:2588.142-2588.216" wire $and$ls180.v:2588$314_Y attribute \src "ls180.v:2588.141-2588.256" wire $and$ls180.v:2588$316_Y attribute \src "ls180.v:2588.66-2588.293" wire $and$ls180.v:2588$319_Y attribute \src "ls180.v:2588.298-2588.445" wire $and$ls180.v:2588$322_Y attribute \src "ls180.v:2588.33-2588.447" wire $and$ls180.v:2588$324_Y attribute \src "ls180.v:2589.67-2589.133" wire $and$ls180.v:2589$325_Y attribute \src "ls180.v:2589.142-2589.216" wire $and$ls180.v:2589$327_Y attribute \src "ls180.v:2589.141-2589.256" wire $and$ls180.v:2589$329_Y attribute \src "ls180.v:2589.66-2589.293" wire $and$ls180.v:2589$332_Y attribute \src "ls180.v:2589.298-2589.445" wire $and$ls180.v:2589$335_Y attribute \src "ls180.v:2589.33-2589.447" wire $and$ls180.v:2589$337_Y attribute \src "ls180.v:2590.67-2590.133" wire $and$ls180.v:2590$338_Y attribute \src "ls180.v:2590.142-2590.216" wire $and$ls180.v:2590$340_Y attribute \src "ls180.v:2590.141-2590.256" wire $and$ls180.v:2590$342_Y attribute \src "ls180.v:2590.66-2590.293" wire $and$ls180.v:2590$345_Y attribute \src "ls180.v:2590.298-2590.445" wire $and$ls180.v:2590$348_Y attribute \src "ls180.v:2590.33-2590.447" wire $and$ls180.v:2590$350_Y attribute \src "ls180.v:2591.67-2591.133" wire $and$ls180.v:2591$351_Y attribute \src "ls180.v:2591.142-2591.216" wire $and$ls180.v:2591$353_Y attribute \src "ls180.v:2591.141-2591.256" wire $and$ls180.v:2591$355_Y attribute \src "ls180.v:2591.66-2591.293" wire $and$ls180.v:2591$358_Y attribute \src "ls180.v:2591.298-2591.445" wire $and$ls180.v:2591$361_Y attribute \src "ls180.v:2591.33-2591.447" wire $and$ls180.v:2591$363_Y attribute \src "ls180.v:2620.8-2620.63" wire $and$ls180.v:2620$368_Y attribute \src "ls180.v:2620.7-2620.99" wire $and$ls180.v:2620$370_Y attribute \src "ls180.v:2623.8-2623.63" wire $and$ls180.v:2623$371_Y attribute \src "ls180.v:2623.7-2623.99" wire $and$ls180.v:2623$373_Y attribute \src "ls180.v:2629.8-2629.63" wire $and$ls180.v:2629$375_Y attribute \src "ls180.v:2629.7-2629.99" wire $and$ls180.v:2629$377_Y attribute \src "ls180.v:2632.8-2632.63" wire $and$ls180.v:2632$378_Y attribute \src "ls180.v:2632.7-2632.99" wire $and$ls180.v:2632$380_Y attribute \src "ls180.v:2638.8-2638.63" wire $and$ls180.v:2638$382_Y attribute \src "ls180.v:2638.7-2638.99" wire $and$ls180.v:2638$384_Y attribute \src "ls180.v:2641.8-2641.63" wire $and$ls180.v:2641$385_Y attribute \src "ls180.v:2641.7-2641.99" wire $and$ls180.v:2641$387_Y attribute \src "ls180.v:2647.8-2647.63" wire $and$ls180.v:2647$389_Y attribute \src "ls180.v:2647.7-2647.99" wire $and$ls180.v:2647$391_Y attribute \src "ls180.v:2650.8-2650.63" wire $and$ls180.v:2650$392_Y attribute \src "ls180.v:2650.7-2650.99" wire $and$ls180.v:2650$394_Y attribute \src "ls180.v:2675.61-2675.131" wire $and$ls180.v:2675$399_Y attribute \src "ls180.v:2675.60-2675.169" wire $and$ls180.v:2675$401_Y attribute \src "ls180.v:2675.36-2675.192" wire $and$ls180.v:2675$404_Y attribute \src "ls180.v:2713.61-2713.131" wire $and$ls180.v:2713$408_Y attribute \src "ls180.v:2713.60-2713.169" wire $and$ls180.v:2713$410_Y attribute \src "ls180.v:2713.36-2713.192" wire $and$ls180.v:2713$413_Y attribute \src "ls180.v:2731.115-2731.184" wire $and$ls180.v:2731$418_Y attribute \src "ls180.v:2731.190-2731.259" wire $and$ls180.v:2731$421_Y attribute \src "ls180.v:2731.265-2731.334" wire $and$ls180.v:2731$424_Y attribute \src "ls180.v:2731.46-2731.337" wire $and$ls180.v:2731$427_Y attribute \src "ls180.v:2731.45-2731.355" wire $and$ls180.v:2731$428_Y attribute \src "ls180.v:2732.39-2732.101" wire $and$ls180.v:2732$431_Y attribute \src "ls180.v:2736.115-2736.184" wire $and$ls180.v:2736$434_Y attribute \src "ls180.v:2736.190-2736.259" wire $and$ls180.v:2736$437_Y attribute \src "ls180.v:2736.265-2736.334" wire $and$ls180.v:2736$440_Y attribute \src "ls180.v:2736.46-2736.337" wire $and$ls180.v:2736$443_Y attribute \src "ls180.v:2736.45-2736.355" wire $and$ls180.v:2736$444_Y attribute \src "ls180.v:2737.39-2737.101" wire $and$ls180.v:2737$447_Y attribute \src "ls180.v:2741.115-2741.184" wire $and$ls180.v:2741$450_Y attribute \src "ls180.v:2741.190-2741.259" wire $and$ls180.v:2741$453_Y attribute \src "ls180.v:2741.265-2741.334" wire $and$ls180.v:2741$456_Y attribute \src "ls180.v:2741.46-2741.337" wire $and$ls180.v:2741$459_Y attribute \src "ls180.v:2741.45-2741.355" wire $and$ls180.v:2741$460_Y attribute \src "ls180.v:2742.39-2742.101" wire $and$ls180.v:2742$463_Y attribute \src "ls180.v:2746.115-2746.184" wire $and$ls180.v:2746$466_Y attribute \src "ls180.v:2746.190-2746.259" wire $and$ls180.v:2746$469_Y attribute \src "ls180.v:2746.265-2746.334" wire $and$ls180.v:2746$472_Y attribute \src "ls180.v:2746.46-2746.337" wire $and$ls180.v:2746$475_Y attribute \src "ls180.v:2746.45-2746.355" wire $and$ls180.v:2746$476_Y attribute \src "ls180.v:2747.39-2747.101" wire $and$ls180.v:2747$479_Y attribute \src "ls180.v:2751.151-2751.220" wire $and$ls180.v:2751$483_Y attribute \src "ls180.v:2751.226-2751.295" wire $and$ls180.v:2751$486_Y attribute \src "ls180.v:2751.301-2751.370" wire $and$ls180.v:2751$489_Y attribute \src "ls180.v:2751.82-2751.373" wire $and$ls180.v:2751$492_Y attribute \src "ls180.v:2751.38-2751.374" wire $and$ls180.v:2751$493_Y attribute \src "ls180.v:2751.37-2751.405" wire $and$ls180.v:2751$494_Y attribute \src "ls180.v:2751.525-2751.594" wire $and$ls180.v:2751$499_Y attribute \src "ls180.v:2751.600-2751.669" wire $and$ls180.v:2751$502_Y attribute \src "ls180.v:2751.675-2751.744" wire $and$ls180.v:2751$505_Y attribute \src "ls180.v:2751.456-2751.747" wire $and$ls180.v:2751$508_Y attribute \src "ls180.v:2751.412-2751.748" wire $and$ls180.v:2751$509_Y attribute \src "ls180.v:2751.411-2751.779" wire $and$ls180.v:2751$510_Y attribute \src "ls180.v:2751.899-2751.968" wire $and$ls180.v:2751$515_Y attribute \src "ls180.v:2751.974-2751.1043" wire $and$ls180.v:2751$518_Y attribute \src "ls180.v:2751.1049-2751.1118" wire $and$ls180.v:2751$521_Y attribute \src "ls180.v:2751.830-2751.1121" wire $and$ls180.v:2751$524_Y attribute \src "ls180.v:2751.786-2751.1122" wire $and$ls180.v:2751$525_Y attribute \src "ls180.v:2751.785-2751.1153" wire $and$ls180.v:2751$526_Y attribute \src "ls180.v:2751.1273-2751.1342" wire $and$ls180.v:2751$531_Y attribute \src "ls180.v:2751.1348-2751.1417" wire $and$ls180.v:2751$534_Y attribute \src "ls180.v:2751.1423-2751.1492" wire $and$ls180.v:2751$537_Y attribute \src "ls180.v:2751.1204-2751.1495" wire $and$ls180.v:2751$540_Y attribute \src "ls180.v:2751.1160-2751.1496" wire $and$ls180.v:2751$541_Y attribute \src "ls180.v:2751.1159-2751.1527" wire $and$ls180.v:2751$542_Y attribute \src "ls180.v:2809.9-2809.36" wire $and$ls180.v:2809$548_Y attribute \src "ls180.v:2827.9-2827.36" wire $and$ls180.v:2827$555_Y attribute \src "ls180.v:2840.27-2840.60" wire $and$ls180.v:2840$559_Y attribute \src "ls180.v:2840.26-2840.79" wire $and$ls180.v:2840$561_Y attribute \src "ls180.v:2841.29-2841.82" wire $and$ls180.v:2841$563_Y attribute \src "ls180.v:2841.28-2841.103" wire $and$ls180.v:2841$565_Y attribute \src "ls180.v:2842.28-2842.84" wire $and$ls180.v:2842$568_Y attribute \src "ls180.v:2843.39-2843.65" wire $and$ls180.v:2843$569_Y attribute \src "ls180.v:2843.70-2843.99" wire $and$ls180.v:2843$571_Y attribute \src "ls180.v:2843.27-2843.101" wire $and$ls180.v:2843$573_Y attribute \src "ls180.v:2844.20-2844.51" wire $and$ls180.v:2844$574_Y attribute \src "ls180.v:2845.22-2845.57" wire $and$ls180.v:2845$576_Y attribute \src "ls180.v:2846.21-2846.56" wire $and$ls180.v:2846$578_Y attribute \src "ls180.v:2875.44-2875.58" wire $and$ls180.v:2875$584_Y attribute \src "ls180.v:2879.7-2879.58" wire $and$ls180.v:2879$588_Y attribute \src "ls180.v:2890.7-2890.58" wire $and$ls180.v:2890$591_Y attribute \src "ls180.v:2899.16-2899.67" wire $and$ls180.v:2899$593_Y attribute \src "ls180.v:2899.72-2899.123" wire $and$ls180.v:2899$594_Y attribute \src "ls180.v:2914.31-2914.93" wire $and$ls180.v:2914$598_Y attribute \src "ls180.v:2925.29-2925.96" wire $and$ls180.v:2925$603_Y attribute \src "ls180.v:2926.27-2926.74" wire $and$ls180.v:2926$604_Y attribute \src "ls180.v:2944.31-2944.93" wire $and$ls180.v:2944$609_Y attribute \src "ls180.v:2955.29-2955.96" wire $and$ls180.v:2955$614_Y attribute \src "ls180.v:2956.27-2956.74" wire $and$ls180.v:2956$615_Y attribute \src "ls180.v:3053.9-3053.84" wire $and$ls180.v:3053$623_Y attribute \src "ls180.v:3056.60-3056.144" wire $and$ls180.v:3056$625_Y attribute \src "ls180.v:3074.58-3074.110" wire $and$ls180.v:3074$627_Y attribute \src "ls180.v:3075.58-3075.110" wire $and$ls180.v:3075$629_Y attribute \src "ls180.v:3076.58-3076.110" wire $and$ls180.v:3076$631_Y attribute \src "ls180.v:3077.58-3077.110" wire $and$ls180.v:3077$633_Y attribute \src "ls180.v:3078.58-3078.110" wire $and$ls180.v:3078$635_Y attribute \src "ls180.v:3079.58-3079.110" wire $and$ls180.v:3079$637_Y attribute \src "ls180.v:3132.35-3132.84" wire $and$ls180.v:3132$645_Y attribute \src "ls180.v:3133.31-3133.80" wire $and$ls180.v:3133$646_Y attribute \src "ls180.v:3134.45-3134.94" wire $and$ls180.v:3134$647_Y attribute \src "ls180.v:3135.45-3135.94" wire $and$ls180.v:3135$648_Y attribute \src "ls180.v:3136.24-3136.73" wire $and$ls180.v:3136$649_Y attribute \src "ls180.v:3137.48-3137.97" wire $and$ls180.v:3137$650_Y attribute \src "ls180.v:3139.29-3139.76" wire $and$ls180.v:3139$656_Y attribute \src "ls180.v:3139.28-3139.105" wire $and$ls180.v:3139$658_Y attribute \src "ls180.v:3145.36-3145.96" wire width 32 $and$ls180.v:3145$665_Y attribute \src "ls180.v:3145.101-3145.157" wire width 32 $and$ls180.v:3145$666_Y attribute \src "ls180.v:3145.163-3145.233" wire width 32 $and$ls180.v:3145$668_Y attribute \src "ls180.v:3145.239-3145.309" wire width 32 $and$ls180.v:3145$670_Y attribute \src "ls180.v:3145.315-3145.364" wire width 32 $and$ls180.v:3145$672_Y attribute \src "ls180.v:3145.370-3145.443" wire width 32 $and$ls180.v:3145$674_Y attribute \src "ls180.v:3155.43-3155.104" wire $and$ls180.v:3155$678_Y attribute \src "ls180.v:3155.42-3155.158" wire $and$ls180.v:3155$680_Y attribute \src "ls180.v:3156.43-3156.107" wire $and$ls180.v:3156$682_Y attribute \src "ls180.v:3156.42-3156.161" wire $and$ls180.v:3156$684_Y attribute \src "ls180.v:3158.45-3158.106" wire $and$ls180.v:3158$685_Y attribute \src "ls180.v:3158.44-3158.160" wire $and$ls180.v:3158$687_Y attribute \src "ls180.v:3159.45-3159.109" wire $and$ls180.v:3159$689_Y attribute \src "ls180.v:3159.44-3159.163" wire $and$ls180.v:3159$691_Y attribute \src "ls180.v:3161.45-3161.106" wire $and$ls180.v:3161$692_Y attribute \src "ls180.v:3161.44-3161.160" wire $and$ls180.v:3161$694_Y attribute \src "ls180.v:3162.45-3162.109" wire $and$ls180.v:3162$696_Y attribute \src "ls180.v:3162.44-3162.163" wire $and$ls180.v:3162$698_Y attribute \src "ls180.v:3164.45-3164.106" wire $and$ls180.v:3164$699_Y attribute \src "ls180.v:3164.44-3164.160" wire $and$ls180.v:3164$701_Y attribute \src "ls180.v:3165.45-3165.109" wire $and$ls180.v:3165$703_Y attribute \src "ls180.v:3165.44-3165.163" wire $and$ls180.v:3165$705_Y attribute \src "ls180.v:3167.45-3167.106" wire $and$ls180.v:3167$706_Y attribute \src "ls180.v:3167.44-3167.160" wire $and$ls180.v:3167$708_Y attribute \src "ls180.v:3168.45-3168.109" wire $and$ls180.v:3168$710_Y attribute \src "ls180.v:3168.44-3168.163" wire $and$ls180.v:3168$712_Y attribute \src "ls180.v:3170.48-3170.109" wire $and$ls180.v:3170$713_Y attribute \src "ls180.v:3170.47-3170.163" wire $and$ls180.v:3170$715_Y attribute \src "ls180.v:3171.48-3171.112" wire $and$ls180.v:3171$717_Y attribute \src "ls180.v:3171.47-3171.166" wire $and$ls180.v:3171$719_Y attribute \src "ls180.v:3173.48-3173.109" wire $and$ls180.v:3173$720_Y attribute \src "ls180.v:3173.47-3173.163" wire $and$ls180.v:3173$722_Y attribute \src "ls180.v:3174.48-3174.112" wire $and$ls180.v:3174$724_Y attribute \src "ls180.v:3174.47-3174.166" wire $and$ls180.v:3174$726_Y attribute \src "ls180.v:3176.48-3176.109" wire $and$ls180.v:3176$727_Y attribute \src "ls180.v:3176.47-3176.163" wire $and$ls180.v:3176$729_Y attribute \src "ls180.v:3177.48-3177.112" wire $and$ls180.v:3177$731_Y attribute \src "ls180.v:3177.47-3177.166" wire $and$ls180.v:3177$733_Y attribute \src "ls180.v:3179.48-3179.109" wire $and$ls180.v:3179$734_Y attribute \src "ls180.v:3179.47-3179.163" wire $and$ls180.v:3179$736_Y attribute \src "ls180.v:3180.48-3180.112" wire $and$ls180.v:3180$738_Y attribute \src "ls180.v:3180.47-3180.166" wire $and$ls180.v:3180$740_Y attribute \src "ls180.v:3193.40-3193.101" wire $and$ls180.v:3193$742_Y attribute \src "ls180.v:3193.39-3193.155" wire $and$ls180.v:3193$744_Y attribute \src "ls180.v:3194.40-3194.104" wire $and$ls180.v:3194$746_Y attribute \src "ls180.v:3194.39-3194.158" wire $and$ls180.v:3194$748_Y attribute \src "ls180.v:3196.39-3196.100" wire $and$ls180.v:3196$749_Y attribute \src "ls180.v:3196.38-3196.154" wire $and$ls180.v:3196$751_Y attribute \src "ls180.v:3197.39-3197.103" wire $and$ls180.v:3197$753_Y attribute \src "ls180.v:3197.38-3197.157" wire $and$ls180.v:3197$755_Y attribute \src "ls180.v:3199.41-3199.102" wire $and$ls180.v:3199$756_Y attribute \src "ls180.v:3199.40-3199.156" wire $and$ls180.v:3199$758_Y attribute \src "ls180.v:3200.41-3200.105" wire $and$ls180.v:3200$760_Y attribute \src "ls180.v:3200.40-3200.159" wire $and$ls180.v:3200$762_Y attribute \src "ls180.v:3207.40-3207.101" wire $and$ls180.v:3207$764_Y attribute \src "ls180.v:3207.39-3207.155" wire $and$ls180.v:3207$766_Y attribute \src "ls180.v:3208.40-3208.104" wire $and$ls180.v:3208$768_Y attribute \src "ls180.v:3208.39-3208.158" wire $and$ls180.v:3208$770_Y attribute \src "ls180.v:3210.39-3210.100" wire $and$ls180.v:3210$771_Y attribute \src "ls180.v:3210.38-3210.154" wire $and$ls180.v:3210$773_Y attribute \src "ls180.v:3211.39-3211.103" wire $and$ls180.v:3211$775_Y attribute \src "ls180.v:3211.38-3211.157" wire $and$ls180.v:3211$777_Y attribute \src "ls180.v:3213.41-3213.102" wire $and$ls180.v:3213$778_Y attribute \src "ls180.v:3213.40-3213.156" wire $and$ls180.v:3213$780_Y attribute \src "ls180.v:3214.41-3214.105" wire $and$ls180.v:3214$782_Y attribute \src "ls180.v:3214.40-3214.159" wire $and$ls180.v:3214$784_Y attribute \src "ls180.v:3221.39-3221.100" wire $and$ls180.v:3221$786_Y attribute \src "ls180.v:3221.38-3221.152" wire $and$ls180.v:3221$788_Y attribute \src "ls180.v:3222.39-3222.103" wire $and$ls180.v:3222$790_Y attribute \src "ls180.v:3222.38-3222.155" wire $and$ls180.v:3222$792_Y attribute \src "ls180.v:3224.38-3224.99" wire $and$ls180.v:3224$793_Y attribute \src "ls180.v:3224.37-3224.151" wire $and$ls180.v:3224$795_Y attribute \src "ls180.v:3225.38-3225.102" wire $and$ls180.v:3225$797_Y attribute \src "ls180.v:3225.37-3225.154" wire $and$ls180.v:3225$799_Y attribute \src "ls180.v:3235.50-3235.111" wire $and$ls180.v:3235$801_Y attribute \src "ls180.v:3235.49-3235.165" wire $and$ls180.v:3235$803_Y attribute \src "ls180.v:3236.50-3236.114" wire $and$ls180.v:3236$805_Y attribute \src "ls180.v:3236.49-3236.168" wire $and$ls180.v:3236$807_Y attribute \src "ls180.v:3238.54-3238.115" wire $and$ls180.v:3238$808_Y attribute \src "ls180.v:3238.53-3238.169" wire $and$ls180.v:3238$810_Y attribute \src "ls180.v:3239.54-3239.118" wire $and$ls180.v:3239$812_Y attribute \src "ls180.v:3239.53-3239.172" wire $and$ls180.v:3239$814_Y attribute \src "ls180.v:3241.35-3241.96" wire $and$ls180.v:3241$815_Y attribute \src "ls180.v:3241.34-3241.150" wire $and$ls180.v:3241$817_Y attribute \src "ls180.v:3242.35-3242.99" wire $and$ls180.v:3242$819_Y attribute \src "ls180.v:3242.34-3242.153" wire $and$ls180.v:3242$821_Y attribute \src "ls180.v:3244.54-3244.115" wire $and$ls180.v:3244$822_Y attribute \src "ls180.v:3244.53-3244.169" wire $and$ls180.v:3244$824_Y attribute \src "ls180.v:3245.54-3245.118" wire $and$ls180.v:3245$826_Y attribute \src "ls180.v:3245.53-3245.172" wire $and$ls180.v:3245$828_Y attribute \src "ls180.v:3247.54-3247.115" wire $and$ls180.v:3247$829_Y attribute \src "ls180.v:3247.53-3247.169" wire $and$ls180.v:3247$831_Y attribute \src "ls180.v:3248.54-3248.118" wire $and$ls180.v:3248$833_Y attribute \src "ls180.v:3248.53-3248.172" wire $and$ls180.v:3248$835_Y attribute \src "ls180.v:3250.55-3250.116" wire $and$ls180.v:3250$836_Y attribute \src "ls180.v:3250.54-3250.170" wire $and$ls180.v:3250$838_Y attribute \src "ls180.v:3251.55-3251.119" wire $and$ls180.v:3251$840_Y attribute \src "ls180.v:3251.54-3251.173" wire $and$ls180.v:3251$842_Y attribute \src "ls180.v:3253.53-3253.114" wire $and$ls180.v:3253$843_Y attribute \src "ls180.v:3253.52-3253.168" wire $and$ls180.v:3253$845_Y attribute \src "ls180.v:3254.53-3254.117" wire $and$ls180.v:3254$847_Y attribute \src "ls180.v:3254.52-3254.171" wire $and$ls180.v:3254$849_Y attribute \src "ls180.v:3256.53-3256.114" wire $and$ls180.v:3256$850_Y attribute \src "ls180.v:3256.52-3256.168" wire $and$ls180.v:3256$852_Y attribute \src "ls180.v:3257.53-3257.117" wire $and$ls180.v:3257$854_Y attribute \src "ls180.v:3257.52-3257.171" wire $and$ls180.v:3257$856_Y attribute \src "ls180.v:3259.53-3259.114" wire $and$ls180.v:3259$857_Y attribute \src "ls180.v:3259.52-3259.168" wire $and$ls180.v:3259$859_Y attribute \src "ls180.v:3260.53-3260.117" wire $and$ls180.v:3260$861_Y attribute \src "ls180.v:3260.52-3260.171" wire $and$ls180.v:3260$863_Y attribute \src "ls180.v:3262.53-3262.114" wire $and$ls180.v:3262$864_Y attribute \src "ls180.v:3262.52-3262.168" wire $and$ls180.v:3262$866_Y attribute \src "ls180.v:3263.53-3263.117" wire $and$ls180.v:3263$868_Y attribute \src "ls180.v:3263.52-3263.171" wire $and$ls180.v:3263$870_Y attribute \src "ls180.v:3280.42-3280.103" wire $and$ls180.v:3280$872_Y attribute \src "ls180.v:3280.41-3280.157" wire $and$ls180.v:3280$874_Y attribute \src "ls180.v:3281.42-3281.106" wire $and$ls180.v:3281$876_Y attribute \src "ls180.v:3281.41-3281.160" wire $and$ls180.v:3281$878_Y attribute \src "ls180.v:3283.42-3283.103" wire $and$ls180.v:3283$879_Y attribute \src "ls180.v:3283.41-3283.157" wire $and$ls180.v:3283$881_Y attribute \src "ls180.v:3284.42-3284.106" wire $and$ls180.v:3284$883_Y attribute \src "ls180.v:3284.41-3284.160" wire $and$ls180.v:3284$885_Y attribute \src "ls180.v:3286.42-3286.103" wire $and$ls180.v:3286$886_Y attribute \src "ls180.v:3286.41-3286.157" wire $and$ls180.v:3286$888_Y attribute \src "ls180.v:3287.42-3287.106" wire $and$ls180.v:3287$890_Y attribute \src "ls180.v:3287.41-3287.160" wire $and$ls180.v:3287$892_Y attribute \src "ls180.v:3289.42-3289.103" wire $and$ls180.v:3289$893_Y attribute \src "ls180.v:3289.41-3289.157" wire $and$ls180.v:3289$895_Y attribute \src "ls180.v:3290.42-3290.106" wire $and$ls180.v:3290$897_Y attribute \src "ls180.v:3290.41-3290.160" wire $and$ls180.v:3290$899_Y attribute \src "ls180.v:3292.44-3292.105" wire $and$ls180.v:3292$900_Y attribute \src "ls180.v:3292.43-3292.159" wire $and$ls180.v:3292$902_Y attribute \src "ls180.v:3293.44-3293.108" wire $and$ls180.v:3293$904_Y attribute \src "ls180.v:3293.43-3293.162" wire $and$ls180.v:3293$906_Y attribute \src "ls180.v:3295.44-3295.105" wire $and$ls180.v:3295$907_Y attribute \src "ls180.v:3295.43-3295.159" wire $and$ls180.v:3295$909_Y attribute \src "ls180.v:3296.44-3296.108" wire $and$ls180.v:3296$911_Y attribute \src "ls180.v:3296.43-3296.162" wire $and$ls180.v:3296$913_Y attribute \src "ls180.v:3298.44-3298.105" wire $and$ls180.v:3298$914_Y attribute \src "ls180.v:3298.43-3298.159" wire $and$ls180.v:3298$916_Y attribute \src "ls180.v:3299.44-3299.108" wire $and$ls180.v:3299$918_Y attribute \src "ls180.v:3299.43-3299.162" wire $and$ls180.v:3299$920_Y attribute \src "ls180.v:3301.44-3301.105" wire $and$ls180.v:3301$921_Y attribute \src "ls180.v:3301.43-3301.159" wire $and$ls180.v:3301$923_Y attribute \src "ls180.v:3302.44-3302.108" wire $and$ls180.v:3302$925_Y attribute \src "ls180.v:3302.43-3302.162" wire $and$ls180.v:3302$927_Y attribute \src "ls180.v:3304.40-3304.101" wire $and$ls180.v:3304$928_Y attribute \src "ls180.v:3304.39-3304.155" wire $and$ls180.v:3304$930_Y attribute \src "ls180.v:3305.40-3305.104" wire $and$ls180.v:3305$932_Y attribute \src "ls180.v:3305.39-3305.158" wire $and$ls180.v:3305$934_Y attribute \src "ls180.v:3307.50-3307.111" wire $and$ls180.v:3307$935_Y attribute \src "ls180.v:3307.49-3307.165" wire $and$ls180.v:3307$937_Y attribute \src "ls180.v:3308.50-3308.114" wire $and$ls180.v:3308$939_Y attribute \src "ls180.v:3308.49-3308.168" wire $and$ls180.v:3308$941_Y attribute \src "ls180.v:3310.43-3310.104" wire $and$ls180.v:3310$942_Y attribute \src "ls180.v:3310.42-3310.159" wire $and$ls180.v:3310$944_Y attribute \src "ls180.v:3311.43-3311.107" wire $and$ls180.v:3311$946_Y attribute \src "ls180.v:3311.42-3311.162" wire $and$ls180.v:3311$948_Y attribute \src "ls180.v:3313.43-3313.104" wire $and$ls180.v:3313$949_Y attribute \src "ls180.v:3313.42-3313.159" wire $and$ls180.v:3313$951_Y attribute \src "ls180.v:3314.43-3314.107" wire $and$ls180.v:3314$953_Y attribute \src "ls180.v:3314.42-3314.162" wire $and$ls180.v:3314$955_Y attribute \src "ls180.v:3316.43-3316.104" wire $and$ls180.v:3316$956_Y attribute \src "ls180.v:3316.42-3316.159" wire $and$ls180.v:3316$958_Y attribute \src "ls180.v:3317.43-3317.107" wire $and$ls180.v:3317$960_Y attribute \src "ls180.v:3317.42-3317.162" wire $and$ls180.v:3317$962_Y attribute \src "ls180.v:3319.43-3319.104" wire $and$ls180.v:3319$963_Y attribute \src "ls180.v:3319.42-3319.159" wire $and$ls180.v:3319$965_Y attribute \src "ls180.v:3320.43-3320.107" wire $and$ls180.v:3320$967_Y attribute \src "ls180.v:3320.42-3320.162" wire $and$ls180.v:3320$969_Y attribute \src "ls180.v:3322.47-3322.108" wire $and$ls180.v:3322$970_Y attribute \src "ls180.v:3322.46-3322.163" wire $and$ls180.v:3322$972_Y attribute \src "ls180.v:3323.47-3323.111" wire $and$ls180.v:3323$974_Y attribute \src "ls180.v:3323.46-3323.166" wire $and$ls180.v:3323$976_Y attribute \src "ls180.v:3325.48-3325.109" wire $and$ls180.v:3325$977_Y attribute \src "ls180.v:3325.47-3325.164" wire $and$ls180.v:3325$979_Y attribute \src "ls180.v:3326.48-3326.112" wire $and$ls180.v:3326$981_Y attribute \src "ls180.v:3326.47-3326.167" wire $and$ls180.v:3326$983_Y attribute \src "ls180.v:3328.47-3328.108" wire $and$ls180.v:3328$984_Y attribute \src "ls180.v:3328.46-3328.163" wire $and$ls180.v:3328$986_Y attribute \src "ls180.v:3329.47-3329.111" wire $and$ls180.v:3329$988_Y attribute \src "ls180.v:3329.46-3329.166" wire $and$ls180.v:3329$990_Y attribute \src "ls180.v:3348.20-3348.81" wire $and$ls180.v:3348$992_Y attribute \src "ls180.v:3348.19-3348.135" wire $and$ls180.v:3348$994_Y attribute \src "ls180.v:3349.20-3349.84" wire $and$ls180.v:3349$996_Y attribute \src "ls180.v:3349.19-3349.138" wire $and$ls180.v:3349$998_Y attribute \src "ls180.v:3351.42-3351.158" wire $and$ls180.v:3351$1001_Y attribute \src "ls180.v:3351.43-3351.104" wire $and$ls180.v:3351$999_Y attribute \src "ls180.v:3352.43-3352.107" wire $and$ls180.v:3352$1003_Y attribute \src "ls180.v:3352.42-3352.161" wire $and$ls180.v:3352$1005_Y attribute \src "ls180.v:3354.44-3354.105" wire $and$ls180.v:3354$1006_Y attribute \src "ls180.v:3354.43-3354.159" wire $and$ls180.v:3354$1008_Y attribute \src "ls180.v:3355.44-3355.108" wire $and$ls180.v:3355$1010_Y attribute \src "ls180.v:3355.43-3355.162" wire $and$ls180.v:3355$1012_Y attribute \src "ls180.v:3357.35-3357.96" wire $and$ls180.v:3357$1013_Y attribute \src "ls180.v:3357.34-3357.150" wire $and$ls180.v:3357$1015_Y attribute \src "ls180.v:3358.35-3358.99" wire $and$ls180.v:3358$1017_Y attribute \src "ls180.v:3358.34-3358.153" wire $and$ls180.v:3358$1019_Y attribute \src "ls180.v:3360.36-3360.97" wire $and$ls180.v:3360$1020_Y attribute \src "ls180.v:3360.35-3360.151" wire $and$ls180.v:3360$1022_Y attribute \src "ls180.v:3361.36-3361.100" wire $and$ls180.v:3361$1024_Y attribute \src "ls180.v:3361.35-3361.154" wire $and$ls180.v:3361$1026_Y attribute \src "ls180.v:3363.47-3363.108" wire $and$ls180.v:3363$1027_Y attribute \src "ls180.v:3363.46-3363.162" wire $and$ls180.v:3363$1029_Y attribute \src "ls180.v:3364.47-3364.111" wire $and$ls180.v:3364$1031_Y attribute \src "ls180.v:3364.46-3364.165" wire $and$ls180.v:3364$1033_Y attribute \src "ls180.v:3366.44-3366.105" wire $and$ls180.v:3366$1034_Y attribute \src "ls180.v:3366.43-3366.159" wire $and$ls180.v:3366$1036_Y attribute \src "ls180.v:3367.44-3367.108" wire $and$ls180.v:3367$1038_Y attribute \src "ls180.v:3367.43-3367.162" wire $and$ls180.v:3367$1040_Y attribute \src "ls180.v:3369.43-3369.104" wire $and$ls180.v:3369$1041_Y attribute \src "ls180.v:3369.42-3369.158" wire $and$ls180.v:3369$1043_Y attribute \src "ls180.v:3370.43-3370.107" wire $and$ls180.v:3370$1045_Y attribute \src "ls180.v:3370.42-3370.161" wire $and$ls180.v:3370$1047_Y attribute \src "ls180.v:3382.49-3382.110" wire $and$ls180.v:3382$1049_Y attribute \src "ls180.v:3382.48-3382.164" wire $and$ls180.v:3382$1051_Y attribute \src "ls180.v:3383.49-3383.113" wire $and$ls180.v:3383$1053_Y attribute \src "ls180.v:3383.48-3383.167" wire $and$ls180.v:3383$1055_Y attribute \src "ls180.v:3385.49-3385.110" wire $and$ls180.v:3385$1056_Y attribute \src "ls180.v:3385.48-3385.164" wire $and$ls180.v:3385$1058_Y attribute \src "ls180.v:3386.49-3386.113" wire $and$ls180.v:3386$1060_Y attribute \src "ls180.v:3386.48-3386.167" wire $and$ls180.v:3386$1062_Y attribute \src "ls180.v:3388.49-3388.110" wire $and$ls180.v:3388$1063_Y attribute \src "ls180.v:3388.48-3388.164" wire $and$ls180.v:3388$1065_Y attribute \src "ls180.v:3389.49-3389.113" wire $and$ls180.v:3389$1067_Y attribute \src "ls180.v:3389.48-3389.167" wire $and$ls180.v:3389$1069_Y attribute \src "ls180.v:3391.49-3391.110" wire $and$ls180.v:3391$1070_Y attribute \src "ls180.v:3391.48-3391.164" wire $and$ls180.v:3391$1072_Y attribute \src "ls180.v:3392.49-3392.113" wire $and$ls180.v:3392$1074_Y attribute \src "ls180.v:3392.48-3392.167" wire $and$ls180.v:3392$1076_Y attribute \src "ls180.v:3752.96-3752.165" wire $and$ls180.v:3752$1107_Y attribute \src "ls180.v:3752.171-3752.240" wire $and$ls180.v:3752$1110_Y attribute \src "ls180.v:3752.246-3752.315" wire $and$ls180.v:3752$1113_Y attribute \src "ls180.v:3752.27-3752.318" wire $and$ls180.v:3752$1116_Y attribute \src "ls180.v:3752.26-3752.336" wire $and$ls180.v:3752$1117_Y attribute \src "ls180.v:3776.96-3776.165" wire $and$ls180.v:3776$1123_Y attribute \src "ls180.v:3776.171-3776.240" wire $and$ls180.v:3776$1126_Y attribute \src "ls180.v:3776.246-3776.315" wire $and$ls180.v:3776$1129_Y attribute \src "ls180.v:3776.27-3776.318" wire $and$ls180.v:3776$1132_Y attribute \src "ls180.v:3776.26-3776.336" wire $and$ls180.v:3776$1133_Y attribute \src "ls180.v:3800.96-3800.165" wire $and$ls180.v:3800$1139_Y attribute \src "ls180.v:3800.171-3800.240" wire $and$ls180.v:3800$1142_Y attribute \src "ls180.v:3800.246-3800.315" wire $and$ls180.v:3800$1145_Y attribute \src "ls180.v:3800.27-3800.318" wire $and$ls180.v:3800$1148_Y attribute \src "ls180.v:3800.26-3800.336" wire $and$ls180.v:3800$1149_Y attribute \src "ls180.v:3824.96-3824.165" wire $and$ls180.v:3824$1155_Y attribute \src "ls180.v:3824.171-3824.240" wire $and$ls180.v:3824$1158_Y attribute \src "ls180.v:3824.246-3824.315" wire $and$ls180.v:3824$1161_Y attribute \src "ls180.v:3824.27-3824.318" wire $and$ls180.v:3824$1164_Y attribute \src "ls180.v:3824.26-3824.336" wire $and$ls180.v:3824$1165_Y attribute \src "ls180.v:3981.22-3981.77" wire $and$ls180.v:3981$1177_Y attribute \src "ls180.v:3981.21-3981.113" wire $and$ls180.v:3981$1178_Y attribute \src "ls180.v:3984.22-3984.77" wire $and$ls180.v:3984$1179_Y attribute \src "ls180.v:3984.21-3984.113" wire $and$ls180.v:3984$1180_Y attribute \src "ls180.v:3987.22-3987.55" wire $and$ls180.v:3987$1181_Y attribute \src "ls180.v:3987.21-3987.80" wire $and$ls180.v:3987$1182_Y attribute \src "ls180.v:3998.22-3998.77" wire $and$ls180.v:3998$1184_Y attribute \src "ls180.v:3998.21-3998.113" wire $and$ls180.v:3998$1185_Y attribute \src "ls180.v:4001.22-4001.77" wire $and$ls180.v:4001$1186_Y attribute \src "ls180.v:4001.21-4001.113" wire $and$ls180.v:4001$1187_Y attribute \src "ls180.v:4004.22-4004.55" wire $and$ls180.v:4004$1188_Y attribute \src "ls180.v:4004.21-4004.80" wire $and$ls180.v:4004$1189_Y attribute \src "ls180.v:4015.22-4015.77" wire $and$ls180.v:4015$1191_Y attribute \src "ls180.v:4015.21-4015.112" wire $and$ls180.v:4015$1192_Y attribute \src "ls180.v:4018.22-4018.77" wire $and$ls180.v:4018$1193_Y attribute \src "ls180.v:4018.21-4018.112" wire $and$ls180.v:4018$1194_Y attribute \src "ls180.v:4021.22-4021.55" wire $and$ls180.v:4021$1195_Y attribute \src "ls180.v:4021.21-4021.79" wire $and$ls180.v:4021$1196_Y attribute \src "ls180.v:4032.22-4032.77" wire $and$ls180.v:4032$1198_Y attribute \src "ls180.v:4032.21-4032.117" wire $and$ls180.v:4032$1199_Y attribute \src "ls180.v:4035.22-4035.77" wire $and$ls180.v:4035$1200_Y attribute \src "ls180.v:4035.21-4035.117" wire $and$ls180.v:4035$1201_Y attribute \src "ls180.v:4038.22-4038.55" wire $and$ls180.v:4038$1202_Y attribute \src "ls180.v:4038.21-4038.84" wire $and$ls180.v:4038$1203_Y attribute \src "ls180.v:4049.22-4049.77" wire $and$ls180.v:4049$1205_Y attribute \src "ls180.v:4049.21-4049.118" wire $and$ls180.v:4049$1206_Y attribute \src "ls180.v:4052.22-4052.77" wire $and$ls180.v:4052$1207_Y attribute \src "ls180.v:4052.21-4052.118" wire $and$ls180.v:4052$1208_Y attribute \src "ls180.v:4055.22-4055.55" wire $and$ls180.v:4055$1209_Y attribute \src "ls180.v:4055.21-4055.85" wire $and$ls180.v:4055$1210_Y attribute \src "ls180.v:4223.57-4223.97" wire $and$ls180.v:4223$1213_Y attribute \src "ls180.v:4224.57-4224.97" wire $and$ls180.v:4224$1214_Y attribute \src "ls180.v:4356.8-4356.57" wire $and$ls180.v:4356$1261_Y attribute \src "ls180.v:4356.7-4356.87" wire $and$ls180.v:4356$1263_Y attribute \src "ls180.v:4375.7-4375.65" wire $and$ls180.v:4375$1267_Y attribute \src "ls180.v:4379.8-4379.49" wire $and$ls180.v:4379$1268_Y attribute \src "ls180.v:4379.7-4379.75" wire $and$ls180.v:4379$1270_Y attribute \src "ls180.v:4387.7-4387.46" wire $and$ls180.v:4387$1272_Y attribute \src "ls180.v:4415.7-4415.65" wire $and$ls180.v:4415$1279_Y attribute \src "ls180.v:4457.8-4457.121" wire $and$ls180.v:4457$1285_Y attribute \src "ls180.v:4457.7-4457.175" wire $and$ls180.v:4457$1287_Y attribute \src "ls180.v:4463.8-4463.121" wire $and$ls180.v:4463$1290_Y attribute \src "ls180.v:4463.7-4463.175" wire $and$ls180.v:4463$1292_Y attribute \src "ls180.v:4503.8-4503.121" wire $and$ls180.v:4503$1301_Y attribute \src "ls180.v:4503.7-4503.175" wire $and$ls180.v:4503$1303_Y attribute \src "ls180.v:4509.8-4509.121" wire $and$ls180.v:4509$1306_Y attribute \src "ls180.v:4509.7-4509.175" wire $and$ls180.v:4509$1308_Y attribute \src "ls180.v:4549.8-4549.121" wire $and$ls180.v:4549$1317_Y attribute \src "ls180.v:4549.7-4549.175" wire $and$ls180.v:4549$1319_Y attribute \src "ls180.v:4555.8-4555.121" wire $and$ls180.v:4555$1322_Y attribute \src "ls180.v:4555.7-4555.175" wire $and$ls180.v:4555$1324_Y attribute \src "ls180.v:4595.8-4595.121" wire $and$ls180.v:4595$1333_Y attribute \src "ls180.v:4595.7-4595.175" wire $and$ls180.v:4595$1335_Y attribute \src "ls180.v:4601.8-4601.121" wire $and$ls180.v:4601$1338_Y attribute \src "ls180.v:4601.7-4601.175" wire $and$ls180.v:4601$1340_Y attribute \src "ls180.v:4798.53-4798.129" wire $and$ls180.v:4798$1365_Y attribute \src "ls180.v:4798.135-4798.211" wire $and$ls180.v:4798$1368_Y attribute \src "ls180.v:4798.217-4798.293" wire $and$ls180.v:4798$1371_Y attribute \src "ls180.v:4798.299-4798.375" wire $and$ls180.v:4798$1374_Y attribute \src "ls180.v:4799.54-4799.130" wire $and$ls180.v:4799$1377_Y attribute \src "ls180.v:4799.136-4799.212" wire $and$ls180.v:4799$1380_Y attribute \src "ls180.v:4799.218-4799.294" wire $and$ls180.v:4799$1383_Y attribute \src "ls180.v:4799.300-4799.376" wire $and$ls180.v:4799$1386_Y attribute \src "ls180.v:4818.8-4818.39" wire $and$ls180.v:4818$1389_Y attribute \src "ls180.v:4821.8-4821.43" wire $and$ls180.v:4821$1390_Y attribute \src "ls180.v:4826.8-4826.49" wire $and$ls180.v:4826$1392_Y attribute \src "ls180.v:4826.7-4826.75" wire $and$ls180.v:4826$1394_Y attribute \src "ls180.v:4832.8-4832.49" wire $and$ls180.v:4832$1395_Y attribute \src "ls180.v:4856.8-4856.38" wire $and$ls180.v:4856$1402_Y attribute \src "ls180.v:4889.7-4889.37" wire $and$ls180.v:4889$1408_Y attribute \src "ls180.v:4896.7-4896.37" wire $and$ls180.v:4896$1410_Y attribute \src "ls180.v:4906.8-4906.55" wire $and$ls180.v:4906$1411_Y attribute \src "ls180.v:4906.7-4906.77" wire $and$ls180.v:4906$1413_Y attribute \src "ls180.v:4912.8-4912.55" wire $and$ls180.v:4912$1416_Y attribute \src "ls180.v:4912.7-4912.77" wire $and$ls180.v:4912$1418_Y attribute \src "ls180.v:4928.8-4928.55" wire $and$ls180.v:4928$1422_Y attribute \src "ls180.v:4928.7-4928.77" wire $and$ls180.v:4928$1424_Y attribute \src "ls180.v:4934.8-4934.55" wire $and$ls180.v:4934$1427_Y attribute \src "ls180.v:4934.7-4934.77" wire $and$ls180.v:4934$1429_Y attribute \src "ls180.v:1547.37-1547.91" wire $eq$ls180.v:1547$21_Y attribute \src "ls180.v:1554.11-1554.49" wire $eq$ls180.v:1554$26_Y attribute \src "ls180.v:1607.37-1607.91" wire $eq$ls180.v:1607$32_Y attribute \src "ls180.v:1614.11-1614.49" wire $eq$ls180.v:1614$37_Y attribute \src "ls180.v:1667.37-1667.91" wire $eq$ls180.v:1667$43_Y attribute \src "ls180.v:1674.11-1674.49" wire $eq$ls180.v:1674$48_Y attribute \src "ls180.v:1870.29-1870.55" wire $eq$ls180.v:1870$89_Y attribute \src "ls180.v:1874.58-1874.87" wire $eq$ls180.v:1874$92_Y attribute \src "ls180.v:1918.38-1918.119" wire $eq$ls180.v:1918$97_Y attribute \src "ls180.v:1935.42-1935.78" wire $eq$ls180.v:1935$110_Y attribute \src "ls180.v:2075.38-2075.119" wire $eq$ls180.v:2075$127_Y attribute \src "ls180.v:2092.42-2092.78" wire $eq$ls180.v:2092$140_Y attribute \src "ls180.v:2232.38-2232.119" wire $eq$ls180.v:2232$157_Y attribute \src "ls180.v:2249.42-2249.78" wire $eq$ls180.v:2249$170_Y attribute \src "ls180.v:2389.38-2389.119" wire $eq$ls180.v:2389$187_Y attribute \src "ls180.v:2406.42-2406.78" wire $eq$ls180.v:2406$200_Y attribute \src "ls180.v:2543.27-2543.46" wire $eq$ls180.v:2543$247_Y attribute \src "ls180.v:2544.27-2544.46" wire $eq$ls180.v:2544$248_Y attribute \src "ls180.v:2555.299-2555.368" wire $eq$ls180.v:2555$262_Y attribute \src "ls180.v:2555.373-2555.444" wire $eq$ls180.v:2555$263_Y attribute \src "ls180.v:2556.299-2556.368" wire $eq$ls180.v:2556$275_Y attribute \src "ls180.v:2556.373-2556.444" wire $eq$ls180.v:2556$276_Y attribute \src "ls180.v:2557.299-2557.368" wire $eq$ls180.v:2557$288_Y attribute \src "ls180.v:2557.373-2557.444" wire $eq$ls180.v:2557$289_Y attribute \src "ls180.v:2558.299-2558.368" wire $eq$ls180.v:2558$301_Y attribute \src "ls180.v:2558.373-2558.444" wire $eq$ls180.v:2558$302_Y attribute \src "ls180.v:2588.299-2588.368" wire $eq$ls180.v:2588$320_Y attribute \src "ls180.v:2588.373-2588.444" wire $eq$ls180.v:2588$321_Y attribute \src "ls180.v:2589.299-2589.368" wire $eq$ls180.v:2589$333_Y attribute \src "ls180.v:2589.373-2589.444" wire $eq$ls180.v:2589$334_Y attribute \src "ls180.v:2590.299-2590.368" wire $eq$ls180.v:2590$346_Y attribute \src "ls180.v:2590.373-2590.444" wire $eq$ls180.v:2590$347_Y attribute \src "ls180.v:2591.299-2591.368" wire $eq$ls180.v:2591$359_Y attribute \src "ls180.v:2591.373-2591.444" wire $eq$ls180.v:2591$360_Y attribute \src "ls180.v:2620.68-2620.98" wire $eq$ls180.v:2620$369_Y attribute \src "ls180.v:2623.68-2623.98" wire $eq$ls180.v:2623$372_Y attribute \src "ls180.v:2629.68-2629.98" wire $eq$ls180.v:2629$376_Y attribute \src "ls180.v:2632.68-2632.98" wire $eq$ls180.v:2632$379_Y attribute \src "ls180.v:2638.68-2638.98" wire $eq$ls180.v:2638$383_Y attribute \src "ls180.v:2641.68-2641.98" wire $eq$ls180.v:2641$386_Y attribute \src "ls180.v:2647.68-2647.98" wire $eq$ls180.v:2647$390_Y attribute \src "ls180.v:2650.68-2650.98" wire $eq$ls180.v:2650$393_Y attribute \src "ls180.v:2731.47-2731.82" wire $eq$ls180.v:2731$416_Y attribute \src "ls180.v:2731.145-2731.183" wire $eq$ls180.v:2731$417_Y attribute \src "ls180.v:2731.220-2731.258" wire $eq$ls180.v:2731$420_Y attribute \src "ls180.v:2731.295-2731.333" wire $eq$ls180.v:2731$423_Y attribute \src "ls180.v:2736.47-2736.82" wire $eq$ls180.v:2736$432_Y attribute \src "ls180.v:2736.145-2736.183" wire $eq$ls180.v:2736$433_Y attribute \src "ls180.v:2736.220-2736.258" wire $eq$ls180.v:2736$436_Y attribute \src "ls180.v:2736.295-2736.333" wire $eq$ls180.v:2736$439_Y attribute \src "ls180.v:2741.47-2741.82" wire $eq$ls180.v:2741$448_Y attribute \src "ls180.v:2741.145-2741.183" wire $eq$ls180.v:2741$449_Y attribute \src "ls180.v:2741.220-2741.258" wire $eq$ls180.v:2741$452_Y attribute \src "ls180.v:2741.295-2741.333" wire $eq$ls180.v:2741$455_Y attribute \src "ls180.v:2746.47-2746.82" wire $eq$ls180.v:2746$464_Y attribute \src "ls180.v:2746.145-2746.183" wire $eq$ls180.v:2746$465_Y attribute \src "ls180.v:2746.220-2746.258" wire $eq$ls180.v:2746$468_Y attribute \src "ls180.v:2746.295-2746.333" wire $eq$ls180.v:2746$471_Y attribute \src "ls180.v:2751.39-2751.77" wire $eq$ls180.v:2751$480_Y attribute \src "ls180.v:2751.83-2751.118" wire $eq$ls180.v:2751$481_Y attribute \src "ls180.v:2751.181-2751.219" wire $eq$ls180.v:2751$482_Y attribute \src "ls180.v:2751.256-2751.294" wire $eq$ls180.v:2751$485_Y attribute \src "ls180.v:2751.331-2751.369" wire $eq$ls180.v:2751$488_Y attribute \src "ls180.v:2751.413-2751.451" wire $eq$ls180.v:2751$496_Y attribute \src "ls180.v:2751.457-2751.492" wire $eq$ls180.v:2751$497_Y attribute \src "ls180.v:2751.555-2751.593" wire $eq$ls180.v:2751$498_Y attribute \src "ls180.v:2751.630-2751.668" wire $eq$ls180.v:2751$501_Y attribute \src "ls180.v:2751.705-2751.743" wire $eq$ls180.v:2751$504_Y attribute \src "ls180.v:2751.787-2751.825" wire $eq$ls180.v:2751$512_Y attribute \src "ls180.v:2751.831-2751.866" wire $eq$ls180.v:2751$513_Y attribute \src "ls180.v:2751.929-2751.967" wire $eq$ls180.v:2751$514_Y attribute \src "ls180.v:2751.1004-2751.1042" wire $eq$ls180.v:2751$517_Y attribute \src "ls180.v:2751.1079-2751.1117" wire $eq$ls180.v:2751$520_Y attribute \src "ls180.v:2751.1161-2751.1199" wire $eq$ls180.v:2751$528_Y attribute \src "ls180.v:2751.1205-2751.1240" wire $eq$ls180.v:2751$529_Y attribute \src "ls180.v:2751.1303-2751.1341" wire $eq$ls180.v:2751$530_Y attribute \src "ls180.v:2751.1378-2751.1416" wire $eq$ls180.v:2751$533_Y attribute \src "ls180.v:2751.1453-2751.1491" wire $eq$ls180.v:2751$536_Y attribute \src "ls180.v:2810.24-2810.47" wire $eq$ls180.v:2810$549_Y attribute \src "ls180.v:2817.11-2817.36" wire $eq$ls180.v:2817$554_Y attribute \src "ls180.v:3074.84-3074.109" wire $eq$ls180.v:3074$626_Y attribute \src "ls180.v:3075.84-3075.109" wire $eq$ls180.v:3075$628_Y attribute \src "ls180.v:3076.84-3076.109" wire $eq$ls180.v:3076$630_Y attribute \src "ls180.v:3077.84-3077.109" wire $eq$ls180.v:3077$632_Y attribute \src "ls180.v:3078.84-3078.109" wire $eq$ls180.v:3078$634_Y attribute \src "ls180.v:3079.84-3079.109" wire $eq$ls180.v:3079$636_Y attribute \src "ls180.v:3083.31-3083.67" wire $eq$ls180.v:3083$639_Y attribute \src "ls180.v:3084.31-3084.68" wire $eq$ls180.v:3084$640_Y attribute \src "ls180.v:3085.31-3085.76" wire $eq$ls180.v:3085$641_Y attribute \src "ls180.v:3086.31-3086.74" wire $eq$ls180.v:3086$642_Y attribute \src "ls180.v:3087.31-3087.69" wire $eq$ls180.v:3087$643_Y attribute \src "ls180.v:3088.31-3088.73" wire $eq$ls180.v:3088$644_Y attribute \src "ls180.v:3152.28-3152.53" wire $eq$ls180.v:3152$676_Y attribute \src "ls180.v:3153.36-3153.85" wire $eq$ls180.v:3153$677_Y attribute \src "ls180.v:3155.109-3155.157" wire $eq$ls180.v:3155$679_Y attribute \src "ls180.v:3156.112-3156.160" wire $eq$ls180.v:3156$683_Y attribute \src "ls180.v:3158.111-3158.159" wire $eq$ls180.v:3158$686_Y attribute \src "ls180.v:3159.114-3159.162" wire $eq$ls180.v:3159$690_Y attribute \src "ls180.v:3161.111-3161.159" wire $eq$ls180.v:3161$693_Y attribute \src "ls180.v:3162.114-3162.162" wire $eq$ls180.v:3162$697_Y attribute \src "ls180.v:3164.111-3164.159" wire $eq$ls180.v:3164$700_Y attribute \src "ls180.v:3165.114-3165.162" wire $eq$ls180.v:3165$704_Y attribute \src "ls180.v:3167.111-3167.159" wire $eq$ls180.v:3167$707_Y attribute \src "ls180.v:3168.114-3168.162" wire $eq$ls180.v:3168$711_Y attribute \src "ls180.v:3170.114-3170.162" wire $eq$ls180.v:3170$714_Y attribute \src "ls180.v:3171.117-3171.165" wire $eq$ls180.v:3171$718_Y attribute \src "ls180.v:3173.114-3173.162" wire $eq$ls180.v:3173$721_Y attribute \src "ls180.v:3174.117-3174.165" wire $eq$ls180.v:3174$725_Y attribute \src "ls180.v:3176.114-3176.162" wire $eq$ls180.v:3176$728_Y attribute \src "ls180.v:3177.117-3177.165" wire $eq$ls180.v:3177$732_Y attribute \src "ls180.v:3179.114-3179.162" wire $eq$ls180.v:3179$735_Y attribute \src "ls180.v:3180.117-3180.165" wire $eq$ls180.v:3180$739_Y attribute \src "ls180.v:3191.36-3191.85" wire $eq$ls180.v:3191$741_Y attribute \src "ls180.v:3193.106-3193.154" wire $eq$ls180.v:3193$743_Y attribute \src "ls180.v:3194.109-3194.157" wire $eq$ls180.v:3194$747_Y attribute \src "ls180.v:3196.105-3196.153" wire $eq$ls180.v:3196$750_Y attribute \src "ls180.v:3197.108-3197.156" wire $eq$ls180.v:3197$754_Y attribute \src "ls180.v:3199.107-3199.155" wire $eq$ls180.v:3199$757_Y attribute \src "ls180.v:3200.110-3200.158" wire $eq$ls180.v:3200$761_Y attribute \src "ls180.v:3205.36-3205.85" wire $eq$ls180.v:3205$763_Y attribute \src "ls180.v:3207.106-3207.154" wire $eq$ls180.v:3207$765_Y attribute \src "ls180.v:3208.109-3208.157" wire $eq$ls180.v:3208$769_Y attribute \src "ls180.v:3210.105-3210.153" wire $eq$ls180.v:3210$772_Y attribute \src "ls180.v:3211.108-3211.156" wire $eq$ls180.v:3211$776_Y attribute \src "ls180.v:3213.107-3213.155" wire $eq$ls180.v:3213$779_Y attribute \src "ls180.v:3214.110-3214.158" wire $eq$ls180.v:3214$783_Y attribute \src "ls180.v:3219.36-3219.85" wire $eq$ls180.v:3219$785_Y attribute \src "ls180.v:3221.105-3221.151" wire $eq$ls180.v:3221$787_Y attribute \src "ls180.v:3222.108-3222.154" wire $eq$ls180.v:3222$791_Y attribute \src "ls180.v:3224.104-3224.150" wire $eq$ls180.v:3224$794_Y attribute \src "ls180.v:3225.107-3225.153" wire $eq$ls180.v:3225$798_Y attribute \src "ls180.v:3233.36-3233.85" wire $eq$ls180.v:3233$800_Y attribute \src "ls180.v:3235.116-3235.164" wire $eq$ls180.v:3235$802_Y attribute \src "ls180.v:3236.119-3236.167" wire $eq$ls180.v:3236$806_Y attribute \src "ls180.v:3238.120-3238.168" wire $eq$ls180.v:3238$809_Y attribute \src "ls180.v:3239.123-3239.171" wire $eq$ls180.v:3239$813_Y attribute \src "ls180.v:3241.101-3241.149" wire $eq$ls180.v:3241$816_Y attribute \src "ls180.v:3242.104-3242.152" wire $eq$ls180.v:3242$820_Y attribute \src "ls180.v:3244.120-3244.168" wire $eq$ls180.v:3244$823_Y attribute \src "ls180.v:3245.123-3245.171" wire $eq$ls180.v:3245$827_Y attribute \src "ls180.v:3247.120-3247.168" wire $eq$ls180.v:3247$830_Y attribute \src "ls180.v:3248.123-3248.171" wire $eq$ls180.v:3248$834_Y attribute \src "ls180.v:3250.121-3250.169" wire $eq$ls180.v:3250$837_Y attribute \src "ls180.v:3251.124-3251.172" wire $eq$ls180.v:3251$841_Y attribute \src "ls180.v:3253.119-3253.167" wire $eq$ls180.v:3253$844_Y attribute \src "ls180.v:3254.122-3254.170" wire $eq$ls180.v:3254$848_Y attribute \src "ls180.v:3256.119-3256.167" wire $eq$ls180.v:3256$851_Y attribute \src "ls180.v:3257.122-3257.170" wire $eq$ls180.v:3257$855_Y attribute \src "ls180.v:3259.119-3259.167" wire $eq$ls180.v:3259$858_Y attribute \src "ls180.v:3260.122-3260.170" wire $eq$ls180.v:3260$862_Y attribute \src "ls180.v:3262.119-3262.167" wire $eq$ls180.v:3262$865_Y attribute \src "ls180.v:3263.122-3263.170" wire $eq$ls180.v:3263$869_Y attribute \src "ls180.v:3278.36-3278.85" wire $eq$ls180.v:3278$871_Y attribute \src "ls180.v:3280.108-3280.156" wire $eq$ls180.v:3280$873_Y attribute \src "ls180.v:3281.111-3281.159" wire $eq$ls180.v:3281$877_Y attribute \src "ls180.v:3283.108-3283.156" wire $eq$ls180.v:3283$880_Y attribute \src "ls180.v:3284.111-3284.159" wire $eq$ls180.v:3284$884_Y attribute \src "ls180.v:3286.108-3286.156" wire $eq$ls180.v:3286$887_Y attribute \src "ls180.v:3287.111-3287.159" wire $eq$ls180.v:3287$891_Y attribute \src "ls180.v:3289.108-3289.156" wire $eq$ls180.v:3289$894_Y attribute \src "ls180.v:3290.111-3290.159" wire $eq$ls180.v:3290$898_Y attribute \src "ls180.v:3292.110-3292.158" wire $eq$ls180.v:3292$901_Y attribute \src "ls180.v:3293.113-3293.161" wire $eq$ls180.v:3293$905_Y attribute \src "ls180.v:3295.110-3295.158" wire $eq$ls180.v:3295$908_Y attribute \src "ls180.v:3296.113-3296.161" wire $eq$ls180.v:3296$912_Y attribute \src "ls180.v:3298.110-3298.158" wire $eq$ls180.v:3298$915_Y attribute \src "ls180.v:3299.113-3299.161" wire $eq$ls180.v:3299$919_Y attribute \src "ls180.v:3301.110-3301.158" wire $eq$ls180.v:3301$922_Y attribute \src "ls180.v:3302.113-3302.161" wire $eq$ls180.v:3302$926_Y attribute \src "ls180.v:3304.106-3304.154" wire $eq$ls180.v:3304$929_Y attribute \src "ls180.v:3305.109-3305.157" wire $eq$ls180.v:3305$933_Y attribute \src "ls180.v:3307.116-3307.164" wire $eq$ls180.v:3307$936_Y attribute \src "ls180.v:3308.119-3308.167" wire $eq$ls180.v:3308$940_Y attribute \src "ls180.v:3310.109-3310.158" wire $eq$ls180.v:3310$943_Y attribute \src "ls180.v:3311.112-3311.161" wire $eq$ls180.v:3311$947_Y attribute \src "ls180.v:3313.109-3313.158" wire $eq$ls180.v:3313$950_Y attribute \src "ls180.v:3314.112-3314.161" wire $eq$ls180.v:3314$954_Y attribute \src "ls180.v:3316.109-3316.158" wire $eq$ls180.v:3316$957_Y attribute \src "ls180.v:3317.112-3317.161" wire $eq$ls180.v:3317$961_Y attribute \src "ls180.v:3319.109-3319.158" wire $eq$ls180.v:3319$964_Y attribute \src "ls180.v:3320.112-3320.161" wire $eq$ls180.v:3320$968_Y attribute \src "ls180.v:3322.113-3322.162" wire $eq$ls180.v:3322$971_Y attribute \src "ls180.v:3323.116-3323.165" wire $eq$ls180.v:3323$975_Y attribute \src "ls180.v:3325.114-3325.163" wire $eq$ls180.v:3325$978_Y attribute \src "ls180.v:3326.117-3326.166" wire $eq$ls180.v:3326$982_Y attribute \src "ls180.v:3328.113-3328.162" wire $eq$ls180.v:3328$985_Y attribute \src "ls180.v:3329.116-3329.165" wire $eq$ls180.v:3329$989_Y attribute \src "ls180.v:3346.36-3346.85" wire $eq$ls180.v:3346$991_Y attribute \src "ls180.v:3348.86-3348.134" wire $eq$ls180.v:3348$993_Y attribute \src "ls180.v:3349.89-3349.137" wire $eq$ls180.v:3349$997_Y attribute \src "ls180.v:3351.109-3351.157" wire $eq$ls180.v:3351$1000_Y attribute \src "ls180.v:3352.112-3352.160" wire $eq$ls180.v:3352$1004_Y attribute \src "ls180.v:3354.110-3354.158" wire $eq$ls180.v:3354$1007_Y attribute \src "ls180.v:3355.113-3355.161" wire $eq$ls180.v:3355$1011_Y attribute \src "ls180.v:3357.101-3357.149" wire $eq$ls180.v:3357$1014_Y attribute \src "ls180.v:3358.104-3358.152" wire $eq$ls180.v:3358$1018_Y attribute \src "ls180.v:3360.102-3360.150" wire $eq$ls180.v:3360$1021_Y attribute \src "ls180.v:3361.105-3361.153" wire $eq$ls180.v:3361$1025_Y attribute \src "ls180.v:3363.113-3363.161" wire $eq$ls180.v:3363$1028_Y attribute \src "ls180.v:3364.116-3364.164" wire $eq$ls180.v:3364$1032_Y attribute \src "ls180.v:3366.110-3366.158" wire $eq$ls180.v:3366$1035_Y attribute \src "ls180.v:3367.113-3367.161" wire $eq$ls180.v:3367$1039_Y attribute \src "ls180.v:3369.109-3369.157" wire $eq$ls180.v:3369$1042_Y attribute \src "ls180.v:3370.112-3370.160" wire $eq$ls180.v:3370$1046_Y attribute \src "ls180.v:3380.36-3380.85" wire $eq$ls180.v:3380$1048_Y attribute \src "ls180.v:3382.115-3382.163" wire $eq$ls180.v:3382$1050_Y attribute \src "ls180.v:3383.118-3383.166" wire $eq$ls180.v:3383$1054_Y attribute \src "ls180.v:3385.115-3385.163" wire $eq$ls180.v:3385$1057_Y attribute \src "ls180.v:3386.118-3386.166" wire $eq$ls180.v:3386$1061_Y attribute \src "ls180.v:3388.115-3388.163" wire $eq$ls180.v:3388$1064_Y attribute \src "ls180.v:3389.118-3389.166" wire $eq$ls180.v:3389$1068_Y attribute \src "ls180.v:3391.115-3391.163" wire $eq$ls180.v:3391$1071_Y attribute \src "ls180.v:3392.118-3392.166" wire $eq$ls180.v:3392$1075_Y attribute \src "ls180.v:3752.28-3752.63" wire $eq$ls180.v:3752$1105_Y attribute \src "ls180.v:3752.126-3752.164" wire $eq$ls180.v:3752$1106_Y attribute \src "ls180.v:3752.201-3752.239" wire $eq$ls180.v:3752$1109_Y attribute \src "ls180.v:3752.276-3752.314" wire $eq$ls180.v:3752$1112_Y attribute \src "ls180.v:3776.28-3776.63" wire $eq$ls180.v:3776$1121_Y attribute \src "ls180.v:3776.126-3776.164" wire $eq$ls180.v:3776$1122_Y attribute \src "ls180.v:3776.201-3776.239" wire $eq$ls180.v:3776$1125_Y attribute \src "ls180.v:3776.276-3776.314" wire $eq$ls180.v:3776$1128_Y attribute \src "ls180.v:3800.28-3800.63" wire $eq$ls180.v:3800$1137_Y attribute \src "ls180.v:3800.126-3800.164" wire $eq$ls180.v:3800$1138_Y attribute \src "ls180.v:3800.201-3800.239" wire $eq$ls180.v:3800$1141_Y attribute \src "ls180.v:3800.276-3800.314" wire $eq$ls180.v:3800$1144_Y attribute \src "ls180.v:3824.28-3824.63" wire $eq$ls180.v:3824$1153_Y attribute \src "ls180.v:3824.126-3824.164" wire $eq$ls180.v:3824$1154_Y attribute \src "ls180.v:3824.201-3824.239" wire $eq$ls180.v:3824$1157_Y attribute \src "ls180.v:3824.276-3824.314" wire $eq$ls180.v:3824$1160_Y attribute \src "ls180.v:4360.8-4360.33" wire $eq$ls180.v:4360$1264_Y attribute \src "ls180.v:4395.8-4395.37" wire $eq$ls180.v:4395$1275_Y attribute \src "ls180.v:4415.33-4415.64" wire $eq$ls180.v:4415$1278_Y attribute \src "ls180.v:4422.7-4422.38" wire $eq$ls180.v:4422$1280_Y attribute \src "ls180.v:4429.7-4429.38" wire $eq$ls180.v:4429$1281_Y attribute \src "ls180.v:4437.7-4437.38" wire $eq$ls180.v:4437$1282_Y attribute \src "ls180.v:4489.9-4489.49" wire $eq$ls180.v:4489$1300_Y attribute \src "ls180.v:4535.9-4535.49" wire $eq$ls180.v:4535$1316_Y attribute \src "ls180.v:4581.9-4581.49" wire $eq$ls180.v:4581$1332_Y attribute \src "ls180.v:4627.9-4627.49" wire $eq$ls180.v:4627$1348_Y attribute \src "ls180.v:4777.9-4777.36" wire $eq$ls180.v:4777$1360_Y attribute \src "ls180.v:4792.9-4792.36" wire $eq$ls180.v:4792$1363_Y attribute \src "ls180.v:4798.54-4798.92" wire $eq$ls180.v:4798$1364_Y attribute \src "ls180.v:4798.136-4798.174" wire $eq$ls180.v:4798$1367_Y attribute \src "ls180.v:4798.218-4798.256" wire $eq$ls180.v:4798$1370_Y attribute \src "ls180.v:4798.300-4798.338" wire $eq$ls180.v:4798$1373_Y attribute \src "ls180.v:4799.55-4799.93" wire $eq$ls180.v:4799$1376_Y attribute \src "ls180.v:4799.137-4799.175" wire $eq$ls180.v:4799$1379_Y attribute \src "ls180.v:4799.219-4799.257" wire $eq$ls180.v:4799$1382_Y attribute \src "ls180.v:4799.301-4799.339" wire $eq$ls180.v:4799$1385_Y attribute \src "ls180.v:4834.9-4834.37" wire $eq$ls180.v:4834$1397_Y attribute \src "ls180.v:4837.10-4837.38" wire $eq$ls180.v:4837$1398_Y attribute \src "ls180.v:4863.9-4863.37" wire $eq$ls180.v:4863$1404_Y attribute \src "ls180.v:4868.10-4868.38" wire $eq$ls180.v:4868$1405_Y attribute \src "ls180.v:5502.28-5502.31" wire width 32 $memrd$\mem$ls180.v:5502$1463_DATA attribute \src "ls180.v:5522.20-5522.25" wire width 32 $memrd$\mem_1$ls180.v:5522$1489_DATA attribute \src "ls180.v:5533.12-5533.19" wire width 25 $memrd$\storage$ls180.v:5533$1497_DATA attribute \src "ls180.v:5540.63-5540.70" wire width 25 $memrd$\storage$ls180.v:5540$1499_DATA attribute \src "ls180.v:5547.14-5547.23" wire width 25 $memrd$\storage_1$ls180.v:5547$1507_DATA attribute \src "ls180.v:5554.63-5554.72" wire width 25 $memrd$\storage_1$ls180.v:5554$1509_DATA attribute \src "ls180.v:5561.14-5561.23" wire width 25 $memrd$\storage_2$ls180.v:5561$1517_DATA attribute \src "ls180.v:5568.63-5568.72" wire width 25 $memrd$\storage_2$ls180.v:5568$1519_DATA attribute \src "ls180.v:5575.14-5575.23" wire width 25 $memrd$\storage_3$ls180.v:5575$1527_DATA attribute \src "ls180.v:5582.63-5582.72" wire width 25 $memrd$\storage_3$ls180.v:5582$1529_DATA attribute \src "ls180.v:5590.14-5590.23" wire width 10 $memrd$\storage_4$ls180.v:5590$1537_DATA attribute \src "ls180.v:5595.15-5595.24" wire width 10 $memrd$\storage_4$ls180.v:5595$1539_DATA attribute \src "ls180.v:5607.14-5607.23" wire width 10 $memrd$\storage_5$ls180.v:5607$1547_DATA attribute \src "ls180.v:5612.15-5612.24" wire width 10 $memrd$\storage_5$ls180.v:5612$1549_DATA attribute \src "ls180.v:0.0-0.0" wire width 7 $memwr$\mem$ls180.v:5492$1_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5492$1_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5492$1_EN attribute \src "ls180.v:0.0-0.0" wire width 7 $memwr$\mem$ls180.v:5494$2_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5494$2_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5494$2_EN attribute \src "ls180.v:0.0-0.0" wire width 7 $memwr$\mem$ls180.v:5496$3_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5496$3_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5496$3_EN attribute \src "ls180.v:0.0-0.0" wire width 7 $memwr$\mem$ls180.v:5498$4_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5498$4_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem$ls180.v:5498$4_EN attribute \src "ls180.v:0.0-0.0" wire width 5 $memwr$\mem_1$ls180.v:5512$5_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5512$5_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5512$5_EN attribute \src "ls180.v:0.0-0.0" wire width 5 $memwr$\mem_1$ls180.v:5514$6_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5514$6_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5514$6_EN attribute \src "ls180.v:0.0-0.0" wire width 5 $memwr$\mem_1$ls180.v:5516$7_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5516$7_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5516$7_EN attribute \src "ls180.v:0.0-0.0" wire width 5 $memwr$\mem_1$ls180.v:5518$8_ADDR attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5518$8_DATA attribute \src "ls180.v:0.0-0.0" wire width 32 $memwr$\mem_1$ls180.v:5518$8_EN attribute \src "ls180.v:0.0-0.0" wire width 3 $memwr$\storage$ls180.v:5532$9_ADDR attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage$ls180.v:5532$9_DATA attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage$ls180.v:5532$9_EN attribute \src "ls180.v:0.0-0.0" wire width 3 $memwr$\storage_1$ls180.v:5546$10_ADDR attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage_1$ls180.v:5546$10_DATA attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage_1$ls180.v:5546$10_EN attribute \src "ls180.v:0.0-0.0" wire width 3 $memwr$\storage_2$ls180.v:5560$11_ADDR attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage_2$ls180.v:5560$11_DATA attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage_2$ls180.v:5560$11_EN attribute \src "ls180.v:0.0-0.0" wire width 3 $memwr$\storage_3$ls180.v:5574$12_ADDR attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage_3$ls180.v:5574$12_DATA attribute \src "ls180.v:0.0-0.0" wire width 25 $memwr$\storage_3$ls180.v:5574$12_EN attribute \src "ls180.v:0.0-0.0" wire width 4 $memwr$\storage_4$ls180.v:5589$13_ADDR attribute \src "ls180.v:0.0-0.0" wire width 10 $memwr$\storage_4$ls180.v:5589$13_DATA attribute \src "ls180.v:0.0-0.0" wire width 10 $memwr$\storage_4$ls180.v:5589$13_EN attribute \src "ls180.v:0.0-0.0" wire width 4 $memwr$\storage_5$ls180.v:5606$14_ADDR attribute \src "ls180.v:0.0-0.0" wire width 10 $memwr$\storage_5$ls180.v:5606$14_DATA attribute \src "ls180.v:0.0-0.0" wire width 10 $memwr$\storage_5$ls180.v:5606$14_EN attribute \src "ls180.v:1702.36-1702.61" wire $ne$ls180.v:1702$63_Y attribute \src "ls180.v:1873.60-1873.89" wire $ne$ls180.v:1873$90_Y attribute \src "ls180.v:1934.8-1934.132" wire $ne$ls180.v:1934$109_Y attribute \src "ls180.v:1966.70-1966.123" wire $ne$ls180.v:1966$116_Y attribute \src "ls180.v:1967.70-1967.123" wire $ne$ls180.v:1967$117_Y attribute \src "ls180.v:2091.8-2091.132" wire $ne$ls180.v:2091$139_Y attribute \src "ls180.v:2123.70-2123.123" wire $ne$ls180.v:2123$146_Y attribute \src "ls180.v:2124.70-2124.123" wire $ne$ls180.v:2124$147_Y attribute \src "ls180.v:2248.8-2248.132" wire $ne$ls180.v:2248$169_Y attribute \src "ls180.v:2280.70-2280.123" wire $ne$ls180.v:2280$176_Y attribute \src "ls180.v:2281.70-2281.123" wire $ne$ls180.v:2281$177_Y attribute \src "ls180.v:2405.8-2405.132" wire $ne$ls180.v:2405$199_Y attribute \src "ls180.v:2437.70-2437.123" wire $ne$ls180.v:2437$206_Y attribute \src "ls180.v:2438.70-2438.123" wire $ne$ls180.v:2438$207_Y attribute \src "ls180.v:2930.37-2930.60" wire $ne$ls180.v:2930$605_Y attribute \src "ls180.v:2931.37-2931.59" wire $ne$ls180.v:2931$606_Y attribute \src "ls180.v:2960.37-2960.60" wire $ne$ls180.v:2960$616_Y attribute \src "ls180.v:2961.37-2961.59" wire $ne$ls180.v:2961$617_Y attribute \src "ls180.v:3056.99-3056.143" wire $ne$ls180.v:3056$624_Y attribute \src "ls180.v:4350.7-4350.47" wire $ne$ls180.v:4350$1259_Y attribute \src "ls180.v:4404.9-4404.38" wire $ne$ls180.v:4404$1276_Y attribute \src "ls180.v:4440.8-4440.39" wire $ne$ls180.v:4440$1283_Y attribute \src "ls180.v:1510.40-1510.70" wire $not$ls180.v:1510$17_Y attribute \src "ls180.v:1549.56-1549.84" wire $not$ls180.v:1549$22_Y attribute \src "ls180.v:1550.56-1550.84" wire $not$ls180.v:1550$23_Y attribute \src "ls180.v:1570.40-1570.70" wire $not$ls180.v:1570$28_Y attribute \src "ls180.v:1609.56-1609.84" wire $not$ls180.v:1609$33_Y attribute \src "ls180.v:1610.56-1610.84" wire $not$ls180.v:1610$34_Y attribute \src "ls180.v:1630.40-1630.73" wire $not$ls180.v:1630$39_Y attribute \src "ls180.v:1669.56-1669.84" wire $not$ls180.v:1669$44_Y attribute \src "ls180.v:1670.56-1670.84" wire $not$ls180.v:1670$45_Y attribute \src "ls180.v:1822.29-1822.54" wire $not$ls180.v:1822$82_Y attribute \src "ls180.v:1823.26-1823.51" wire $not$ls180.v:1823$83_Y attribute \src "ls180.v:1824.27-1824.52" wire $not$ls180.v:1824$84_Y attribute \src "ls180.v:1825.27-1825.52" wire $not$ls180.v:1825$85_Y attribute \src "ls180.v:1867.28-1867.46" wire $not$ls180.v:1867$88_Y attribute \src "ls180.v:1968.53-1968.96" wire $not$ls180.v:1968$118_Y attribute \src "ls180.v:2022.9-2022.40" wire $not$ls180.v:2022$123_Y attribute \src "ls180.v:2125.53-2125.96" wire $not$ls180.v:2125$148_Y attribute \src "ls180.v:2179.9-2179.40" wire $not$ls180.v:2179$153_Y attribute \src "ls180.v:2282.53-2282.96" wire $not$ls180.v:2282$178_Y attribute \src "ls180.v:2336.9-2336.40" wire $not$ls180.v:2336$183_Y attribute \src "ls180.v:2439.53-2439.96" wire $not$ls180.v:2439$208_Y attribute \src "ls180.v:2493.9-2493.40" wire $not$ls180.v:2493$213_Y attribute \src "ls180.v:2535.129-2535.162" wire $not$ls180.v:2535$216_Y attribute \src "ls180.v:2535.168-2535.200" wire $not$ls180.v:2535$218_Y attribute \src "ls180.v:2536.129-2536.162" wire $not$ls180.v:2536$222_Y attribute \src "ls180.v:2536.168-2536.200" wire $not$ls180.v:2536$224_Y attribute \src "ls180.v:2552.38-2552.63" wire width 2 $not$ls180.v:2552$252_Y attribute \src "ls180.v:2555.180-2555.215" wire $not$ls180.v:2555$255_Y attribute \src "ls180.v:2555.221-2555.255" wire $not$ls180.v:2555$257_Y attribute \src "ls180.v:2555.139-2555.257" wire $not$ls180.v:2555$259_Y attribute \src "ls180.v:2556.180-2556.215" wire $not$ls180.v:2556$268_Y attribute \src "ls180.v:2556.221-2556.255" wire $not$ls180.v:2556$270_Y attribute \src "ls180.v:2556.139-2556.257" wire $not$ls180.v:2556$272_Y attribute \src "ls180.v:2557.180-2557.215" wire $not$ls180.v:2557$281_Y attribute \src "ls180.v:2557.221-2557.255" wire $not$ls180.v:2557$283_Y attribute \src "ls180.v:2557.139-2557.257" wire $not$ls180.v:2557$285_Y attribute \src "ls180.v:2558.180-2558.215" wire $not$ls180.v:2558$294_Y attribute \src "ls180.v:2558.221-2558.255" wire $not$ls180.v:2558$296_Y attribute \src "ls180.v:2558.139-2558.257" wire $not$ls180.v:2558$298_Y attribute \src "ls180.v:2585.61-2585.88" wire $not$ls180.v:2585$309_Y attribute \src "ls180.v:2588.180-2588.215" wire $not$ls180.v:2588$313_Y attribute \src "ls180.v:2588.221-2588.255" wire $not$ls180.v:2588$315_Y attribute \src "ls180.v:2588.139-2588.257" wire $not$ls180.v:2588$317_Y attribute \src "ls180.v:2589.180-2589.215" wire $not$ls180.v:2589$326_Y attribute \src "ls180.v:2589.221-2589.255" wire $not$ls180.v:2589$328_Y attribute \src "ls180.v:2589.139-2589.257" wire $not$ls180.v:2589$330_Y attribute \src "ls180.v:2590.180-2590.215" wire $not$ls180.v:2590$339_Y attribute \src "ls180.v:2590.221-2590.255" wire $not$ls180.v:2590$341_Y attribute \src "ls180.v:2590.139-2590.257" wire $not$ls180.v:2590$343_Y attribute \src "ls180.v:2591.180-2591.215" wire $not$ls180.v:2591$352_Y attribute \src "ls180.v:2591.221-2591.255" wire $not$ls180.v:2591$354_Y attribute \src "ls180.v:2591.139-2591.257" wire $not$ls180.v:2591$356_Y attribute \src "ls180.v:2654.61-2654.88" wire $not$ls180.v:2654$395_Y attribute \src "ls180.v:2675.97-2675.130" wire $not$ls180.v:2675$398_Y attribute \src "ls180.v:2675.136-2675.168" wire $not$ls180.v:2675$400_Y attribute \src "ls180.v:2675.58-2675.170" wire $not$ls180.v:2675$402_Y attribute \src "ls180.v:2683.11-2683.33" wire $not$ls180.v:2683$405_Y attribute \src "ls180.v:2713.97-2713.130" wire $not$ls180.v:2713$407_Y attribute \src "ls180.v:2713.136-2713.168" wire $not$ls180.v:2713$409_Y attribute \src "ls180.v:2713.58-2713.170" wire $not$ls180.v:2713$411_Y attribute \src "ls180.v:2721.11-2721.32" wire $not$ls180.v:2721$414_Y attribute \src "ls180.v:2731.87-2731.336" wire $not$ls180.v:2731$426_Y attribute \src "ls180.v:2732.40-2732.68" wire $not$ls180.v:2732$429_Y attribute \src "ls180.v:2732.73-2732.100" wire $not$ls180.v:2732$430_Y attribute \src "ls180.v:2736.87-2736.336" wire $not$ls180.v:2736$442_Y attribute \src "ls180.v:2737.40-2737.68" wire $not$ls180.v:2737$445_Y attribute \src "ls180.v:2737.73-2737.100" wire $not$ls180.v:2737$446_Y attribute \src "ls180.v:2741.87-2741.336" wire $not$ls180.v:2741$458_Y attribute \src "ls180.v:2742.40-2742.68" wire $not$ls180.v:2742$461_Y attribute \src "ls180.v:2742.73-2742.100" wire $not$ls180.v:2742$462_Y attribute \src "ls180.v:2746.87-2746.336" wire $not$ls180.v:2746$474_Y attribute \src "ls180.v:2747.40-2747.68" wire $not$ls180.v:2747$477_Y attribute \src "ls180.v:2747.73-2747.100" wire $not$ls180.v:2747$478_Y attribute \src "ls180.v:2751.123-2751.372" wire $not$ls180.v:2751$491_Y attribute \src "ls180.v:2751.497-2751.746" wire $not$ls180.v:2751$507_Y attribute \src "ls180.v:2751.871-2751.1120" wire $not$ls180.v:2751$523_Y attribute \src "ls180.v:2751.1245-2751.1494" wire $not$ls180.v:2751$539_Y attribute \src "ls180.v:2773.27-2773.40" wire $not$ls180.v:2773$545_Y attribute \src "ls180.v:2812.25-2812.40" wire $not$ls180.v:2812$550_Y attribute \src "ls180.v:2813.25-2813.40" wire $not$ls180.v:2813$551_Y attribute \src "ls180.v:2838.22-2838.38" wire $not$ls180.v:2838$557_Y attribute \src "ls180.v:2839.25-2839.40" wire $not$ls180.v:2839$558_Y attribute \src "ls180.v:2840.65-2840.78" wire $not$ls180.v:2840$560_Y attribute \src "ls180.v:2841.87-2841.102" wire $not$ls180.v:2841$564_Y attribute \src "ls180.v:2842.63-2842.83" wire $not$ls180.v:2842$567_Y attribute \src "ls180.v:2843.71-2843.86" wire $not$ls180.v:2843$570_Y attribute \src "ls180.v:2859.25-2859.44" wire $not$ls180.v:2859$579_Y attribute \src "ls180.v:2860.26-2860.47" wire $not$ls180.v:2860$580_Y attribute \src "ls180.v:2866.22-2866.41" wire $not$ls180.v:2866$581_Y attribute \src "ls180.v:2872.26-2872.47" wire $not$ls180.v:2872$582_Y attribute \src "ls180.v:2873.25-2873.44" wire $not$ls180.v:2873$583_Y attribute \src "ls180.v:2876.22-2876.43" wire $not$ls180.v:2876$586_Y attribute \src "ls180.v:2914.61-2914.78" wire $not$ls180.v:2914$596_Y attribute \src "ls180.v:2944.61-2944.78" wire $not$ls180.v:2944$607_Y attribute \src "ls180.v:3139.81-3139.104" wire $not$ls180.v:3139$657_Y attribute \src "ls180.v:3156.71-3156.106" wire $not$ls180.v:3156$681_Y attribute \src "ls180.v:3159.73-3159.108" wire $not$ls180.v:3159$688_Y attribute \src "ls180.v:3162.73-3162.108" wire $not$ls180.v:3162$695_Y attribute \src "ls180.v:3165.73-3165.108" wire $not$ls180.v:3165$702_Y attribute \src "ls180.v:3168.73-3168.108" wire $not$ls180.v:3168$709_Y attribute \src "ls180.v:3171.76-3171.111" wire $not$ls180.v:3171$716_Y attribute \src "ls180.v:3174.76-3174.111" wire $not$ls180.v:3174$723_Y attribute \src "ls180.v:3177.76-3177.111" wire $not$ls180.v:3177$730_Y attribute \src "ls180.v:3180.76-3180.111" wire $not$ls180.v:3180$737_Y attribute \src "ls180.v:3194.68-3194.103" wire $not$ls180.v:3194$745_Y attribute \src "ls180.v:3197.67-3197.102" wire $not$ls180.v:3197$752_Y attribute \src "ls180.v:3200.69-3200.104" wire $not$ls180.v:3200$759_Y attribute \src "ls180.v:3208.68-3208.103" wire $not$ls180.v:3208$767_Y attribute \src "ls180.v:3211.67-3211.102" wire $not$ls180.v:3211$774_Y attribute \src "ls180.v:3214.69-3214.104" wire $not$ls180.v:3214$781_Y attribute \src "ls180.v:3222.67-3222.102" wire $not$ls180.v:3222$789_Y attribute \src "ls180.v:3225.66-3225.101" wire $not$ls180.v:3225$796_Y attribute \src "ls180.v:3236.78-3236.113" wire $not$ls180.v:3236$804_Y attribute \src "ls180.v:3239.82-3239.117" wire $not$ls180.v:3239$811_Y attribute \src "ls180.v:3242.63-3242.98" wire $not$ls180.v:3242$818_Y attribute \src "ls180.v:3245.82-3245.117" wire $not$ls180.v:3245$825_Y attribute \src "ls180.v:3248.82-3248.117" wire $not$ls180.v:3248$832_Y attribute \src "ls180.v:3251.83-3251.118" wire $not$ls180.v:3251$839_Y attribute \src "ls180.v:3254.81-3254.116" wire $not$ls180.v:3254$846_Y attribute \src "ls180.v:3257.81-3257.116" wire $not$ls180.v:3257$853_Y attribute \src "ls180.v:3260.81-3260.116" wire $not$ls180.v:3260$860_Y attribute \src "ls180.v:3263.81-3263.116" wire $not$ls180.v:3263$867_Y attribute \src "ls180.v:3281.70-3281.105" wire $not$ls180.v:3281$875_Y attribute \src "ls180.v:3284.70-3284.105" wire $not$ls180.v:3284$882_Y attribute \src "ls180.v:3287.70-3287.105" wire $not$ls180.v:3287$889_Y attribute \src "ls180.v:3290.70-3290.105" wire $not$ls180.v:3290$896_Y attribute \src "ls180.v:3293.72-3293.107" wire $not$ls180.v:3293$903_Y attribute \src "ls180.v:3296.72-3296.107" wire $not$ls180.v:3296$910_Y attribute \src "ls180.v:3299.72-3299.107" wire $not$ls180.v:3299$917_Y attribute \src "ls180.v:3302.72-3302.107" wire $not$ls180.v:3302$924_Y attribute \src "ls180.v:3305.68-3305.103" wire $not$ls180.v:3305$931_Y attribute \src "ls180.v:3308.78-3308.113" wire $not$ls180.v:3308$938_Y attribute \src "ls180.v:3311.71-3311.106" wire $not$ls180.v:3311$945_Y attribute \src "ls180.v:3314.71-3314.106" wire $not$ls180.v:3314$952_Y attribute \src "ls180.v:3317.71-3317.106" wire $not$ls180.v:3317$959_Y attribute \src "ls180.v:3320.71-3320.106" wire $not$ls180.v:3320$966_Y attribute \src "ls180.v:3323.75-3323.110" wire $not$ls180.v:3323$973_Y attribute \src "ls180.v:3326.76-3326.111" wire $not$ls180.v:3326$980_Y attribute \src "ls180.v:3329.75-3329.110" wire $not$ls180.v:3329$987_Y attribute \src "ls180.v:3349.48-3349.83" wire $not$ls180.v:3349$995_Y attribute \src "ls180.v:3352.71-3352.106" wire $not$ls180.v:3352$1002_Y attribute \src "ls180.v:3355.72-3355.107" wire $not$ls180.v:3355$1009_Y attribute \src "ls180.v:3358.63-3358.98" wire $not$ls180.v:3358$1016_Y attribute \src "ls180.v:3361.64-3361.99" wire $not$ls180.v:3361$1023_Y attribute \src "ls180.v:3364.75-3364.110" wire $not$ls180.v:3364$1030_Y attribute \src "ls180.v:3367.72-3367.107" wire $not$ls180.v:3367$1037_Y attribute \src "ls180.v:3370.71-3370.106" wire $not$ls180.v:3370$1044_Y attribute \src "ls180.v:3383.77-3383.112" wire $not$ls180.v:3383$1052_Y attribute \src "ls180.v:3386.77-3386.112" wire $not$ls180.v:3386$1059_Y attribute \src "ls180.v:3389.77-3389.112" wire $not$ls180.v:3389$1066_Y attribute \src "ls180.v:3392.77-3392.112" wire $not$ls180.v:3392$1073_Y attribute \src "ls180.v:3752.68-3752.317" wire $not$ls180.v:3752$1115_Y attribute \src "ls180.v:3776.68-3776.317" wire $not$ls180.v:3776$1131_Y attribute \src "ls180.v:3800.68-3800.317" wire $not$ls180.v:3800$1147_Y attribute \src "ls180.v:3824.68-3824.317" wire $not$ls180.v:3824$1163_Y attribute \src "ls180.v:4356.62-4356.86" wire $not$ls180.v:4356$1262_Y attribute \src "ls180.v:4375.8-4375.33" wire $not$ls180.v:4375$1266_Y attribute \src "ls180.v:4379.54-4379.74" wire $not$ls180.v:4379$1269_Y attribute \src "ls180.v:4387.27-4387.45" wire $not$ls180.v:4387$1271_Y attribute \src "ls180.v:4457.126-4457.174" wire $not$ls180.v:4457$1286_Y attribute \src "ls180.v:4463.126-4463.174" wire $not$ls180.v:4463$1291_Y attribute \src "ls180.v:4464.8-4464.56" wire $not$ls180.v:4464$1293_Y attribute \src "ls180.v:4472.8-4472.51" wire $not$ls180.v:4472$1296_Y attribute \src "ls180.v:4487.8-4487.41" wire $not$ls180.v:4487$1298_Y attribute \src "ls180.v:4503.126-4503.174" wire $not$ls180.v:4503$1302_Y attribute \src "ls180.v:4509.126-4509.174" wire $not$ls180.v:4509$1307_Y attribute \src "ls180.v:4510.8-4510.56" wire $not$ls180.v:4510$1309_Y attribute \src "ls180.v:4518.8-4518.51" wire $not$ls180.v:4518$1312_Y attribute \src "ls180.v:4533.8-4533.41" wire $not$ls180.v:4533$1314_Y attribute \src "ls180.v:4549.126-4549.174" wire $not$ls180.v:4549$1318_Y attribute \src "ls180.v:4555.126-4555.174" wire $not$ls180.v:4555$1323_Y attribute \src "ls180.v:4556.8-4556.56" wire $not$ls180.v:4556$1325_Y attribute \src "ls180.v:4564.8-4564.51" wire $not$ls180.v:4564$1328_Y attribute \src "ls180.v:4579.8-4579.41" wire $not$ls180.v:4579$1330_Y attribute \src "ls180.v:4595.126-4595.174" wire $not$ls180.v:4595$1334_Y attribute \src "ls180.v:4601.126-4601.174" wire $not$ls180.v:4601$1339_Y attribute \src "ls180.v:4602.8-4602.56" wire $not$ls180.v:4602$1341_Y attribute \src "ls180.v:4610.8-4610.51" wire $not$ls180.v:4610$1344_Y attribute \src "ls180.v:4625.8-4625.41" wire $not$ls180.v:4625$1346_Y attribute \src "ls180.v:4633.7-4633.17" wire $not$ls180.v:4633$1349_Y attribute \src "ls180.v:4636.8-4636.24" wire $not$ls180.v:4636$1350_Y attribute \src "ls180.v:4640.7-4640.17" wire $not$ls180.v:4640$1352_Y attribute \src "ls180.v:4643.8-4643.24" wire $not$ls180.v:4643$1353_Y attribute \src "ls180.v:4762.25-4762.38" wire $not$ls180.v:4762$1355_Y attribute \src "ls180.v:4763.25-4763.38" wire $not$ls180.v:4763$1356_Y attribute \src "ls180.v:4764.24-4764.37" wire $not$ls180.v:4764$1357_Y attribute \src "ls180.v:4775.8-4775.28" wire $not$ls180.v:4775$1358_Y attribute \src "ls180.v:4790.8-4790.28" wire $not$ls180.v:4790$1361_Y attribute \src "ls180.v:4826.31-4826.48" wire $not$ls180.v:4826$1391_Y attribute \src "ls180.v:4826.54-4826.74" wire $not$ls180.v:4826$1393_Y attribute \src "ls180.v:4855.7-4855.24" wire $not$ls180.v:4855$1400_Y attribute \src "ls180.v:4856.9-4856.21" wire $not$ls180.v:4856$1401_Y attribute \src "ls180.v:4889.8-4889.19" wire $not$ls180.v:4889$1407_Y attribute \src "ls180.v:4896.8-4896.19" wire $not$ls180.v:4896$1409_Y attribute \src "ls180.v:4906.60-4906.76" wire $not$ls180.v:4906$1412_Y attribute \src "ls180.v:4912.60-4912.76" wire $not$ls180.v:4912$1417_Y attribute \src "ls180.v:4913.8-4913.24" wire $not$ls180.v:4913$1419_Y attribute \src "ls180.v:4928.60-4928.76" wire $not$ls180.v:4928$1423_Y attribute \src "ls180.v:4934.60-4934.76" wire $not$ls180.v:4934$1428_Y attribute \src "ls180.v:4935.8-4935.24" wire $not$ls180.v:4935$1430_Y attribute \src "ls180.v:4969.9-4969.32" wire $not$ls180.v:4969$1433_Y attribute \src "ls180.v:4980.9-4980.32" wire $not$ls180.v:4980$1434_Y attribute \src "ls180.v:4991.9-4991.32" wire $not$ls180.v:4991$1435_Y attribute \src "ls180.v:5004.8-5004.25" wire $not$ls180.v:5004$1436_Y attribute \src "ls180.v:1551.10-1551.86" wire $or$ls180.v:1551$24_Y attribute \src "ls180.v:1611.10-1611.86" wire $or$ls180.v:1611$35_Y attribute \src "ls180.v:1671.10-1671.86" wire $or$ls180.v:1671$46_Y attribute \src "ls180.v:1873.34-1873.90" wire $or$ls180.v:1873$91_Y attribute \src "ls180.v:1916.54-1916.125" wire $or$ls180.v:1916$95_Y attribute \src "ls180.v:1917.39-1917.136" wire $or$ls180.v:1917$96_Y attribute \src "ls180.v:1925.40-1925.155" wire width 13 $or$ls180.v:1925$100_Y attribute \src "ls180.v:1962.117-1962.225" wire $or$ls180.v:1962$113_Y attribute \src "ls180.v:1968.52-1968.142" wire $or$ls180.v:1968$119_Y attribute \src "ls180.v:2073.54-2073.125" wire $or$ls180.v:2073$125_Y attribute \src "ls180.v:2074.39-2074.136" wire $or$ls180.v:2074$126_Y attribute \src "ls180.v:2082.40-2082.155" wire width 13 $or$ls180.v:2082$130_Y attribute \src "ls180.v:2119.117-2119.225" wire $or$ls180.v:2119$143_Y attribute \src "ls180.v:2125.52-2125.142" wire $or$ls180.v:2125$149_Y attribute \src "ls180.v:2230.54-2230.125" wire $or$ls180.v:2230$155_Y attribute \src "ls180.v:2231.39-2231.136" wire $or$ls180.v:2231$156_Y attribute \src "ls180.v:2239.40-2239.155" wire width 13 $or$ls180.v:2239$160_Y attribute \src "ls180.v:2276.117-2276.225" wire $or$ls180.v:2276$173_Y attribute \src "ls180.v:2282.52-2282.142" wire $or$ls180.v:2282$179_Y attribute \src "ls180.v:2387.54-2387.125" wire $or$ls180.v:2387$185_Y attribute \src "ls180.v:2388.39-2388.136" wire $or$ls180.v:2388$186_Y attribute \src "ls180.v:2396.40-2396.155" wire width 13 $or$ls180.v:2396$190_Y attribute \src "ls180.v:2433.117-2433.225" wire $or$ls180.v:2433$203_Y attribute \src "ls180.v:2439.52-2439.142" wire $or$ls180.v:2439$209_Y attribute \src "ls180.v:2538.92-2538.168" wire $or$ls180.v:2538$229_Y attribute \src "ls180.v:2541.34-2541.179" wire $or$ls180.v:2541$235_Y attribute \src "ls180.v:2541.33-2541.254" wire $or$ls180.v:2541$237_Y attribute \src "ls180.v:2541.32-2541.329" wire $or$ls180.v:2541$239_Y attribute \src "ls180.v:2542.35-2542.182" wire $or$ls180.v:2542$242_Y attribute \src "ls180.v:2542.34-2542.258" wire $or$ls180.v:2542$244_Y attribute \src "ls180.v:2542.33-2542.334" wire $or$ls180.v:2542$246_Y attribute \src "ls180.v:2555.138-2555.292" wire $or$ls180.v:2555$260_Y attribute \src "ls180.v:2555.65-2555.446" wire $or$ls180.v:2555$265_Y attribute \src "ls180.v:2556.138-2556.292" wire $or$ls180.v:2556$273_Y attribute \src "ls180.v:2556.65-2556.446" wire $or$ls180.v:2556$278_Y attribute \src "ls180.v:2557.138-2557.292" wire $or$ls180.v:2557$286_Y attribute \src "ls180.v:2557.65-2557.446" wire $or$ls180.v:2557$291_Y attribute \src "ls180.v:2558.138-2558.292" wire $or$ls180.v:2558$299_Y attribute \src "ls180.v:2558.65-2558.446" wire $or$ls180.v:2558$304_Y attribute \src "ls180.v:2585.31-2585.89" wire $or$ls180.v:2585$310_Y attribute \src "ls180.v:2588.138-2588.292" wire $or$ls180.v:2588$318_Y attribute \src "ls180.v:2588.65-2588.446" wire $or$ls180.v:2588$323_Y attribute \src "ls180.v:2589.138-2589.292" wire $or$ls180.v:2589$331_Y attribute \src "ls180.v:2589.65-2589.446" wire $or$ls180.v:2589$336_Y attribute \src "ls180.v:2590.138-2590.292" wire $or$ls180.v:2590$344_Y attribute \src "ls180.v:2590.65-2590.446" wire $or$ls180.v:2590$349_Y attribute \src "ls180.v:2591.138-2591.292" wire $or$ls180.v:2591$357_Y attribute \src "ls180.v:2591.65-2591.446" wire $or$ls180.v:2591$362_Y attribute \src "ls180.v:2654.31-2654.89" wire $or$ls180.v:2654$396_Y attribute \src "ls180.v:2675.57-2675.191" wire $or$ls180.v:2675$403_Y attribute \src "ls180.v:2683.10-2683.52" wire $or$ls180.v:2683$406_Y attribute \src "ls180.v:2713.57-2713.191" wire $or$ls180.v:2713$412_Y attribute \src "ls180.v:2721.10-2721.51" wire $or$ls180.v:2721$415_Y attribute \src "ls180.v:2731.91-2731.185" wire $or$ls180.v:2731$419_Y attribute \src "ls180.v:2731.90-2731.260" wire $or$ls180.v:2731$422_Y attribute \src "ls180.v:2731.89-2731.335" wire $or$ls180.v:2731$425_Y attribute \src "ls180.v:2736.91-2736.185" wire $or$ls180.v:2736$435_Y attribute \src "ls180.v:2736.90-2736.260" wire $or$ls180.v:2736$438_Y attribute \src "ls180.v:2736.89-2736.335" wire $or$ls180.v:2736$441_Y attribute \src "ls180.v:2741.91-2741.185" wire $or$ls180.v:2741$451_Y attribute \src "ls180.v:2741.90-2741.260" wire $or$ls180.v:2741$454_Y attribute \src "ls180.v:2741.89-2741.335" wire $or$ls180.v:2741$457_Y attribute \src "ls180.v:2746.91-2746.185" wire $or$ls180.v:2746$467_Y attribute \src "ls180.v:2746.90-2746.260" wire $or$ls180.v:2746$470_Y attribute \src "ls180.v:2746.89-2746.335" wire $or$ls180.v:2746$473_Y attribute \src "ls180.v:2751.127-2751.221" wire $or$ls180.v:2751$484_Y attribute \src "ls180.v:2751.126-2751.296" wire $or$ls180.v:2751$487_Y attribute \src "ls180.v:2751.125-2751.371" wire $or$ls180.v:2751$490_Y attribute \src "ls180.v:2751.29-2751.406" wire $or$ls180.v:2751$495_Y attribute \src "ls180.v:2751.501-2751.595" wire $or$ls180.v:2751$500_Y attribute \src "ls180.v:2751.500-2751.670" wire $or$ls180.v:2751$503_Y attribute \src "ls180.v:2751.499-2751.745" wire $or$ls180.v:2751$506_Y attribute \src "ls180.v:2751.28-2751.780" wire $or$ls180.v:2751$511_Y attribute \src "ls180.v:2751.875-2751.969" wire $or$ls180.v:2751$516_Y attribute \src "ls180.v:2751.874-2751.1044" wire $or$ls180.v:2751$519_Y attribute \src "ls180.v:2751.873-2751.1119" wire $or$ls180.v:2751$522_Y attribute \src "ls180.v:2751.27-2751.1154" wire $or$ls180.v:2751$527_Y attribute \src "ls180.v:2751.1249-2751.1343" wire $or$ls180.v:2751$532_Y attribute \src "ls180.v:2751.1248-2751.1418" wire $or$ls180.v:2751$535_Y attribute \src "ls180.v:2751.1247-2751.1493" wire $or$ls180.v:2751$538_Y attribute \src "ls180.v:2751.26-2751.1528" wire $or$ls180.v:2751$543_Y attribute \src "ls180.v:2814.10-2814.42" wire $or$ls180.v:2814$552_Y attribute \src "ls180.v:2841.30-2841.59" wire $or$ls180.v:2841$562_Y attribute \src "ls180.v:2842.29-2842.58" wire $or$ls180.v:2842$566_Y attribute \src "ls180.v:2843.38-2843.100" wire $or$ls180.v:2843$572_Y attribute \src "ls180.v:2844.19-2844.67" wire $or$ls180.v:2844$575_Y attribute \src "ls180.v:2845.21-2845.75" wire $or$ls180.v:2845$577_Y attribute \src "ls180.v:2875.32-2875.59" wire $or$ls180.v:2875$585_Y attribute \src "ls180.v:2899.15-2899.124" wire $or$ls180.v:2899$595_Y attribute \src "ls180.v:2914.60-2914.92" wire $or$ls180.v:2914$597_Y attribute \src "ls180.v:2925.52-2925.95" wire $or$ls180.v:2925$602_Y attribute \src "ls180.v:2944.60-2944.92" wire $or$ls180.v:2944$608_Y attribute \src "ls180.v:2955.52-2955.95" wire $or$ls180.v:2955$613_Y attribute \src "ls180.v:3138.38-3138.83" wire $or$ls180.v:3138$651_Y attribute \src "ls180.v:3138.37-3138.120" wire $or$ls180.v:3138$652_Y attribute \src "ls180.v:3138.36-3138.157" wire $or$ls180.v:3138$653_Y attribute \src "ls180.v:3138.35-3138.173" wire $or$ls180.v:3138$654_Y attribute \src "ls180.v:3138.34-3138.213" wire $or$ls180.v:3138$655_Y attribute \src "ls180.v:3144.33-3144.78" wire $or$ls180.v:3144$660_Y attribute \src "ls180.v:3144.32-3144.115" wire $or$ls180.v:3144$661_Y attribute \src "ls180.v:3144.31-3144.152" wire $or$ls180.v:3144$662_Y attribute \src "ls180.v:3144.30-3144.168" wire $or$ls180.v:3144$663_Y attribute \src "ls180.v:3144.29-3144.208" wire $or$ls180.v:3144$664_Y attribute \src "ls180.v:3145.35-3145.158" wire width 32 $or$ls180.v:3145$667_Y attribute \src "ls180.v:3145.34-3145.234" wire width 32 $or$ls180.v:3145$669_Y attribute \src "ls180.v:3145.33-3145.310" wire width 32 $or$ls180.v:3145$671_Y attribute \src "ls180.v:3145.32-3145.365" wire width 32 $or$ls180.v:3145$673_Y attribute \src "ls180.v:3145.31-3145.444" wire width 32 $or$ls180.v:3145$675_Y attribute \src "ls180.v:3425.52-3425.129" wire width 8 $or$ls180.v:3425$1077_Y attribute \src "ls180.v:3425.51-3425.170" wire width 8 $or$ls180.v:3425$1078_Y attribute \src "ls180.v:3425.50-3425.211" wire width 8 $or$ls180.v:3425$1079_Y attribute \src "ls180.v:3425.49-3425.252" wire width 8 $or$ls180.v:3425$1080_Y attribute \src "ls180.v:3425.48-3425.293" wire width 8 $or$ls180.v:3425$1081_Y attribute \src "ls180.v:3425.47-3425.334" wire width 8 $or$ls180.v:3425$1082_Y attribute \src "ls180.v:3425.46-3425.375" wire width 8 $or$ls180.v:3425$1083_Y attribute \src "ls180.v:3752.72-3752.166" wire $or$ls180.v:3752$1108_Y attribute \src "ls180.v:3752.71-3752.241" wire $or$ls180.v:3752$1111_Y attribute \src "ls180.v:3752.70-3752.316" wire $or$ls180.v:3752$1114_Y attribute \src "ls180.v:3776.72-3776.166" wire $or$ls180.v:3776$1124_Y attribute \src "ls180.v:3776.71-3776.241" wire $or$ls180.v:3776$1127_Y attribute \src "ls180.v:3776.70-3776.316" wire $or$ls180.v:3776$1130_Y attribute \src "ls180.v:3800.72-3800.166" wire $or$ls180.v:3800$1140_Y attribute \src "ls180.v:3800.71-3800.241" wire $or$ls180.v:3800$1143_Y attribute \src "ls180.v:3800.70-3800.316" wire $or$ls180.v:3800$1146_Y attribute \src "ls180.v:3824.72-3824.166" wire $or$ls180.v:3824$1156_Y attribute \src "ls180.v:3824.71-3824.241" wire $or$ls180.v:3824$1159_Y attribute \src "ls180.v:3824.70-3824.316" wire $or$ls180.v:3824$1162_Y attribute \src "ls180.v:4277.15-4277.58" wire $or$ls180.v:4277$1216_Y attribute \src "ls180.v:4278.15-4278.58" wire $or$ls180.v:4278$1217_Y attribute \src "ls180.v:4279.15-4279.58" wire $or$ls180.v:4279$1218_Y attribute \src "ls180.v:4280.15-4280.58" wire $or$ls180.v:4280$1219_Y attribute \src "ls180.v:4281.15-4281.58" wire $or$ls180.v:4281$1220_Y attribute \src "ls180.v:4282.15-4282.58" wire $or$ls180.v:4282$1221_Y attribute \src "ls180.v:4283.15-4283.58" wire $or$ls180.v:4283$1222_Y attribute \src "ls180.v:4284.15-4284.58" wire $or$ls180.v:4284$1223_Y attribute \src "ls180.v:4285.15-4285.58" wire $or$ls180.v:4285$1224_Y attribute \src "ls180.v:4286.15-4286.58" wire $or$ls180.v:4286$1225_Y attribute \src "ls180.v:4287.16-4287.60" wire $or$ls180.v:4287$1226_Y attribute \src "ls180.v:4288.16-4288.60" wire $or$ls180.v:4288$1227_Y attribute \src "ls180.v:4289.16-4289.60" wire $or$ls180.v:4289$1228_Y attribute \src "ls180.v:4290.16-4290.60" wire $or$ls180.v:4290$1229_Y attribute \src "ls180.v:4291.16-4291.60" wire $or$ls180.v:4291$1230_Y attribute \src "ls180.v:4292.16-4292.60" wire $or$ls180.v:4292$1231_Y attribute \src "ls180.v:4293.16-4293.60" wire $or$ls180.v:4293$1232_Y attribute \src "ls180.v:4294.16-4294.60" wire $or$ls180.v:4294$1233_Y attribute \src "ls180.v:4295.16-4295.60" wire $or$ls180.v:4295$1234_Y attribute \src "ls180.v:4296.16-4296.60" wire $or$ls180.v:4296$1235_Y attribute \src "ls180.v:4297.16-4297.60" wire $or$ls180.v:4297$1236_Y attribute \src "ls180.v:4298.16-4298.60" wire $or$ls180.v:4298$1237_Y attribute \src "ls180.v:4299.16-4299.60" wire $or$ls180.v:4299$1238_Y attribute \src "ls180.v:4300.16-4300.60" wire $or$ls180.v:4300$1239_Y attribute \src "ls180.v:4301.16-4301.60" wire $or$ls180.v:4301$1240_Y attribute \src "ls180.v:4302.16-4302.60" wire $or$ls180.v:4302$1241_Y attribute \src "ls180.v:4303.16-4303.60" wire $or$ls180.v:4303$1242_Y attribute \src "ls180.v:4304.16-4304.60" wire $or$ls180.v:4304$1243_Y attribute \src "ls180.v:4305.16-4305.60" wire $or$ls180.v:4305$1244_Y attribute \src "ls180.v:4306.16-4306.60" wire $or$ls180.v:4306$1245_Y attribute \src "ls180.v:4307.16-4307.60" wire $or$ls180.v:4307$1246_Y attribute \src "ls180.v:4308.16-4308.60" wire $or$ls180.v:4308$1247_Y attribute \src "ls180.v:4309.16-4309.60" wire $or$ls180.v:4309$1248_Y attribute \src "ls180.v:4310.16-4310.60" wire $or$ls180.v:4310$1249_Y attribute \src "ls180.v:4311.16-4311.60" wire $or$ls180.v:4311$1250_Y attribute \src "ls180.v:4312.16-4312.60" wire $or$ls180.v:4312$1251_Y attribute \src "ls180.v:4313.16-4313.60" wire $or$ls180.v:4313$1252_Y attribute \src "ls180.v:4314.16-4314.60" wire $or$ls180.v:4314$1253_Y attribute \src "ls180.v:4315.16-4315.60" wire $or$ls180.v:4315$1254_Y attribute \src "ls180.v:4316.16-4316.60" wire $or$ls180.v:4316$1255_Y attribute \src "ls180.v:4317.7-4317.83" wire $or$ls180.v:4317$1256_Y attribute \src "ls180.v:4328.7-4328.83" wire $or$ls180.v:4328$1257_Y attribute \src "ls180.v:4339.7-4339.83" wire $or$ls180.v:4339$1258_Y attribute \src "ls180.v:4472.7-4472.97" wire $or$ls180.v:4472$1297_Y attribute \src "ls180.v:4518.7-4518.97" wire $or$ls180.v:4518$1313_Y attribute \src "ls180.v:4564.7-4564.97" wire $or$ls180.v:4564$1329_Y attribute \src "ls180.v:4610.7-4610.97" wire $or$ls180.v:4610$1345_Y attribute \src "ls180.v:4798.45-4798.130" wire $or$ls180.v:4798$1366_Y attribute \src "ls180.v:4798.44-4798.212" wire $or$ls180.v:4798$1369_Y attribute \src "ls180.v:4798.43-4798.294" wire $or$ls180.v:4798$1372_Y attribute \src "ls180.v:4798.42-4798.376" wire $or$ls180.v:4798$1375_Y attribute \src "ls180.v:4799.46-4799.131" wire $or$ls180.v:4799$1378_Y attribute \src "ls180.v:4799.45-4799.213" wire $or$ls180.v:4799$1381_Y attribute \src "ls180.v:4799.44-4799.295" wire $or$ls180.v:4799$1384_Y attribute \src "ls180.v:4799.43-4799.377" wire $or$ls180.v:4799$1387_Y attribute \src "ls180.v:4803.7-4803.39" wire $or$ls180.v:4803$1388_Y attribute \src "ls180.v:5711.8-5711.46" wire $or$ls180.v:5711$1550_Y attribute \src "ls180.v:1925.41-1925.84" wire width 13 $sshl$ls180.v:1925$99_Y attribute \src "ls180.v:2082.41-2082.84" wire width 13 $sshl$ls180.v:2082$129_Y attribute \src "ls180.v:2239.41-2239.84" wire width 13 $sshl$ls180.v:2239$159_Y attribute \src "ls180.v:2396.41-2396.84" wire width 13 $sshl$ls180.v:2396$189_Y attribute \src "ls180.v:1956.58-1956.112" wire width 3 $sub$ls180.v:1956$112_Y attribute \src "ls180.v:2113.58-2113.112" wire width 3 $sub$ls180.v:2113$142_Y attribute \src "ls180.v:2270.58-2270.112" wire width 3 $sub$ls180.v:2270$172_Y attribute \src "ls180.v:2427.58-2427.112" wire width 3 $sub$ls180.v:2427$202_Y attribute \src "ls180.v:2833.33-2833.65" wire width 31 $sub$ls180.v:2833$556_Y attribute \src "ls180.v:2919.26-2919.48" wire width 4 $sub$ls180.v:2919$601_Y attribute \src "ls180.v:2949.26-2949.48" wire width 4 $sub$ls180.v:2949$612_Y attribute \src "ls180.v:4363.26-4363.50" wire width 32 $sub$ls180.v:4363$1265_Y attribute \src "ls180.v:4388.26-4388.51" wire width 10 $sub$ls180.v:4388$1273_Y attribute \src "ls180.v:4394.29-4394.57" wire $sub$ls180.v:4394$1274_Y attribute \src "ls180.v:4405.31-4405.59" wire $sub$ls180.v:4405$1277_Y attribute \src "ls180.v:4469.54-4469.106" wire width 4 $sub$ls180.v:4469$1295_Y attribute \src "ls180.v:4488.41-4488.80" wire width 3 $sub$ls180.v:4488$1299_Y attribute \src "ls180.v:4515.54-4515.106" wire width 4 $sub$ls180.v:4515$1311_Y attribute \src "ls180.v:4534.41-4534.80" wire width 3 $sub$ls180.v:4534$1315_Y attribute \src "ls180.v:4561.54-4561.106" wire width 4 $sub$ls180.v:4561$1327_Y attribute \src "ls180.v:4580.41-4580.80" wire width 3 $sub$ls180.v:4580$1331_Y attribute \src "ls180.v:4607.54-4607.106" wire width 4 $sub$ls180.v:4607$1343_Y attribute \src "ls180.v:4626.41-4626.80" wire width 3 $sub$ls180.v:4626$1347_Y attribute \src "ls180.v:4637.20-4637.38" wire width 5 $sub$ls180.v:4637$1351_Y attribute \src "ls180.v:4644.20-4644.38" wire width 4 $sub$ls180.v:4644$1354_Y attribute \src "ls180.v:4776.28-4776.54" wire $sub$ls180.v:4776$1359_Y attribute \src "ls180.v:4791.28-4791.54" wire width 3 $sub$ls180.v:4791$1362_Y attribute \src "ls180.v:4918.23-4918.44" wire width 5 $sub$ls180.v:4918$1421_Y attribute \src "ls180.v:4940.23-4940.44" wire width 5 $sub$ls180.v:4940$1432_Y attribute \src "ls180.v:5005.26-5005.50" wire width 20 $sub$ls180.v:5005$1437_Y attribute \src "ls180.v:828.6-828.13" wire \ack_cmd attribute \src "ls180.v:830.6-830.15" wire \ack_rdata attribute \src "ls180.v:829.6-829.15" wire \ack_wdata attribute \src "ls180.v:1375.11-1375.23" wire width 2 \array_muxed0 attribute \src "ls180.v:1376.12-1376.24" wire width 13 \array_muxed1 attribute \src "ls180.v:1377.5-1377.17" wire \array_muxed2 attribute \src "ls180.v:1378.5-1378.17" wire \array_muxed3 attribute \src "ls180.v:1379.5-1379.17" wire \array_muxed4 attribute \src "ls180.v:1380.5-1380.17" wire \array_muxed5 attribute \src "ls180.v:1381.5-1381.17" wire \array_muxed6 attribute \src "ls180.v:826.5-826.17" wire \cmd_consumed attribute \src "ls180.v:823.5-823.22" wire \converter_counter attribute \src "ls180.v:1049.5-1049.46" wire \converter_counter_subfragments_next_value attribute \src "ls180.v:1050.5-1050.49" wire \converter_counter_subfragments_next_value_ce attribute \src "ls180.v:825.12-825.27" wire width 32 \converter_dat_r attribute \src "ls180.v:824.6-824.21" wire \converter_reset attribute \src "ls180.v:822.5-822.19" wire \converter_skip attribute \src "ls180.v:252.6-252.18" wire \dfi_p0_act_n attribute \src "ls180.v:243.13-243.27" wire width 13 \dfi_p0_address attribute \src "ls180.v:244.12-244.23" wire width 2 \dfi_p0_bank attribute \src "ls180.v:245.6-245.18" wire \dfi_p0_cas_n attribute \src "ls180.v:249.6-249.16" wire \dfi_p0_cke attribute \src "ls180.v:246.6-246.17" wire \dfi_p0_cs_n attribute \src "ls180.v:250.6-250.16" wire \dfi_p0_odt attribute \src "ls180.v:247.6-247.18" wire \dfi_p0_ras_n attribute \src "ls180.v:257.12-257.25" wire width 16 \dfi_p0_rddata attribute \src "ls180.v:256.6-256.22" wire \dfi_p0_rddata_en attribute \src "ls180.v:258.5-258.24" wire \dfi_p0_rddata_valid attribute \src "ls180.v:251.6-251.20" wire \dfi_p0_reset_n attribute \src "ls180.v:248.6-248.17" wire \dfi_p0_we_n attribute \src "ls180.v:253.13-253.26" wire width 16 \dfi_p0_wrdata attribute \src "ls180.v:254.6-254.22" wire \dfi_p0_wrdata_en attribute \src "ls180.v:255.12-255.30" wire width 2 \dfi_p0_wrdata_mask attribute \src "ls180.v:993.12-993.17" wire width 40 \dummy attribute \src "ls180.v:30.13-30.19" wire input 26 \eint_0 attribute \src "ls180.v:31.13-31.19" wire input 27 \eint_1 attribute \src "ls180.v:32.13-32.19" wire input 28 \eint_2 attribute \src "ls180.v:991.11-991.19" wire width 3 \eint_tmp attribute \src "ls180.v:879.12-879.34" wire width 2 \eventmanager_pending_r attribute \src "ls180.v:878.6-878.29" wire \eventmanager_pending_re attribute \src "ls180.v:881.11-881.33" wire width 2 \eventmanager_pending_w attribute \src "ls180.v:880.6-880.29" wire \eventmanager_pending_we attribute \src "ls180.v:883.5-883.20" wire \eventmanager_re attribute \src "ls180.v:875.12-875.33" wire width 2 \eventmanager_status_r attribute \src "ls180.v:874.6-874.28" wire \eventmanager_status_re attribute \src "ls180.v:877.11-877.32" wire width 2 \eventmanager_status_w attribute \src "ls180.v:876.6-876.28" wire \eventmanager_status_we attribute \src "ls180.v:882.11-882.31" wire width 2 \eventmanager_storage attribute \src "ls180.v:974.5-974.16" wire \gpio0_oe_re attribute \src "ls180.v:973.11-973.27" wire width 8 \gpio0_oe_storage attribute \src "ls180.v:978.5-978.17" wire \gpio0_out_re attribute \src "ls180.v:977.11-977.28" wire width 8 \gpio0_out_storage attribute \src "ls180.v:979.11-979.28" wire width 8 \gpio0_pads_gpio0i attribute \src "ls180.v:980.11-980.28" wire width 8 \gpio0_pads_gpio0o attribute \src "ls180.v:981.11-981.29" wire width 8 \gpio0_pads_gpio0oe attribute \src "ls180.v:975.11-975.23" wire width 8 \gpio0_status attribute \src "ls180.v:976.6-976.14" wire \gpio0_we attribute \src "ls180.v:983.5-983.16" wire \gpio1_oe_re attribute \src "ls180.v:982.11-982.27" wire width 8 \gpio1_oe_storage attribute \src "ls180.v:987.5-987.17" wire \gpio1_out_re attribute \src "ls180.v:986.11-986.28" wire width 8 \gpio1_out_storage attribute \src "ls180.v:988.11-988.28" wire width 8 \gpio1_pads_gpio1i attribute \src "ls180.v:989.11-989.28" wire width 8 \gpio1_pads_gpio1o attribute \src "ls180.v:990.11-990.29" wire width 8 \gpio1_pads_gpio1oe attribute \src "ls180.v:984.11-984.23" wire width 8 \gpio1_status attribute \src "ls180.v:985.6-985.14" wire \gpio1_we attribute \src "ls180.v:25.20-25.26" wire width 16 input 21 \gpio_i attribute \src "ls180.v:26.21-26.27" wire width 16 output 22 \gpio_o attribute \src "ls180.v:27.21-27.28" wire width 16 output 23 \gpio_oe attribute \src "ls180.v:995.6-995.12" wire \i2c_oe attribute \src "ls180.v:998.5-998.11" wire \i2c_re attribute \src "ls180.v:21.14-21.21" wire output 17 \i2c_scl attribute \src "ls180.v:994.6-994.15" wire \i2c_scl_1 attribute \src "ls180.v:996.6-996.14" wire \i2c_sda0 attribute \src "ls180.v:999.6-999.14" wire \i2c_sda1 attribute \src "ls180.v:22.13-22.22" wire input 18 \i2c_sda_i attribute \src "ls180.v:23.14-23.23" wire output 19 \i2c_sda_o attribute \src "ls180.v:24.14-24.24" wire output 20 \i2c_sda_oe attribute \src "ls180.v:1000.6-1000.16" wire \i2c_status attribute \src "ls180.v:997.11-997.22" wire width 3 \i2c_storage attribute \src "ls180.v:1001.6-1001.12" wire \i2c_we attribute \src "ls180.v:242.5-242.12" wire \int_rst attribute \src "ls180.v:863.6-863.9" wire \irq attribute \src "ls180.v:36.13-36.21" wire input 32 \jtag_tck attribute \src "ls180.v:37.13-37.21" wire input 33 \jtag_tdi attribute \src "ls180.v:38.14-38.22" wire output 34 \jtag_tdo attribute \src "ls180.v:35.13-35.21" wire input 31 \jtag_tms attribute \src "ls180.v:193.12-193.27" wire width 7 \libresocsim_adr attribute \src "ls180.v:49.6-49.27" wire \libresocsim_bus_error attribute \src "ls180.v:50.12-50.34" wire width 32 \libresocsim_bus_errors attribute \src "ls180.v:46.13-46.42" wire width 32 \libresocsim_bus_errors_status attribute \src "ls180.v:47.6-47.31" wire \libresocsim_bus_errors_we attribute \src "ls180.v:149.5-149.35" wire \libresocsim_converter0_counter attribute \src "ls180.v:1004.5-1004.70" wire \libresocsim_converter0_counter_subfragments_converter0_next_value attribute \src "ls180.v:1005.5-1005.73" wire \libresocsim_converter0_counter_subfragments_converter0_next_value_ce attribute \src "ls180.v:151.12-151.40" wire width 64 \libresocsim_converter0_dat_r attribute \src "ls180.v:150.6-150.34" wire \libresocsim_converter0_reset attribute \src "ls180.v:148.5-148.32" wire \libresocsim_converter0_skip attribute \src "ls180.v:164.5-164.35" wire \libresocsim_converter1_counter attribute \src "ls180.v:1008.5-1008.70" wire \libresocsim_converter1_counter_subfragments_converter1_next_value attribute \src "ls180.v:1009.5-1009.73" wire \libresocsim_converter1_counter_subfragments_converter1_next_value_ce attribute \src "ls180.v:166.12-166.40" wire width 64 \libresocsim_converter1_dat_r attribute \src "ls180.v:165.6-165.34" wire \libresocsim_converter1_reset attribute \src "ls180.v:163.5-163.32" wire \libresocsim_converter1_skip attribute \src "ls180.v:179.5-179.35" wire \libresocsim_converter2_counter attribute \src "ls180.v:1012.5-1012.70" wire \libresocsim_converter2_counter_subfragments_converter2_next_value attribute \src "ls180.v:1013.5-1013.73" wire \libresocsim_converter2_counter_subfragments_converter2_next_value_ce attribute \src "ls180.v:181.12-181.40" wire width 64 \libresocsim_converter2_dat_r attribute \src "ls180.v:180.6-180.34" wire \libresocsim_converter2_reset attribute \src "ls180.v:178.5-178.32" wire \libresocsim_converter2_skip attribute \src "ls180.v:1084.12-1084.29" wire width 20 \libresocsim_count attribute \src "ls180.v:1325.13-1325.45" wire width 14 \libresocsim_csr_interconnect_adr attribute \src "ls180.v:1328.12-1328.46" wire width 8 \libresocsim_csr_interconnect_dat_r attribute \src "ls180.v:1327.12-1327.46" wire width 8 \libresocsim_csr_interconnect_dat_w attribute \src "ls180.v:1326.6-1326.37" wire \libresocsim_csr_interconnect_we attribute \src "ls180.v:1122.12-1122.46" wire width 8 \libresocsim_csrbank0_bus_errors0_r attribute \src "ls180.v:1121.6-1121.41" wire \libresocsim_csrbank0_bus_errors0_re attribute \src "ls180.v:1124.12-1124.46" wire width 8 \libresocsim_csrbank0_bus_errors0_w attribute \src "ls180.v:1123.6-1123.41" wire \libresocsim_csrbank0_bus_errors0_we attribute \src "ls180.v:1118.12-1118.46" wire width 8 \libresocsim_csrbank0_bus_errors1_r attribute \src "ls180.v:1117.6-1117.41" wire \libresocsim_csrbank0_bus_errors1_re attribute \src "ls180.v:1120.12-1120.46" wire width 8 \libresocsim_csrbank0_bus_errors1_w attribute \src "ls180.v:1119.6-1119.41" wire \libresocsim_csrbank0_bus_errors1_we attribute \src "ls180.v:1114.12-1114.46" wire width 8 \libresocsim_csrbank0_bus_errors2_r attribute \src "ls180.v:1113.6-1113.41" wire \libresocsim_csrbank0_bus_errors2_re attribute \src "ls180.v:1116.12-1116.46" wire width 8 \libresocsim_csrbank0_bus_errors2_w attribute \src "ls180.v:1115.6-1115.41" wire \libresocsim_csrbank0_bus_errors2_we attribute \src "ls180.v:1110.12-1110.46" wire width 8 \libresocsim_csrbank0_bus_errors3_r attribute \src "ls180.v:1109.6-1109.41" wire \libresocsim_csrbank0_bus_errors3_re attribute \src "ls180.v:1112.12-1112.46" wire width 8 \libresocsim_csrbank0_bus_errors3_w attribute \src "ls180.v:1111.6-1111.41" wire \libresocsim_csrbank0_bus_errors3_we attribute \src "ls180.v:1090.6-1090.35" wire \libresocsim_csrbank0_reset0_r attribute \src "ls180.v:1089.6-1089.36" wire \libresocsim_csrbank0_reset0_re attribute \src "ls180.v:1092.6-1092.35" wire \libresocsim_csrbank0_reset0_w attribute \src "ls180.v:1091.6-1091.36" wire \libresocsim_csrbank0_reset0_we attribute \src "ls180.v:1106.12-1106.43" wire width 8 \libresocsim_csrbank0_scratch0_r attribute \src "ls180.v:1105.6-1105.38" wire \libresocsim_csrbank0_scratch0_re attribute \src "ls180.v:1108.12-1108.43" wire width 8 \libresocsim_csrbank0_scratch0_w attribute \src "ls180.v:1107.6-1107.38" wire \libresocsim_csrbank0_scratch0_we attribute \src "ls180.v:1102.12-1102.43" wire width 8 \libresocsim_csrbank0_scratch1_r attribute \src "ls180.v:1101.6-1101.38" wire \libresocsim_csrbank0_scratch1_re attribute \src "ls180.v:1104.12-1104.43" wire width 8 \libresocsim_csrbank0_scratch1_w attribute \src "ls180.v:1103.6-1103.38" wire \libresocsim_csrbank0_scratch1_we attribute \src "ls180.v:1098.12-1098.43" wire width 8 \libresocsim_csrbank0_scratch2_r attribute \src "ls180.v:1097.6-1097.38" wire \libresocsim_csrbank0_scratch2_re attribute \src "ls180.v:1100.12-1100.43" wire width 8 \libresocsim_csrbank0_scratch2_w attribute \src "ls180.v:1099.6-1099.38" wire \libresocsim_csrbank0_scratch2_we attribute \src "ls180.v:1094.12-1094.43" wire width 8 \libresocsim_csrbank0_scratch3_r attribute \src "ls180.v:1093.6-1093.38" wire \libresocsim_csrbank0_scratch3_re attribute \src "ls180.v:1096.12-1096.43" wire width 8 \libresocsim_csrbank0_scratch3_w attribute \src "ls180.v:1095.6-1095.38" wire \libresocsim_csrbank0_scratch3_we attribute \src "ls180.v:1125.6-1125.30" wire \libresocsim_csrbank0_sel attribute \src "ls180.v:1135.12-1135.37" wire width 8 \libresocsim_csrbank1_in_r attribute \src "ls180.v:1134.6-1134.32" wire \libresocsim_csrbank1_in_re attribute \src "ls180.v:1137.12-1137.37" wire width 8 \libresocsim_csrbank1_in_w attribute \src "ls180.v:1136.6-1136.32" wire \libresocsim_csrbank1_in_we attribute \src "ls180.v:1131.12-1131.38" wire width 8 \libresocsim_csrbank1_oe0_r attribute \src "ls180.v:1130.6-1130.33" wire \libresocsim_csrbank1_oe0_re attribute \src "ls180.v:1133.12-1133.38" wire width 8 \libresocsim_csrbank1_oe0_w attribute \src "ls180.v:1132.6-1132.33" wire \libresocsim_csrbank1_oe0_we attribute \src "ls180.v:1139.12-1139.39" wire width 8 \libresocsim_csrbank1_out0_r attribute \src "ls180.v:1138.6-1138.34" wire \libresocsim_csrbank1_out0_re attribute \src "ls180.v:1141.12-1141.39" wire width 8 \libresocsim_csrbank1_out0_w attribute \src "ls180.v:1140.6-1140.34" wire \libresocsim_csrbank1_out0_we attribute \src "ls180.v:1142.6-1142.30" wire \libresocsim_csrbank1_sel attribute \src "ls180.v:1152.12-1152.37" wire width 8 \libresocsim_csrbank2_in_r attribute \src "ls180.v:1151.6-1151.32" wire \libresocsim_csrbank2_in_re attribute \src "ls180.v:1154.12-1154.37" wire width 8 \libresocsim_csrbank2_in_w attribute \src "ls180.v:1153.6-1153.32" wire \libresocsim_csrbank2_in_we attribute \src "ls180.v:1148.12-1148.38" wire width 8 \libresocsim_csrbank2_oe0_r attribute \src "ls180.v:1147.6-1147.33" wire \libresocsim_csrbank2_oe0_re attribute \src "ls180.v:1150.12-1150.38" wire width 8 \libresocsim_csrbank2_oe0_w attribute \src "ls180.v:1149.6-1149.33" wire \libresocsim_csrbank2_oe0_we attribute \src "ls180.v:1156.12-1156.39" wire width 8 \libresocsim_csrbank2_out0_r attribute \src "ls180.v:1155.6-1155.34" wire \libresocsim_csrbank2_out0_re attribute \src "ls180.v:1158.12-1158.39" wire width 8 \libresocsim_csrbank2_out0_w attribute \src "ls180.v:1157.6-1157.34" wire \libresocsim_csrbank2_out0_we attribute \src "ls180.v:1159.6-1159.30" wire \libresocsim_csrbank2_sel attribute \src "ls180.v:1169.6-1169.30" wire \libresocsim_csrbank3_r_r attribute \src "ls180.v:1168.6-1168.31" wire \libresocsim_csrbank3_r_re attribute \src "ls180.v:1171.6-1171.30" wire \libresocsim_csrbank3_r_w attribute \src "ls180.v:1170.6-1170.31" wire \libresocsim_csrbank3_r_we attribute \src "ls180.v:1172.6-1172.30" wire \libresocsim_csrbank3_sel attribute \src "ls180.v:1165.12-1165.37" wire width 3 \libresocsim_csrbank3_w0_r attribute \src "ls180.v:1164.6-1164.32" wire \libresocsim_csrbank3_w0_re attribute \src "ls180.v:1167.12-1167.37" wire width 3 \libresocsim_csrbank3_w0_w attribute \src "ls180.v:1166.6-1166.32" wire \libresocsim_csrbank3_w0_we attribute \src "ls180.v:1178.12-1178.48" wire width 4 \libresocsim_csrbank4_dfii_control0_r attribute \src "ls180.v:1177.6-1177.43" wire \libresocsim_csrbank4_dfii_control0_re attribute \src "ls180.v:1180.12-1180.48" wire width 4 \libresocsim_csrbank4_dfii_control0_w attribute \src "ls180.v:1179.6-1179.43" wire \libresocsim_csrbank4_dfii_control0_we attribute \src "ls180.v:1190.12-1190.52" wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_r attribute \src "ls180.v:1189.6-1189.47" wire \libresocsim_csrbank4_dfii_pi0_address0_re attribute \src "ls180.v:1192.12-1192.52" wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_w attribute \src "ls180.v:1191.6-1191.47" wire \libresocsim_csrbank4_dfii_pi0_address0_we attribute \src "ls180.v:1186.12-1186.52" wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_r attribute \src "ls180.v:1185.6-1185.47" wire \libresocsim_csrbank4_dfii_pi0_address1_re attribute \src "ls180.v:1188.12-1188.52" wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_w attribute \src "ls180.v:1187.6-1187.47" wire \libresocsim_csrbank4_dfii_pi0_address1_we attribute \src "ls180.v:1194.12-1194.53" wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_r attribute \src "ls180.v:1193.6-1193.48" wire \libresocsim_csrbank4_dfii_pi0_baddress0_re attribute \src "ls180.v:1196.12-1196.53" wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_w attribute \src "ls180.v:1195.6-1195.48" wire \libresocsim_csrbank4_dfii_pi0_baddress0_we attribute \src "ls180.v:1182.12-1182.52" wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_r attribute \src "ls180.v:1181.6-1181.47" wire \libresocsim_csrbank4_dfii_pi0_command0_re attribute \src "ls180.v:1184.12-1184.52" wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_w attribute \src "ls180.v:1183.6-1183.47" wire \libresocsim_csrbank4_dfii_pi0_command0_we attribute \src "ls180.v:1210.12-1210.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_r attribute \src "ls180.v:1209.6-1209.46" wire \libresocsim_csrbank4_dfii_pi0_rddata0_re attribute \src "ls180.v:1212.12-1212.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_w attribute \src "ls180.v:1211.6-1211.46" wire \libresocsim_csrbank4_dfii_pi0_rddata0_we attribute \src "ls180.v:1206.12-1206.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_r attribute \src "ls180.v:1205.6-1205.46" wire \libresocsim_csrbank4_dfii_pi0_rddata1_re attribute \src "ls180.v:1208.12-1208.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_w attribute \src "ls180.v:1207.6-1207.46" wire \libresocsim_csrbank4_dfii_pi0_rddata1_we attribute \src "ls180.v:1202.12-1202.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_r attribute \src "ls180.v:1201.6-1201.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata0_re attribute \src "ls180.v:1204.12-1204.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_w attribute \src "ls180.v:1203.6-1203.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata0_we attribute \src "ls180.v:1198.12-1198.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_r attribute \src "ls180.v:1197.6-1197.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata1_re attribute \src "ls180.v:1200.12-1200.51" wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_w attribute \src "ls180.v:1199.6-1199.46" wire \libresocsim_csrbank4_dfii_pi0_wrdata1_we attribute \src "ls180.v:1213.6-1213.30" wire \libresocsim_csrbank4_sel attribute \src "ls180.v:1251.6-1251.32" wire \libresocsim_csrbank5_en0_r attribute \src "ls180.v:1250.6-1250.33" wire \libresocsim_csrbank5_en0_re attribute \src "ls180.v:1253.6-1253.32" wire \libresocsim_csrbank5_en0_w attribute \src "ls180.v:1252.6-1252.33" wire \libresocsim_csrbank5_en0_we attribute \src "ls180.v:1275.6-1275.39" wire \libresocsim_csrbank5_ev_enable0_r attribute \src "ls180.v:1274.6-1274.40" wire \libresocsim_csrbank5_ev_enable0_re attribute \src "ls180.v:1277.6-1277.39" wire \libresocsim_csrbank5_ev_enable0_w attribute \src "ls180.v:1276.6-1276.40" wire \libresocsim_csrbank5_ev_enable0_we attribute \src "ls180.v:1231.12-1231.40" wire width 8 \libresocsim_csrbank5_load0_r attribute \src "ls180.v:1230.6-1230.35" wire \libresocsim_csrbank5_load0_re attribute \src "ls180.v:1233.12-1233.40" wire width 8 \libresocsim_csrbank5_load0_w attribute \src "ls180.v:1232.6-1232.35" wire \libresocsim_csrbank5_load0_we attribute \src "ls180.v:1227.12-1227.40" wire width 8 \libresocsim_csrbank5_load1_r attribute \src "ls180.v:1226.6-1226.35" wire \libresocsim_csrbank5_load1_re attribute \src "ls180.v:1229.12-1229.40" wire width 8 \libresocsim_csrbank5_load1_w attribute \src "ls180.v:1228.6-1228.35" wire \libresocsim_csrbank5_load1_we attribute \src "ls180.v:1223.12-1223.40" wire width 8 \libresocsim_csrbank5_load2_r attribute \src "ls180.v:1222.6-1222.35" wire \libresocsim_csrbank5_load2_re attribute \src "ls180.v:1225.12-1225.40" wire width 8 \libresocsim_csrbank5_load2_w attribute \src "ls180.v:1224.6-1224.35" wire \libresocsim_csrbank5_load2_we attribute \src "ls180.v:1219.12-1219.40" wire width 8 \libresocsim_csrbank5_load3_r attribute \src "ls180.v:1218.6-1218.35" wire \libresocsim_csrbank5_load3_re attribute \src "ls180.v:1221.12-1221.40" wire width 8 \libresocsim_csrbank5_load3_w attribute \src "ls180.v:1220.6-1220.35" wire \libresocsim_csrbank5_load3_we attribute \src "ls180.v:1247.12-1247.42" wire width 8 \libresocsim_csrbank5_reload0_r attribute \src "ls180.v:1246.6-1246.37" wire \libresocsim_csrbank5_reload0_re attribute \src "ls180.v:1249.12-1249.42" wire width 8 \libresocsim_csrbank5_reload0_w attribute \src "ls180.v:1248.6-1248.37" wire \libresocsim_csrbank5_reload0_we attribute \src "ls180.v:1243.12-1243.42" wire width 8 \libresocsim_csrbank5_reload1_r attribute \src "ls180.v:1242.6-1242.37" wire \libresocsim_csrbank5_reload1_re attribute \src "ls180.v:1245.12-1245.42" wire width 8 \libresocsim_csrbank5_reload1_w attribute \src "ls180.v:1244.6-1244.37" wire \libresocsim_csrbank5_reload1_we attribute \src "ls180.v:1239.12-1239.42" wire width 8 \libresocsim_csrbank5_reload2_r attribute \src "ls180.v:1238.6-1238.37" wire \libresocsim_csrbank5_reload2_re attribute \src "ls180.v:1241.12-1241.42" wire width 8 \libresocsim_csrbank5_reload2_w attribute \src "ls180.v:1240.6-1240.37" wire \libresocsim_csrbank5_reload2_we attribute \src "ls180.v:1235.12-1235.42" wire width 8 \libresocsim_csrbank5_reload3_r attribute \src "ls180.v:1234.6-1234.37" wire \libresocsim_csrbank5_reload3_re attribute \src "ls180.v:1237.12-1237.42" wire width 8 \libresocsim_csrbank5_reload3_w attribute \src "ls180.v:1236.6-1236.37" wire \libresocsim_csrbank5_reload3_we attribute \src "ls180.v:1278.6-1278.30" wire \libresocsim_csrbank5_sel attribute \src "ls180.v:1255.6-1255.42" wire \libresocsim_csrbank5_update_value0_r attribute \src "ls180.v:1254.6-1254.43" wire \libresocsim_csrbank5_update_value0_re attribute \src "ls180.v:1257.6-1257.42" wire \libresocsim_csrbank5_update_value0_w attribute \src "ls180.v:1256.6-1256.43" wire \libresocsim_csrbank5_update_value0_we attribute \src "ls180.v:1271.12-1271.41" wire width 8 \libresocsim_csrbank5_value0_r attribute \src "ls180.v:1270.6-1270.36" wire \libresocsim_csrbank5_value0_re attribute \src "ls180.v:1273.12-1273.41" wire width 8 \libresocsim_csrbank5_value0_w attribute \src "ls180.v:1272.6-1272.36" wire \libresocsim_csrbank5_value0_we attribute \src "ls180.v:1267.12-1267.41" wire width 8 \libresocsim_csrbank5_value1_r attribute \src "ls180.v:1266.6-1266.36" wire \libresocsim_csrbank5_value1_re attribute \src "ls180.v:1269.12-1269.41" wire width 8 \libresocsim_csrbank5_value1_w attribute \src "ls180.v:1268.6-1268.36" wire \libresocsim_csrbank5_value1_we attribute \src "ls180.v:1263.12-1263.41" wire width 8 \libresocsim_csrbank5_value2_r attribute \src "ls180.v:1262.6-1262.36" wire \libresocsim_csrbank5_value2_re attribute \src "ls180.v:1265.12-1265.41" wire width 8 \libresocsim_csrbank5_value2_w attribute \src "ls180.v:1264.6-1264.36" wire \libresocsim_csrbank5_value2_we attribute \src "ls180.v:1259.12-1259.41" wire width 8 \libresocsim_csrbank5_value3_r attribute \src "ls180.v:1258.6-1258.36" wire \libresocsim_csrbank5_value3_re attribute \src "ls180.v:1261.12-1261.41" wire width 8 \libresocsim_csrbank5_value3_w attribute \src "ls180.v:1260.6-1260.36" wire \libresocsim_csrbank5_value3_we attribute \src "ls180.v:1292.12-1292.45" wire width 2 \libresocsim_csrbank6_ev_enable0_r attribute \src "ls180.v:1291.6-1291.40" wire \libresocsim_csrbank6_ev_enable0_re attribute \src "ls180.v:1294.12-1294.45" wire width 2 \libresocsim_csrbank6_ev_enable0_w attribute \src "ls180.v:1293.6-1293.40" wire \libresocsim_csrbank6_ev_enable0_we attribute \src "ls180.v:1288.6-1288.36" wire \libresocsim_csrbank6_rxempty_r attribute \src "ls180.v:1287.6-1287.37" wire \libresocsim_csrbank6_rxempty_re attribute \src "ls180.v:1290.6-1290.36" wire \libresocsim_csrbank6_rxempty_w attribute \src "ls180.v:1289.6-1289.37" wire \libresocsim_csrbank6_rxempty_we attribute \src "ls180.v:1300.6-1300.35" wire \libresocsim_csrbank6_rxfull_r attribute \src "ls180.v:1299.6-1299.36" wire \libresocsim_csrbank6_rxfull_re attribute \src "ls180.v:1302.6-1302.35" wire \libresocsim_csrbank6_rxfull_w attribute \src "ls180.v:1301.6-1301.36" wire \libresocsim_csrbank6_rxfull_we attribute \src "ls180.v:1303.6-1303.30" wire \libresocsim_csrbank6_sel attribute \src "ls180.v:1296.6-1296.36" wire \libresocsim_csrbank6_txempty_r attribute \src "ls180.v:1295.6-1295.37" wire \libresocsim_csrbank6_txempty_re attribute \src "ls180.v:1298.6-1298.36" wire \libresocsim_csrbank6_txempty_w attribute \src "ls180.v:1297.6-1297.37" wire \libresocsim_csrbank6_txempty_we attribute \src "ls180.v:1284.6-1284.35" wire \libresocsim_csrbank6_txfull_r attribute \src "ls180.v:1283.6-1283.36" wire \libresocsim_csrbank6_txfull_re attribute \src "ls180.v:1286.6-1286.35" wire \libresocsim_csrbank6_txfull_w attribute \src "ls180.v:1285.6-1285.36" wire \libresocsim_csrbank6_txfull_we attribute \src "ls180.v:1324.6-1324.30" wire \libresocsim_csrbank7_sel attribute \src "ls180.v:1321.12-1321.47" wire width 8 \libresocsim_csrbank7_tuning_word0_r attribute \src "ls180.v:1320.6-1320.42" wire \libresocsim_csrbank7_tuning_word0_re attribute \src "ls180.v:1323.12-1323.47" wire width 8 \libresocsim_csrbank7_tuning_word0_w attribute \src "ls180.v:1322.6-1322.42" wire \libresocsim_csrbank7_tuning_word0_we attribute \src "ls180.v:1317.12-1317.47" wire width 8 \libresocsim_csrbank7_tuning_word1_r attribute \src "ls180.v:1316.6-1316.42" wire \libresocsim_csrbank7_tuning_word1_re attribute \src "ls180.v:1319.12-1319.47" wire width 8 \libresocsim_csrbank7_tuning_word1_w attribute \src "ls180.v:1318.6-1318.42" wire \libresocsim_csrbank7_tuning_word1_we attribute \src "ls180.v:1313.12-1313.47" wire width 8 \libresocsim_csrbank7_tuning_word2_r attribute \src "ls180.v:1312.6-1312.42" wire \libresocsim_csrbank7_tuning_word2_re attribute \src "ls180.v:1315.12-1315.47" wire width 8 \libresocsim_csrbank7_tuning_word2_w attribute \src "ls180.v:1314.6-1314.42" wire \libresocsim_csrbank7_tuning_word2_we attribute \src "ls180.v:1309.12-1309.47" wire width 8 \libresocsim_csrbank7_tuning_word3_r attribute \src "ls180.v:1308.6-1308.42" wire \libresocsim_csrbank7_tuning_word3_re attribute \src "ls180.v:1311.12-1311.47" wire width 8 \libresocsim_csrbank7_tuning_word3_w attribute \src "ls180.v:1310.6-1310.42" wire \libresocsim_csrbank7_tuning_word3_we attribute \src "ls180.v:194.13-194.30" wire width 32 \libresocsim_dat_r attribute \src "ls180.v:196.13-196.30" wire width 32 \libresocsim_dat_w attribute \src "ls180.v:1083.6-1083.22" wire \libresocsim_done attribute \src "ls180.v:202.5-202.22" wire \libresocsim_en_re attribute \src "ls180.v:201.5-201.27" wire \libresocsim_en_storage attribute \src "ls180.v:1081.5-1081.22" wire \libresocsim_error attribute \src "ls180.v:218.6-218.40" wire \libresocsim_eventmanager_pending_r attribute \src "ls180.v:217.6-217.41" wire \libresocsim_eventmanager_pending_re attribute \src "ls180.v:220.6-220.40" wire \libresocsim_eventmanager_pending_w attribute \src "ls180.v:219.6-219.41" wire \libresocsim_eventmanager_pending_we attribute \src "ls180.v:222.5-222.32" wire \libresocsim_eventmanager_re attribute \src "ls180.v:214.6-214.39" wire \libresocsim_eventmanager_status_r attribute \src "ls180.v:213.6-213.40" wire \libresocsim_eventmanager_status_re attribute \src "ls180.v:216.6-216.39" wire \libresocsim_eventmanager_status_w attribute \src "ls180.v:215.6-215.40" wire \libresocsim_eventmanager_status_we attribute \src "ls180.v:221.5-221.37" wire \libresocsim_eventmanager_storage attribute \src "ls180.v:1078.11-1078.28" wire width 2 \libresocsim_grant attribute \src "ls180.v:1085.13-1085.48" wire width 14 \libresocsim_interface0_bank_bus_adr attribute \src "ls180.v:1088.11-1088.48" wire width 8 \libresocsim_interface0_bank_bus_dat_r attribute \src "ls180.v:1087.12-1087.49" wire width 8 \libresocsim_interface0_bank_bus_dat_w attribute \src "ls180.v:1086.6-1086.40" wire \libresocsim_interface0_bank_bus_we attribute \src "ls180.v:143.6-143.52" wire \libresocsim_interface0_converted_interface_ack attribute \src "ls180.v:137.12-137.58" wire width 30 \libresocsim_interface0_converted_interface_adr attribute \src "ls180.v:146.11-146.57" wire width 2 \libresocsim_interface0_converted_interface_bte attribute \src "ls180.v:145.11-145.57" wire width 3 \libresocsim_interface0_converted_interface_cti attribute \src "ls180.v:141.5-141.51" wire \libresocsim_interface0_converted_interface_cyc attribute \src "ls180.v:139.13-139.61" wire width 32 \libresocsim_interface0_converted_interface_dat_r attribute \src "ls180.v:138.12-138.60" wire width 32 \libresocsim_interface0_converted_interface_dat_w attribute \src "ls180.v:147.6-147.52" wire \libresocsim_interface0_converted_interface_err attribute \src "ls180.v:140.11-140.57" wire width 4 \libresocsim_interface0_converted_interface_sel attribute \src "ls180.v:142.5-142.51" wire \libresocsim_interface0_converted_interface_stb attribute \src "ls180.v:144.5-144.50" wire \libresocsim_interface0_converted_interface_we attribute \src "ls180.v:1126.13-1126.48" wire width 14 \libresocsim_interface1_bank_bus_adr attribute \src "ls180.v:1129.11-1129.48" wire width 8 \libresocsim_interface1_bank_bus_dat_r attribute \src "ls180.v:1128.12-1128.49" wire width 8 \libresocsim_interface1_bank_bus_dat_w attribute \src "ls180.v:1127.6-1127.40" wire \libresocsim_interface1_bank_bus_we attribute \src "ls180.v:158.6-158.52" wire \libresocsim_interface1_converted_interface_ack attribute \src "ls180.v:152.12-152.58" wire width 30 \libresocsim_interface1_converted_interface_adr attribute \src "ls180.v:161.11-161.57" wire width 2 \libresocsim_interface1_converted_interface_bte attribute \src "ls180.v:160.11-160.57" wire width 3 \libresocsim_interface1_converted_interface_cti attribute \src "ls180.v:156.5-156.51" wire \libresocsim_interface1_converted_interface_cyc attribute \src "ls180.v:154.13-154.61" wire width 32 \libresocsim_interface1_converted_interface_dat_r attribute \src "ls180.v:153.12-153.60" wire width 32 \libresocsim_interface1_converted_interface_dat_w attribute \src "ls180.v:162.6-162.52" wire \libresocsim_interface1_converted_interface_err attribute \src "ls180.v:155.11-155.57" wire width 4 \libresocsim_interface1_converted_interface_sel attribute \src "ls180.v:157.5-157.51" wire \libresocsim_interface1_converted_interface_stb attribute \src "ls180.v:159.5-159.50" wire \libresocsim_interface1_converted_interface_we attribute \src "ls180.v:1143.13-1143.48" wire width 14 \libresocsim_interface2_bank_bus_adr attribute \src "ls180.v:1146.11-1146.48" wire width 8 \libresocsim_interface2_bank_bus_dat_r attribute \src "ls180.v:1145.12-1145.49" wire width 8 \libresocsim_interface2_bank_bus_dat_w attribute \src "ls180.v:1144.6-1144.40" wire \libresocsim_interface2_bank_bus_we attribute \src "ls180.v:173.6-173.52" wire \libresocsim_interface2_converted_interface_ack attribute \src "ls180.v:167.12-167.58" wire width 30 \libresocsim_interface2_converted_interface_adr attribute \src "ls180.v:176.11-176.57" wire width 2 \libresocsim_interface2_converted_interface_bte attribute \src "ls180.v:175.11-175.57" wire width 3 \libresocsim_interface2_converted_interface_cti attribute \src "ls180.v:171.5-171.51" wire \libresocsim_interface2_converted_interface_cyc attribute \src "ls180.v:169.13-169.61" wire width 32 \libresocsim_interface2_converted_interface_dat_r attribute \src "ls180.v:168.12-168.60" wire width 32 \libresocsim_interface2_converted_interface_dat_w attribute \src "ls180.v:177.6-177.52" wire \libresocsim_interface2_converted_interface_err attribute \src "ls180.v:170.11-170.57" wire width 4 \libresocsim_interface2_converted_interface_sel attribute \src "ls180.v:172.5-172.51" wire \libresocsim_interface2_converted_interface_stb attribute \src "ls180.v:174.5-174.50" wire \libresocsim_interface2_converted_interface_we attribute \src "ls180.v:1160.13-1160.48" wire width 14 \libresocsim_interface3_bank_bus_adr attribute \src "ls180.v:1163.11-1163.48" wire width 8 \libresocsim_interface3_bank_bus_dat_r attribute \src "ls180.v:1162.12-1162.49" wire width 8 \libresocsim_interface3_bank_bus_dat_w attribute \src "ls180.v:1161.6-1161.40" wire \libresocsim_interface3_bank_bus_we attribute \src "ls180.v:1173.13-1173.48" wire width 14 \libresocsim_interface4_bank_bus_adr attribute \src "ls180.v:1176.11-1176.48" wire width 8 \libresocsim_interface4_bank_bus_dat_r attribute \src "ls180.v:1175.12-1175.49" wire width 8 \libresocsim_interface4_bank_bus_dat_w attribute \src "ls180.v:1174.6-1174.40" wire \libresocsim_interface4_bank_bus_we attribute \src "ls180.v:1214.13-1214.48" wire width 14 \libresocsim_interface5_bank_bus_adr attribute \src "ls180.v:1217.11-1217.48" wire width 8 \libresocsim_interface5_bank_bus_dat_r attribute \src "ls180.v:1216.12-1216.49" wire width 8 \libresocsim_interface5_bank_bus_dat_w attribute \src "ls180.v:1215.6-1215.40" wire \libresocsim_interface5_bank_bus_we attribute \src "ls180.v:1279.13-1279.48" wire width 14 \libresocsim_interface6_bank_bus_adr attribute \src "ls180.v:1282.11-1282.48" wire width 8 \libresocsim_interface6_bank_bus_dat_r attribute \src "ls180.v:1281.12-1281.49" wire width 8 \libresocsim_interface6_bank_bus_dat_w attribute \src "ls180.v:1280.6-1280.40" wire \libresocsim_interface6_bank_bus_we attribute \src "ls180.v:1304.13-1304.48" wire width 14 \libresocsim_interface7_bank_bus_adr attribute \src "ls180.v:1307.11-1307.48" wire width 8 \libresocsim_interface7_bank_bus_dat_r attribute \src "ls180.v:1306.12-1306.49" wire width 8 \libresocsim_interface7_bank_bus_dat_w attribute \src "ls180.v:1305.6-1305.40" wire \libresocsim_interface7_bank_bus_we attribute \src "ls180.v:207.6-207.21" wire \libresocsim_irq attribute \src "ls180.v:106.6-106.27" wire \libresocsim_libresoc0 attribute \src "ls180.v:107.6-107.27" wire \libresocsim_libresoc1 attribute \src "ls180.v:108.13-108.34" wire width 64 \libresocsim_libresoc2 attribute \src "ls180.v:134.6-134.51" wire \libresocsim_libresoc_constraintmanager_eint_0 attribute \src "ls180.v:135.6-135.51" wire \libresocsim_libresoc_constraintmanager_eint_1 attribute \src "ls180.v:136.6-136.51" wire \libresocsim_libresoc_constraintmanager_eint_2 attribute \src "ls180.v:129.13-129.58" wire width 16 \libresocsim_libresoc_constraintmanager_gpio_i attribute \src "ls180.v:130.12-130.57" wire width 16 \libresocsim_libresoc_constraintmanager_gpio_o attribute \src "ls180.v:131.12-131.58" wire width 16 \libresocsim_libresoc_constraintmanager_gpio_oe attribute \src "ls180.v:125.6-125.52" wire \libresocsim_libresoc_constraintmanager_i2c_scl attribute \src "ls180.v:126.6-126.54" wire \libresocsim_libresoc_constraintmanager_i2c_sda_i attribute \src "ls180.v:127.6-127.54" wire \libresocsim_libresoc_constraintmanager_i2c_sda_o attribute \src "ls180.v:128.6-128.55" wire \libresocsim_libresoc_constraintmanager_i2c_sda_oe attribute \src "ls180.v:109.12-109.58" wire width 13 \libresocsim_libresoc_constraintmanager_sdram_a attribute \src "ls180.v:118.11-118.58" wire width 2 \libresocsim_libresoc_constraintmanager_sdram_ba attribute \src "ls180.v:115.5-115.55" wire \libresocsim_libresoc_constraintmanager_sdram_cas_n attribute \src "ls180.v:117.5-117.53" wire \libresocsim_libresoc_constraintmanager_sdram_cke attribute \src "ls180.v:120.5-120.55" wire \libresocsim_libresoc_constraintmanager_sdram_clock attribute \src "ls180.v:116.5-116.54" wire \libresocsim_libresoc_constraintmanager_sdram_cs_n attribute \src "ls180.v:119.11-119.58" wire width 2 \libresocsim_libresoc_constraintmanager_sdram_dm attribute \src "ls180.v:110.13-110.62" wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_i attribute \src "ls180.v:111.12-111.61" wire width 16 \libresocsim_libresoc_constraintmanager_sdram_dq_o attribute \src "ls180.v:112.5-112.55" wire \libresocsim_libresoc_constraintmanager_sdram_dq_oe attribute \src "ls180.v:114.5-114.55" wire \libresocsim_libresoc_constraintmanager_sdram_ras_n attribute \src "ls180.v:113.5-113.54" wire \libresocsim_libresoc_constraintmanager_sdram_we_n attribute \src "ls180.v:121.5-121.57" wire \libresocsim_libresoc_constraintmanager_spimaster_clk attribute \src "ls180.v:123.5-123.58" wire \libresocsim_libresoc_constraintmanager_spimaster_cs_n attribute \src "ls180.v:124.6-124.59" wire \libresocsim_libresoc_constraintmanager_spimaster_miso attribute \src "ls180.v:122.5-122.58" wire \libresocsim_libresoc_constraintmanager_spimaster_mosi attribute \src "ls180.v:133.5-133.51" wire \libresocsim_libresoc_constraintmanager_uart_rx attribute \src "ls180.v:132.5-132.51" wire \libresocsim_libresoc_constraintmanager_uart_tx attribute \src "ls180.v:59.5-59.34" wire \libresocsim_libresoc_dbus_ack attribute \src "ls180.v:53.13-53.42" wire width 29 \libresocsim_libresoc_dbus_adr attribute \src "ls180.v:57.6-57.35" wire \libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:55.13-55.44" wire width 64 \libresocsim_libresoc_dbus_dat_r attribute \src "ls180.v:54.13-54.44" wire width 64 \libresocsim_libresoc_dbus_dat_w attribute \src "ls180.v:61.5-61.34" wire \libresocsim_libresoc_dbus_err attribute \src "ls180.v:56.12-56.41" wire width 8 \libresocsim_libresoc_dbus_sel attribute \src "ls180.v:58.6-58.35" wire \libresocsim_libresoc_dbus_stb attribute \src "ls180.v:60.6-60.34" wire \libresocsim_libresoc_dbus_we attribute \src "ls180.v:68.5-68.34" wire \libresocsim_libresoc_ibus_ack attribute \src "ls180.v:62.13-62.42" wire width 29 \libresocsim_libresoc_ibus_adr attribute \src "ls180.v:66.6-66.35" wire \libresocsim_libresoc_ibus_cyc attribute \src "ls180.v:64.13-64.44" wire width 64 \libresocsim_libresoc_ibus_dat_r attribute \src "ls180.v:63.13-63.44" wire width 64 \libresocsim_libresoc_ibus_dat_w attribute \src "ls180.v:70.5-70.34" wire \libresocsim_libresoc_ibus_err attribute \src "ls180.v:65.12-65.41" wire width 8 \libresocsim_libresoc_ibus_sel attribute \src "ls180.v:67.6-67.35" wire \libresocsim_libresoc_ibus_stb attribute \src "ls180.v:69.6-69.34" wire \libresocsim_libresoc_ibus_we attribute \src "ls180.v:52.12-52.42" wire width 16 \libresocsim_libresoc_interrupt attribute \src "ls180.v:102.6-102.35" wire \libresocsim_libresoc_jtag_tck attribute \src "ls180.v:104.6-104.35" wire \libresocsim_libresoc_jtag_tdi attribute \src "ls180.v:105.6-105.35" wire \libresocsim_libresoc_jtag_tdo attribute \src "ls180.v:103.6-103.35" wire \libresocsim_libresoc_jtag_tms attribute \src "ls180.v:99.5-99.37" wire \libresocsim_libresoc_jtag_wb_ack attribute \src "ls180.v:93.13-93.45" wire width 29 \libresocsim_libresoc_jtag_wb_adr attribute \src "ls180.v:97.6-97.38" wire \libresocsim_libresoc_jtag_wb_cyc attribute \src "ls180.v:95.13-95.47" wire width 64 \libresocsim_libresoc_jtag_wb_dat_r attribute \src "ls180.v:94.13-94.47" wire width 64 \libresocsim_libresoc_jtag_wb_dat_w attribute \src "ls180.v:101.5-101.37" wire \libresocsim_libresoc_jtag_wb_err attribute \src "ls180.v:96.12-96.44" wire width 8 \libresocsim_libresoc_jtag_wb_sel attribute \src "ls180.v:98.6-98.38" wire \libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:100.6-100.37" wire \libresocsim_libresoc_jtag_wb_we attribute \src "ls180.v:51.6-51.32" wire \libresocsim_libresoc_reset attribute \src "ls180.v:77.6-77.39" wire \libresocsim_libresoc_xics_icp_ack attribute \src "ls180.v:71.13-71.46" wire width 30 \libresocsim_libresoc_xics_icp_adr attribute \src "ls180.v:80.12-80.45" wire width 2 \libresocsim_libresoc_xics_icp_bte attribute \src "ls180.v:79.12-79.45" wire width 3 \libresocsim_libresoc_xics_icp_cti attribute \src "ls180.v:75.6-75.39" wire \libresocsim_libresoc_xics_icp_cyc attribute \src "ls180.v:73.13-73.48" wire width 32 \libresocsim_libresoc_xics_icp_dat_r attribute \src "ls180.v:72.13-72.48" wire width 32 \libresocsim_libresoc_xics_icp_dat_w attribute \src "ls180.v:81.6-81.39" wire \libresocsim_libresoc_xics_icp_err attribute \src "ls180.v:74.12-74.45" wire width 4 \libresocsim_libresoc_xics_icp_sel attribute \src "ls180.v:76.6-76.39" wire \libresocsim_libresoc_xics_icp_stb attribute \src "ls180.v:78.6-78.38" wire \libresocsim_libresoc_xics_icp_we attribute \src "ls180.v:88.6-88.39" wire \libresocsim_libresoc_xics_ics_ack attribute \src "ls180.v:82.13-82.46" wire width 30 \libresocsim_libresoc_xics_ics_adr attribute \src "ls180.v:91.12-91.45" wire width 2 \libresocsim_libresoc_xics_ics_bte attribute \src "ls180.v:90.12-90.45" wire width 3 \libresocsim_libresoc_xics_ics_cti attribute \src "ls180.v:86.6-86.39" wire \libresocsim_libresoc_xics_ics_cyc attribute \src "ls180.v:84.13-84.48" wire width 32 \libresocsim_libresoc_xics_ics_dat_r attribute \src "ls180.v:83.13-83.48" wire width 32 \libresocsim_libresoc_xics_ics_dat_w attribute \src "ls180.v:92.6-92.39" wire \libresocsim_libresoc_xics_ics_err attribute \src "ls180.v:85.12-85.45" wire width 4 \libresocsim_libresoc_xics_ics_sel attribute \src "ls180.v:87.6-87.39" wire \libresocsim_libresoc_xics_ics_stb attribute \src "ls180.v:89.6-89.38" wire \libresocsim_libresoc_xics_ics_we attribute \src "ls180.v:1051.12-1051.39" wire width 14 \libresocsim_libresocsim_adr attribute \src "ls180.v:1333.12-1333.63" wire width 14 \libresocsim_libresocsim_adr_libresocsim_next_value1 attribute \src "ls180.v:1334.5-1334.59" wire \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 attribute \src "ls180.v:1054.12-1054.41" wire width 8 \libresocsim_libresocsim_dat_r attribute \src "ls180.v:1053.11-1053.40" wire width 8 \libresocsim_libresocsim_dat_w attribute \src "ls180.v:1331.11-1331.64" wire width 8 \libresocsim_libresocsim_dat_w_libresocsim_next_value0 attribute \src "ls180.v:1332.5-1332.61" wire \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 attribute \src "ls180.v:1052.5-1052.31" wire \libresocsim_libresocsim_we attribute \src "ls180.v:1335.5-1335.55" wire \libresocsim_libresocsim_we_libresocsim_next_value2 attribute \src "ls180.v:1336.5-1336.58" wire \libresocsim_libresocsim_we_libresocsim_next_value_ce2 attribute \src "ls180.v:1061.5-1061.41" wire \libresocsim_libresocsim_wishbone_ack attribute \src "ls180.v:1055.13-1055.49" wire width 30 \libresocsim_libresocsim_wishbone_adr attribute \src "ls180.v:1064.12-1064.48" wire width 2 \libresocsim_libresocsim_wishbone_bte attribute \src "ls180.v:1063.12-1063.48" wire width 3 \libresocsim_libresocsim_wishbone_cti attribute \src "ls180.v:1059.6-1059.42" wire \libresocsim_libresocsim_wishbone_cyc attribute \src "ls180.v:1057.12-1057.50" wire width 32 \libresocsim_libresocsim_wishbone_dat_r attribute \src "ls180.v:1056.13-1056.51" wire width 32 \libresocsim_libresocsim_wishbone_dat_w attribute \src "ls180.v:1065.5-1065.41" wire \libresocsim_libresocsim_wishbone_err attribute \src "ls180.v:1058.12-1058.48" wire width 4 \libresocsim_libresocsim_wishbone_sel attribute \src "ls180.v:1060.6-1060.42" wire \libresocsim_libresocsim_wishbone_stb attribute \src "ls180.v:1062.6-1062.41" wire \libresocsim_libresocsim_wishbone_we attribute \src "ls180.v:198.5-198.24" wire \libresocsim_load_re attribute \src "ls180.v:197.12-197.36" wire width 32 \libresocsim_load_storage attribute \src "ls180.v:1330.11-1330.33" wire width 2 \libresocsim_next_state attribute \src "ls180.v:188.5-188.28" wire \libresocsim_ram_bus_ack attribute \src "ls180.v:182.13-182.36" wire width 30 \libresocsim_ram_bus_adr attribute \src "ls180.v:191.12-191.35" wire width 2 \libresocsim_ram_bus_bte attribute \src "ls180.v:190.12-190.35" wire width 3 \libresocsim_ram_bus_cti attribute \src "ls180.v:186.6-186.29" wire \libresocsim_ram_bus_cyc attribute \src "ls180.v:184.13-184.38" wire width 32 \libresocsim_ram_bus_dat_r attribute \src "ls180.v:183.13-183.38" wire width 32 \libresocsim_ram_bus_dat_w attribute \src "ls180.v:192.5-192.28" wire \libresocsim_ram_bus_err attribute \src "ls180.v:185.12-185.35" wire width 4 \libresocsim_ram_bus_sel attribute \src "ls180.v:187.6-187.29" wire \libresocsim_ram_bus_stb attribute \src "ls180.v:189.6-189.28" wire \libresocsim_ram_bus_we attribute \src "ls180.v:200.5-200.26" wire \libresocsim_reload_re attribute \src "ls180.v:199.12-199.38" wire width 32 \libresocsim_reload_storage attribute \src "ls180.v:1077.12-1077.31" wire width 3 \libresocsim_request attribute \src "ls180.v:48.6-48.23" wire \libresocsim_reset attribute \src "ls180.v:43.5-43.25" wire \libresocsim_reset_re attribute \src "ls180.v:42.5-42.30" wire \libresocsim_reset_storage attribute \src "ls180.v:45.5-45.27" wire \libresocsim_scratch_re attribute \src "ls180.v:44.12-44.39" wire width 32 \libresocsim_scratch_storage attribute \src "ls180.v:1072.5-1072.27" wire \libresocsim_shared_ack attribute \src "ls180.v:1066.13-1066.35" wire width 30 \libresocsim_shared_adr attribute \src "ls180.v:1075.12-1075.34" wire width 2 \libresocsim_shared_bte attribute \src "ls180.v:1074.12-1074.34" wire width 3 \libresocsim_shared_cti attribute \src "ls180.v:1070.6-1070.28" wire \libresocsim_shared_cyc attribute \src "ls180.v:1068.12-1068.36" wire width 32 \libresocsim_shared_dat_r attribute \src "ls180.v:1067.13-1067.37" wire width 32 \libresocsim_shared_dat_w attribute \src "ls180.v:1076.6-1076.28" wire \libresocsim_shared_err attribute \src "ls180.v:1069.12-1069.34" wire width 4 \libresocsim_shared_sel attribute \src "ls180.v:1071.6-1071.28" wire \libresocsim_shared_stb attribute \src "ls180.v:1073.6-1073.27" wire \libresocsim_shared_we attribute \src "ls180.v:1079.11-1079.32" wire width 6 \libresocsim_slave_sel attribute \src "ls180.v:1080.11-1080.34" wire width 6 \libresocsim_slave_sel_r attribute \src "ls180.v:1329.11-1329.28" wire width 2 \libresocsim_state attribute \src "ls180.v:204.5-204.32" wire \libresocsim_update_value_re attribute \src "ls180.v:203.5-203.37" wire \libresocsim_update_value_storage attribute \src "ls180.v:223.12-223.29" wire width 32 \libresocsim_value attribute \src "ls180.v:205.12-205.36" wire width 32 \libresocsim_value_status attribute \src "ls180.v:206.6-206.26" wire \libresocsim_value_we attribute \src "ls180.v:1082.6-1082.22" wire \libresocsim_wait attribute \src "ls180.v:195.11-195.25" wire width 4 \libresocsim_we attribute \src "ls180.v:211.5-211.27" wire \libresocsim_zero_clear attribute \src "ls180.v:212.5-212.33" wire \libresocsim_zero_old_trigger attribute \src "ls180.v:209.5-209.29" wire \libresocsim_zero_pending attribute \src "ls180.v:208.6-208.29" wire \libresocsim_zero_status attribute \src "ls180.v:210.6-210.30" wire \libresocsim_zero_trigger attribute \src "ls180.v:820.6-820.21" wire \litedram_wb_ack attribute \src "ls180.v:814.12-814.27" wire width 30 \litedram_wb_adr attribute \src "ls180.v:818.5-818.20" wire \litedram_wb_cyc attribute \src "ls180.v:816.13-816.30" wire width 16 \litedram_wb_dat_r attribute \src "ls180.v:815.12-815.29" wire width 16 \litedram_wb_dat_w attribute \src "ls180.v:817.11-817.26" wire width 2 \litedram_wb_sel attribute \src "ls180.v:819.5-819.20" wire \litedram_wb_stb attribute \src "ls180.v:821.5-821.19" wire \litedram_wb_we attribute \src "ls180.v:5489.11-5489.17" wire width 7 \memadr attribute \src "ls180.v:5509.11-5509.19" wire width 5 \memadr_1 attribute \src "ls180.v:5529.12-5529.18" wire width 25 \memdat attribute \src "ls180.v:5543.12-5543.20" wire width 25 \memdat_1 attribute \src "ls180.v:5557.12-5557.20" wire width 25 \memdat_2 attribute \src "ls180.v:5571.12-5571.20" wire width 25 \memdat_3 attribute \src "ls180.v:5585.11-5585.19" wire width 10 \memdat_4 attribute \src "ls180.v:5586.11-5586.19" wire width 10 \memdat_5 attribute \src "ls180.v:5602.11-5602.19" wire width 10 \memdat_6 attribute \src "ls180.v:5603.11-5603.19" wire width 10 \memdat_7 attribute \src "ls180.v:39.20-39.22" wire width 40 input 35 \nc attribute \src "ls180.v:992.13-992.17" wire width 40 \nc_1 attribute \src "ls180.v:241.6-241.13" wire \por_clk attribute \src "ls180.v:793.6-793.19" wire \port_cmd_last attribute \src "ls180.v:795.13-795.34" wire width 24 \port_cmd_payload_addr attribute \src "ls180.v:794.6-794.25" wire \port_cmd_payload_we attribute \src "ls180.v:792.6-792.20" wire \port_cmd_ready attribute \src "ls180.v:791.6-791.20" wire \port_cmd_valid attribute \src "ls180.v:790.6-790.16" wire \port_flush attribute \src "ls180.v:802.13-802.36" wire width 16 \port_rdata_payload_data attribute \src "ls180.v:801.6-801.22" wire \port_rdata_ready attribute \src "ls180.v:800.6-800.22" wire \port_rdata_valid attribute \src "ls180.v:798.13-798.36" wire width 16 \port_wdata_payload_data attribute \src "ls180.v:799.12-799.33" wire width 2 \port_wdata_payload_we attribute \src "ls180.v:797.6-797.22" wire \port_wdata_ready attribute \src "ls180.v:796.6-796.22" wire \port_wdata_valid attribute \src "ls180.v:235.12-235.19" wire width 5 \ram_adr attribute \src "ls180.v:230.5-230.24" wire \ram_bus_ram_bus_ack attribute \src "ls180.v:224.13-224.32" wire width 30 \ram_bus_ram_bus_adr attribute \src "ls180.v:233.12-233.31" wire width 2 \ram_bus_ram_bus_bte attribute \src "ls180.v:232.12-232.31" wire width 3 \ram_bus_ram_bus_cti attribute \src "ls180.v:228.6-228.25" wire \ram_bus_ram_bus_cyc attribute \src "ls180.v:226.13-226.34" wire width 32 \ram_bus_ram_bus_dat_r attribute \src "ls180.v:225.13-225.34" wire width 32 \ram_bus_ram_bus_dat_w attribute \src "ls180.v:234.5-234.24" wire \ram_bus_ram_bus_err attribute \src "ls180.v:227.12-227.31" wire width 4 \ram_bus_ram_bus_sel attribute \src "ls180.v:229.6-229.25" wire \ram_bus_ram_bus_stb attribute \src "ls180.v:231.6-231.24" wire \ram_bus_ram_bus_we attribute \src "ls180.v:236.13-236.22" wire width 32 \ram_dat_r attribute \src "ls180.v:238.13-238.22" wire width 32 \ram_dat_w attribute \src "ls180.v:237.11-237.17" wire width 4 \ram_we attribute \src "ls180.v:259.11-259.20" wire width 3 \rddata_en attribute \no_retiming "true" attribute \src "ls180.v:1438.32-1438.37" wire \regs0 attribute \no_retiming "true" attribute \src "ls180.v:1439.32-1439.37" wire \regs1 attribute \src "ls180.v:972.5-972.10" wire \reset attribute \src "ls180.v:1337.5-1337.21" wire \rhs_array_muxed0 attribute \src "ls180.v:1338.12-1338.28" wire width 13 \rhs_array_muxed1 attribute \src "ls180.v:1350.5-1350.22" wire \rhs_array_muxed10 attribute \src "ls180.v:1351.5-1351.22" wire \rhs_array_muxed11 attribute \src "ls180.v:1355.12-1355.29" wire width 22 \rhs_array_muxed12 attribute \src "ls180.v:1356.5-1356.22" wire \rhs_array_muxed13 attribute \src "ls180.v:1357.5-1357.22" wire \rhs_array_muxed14 attribute \src "ls180.v:1358.12-1358.29" wire width 22 \rhs_array_muxed15 attribute \src "ls180.v:1359.5-1359.22" wire \rhs_array_muxed16 attribute \src "ls180.v:1360.5-1360.22" wire \rhs_array_muxed17 attribute \src "ls180.v:1361.12-1361.29" wire width 22 \rhs_array_muxed18 attribute \src "ls180.v:1362.5-1362.22" wire \rhs_array_muxed19 attribute \src "ls180.v:1339.11-1339.27" wire width 2 \rhs_array_muxed2 attribute \src "ls180.v:1363.5-1363.22" wire \rhs_array_muxed20 attribute \src "ls180.v:1364.12-1364.29" wire width 22 \rhs_array_muxed21 attribute \src "ls180.v:1365.5-1365.22" wire \rhs_array_muxed22 attribute \src "ls180.v:1366.5-1366.22" wire \rhs_array_muxed23 attribute \src "ls180.v:1367.12-1367.29" wire width 30 \rhs_array_muxed24 attribute \src "ls180.v:1368.12-1368.29" wire width 32 \rhs_array_muxed25 attribute \src "ls180.v:1369.11-1369.28" wire width 4 \rhs_array_muxed26 attribute \src "ls180.v:1370.5-1370.22" wire \rhs_array_muxed27 attribute \src "ls180.v:1371.5-1371.22" wire \rhs_array_muxed28 attribute \src "ls180.v:1372.5-1372.22" wire \rhs_array_muxed29 attribute \src "ls180.v:1340.5-1340.21" wire \rhs_array_muxed3 attribute \src "ls180.v:1373.11-1373.28" wire width 3 \rhs_array_muxed30 attribute \src "ls180.v:1374.11-1374.28" wire width 2 \rhs_array_muxed31 attribute \src "ls180.v:1341.5-1341.21" wire \rhs_array_muxed4 attribute \src "ls180.v:1342.5-1342.21" wire \rhs_array_muxed5 attribute \src "ls180.v:1346.5-1346.21" wire \rhs_array_muxed6 attribute \src "ls180.v:1347.12-1347.28" wire width 13 \rhs_array_muxed7 attribute \src "ls180.v:1348.11-1348.27" wire width 2 \rhs_array_muxed8 attribute \src "ls180.v:1349.5-1349.21" wire \rhs_array_muxed9 attribute \src "ls180.v:872.5-872.13" wire \rx_clear attribute \src "ls180.v:956.11-956.26" wire width 4 \rx_fifo_consume attribute \src "ls180.v:961.6-961.21" wire \rx_fifo_do_read attribute \src "ls180.v:967.6-967.27" wire \rx_fifo_fifo_in_first attribute \src "ls180.v:968.6-968.26" wire \rx_fifo_fifo_in_last attribute \src "ls180.v:966.12-966.40" wire width 8 \rx_fifo_fifo_in_payload_data attribute \src "ls180.v:970.6-970.28" wire \rx_fifo_fifo_out_first attribute \src "ls180.v:971.6-971.27" wire \rx_fifo_fifo_out_last attribute \src "ls180.v:969.12-969.41" wire width 8 \rx_fifo_fifo_out_payload_data attribute \src "ls180.v:953.11-953.25" wire width 5 \rx_fifo_level0 attribute \src "ls180.v:965.12-965.26" wire width 5 \rx_fifo_level1 attribute \src "ls180.v:955.11-955.26" wire width 4 \rx_fifo_produce attribute \src "ls180.v:962.12-962.30" wire width 4 \rx_fifo_rdport_adr attribute \src "ls180.v:963.12-963.32" wire width 10 \rx_fifo_rdport_dat_r attribute \src "ls180.v:964.6-964.23" wire \rx_fifo_rdport_re attribute \src "ls180.v:945.6-945.16" wire \rx_fifo_re attribute \src "ls180.v:946.5-946.21" wire \rx_fifo_readable attribute \src "ls180.v:954.5-954.20" wire \rx_fifo_replace attribute \src "ls180.v:937.6-937.24" wire \rx_fifo_sink_first attribute \src "ls180.v:938.6-938.23" wire \rx_fifo_sink_last attribute \src "ls180.v:939.12-939.37" wire width 8 \rx_fifo_sink_payload_data attribute \src "ls180.v:936.6-936.24" wire \rx_fifo_sink_ready attribute \src "ls180.v:935.6-935.24" wire \rx_fifo_sink_valid attribute \src "ls180.v:942.6-942.26" wire \rx_fifo_source_first attribute \src "ls180.v:943.6-943.25" wire \rx_fifo_source_last attribute \src "ls180.v:944.12-944.39" wire width 8 \rx_fifo_source_payload_data attribute \src "ls180.v:941.6-941.26" wire \rx_fifo_source_ready attribute \src "ls180.v:940.6-940.26" wire \rx_fifo_source_valid attribute \src "ls180.v:951.12-951.32" wire width 10 \rx_fifo_syncfifo_din attribute \src "ls180.v:952.12-952.33" wire width 10 \rx_fifo_syncfifo_dout attribute \src "ls180.v:949.6-949.25" wire \rx_fifo_syncfifo_re attribute \src "ls180.v:950.6-950.31" wire \rx_fifo_syncfifo_readable attribute \src "ls180.v:947.6-947.25" wire \rx_fifo_syncfifo_we attribute \src "ls180.v:948.6-948.31" wire \rx_fifo_syncfifo_writable attribute \src "ls180.v:957.11-957.29" wire width 4 \rx_fifo_wrport_adr attribute \src "ls180.v:958.12-958.32" wire width 10 \rx_fifo_wrport_dat_r attribute \src "ls180.v:960.12-960.32" wire width 10 \rx_fifo_wrport_dat_w attribute \src "ls180.v:959.6-959.23" wire \rx_fifo_wrport_we attribute \src "ls180.v:873.5-873.19" wire \rx_old_trigger attribute \src "ls180.v:870.5-870.15" wire \rx_pending attribute \src "ls180.v:869.6-869.15" wire \rx_status attribute \src "ls180.v:871.6-871.16" wire \rx_trigger attribute \src "ls180.v:861.6-861.20" wire \rxempty_status attribute \src "ls180.v:862.6-862.16" wire \rxempty_we attribute \src "ls180.v:886.6-886.19" wire \rxfull_status attribute \src "ls180.v:887.6-887.15" wire \rxfull_we attribute \src "ls180.v:856.12-856.18" wire width 8 \rxtx_r attribute \src "ls180.v:855.6-855.13" wire \rxtx_re attribute \src "ls180.v:858.12-858.18" wire width 8 \rxtx_w attribute \src "ls180.v:857.6-857.13" wire \rxtx_we attribute \src "ls180.v:5.21-5.28" wire width 13 output 1 \sdram_a attribute \src "ls180.v:321.5-321.21" wire \sdram_address_re attribute \src "ls180.v:320.12-320.33" wire width 13 \sdram_address_storage attribute \src "ls180.v:14.20-14.28" wire width 2 output 10 \sdram_ba attribute \src "ls180.v:323.5-323.22" wire \sdram_baddress_re attribute \src "ls180.v:322.11-322.33" wire width 2 \sdram_baddress_storage attribute \src "ls180.v:419.5-419.38" wire \sdram_bankmachine0_auto_precharge attribute \src "ls180.v:441.11-441.58" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_consume attribute \src "ls180.v:446.6-446.53" wire \sdram_bankmachine0_cmd_buffer_lookahead_do_read attribute \src "ls180.v:451.6-451.59" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first attribute \src "ls180.v:452.6-452.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last attribute \src "ls180.v:450.13-450.73" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr attribute \src "ls180.v:449.6-449.64" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we attribute \src "ls180.v:455.6-455.60" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first attribute \src "ls180.v:456.6-456.59" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last attribute \src "ls180.v:454.13-454.74" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr attribute \src "ls180.v:453.6-453.65" wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we attribute \src "ls180.v:438.11-438.56" wire width 4 \sdram_bankmachine0_cmd_buffer_lookahead_level attribute \src "ls180.v:440.11-440.58" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_produce attribute \src "ls180.v:447.12-447.62" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr attribute \src "ls180.v:448.13-448.65" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r attribute \src "ls180.v:439.5-439.52" wire \sdram_bankmachine0_cmd_buffer_lookahead_replace attribute \src "ls180.v:422.5-422.55" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_first attribute \src "ls180.v:423.5-423.54" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_last attribute \src "ls180.v:425.13-425.70" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr attribute \src "ls180.v:424.6-424.61" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we attribute \src "ls180.v:421.6-421.56" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:420.6-420.56" wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid attribute \src "ls180.v:428.6-428.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_first attribute \src "ls180.v:429.6-429.57" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_last attribute \src "ls180.v:431.13-431.72" wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr attribute \src "ls180.v:430.6-430.63" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we attribute \src "ls180.v:427.6-427.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:426.6-426.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_source_valid attribute \src "ls180.v:436.13-436.66" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din attribute \src "ls180.v:437.13-437.67" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout attribute \src "ls180.v:434.6-434.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re attribute \src "ls180.v:435.6-435.64" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable attribute \src "ls180.v:432.6-432.58" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we attribute \src "ls180.v:433.6-433.64" wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable attribute \src "ls180.v:442.11-442.61" wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr attribute \src "ls180.v:443.13-443.65" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r attribute \src "ls180.v:445.13-445.65" wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w attribute \src "ls180.v:444.6-444.55" wire \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:459.6-459.46" wire \sdram_bankmachine0_cmd_buffer_sink_first attribute \src "ls180.v:460.6-460.45" wire \sdram_bankmachine0_cmd_buffer_sink_last attribute \src "ls180.v:462.13-462.60" wire width 22 \sdram_bankmachine0_cmd_buffer_sink_payload_addr attribute \src "ls180.v:461.6-461.51" wire \sdram_bankmachine0_cmd_buffer_sink_payload_we attribute \src "ls180.v:458.6-458.46" wire \sdram_bankmachine0_cmd_buffer_sink_ready attribute \src "ls180.v:457.6-457.46" wire \sdram_bankmachine0_cmd_buffer_sink_valid attribute \src "ls180.v:465.5-465.47" wire \sdram_bankmachine0_cmd_buffer_source_first attribute \src "ls180.v:466.5-466.46" wire \sdram_bankmachine0_cmd_buffer_source_last attribute \src "ls180.v:468.12-468.61" wire width 22 \sdram_bankmachine0_cmd_buffer_source_payload_addr attribute \src "ls180.v:467.5-467.52" wire \sdram_bankmachine0_cmd_buffer_source_payload_we attribute \src "ls180.v:464.6-464.48" wire \sdram_bankmachine0_cmd_buffer_source_ready attribute \src "ls180.v:463.5-463.47" wire \sdram_bankmachine0_cmd_buffer_source_valid attribute \src "ls180.v:411.12-411.44" wire width 13 \sdram_bankmachine0_cmd_payload_a attribute \src "ls180.v:412.12-412.45" wire width 2 \sdram_bankmachine0_cmd_payload_ba attribute \src "ls180.v:413.5-413.39" wire \sdram_bankmachine0_cmd_payload_cas attribute \src "ls180.v:416.5-416.42" wire \sdram_bankmachine0_cmd_payload_is_cmd attribute \src "ls180.v:417.5-417.43" wire \sdram_bankmachine0_cmd_payload_is_read attribute \src "ls180.v:418.5-418.44" wire \sdram_bankmachine0_cmd_payload_is_write attribute \src "ls180.v:414.5-414.39" wire \sdram_bankmachine0_cmd_payload_ras attribute \src "ls180.v:415.5-415.38" wire \sdram_bankmachine0_cmd_payload_we attribute \src "ls180.v:410.5-410.33" wire \sdram_bankmachine0_cmd_ready attribute \src "ls180.v:409.5-409.33" wire \sdram_bankmachine0_cmd_valid attribute \src "ls180.v:408.5-408.35" wire \sdram_bankmachine0_refresh_gnt attribute \src "ls180.v:407.6-407.36" wire \sdram_bankmachine0_refresh_req attribute \src "ls180.v:403.13-403.40" wire width 22 \sdram_bankmachine0_req_addr attribute \src "ls180.v:404.6-404.33" wire \sdram_bankmachine0_req_lock attribute \src "ls180.v:406.5-406.39" wire \sdram_bankmachine0_req_rdata_valid attribute \src "ls180.v:401.6-401.34" wire \sdram_bankmachine0_req_ready attribute \src "ls180.v:400.6-400.34" wire \sdram_bankmachine0_req_valid attribute \src "ls180.v:405.5-405.39" wire \sdram_bankmachine0_req_wdata_ready attribute \src "ls180.v:402.6-402.31" wire \sdram_bankmachine0_req_we attribute \src "ls180.v:469.12-469.34" wire width 13 \sdram_bankmachine0_row attribute \src "ls180.v:473.5-473.33" wire \sdram_bankmachine0_row_close attribute \src "ls180.v:474.5-474.42" wire \sdram_bankmachine0_row_col_n_addr_sel attribute \src "ls180.v:471.6-471.32" wire \sdram_bankmachine0_row_hit attribute \src "ls180.v:472.5-472.32" wire \sdram_bankmachine0_row_open attribute \src "ls180.v:470.5-470.34" wire \sdram_bankmachine0_row_opened attribute \no_retiming "true" attribute \src "ls180.v:481.32-481.64" wire \sdram_bankmachine0_trascon_ready attribute \src "ls180.v:480.6-480.38" wire \sdram_bankmachine0_trascon_valid attribute \no_retiming "true" attribute \src "ls180.v:479.32-479.63" wire \sdram_bankmachine0_trccon_ready attribute \src "ls180.v:478.6-478.37" wire \sdram_bankmachine0_trccon_valid attribute \src "ls180.v:477.11-477.43" wire width 3 \sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" attribute \src "ls180.v:476.32-476.64" wire \sdram_bankmachine0_twtpcon_ready attribute \src "ls180.v:475.6-475.38" wire \sdram_bankmachine0_twtpcon_valid attribute \src "ls180.v:501.5-501.38" wire \sdram_bankmachine1_auto_precharge attribute \src "ls180.v:523.11-523.58" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_consume attribute \src "ls180.v:528.6-528.53" wire \sdram_bankmachine1_cmd_buffer_lookahead_do_read attribute \src "ls180.v:533.6-533.59" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first attribute \src "ls180.v:534.6-534.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last attribute \src "ls180.v:532.13-532.73" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr attribute \src "ls180.v:531.6-531.64" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we attribute \src "ls180.v:537.6-537.60" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first attribute \src "ls180.v:538.6-538.59" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last attribute \src "ls180.v:536.13-536.74" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr attribute \src "ls180.v:535.6-535.65" wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we attribute \src "ls180.v:520.11-520.56" wire width 4 \sdram_bankmachine1_cmd_buffer_lookahead_level attribute \src "ls180.v:522.11-522.58" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_produce attribute \src "ls180.v:529.12-529.62" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr attribute \src "ls180.v:530.13-530.65" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r attribute \src "ls180.v:521.5-521.52" wire \sdram_bankmachine1_cmd_buffer_lookahead_replace attribute \src "ls180.v:504.5-504.55" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_first attribute \src "ls180.v:505.5-505.54" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_last attribute \src "ls180.v:507.13-507.70" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr attribute \src "ls180.v:506.6-506.61" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we attribute \src "ls180.v:503.6-503.56" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:502.6-502.56" wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid attribute \src "ls180.v:510.6-510.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_first attribute \src "ls180.v:511.6-511.57" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_last attribute \src "ls180.v:513.13-513.72" wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr attribute \src "ls180.v:512.6-512.63" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we attribute \src "ls180.v:509.6-509.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:508.6-508.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_source_valid attribute \src "ls180.v:518.13-518.66" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din attribute \src "ls180.v:519.13-519.67" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout attribute \src "ls180.v:516.6-516.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re attribute \src "ls180.v:517.6-517.64" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable attribute \src "ls180.v:514.6-514.58" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we attribute \src "ls180.v:515.6-515.64" wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable attribute \src "ls180.v:524.11-524.61" wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr attribute \src "ls180.v:525.13-525.65" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r attribute \src "ls180.v:527.13-527.65" wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w attribute \src "ls180.v:526.6-526.55" wire \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:541.6-541.46" wire \sdram_bankmachine1_cmd_buffer_sink_first attribute \src "ls180.v:542.6-542.45" wire \sdram_bankmachine1_cmd_buffer_sink_last attribute \src "ls180.v:544.13-544.60" wire width 22 \sdram_bankmachine1_cmd_buffer_sink_payload_addr attribute \src "ls180.v:543.6-543.51" wire \sdram_bankmachine1_cmd_buffer_sink_payload_we attribute \src "ls180.v:540.6-540.46" wire \sdram_bankmachine1_cmd_buffer_sink_ready attribute \src "ls180.v:539.6-539.46" wire \sdram_bankmachine1_cmd_buffer_sink_valid attribute \src "ls180.v:547.5-547.47" wire \sdram_bankmachine1_cmd_buffer_source_first attribute \src "ls180.v:548.5-548.46" wire \sdram_bankmachine1_cmd_buffer_source_last attribute \src "ls180.v:550.12-550.61" wire width 22 \sdram_bankmachine1_cmd_buffer_source_payload_addr attribute \src "ls180.v:549.5-549.52" wire \sdram_bankmachine1_cmd_buffer_source_payload_we attribute \src "ls180.v:546.6-546.48" wire \sdram_bankmachine1_cmd_buffer_source_ready attribute \src "ls180.v:545.5-545.47" wire \sdram_bankmachine1_cmd_buffer_source_valid attribute \src "ls180.v:493.12-493.44" wire width 13 \sdram_bankmachine1_cmd_payload_a attribute \src "ls180.v:494.12-494.45" wire width 2 \sdram_bankmachine1_cmd_payload_ba attribute \src "ls180.v:495.5-495.39" wire \sdram_bankmachine1_cmd_payload_cas attribute \src "ls180.v:498.5-498.42" wire \sdram_bankmachine1_cmd_payload_is_cmd attribute \src "ls180.v:499.5-499.43" wire \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:500.5-500.44" wire \sdram_bankmachine1_cmd_payload_is_write attribute \src "ls180.v:496.5-496.39" wire \sdram_bankmachine1_cmd_payload_ras attribute \src "ls180.v:497.5-497.38" wire \sdram_bankmachine1_cmd_payload_we attribute \src "ls180.v:492.5-492.33" wire \sdram_bankmachine1_cmd_ready attribute \src "ls180.v:491.5-491.33" wire \sdram_bankmachine1_cmd_valid attribute \src "ls180.v:490.5-490.35" wire \sdram_bankmachine1_refresh_gnt attribute \src "ls180.v:489.6-489.36" wire \sdram_bankmachine1_refresh_req attribute \src "ls180.v:485.13-485.40" wire width 22 \sdram_bankmachine1_req_addr attribute \src "ls180.v:486.6-486.33" wire \sdram_bankmachine1_req_lock attribute \src "ls180.v:488.5-488.39" wire \sdram_bankmachine1_req_rdata_valid attribute \src "ls180.v:483.6-483.34" wire \sdram_bankmachine1_req_ready attribute \src "ls180.v:482.6-482.34" wire \sdram_bankmachine1_req_valid attribute \src "ls180.v:487.5-487.39" wire \sdram_bankmachine1_req_wdata_ready attribute \src "ls180.v:484.6-484.31" wire \sdram_bankmachine1_req_we attribute \src "ls180.v:551.12-551.34" wire width 13 \sdram_bankmachine1_row attribute \src "ls180.v:555.5-555.33" wire \sdram_bankmachine1_row_close attribute \src "ls180.v:556.5-556.42" wire \sdram_bankmachine1_row_col_n_addr_sel attribute \src "ls180.v:553.6-553.32" wire \sdram_bankmachine1_row_hit attribute \src "ls180.v:554.5-554.32" wire \sdram_bankmachine1_row_open attribute \src "ls180.v:552.5-552.34" wire \sdram_bankmachine1_row_opened attribute \no_retiming "true" attribute \src "ls180.v:563.32-563.64" wire \sdram_bankmachine1_trascon_ready attribute \src "ls180.v:562.6-562.38" wire \sdram_bankmachine1_trascon_valid attribute \no_retiming "true" attribute \src "ls180.v:561.32-561.63" wire \sdram_bankmachine1_trccon_ready attribute \src "ls180.v:560.6-560.37" wire \sdram_bankmachine1_trccon_valid attribute \src "ls180.v:559.11-559.43" wire width 3 \sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" attribute \src "ls180.v:558.32-558.64" wire \sdram_bankmachine1_twtpcon_ready attribute \src "ls180.v:557.6-557.38" wire \sdram_bankmachine1_twtpcon_valid attribute \src "ls180.v:583.5-583.38" wire \sdram_bankmachine2_auto_precharge attribute \src "ls180.v:605.11-605.58" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_consume attribute \src "ls180.v:610.6-610.53" wire \sdram_bankmachine2_cmd_buffer_lookahead_do_read attribute \src "ls180.v:615.6-615.59" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first attribute \src "ls180.v:616.6-616.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last attribute \src "ls180.v:614.13-614.73" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr attribute \src "ls180.v:613.6-613.64" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we attribute \src "ls180.v:619.6-619.60" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first attribute \src "ls180.v:620.6-620.59" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last attribute \src "ls180.v:618.13-618.74" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr attribute \src "ls180.v:617.6-617.65" wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we attribute \src "ls180.v:602.11-602.56" wire width 4 \sdram_bankmachine2_cmd_buffer_lookahead_level attribute \src "ls180.v:604.11-604.58" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_produce attribute \src "ls180.v:611.12-611.62" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr attribute \src "ls180.v:612.13-612.65" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r attribute \src "ls180.v:603.5-603.52" wire \sdram_bankmachine2_cmd_buffer_lookahead_replace attribute \src "ls180.v:586.5-586.55" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_first attribute \src "ls180.v:587.5-587.54" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_last attribute \src "ls180.v:589.13-589.70" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr attribute \src "ls180.v:588.6-588.61" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we attribute \src "ls180.v:585.6-585.56" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:584.6-584.56" wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid attribute \src "ls180.v:592.6-592.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_first attribute \src "ls180.v:593.6-593.57" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_last attribute \src "ls180.v:595.13-595.72" wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr attribute \src "ls180.v:594.6-594.63" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we attribute \src "ls180.v:591.6-591.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:590.6-590.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_source_valid attribute \src "ls180.v:600.13-600.66" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din attribute \src "ls180.v:601.13-601.67" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout attribute \src "ls180.v:598.6-598.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re attribute \src "ls180.v:599.6-599.64" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable attribute \src "ls180.v:596.6-596.58" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we attribute \src "ls180.v:597.6-597.64" wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable attribute \src "ls180.v:606.11-606.61" wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr attribute \src "ls180.v:607.13-607.65" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r attribute \src "ls180.v:609.13-609.65" wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w attribute \src "ls180.v:608.6-608.55" wire \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:623.6-623.46" wire \sdram_bankmachine2_cmd_buffer_sink_first attribute \src "ls180.v:624.6-624.45" wire \sdram_bankmachine2_cmd_buffer_sink_last attribute \src "ls180.v:626.13-626.60" wire width 22 \sdram_bankmachine2_cmd_buffer_sink_payload_addr attribute \src "ls180.v:625.6-625.51" wire \sdram_bankmachine2_cmd_buffer_sink_payload_we attribute \src "ls180.v:622.6-622.46" wire \sdram_bankmachine2_cmd_buffer_sink_ready attribute \src "ls180.v:621.6-621.46" wire \sdram_bankmachine2_cmd_buffer_sink_valid attribute \src "ls180.v:629.5-629.47" wire \sdram_bankmachine2_cmd_buffer_source_first attribute \src "ls180.v:630.5-630.46" wire \sdram_bankmachine2_cmd_buffer_source_last attribute \src "ls180.v:632.12-632.61" wire width 22 \sdram_bankmachine2_cmd_buffer_source_payload_addr attribute \src "ls180.v:631.5-631.52" wire \sdram_bankmachine2_cmd_buffer_source_payload_we attribute \src "ls180.v:628.6-628.48" wire \sdram_bankmachine2_cmd_buffer_source_ready attribute \src "ls180.v:627.5-627.47" wire \sdram_bankmachine2_cmd_buffer_source_valid attribute \src "ls180.v:575.12-575.44" wire width 13 \sdram_bankmachine2_cmd_payload_a attribute \src "ls180.v:576.12-576.45" wire width 2 \sdram_bankmachine2_cmd_payload_ba attribute \src "ls180.v:577.5-577.39" wire \sdram_bankmachine2_cmd_payload_cas attribute \src "ls180.v:580.5-580.42" wire \sdram_bankmachine2_cmd_payload_is_cmd attribute \src "ls180.v:581.5-581.43" wire \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:582.5-582.44" wire \sdram_bankmachine2_cmd_payload_is_write attribute \src "ls180.v:578.5-578.39" wire \sdram_bankmachine2_cmd_payload_ras attribute \src "ls180.v:579.5-579.38" wire \sdram_bankmachine2_cmd_payload_we attribute \src "ls180.v:574.5-574.33" wire \sdram_bankmachine2_cmd_ready attribute \src "ls180.v:573.5-573.33" wire \sdram_bankmachine2_cmd_valid attribute \src "ls180.v:572.5-572.35" wire \sdram_bankmachine2_refresh_gnt attribute \src "ls180.v:571.6-571.36" wire \sdram_bankmachine2_refresh_req attribute \src "ls180.v:567.13-567.40" wire width 22 \sdram_bankmachine2_req_addr attribute \src "ls180.v:568.6-568.33" wire \sdram_bankmachine2_req_lock attribute \src "ls180.v:570.5-570.39" wire \sdram_bankmachine2_req_rdata_valid attribute \src "ls180.v:565.6-565.34" wire \sdram_bankmachine2_req_ready attribute \src "ls180.v:564.6-564.34" wire \sdram_bankmachine2_req_valid attribute \src "ls180.v:569.5-569.39" wire \sdram_bankmachine2_req_wdata_ready attribute \src "ls180.v:566.6-566.31" wire \sdram_bankmachine2_req_we attribute \src "ls180.v:633.12-633.34" wire width 13 \sdram_bankmachine2_row attribute \src "ls180.v:637.5-637.33" wire \sdram_bankmachine2_row_close attribute \src "ls180.v:638.5-638.42" wire \sdram_bankmachine2_row_col_n_addr_sel attribute \src "ls180.v:635.6-635.32" wire \sdram_bankmachine2_row_hit attribute \src "ls180.v:636.5-636.32" wire \sdram_bankmachine2_row_open attribute \src "ls180.v:634.5-634.34" wire \sdram_bankmachine2_row_opened attribute \no_retiming "true" attribute \src "ls180.v:645.32-645.64" wire \sdram_bankmachine2_trascon_ready attribute \src "ls180.v:644.6-644.38" wire \sdram_bankmachine2_trascon_valid attribute \no_retiming "true" attribute \src "ls180.v:643.32-643.63" wire \sdram_bankmachine2_trccon_ready attribute \src "ls180.v:642.6-642.37" wire \sdram_bankmachine2_trccon_valid attribute \src "ls180.v:641.11-641.43" wire width 3 \sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" attribute \src "ls180.v:640.32-640.64" wire \sdram_bankmachine2_twtpcon_ready attribute \src "ls180.v:639.6-639.38" wire \sdram_bankmachine2_twtpcon_valid attribute \src "ls180.v:665.5-665.38" wire \sdram_bankmachine3_auto_precharge attribute \src "ls180.v:687.11-687.58" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_consume attribute \src "ls180.v:692.6-692.53" wire \sdram_bankmachine3_cmd_buffer_lookahead_do_read attribute \src "ls180.v:697.6-697.59" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first attribute \src "ls180.v:698.6-698.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last attribute \src "ls180.v:696.13-696.73" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr attribute \src "ls180.v:695.6-695.64" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we attribute \src "ls180.v:701.6-701.60" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first attribute \src "ls180.v:702.6-702.59" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last attribute \src "ls180.v:700.13-700.74" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr attribute \src "ls180.v:699.6-699.65" wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we attribute \src "ls180.v:684.11-684.56" wire width 4 \sdram_bankmachine3_cmd_buffer_lookahead_level attribute \src "ls180.v:686.11-686.58" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_produce attribute \src "ls180.v:693.12-693.62" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr attribute \src "ls180.v:694.13-694.65" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r attribute \src "ls180.v:685.5-685.52" wire \sdram_bankmachine3_cmd_buffer_lookahead_replace attribute \src "ls180.v:668.5-668.55" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_first attribute \src "ls180.v:669.5-669.54" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_last attribute \src "ls180.v:671.13-671.70" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr attribute \src "ls180.v:670.6-670.61" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we attribute \src "ls180.v:667.6-667.56" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready attribute \src "ls180.v:666.6-666.56" wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid attribute \src "ls180.v:674.6-674.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_first attribute \src "ls180.v:675.6-675.57" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_last attribute \src "ls180.v:677.13-677.72" wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr attribute \src "ls180.v:676.6-676.63" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we attribute \src "ls180.v:673.6-673.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_ready attribute \src "ls180.v:672.6-672.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_source_valid attribute \src "ls180.v:682.13-682.66" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din attribute \src "ls180.v:683.13-683.67" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout attribute \src "ls180.v:680.6-680.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re attribute \src "ls180.v:681.6-681.64" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable attribute \src "ls180.v:678.6-678.58" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we attribute \src "ls180.v:679.6-679.64" wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable attribute \src "ls180.v:688.11-688.61" wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr attribute \src "ls180.v:689.13-689.65" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r attribute \src "ls180.v:691.13-691.65" wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w attribute \src "ls180.v:690.6-690.55" wire \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:705.6-705.46" wire \sdram_bankmachine3_cmd_buffer_sink_first attribute \src "ls180.v:706.6-706.45" wire \sdram_bankmachine3_cmd_buffer_sink_last attribute \src "ls180.v:708.13-708.60" wire width 22 \sdram_bankmachine3_cmd_buffer_sink_payload_addr attribute \src "ls180.v:707.6-707.51" wire \sdram_bankmachine3_cmd_buffer_sink_payload_we attribute \src "ls180.v:704.6-704.46" wire \sdram_bankmachine3_cmd_buffer_sink_ready attribute \src "ls180.v:703.6-703.46" wire \sdram_bankmachine3_cmd_buffer_sink_valid attribute \src "ls180.v:711.5-711.47" wire \sdram_bankmachine3_cmd_buffer_source_first attribute \src "ls180.v:712.5-712.46" wire \sdram_bankmachine3_cmd_buffer_source_last attribute \src "ls180.v:714.12-714.61" wire width 22 \sdram_bankmachine3_cmd_buffer_source_payload_addr attribute \src "ls180.v:713.5-713.52" wire \sdram_bankmachine3_cmd_buffer_source_payload_we attribute \src "ls180.v:710.6-710.48" wire \sdram_bankmachine3_cmd_buffer_source_ready attribute \src "ls180.v:709.5-709.47" wire \sdram_bankmachine3_cmd_buffer_source_valid attribute \src "ls180.v:657.12-657.44" wire width 13 \sdram_bankmachine3_cmd_payload_a attribute \src "ls180.v:658.12-658.45" wire width 2 \sdram_bankmachine3_cmd_payload_ba attribute \src "ls180.v:659.5-659.39" wire \sdram_bankmachine3_cmd_payload_cas attribute \src "ls180.v:662.5-662.42" wire \sdram_bankmachine3_cmd_payload_is_cmd attribute \src "ls180.v:663.5-663.43" wire \sdram_bankmachine3_cmd_payload_is_read attribute \src "ls180.v:664.5-664.44" wire \sdram_bankmachine3_cmd_payload_is_write attribute \src "ls180.v:660.5-660.39" wire \sdram_bankmachine3_cmd_payload_ras attribute \src "ls180.v:661.5-661.38" wire \sdram_bankmachine3_cmd_payload_we attribute \src "ls180.v:656.5-656.33" wire \sdram_bankmachine3_cmd_ready attribute \src "ls180.v:655.5-655.33" wire \sdram_bankmachine3_cmd_valid attribute \src "ls180.v:654.5-654.35" wire \sdram_bankmachine3_refresh_gnt attribute \src "ls180.v:653.6-653.36" wire \sdram_bankmachine3_refresh_req attribute \src "ls180.v:649.13-649.40" wire width 22 \sdram_bankmachine3_req_addr attribute \src "ls180.v:650.6-650.33" wire \sdram_bankmachine3_req_lock attribute \src "ls180.v:652.5-652.39" wire \sdram_bankmachine3_req_rdata_valid attribute \src "ls180.v:647.6-647.34" wire \sdram_bankmachine3_req_ready attribute \src "ls180.v:646.6-646.34" wire \sdram_bankmachine3_req_valid attribute \src "ls180.v:651.5-651.39" wire \sdram_bankmachine3_req_wdata_ready attribute \src "ls180.v:648.6-648.31" wire \sdram_bankmachine3_req_we attribute \src "ls180.v:715.12-715.34" wire width 13 \sdram_bankmachine3_row attribute \src "ls180.v:719.5-719.33" wire \sdram_bankmachine3_row_close attribute \src "ls180.v:720.5-720.42" wire \sdram_bankmachine3_row_col_n_addr_sel attribute \src "ls180.v:717.6-717.32" wire \sdram_bankmachine3_row_hit attribute \src "ls180.v:718.5-718.32" wire \sdram_bankmachine3_row_open attribute \src "ls180.v:716.5-716.34" wire \sdram_bankmachine3_row_opened attribute \no_retiming "true" attribute \src "ls180.v:727.32-727.64" wire \sdram_bankmachine3_trascon_ready attribute \src "ls180.v:726.6-726.38" wire \sdram_bankmachine3_trascon_valid attribute \no_retiming "true" attribute \src "ls180.v:725.32-725.63" wire \sdram_bankmachine3_trccon_ready attribute \src "ls180.v:724.6-724.37" wire \sdram_bankmachine3_trccon_valid attribute \src "ls180.v:723.11-723.43" wire width 3 \sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" attribute \src "ls180.v:722.32-722.64" wire \sdram_bankmachine3_twtpcon_ready attribute \src "ls180.v:721.6-721.38" wire \sdram_bankmachine3_twtpcon_valid attribute \src "ls180.v:729.6-729.23" wire \sdram_cas_allowed attribute \src "ls180.v:11.14-11.25" wire output 7 \sdram_cas_n attribute \src "ls180.v:747.6-747.25" wire \sdram_choose_cmd_ce attribute \src "ls180.v:736.13-736.43" wire width 13 \sdram_choose_cmd_cmd_payload_a attribute \src "ls180.v:737.12-737.43" wire width 2 \sdram_choose_cmd_cmd_payload_ba attribute \src "ls180.v:738.5-738.37" wire \sdram_choose_cmd_cmd_payload_cas attribute \src "ls180.v:741.6-741.41" wire \sdram_choose_cmd_cmd_payload_is_cmd attribute \src "ls180.v:742.6-742.42" wire \sdram_choose_cmd_cmd_payload_is_read attribute \src "ls180.v:743.6-743.43" wire \sdram_choose_cmd_cmd_payload_is_write attribute \src "ls180.v:739.5-739.37" wire \sdram_choose_cmd_cmd_payload_ras attribute \src "ls180.v:740.5-740.36" wire \sdram_choose_cmd_cmd_payload_we attribute \src "ls180.v:735.5-735.31" wire \sdram_choose_cmd_cmd_ready attribute \src "ls180.v:734.6-734.32" wire \sdram_choose_cmd_cmd_valid attribute \src "ls180.v:746.11-746.33" wire width 2 \sdram_choose_cmd_grant attribute \src "ls180.v:745.12-745.36" wire width 4 \sdram_choose_cmd_request attribute \src "ls180.v:744.11-744.34" wire width 4 \sdram_choose_cmd_valids attribute \src "ls180.v:733.5-733.36" wire \sdram_choose_cmd_want_activates attribute \src "ls180.v:732.5-732.31" wire \sdram_choose_cmd_want_cmds attribute \src "ls180.v:730.5-730.32" wire \sdram_choose_cmd_want_reads attribute \src "ls180.v:731.5-731.33" wire \sdram_choose_cmd_want_writes attribute \src "ls180.v:765.6-765.25" wire \sdram_choose_req_ce attribute \src "ls180.v:754.13-754.43" wire width 13 \sdram_choose_req_cmd_payload_a attribute \src "ls180.v:755.12-755.43" wire width 2 \sdram_choose_req_cmd_payload_ba attribute \src "ls180.v:756.5-756.37" wire \sdram_choose_req_cmd_payload_cas attribute \src "ls180.v:759.6-759.41" wire \sdram_choose_req_cmd_payload_is_cmd attribute \src "ls180.v:760.6-760.42" wire \sdram_choose_req_cmd_payload_is_read attribute \src "ls180.v:761.6-761.43" wire \sdram_choose_req_cmd_payload_is_write attribute \src "ls180.v:757.5-757.37" wire \sdram_choose_req_cmd_payload_ras attribute \src "ls180.v:758.5-758.36" wire \sdram_choose_req_cmd_payload_we attribute \src "ls180.v:753.5-753.31" wire \sdram_choose_req_cmd_ready attribute \src "ls180.v:752.6-752.32" wire \sdram_choose_req_cmd_valid attribute \src "ls180.v:764.11-764.33" wire width 2 \sdram_choose_req_grant attribute \src "ls180.v:763.12-763.36" wire width 4 \sdram_choose_req_request attribute \src "ls180.v:762.11-762.34" wire width 4 \sdram_choose_req_valids attribute \src "ls180.v:751.5-751.36" wire \sdram_choose_req_want_activates attribute \src "ls180.v:750.6-750.32" wire \sdram_choose_req_want_cmds attribute \src "ls180.v:748.5-748.32" wire \sdram_choose_req_want_reads attribute \src "ls180.v:749.5-749.33" wire \sdram_choose_req_want_writes attribute \src "ls180.v:13.14-13.23" wire output 9 \sdram_cke attribute \src "ls180.v:309.6-309.17" wire \sdram_cke_1 attribute \src "ls180.v:16.14-16.25" wire output 12 \sdram_clock attribute \src "ls180.v:377.5-377.19" wire \sdram_cmd_last attribute \src "ls180.v:378.12-378.31" wire width 13 \sdram_cmd_payload_a attribute \src "ls180.v:379.11-379.31" wire width 2 \sdram_cmd_payload_ba attribute \src "ls180.v:380.5-380.26" wire \sdram_cmd_payload_cas attribute \src "ls180.v:383.5-383.30" wire \sdram_cmd_payload_is_read attribute \src "ls180.v:384.5-384.31" wire \sdram_cmd_payload_is_write attribute \src "ls180.v:381.5-381.26" wire \sdram_cmd_payload_ras attribute \src "ls180.v:382.5-382.25" wire \sdram_cmd_payload_we attribute \src "ls180.v:376.5-376.20" wire \sdram_cmd_ready attribute \src "ls180.v:375.5-375.20" wire \sdram_cmd_valid attribute \src "ls180.v:317.6-317.27" wire \sdram_command_issue_r attribute \src "ls180.v:316.6-316.28" wire \sdram_command_issue_re attribute \src "ls180.v:319.5-319.26" wire \sdram_command_issue_w attribute \src "ls180.v:318.6-318.28" wire \sdram_command_issue_we attribute \src "ls180.v:315.5-315.21" wire \sdram_command_re attribute \src "ls180.v:314.11-314.32" wire width 6 \sdram_command_storage attribute \src "ls180.v:12.14-12.24" wire output 8 \sdram_cs_n attribute \src "ls180.v:368.5-368.23" wire \sdram_dfi_p0_act_n attribute \src "ls180.v:359.12-359.32" wire width 13 \sdram_dfi_p0_address attribute \src "ls180.v:360.11-360.28" wire width 2 \sdram_dfi_p0_bank attribute \src "ls180.v:361.5-361.23" wire \sdram_dfi_p0_cas_n attribute \src "ls180.v:365.6-365.22" wire \sdram_dfi_p0_cke attribute \src "ls180.v:362.5-362.22" wire \sdram_dfi_p0_cs_n attribute \src "ls180.v:366.6-366.22" wire \sdram_dfi_p0_odt attribute \src "ls180.v:363.5-363.23" wire \sdram_dfi_p0_ras_n attribute \src "ls180.v:373.13-373.32" wire width 16 \sdram_dfi_p0_rddata attribute \src "ls180.v:372.5-372.27" wire \sdram_dfi_p0_rddata_en attribute \src "ls180.v:374.6-374.31" wire \sdram_dfi_p0_rddata_valid attribute \src "ls180.v:367.6-367.26" wire \sdram_dfi_p0_reset_n attribute \src "ls180.v:364.5-364.22" wire \sdram_dfi_p0_we_n attribute \src "ls180.v:369.13-369.32" wire width 16 \sdram_dfi_p0_wrdata attribute \src "ls180.v:370.5-370.27" wire \sdram_dfi_p0_wrdata_en attribute \src "ls180.v:371.12-371.36" wire width 2 \sdram_dfi_p0_wrdata_mask attribute \src "ls180.v:15.20-15.28" wire width 2 output 11 \sdram_dm attribute \src "ls180.v:6.20-6.30" wire width 16 input 2 \sdram_dq_i attribute \src "ls180.v:7.21-7.31" wire width 16 output 3 \sdram_dq_o attribute \src "ls180.v:8.14-8.25" wire output 4 \sdram_dq_oe attribute \src "ls180.v:783.5-783.14" wire \sdram_en0 attribute \src "ls180.v:786.5-786.14" wire \sdram_en1 attribute \src "ls180.v:789.6-789.25" wire \sdram_go_to_refresh attribute \src "ls180.v:331.13-331.39" wire width 22 \sdram_interface_bank0_addr attribute \src "ls180.v:332.6-332.32" wire \sdram_interface_bank0_lock attribute \src "ls180.v:334.6-334.39" wire \sdram_interface_bank0_rdata_valid attribute \src "ls180.v:329.6-329.33" wire \sdram_interface_bank0_ready attribute \src "ls180.v:328.6-328.33" wire \sdram_interface_bank0_valid attribute \src "ls180.v:333.6-333.39" wire \sdram_interface_bank0_wdata_ready attribute \src "ls180.v:330.6-330.30" wire \sdram_interface_bank0_we attribute \src "ls180.v:338.13-338.39" wire width 22 \sdram_interface_bank1_addr attribute \src "ls180.v:339.6-339.32" wire \sdram_interface_bank1_lock attribute \src "ls180.v:341.6-341.39" wire \sdram_interface_bank1_rdata_valid attribute \src "ls180.v:336.6-336.33" wire \sdram_interface_bank1_ready attribute \src "ls180.v:335.6-335.33" wire \sdram_interface_bank1_valid attribute \src "ls180.v:340.6-340.39" wire \sdram_interface_bank1_wdata_ready attribute \src "ls180.v:337.6-337.30" wire \sdram_interface_bank1_we attribute \src "ls180.v:345.13-345.39" wire width 22 \sdram_interface_bank2_addr attribute \src "ls180.v:346.6-346.32" wire \sdram_interface_bank2_lock attribute \src "ls180.v:348.6-348.39" wire \sdram_interface_bank2_rdata_valid attribute \src "ls180.v:343.6-343.33" wire \sdram_interface_bank2_ready attribute \src "ls180.v:342.6-342.33" wire \sdram_interface_bank2_valid attribute \src "ls180.v:347.6-347.39" wire \sdram_interface_bank2_wdata_ready attribute \src "ls180.v:344.6-344.30" wire \sdram_interface_bank2_we attribute \src "ls180.v:352.13-352.39" wire width 22 \sdram_interface_bank3_addr attribute \src "ls180.v:353.6-353.32" wire \sdram_interface_bank3_lock attribute \src "ls180.v:355.6-355.39" wire \sdram_interface_bank3_rdata_valid attribute \src "ls180.v:350.6-350.33" wire \sdram_interface_bank3_ready attribute \src "ls180.v:349.6-349.33" wire \sdram_interface_bank3_valid attribute \src "ls180.v:354.6-354.39" wire \sdram_interface_bank3_wdata_ready attribute \src "ls180.v:351.6-351.30" wire \sdram_interface_bank3_we attribute \src "ls180.v:358.13-358.34" wire width 16 \sdram_interface_rdata attribute \src "ls180.v:356.12-356.33" wire width 16 \sdram_interface_wdata attribute \src "ls180.v:357.11-357.35" wire width 2 \sdram_interface_wdata_we attribute \src "ls180.v:269.5-269.24" wire \sdram_inti_p0_act_n attribute \src "ls180.v:260.13-260.34" wire width 13 \sdram_inti_p0_address attribute \src "ls180.v:261.12-261.30" wire width 2 \sdram_inti_p0_bank attribute \src "ls180.v:262.5-262.24" wire \sdram_inti_p0_cas_n attribute \src "ls180.v:266.6-266.23" wire \sdram_inti_p0_cke attribute \src "ls180.v:263.5-263.23" wire \sdram_inti_p0_cs_n attribute \src "ls180.v:267.6-267.23" wire \sdram_inti_p0_odt attribute \src "ls180.v:264.5-264.24" wire \sdram_inti_p0_ras_n attribute \src "ls180.v:274.12-274.32" wire width 16 \sdram_inti_p0_rddata attribute \src "ls180.v:273.6-273.29" wire \sdram_inti_p0_rddata_en attribute \src "ls180.v:275.5-275.31" wire \sdram_inti_p0_rddata_valid attribute \src "ls180.v:268.6-268.27" wire \sdram_inti_p0_reset_n attribute \src "ls180.v:265.5-265.23" wire \sdram_inti_p0_we_n attribute \src "ls180.v:270.13-270.33" wire width 16 \sdram_inti_p0_wrdata attribute \src "ls180.v:271.6-271.29" wire \sdram_inti_p0_wrdata_en attribute \src "ls180.v:272.12-272.37" wire width 2 \sdram_inti_p0_wrdata_mask attribute \src "ls180.v:301.5-301.26" wire \sdram_master_p0_act_n attribute \src "ls180.v:292.12-292.35" wire width 13 \sdram_master_p0_address attribute \src "ls180.v:293.11-293.31" wire width 2 \sdram_master_p0_bank attribute \src "ls180.v:294.5-294.26" wire \sdram_master_p0_cas_n attribute \src "ls180.v:298.5-298.24" wire \sdram_master_p0_cke attribute \src "ls180.v:295.5-295.25" wire \sdram_master_p0_cs_n attribute \src "ls180.v:299.5-299.24" wire \sdram_master_p0_odt attribute \src "ls180.v:296.5-296.26" wire \sdram_master_p0_ras_n attribute \src "ls180.v:306.13-306.35" wire width 16 \sdram_master_p0_rddata attribute \src "ls180.v:305.5-305.30" wire \sdram_master_p0_rddata_en attribute \src "ls180.v:307.6-307.34" wire \sdram_master_p0_rddata_valid attribute \src "ls180.v:300.5-300.28" wire \sdram_master_p0_reset_n attribute \src "ls180.v:297.5-297.25" wire \sdram_master_p0_we_n attribute \src "ls180.v:302.12-302.34" wire width 16 \sdram_master_p0_wrdata attribute \src "ls180.v:303.5-303.30" wire \sdram_master_p0_wrdata_en attribute \src "ls180.v:304.11-304.38" wire width 2 \sdram_master_p0_wrdata_mask attribute \src "ls180.v:784.6-784.21" wire \sdram_max_time0 attribute \src "ls180.v:787.6-787.21" wire \sdram_max_time1 attribute \src "ls180.v:766.12-766.23" wire width 13 \sdram_nop_a attribute \src "ls180.v:767.11-767.23" wire width 2 \sdram_nop_ba attribute \src "ls180.v:310.6-310.15" wire \sdram_odt attribute \src "ls180.v:393.5-393.26" wire \sdram_postponer_count attribute \src "ls180.v:391.6-391.27" wire \sdram_postponer_req_i attribute \src "ls180.v:392.5-392.26" wire \sdram_postponer_req_o attribute \src "ls180.v:728.6-728.23" wire \sdram_ras_allowed attribute \src "ls180.v:10.14-10.25" wire output 6 \sdram_ras_n attribute \src "ls180.v:313.5-313.13" wire \sdram_re attribute \src "ls180.v:781.6-781.26" wire \sdram_read_available attribute \src "ls180.v:311.6-311.19" wire \sdram_reset_n attribute \src "ls180.v:308.6-308.15" wire \sdram_sel attribute \src "ls180.v:399.5-399.26" wire \sdram_sequencer_count attribute \src "ls180.v:398.11-398.34" wire width 4 \sdram_sequencer_counter attribute \src "ls180.v:395.6-395.27" wire \sdram_sequencer_done0 attribute \src "ls180.v:397.5-397.26" wire \sdram_sequencer_done1 attribute \src "ls180.v:394.5-394.27" wire \sdram_sequencer_start0 attribute \src "ls180.v:396.6-396.28" wire \sdram_sequencer_start1 attribute \src "ls180.v:285.6-285.26" wire \sdram_slave_p0_act_n attribute \src "ls180.v:276.13-276.35" wire width 13 \sdram_slave_p0_address attribute \src "ls180.v:277.12-277.31" wire width 2 \sdram_slave_p0_bank attribute \src "ls180.v:278.6-278.26" wire \sdram_slave_p0_cas_n attribute \src "ls180.v:282.6-282.24" wire \sdram_slave_p0_cke attribute \src "ls180.v:279.6-279.25" wire \sdram_slave_p0_cs_n attribute \src "ls180.v:283.6-283.24" wire \sdram_slave_p0_odt attribute \src "ls180.v:280.6-280.26" wire \sdram_slave_p0_ras_n attribute \src "ls180.v:290.12-290.33" wire width 16 \sdram_slave_p0_rddata attribute \src "ls180.v:289.6-289.30" wire \sdram_slave_p0_rddata_en attribute \src "ls180.v:291.5-291.32" wire \sdram_slave_p0_rddata_valid attribute \src "ls180.v:284.6-284.28" wire \sdram_slave_p0_reset_n attribute \src "ls180.v:281.6-281.25" wire \sdram_slave_p0_we_n attribute \src "ls180.v:286.13-286.34" wire width 16 \sdram_slave_p0_wrdata attribute \src "ls180.v:287.6-287.30" wire \sdram_slave_p0_wrdata_en attribute \src "ls180.v:288.12-288.38" wire width 2 \sdram_slave_p0_wrdata_mask attribute \src "ls180.v:326.12-326.24" wire width 16 \sdram_status attribute \src "ls180.v:769.5-769.19" wire \sdram_steerer0 attribute \src "ls180.v:770.5-770.19" wire \sdram_steerer1 attribute \src "ls180.v:768.11-768.28" wire width 2 \sdram_steerer_sel attribute \src "ls180.v:312.11-312.24" wire width 4 \sdram_storage attribute \src "ls180.v:777.5-777.24" wire \sdram_tccdcon_count attribute \no_retiming "true" attribute \src "ls180.v:776.32-776.51" wire \sdram_tccdcon_ready attribute \src "ls180.v:775.6-775.25" wire \sdram_tccdcon_valid attribute \no_retiming "true" attribute \src "ls180.v:774.32-774.51" wire \sdram_tfawcon_ready attribute \src "ls180.v:773.6-773.25" wire \sdram_tfawcon_valid attribute \src "ls180.v:785.11-785.22" wire width 5 \sdram_time0 attribute \src "ls180.v:788.11-788.22" wire width 4 \sdram_time1 attribute \src "ls180.v:388.12-388.30" wire width 10 \sdram_timer_count0 attribute \src "ls180.v:390.11-390.29" wire width 10 \sdram_timer_count1 attribute \src "ls180.v:387.6-387.23" wire \sdram_timer_done0 attribute \src "ls180.v:389.6-389.23" wire \sdram_timer_done1 attribute \src "ls180.v:386.6-386.22" wire \sdram_timer_wait attribute \no_retiming "true" attribute \src "ls180.v:772.32-772.51" wire \sdram_trrdcon_ready attribute \src "ls180.v:771.6-771.25" wire \sdram_trrdcon_valid attribute \src "ls180.v:780.11-780.30" wire width 3 \sdram_twtrcon_count attribute \no_retiming "true" attribute \src "ls180.v:779.32-779.51" wire \sdram_twtrcon_ready attribute \src "ls180.v:778.6-778.25" wire \sdram_twtrcon_valid attribute \src "ls180.v:385.6-385.25" wire \sdram_wants_refresh attribute \src "ls180.v:327.6-327.14" wire \sdram_we attribute \src "ls180.v:9.14-9.24" wire output 5 \sdram_we_n attribute \src "ls180.v:325.5-325.20" wire \sdram_wrdata_re attribute \src "ls180.v:324.12-324.32" wire width 16 \sdram_wrdata_storage attribute \src "ls180.v:782.6-782.27" wire \sdram_write_available attribute \src "ls180.v:1382.6-1382.15" wire \sdrio_clk attribute \src "ls180.v:1383.6-1383.17" wire \sdrio_clk_1 attribute \src "ls180.v:1392.6-1392.18" wire \sdrio_clk_10 attribute \src "ls180.v:1484.6-1484.19" wire \sdrio_clk_100 attribute \src "ls180.v:1485.6-1485.19" wire \sdrio_clk_101 attribute \src "ls180.v:1486.6-1486.19" wire \sdrio_clk_102 attribute \src "ls180.v:1487.6-1487.19" wire \sdrio_clk_103 attribute \src "ls180.v:1393.6-1393.18" wire \sdrio_clk_11 attribute \src "ls180.v:1394.6-1394.18" wire \sdrio_clk_12 attribute \src "ls180.v:1395.6-1395.18" wire \sdrio_clk_13 attribute \src "ls180.v:1396.6-1396.18" wire \sdrio_clk_14 attribute \src "ls180.v:1397.6-1397.18" wire \sdrio_clk_15 attribute \src "ls180.v:1398.6-1398.18" wire \sdrio_clk_16 attribute \src "ls180.v:1399.6-1399.18" wire \sdrio_clk_17 attribute \src "ls180.v:1400.6-1400.18" wire \sdrio_clk_18 attribute \src "ls180.v:1401.6-1401.18" wire \sdrio_clk_19 attribute \src "ls180.v:1384.6-1384.17" wire \sdrio_clk_2 attribute \src "ls180.v:1402.6-1402.18" wire \sdrio_clk_20 attribute \src "ls180.v:1403.6-1403.18" wire \sdrio_clk_21 attribute \src "ls180.v:1404.6-1404.18" wire \sdrio_clk_22 attribute \src "ls180.v:1405.6-1405.18" wire \sdrio_clk_23 attribute \src "ls180.v:1406.6-1406.18" wire \sdrio_clk_24 attribute \src "ls180.v:1407.6-1407.18" wire \sdrio_clk_25 attribute \src "ls180.v:1408.6-1408.18" wire \sdrio_clk_26 attribute \src "ls180.v:1409.6-1409.18" wire \sdrio_clk_27 attribute \src "ls180.v:1410.6-1410.18" wire \sdrio_clk_28 attribute \src "ls180.v:1411.6-1411.18" wire \sdrio_clk_29 attribute \src "ls180.v:1385.6-1385.17" wire \sdrio_clk_3 attribute \src "ls180.v:1412.6-1412.18" wire \sdrio_clk_30 attribute \src "ls180.v:1413.6-1413.18" wire \sdrio_clk_31 attribute \src "ls180.v:1414.6-1414.18" wire \sdrio_clk_32 attribute \src "ls180.v:1415.6-1415.18" wire \sdrio_clk_33 attribute \src "ls180.v:1416.6-1416.18" wire \sdrio_clk_34 attribute \src "ls180.v:1417.6-1417.18" wire \sdrio_clk_35 attribute \src "ls180.v:1418.6-1418.18" wire \sdrio_clk_36 attribute \src "ls180.v:1419.6-1419.18" wire \sdrio_clk_37 attribute \src "ls180.v:1420.6-1420.18" wire \sdrio_clk_38 attribute \src "ls180.v:1421.6-1421.18" wire \sdrio_clk_39 attribute \src "ls180.v:1386.6-1386.17" wire \sdrio_clk_4 attribute \src "ls180.v:1422.6-1422.18" wire \sdrio_clk_40 attribute \src "ls180.v:1423.6-1423.18" wire \sdrio_clk_41 attribute \src "ls180.v:1424.6-1424.18" wire \sdrio_clk_42 attribute \src "ls180.v:1425.6-1425.18" wire \sdrio_clk_43 attribute \src "ls180.v:1426.6-1426.18" wire \sdrio_clk_44 attribute \src "ls180.v:1427.6-1427.18" wire \sdrio_clk_45 attribute \src "ls180.v:1428.6-1428.18" wire \sdrio_clk_46 attribute \src "ls180.v:1429.6-1429.18" wire \sdrio_clk_47 attribute \src "ls180.v:1430.6-1430.18" wire \sdrio_clk_48 attribute \src "ls180.v:1431.6-1431.18" wire \sdrio_clk_49 attribute \src "ls180.v:1387.6-1387.17" wire \sdrio_clk_5 attribute \src "ls180.v:1432.6-1432.18" wire \sdrio_clk_50 attribute \src "ls180.v:1433.6-1433.18" wire \sdrio_clk_51 attribute \src "ls180.v:1434.6-1434.18" wire \sdrio_clk_52 attribute \src "ls180.v:1435.6-1435.18" wire \sdrio_clk_53 attribute \src "ls180.v:1436.6-1436.18" wire \sdrio_clk_54 attribute \src "ls180.v:1437.6-1437.18" wire \sdrio_clk_55 attribute \src "ls180.v:1440.6-1440.18" wire \sdrio_clk_56 attribute \src "ls180.v:1441.6-1441.18" wire \sdrio_clk_57 attribute \src "ls180.v:1442.6-1442.18" wire \sdrio_clk_58 attribute \src "ls180.v:1443.6-1443.18" wire \sdrio_clk_59 attribute \src "ls180.v:1388.6-1388.17" wire \sdrio_clk_6 attribute \src "ls180.v:1444.6-1444.18" wire \sdrio_clk_60 attribute \src "ls180.v:1445.6-1445.18" wire \sdrio_clk_61 attribute \src "ls180.v:1446.6-1446.18" wire \sdrio_clk_62 attribute \src "ls180.v:1447.6-1447.18" wire \sdrio_clk_63 attribute \src "ls180.v:1448.6-1448.18" wire \sdrio_clk_64 attribute \src "ls180.v:1449.6-1449.18" wire \sdrio_clk_65 attribute \src "ls180.v:1450.6-1450.18" wire \sdrio_clk_66 attribute \src "ls180.v:1451.6-1451.18" wire \sdrio_clk_67 attribute \src "ls180.v:1452.6-1452.18" wire \sdrio_clk_68 attribute \src "ls180.v:1453.6-1453.18" wire \sdrio_clk_69 attribute \src "ls180.v:1389.6-1389.17" wire \sdrio_clk_7 attribute \src "ls180.v:1454.6-1454.18" wire \sdrio_clk_70 attribute \src "ls180.v:1455.6-1455.18" wire \sdrio_clk_71 attribute \src "ls180.v:1456.6-1456.18" wire \sdrio_clk_72 attribute \src "ls180.v:1457.6-1457.18" wire \sdrio_clk_73 attribute \src "ls180.v:1458.6-1458.18" wire \sdrio_clk_74 attribute \src "ls180.v:1459.6-1459.18" wire \sdrio_clk_75 attribute \src "ls180.v:1460.6-1460.18" wire \sdrio_clk_76 attribute \src "ls180.v:1461.6-1461.18" wire \sdrio_clk_77 attribute \src "ls180.v:1462.6-1462.18" wire \sdrio_clk_78 attribute \src "ls180.v:1463.6-1463.18" wire \sdrio_clk_79 attribute \src "ls180.v:1390.6-1390.17" wire \sdrio_clk_8 attribute \src "ls180.v:1464.6-1464.18" wire \sdrio_clk_80 attribute \src "ls180.v:1465.6-1465.18" wire \sdrio_clk_81 attribute \src "ls180.v:1466.6-1466.18" wire \sdrio_clk_82 attribute \src "ls180.v:1467.6-1467.18" wire \sdrio_clk_83 attribute \src "ls180.v:1468.6-1468.18" wire \sdrio_clk_84 attribute \src "ls180.v:1469.6-1469.18" wire \sdrio_clk_85 attribute \src "ls180.v:1470.6-1470.18" wire \sdrio_clk_86 attribute \src "ls180.v:1471.6-1471.18" wire \sdrio_clk_87 attribute \src "ls180.v:1472.6-1472.18" wire \sdrio_clk_88 attribute \src "ls180.v:1473.6-1473.18" wire \sdrio_clk_89 attribute \src "ls180.v:1391.6-1391.17" wire \sdrio_clk_9 attribute \src "ls180.v:1474.6-1474.18" wire \sdrio_clk_90 attribute \src "ls180.v:1475.6-1475.18" wire \sdrio_clk_91 attribute \src "ls180.v:1476.6-1476.18" wire \sdrio_clk_92 attribute \src "ls180.v:1477.6-1477.18" wire \sdrio_clk_93 attribute \src "ls180.v:1478.6-1478.18" wire \sdrio_clk_94 attribute \src "ls180.v:1479.6-1479.18" wire \sdrio_clk_95 attribute \src "ls180.v:1480.6-1480.18" wire \sdrio_clk_96 attribute \src "ls180.v:1481.6-1481.18" wire \sdrio_clk_97 attribute \src "ls180.v:1482.6-1482.18" wire \sdrio_clk_98 attribute \src "ls180.v:1483.6-1483.18" wire \sdrio_clk_99 attribute \src "ls180.v:17.14-17.27" wire output 13 \spimaster_clk attribute \src "ls180.v:19.14-19.28" wire output 15 \spimaster_cs_n attribute \src "ls180.v:20.13-20.27" wire input 16 \spimaster_miso attribute \src "ls180.v:18.14-18.28" wire output 14 \spimaster_mosi attribute \src "ls180.v:1017.11-1017.47" wire width 3 \subfragments_bankmachine0_next_state attribute \src "ls180.v:1016.11-1016.42" wire width 3 \subfragments_bankmachine0_state attribute \src "ls180.v:1019.11-1019.47" wire width 3 \subfragments_bankmachine1_next_state attribute \src "ls180.v:1018.11-1018.42" wire width 3 \subfragments_bankmachine1_state attribute \src "ls180.v:1021.11-1021.47" wire width 3 \subfragments_bankmachine2_next_state attribute \src "ls180.v:1020.11-1020.42" wire width 3 \subfragments_bankmachine2_state attribute \src "ls180.v:1023.11-1023.47" wire width 3 \subfragments_bankmachine3_next_state attribute \src "ls180.v:1022.11-1022.42" wire width 3 \subfragments_bankmachine3_state attribute \src "ls180.v:1003.5-1003.39" wire \subfragments_converter0_next_state attribute \src "ls180.v:1002.5-1002.34" wire \subfragments_converter0_state attribute \src "ls180.v:1007.5-1007.39" wire \subfragments_converter1_next_state attribute \src "ls180.v:1006.5-1006.34" wire \subfragments_converter1_state attribute \src "ls180.v:1011.5-1011.39" wire \subfragments_converter2_next_state attribute \src "ls180.v:1010.5-1010.34" wire \subfragments_converter2_state attribute \src "ls180.v:1038.5-1038.25" wire \subfragments_locked0 attribute \src "ls180.v:1039.5-1039.25" wire \subfragments_locked1 attribute \src "ls180.v:1040.5-1040.25" wire \subfragments_locked2 attribute \src "ls180.v:1041.5-1041.25" wire \subfragments_locked3 attribute \src "ls180.v:1025.11-1025.46" wire width 3 \subfragments_multiplexer_next_state attribute \src "ls180.v:1024.11-1024.41" wire width 3 \subfragments_multiplexer_state attribute \src "ls180.v:1043.5-1043.41" wire \subfragments_new_master_rdata_valid0 attribute \src "ls180.v:1044.5-1044.41" wire \subfragments_new_master_rdata_valid1 attribute \src "ls180.v:1045.5-1045.41" wire \subfragments_new_master_rdata_valid2 attribute \src "ls180.v:1046.5-1046.41" wire \subfragments_new_master_rdata_valid3 attribute \src "ls180.v:1042.5-1042.40" wire \subfragments_new_master_wdata_ready attribute \src "ls180.v:1048.5-1048.28" wire \subfragments_next_state attribute \src "ls180.v:1015.11-1015.44" wire width 2 \subfragments_refresher_next_state attribute \src "ls180.v:1014.11-1014.39" wire width 2 \subfragments_refresher_state attribute \src "ls180.v:1028.6-1028.33" wire \subfragments_roundrobin0_ce attribute \src "ls180.v:1027.6-1027.36" wire \subfragments_roundrobin0_grant attribute \src "ls180.v:1026.6-1026.38" wire \subfragments_roundrobin0_request attribute \src "ls180.v:1031.6-1031.33" wire \subfragments_roundrobin1_ce attribute \src "ls180.v:1030.6-1030.36" wire \subfragments_roundrobin1_grant attribute \src "ls180.v:1029.6-1029.38" wire \subfragments_roundrobin1_request attribute \src "ls180.v:1034.6-1034.33" wire \subfragments_roundrobin2_ce attribute \src "ls180.v:1033.6-1033.36" wire \subfragments_roundrobin2_grant attribute \src "ls180.v:1032.6-1032.38" wire \subfragments_roundrobin2_request attribute \src "ls180.v:1037.6-1037.33" wire \subfragments_roundrobin3_ce attribute \src "ls180.v:1036.6-1036.36" wire \subfragments_roundrobin3_grant attribute \src "ls180.v:1035.6-1035.38" wire \subfragments_roundrobin3_request attribute \src "ls180.v:1047.5-1047.23" wire \subfragments_state attribute \src "ls180.v:33.13-33.20" wire input 29 \sys_clk attribute \src "ls180.v:239.6-239.15" wire \sys_clk_1 attribute \src "ls180.v:34.13-34.20" wire input 30 \sys_rst attribute \src "ls180.v:240.6-240.15" wire \sys_rst_1 attribute \src "ls180.v:1343.5-1343.19" wire \t_array_muxed0 attribute \src "ls180.v:1344.5-1344.19" wire \t_array_muxed1 attribute \src "ls180.v:1345.5-1345.19" wire \t_array_muxed2 attribute \src "ls180.v:1352.5-1352.19" wire \t_array_muxed3 attribute \src "ls180.v:1353.5-1353.19" wire \t_array_muxed4 attribute \src "ls180.v:1354.5-1354.19" wire \t_array_muxed5 attribute \src "ls180.v:867.5-867.13" wire \tx_clear attribute \src "ls180.v:919.11-919.26" wire width 4 \tx_fifo_consume attribute \src "ls180.v:924.6-924.21" wire \tx_fifo_do_read attribute \src "ls180.v:930.6-930.27" wire \tx_fifo_fifo_in_first attribute \src "ls180.v:931.6-931.26" wire \tx_fifo_fifo_in_last attribute \src "ls180.v:929.12-929.40" wire width 8 \tx_fifo_fifo_in_payload_data attribute \src "ls180.v:933.6-933.28" wire \tx_fifo_fifo_out_first attribute \src "ls180.v:934.6-934.27" wire \tx_fifo_fifo_out_last attribute \src "ls180.v:932.12-932.41" wire width 8 \tx_fifo_fifo_out_payload_data attribute \src "ls180.v:916.11-916.25" wire width 5 \tx_fifo_level0 attribute \src "ls180.v:928.12-928.26" wire width 5 \tx_fifo_level1 attribute \src "ls180.v:918.11-918.26" wire width 4 \tx_fifo_produce attribute \src "ls180.v:925.12-925.30" wire width 4 \tx_fifo_rdport_adr attribute \src "ls180.v:926.12-926.32" wire width 10 \tx_fifo_rdport_dat_r attribute \src "ls180.v:927.6-927.23" wire \tx_fifo_rdport_re attribute \src "ls180.v:908.6-908.16" wire \tx_fifo_re attribute \src "ls180.v:909.5-909.21" wire \tx_fifo_readable attribute \src "ls180.v:917.5-917.20" wire \tx_fifo_replace attribute \src "ls180.v:900.5-900.23" wire \tx_fifo_sink_first attribute \src "ls180.v:901.5-901.22" wire \tx_fifo_sink_last attribute \src "ls180.v:902.12-902.37" wire width 8 \tx_fifo_sink_payload_data attribute \src "ls180.v:899.6-899.24" wire \tx_fifo_sink_ready attribute \src "ls180.v:898.6-898.24" wire \tx_fifo_sink_valid attribute \src "ls180.v:905.6-905.26" wire \tx_fifo_source_first attribute \src "ls180.v:906.6-906.25" wire \tx_fifo_source_last attribute \src "ls180.v:907.12-907.39" wire width 8 \tx_fifo_source_payload_data attribute \src "ls180.v:904.6-904.26" wire \tx_fifo_source_ready attribute \src "ls180.v:903.6-903.26" wire \tx_fifo_source_valid attribute \src "ls180.v:914.12-914.32" wire width 10 \tx_fifo_syncfifo_din attribute \src "ls180.v:915.12-915.33" wire width 10 \tx_fifo_syncfifo_dout attribute \src "ls180.v:912.6-912.25" wire \tx_fifo_syncfifo_re attribute \src "ls180.v:913.6-913.31" wire \tx_fifo_syncfifo_readable attribute \src "ls180.v:910.6-910.25" wire \tx_fifo_syncfifo_we attribute \src "ls180.v:911.6-911.31" wire \tx_fifo_syncfifo_writable attribute \src "ls180.v:920.11-920.29" wire width 4 \tx_fifo_wrport_adr attribute \src "ls180.v:921.12-921.32" wire width 10 \tx_fifo_wrport_dat_r attribute \src "ls180.v:923.12-923.32" wire width 10 \tx_fifo_wrport_dat_w attribute \src "ls180.v:922.6-922.23" wire \tx_fifo_wrport_we attribute \src "ls180.v:868.5-868.19" wire \tx_old_trigger attribute \src "ls180.v:865.5-865.15" wire \tx_pending attribute \src "ls180.v:864.6-864.15" wire \tx_status attribute \src "ls180.v:866.6-866.16" wire \tx_trigger attribute \src "ls180.v:884.6-884.20" wire \txempty_status attribute \src "ls180.v:885.6-885.16" wire \txempty_we attribute \src "ls180.v:859.6-859.19" wire \txfull_status attribute \src "ls180.v:860.6-860.15" wire \txfull_we attribute \src "ls180.v:849.12-849.41" wire width 32 \uart_phy_phase_accumulator_rx attribute \src "ls180.v:839.12-839.41" wire width 32 \uart_phy_phase_accumulator_tx attribute \src "ls180.v:832.5-832.16" wire \uart_phy_re attribute \src "ls180.v:850.6-850.17" wire \uart_phy_rx attribute \src "ls180.v:853.11-853.31" wire width 4 \uart_phy_rx_bitcount attribute \src "ls180.v:854.5-854.21" wire \uart_phy_rx_busy attribute \src "ls180.v:851.5-851.18" wire \uart_phy_rx_r attribute \src "ls180.v:852.11-852.26" wire width 8 \uart_phy_rx_reg attribute \src "ls180.v:835.6-835.25" wire \uart_phy_sink_first attribute \src "ls180.v:836.6-836.24" wire \uart_phy_sink_last attribute \src "ls180.v:837.12-837.38" wire width 8 \uart_phy_sink_payload_data attribute \src "ls180.v:834.5-834.24" wire \uart_phy_sink_ready attribute \src "ls180.v:833.6-833.25" wire \uart_phy_sink_valid attribute \src "ls180.v:845.5-845.26" wire \uart_phy_source_first attribute \src "ls180.v:846.5-846.25" wire \uart_phy_source_last attribute \src "ls180.v:847.11-847.39" wire width 8 \uart_phy_source_payload_data attribute \src "ls180.v:844.6-844.27" wire \uart_phy_source_ready attribute \src "ls180.v:843.5-843.26" wire \uart_phy_source_valid attribute \src "ls180.v:831.12-831.28" wire width 32 \uart_phy_storage attribute \src "ls180.v:841.11-841.31" wire width 4 \uart_phy_tx_bitcount attribute \src "ls180.v:842.5-842.21" wire \uart_phy_tx_busy attribute \src "ls180.v:840.11-840.26" wire width 8 \uart_phy_tx_reg attribute \src "ls180.v:848.5-848.27" wire \uart_phy_uart_clk_rxen attribute \src "ls180.v:838.5-838.27" wire \uart_phy_uart_clk_txen attribute \src "ls180.v:29.13-29.20" wire input 25 \uart_rx attribute \src "ls180.v:890.6-890.21" wire \uart_sink_first attribute \src "ls180.v:891.6-891.20" wire \uart_sink_last attribute \src "ls180.v:892.12-892.34" wire width 8 \uart_sink_payload_data attribute \src "ls180.v:889.6-889.21" wire \uart_sink_ready attribute \src "ls180.v:888.6-888.21" wire \uart_sink_valid attribute \src "ls180.v:895.6-895.23" wire \uart_source_first attribute \src "ls180.v:896.6-896.22" wire \uart_source_last attribute \src "ls180.v:897.12-897.36" wire width 8 \uart_source_payload_data attribute \src "ls180.v:894.6-894.23" wire \uart_source_ready attribute \src "ls180.v:893.6-893.23" wire \uart_source_valid attribute \src "ls180.v:28.13-28.20" wire input 24 \uart_tx attribute \src "ls180.v:809.5-809.17" wire \wb_sdram_ack attribute \src "ls180.v:803.13-803.25" wire width 30 \wb_sdram_adr attribute \src "ls180.v:812.12-812.24" wire width 2 \wb_sdram_bte attribute \src "ls180.v:811.12-811.24" wire width 3 \wb_sdram_cti attribute \src "ls180.v:807.6-807.18" wire \wb_sdram_cyc attribute \src "ls180.v:805.13-805.27" wire width 32 \wb_sdram_dat_r attribute \src "ls180.v:804.13-804.27" wire width 32 \wb_sdram_dat_w attribute \src "ls180.v:813.5-813.17" wire \wb_sdram_err attribute \src "ls180.v:806.12-806.24" wire width 4 \wb_sdram_sel attribute \src "ls180.v:808.6-808.18" wire \wb_sdram_stb attribute \src "ls180.v:810.6-810.17" wire \wb_sdram_we attribute \src "ls180.v:827.5-827.19" wire \wdata_consumed attribute \src "ls180.v:5488.12-5488.15" memory width 32 size 128 \mem attribute \src "ls180.v:5508.12-5508.17" memory width 32 size 32 \mem_1 attribute \src "ls180.v:5528.12-5528.19" memory width 25 size 8 \storage attribute \src "ls180.v:5542.12-5542.21" memory width 25 size 8 \storage_1 attribute \src "ls180.v:5556.12-5556.21" memory width 25 size 8 \storage_2 attribute \src "ls180.v:5570.12-5570.21" memory width 25 size 8 \storage_3 attribute \src "ls180.v:5584.11-5584.20" memory width 10 size 16 \storage_4 attribute \src "ls180.v:5601.11-5601.20" memory width 10 size 16 \storage_5 attribute \src "ls180.v:1552.76-1552.113" cell $add $add$ls180.v:1552$25 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_counter connect \B 1'1 connect \Y $add$ls180.v:1552$25_Y end attribute \src "ls180.v:1612.76-1612.113" cell $add $add$ls180.v:1612$36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_counter connect \B 1'1 connect \Y $add$ls180.v:1612$36_Y end attribute \src "ls180.v:1672.76-1672.113" cell $add $add$ls180.v:1672$47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_counter connect \B 1'1 connect \Y $add$ls180.v:1672$47_Y end attribute \src "ls180.v:2815.52-2815.76" cell $add $add$ls180.v:2815$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \converter_counter connect \B 1'1 connect \Y $add$ls180.v:2815$553_Y end attribute \src "ls180.v:2915.26-2915.59" cell $add $add$ls180.v:2915$599 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \tx_fifo_level0 connect \B \tx_fifo_readable connect \Y $add$ls180.v:2915$599_Y end attribute \src "ls180.v:2945.26-2945.59" cell $add $add$ls180.v:2945$610 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \rx_fifo_level0 connect \B \rx_fifo_readable connect \Y $add$ls180.v:2945$610_Y end attribute \src "ls180.v:4352.31-4352.60" cell $add $add$ls180.v:4352$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 32 connect \A \libresocsim_bus_errors connect \B 1'1 connect \Y $add$ls180.v:4352$1260_Y end attribute \src "ls180.v:4441.32-4441.62" cell $add $add$ls180.v:4441$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_sequencer_counter connect \B 1'1 connect \Y $add$ls180.v:4441$1284_Y end attribute \src "ls180.v:4458.55-4458.109" cell $add $add$ls180.v:4458$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $add$ls180.v:4458$1288_Y end attribute \src "ls180.v:4461.55-4461.109" cell $add $add$ls180.v:4461$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 connect \Y $add$ls180.v:4461$1289_Y end attribute \src "ls180.v:4465.54-4465.106" cell $add $add$ls180.v:4465$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $add$ls180.v:4465$1294_Y end attribute \src "ls180.v:4504.55-4504.109" cell $add $add$ls180.v:4504$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $add$ls180.v:4504$1304_Y end attribute \src "ls180.v:4507.55-4507.109" cell $add $add$ls180.v:4507$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 connect \Y $add$ls180.v:4507$1305_Y end attribute \src "ls180.v:4511.54-4511.106" cell $add $add$ls180.v:4511$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $add$ls180.v:4511$1310_Y end attribute \src "ls180.v:4550.55-4550.109" cell $add $add$ls180.v:4550$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $add$ls180.v:4550$1320_Y end attribute \src "ls180.v:4553.55-4553.109" cell $add $add$ls180.v:4553$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 connect \Y $add$ls180.v:4553$1321_Y end attribute \src "ls180.v:4557.54-4557.106" cell $add $add$ls180.v:4557$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $add$ls180.v:4557$1326_Y end attribute \src "ls180.v:4596.55-4596.109" cell $add $add$ls180.v:4596$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $add$ls180.v:4596$1336_Y end attribute \src "ls180.v:4599.55-4599.109" cell $add $add$ls180.v:4599$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 connect \Y $add$ls180.v:4599$1337_Y end attribute \src "ls180.v:4603.54-4603.106" cell $add $add$ls180.v:4603$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $add$ls180.v:4603$1342_Y end attribute \src "ls180.v:4833.29-4833.56" cell $add $add$ls180.v:4833$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \uart_phy_tx_bitcount connect \B 1'1 connect \Y $add$ls180.v:4833$1396_Y end attribute \src "ls180.v:4849.63-4849.111" cell $add $add$ls180.v:4849$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 connect \A \uart_phy_phase_accumulator_tx connect \B \uart_phy_storage connect \Y $add$ls180.v:4849$1399_Y end attribute \src "ls180.v:4862.29-4862.56" cell $add $add$ls180.v:4862$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \uart_phy_rx_bitcount connect \B 1'1 connect \Y $add$ls180.v:4862$1403_Y end attribute \src "ls180.v:4881.63-4881.111" cell $add $add$ls180.v:4881$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 connect \A \uart_phy_phase_accumulator_rx connect \B \uart_phy_storage connect \Y $add$ls180.v:4881$1406_Y end attribute \src "ls180.v:4907.23-4907.45" cell $add $add$ls180.v:4907$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \tx_fifo_produce connect \B 1'1 connect \Y $add$ls180.v:4907$1414_Y end attribute \src "ls180.v:4910.23-4910.45" cell $add $add$ls180.v:4910$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \tx_fifo_consume connect \B 1'1 connect \Y $add$ls180.v:4910$1415_Y end attribute \src "ls180.v:4914.23-4914.44" cell $add $add$ls180.v:4914$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \tx_fifo_level0 connect \B 1'1 connect \Y $add$ls180.v:4914$1420_Y end attribute \src "ls180.v:4929.23-4929.45" cell $add $add$ls180.v:4929$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \rx_fifo_produce connect \B 1'1 connect \Y $add$ls180.v:4929$1425_Y end attribute \src "ls180.v:4932.23-4932.45" cell $add $add$ls180.v:4932$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \rx_fifo_consume connect \B 1'1 connect \Y $add$ls180.v:4932$1426_Y end attribute \src "ls180.v:4936.23-4936.44" cell $add $add$ls180.v:4936$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \rx_fifo_level0 connect \B 1'1 connect \Y $add$ls180.v:4936$1431_Y end attribute \src "ls180.v:1546.9-1546.70" cell $and $and$ls180.v:1546$20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_ibus_stb connect \B \libresocsim_libresoc_ibus_cyc connect \Y $and$ls180.v:1546$20_Y end attribute \src "ls180.v:1564.9-1564.70" cell $and $and$ls180.v:1564$27 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_ibus_stb connect \B \libresocsim_libresoc_ibus_cyc connect \Y $and$ls180.v:1564$27_Y end attribute \src "ls180.v:1606.9-1606.70" cell $and $and$ls180.v:1606$31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_dbus_stb connect \B \libresocsim_libresoc_dbus_cyc connect \Y $and$ls180.v:1606$31_Y end attribute \src "ls180.v:1624.9-1624.70" cell $and $and$ls180.v:1624$38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_dbus_stb connect \B \libresocsim_libresoc_dbus_cyc connect \Y $and$ls180.v:1624$38_Y end attribute \src "ls180.v:1666.9-1666.76" cell $and $and$ls180.v:1666$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_jtag_wb_stb connect \B \libresocsim_libresoc_jtag_wb_cyc connect \Y $and$ls180.v:1666$42_Y end attribute \src "ls180.v:1684.9-1684.76" cell $and $and$ls180.v:1684$49 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_jtag_wb_stb connect \B \libresocsim_libresoc_jtag_wb_cyc connect \Y $and$ls180.v:1684$49_Y end attribute \src "ls180.v:1694.26-1694.75" cell $and $and$ls180.v:1694$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb connect \Y $and$ls180.v:1694$51_Y end attribute \src "ls180.v:1694.25-1694.101" cell $and $and$ls180.v:1694$52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1694$51_Y connect \B \libresocsim_ram_bus_we connect \Y $and$ls180.v:1694$52_Y end attribute \src "ls180.v:1694.24-1694.131" cell $and $and$ls180.v:1694$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1694$52_Y connect \B \libresocsim_ram_bus_sel [0] connect \Y $and$ls180.v:1694$53_Y end attribute \src "ls180.v:1695.26-1695.75" cell $and $and$ls180.v:1695$54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb connect \Y $and$ls180.v:1695$54_Y end attribute \src "ls180.v:1695.25-1695.101" cell $and $and$ls180.v:1695$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1695$54_Y connect \B \libresocsim_ram_bus_we connect \Y $and$ls180.v:1695$55_Y end attribute \src "ls180.v:1695.24-1695.131" cell $and $and$ls180.v:1695$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1695$55_Y connect \B \libresocsim_ram_bus_sel [1] connect \Y $and$ls180.v:1695$56_Y end attribute \src "ls180.v:1696.26-1696.75" cell $and $and$ls180.v:1696$57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb connect \Y $and$ls180.v:1696$57_Y end attribute \src "ls180.v:1696.25-1696.101" cell $and $and$ls180.v:1696$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1696$57_Y connect \B \libresocsim_ram_bus_we connect \Y $and$ls180.v:1696$58_Y end attribute \src "ls180.v:1696.24-1696.131" cell $and $and$ls180.v:1696$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1696$58_Y connect \B \libresocsim_ram_bus_sel [2] connect \Y $and$ls180.v:1696$59_Y end attribute \src "ls180.v:1697.26-1697.75" cell $and $and$ls180.v:1697$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb connect \Y $and$ls180.v:1697$60_Y end attribute \src "ls180.v:1697.25-1697.101" cell $and $and$ls180.v:1697$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1697$60_Y connect \B \libresocsim_ram_bus_we connect \Y $and$ls180.v:1697$61_Y end attribute \src "ls180.v:1697.24-1697.131" cell $and $and$ls180.v:1697$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1697$61_Y connect \B \libresocsim_ram_bus_sel [3] connect \Y $and$ls180.v:1697$62_Y end attribute \src "ls180.v:1706.7-1706.79" cell $and $and$ls180.v:1706$65 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_eventmanager_pending_re connect \B \libresocsim_eventmanager_pending_r connect \Y $and$ls180.v:1706$65_Y end attribute \src "ls180.v:1711.27-1711.96" cell $and $and$ls180.v:1711$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_eventmanager_pending_w connect \B \libresocsim_eventmanager_storage connect \Y $and$ls180.v:1711$66_Y end attribute \src "ls180.v:1715.18-1715.59" cell $and $and$ls180.v:1715$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb connect \Y $and$ls180.v:1715$68_Y end attribute \src "ls180.v:1715.17-1715.81" cell $and $and$ls180.v:1715$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1715$68_Y connect \B \ram_bus_ram_bus_we connect \Y $and$ls180.v:1715$69_Y end attribute \src "ls180.v:1715.16-1715.107" cell $and $and$ls180.v:1715$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1715$69_Y connect \B \ram_bus_ram_bus_sel [0] connect \Y $and$ls180.v:1715$70_Y end attribute \src "ls180.v:1716.18-1716.59" cell $and $and$ls180.v:1716$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb connect \Y $and$ls180.v:1716$71_Y end attribute \src "ls180.v:1716.17-1716.81" cell $and $and$ls180.v:1716$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1716$71_Y connect \B \ram_bus_ram_bus_we connect \Y $and$ls180.v:1716$72_Y end attribute \src "ls180.v:1716.16-1716.107" cell $and $and$ls180.v:1716$73 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1716$72_Y connect \B \ram_bus_ram_bus_sel [1] connect \Y $and$ls180.v:1716$73_Y end attribute \src "ls180.v:1717.18-1717.59" cell $and $and$ls180.v:1717$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb connect \Y $and$ls180.v:1717$74_Y end attribute \src "ls180.v:1717.17-1717.81" cell $and $and$ls180.v:1717$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1717$74_Y connect \B \ram_bus_ram_bus_we connect \Y $and$ls180.v:1717$75_Y end attribute \src "ls180.v:1717.16-1717.107" cell $and $and$ls180.v:1717$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1717$75_Y connect \B \ram_bus_ram_bus_sel [2] connect \Y $and$ls180.v:1717$76_Y end attribute \src "ls180.v:1718.18-1718.59" cell $and $and$ls180.v:1718$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb connect \Y $and$ls180.v:1718$77_Y end attribute \src "ls180.v:1718.17-1718.81" cell $and $and$ls180.v:1718$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1718$77_Y connect \B \ram_bus_ram_bus_we connect \Y $and$ls180.v:1718$78_Y end attribute \src "ls180.v:1718.16-1718.107" cell $and $and$ls180.v:1718$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1718$78_Y connect \B \ram_bus_ram_bus_sel [3] connect \Y $and$ls180.v:1718$79_Y end attribute \src "ls180.v:1835.35-1835.84" cell $and $and$ls180.v:1835$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_issue_re connect \B \sdram_command_storage [4] connect \Y $and$ls180.v:1835$86_Y end attribute \src "ls180.v:1836.35-1836.84" cell $and $and$ls180.v:1836$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_issue_re connect \B \sdram_command_storage [5] connect \Y $and$ls180.v:1836$87_Y end attribute \src "ls180.v:1874.33-1874.88" cell $and $and$ls180.v:1874$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_done1 connect \B $eq$ls180.v:1874$92_Y connect \Y $and$ls180.v:1874$93_Y end attribute \src "ls180.v:1928.45-1928.104" cell $and $and$ls180.v:1928$101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_ready connect \Y $and$ls180.v:1928$101_Y end attribute \src "ls180.v:1928.44-1928.147" cell $and $and$ls180.v:1928$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1928$101_Y connect \B \sdram_bankmachine0_cmd_payload_is_write connect \Y $and$ls180.v:1928$102_Y end attribute \src "ls180.v:1929.44-1929.103" cell $and $and$ls180.v:1929$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_ready connect \Y $and$ls180.v:1929$103_Y end attribute \src "ls180.v:1929.43-1929.134" cell $and $and$ls180.v:1929$104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1929$103_Y connect \B \sdram_bankmachine0_row_open connect \Y $and$ls180.v:1929$104_Y end attribute \src "ls180.v:1930.45-1930.104" cell $and $and$ls180.v:1930$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_ready connect \Y $and$ls180.v:1930$105_Y end attribute \src "ls180.v:1930.44-1930.135" cell $and $and$ls180.v:1930$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:1930$105_Y connect \B \sdram_bankmachine0_row_open connect \Y $and$ls180.v:1930$106_Y end attribute \src "ls180.v:1933.7-1933.104" cell $and $and$ls180.v:1933$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine0_cmd_buffer_source_valid connect \Y $and$ls180.v:1933$108_Y end attribute \src "ls180.v:1962.61-1962.226" cell $and $and$ls180.v:1962$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B $or$ls180.v:1962$113_Y connect \Y $and$ls180.v:1962$114_Y end attribute \src "ls180.v:1963.59-1963.172" cell $and $and$ls180.v:1963$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re connect \Y $and$ls180.v:1963$115_Y end attribute \src "ls180.v:1987.9-1987.76" cell $and $and$ls180.v:1987$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_ready connect \B \sdram_bankmachine0_trascon_ready connect \Y $and$ls180.v:1987$121_Y end attribute \src "ls180.v:1999.9-1999.76" cell $and $and$ls180.v:1999$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_ready connect \B \sdram_bankmachine0_trascon_ready connect \Y $and$ls180.v:1999$122_Y end attribute \src "ls180.v:2049.13-2049.77" cell $and $and$ls180.v:2049$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_ready connect \B \sdram_bankmachine0_auto_precharge connect \Y $and$ls180.v:2049$124_Y end attribute \src "ls180.v:2085.45-2085.104" cell $and $and$ls180.v:2085$131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_ready connect \Y $and$ls180.v:2085$131_Y end attribute \src "ls180.v:2085.44-2085.147" cell $and $and$ls180.v:2085$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2085$131_Y connect \B \sdram_bankmachine1_cmd_payload_is_write connect \Y $and$ls180.v:2085$132_Y end attribute \src "ls180.v:2086.44-2086.103" cell $and $and$ls180.v:2086$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_ready connect \Y $and$ls180.v:2086$133_Y end attribute \src "ls180.v:2086.43-2086.134" cell $and $and$ls180.v:2086$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2086$133_Y connect \B \sdram_bankmachine1_row_open connect \Y $and$ls180.v:2086$134_Y end attribute \src "ls180.v:2087.45-2087.104" cell $and $and$ls180.v:2087$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_ready connect \Y $and$ls180.v:2087$135_Y end attribute \src "ls180.v:2087.44-2087.135" cell $and $and$ls180.v:2087$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2087$135_Y connect \B \sdram_bankmachine1_row_open connect \Y $and$ls180.v:2087$136_Y end attribute \src "ls180.v:2090.7-2090.104" cell $and $and$ls180.v:2090$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine1_cmd_buffer_source_valid connect \Y $and$ls180.v:2090$138_Y end attribute \src "ls180.v:2119.61-2119.226" cell $and $and$ls180.v:2119$144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B $or$ls180.v:2119$143_Y connect \Y $and$ls180.v:2119$144_Y end attribute \src "ls180.v:2120.59-2120.172" cell $and $and$ls180.v:2120$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re connect \Y $and$ls180.v:2120$145_Y end attribute \src "ls180.v:2144.9-2144.76" cell $and $and$ls180.v:2144$151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_ready connect \B \sdram_bankmachine1_trascon_ready connect \Y $and$ls180.v:2144$151_Y end attribute \src "ls180.v:2156.9-2156.76" cell $and $and$ls180.v:2156$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_ready connect \B \sdram_bankmachine1_trascon_ready connect \Y $and$ls180.v:2156$152_Y end attribute \src "ls180.v:2206.13-2206.77" cell $and $and$ls180.v:2206$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_ready connect \B \sdram_bankmachine1_auto_precharge connect \Y $and$ls180.v:2206$154_Y end attribute \src "ls180.v:2242.45-2242.104" cell $and $and$ls180.v:2242$161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_ready connect \Y $and$ls180.v:2242$161_Y end attribute \src "ls180.v:2242.44-2242.147" cell $and $and$ls180.v:2242$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2242$161_Y connect \B \sdram_bankmachine2_cmd_payload_is_write connect \Y $and$ls180.v:2242$162_Y end attribute \src "ls180.v:2243.44-2243.103" cell $and $and$ls180.v:2243$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_ready connect \Y $and$ls180.v:2243$163_Y end attribute \src "ls180.v:2243.43-2243.134" cell $and $and$ls180.v:2243$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2243$163_Y connect \B \sdram_bankmachine2_row_open connect \Y $and$ls180.v:2243$164_Y end attribute \src "ls180.v:2244.45-2244.104" cell $and $and$ls180.v:2244$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_ready connect \Y $and$ls180.v:2244$165_Y end attribute \src "ls180.v:2244.44-2244.135" cell $and $and$ls180.v:2244$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2244$165_Y connect \B \sdram_bankmachine2_row_open connect \Y $and$ls180.v:2244$166_Y end attribute \src "ls180.v:2247.7-2247.104" cell $and $and$ls180.v:2247$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine2_cmd_buffer_source_valid connect \Y $and$ls180.v:2247$168_Y end attribute \src "ls180.v:2276.61-2276.226" cell $and $and$ls180.v:2276$174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B $or$ls180.v:2276$173_Y connect \Y $and$ls180.v:2276$174_Y end attribute \src "ls180.v:2277.59-2277.172" cell $and $and$ls180.v:2277$175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re connect \Y $and$ls180.v:2277$175_Y end attribute \src "ls180.v:2301.9-2301.76" cell $and $and$ls180.v:2301$181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_ready connect \B \sdram_bankmachine2_trascon_ready connect \Y $and$ls180.v:2301$181_Y end attribute \src "ls180.v:2313.9-2313.76" cell $and $and$ls180.v:2313$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_ready connect \B \sdram_bankmachine2_trascon_ready connect \Y $and$ls180.v:2313$182_Y end attribute \src "ls180.v:2363.13-2363.77" cell $and $and$ls180.v:2363$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_ready connect \B \sdram_bankmachine2_auto_precharge connect \Y $and$ls180.v:2363$184_Y end attribute \src "ls180.v:2399.45-2399.104" cell $and $and$ls180.v:2399$191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_ready connect \Y $and$ls180.v:2399$191_Y end attribute \src "ls180.v:2399.44-2399.147" cell $and $and$ls180.v:2399$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2399$191_Y connect \B \sdram_bankmachine3_cmd_payload_is_write connect \Y $and$ls180.v:2399$192_Y end attribute \src "ls180.v:2400.44-2400.103" cell $and $and$ls180.v:2400$193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_ready connect \Y $and$ls180.v:2400$193_Y end attribute \src "ls180.v:2400.43-2400.134" cell $and $and$ls180.v:2400$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2400$193_Y connect \B \sdram_bankmachine3_row_open connect \Y $and$ls180.v:2400$194_Y end attribute \src "ls180.v:2401.45-2401.104" cell $and $and$ls180.v:2401$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_ready connect \Y $and$ls180.v:2401$195_Y end attribute \src "ls180.v:2401.44-2401.135" cell $and $and$ls180.v:2401$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2401$195_Y connect \B \sdram_bankmachine3_row_open connect \Y $and$ls180.v:2401$196_Y end attribute \src "ls180.v:2404.7-2404.104" cell $and $and$ls180.v:2404$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine3_cmd_buffer_source_valid connect \Y $and$ls180.v:2404$198_Y end attribute \src "ls180.v:2433.61-2433.226" cell $and $and$ls180.v:2433$204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B $or$ls180.v:2433$203_Y connect \Y $and$ls180.v:2433$204_Y end attribute \src "ls180.v:2434.59-2434.172" cell $and $and$ls180.v:2434$205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re connect \Y $and$ls180.v:2434$205_Y end attribute \src "ls180.v:2458.9-2458.76" cell $and $and$ls180.v:2458$211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_ready connect \B \sdram_bankmachine3_trascon_ready connect \Y $and$ls180.v:2458$211_Y end attribute \src "ls180.v:2470.9-2470.76" cell $and $and$ls180.v:2470$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_ready connect \B \sdram_bankmachine3_trascon_ready connect \Y $and$ls180.v:2470$212_Y end attribute \src "ls180.v:2520.13-2520.77" cell $and $and$ls180.v:2520$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_ready connect \B \sdram_bankmachine3_auto_precharge connect \Y $and$ls180.v:2520$214_Y end attribute \src "ls180.v:2535.32-2535.87" cell $and $and$ls180.v:2535$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2535$215_Y end attribute \src "ls180.v:2535.93-2535.163" cell $and $and$ls180.v:2535$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras connect \B $not$ls180.v:2535$216_Y connect \Y $and$ls180.v:2535$217_Y end attribute \src "ls180.v:2535.92-2535.201" cell $and $and$ls180.v:2535$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2535$217_Y connect \B $not$ls180.v:2535$218_Y connect \Y $and$ls180.v:2535$219_Y end attribute \src "ls180.v:2535.31-2535.202" cell $and $and$ls180.v:2535$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2535$215_Y connect \B $and$ls180.v:2535$219_Y connect \Y $and$ls180.v:2535$220_Y end attribute \src "ls180.v:2536.32-2536.87" cell $and $and$ls180.v:2536$221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2536$221_Y end attribute \src "ls180.v:2536.93-2536.163" cell $and $and$ls180.v:2536$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras connect \B $not$ls180.v:2536$222_Y connect \Y $and$ls180.v:2536$223_Y end attribute \src "ls180.v:2536.92-2536.201" cell $and $and$ls180.v:2536$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2536$223_Y connect \B $not$ls180.v:2536$224_Y connect \Y $and$ls180.v:2536$225_Y end attribute \src "ls180.v:2536.31-2536.202" cell $and $and$ls180.v:2536$226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2536$221_Y connect \B $and$ls180.v:2536$225_Y connect \Y $and$ls180.v:2536$226_Y end attribute \src "ls180.v:2537.29-2537.70" cell $and $and$ls180.v:2537$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_trrdcon_ready connect \B \sdram_tfawcon_ready connect \Y $and$ls180.v:2537$227_Y end attribute \src "ls180.v:2538.32-2538.87" cell $and $and$ls180.v:2538$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2538$228_Y end attribute \src "ls180.v:2538.31-2538.169" cell $and $and$ls180.v:2538$230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2538$228_Y connect \B $or$ls180.v:2538$229_Y connect \Y $and$ls180.v:2538$230_Y end attribute \src "ls180.v:2540.32-2540.87" cell $and $and$ls180.v:2540$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2540$231_Y end attribute \src "ls180.v:2540.31-2540.128" cell $and $and$ls180.v:2540$232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2540$231_Y connect \B \sdram_choose_req_cmd_payload_is_write connect \Y $and$ls180.v:2540$232_Y end attribute \src "ls180.v:2541.35-2541.104" cell $and $and$ls180.v:2541$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_payload_is_read connect \Y $and$ls180.v:2541$233_Y end attribute \src "ls180.v:2541.109-2541.178" cell $and $and$ls180.v:2541$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_payload_is_read connect \Y $and$ls180.v:2541$234_Y end attribute \src "ls180.v:2541.184-2541.253" cell $and $and$ls180.v:2541$236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_payload_is_read connect \Y $and$ls180.v:2541$236_Y end attribute \src "ls180.v:2541.259-2541.328" cell $and $and$ls180.v:2541$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_payload_is_read connect \Y $and$ls180.v:2541$238_Y end attribute \src "ls180.v:2542.36-2542.106" cell $and $and$ls180.v:2542$240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B \sdram_bankmachine0_cmd_payload_is_write connect \Y $and$ls180.v:2542$240_Y end attribute \src "ls180.v:2542.111-2542.181" cell $and $and$ls180.v:2542$241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B \sdram_bankmachine1_cmd_payload_is_write connect \Y $and$ls180.v:2542$241_Y end attribute \src "ls180.v:2542.187-2542.257" cell $and $and$ls180.v:2542$243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B \sdram_bankmachine2_cmd_payload_is_write connect \Y $and$ls180.v:2542$243_Y end attribute \src "ls180.v:2542.263-2542.333" cell $and $and$ls180.v:2542$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B \sdram_bankmachine3_cmd_payload_is_write connect \Y $and$ls180.v:2542$245_Y end attribute \src "ls180.v:2549.33-2549.96" cell $and $and$ls180.v:2549$249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_refresh_gnt connect \B \sdram_bankmachine1_refresh_gnt connect \Y $and$ls180.v:2549$249_Y end attribute \src "ls180.v:2549.32-2549.130" cell $and $and$ls180.v:2549$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2549$249_Y connect \B \sdram_bankmachine2_refresh_gnt connect \Y $and$ls180.v:2549$250_Y end attribute \src "ls180.v:2549.31-2549.164" cell $and $and$ls180.v:2549$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2549$250_Y connect \B \sdram_bankmachine3_refresh_gnt connect \Y $and$ls180.v:2549$251_Y end attribute \src "ls180.v:2555.67-2555.133" cell $and $and$ls180.v:2555$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds connect \Y $and$ls180.v:2555$254_Y end attribute \src "ls180.v:2555.142-2555.216" cell $and $and$ls180.v:2555$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_ras connect \B $not$ls180.v:2555$255_Y connect \Y $and$ls180.v:2555$256_Y end attribute \src "ls180.v:2555.141-2555.256" cell $and $and$ls180.v:2555$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2555$256_Y connect \B $not$ls180.v:2555$257_Y connect \Y $and$ls180.v:2555$258_Y end attribute \src "ls180.v:2555.66-2555.293" cell $and $and$ls180.v:2555$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2555$254_Y connect \B $or$ls180.v:2555$260_Y connect \Y $and$ls180.v:2555$261_Y end attribute \src "ls180.v:2555.298-2555.445" cell $and $and$ls180.v:2555$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2555$262_Y connect \B $eq$ls180.v:2555$263_Y connect \Y $and$ls180.v:2555$264_Y end attribute \src "ls180.v:2555.33-2555.447" cell $and $and$ls180.v:2555$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B $or$ls180.v:2555$265_Y connect \Y $and$ls180.v:2555$266_Y end attribute \src "ls180.v:2556.67-2556.133" cell $and $and$ls180.v:2556$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds connect \Y $and$ls180.v:2556$267_Y end attribute \src "ls180.v:2556.142-2556.216" cell $and $and$ls180.v:2556$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_ras connect \B $not$ls180.v:2556$268_Y connect \Y $and$ls180.v:2556$269_Y end attribute \src "ls180.v:2556.141-2556.256" cell $and $and$ls180.v:2556$271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2556$269_Y connect \B $not$ls180.v:2556$270_Y connect \Y $and$ls180.v:2556$271_Y end attribute \src "ls180.v:2556.66-2556.293" cell $and $and$ls180.v:2556$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2556$267_Y connect \B $or$ls180.v:2556$273_Y connect \Y $and$ls180.v:2556$274_Y end attribute \src "ls180.v:2556.298-2556.445" cell $and $and$ls180.v:2556$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2556$275_Y connect \B $eq$ls180.v:2556$276_Y connect \Y $and$ls180.v:2556$277_Y end attribute \src "ls180.v:2556.33-2556.447" cell $and $and$ls180.v:2556$279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B $or$ls180.v:2556$278_Y connect \Y $and$ls180.v:2556$279_Y end attribute \src "ls180.v:2557.67-2557.133" cell $and $and$ls180.v:2557$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds connect \Y $and$ls180.v:2557$280_Y end attribute \src "ls180.v:2557.142-2557.216" cell $and $and$ls180.v:2557$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_ras connect \B $not$ls180.v:2557$281_Y connect \Y $and$ls180.v:2557$282_Y end attribute \src "ls180.v:2557.141-2557.256" cell $and $and$ls180.v:2557$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2557$282_Y connect \B $not$ls180.v:2557$283_Y connect \Y $and$ls180.v:2557$284_Y end attribute \src "ls180.v:2557.66-2557.293" cell $and $and$ls180.v:2557$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2557$280_Y connect \B $or$ls180.v:2557$286_Y connect \Y $and$ls180.v:2557$287_Y end attribute \src "ls180.v:2557.298-2557.445" cell $and $and$ls180.v:2557$290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2557$288_Y connect \B $eq$ls180.v:2557$289_Y connect \Y $and$ls180.v:2557$290_Y end attribute \src "ls180.v:2557.33-2557.447" cell $and $and$ls180.v:2557$292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B $or$ls180.v:2557$291_Y connect \Y $and$ls180.v:2557$292_Y end attribute \src "ls180.v:2558.67-2558.133" cell $and $and$ls180.v:2558$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_cmd connect \B \sdram_choose_cmd_want_cmds connect \Y $and$ls180.v:2558$293_Y end attribute \src "ls180.v:2558.142-2558.216" cell $and $and$ls180.v:2558$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_ras connect \B $not$ls180.v:2558$294_Y connect \Y $and$ls180.v:2558$295_Y end attribute \src "ls180.v:2558.141-2558.256" cell $and $and$ls180.v:2558$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2558$295_Y connect \B $not$ls180.v:2558$296_Y connect \Y $and$ls180.v:2558$297_Y end attribute \src "ls180.v:2558.66-2558.293" cell $and $and$ls180.v:2558$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2558$293_Y connect \B $or$ls180.v:2558$299_Y connect \Y $and$ls180.v:2558$300_Y end attribute \src "ls180.v:2558.298-2558.445" cell $and $and$ls180.v:2558$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2558$301_Y connect \B $eq$ls180.v:2558$302_Y connect \Y $and$ls180.v:2558$303_Y end attribute \src "ls180.v:2558.33-2558.447" cell $and $and$ls180.v:2558$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B $or$ls180.v:2558$304_Y connect \Y $and$ls180.v:2558$305_Y end attribute \src "ls180.v:2588.67-2588.133" cell $and $and$ls180.v:2588$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds connect \Y $and$ls180.v:2588$312_Y end attribute \src "ls180.v:2588.142-2588.216" cell $and $and$ls180.v:2588$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_ras connect \B $not$ls180.v:2588$313_Y connect \Y $and$ls180.v:2588$314_Y end attribute \src "ls180.v:2588.141-2588.256" cell $and $and$ls180.v:2588$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2588$314_Y connect \B $not$ls180.v:2588$315_Y connect \Y $and$ls180.v:2588$316_Y end attribute \src "ls180.v:2588.66-2588.293" cell $and $and$ls180.v:2588$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2588$312_Y connect \B $or$ls180.v:2588$318_Y connect \Y $and$ls180.v:2588$319_Y end attribute \src "ls180.v:2588.298-2588.445" cell $and $and$ls180.v:2588$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2588$320_Y connect \B $eq$ls180.v:2588$321_Y connect \Y $and$ls180.v:2588$322_Y end attribute \src "ls180.v:2588.33-2588.447" cell $and $and$ls180.v:2588$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_valid connect \B $or$ls180.v:2588$323_Y connect \Y $and$ls180.v:2588$324_Y end attribute \src "ls180.v:2589.67-2589.133" cell $and $and$ls180.v:2589$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds connect \Y $and$ls180.v:2589$325_Y end attribute \src "ls180.v:2589.142-2589.216" cell $and $and$ls180.v:2589$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_ras connect \B $not$ls180.v:2589$326_Y connect \Y $and$ls180.v:2589$327_Y end attribute \src "ls180.v:2589.141-2589.256" cell $and $and$ls180.v:2589$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2589$327_Y connect \B $not$ls180.v:2589$328_Y connect \Y $and$ls180.v:2589$329_Y end attribute \src "ls180.v:2589.66-2589.293" cell $and $and$ls180.v:2589$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2589$325_Y connect \B $or$ls180.v:2589$331_Y connect \Y $and$ls180.v:2589$332_Y end attribute \src "ls180.v:2589.298-2589.445" cell $and $and$ls180.v:2589$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2589$333_Y connect \B $eq$ls180.v:2589$334_Y connect \Y $and$ls180.v:2589$335_Y end attribute \src "ls180.v:2589.33-2589.447" cell $and $and$ls180.v:2589$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_valid connect \B $or$ls180.v:2589$336_Y connect \Y $and$ls180.v:2589$337_Y end attribute \src "ls180.v:2590.67-2590.133" cell $and $and$ls180.v:2590$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds connect \Y $and$ls180.v:2590$338_Y end attribute \src "ls180.v:2590.142-2590.216" cell $and $and$ls180.v:2590$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_ras connect \B $not$ls180.v:2590$339_Y connect \Y $and$ls180.v:2590$340_Y end attribute \src "ls180.v:2590.141-2590.256" cell $and $and$ls180.v:2590$342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2590$340_Y connect \B $not$ls180.v:2590$341_Y connect \Y $and$ls180.v:2590$342_Y end attribute \src "ls180.v:2590.66-2590.293" cell $and $and$ls180.v:2590$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2590$338_Y connect \B $or$ls180.v:2590$344_Y connect \Y $and$ls180.v:2590$345_Y end attribute \src "ls180.v:2590.298-2590.445" cell $and $and$ls180.v:2590$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2590$346_Y connect \B $eq$ls180.v:2590$347_Y connect \Y $and$ls180.v:2590$348_Y end attribute \src "ls180.v:2590.33-2590.447" cell $and $and$ls180.v:2590$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_valid connect \B $or$ls180.v:2590$349_Y connect \Y $and$ls180.v:2590$350_Y end attribute \src "ls180.v:2591.67-2591.133" cell $and $and$ls180.v:2591$351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_cmd connect \B \sdram_choose_req_want_cmds connect \Y $and$ls180.v:2591$351_Y end attribute \src "ls180.v:2591.142-2591.216" cell $and $and$ls180.v:2591$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_ras connect \B $not$ls180.v:2591$352_Y connect \Y $and$ls180.v:2591$353_Y end attribute \src "ls180.v:2591.141-2591.256" cell $and $and$ls180.v:2591$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2591$353_Y connect \B $not$ls180.v:2591$354_Y connect \Y $and$ls180.v:2591$355_Y end attribute \src "ls180.v:2591.66-2591.293" cell $and $and$ls180.v:2591$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2591$351_Y connect \B $or$ls180.v:2591$357_Y connect \Y $and$ls180.v:2591$358_Y end attribute \src "ls180.v:2591.298-2591.445" cell $and $and$ls180.v:2591$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2591$359_Y connect \B $eq$ls180.v:2591$360_Y connect \Y $and$ls180.v:2591$361_Y end attribute \src "ls180.v:2591.33-2591.447" cell $and $and$ls180.v:2591$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_valid connect \B $or$ls180.v:2591$362_Y connect \Y $and$ls180.v:2591$363_Y end attribute \src "ls180.v:2620.8-2620.63" cell $and $and$ls180.v:2620$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready connect \Y $and$ls180.v:2620$368_Y end attribute \src "ls180.v:2620.7-2620.99" cell $and $and$ls180.v:2620$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2620$368_Y connect \B $eq$ls180.v:2620$369_Y connect \Y $and$ls180.v:2620$370_Y end attribute \src "ls180.v:2623.8-2623.63" cell $and $and$ls180.v:2623$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2623$371_Y end attribute \src "ls180.v:2623.7-2623.99" cell $and $and$ls180.v:2623$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2623$371_Y connect \B $eq$ls180.v:2623$372_Y connect \Y $and$ls180.v:2623$373_Y end attribute \src "ls180.v:2629.8-2629.63" cell $and $and$ls180.v:2629$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready connect \Y $and$ls180.v:2629$375_Y end attribute \src "ls180.v:2629.7-2629.99" cell $and $and$ls180.v:2629$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2629$375_Y connect \B $eq$ls180.v:2629$376_Y connect \Y $and$ls180.v:2629$377_Y end attribute \src "ls180.v:2632.8-2632.63" cell $and $and$ls180.v:2632$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2632$378_Y end attribute \src "ls180.v:2632.7-2632.99" cell $and $and$ls180.v:2632$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2632$378_Y connect \B $eq$ls180.v:2632$379_Y connect \Y $and$ls180.v:2632$380_Y end attribute \src "ls180.v:2638.8-2638.63" cell $and $and$ls180.v:2638$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready connect \Y $and$ls180.v:2638$382_Y end attribute \src "ls180.v:2638.7-2638.99" cell $and $and$ls180.v:2638$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2638$382_Y connect \B $eq$ls180.v:2638$383_Y connect \Y $and$ls180.v:2638$384_Y end attribute \src "ls180.v:2641.8-2641.63" cell $and $and$ls180.v:2641$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2641$385_Y end attribute \src "ls180.v:2641.7-2641.99" cell $and $and$ls180.v:2641$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2641$385_Y connect \B $eq$ls180.v:2641$386_Y connect \Y $and$ls180.v:2641$387_Y end attribute \src "ls180.v:2647.8-2647.63" cell $and $and$ls180.v:2647$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \B \sdram_choose_cmd_cmd_ready connect \Y $and$ls180.v:2647$389_Y end attribute \src "ls180.v:2647.7-2647.99" cell $and $and$ls180.v:2647$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2647$389_Y connect \B $eq$ls180.v:2647$390_Y connect \Y $and$ls180.v:2647$391_Y end attribute \src "ls180.v:2650.8-2650.63" cell $and $and$ls180.v:2650$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:2650$392_Y end attribute \src "ls180.v:2650.7-2650.99" cell $and $and$ls180.v:2650$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2650$392_Y connect \B $eq$ls180.v:2650$393_Y connect \Y $and$ls180.v:2650$394_Y end attribute \src "ls180.v:2675.61-2675.131" cell $and $and$ls180.v:2675$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras connect \B $not$ls180.v:2675$398_Y connect \Y $and$ls180.v:2675$399_Y end attribute \src "ls180.v:2675.60-2675.169" cell $and $and$ls180.v:2675$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2675$399_Y connect \B $not$ls180.v:2675$400_Y connect \Y $and$ls180.v:2675$401_Y end attribute \src "ls180.v:2675.36-2675.192" cell $and $and$ls180.v:2675$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cas_allowed connect \B $or$ls180.v:2675$403_Y connect \Y $and$ls180.v:2675$404_Y end attribute \src "ls180.v:2713.61-2713.131" cell $and $and$ls180.v:2713$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_ras connect \B $not$ls180.v:2713$407_Y connect \Y $and$ls180.v:2713$408_Y end attribute \src "ls180.v:2713.60-2713.169" cell $and $and$ls180.v:2713$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2713$408_Y connect \B $not$ls180.v:2713$409_Y connect \Y $and$ls180.v:2713$410_Y end attribute \src "ls180.v:2713.36-2713.192" cell $and $and$ls180.v:2713$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cas_allowed connect \B $or$ls180.v:2713$412_Y connect \Y $and$ls180.v:2713$413_Y end attribute \src "ls180.v:2731.115-2731.184" cell $and $and$ls180.v:2731$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:2731$417_Y connect \Y $and$ls180.v:2731$418_Y end attribute \src "ls180.v:2731.190-2731.259" cell $and $and$ls180.v:2731$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:2731$420_Y connect \Y $and$ls180.v:2731$421_Y end attribute \src "ls180.v:2731.265-2731.334" cell $and $and$ls180.v:2731$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:2731$423_Y connect \Y $and$ls180.v:2731$424_Y end attribute \src "ls180.v:2731.46-2731.337" cell $and $and$ls180.v:2731$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2731$416_Y connect \B $not$ls180.v:2731$426_Y connect \Y $and$ls180.v:2731$427_Y end attribute \src "ls180.v:2731.45-2731.355" cell $and $and$ls180.v:2731$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2731$427_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:2731$428_Y end attribute \src "ls180.v:2732.39-2732.101" cell $and $and$ls180.v:2732$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2732$429_Y connect \B $not$ls180.v:2732$430_Y connect \Y $and$ls180.v:2732$431_Y end attribute \src "ls180.v:2736.115-2736.184" cell $and $and$ls180.v:2736$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:2736$433_Y connect \Y $and$ls180.v:2736$434_Y end attribute \src "ls180.v:2736.190-2736.259" cell $and $and$ls180.v:2736$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:2736$436_Y connect \Y $and$ls180.v:2736$437_Y end attribute \src "ls180.v:2736.265-2736.334" cell $and $and$ls180.v:2736$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:2736$439_Y connect \Y $and$ls180.v:2736$440_Y end attribute \src "ls180.v:2736.46-2736.337" cell $and $and$ls180.v:2736$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2736$432_Y connect \B $not$ls180.v:2736$442_Y connect \Y $and$ls180.v:2736$443_Y end attribute \src "ls180.v:2736.45-2736.355" cell $and $and$ls180.v:2736$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2736$443_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:2736$444_Y end attribute \src "ls180.v:2737.39-2737.101" cell $and $and$ls180.v:2737$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2737$445_Y connect \B $not$ls180.v:2737$446_Y connect \Y $and$ls180.v:2737$447_Y end attribute \src "ls180.v:2741.115-2741.184" cell $and $and$ls180.v:2741$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:2741$449_Y connect \Y $and$ls180.v:2741$450_Y end attribute \src "ls180.v:2741.190-2741.259" cell $and $and$ls180.v:2741$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:2741$452_Y connect \Y $and$ls180.v:2741$453_Y end attribute \src "ls180.v:2741.265-2741.334" cell $and $and$ls180.v:2741$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:2741$455_Y connect \Y $and$ls180.v:2741$456_Y end attribute \src "ls180.v:2741.46-2741.337" cell $and $and$ls180.v:2741$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2741$448_Y connect \B $not$ls180.v:2741$458_Y connect \Y $and$ls180.v:2741$459_Y end attribute \src "ls180.v:2741.45-2741.355" cell $and $and$ls180.v:2741$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2741$459_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:2741$460_Y end attribute \src "ls180.v:2742.39-2742.101" cell $and $and$ls180.v:2742$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2742$461_Y connect \B $not$ls180.v:2742$462_Y connect \Y $and$ls180.v:2742$463_Y end attribute \src "ls180.v:2746.115-2746.184" cell $and $and$ls180.v:2746$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:2746$465_Y connect \Y $and$ls180.v:2746$466_Y end attribute \src "ls180.v:2746.190-2746.259" cell $and $and$ls180.v:2746$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:2746$468_Y connect \Y $and$ls180.v:2746$469_Y end attribute \src "ls180.v:2746.265-2746.334" cell $and $and$ls180.v:2746$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:2746$471_Y connect \Y $and$ls180.v:2746$472_Y end attribute \src "ls180.v:2746.46-2746.337" cell $and $and$ls180.v:2746$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2746$464_Y connect \B $not$ls180.v:2746$474_Y connect \Y $and$ls180.v:2746$475_Y end attribute \src "ls180.v:2746.45-2746.355" cell $and $and$ls180.v:2746$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2746$475_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:2746$476_Y end attribute \src "ls180.v:2747.39-2747.101" cell $and $and$ls180.v:2747$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2747$477_Y connect \B $not$ls180.v:2747$478_Y connect \Y $and$ls180.v:2747$479_Y end attribute \src "ls180.v:2751.151-2751.220" cell $and $and$ls180.v:2751$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:2751$482_Y connect \Y $and$ls180.v:2751$483_Y end attribute \src "ls180.v:2751.226-2751.295" cell $and $and$ls180.v:2751$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:2751$485_Y connect \Y $and$ls180.v:2751$486_Y end attribute \src "ls180.v:2751.301-2751.370" cell $and $and$ls180.v:2751$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:2751$488_Y connect \Y $and$ls180.v:2751$489_Y end attribute \src "ls180.v:2751.82-2751.373" cell $and $and$ls180.v:2751$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$481_Y connect \B $not$ls180.v:2751$491_Y connect \Y $and$ls180.v:2751$492_Y end attribute \src "ls180.v:2751.38-2751.374" cell $and $and$ls180.v:2751$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$480_Y connect \B $and$ls180.v:2751$492_Y connect \Y $and$ls180.v:2751$493_Y end attribute \src "ls180.v:2751.37-2751.405" cell $and $and$ls180.v:2751$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2751$493_Y connect \B \sdram_interface_bank0_ready connect \Y $and$ls180.v:2751$494_Y end attribute \src "ls180.v:2751.525-2751.594" cell $and $and$ls180.v:2751$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:2751$498_Y connect \Y $and$ls180.v:2751$499_Y end attribute \src "ls180.v:2751.600-2751.669" cell $and $and$ls180.v:2751$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:2751$501_Y connect \Y $and$ls180.v:2751$502_Y end attribute \src "ls180.v:2751.675-2751.744" cell $and $and$ls180.v:2751$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:2751$504_Y connect \Y $and$ls180.v:2751$505_Y end attribute \src "ls180.v:2751.456-2751.747" cell $and $and$ls180.v:2751$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$497_Y connect \B $not$ls180.v:2751$507_Y connect \Y $and$ls180.v:2751$508_Y end attribute \src "ls180.v:2751.412-2751.748" cell $and $and$ls180.v:2751$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$496_Y connect \B $and$ls180.v:2751$508_Y connect \Y $and$ls180.v:2751$509_Y end attribute \src "ls180.v:2751.411-2751.779" cell $and $and$ls180.v:2751$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2751$509_Y connect \B \sdram_interface_bank1_ready connect \Y $and$ls180.v:2751$510_Y end attribute \src "ls180.v:2751.899-2751.968" cell $and $and$ls180.v:2751$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:2751$514_Y connect \Y $and$ls180.v:2751$515_Y end attribute \src "ls180.v:2751.974-2751.1043" cell $and $and$ls180.v:2751$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:2751$517_Y connect \Y $and$ls180.v:2751$518_Y end attribute \src "ls180.v:2751.1049-2751.1118" cell $and $and$ls180.v:2751$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:2751$520_Y connect \Y $and$ls180.v:2751$521_Y end attribute \src "ls180.v:2751.830-2751.1121" cell $and $and$ls180.v:2751$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$513_Y connect \B $not$ls180.v:2751$523_Y connect \Y $and$ls180.v:2751$524_Y end attribute \src "ls180.v:2751.786-2751.1122" cell $and $and$ls180.v:2751$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$512_Y connect \B $and$ls180.v:2751$524_Y connect \Y $and$ls180.v:2751$525_Y end attribute \src "ls180.v:2751.785-2751.1153" cell $and $and$ls180.v:2751$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2751$525_Y connect \B \sdram_interface_bank2_ready connect \Y $and$ls180.v:2751$526_Y end attribute \src "ls180.v:2751.1273-2751.1342" cell $and $and$ls180.v:2751$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:2751$530_Y connect \Y $and$ls180.v:2751$531_Y end attribute \src "ls180.v:2751.1348-2751.1417" cell $and $and$ls180.v:2751$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:2751$533_Y connect \Y $and$ls180.v:2751$534_Y end attribute \src "ls180.v:2751.1423-2751.1492" cell $and $and$ls180.v:2751$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:2751$536_Y connect \Y $and$ls180.v:2751$537_Y end attribute \src "ls180.v:2751.1204-2751.1495" cell $and $and$ls180.v:2751$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$529_Y connect \B $not$ls180.v:2751$539_Y connect \Y $and$ls180.v:2751$540_Y end attribute \src "ls180.v:2751.1160-2751.1496" cell $and $and$ls180.v:2751$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:2751$528_Y connect \B $and$ls180.v:2751$540_Y connect \Y $and$ls180.v:2751$541_Y end attribute \src "ls180.v:2751.1159-2751.1527" cell $and $and$ls180.v:2751$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2751$541_Y connect \B \sdram_interface_bank3_ready connect \Y $and$ls180.v:2751$542_Y end attribute \src "ls180.v:2809.9-2809.36" cell $and $and$ls180.v:2809$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wb_sdram_stb connect \B \wb_sdram_cyc connect \Y $and$ls180.v:2809$548_Y end attribute \src "ls180.v:2827.9-2827.36" cell $and $and$ls180.v:2827$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wb_sdram_stb connect \B \wb_sdram_cyc connect \Y $and$ls180.v:2827$555_Y end attribute \src "ls180.v:2840.27-2840.60" cell $and $and$ls180.v:2840$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_cyc connect \B \litedram_wb_stb connect \Y $and$ls180.v:2840$559_Y end attribute \src "ls180.v:2840.26-2840.79" cell $and $and$ls180.v:2840$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2840$559_Y connect \B $not$ls180.v:2840$560_Y connect \Y $and$ls180.v:2840$561_Y end attribute \src "ls180.v:2841.29-2841.82" cell $and $and$ls180.v:2841$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2841$562_Y connect \B \port_cmd_payload_we connect \Y $and$ls180.v:2841$563_Y end attribute \src "ls180.v:2841.28-2841.103" cell $and $and$ls180.v:2841$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2841$563_Y connect \B $not$ls180.v:2841$564_Y connect \Y $and$ls180.v:2841$565_Y end attribute \src "ls180.v:2842.28-2842.84" cell $and $and$ls180.v:2842$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2842$566_Y connect \B $not$ls180.v:2842$567_Y connect \Y $and$ls180.v:2842$568_Y end attribute \src "ls180.v:2843.39-2843.65" cell $and $and$ls180.v:2843$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_we connect \B \ack_wdata connect \Y $and$ls180.v:2843$569_Y end attribute \src "ls180.v:2843.70-2843.99" cell $and $and$ls180.v:2843$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2843$570_Y connect \B \ack_rdata connect \Y $and$ls180.v:2843$571_Y end attribute \src "ls180.v:2843.27-2843.101" cell $and $and$ls180.v:2843$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ack_cmd connect \B $or$ls180.v:2843$572_Y connect \Y $and$ls180.v:2843$573_Y end attribute \src "ls180.v:2844.20-2844.51" cell $and $and$ls180.v:2844$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \port_cmd_ready connect \Y $and$ls180.v:2844$574_Y end attribute \src "ls180.v:2845.22-2845.57" cell $and $and$ls180.v:2845$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_wdata_valid connect \B \port_wdata_ready connect \Y $and$ls180.v:2845$576_Y end attribute \src "ls180.v:2846.21-2846.56" cell $and $and$ls180.v:2846$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_rdata_valid connect \B \port_rdata_ready connect \Y $and$ls180.v:2846$578_Y end attribute \src "ls180.v:2875.44-2875.58" cell $and $and$ls180.v:2875$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \rxtx_we connect \Y $and$ls180.v:2875$584_Y end attribute \src "ls180.v:2879.7-2879.58" cell $and $and$ls180.v:2879$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_re connect \B \eventmanager_pending_r [0] connect \Y $and$ls180.v:2879$588_Y end attribute \src "ls180.v:2890.7-2890.58" cell $and $and$ls180.v:2890$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_re connect \B \eventmanager_pending_r [1] connect \Y $and$ls180.v:2890$591_Y end attribute \src "ls180.v:2899.16-2899.67" cell $and $and$ls180.v:2899$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_w [0] connect \B \eventmanager_storage [0] connect \Y $and$ls180.v:2899$593_Y end attribute \src "ls180.v:2899.72-2899.123" cell $and $and$ls180.v:2899$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \eventmanager_pending_w [1] connect \B \eventmanager_storage [1] connect \Y $and$ls180.v:2899$594_Y end attribute \src "ls180.v:2914.31-2914.93" cell $and $and$ls180.v:2914$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_readable connect \B $or$ls180.v:2914$597_Y connect \Y $and$ls180.v:2914$598_Y end attribute \src "ls180.v:2925.29-2925.96" cell $and $and$ls180.v:2925$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_we connect \B $or$ls180.v:2925$602_Y connect \Y $and$ls180.v:2925$603_Y end attribute \src "ls180.v:2926.27-2926.74" cell $and $and$ls180.v:2926$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_readable connect \B \tx_fifo_syncfifo_re connect \Y $and$ls180.v:2926$604_Y end attribute \src "ls180.v:2944.31-2944.93" cell $and $and$ls180.v:2944$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_readable connect \B $or$ls180.v:2944$608_Y connect \Y $and$ls180.v:2944$609_Y end attribute \src "ls180.v:2955.29-2955.96" cell $and $and$ls180.v:2955$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_we connect \B $or$ls180.v:2955$613_Y connect \Y $and$ls180.v:2955$614_Y end attribute \src "ls180.v:2956.27-2956.74" cell $and $and$ls180.v:2956$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_readable connect \B \rx_fifo_syncfifo_re connect \Y $and$ls180.v:2956$615_Y end attribute \src "ls180.v:3053.9-3053.84" cell $and $and$ls180.v:3053$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresocsim_wishbone_cyc connect \B \libresocsim_libresocsim_wishbone_stb connect \Y $and$ls180.v:3053$623_Y end attribute \src "ls180.v:3056.60-3056.144" cell $and $and$ls180.v:3056$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresocsim_wishbone_we connect \B $ne$ls180.v:3056$624_Y connect \Y $and$ls180.v:3056$625_Y end attribute \src "ls180.v:3074.58-3074.110" cell $and $and$ls180.v:3074$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack connect \B $eq$ls180.v:3074$626_Y connect \Y $and$ls180.v:3074$627_Y end attribute \src "ls180.v:3075.58-3075.110" cell $and $and$ls180.v:3075$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack connect \B $eq$ls180.v:3075$628_Y connect \Y $and$ls180.v:3075$629_Y end attribute \src "ls180.v:3076.58-3076.110" cell $and $and$ls180.v:3076$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack connect \B $eq$ls180.v:3076$630_Y connect \Y $and$ls180.v:3076$631_Y end attribute \src "ls180.v:3077.58-3077.110" cell $and $and$ls180.v:3077$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_err connect \B $eq$ls180.v:3077$632_Y connect \Y $and$ls180.v:3077$633_Y end attribute \src "ls180.v:3078.58-3078.110" cell $and $and$ls180.v:3078$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_err connect \B $eq$ls180.v:3078$634_Y connect \Y $and$ls180.v:3078$635_Y end attribute \src "ls180.v:3079.58-3079.110" cell $and $and$ls180.v:3079$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_err connect \B $eq$ls180.v:3079$636_Y connect \Y $and$ls180.v:3079$637_Y end attribute \src "ls180.v:3132.35-3132.84" cell $and $and$ls180.v:3132$645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [0] connect \Y $and$ls180.v:3132$645_Y end attribute \src "ls180.v:3133.31-3133.80" cell $and $and$ls180.v:3133$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [1] connect \Y $and$ls180.v:3133$646_Y end attribute \src "ls180.v:3134.45-3134.94" cell $and $and$ls180.v:3134$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [2] connect \Y $and$ls180.v:3134$647_Y end attribute \src "ls180.v:3135.45-3135.94" cell $and $and$ls180.v:3135$648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [3] connect \Y $and$ls180.v:3135$648_Y end attribute \src "ls180.v:3136.24-3136.73" cell $and $and$ls180.v:3136$649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [4] connect \Y $and$ls180.v:3136$649_Y end attribute \src "ls180.v:3137.48-3137.97" cell $and $and$ls180.v:3137$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_cyc connect \B \libresocsim_slave_sel [5] connect \Y $and$ls180.v:3137$650_Y end attribute \src "ls180.v:3139.29-3139.76" cell $and $and$ls180.v:3139$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_stb connect \B \libresocsim_shared_cyc connect \Y $and$ls180.v:3139$656_Y end attribute \src "ls180.v:3139.28-3139.105" cell $and $and$ls180.v:3139$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3139$656_Y connect \B $not$ls180.v:3139$657_Y connect \Y $and$ls180.v:3139$658_Y end attribute \src "ls180.v:3145.36-3145.96" cell $and $and$ls180.v:3145$665 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] } connect \B \libresocsim_ram_bus_dat_r connect \Y $and$ls180.v:3145$665_Y end attribute \src "ls180.v:3145.101-3145.157" cell $and $and$ls180.v:3145$666 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] } connect \B \ram_bus_ram_bus_dat_r connect \Y $and$ls180.v:3145$666_Y end attribute \src "ls180.v:3145.163-3145.233" cell $and $and$ls180.v:3145$668 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] } connect \B \libresocsim_libresoc_xics_icp_dat_r connect \Y $and$ls180.v:3145$668_Y end attribute \src "ls180.v:3145.239-3145.309" cell $and $and$ls180.v:3145$670 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] } connect \B \libresocsim_libresoc_xics_ics_dat_r connect \Y $and$ls180.v:3145$670_Y end attribute \src "ls180.v:3145.315-3145.364" cell $and $and$ls180.v:3145$672 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] } connect \B \wb_sdram_dat_r connect \Y $and$ls180.v:3145$672_Y end attribute \src "ls180.v:3145.370-3145.443" cell $and $and$ls180.v:3145$674 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A { \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] } connect \B \libresocsim_libresocsim_wishbone_dat_r connect \Y $and$ls180.v:3145$674_Y end attribute \src "ls180.v:3155.43-3155.104" cell $and $and$ls180.v:3155$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3155$678_Y end attribute \src "ls180.v:3155.42-3155.158" cell $and $and$ls180.v:3155$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3155$678_Y connect \B $eq$ls180.v:3155$679_Y connect \Y $and$ls180.v:3155$680_Y end attribute \src "ls180.v:3156.43-3156.107" cell $and $and$ls180.v:3156$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3156$681_Y connect \Y $and$ls180.v:3156$682_Y end attribute \src "ls180.v:3156.42-3156.161" cell $and $and$ls180.v:3156$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3156$682_Y connect \B $eq$ls180.v:3156$683_Y connect \Y $and$ls180.v:3156$684_Y end attribute \src "ls180.v:3158.45-3158.106" cell $and $and$ls180.v:3158$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3158$685_Y end attribute \src "ls180.v:3158.44-3158.160" cell $and $and$ls180.v:3158$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3158$685_Y connect \B $eq$ls180.v:3158$686_Y connect \Y $and$ls180.v:3158$687_Y end attribute \src "ls180.v:3159.45-3159.109" cell $and $and$ls180.v:3159$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3159$688_Y connect \Y $and$ls180.v:3159$689_Y end attribute \src "ls180.v:3159.44-3159.163" cell $and $and$ls180.v:3159$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3159$689_Y connect \B $eq$ls180.v:3159$690_Y connect \Y $and$ls180.v:3159$691_Y end attribute \src "ls180.v:3161.45-3161.106" cell $and $and$ls180.v:3161$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3161$692_Y end attribute \src "ls180.v:3161.44-3161.160" cell $and $and$ls180.v:3161$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3161$692_Y connect \B $eq$ls180.v:3161$693_Y connect \Y $and$ls180.v:3161$694_Y end attribute \src "ls180.v:3162.45-3162.109" cell $and $and$ls180.v:3162$696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3162$695_Y connect \Y $and$ls180.v:3162$696_Y end attribute \src "ls180.v:3162.44-3162.163" cell $and $and$ls180.v:3162$698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3162$696_Y connect \B $eq$ls180.v:3162$697_Y connect \Y $and$ls180.v:3162$698_Y end attribute \src "ls180.v:3164.45-3164.106" cell $and $and$ls180.v:3164$699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3164$699_Y end attribute \src "ls180.v:3164.44-3164.160" cell $and $and$ls180.v:3164$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3164$699_Y connect \B $eq$ls180.v:3164$700_Y connect \Y $and$ls180.v:3164$701_Y end attribute \src "ls180.v:3165.45-3165.109" cell $and $and$ls180.v:3165$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3165$702_Y connect \Y $and$ls180.v:3165$703_Y end attribute \src "ls180.v:3165.44-3165.163" cell $and $and$ls180.v:3165$705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3165$703_Y connect \B $eq$ls180.v:3165$704_Y connect \Y $and$ls180.v:3165$705_Y end attribute \src "ls180.v:3167.45-3167.106" cell $and $and$ls180.v:3167$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3167$706_Y end attribute \src "ls180.v:3167.44-3167.160" cell $and $and$ls180.v:3167$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3167$706_Y connect \B $eq$ls180.v:3167$707_Y connect \Y $and$ls180.v:3167$708_Y end attribute \src "ls180.v:3168.45-3168.109" cell $and $and$ls180.v:3168$710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3168$709_Y connect \Y $and$ls180.v:3168$710_Y end attribute \src "ls180.v:3168.44-3168.163" cell $and $and$ls180.v:3168$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3168$710_Y connect \B $eq$ls180.v:3168$711_Y connect \Y $and$ls180.v:3168$712_Y end attribute \src "ls180.v:3170.48-3170.109" cell $and $and$ls180.v:3170$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3170$713_Y end attribute \src "ls180.v:3170.47-3170.163" cell $and $and$ls180.v:3170$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3170$713_Y connect \B $eq$ls180.v:3170$714_Y connect \Y $and$ls180.v:3170$715_Y end attribute \src "ls180.v:3171.48-3171.112" cell $and $and$ls180.v:3171$717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3171$716_Y connect \Y $and$ls180.v:3171$717_Y end attribute \src "ls180.v:3171.47-3171.166" cell $and $and$ls180.v:3171$719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3171$717_Y connect \B $eq$ls180.v:3171$718_Y connect \Y $and$ls180.v:3171$719_Y end attribute \src "ls180.v:3173.48-3173.109" cell $and $and$ls180.v:3173$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3173$720_Y end attribute \src "ls180.v:3173.47-3173.163" cell $and $and$ls180.v:3173$722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3173$720_Y connect \B $eq$ls180.v:3173$721_Y connect \Y $and$ls180.v:3173$722_Y end attribute \src "ls180.v:3174.48-3174.112" cell $and $and$ls180.v:3174$724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3174$723_Y connect \Y $and$ls180.v:3174$724_Y end attribute \src "ls180.v:3174.47-3174.166" cell $and $and$ls180.v:3174$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3174$724_Y connect \B $eq$ls180.v:3174$725_Y connect \Y $and$ls180.v:3174$726_Y end attribute \src "ls180.v:3176.48-3176.109" cell $and $and$ls180.v:3176$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3176$727_Y end attribute \src "ls180.v:3176.47-3176.163" cell $and $and$ls180.v:3176$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3176$727_Y connect \B $eq$ls180.v:3176$728_Y connect \Y $and$ls180.v:3176$729_Y end attribute \src "ls180.v:3177.48-3177.112" cell $and $and$ls180.v:3177$731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3177$730_Y connect \Y $and$ls180.v:3177$731_Y end attribute \src "ls180.v:3177.47-3177.166" cell $and $and$ls180.v:3177$733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3177$731_Y connect \B $eq$ls180.v:3177$732_Y connect \Y $and$ls180.v:3177$733_Y end attribute \src "ls180.v:3179.48-3179.109" cell $and $and$ls180.v:3179$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B \libresocsim_interface0_bank_bus_we connect \Y $and$ls180.v:3179$734_Y end attribute \src "ls180.v:3179.47-3179.163" cell $and $and$ls180.v:3179$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3179$734_Y connect \B $eq$ls180.v:3179$735_Y connect \Y $and$ls180.v:3179$736_Y end attribute \src "ls180.v:3180.48-3180.112" cell $and $and$ls180.v:3180$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank0_sel connect \B $not$ls180.v:3180$737_Y connect \Y $and$ls180.v:3180$738_Y end attribute \src "ls180.v:3180.47-3180.166" cell $and $and$ls180.v:3180$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3180$738_Y connect \B $eq$ls180.v:3180$739_Y connect \Y $and$ls180.v:3180$740_Y end attribute \src "ls180.v:3193.40-3193.101" cell $and $and$ls180.v:3193$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B \libresocsim_interface1_bank_bus_we connect \Y $and$ls180.v:3193$742_Y end attribute \src "ls180.v:3193.39-3193.155" cell $and $and$ls180.v:3193$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3193$742_Y connect \B $eq$ls180.v:3193$743_Y connect \Y $and$ls180.v:3193$744_Y end attribute \src "ls180.v:3194.40-3194.104" cell $and $and$ls180.v:3194$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B $not$ls180.v:3194$745_Y connect \Y $and$ls180.v:3194$746_Y end attribute \src "ls180.v:3194.39-3194.158" cell $and $and$ls180.v:3194$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3194$746_Y connect \B $eq$ls180.v:3194$747_Y connect \Y $and$ls180.v:3194$748_Y end attribute \src "ls180.v:3196.39-3196.100" cell $and $and$ls180.v:3196$749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B \libresocsim_interface1_bank_bus_we connect \Y $and$ls180.v:3196$749_Y end attribute \src "ls180.v:3196.38-3196.154" cell $and $and$ls180.v:3196$751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3196$749_Y connect \B $eq$ls180.v:3196$750_Y connect \Y $and$ls180.v:3196$751_Y end attribute \src "ls180.v:3197.39-3197.103" cell $and $and$ls180.v:3197$753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B $not$ls180.v:3197$752_Y connect \Y $and$ls180.v:3197$753_Y end attribute \src "ls180.v:3197.38-3197.157" cell $and $and$ls180.v:3197$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3197$753_Y connect \B $eq$ls180.v:3197$754_Y connect \Y $and$ls180.v:3197$755_Y end attribute \src "ls180.v:3199.41-3199.102" cell $and $and$ls180.v:3199$756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B \libresocsim_interface1_bank_bus_we connect \Y $and$ls180.v:3199$756_Y end attribute \src "ls180.v:3199.40-3199.156" cell $and $and$ls180.v:3199$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3199$756_Y connect \B $eq$ls180.v:3199$757_Y connect \Y $and$ls180.v:3199$758_Y end attribute \src "ls180.v:3200.41-3200.105" cell $and $and$ls180.v:3200$760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank1_sel connect \B $not$ls180.v:3200$759_Y connect \Y $and$ls180.v:3200$760_Y end attribute \src "ls180.v:3200.40-3200.159" cell $and $and$ls180.v:3200$762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3200$760_Y connect \B $eq$ls180.v:3200$761_Y connect \Y $and$ls180.v:3200$762_Y end attribute \src "ls180.v:3207.40-3207.101" cell $and $and$ls180.v:3207$764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B \libresocsim_interface2_bank_bus_we connect \Y $and$ls180.v:3207$764_Y end attribute \src "ls180.v:3207.39-3207.155" cell $and $and$ls180.v:3207$766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3207$764_Y connect \B $eq$ls180.v:3207$765_Y connect \Y $and$ls180.v:3207$766_Y end attribute \src "ls180.v:3208.40-3208.104" cell $and $and$ls180.v:3208$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B $not$ls180.v:3208$767_Y connect \Y $and$ls180.v:3208$768_Y end attribute \src "ls180.v:3208.39-3208.158" cell $and $and$ls180.v:3208$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3208$768_Y connect \B $eq$ls180.v:3208$769_Y connect \Y $and$ls180.v:3208$770_Y end attribute \src "ls180.v:3210.39-3210.100" cell $and $and$ls180.v:3210$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B \libresocsim_interface2_bank_bus_we connect \Y $and$ls180.v:3210$771_Y end attribute \src "ls180.v:3210.38-3210.154" cell $and $and$ls180.v:3210$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3210$771_Y connect \B $eq$ls180.v:3210$772_Y connect \Y $and$ls180.v:3210$773_Y end attribute \src "ls180.v:3211.39-3211.103" cell $and $and$ls180.v:3211$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B $not$ls180.v:3211$774_Y connect \Y $and$ls180.v:3211$775_Y end attribute \src "ls180.v:3211.38-3211.157" cell $and $and$ls180.v:3211$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3211$775_Y connect \B $eq$ls180.v:3211$776_Y connect \Y $and$ls180.v:3211$777_Y end attribute \src "ls180.v:3213.41-3213.102" cell $and $and$ls180.v:3213$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B \libresocsim_interface2_bank_bus_we connect \Y $and$ls180.v:3213$778_Y end attribute \src "ls180.v:3213.40-3213.156" cell $and $and$ls180.v:3213$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3213$778_Y connect \B $eq$ls180.v:3213$779_Y connect \Y $and$ls180.v:3213$780_Y end attribute \src "ls180.v:3214.41-3214.105" cell $and $and$ls180.v:3214$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank2_sel connect \B $not$ls180.v:3214$781_Y connect \Y $and$ls180.v:3214$782_Y end attribute \src "ls180.v:3214.40-3214.159" cell $and $and$ls180.v:3214$784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3214$782_Y connect \B $eq$ls180.v:3214$783_Y connect \Y $and$ls180.v:3214$784_Y end attribute \src "ls180.v:3221.39-3221.100" cell $and $and$ls180.v:3221$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel connect \B \libresocsim_interface3_bank_bus_we connect \Y $and$ls180.v:3221$786_Y end attribute \src "ls180.v:3221.38-3221.152" cell $and $and$ls180.v:3221$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3221$786_Y connect \B $eq$ls180.v:3221$787_Y connect \Y $and$ls180.v:3221$788_Y end attribute \src "ls180.v:3222.39-3222.103" cell $and $and$ls180.v:3222$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel connect \B $not$ls180.v:3222$789_Y connect \Y $and$ls180.v:3222$790_Y end attribute \src "ls180.v:3222.38-3222.155" cell $and $and$ls180.v:3222$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3222$790_Y connect \B $eq$ls180.v:3222$791_Y connect \Y $and$ls180.v:3222$792_Y end attribute \src "ls180.v:3224.38-3224.99" cell $and $and$ls180.v:3224$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel connect \B \libresocsim_interface3_bank_bus_we connect \Y $and$ls180.v:3224$793_Y end attribute \src "ls180.v:3224.37-3224.151" cell $and $and$ls180.v:3224$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3224$793_Y connect \B $eq$ls180.v:3224$794_Y connect \Y $and$ls180.v:3224$795_Y end attribute \src "ls180.v:3225.38-3225.102" cell $and $and$ls180.v:3225$797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank3_sel connect \B $not$ls180.v:3225$796_Y connect \Y $and$ls180.v:3225$797_Y end attribute \src "ls180.v:3225.37-3225.154" cell $and $and$ls180.v:3225$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3225$797_Y connect \B $eq$ls180.v:3225$798_Y connect \Y $and$ls180.v:3225$799_Y end attribute \src "ls180.v:3235.50-3235.111" cell $and $and$ls180.v:3235$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3235$801_Y end attribute \src "ls180.v:3235.49-3235.165" cell $and $and$ls180.v:3235$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3235$801_Y connect \B $eq$ls180.v:3235$802_Y connect \Y $and$ls180.v:3235$803_Y end attribute \src "ls180.v:3236.50-3236.114" cell $and $and$ls180.v:3236$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3236$804_Y connect \Y $and$ls180.v:3236$805_Y end attribute \src "ls180.v:3236.49-3236.168" cell $and $and$ls180.v:3236$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3236$805_Y connect \B $eq$ls180.v:3236$806_Y connect \Y $and$ls180.v:3236$807_Y end attribute \src "ls180.v:3238.54-3238.115" cell $and $and$ls180.v:3238$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3238$808_Y end attribute \src "ls180.v:3238.53-3238.169" cell $and $and$ls180.v:3238$810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3238$808_Y connect \B $eq$ls180.v:3238$809_Y connect \Y $and$ls180.v:3238$810_Y end attribute \src "ls180.v:3239.54-3239.118" cell $and $and$ls180.v:3239$812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3239$811_Y connect \Y $and$ls180.v:3239$812_Y end attribute \src "ls180.v:3239.53-3239.172" cell $and $and$ls180.v:3239$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3239$812_Y connect \B $eq$ls180.v:3239$813_Y connect \Y $and$ls180.v:3239$814_Y end attribute \src "ls180.v:3241.35-3241.96" cell $and $and$ls180.v:3241$815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3241$815_Y end attribute \src "ls180.v:3241.34-3241.150" cell $and $and$ls180.v:3241$817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3241$815_Y connect \B $eq$ls180.v:3241$816_Y connect \Y $and$ls180.v:3241$817_Y end attribute \src "ls180.v:3242.35-3242.99" cell $and $and$ls180.v:3242$819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3242$818_Y connect \Y $and$ls180.v:3242$819_Y end attribute \src "ls180.v:3242.34-3242.153" cell $and $and$ls180.v:3242$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3242$819_Y connect \B $eq$ls180.v:3242$820_Y connect \Y $and$ls180.v:3242$821_Y end attribute \src "ls180.v:3244.54-3244.115" cell $and $and$ls180.v:3244$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3244$822_Y end attribute \src "ls180.v:3244.53-3244.169" cell $and $and$ls180.v:3244$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3244$822_Y connect \B $eq$ls180.v:3244$823_Y connect \Y $and$ls180.v:3244$824_Y end attribute \src "ls180.v:3245.54-3245.118" cell $and $and$ls180.v:3245$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3245$825_Y connect \Y $and$ls180.v:3245$826_Y end attribute \src "ls180.v:3245.53-3245.172" cell $and $and$ls180.v:3245$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3245$826_Y connect \B $eq$ls180.v:3245$827_Y connect \Y $and$ls180.v:3245$828_Y end attribute \src "ls180.v:3247.54-3247.115" cell $and $and$ls180.v:3247$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3247$829_Y end attribute \src "ls180.v:3247.53-3247.169" cell $and $and$ls180.v:3247$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3247$829_Y connect \B $eq$ls180.v:3247$830_Y connect \Y $and$ls180.v:3247$831_Y end attribute \src "ls180.v:3248.54-3248.118" cell $and $and$ls180.v:3248$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3248$832_Y connect \Y $and$ls180.v:3248$833_Y end attribute \src "ls180.v:3248.53-3248.172" cell $and $and$ls180.v:3248$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3248$833_Y connect \B $eq$ls180.v:3248$834_Y connect \Y $and$ls180.v:3248$835_Y end attribute \src "ls180.v:3250.55-3250.116" cell $and $and$ls180.v:3250$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3250$836_Y end attribute \src "ls180.v:3250.54-3250.170" cell $and $and$ls180.v:3250$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3250$836_Y connect \B $eq$ls180.v:3250$837_Y connect \Y $and$ls180.v:3250$838_Y end attribute \src "ls180.v:3251.55-3251.119" cell $and $and$ls180.v:3251$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3251$839_Y connect \Y $and$ls180.v:3251$840_Y end attribute \src "ls180.v:3251.54-3251.173" cell $and $and$ls180.v:3251$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3251$840_Y connect \B $eq$ls180.v:3251$841_Y connect \Y $and$ls180.v:3251$842_Y end attribute \src "ls180.v:3253.53-3253.114" cell $and $and$ls180.v:3253$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3253$843_Y end attribute \src "ls180.v:3253.52-3253.168" cell $and $and$ls180.v:3253$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3253$843_Y connect \B $eq$ls180.v:3253$844_Y connect \Y $and$ls180.v:3253$845_Y end attribute \src "ls180.v:3254.53-3254.117" cell $and $and$ls180.v:3254$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3254$846_Y connect \Y $and$ls180.v:3254$847_Y end attribute \src "ls180.v:3254.52-3254.171" cell $and $and$ls180.v:3254$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3254$847_Y connect \B $eq$ls180.v:3254$848_Y connect \Y $and$ls180.v:3254$849_Y end attribute \src "ls180.v:3256.53-3256.114" cell $and $and$ls180.v:3256$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3256$850_Y end attribute \src "ls180.v:3256.52-3256.168" cell $and $and$ls180.v:3256$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3256$850_Y connect \B $eq$ls180.v:3256$851_Y connect \Y $and$ls180.v:3256$852_Y end attribute \src "ls180.v:3257.53-3257.117" cell $and $and$ls180.v:3257$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3257$853_Y connect \Y $and$ls180.v:3257$854_Y end attribute \src "ls180.v:3257.52-3257.171" cell $and $and$ls180.v:3257$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3257$854_Y connect \B $eq$ls180.v:3257$855_Y connect \Y $and$ls180.v:3257$856_Y end attribute \src "ls180.v:3259.53-3259.114" cell $and $and$ls180.v:3259$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3259$857_Y end attribute \src "ls180.v:3259.52-3259.168" cell $and $and$ls180.v:3259$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3259$857_Y connect \B $eq$ls180.v:3259$858_Y connect \Y $and$ls180.v:3259$859_Y end attribute \src "ls180.v:3260.53-3260.117" cell $and $and$ls180.v:3260$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3260$860_Y connect \Y $and$ls180.v:3260$861_Y end attribute \src "ls180.v:3260.52-3260.171" cell $and $and$ls180.v:3260$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3260$861_Y connect \B $eq$ls180.v:3260$862_Y connect \Y $and$ls180.v:3260$863_Y end attribute \src "ls180.v:3262.53-3262.114" cell $and $and$ls180.v:3262$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B \libresocsim_interface4_bank_bus_we connect \Y $and$ls180.v:3262$864_Y end attribute \src "ls180.v:3262.52-3262.168" cell $and $and$ls180.v:3262$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3262$864_Y connect \B $eq$ls180.v:3262$865_Y connect \Y $and$ls180.v:3262$866_Y end attribute \src "ls180.v:3263.53-3263.117" cell $and $and$ls180.v:3263$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank4_sel connect \B $not$ls180.v:3263$867_Y connect \Y $and$ls180.v:3263$868_Y end attribute \src "ls180.v:3263.52-3263.171" cell $and $and$ls180.v:3263$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3263$868_Y connect \B $eq$ls180.v:3263$869_Y connect \Y $and$ls180.v:3263$870_Y end attribute \src "ls180.v:3280.42-3280.103" cell $and $and$ls180.v:3280$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3280$872_Y end attribute \src "ls180.v:3280.41-3280.157" cell $and $and$ls180.v:3280$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3280$872_Y connect \B $eq$ls180.v:3280$873_Y connect \Y $and$ls180.v:3280$874_Y end attribute \src "ls180.v:3281.42-3281.106" cell $and $and$ls180.v:3281$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3281$875_Y connect \Y $and$ls180.v:3281$876_Y end attribute \src "ls180.v:3281.41-3281.160" cell $and $and$ls180.v:3281$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3281$876_Y connect \B $eq$ls180.v:3281$877_Y connect \Y $and$ls180.v:3281$878_Y end attribute \src "ls180.v:3283.42-3283.103" cell $and $and$ls180.v:3283$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3283$879_Y end attribute \src "ls180.v:3283.41-3283.157" cell $and $and$ls180.v:3283$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3283$879_Y connect \B $eq$ls180.v:3283$880_Y connect \Y $and$ls180.v:3283$881_Y end attribute \src "ls180.v:3284.42-3284.106" cell $and $and$ls180.v:3284$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3284$882_Y connect \Y $and$ls180.v:3284$883_Y end attribute \src "ls180.v:3284.41-3284.160" cell $and $and$ls180.v:3284$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3284$883_Y connect \B $eq$ls180.v:3284$884_Y connect \Y $and$ls180.v:3284$885_Y end attribute \src "ls180.v:3286.42-3286.103" cell $and $and$ls180.v:3286$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3286$886_Y end attribute \src "ls180.v:3286.41-3286.157" cell $and $and$ls180.v:3286$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3286$886_Y connect \B $eq$ls180.v:3286$887_Y connect \Y $and$ls180.v:3286$888_Y end attribute \src "ls180.v:3287.42-3287.106" cell $and $and$ls180.v:3287$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3287$889_Y connect \Y $and$ls180.v:3287$890_Y end attribute \src "ls180.v:3287.41-3287.160" cell $and $and$ls180.v:3287$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3287$890_Y connect \B $eq$ls180.v:3287$891_Y connect \Y $and$ls180.v:3287$892_Y end attribute \src "ls180.v:3289.42-3289.103" cell $and $and$ls180.v:3289$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3289$893_Y end attribute \src "ls180.v:3289.41-3289.157" cell $and $and$ls180.v:3289$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3289$893_Y connect \B $eq$ls180.v:3289$894_Y connect \Y $and$ls180.v:3289$895_Y end attribute \src "ls180.v:3290.42-3290.106" cell $and $and$ls180.v:3290$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3290$896_Y connect \Y $and$ls180.v:3290$897_Y end attribute \src "ls180.v:3290.41-3290.160" cell $and $and$ls180.v:3290$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3290$897_Y connect \B $eq$ls180.v:3290$898_Y connect \Y $and$ls180.v:3290$899_Y end attribute \src "ls180.v:3292.44-3292.105" cell $and $and$ls180.v:3292$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3292$900_Y end attribute \src "ls180.v:3292.43-3292.159" cell $and $and$ls180.v:3292$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3292$900_Y connect \B $eq$ls180.v:3292$901_Y connect \Y $and$ls180.v:3292$902_Y end attribute \src "ls180.v:3293.44-3293.108" cell $and $and$ls180.v:3293$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3293$903_Y connect \Y $and$ls180.v:3293$904_Y end attribute \src "ls180.v:3293.43-3293.162" cell $and $and$ls180.v:3293$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3293$904_Y connect \B $eq$ls180.v:3293$905_Y connect \Y $and$ls180.v:3293$906_Y end attribute \src "ls180.v:3295.44-3295.105" cell $and $and$ls180.v:3295$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3295$907_Y end attribute \src "ls180.v:3295.43-3295.159" cell $and $and$ls180.v:3295$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3295$907_Y connect \B $eq$ls180.v:3295$908_Y connect \Y $and$ls180.v:3295$909_Y end attribute \src "ls180.v:3296.44-3296.108" cell $and $and$ls180.v:3296$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3296$910_Y connect \Y $and$ls180.v:3296$911_Y end attribute \src "ls180.v:3296.43-3296.162" cell $and $and$ls180.v:3296$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3296$911_Y connect \B $eq$ls180.v:3296$912_Y connect \Y $and$ls180.v:3296$913_Y end attribute \src "ls180.v:3298.44-3298.105" cell $and $and$ls180.v:3298$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3298$914_Y end attribute \src "ls180.v:3298.43-3298.159" cell $and $and$ls180.v:3298$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3298$914_Y connect \B $eq$ls180.v:3298$915_Y connect \Y $and$ls180.v:3298$916_Y end attribute \src "ls180.v:3299.44-3299.108" cell $and $and$ls180.v:3299$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3299$917_Y connect \Y $and$ls180.v:3299$918_Y end attribute \src "ls180.v:3299.43-3299.162" cell $and $and$ls180.v:3299$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3299$918_Y connect \B $eq$ls180.v:3299$919_Y connect \Y $and$ls180.v:3299$920_Y end attribute \src "ls180.v:3301.44-3301.105" cell $and $and$ls180.v:3301$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3301$921_Y end attribute \src "ls180.v:3301.43-3301.159" cell $and $and$ls180.v:3301$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3301$921_Y connect \B $eq$ls180.v:3301$922_Y connect \Y $and$ls180.v:3301$923_Y end attribute \src "ls180.v:3302.44-3302.108" cell $and $and$ls180.v:3302$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3302$924_Y connect \Y $and$ls180.v:3302$925_Y end attribute \src "ls180.v:3302.43-3302.162" cell $and $and$ls180.v:3302$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3302$925_Y connect \B $eq$ls180.v:3302$926_Y connect \Y $and$ls180.v:3302$927_Y end attribute \src "ls180.v:3304.40-3304.101" cell $and $and$ls180.v:3304$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3304$928_Y end attribute \src "ls180.v:3304.39-3304.155" cell $and $and$ls180.v:3304$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3304$928_Y connect \B $eq$ls180.v:3304$929_Y connect \Y $and$ls180.v:3304$930_Y end attribute \src "ls180.v:3305.40-3305.104" cell $and $and$ls180.v:3305$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3305$931_Y connect \Y $and$ls180.v:3305$932_Y end attribute \src "ls180.v:3305.39-3305.158" cell $and $and$ls180.v:3305$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3305$932_Y connect \B $eq$ls180.v:3305$933_Y connect \Y $and$ls180.v:3305$934_Y end attribute \src "ls180.v:3307.50-3307.111" cell $and $and$ls180.v:3307$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3307$935_Y end attribute \src "ls180.v:3307.49-3307.165" cell $and $and$ls180.v:3307$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3307$935_Y connect \B $eq$ls180.v:3307$936_Y connect \Y $and$ls180.v:3307$937_Y end attribute \src "ls180.v:3308.50-3308.114" cell $and $and$ls180.v:3308$939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3308$938_Y connect \Y $and$ls180.v:3308$939_Y end attribute \src "ls180.v:3308.49-3308.168" cell $and $and$ls180.v:3308$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3308$939_Y connect \B $eq$ls180.v:3308$940_Y connect \Y $and$ls180.v:3308$941_Y end attribute \src "ls180.v:3310.43-3310.104" cell $and $and$ls180.v:3310$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3310$942_Y end attribute \src "ls180.v:3310.42-3310.159" cell $and $and$ls180.v:3310$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3310$942_Y connect \B $eq$ls180.v:3310$943_Y connect \Y $and$ls180.v:3310$944_Y end attribute \src "ls180.v:3311.43-3311.107" cell $and $and$ls180.v:3311$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3311$945_Y connect \Y $and$ls180.v:3311$946_Y end attribute \src "ls180.v:3311.42-3311.162" cell $and $and$ls180.v:3311$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3311$946_Y connect \B $eq$ls180.v:3311$947_Y connect \Y $and$ls180.v:3311$948_Y end attribute \src "ls180.v:3313.43-3313.104" cell $and $and$ls180.v:3313$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3313$949_Y end attribute \src "ls180.v:3313.42-3313.159" cell $and $and$ls180.v:3313$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3313$949_Y connect \B $eq$ls180.v:3313$950_Y connect \Y $and$ls180.v:3313$951_Y end attribute \src "ls180.v:3314.43-3314.107" cell $and $and$ls180.v:3314$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3314$952_Y connect \Y $and$ls180.v:3314$953_Y end attribute \src "ls180.v:3314.42-3314.162" cell $and $and$ls180.v:3314$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3314$953_Y connect \B $eq$ls180.v:3314$954_Y connect \Y $and$ls180.v:3314$955_Y end attribute \src "ls180.v:3316.43-3316.104" cell $and $and$ls180.v:3316$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3316$956_Y end attribute \src "ls180.v:3316.42-3316.159" cell $and $and$ls180.v:3316$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3316$956_Y connect \B $eq$ls180.v:3316$957_Y connect \Y $and$ls180.v:3316$958_Y end attribute \src "ls180.v:3317.43-3317.107" cell $and $and$ls180.v:3317$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3317$959_Y connect \Y $and$ls180.v:3317$960_Y end attribute \src "ls180.v:3317.42-3317.162" cell $and $and$ls180.v:3317$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3317$960_Y connect \B $eq$ls180.v:3317$961_Y connect \Y $and$ls180.v:3317$962_Y end attribute \src "ls180.v:3319.43-3319.104" cell $and $and$ls180.v:3319$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3319$963_Y end attribute \src "ls180.v:3319.42-3319.159" cell $and $and$ls180.v:3319$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3319$963_Y connect \B $eq$ls180.v:3319$964_Y connect \Y $and$ls180.v:3319$965_Y end attribute \src "ls180.v:3320.43-3320.107" cell $and $and$ls180.v:3320$967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3320$966_Y connect \Y $and$ls180.v:3320$967_Y end attribute \src "ls180.v:3320.42-3320.162" cell $and $and$ls180.v:3320$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3320$967_Y connect \B $eq$ls180.v:3320$968_Y connect \Y $and$ls180.v:3320$969_Y end attribute \src "ls180.v:3322.47-3322.108" cell $and $and$ls180.v:3322$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3322$970_Y end attribute \src "ls180.v:3322.46-3322.163" cell $and $and$ls180.v:3322$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3322$970_Y connect \B $eq$ls180.v:3322$971_Y connect \Y $and$ls180.v:3322$972_Y end attribute \src "ls180.v:3323.47-3323.111" cell $and $and$ls180.v:3323$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3323$973_Y connect \Y $and$ls180.v:3323$974_Y end attribute \src "ls180.v:3323.46-3323.166" cell $and $and$ls180.v:3323$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3323$974_Y connect \B $eq$ls180.v:3323$975_Y connect \Y $and$ls180.v:3323$976_Y end attribute \src "ls180.v:3325.48-3325.109" cell $and $and$ls180.v:3325$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3325$977_Y end attribute \src "ls180.v:3325.47-3325.164" cell $and $and$ls180.v:3325$979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3325$977_Y connect \B $eq$ls180.v:3325$978_Y connect \Y $and$ls180.v:3325$979_Y end attribute \src "ls180.v:3326.48-3326.112" cell $and $and$ls180.v:3326$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3326$980_Y connect \Y $and$ls180.v:3326$981_Y end attribute \src "ls180.v:3326.47-3326.167" cell $and $and$ls180.v:3326$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3326$981_Y connect \B $eq$ls180.v:3326$982_Y connect \Y $and$ls180.v:3326$983_Y end attribute \src "ls180.v:3328.47-3328.108" cell $and $and$ls180.v:3328$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B \libresocsim_interface5_bank_bus_we connect \Y $and$ls180.v:3328$984_Y end attribute \src "ls180.v:3328.46-3328.163" cell $and $and$ls180.v:3328$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3328$984_Y connect \B $eq$ls180.v:3328$985_Y connect \Y $and$ls180.v:3328$986_Y end attribute \src "ls180.v:3329.47-3329.111" cell $and $and$ls180.v:3329$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank5_sel connect \B $not$ls180.v:3329$987_Y connect \Y $and$ls180.v:3329$988_Y end attribute \src "ls180.v:3329.46-3329.166" cell $and $and$ls180.v:3329$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3329$988_Y connect \B $eq$ls180.v:3329$989_Y connect \Y $and$ls180.v:3329$990_Y end attribute \src "ls180.v:3348.20-3348.81" cell $and $and$ls180.v:3348$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3348$992_Y end attribute \src "ls180.v:3348.19-3348.135" cell $and $and$ls180.v:3348$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3348$992_Y connect \B $eq$ls180.v:3348$993_Y connect \Y $and$ls180.v:3348$994_Y end attribute \src "ls180.v:3349.20-3349.84" cell $and $and$ls180.v:3349$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3349$995_Y connect \Y $and$ls180.v:3349$996_Y end attribute \src "ls180.v:3349.19-3349.138" cell $and $and$ls180.v:3349$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3349$996_Y connect \B $eq$ls180.v:3349$997_Y connect \Y $and$ls180.v:3349$998_Y end attribute \src "ls180.v:3351.42-3351.158" cell $and $and$ls180.v:3351$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3351$999_Y connect \B $eq$ls180.v:3351$1000_Y connect \Y $and$ls180.v:3351$1001_Y end attribute \src "ls180.v:3351.43-3351.104" cell $and $and$ls180.v:3351$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3351$999_Y end attribute \src "ls180.v:3352.43-3352.107" cell $and $and$ls180.v:3352$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3352$1002_Y connect \Y $and$ls180.v:3352$1003_Y end attribute \src "ls180.v:3352.42-3352.161" cell $and $and$ls180.v:3352$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3352$1003_Y connect \B $eq$ls180.v:3352$1004_Y connect \Y $and$ls180.v:3352$1005_Y end attribute \src "ls180.v:3354.44-3354.105" cell $and $and$ls180.v:3354$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3354$1006_Y end attribute \src "ls180.v:3354.43-3354.159" cell $and $and$ls180.v:3354$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3354$1006_Y connect \B $eq$ls180.v:3354$1007_Y connect \Y $and$ls180.v:3354$1008_Y end attribute \src "ls180.v:3355.44-3355.108" cell $and $and$ls180.v:3355$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3355$1009_Y connect \Y $and$ls180.v:3355$1010_Y end attribute \src "ls180.v:3355.43-3355.162" cell $and $and$ls180.v:3355$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3355$1010_Y connect \B $eq$ls180.v:3355$1011_Y connect \Y $and$ls180.v:3355$1012_Y end attribute \src "ls180.v:3357.35-3357.96" cell $and $and$ls180.v:3357$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3357$1013_Y end attribute \src "ls180.v:3357.34-3357.150" cell $and $and$ls180.v:3357$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3357$1013_Y connect \B $eq$ls180.v:3357$1014_Y connect \Y $and$ls180.v:3357$1015_Y end attribute \src "ls180.v:3358.35-3358.99" cell $and $and$ls180.v:3358$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3358$1016_Y connect \Y $and$ls180.v:3358$1017_Y end attribute \src "ls180.v:3358.34-3358.153" cell $and $and$ls180.v:3358$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3358$1017_Y connect \B $eq$ls180.v:3358$1018_Y connect \Y $and$ls180.v:3358$1019_Y end attribute \src "ls180.v:3360.36-3360.97" cell $and $and$ls180.v:3360$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3360$1020_Y end attribute \src "ls180.v:3360.35-3360.151" cell $and $and$ls180.v:3360$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3360$1020_Y connect \B $eq$ls180.v:3360$1021_Y connect \Y $and$ls180.v:3360$1022_Y end attribute \src "ls180.v:3361.36-3361.100" cell $and $and$ls180.v:3361$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3361$1023_Y connect \Y $and$ls180.v:3361$1024_Y end attribute \src "ls180.v:3361.35-3361.154" cell $and $and$ls180.v:3361$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3361$1024_Y connect \B $eq$ls180.v:3361$1025_Y connect \Y $and$ls180.v:3361$1026_Y end attribute \src "ls180.v:3363.47-3363.108" cell $and $and$ls180.v:3363$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3363$1027_Y end attribute \src "ls180.v:3363.46-3363.162" cell $and $and$ls180.v:3363$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3363$1027_Y connect \B $eq$ls180.v:3363$1028_Y connect \Y $and$ls180.v:3363$1029_Y end attribute \src "ls180.v:3364.47-3364.111" cell $and $and$ls180.v:3364$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3364$1030_Y connect \Y $and$ls180.v:3364$1031_Y end attribute \src "ls180.v:3364.46-3364.165" cell $and $and$ls180.v:3364$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3364$1031_Y connect \B $eq$ls180.v:3364$1032_Y connect \Y $and$ls180.v:3364$1033_Y end attribute \src "ls180.v:3366.44-3366.105" cell $and $and$ls180.v:3366$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3366$1034_Y end attribute \src "ls180.v:3366.43-3366.159" cell $and $and$ls180.v:3366$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3366$1034_Y connect \B $eq$ls180.v:3366$1035_Y connect \Y $and$ls180.v:3366$1036_Y end attribute \src "ls180.v:3367.44-3367.108" cell $and $and$ls180.v:3367$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3367$1037_Y connect \Y $and$ls180.v:3367$1038_Y end attribute \src "ls180.v:3367.43-3367.162" cell $and $and$ls180.v:3367$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3367$1038_Y connect \B $eq$ls180.v:3367$1039_Y connect \Y $and$ls180.v:3367$1040_Y end attribute \src "ls180.v:3369.43-3369.104" cell $and $and$ls180.v:3369$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B \libresocsim_interface6_bank_bus_we connect \Y $and$ls180.v:3369$1041_Y end attribute \src "ls180.v:3369.42-3369.158" cell $and $and$ls180.v:3369$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3369$1041_Y connect \B $eq$ls180.v:3369$1042_Y connect \Y $and$ls180.v:3369$1043_Y end attribute \src "ls180.v:3370.43-3370.107" cell $and $and$ls180.v:3370$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank6_sel connect \B $not$ls180.v:3370$1044_Y connect \Y $and$ls180.v:3370$1045_Y end attribute \src "ls180.v:3370.42-3370.161" cell $and $and$ls180.v:3370$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3370$1045_Y connect \B $eq$ls180.v:3370$1046_Y connect \Y $and$ls180.v:3370$1047_Y end attribute \src "ls180.v:3382.49-3382.110" cell $and $and$ls180.v:3382$1049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we connect \Y $and$ls180.v:3382$1049_Y end attribute \src "ls180.v:3382.48-3382.164" cell $and $and$ls180.v:3382$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3382$1049_Y connect \B $eq$ls180.v:3382$1050_Y connect \Y $and$ls180.v:3382$1051_Y end attribute \src "ls180.v:3383.49-3383.113" cell $and $and$ls180.v:3383$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B $not$ls180.v:3383$1052_Y connect \Y $and$ls180.v:3383$1053_Y end attribute \src "ls180.v:3383.48-3383.167" cell $and $and$ls180.v:3383$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3383$1053_Y connect \B $eq$ls180.v:3383$1054_Y connect \Y $and$ls180.v:3383$1055_Y end attribute \src "ls180.v:3385.49-3385.110" cell $and $and$ls180.v:3385$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we connect \Y $and$ls180.v:3385$1056_Y end attribute \src "ls180.v:3385.48-3385.164" cell $and $and$ls180.v:3385$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3385$1056_Y connect \B $eq$ls180.v:3385$1057_Y connect \Y $and$ls180.v:3385$1058_Y end attribute \src "ls180.v:3386.49-3386.113" cell $and $and$ls180.v:3386$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B $not$ls180.v:3386$1059_Y connect \Y $and$ls180.v:3386$1060_Y end attribute \src "ls180.v:3386.48-3386.167" cell $and $and$ls180.v:3386$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3386$1060_Y connect \B $eq$ls180.v:3386$1061_Y connect \Y $and$ls180.v:3386$1062_Y end attribute \src "ls180.v:3388.49-3388.110" cell $and $and$ls180.v:3388$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we connect \Y $and$ls180.v:3388$1063_Y end attribute \src "ls180.v:3388.48-3388.164" cell $and $and$ls180.v:3388$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3388$1063_Y connect \B $eq$ls180.v:3388$1064_Y connect \Y $and$ls180.v:3388$1065_Y end attribute \src "ls180.v:3389.49-3389.113" cell $and $and$ls180.v:3389$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B $not$ls180.v:3389$1066_Y connect \Y $and$ls180.v:3389$1067_Y end attribute \src "ls180.v:3389.48-3389.167" cell $and $and$ls180.v:3389$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3389$1067_Y connect \B $eq$ls180.v:3389$1068_Y connect \Y $and$ls180.v:3389$1069_Y end attribute \src "ls180.v:3391.49-3391.110" cell $and $and$ls180.v:3391$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B \libresocsim_interface7_bank_bus_we connect \Y $and$ls180.v:3391$1070_Y end attribute \src "ls180.v:3391.48-3391.164" cell $and $and$ls180.v:3391$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3391$1070_Y connect \B $eq$ls180.v:3391$1071_Y connect \Y $and$ls180.v:3391$1072_Y end attribute \src "ls180.v:3392.49-3392.113" cell $and $and$ls180.v:3392$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_csrbank7_sel connect \B $not$ls180.v:3392$1073_Y connect \Y $and$ls180.v:3392$1074_Y end attribute \src "ls180.v:3392.48-3392.167" cell $and $and$ls180.v:3392$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3392$1074_Y connect \B $eq$ls180.v:3392$1075_Y connect \Y $and$ls180.v:3392$1076_Y end attribute \src "ls180.v:3752.96-3752.165" cell $and $and$ls180.v:3752$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:3752$1106_Y connect \Y $and$ls180.v:3752$1107_Y end attribute \src "ls180.v:3752.171-3752.240" cell $and $and$ls180.v:3752$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:3752$1109_Y connect \Y $and$ls180.v:3752$1110_Y end attribute \src "ls180.v:3752.246-3752.315" cell $and $and$ls180.v:3752$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:3752$1112_Y connect \Y $and$ls180.v:3752$1113_Y end attribute \src "ls180.v:3752.27-3752.318" cell $and $and$ls180.v:3752$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:3752$1105_Y connect \B $not$ls180.v:3752$1115_Y connect \Y $and$ls180.v:3752$1116_Y end attribute \src "ls180.v:3752.26-3752.336" cell $and $and$ls180.v:3752$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3752$1116_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:3752$1117_Y end attribute \src "ls180.v:3776.96-3776.165" cell $and $and$ls180.v:3776$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:3776$1122_Y connect \Y $and$ls180.v:3776$1123_Y end attribute \src "ls180.v:3776.171-3776.240" cell $and $and$ls180.v:3776$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:3776$1125_Y connect \Y $and$ls180.v:3776$1126_Y end attribute \src "ls180.v:3776.246-3776.315" cell $and $and$ls180.v:3776$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:3776$1128_Y connect \Y $and$ls180.v:3776$1129_Y end attribute \src "ls180.v:3776.27-3776.318" cell $and $and$ls180.v:3776$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:3776$1121_Y connect \B $not$ls180.v:3776$1131_Y connect \Y $and$ls180.v:3776$1132_Y end attribute \src "ls180.v:3776.26-3776.336" cell $and $and$ls180.v:3776$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3776$1132_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:3776$1133_Y end attribute \src "ls180.v:3800.96-3800.165" cell $and $and$ls180.v:3800$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:3800$1138_Y connect \Y $and$ls180.v:3800$1139_Y end attribute \src "ls180.v:3800.171-3800.240" cell $and $and$ls180.v:3800$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:3800$1141_Y connect \Y $and$ls180.v:3800$1142_Y end attribute \src "ls180.v:3800.246-3800.315" cell $and $and$ls180.v:3800$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \B $eq$ls180.v:3800$1144_Y connect \Y $and$ls180.v:3800$1145_Y end attribute \src "ls180.v:3800.27-3800.318" cell $and $and$ls180.v:3800$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:3800$1137_Y connect \B $not$ls180.v:3800$1147_Y connect \Y $and$ls180.v:3800$1148_Y end attribute \src "ls180.v:3800.26-3800.336" cell $and $and$ls180.v:3800$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3800$1148_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:3800$1149_Y end attribute \src "ls180.v:3824.96-3824.165" cell $and $and$ls180.v:3824$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \B $eq$ls180.v:3824$1154_Y connect \Y $and$ls180.v:3824$1155_Y end attribute \src "ls180.v:3824.171-3824.240" cell $and $and$ls180.v:3824$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \B $eq$ls180.v:3824$1157_Y connect \Y $and$ls180.v:3824$1158_Y end attribute \src "ls180.v:3824.246-3824.315" cell $and $and$ls180.v:3824$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \B $eq$ls180.v:3824$1160_Y connect \Y $and$ls180.v:3824$1161_Y end attribute \src "ls180.v:3824.27-3824.318" cell $and $and$ls180.v:3824$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:3824$1153_Y connect \B $not$ls180.v:3824$1163_Y connect \Y $and$ls180.v:3824$1164_Y end attribute \src "ls180.v:3824.26-3824.336" cell $and $and$ls180.v:3824$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3824$1164_Y connect \B \port_cmd_valid connect \Y $and$ls180.v:3824$1165_Y end attribute \src "ls180.v:3981.22-3981.77" cell $and $and$ls180.v:3981$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:3981$1177_Y end attribute \src "ls180.v:3981.21-3981.113" cell $and $and$ls180.v:3981$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3981$1177_Y connect \B \sdram_choose_req_cmd_payload_cas connect \Y $and$ls180.v:3981$1178_Y end attribute \src "ls180.v:3984.22-3984.77" cell $and $and$ls180.v:3984$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:3984$1179_Y end attribute \src "ls180.v:3984.21-3984.113" cell $and $and$ls180.v:3984$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3984$1179_Y connect \B \sdram_choose_req_cmd_payload_cas connect \Y $and$ls180.v:3984$1180_Y end attribute \src "ls180.v:3987.22-3987.55" cell $and $and$ls180.v:3987$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready connect \Y $and$ls180.v:3987$1181_Y end attribute \src "ls180.v:3987.21-3987.80" cell $and $and$ls180.v:3987$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3987$1181_Y connect \B \sdram_cmd_payload_cas connect \Y $and$ls180.v:3987$1182_Y end attribute \src "ls180.v:3998.22-3998.77" cell $and $and$ls180.v:3998$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:3998$1184_Y end attribute \src "ls180.v:3998.21-3998.113" cell $and $and$ls180.v:3998$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:3998$1184_Y connect \B \sdram_choose_req_cmd_payload_ras connect \Y $and$ls180.v:3998$1185_Y end attribute \src "ls180.v:4001.22-4001.77" cell $and $and$ls180.v:4001$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:4001$1186_Y end attribute \src "ls180.v:4001.21-4001.113" cell $and $and$ls180.v:4001$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4001$1186_Y connect \B \sdram_choose_req_cmd_payload_ras connect \Y $and$ls180.v:4001$1187_Y end attribute \src "ls180.v:4004.22-4004.55" cell $and $and$ls180.v:4004$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready connect \Y $and$ls180.v:4004$1188_Y end attribute \src "ls180.v:4004.21-4004.80" cell $and $and$ls180.v:4004$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4004$1188_Y connect \B \sdram_cmd_payload_ras connect \Y $and$ls180.v:4004$1189_Y end attribute \src "ls180.v:4015.22-4015.77" cell $and $and$ls180.v:4015$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:4015$1191_Y end attribute \src "ls180.v:4015.21-4015.112" cell $and $and$ls180.v:4015$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4015$1191_Y connect \B \sdram_choose_req_cmd_payload_we connect \Y $and$ls180.v:4015$1192_Y end attribute \src "ls180.v:4018.22-4018.77" cell $and $and$ls180.v:4018$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:4018$1193_Y end attribute \src "ls180.v:4018.21-4018.112" cell $and $and$ls180.v:4018$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4018$1193_Y connect \B \sdram_choose_req_cmd_payload_we connect \Y $and$ls180.v:4018$1194_Y end attribute \src "ls180.v:4021.22-4021.55" cell $and $and$ls180.v:4021$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready connect \Y $and$ls180.v:4021$1195_Y end attribute \src "ls180.v:4021.21-4021.79" cell $and $and$ls180.v:4021$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4021$1195_Y connect \B \sdram_cmd_payload_we connect \Y $and$ls180.v:4021$1196_Y end attribute \src "ls180.v:4032.22-4032.77" cell $and $and$ls180.v:4032$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:4032$1198_Y end attribute \src "ls180.v:4032.21-4032.117" cell $and $and$ls180.v:4032$1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4032$1198_Y connect \B \sdram_choose_req_cmd_payload_is_read connect \Y $and$ls180.v:4032$1199_Y end attribute \src "ls180.v:4035.22-4035.77" cell $and $and$ls180.v:4035$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:4035$1200_Y end attribute \src "ls180.v:4035.21-4035.117" cell $and $and$ls180.v:4035$1201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4035$1200_Y connect \B \sdram_choose_req_cmd_payload_is_read connect \Y $and$ls180.v:4035$1201_Y end attribute \src "ls180.v:4038.22-4038.55" cell $and $and$ls180.v:4038$1202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready connect \Y $and$ls180.v:4038$1202_Y end attribute \src "ls180.v:4038.21-4038.84" cell $and $and$ls180.v:4038$1203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4038$1202_Y connect \B \sdram_cmd_payload_is_read connect \Y $and$ls180.v:4038$1203_Y end attribute \src "ls180.v:4049.22-4049.77" cell $and $and$ls180.v:4049$1205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:4049$1205_Y end attribute \src "ls180.v:4049.21-4049.118" cell $and $and$ls180.v:4049$1206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4049$1205_Y connect \B \sdram_choose_req_cmd_payload_is_write connect \Y $and$ls180.v:4049$1206_Y end attribute \src "ls180.v:4052.22-4052.77" cell $and $and$ls180.v:4052$1207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \B \sdram_choose_req_cmd_ready connect \Y $and$ls180.v:4052$1207_Y end attribute \src "ls180.v:4052.21-4052.118" cell $and $and$ls180.v:4052$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4052$1207_Y connect \B \sdram_choose_req_cmd_payload_is_write connect \Y $and$ls180.v:4052$1208_Y end attribute \src "ls180.v:4055.22-4055.55" cell $and $and$ls180.v:4055$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_cmd_valid connect \B \sdram_cmd_ready connect \Y $and$ls180.v:4055$1209_Y end attribute \src "ls180.v:4055.21-4055.85" cell $and $and$ls180.v:4055$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4055$1209_Y connect \B \sdram_cmd_payload_is_write connect \Y $and$ls180.v:4055$1210_Y end attribute \src "ls180.v:4223.57-4223.97" cell $and $and$ls180.v:4223$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dfi_p0_wrdata_en connect \B \dfi_p0_wrdata_mask [0] connect \Y $and$ls180.v:4223$1213_Y end attribute \src "ls180.v:4224.57-4224.97" cell $and $and$ls180.v:4224$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dfi_p0_wrdata_en connect \B \dfi_p0_wrdata_mask [1] connect \Y $and$ls180.v:4224$1214_Y end attribute \src "ls180.v:4356.8-4356.57" cell $and $and$ls180.v:4356$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_cyc connect \B \libresocsim_ram_bus_stb connect \Y $and$ls180.v:4356$1261_Y end attribute \src "ls180.v:4356.7-4356.87" cell $and $and$ls180.v:4356$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4356$1261_Y connect \B $not$ls180.v:4356$1262_Y connect \Y $and$ls180.v:4356$1263_Y end attribute \src "ls180.v:4375.7-4375.65" cell $and $and$ls180.v:4375$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4375$1266_Y connect \B \libresocsim_zero_old_trigger connect \Y $and$ls180.v:4375$1267_Y end attribute \src "ls180.v:4379.8-4379.49" cell $and $and$ls180.v:4379$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_cyc connect \B \ram_bus_ram_bus_stb connect \Y $and$ls180.v:4379$1268_Y end attribute \src "ls180.v:4379.7-4379.75" cell $and $and$ls180.v:4379$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4379$1268_Y connect \B $not$ls180.v:4379$1269_Y connect \Y $and$ls180.v:4379$1270_Y end attribute \src "ls180.v:4387.7-4387.46" cell $and $and$ls180.v:4387$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_timer_wait connect \B $not$ls180.v:4387$1271_Y connect \Y $and$ls180.v:4387$1272_Y end attribute \src "ls180.v:4415.7-4415.65" cell $and $and$ls180.v:4415$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_start1 connect \B $eq$ls180.v:4415$1278_Y connect \Y $and$ls180.v:4415$1279_Y end attribute \src "ls180.v:4457.8-4457.121" cell $and $and$ls180.v:4457$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \Y $and$ls180.v:4457$1285_Y end attribute \src "ls180.v:4457.7-4457.175" cell $and $and$ls180.v:4457$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4457$1285_Y connect \B $not$ls180.v:4457$1286_Y connect \Y $and$ls180.v:4457$1287_Y end attribute \src "ls180.v:4463.8-4463.121" cell $and $and$ls180.v:4463$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \Y $and$ls180.v:4463$1290_Y end attribute \src "ls180.v:4463.7-4463.175" cell $and $and$ls180.v:4463$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4463$1290_Y connect \B $not$ls180.v:4463$1291_Y connect \Y $and$ls180.v:4463$1292_Y end attribute \src "ls180.v:4503.8-4503.121" cell $and $and$ls180.v:4503$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \Y $and$ls180.v:4503$1301_Y end attribute \src "ls180.v:4503.7-4503.175" cell $and $and$ls180.v:4503$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4503$1301_Y connect \B $not$ls180.v:4503$1302_Y connect \Y $and$ls180.v:4503$1303_Y end attribute \src "ls180.v:4509.8-4509.121" cell $and $and$ls180.v:4509$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \Y $and$ls180.v:4509$1306_Y end attribute \src "ls180.v:4509.7-4509.175" cell $and $and$ls180.v:4509$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4509$1306_Y connect \B $not$ls180.v:4509$1307_Y connect \Y $and$ls180.v:4509$1308_Y end attribute \src "ls180.v:4549.8-4549.121" cell $and $and$ls180.v:4549$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \Y $and$ls180.v:4549$1317_Y end attribute \src "ls180.v:4549.7-4549.175" cell $and $and$ls180.v:4549$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4549$1317_Y connect \B $not$ls180.v:4549$1318_Y connect \Y $and$ls180.v:4549$1319_Y end attribute \src "ls180.v:4555.8-4555.121" cell $and $and$ls180.v:4555$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \Y $and$ls180.v:4555$1322_Y end attribute \src "ls180.v:4555.7-4555.175" cell $and $and$ls180.v:4555$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4555$1322_Y connect \B $not$ls180.v:4555$1323_Y connect \Y $and$ls180.v:4555$1324_Y end attribute \src "ls180.v:4595.8-4595.121" cell $and $and$ls180.v:4595$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \Y $and$ls180.v:4595$1333_Y end attribute \src "ls180.v:4595.7-4595.175" cell $and $and$ls180.v:4595$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4595$1333_Y connect \B $not$ls180.v:4595$1334_Y connect \Y $and$ls180.v:4595$1335_Y end attribute \src "ls180.v:4601.8-4601.121" cell $and $and$ls180.v:4601$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \Y $and$ls180.v:4601$1338_Y end attribute \src "ls180.v:4601.7-4601.175" cell $and $and$ls180.v:4601$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4601$1338_Y connect \B $not$ls180.v:4601$1339_Y connect \Y $and$ls180.v:4601$1340_Y end attribute \src "ls180.v:4798.53-4798.129" cell $and $and$ls180.v:4798$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4798$1364_Y connect \B \sdram_interface_bank0_wdata_ready connect \Y $and$ls180.v:4798$1365_Y end attribute \src "ls180.v:4798.135-4798.211" cell $and $and$ls180.v:4798$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4798$1367_Y connect \B \sdram_interface_bank1_wdata_ready connect \Y $and$ls180.v:4798$1368_Y end attribute \src "ls180.v:4798.217-4798.293" cell $and $and$ls180.v:4798$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4798$1370_Y connect \B \sdram_interface_bank2_wdata_ready connect \Y $and$ls180.v:4798$1371_Y end attribute \src "ls180.v:4798.299-4798.375" cell $and $and$ls180.v:4798$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4798$1373_Y connect \B \sdram_interface_bank3_wdata_ready connect \Y $and$ls180.v:4798$1374_Y end attribute \src "ls180.v:4799.54-4799.130" cell $and $and$ls180.v:4799$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4799$1376_Y connect \B \sdram_interface_bank0_rdata_valid connect \Y $and$ls180.v:4799$1377_Y end attribute \src "ls180.v:4799.136-4799.212" cell $and $and$ls180.v:4799$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4799$1379_Y connect \B \sdram_interface_bank1_rdata_valid connect \Y $and$ls180.v:4799$1380_Y end attribute \src "ls180.v:4799.218-4799.294" cell $and $and$ls180.v:4799$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4799$1382_Y connect \B \sdram_interface_bank2_rdata_valid connect \Y $and$ls180.v:4799$1383_Y end attribute \src "ls180.v:4799.300-4799.376" cell $and $and$ls180.v:4799$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $eq$ls180.v:4799$1385_Y connect \B \sdram_interface_bank3_rdata_valid connect \Y $and$ls180.v:4799$1386_Y end attribute \src "ls180.v:4818.8-4818.39" cell $and $and$ls180.v:4818$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \port_cmd_ready connect \Y $and$ls180.v:4818$1389_Y end attribute \src "ls180.v:4821.8-4821.43" cell $and $and$ls180.v:4821$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_wdata_valid connect \B \port_wdata_ready connect \Y $and$ls180.v:4821$1390_Y end attribute \src "ls180.v:4826.8-4826.49" cell $and $and$ls180.v:4826$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_sink_valid connect \B $not$ls180.v:4826$1391_Y connect \Y $and$ls180.v:4826$1392_Y end attribute \src "ls180.v:4826.7-4826.75" cell $and $and$ls180.v:4826$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4826$1392_Y connect \B $not$ls180.v:4826$1393_Y connect \Y $and$ls180.v:4826$1394_Y end attribute \src "ls180.v:4832.8-4832.49" cell $and $and$ls180.v:4832$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_uart_clk_txen connect \B \uart_phy_tx_busy connect \Y $and$ls180.v:4832$1395_Y end attribute \src "ls180.v:4856.8-4856.38" cell $and $and$ls180.v:4856$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4856$1401_Y connect \B \uart_phy_rx_r connect \Y $and$ls180.v:4856$1402_Y end attribute \src "ls180.v:4889.7-4889.37" cell $and $and$ls180.v:4889$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4889$1407_Y connect \B \tx_old_trigger connect \Y $and$ls180.v:4889$1408_Y end attribute \src "ls180.v:4896.7-4896.37" cell $and $and$ls180.v:4896$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4896$1409_Y connect \B \rx_old_trigger connect \Y $and$ls180.v:4896$1410_Y end attribute \src "ls180.v:4906.8-4906.55" cell $and $and$ls180.v:4906$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_we connect \B \tx_fifo_syncfifo_writable connect \Y $and$ls180.v:4906$1411_Y end attribute \src "ls180.v:4906.7-4906.77" cell $and $and$ls180.v:4906$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4906$1411_Y connect \B $not$ls180.v:4906$1412_Y connect \Y $and$ls180.v:4906$1413_Y end attribute \src "ls180.v:4912.8-4912.55" cell $and $and$ls180.v:4912$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_we connect \B \tx_fifo_syncfifo_writable connect \Y $and$ls180.v:4912$1416_Y end attribute \src "ls180.v:4912.7-4912.77" cell $and $and$ls180.v:4912$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4912$1416_Y connect \B $not$ls180.v:4912$1417_Y connect \Y $and$ls180.v:4912$1418_Y end attribute \src "ls180.v:4928.8-4928.55" cell $and $and$ls180.v:4928$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_we connect \B \rx_fifo_syncfifo_writable connect \Y $and$ls180.v:4928$1422_Y end attribute \src "ls180.v:4928.7-4928.77" cell $and $and$ls180.v:4928$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4928$1422_Y connect \B $not$ls180.v:4928$1423_Y connect \Y $and$ls180.v:4928$1424_Y end attribute \src "ls180.v:4934.8-4934.55" cell $and $and$ls180.v:4934$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_we connect \B \rx_fifo_syncfifo_writable connect \Y $and$ls180.v:4934$1427_Y end attribute \src "ls180.v:4934.7-4934.77" cell $and $and$ls180.v:4934$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:4934$1427_Y connect \B $not$ls180.v:4934$1428_Y connect \Y $and$ls180.v:4934$1429_Y end attribute \src "ls180.v:1547.37-1547.91" cell $eq $eq$ls180.v:1547$21 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_converted_interface_sel connect \B 1'0 connect \Y $eq$ls180.v:1547$21_Y end attribute \src "ls180.v:1554.11-1554.49" cell $eq $eq$ls180.v:1554$26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_counter connect \B 1'1 connect \Y $eq$ls180.v:1554$26_Y end attribute \src "ls180.v:1607.37-1607.91" cell $eq $eq$ls180.v:1607$32 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_converted_interface_sel connect \B 1'0 connect \Y $eq$ls180.v:1607$32_Y end attribute \src "ls180.v:1614.11-1614.49" cell $eq $eq$ls180.v:1614$37 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_counter connect \B 1'1 connect \Y $eq$ls180.v:1614$37_Y end attribute \src "ls180.v:1667.37-1667.91" cell $eq $eq$ls180.v:1667$43 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_converted_interface_sel connect \B 1'0 connect \Y $eq$ls180.v:1667$43_Y end attribute \src "ls180.v:1674.11-1674.49" cell $eq $eq$ls180.v:1674$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_counter connect \B 1'1 connect \Y $eq$ls180.v:1674$48_Y end attribute \src "ls180.v:1870.29-1870.55" cell $eq $eq$ls180.v:1870$89 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_timer_count1 connect \B 1'0 connect \Y $eq$ls180.v:1870$89_Y end attribute \src "ls180.v:1874.58-1874.87" cell $eq $eq$ls180.v:1874$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'0 connect \Y $eq$ls180.v:1874$92_Y end attribute \src "ls180.v:1918.38-1918.119" cell $eq $eq$ls180.v:1918$97 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_row connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] connect \Y $eq$ls180.v:1918$97_Y end attribute \src "ls180.v:1935.42-1935.78" cell $eq $eq$ls180.v:1935$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_row_close connect \B 1'0 connect \Y $eq$ls180.v:1935$110_Y end attribute \src "ls180.v:2075.38-2075.119" cell $eq $eq$ls180.v:2075$127 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_row connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] connect \Y $eq$ls180.v:2075$127_Y end attribute \src "ls180.v:2092.42-2092.78" cell $eq $eq$ls180.v:2092$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_row_close connect \B 1'0 connect \Y $eq$ls180.v:2092$140_Y end attribute \src "ls180.v:2232.38-2232.119" cell $eq $eq$ls180.v:2232$157 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_row connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] connect \Y $eq$ls180.v:2232$157_Y end attribute \src "ls180.v:2249.42-2249.78" cell $eq $eq$ls180.v:2249$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_row_close connect \B 1'0 connect \Y $eq$ls180.v:2249$170_Y end attribute \src "ls180.v:2389.38-2389.119" cell $eq $eq$ls180.v:2389$187 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_row connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] connect \Y $eq$ls180.v:2389$187_Y end attribute \src "ls180.v:2406.42-2406.78" cell $eq $eq$ls180.v:2406$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_row_close connect \B 1'0 connect \Y $eq$ls180.v:2406$200_Y end attribute \src "ls180.v:2543.27-2543.46" cell $eq $eq$ls180.v:2543$247 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_time0 connect \B 1'0 connect \Y $eq$ls180.v:2543$247_Y end attribute \src "ls180.v:2544.27-2544.46" cell $eq $eq$ls180.v:2544$248 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_time1 connect \B 1'0 connect \Y $eq$ls180.v:2544$248_Y end attribute \src "ls180.v:2555.299-2555.368" cell $eq $eq$ls180.v:2555$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads connect \Y $eq$ls180.v:2555$262_Y end attribute \src "ls180.v:2555.373-2555.444" cell $eq $eq$ls180.v:2555$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes connect \Y $eq$ls180.v:2555$263_Y end attribute \src "ls180.v:2556.299-2556.368" cell $eq $eq$ls180.v:2556$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads connect \Y $eq$ls180.v:2556$275_Y end attribute \src "ls180.v:2556.373-2556.444" cell $eq $eq$ls180.v:2556$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes connect \Y $eq$ls180.v:2556$276_Y end attribute \src "ls180.v:2557.299-2557.368" cell $eq $eq$ls180.v:2557$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads connect \Y $eq$ls180.v:2557$288_Y end attribute \src "ls180.v:2557.373-2557.444" cell $eq $eq$ls180.v:2557$289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes connect \Y $eq$ls180.v:2557$289_Y end attribute \src "ls180.v:2558.299-2558.368" cell $eq $eq$ls180.v:2558$301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_read connect \B \sdram_choose_cmd_want_reads connect \Y $eq$ls180.v:2558$301_Y end attribute \src "ls180.v:2558.373-2558.444" cell $eq $eq$ls180.v:2558$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_write connect \B \sdram_choose_cmd_want_writes connect \Y $eq$ls180.v:2558$302_Y end attribute \src "ls180.v:2588.299-2588.368" cell $eq $eq$ls180.v:2588$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_read connect \B \sdram_choose_req_want_reads connect \Y $eq$ls180.v:2588$320_Y end attribute \src "ls180.v:2588.373-2588.444" cell $eq $eq$ls180.v:2588$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_is_write connect \B \sdram_choose_req_want_writes connect \Y $eq$ls180.v:2588$321_Y end attribute \src "ls180.v:2589.299-2589.368" cell $eq $eq$ls180.v:2589$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_read connect \B \sdram_choose_req_want_reads connect \Y $eq$ls180.v:2589$333_Y end attribute \src "ls180.v:2589.373-2589.444" cell $eq $eq$ls180.v:2589$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_is_write connect \B \sdram_choose_req_want_writes connect \Y $eq$ls180.v:2589$334_Y end attribute \src "ls180.v:2590.299-2590.368" cell $eq $eq$ls180.v:2590$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_read connect \B \sdram_choose_req_want_reads connect \Y $eq$ls180.v:2590$346_Y end attribute \src "ls180.v:2590.373-2590.444" cell $eq $eq$ls180.v:2590$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_is_write connect \B \sdram_choose_req_want_writes connect \Y $eq$ls180.v:2590$347_Y end attribute \src "ls180.v:2591.299-2591.368" cell $eq $eq$ls180.v:2591$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_read connect \B \sdram_choose_req_want_reads connect \Y $eq$ls180.v:2591$359_Y end attribute \src "ls180.v:2591.373-2591.444" cell $eq $eq$ls180.v:2591$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_is_write connect \B \sdram_choose_req_want_writes connect \Y $eq$ls180.v:2591$360_Y end attribute \src "ls180.v:2620.68-2620.98" cell $eq $eq$ls180.v:2620$369 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 1'0 connect \Y $eq$ls180.v:2620$369_Y end attribute \src "ls180.v:2623.68-2623.98" cell $eq $eq$ls180.v:2623$372 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 1'0 connect \Y $eq$ls180.v:2623$372_Y end attribute \src "ls180.v:2629.68-2629.98" cell $eq $eq$ls180.v:2629$376 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 1'1 connect \Y $eq$ls180.v:2629$376_Y end attribute \src "ls180.v:2632.68-2632.98" cell $eq $eq$ls180.v:2632$379 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 1'1 connect \Y $eq$ls180.v:2632$379_Y end attribute \src "ls180.v:2638.68-2638.98" cell $eq $eq$ls180.v:2638$383 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 2'10 connect \Y $eq$ls180.v:2638$383_Y end attribute \src "ls180.v:2641.68-2641.98" cell $eq $eq$ls180.v:2641$386 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 2'10 connect \Y $eq$ls180.v:2641$386_Y end attribute \src "ls180.v:2647.68-2647.98" cell $eq $eq$ls180.v:2647$390 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_grant connect \B 2'11 connect \Y $eq$ls180.v:2647$390_Y end attribute \src "ls180.v:2650.68-2650.98" cell $eq $eq$ls180.v:2650$393 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_grant connect \B 2'11 connect \Y $eq$ls180.v:2650$393_Y end attribute \src "ls180.v:2731.47-2731.82" cell $eq $eq$ls180.v:2731$416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'0 connect \Y $eq$ls180.v:2731$416_Y end attribute \src "ls180.v:2731.145-2731.183" cell $eq $eq$ls180.v:2731$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:2731$417_Y end attribute \src "ls180.v:2731.220-2731.258" cell $eq $eq$ls180.v:2731$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:2731$420_Y end attribute \src "ls180.v:2731.295-2731.333" cell $eq $eq$ls180.v:2731$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:2731$423_Y end attribute \src "ls180.v:2736.47-2736.82" cell $eq $eq$ls180.v:2736$432 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'1 connect \Y $eq$ls180.v:2736$432_Y end attribute \src "ls180.v:2736.145-2736.183" cell $eq $eq$ls180.v:2736$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:2736$433_Y end attribute \src "ls180.v:2736.220-2736.258" cell $eq $eq$ls180.v:2736$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:2736$436_Y end attribute \src "ls180.v:2736.295-2736.333" cell $eq $eq$ls180.v:2736$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:2736$439_Y end attribute \src "ls180.v:2741.47-2741.82" cell $eq $eq$ls180.v:2741$448 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'10 connect \Y $eq$ls180.v:2741$448_Y end attribute \src "ls180.v:2741.145-2741.183" cell $eq $eq$ls180.v:2741$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:2741$449_Y end attribute \src "ls180.v:2741.220-2741.258" cell $eq $eq$ls180.v:2741$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:2741$452_Y end attribute \src "ls180.v:2741.295-2741.333" cell $eq $eq$ls180.v:2741$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:2741$455_Y end attribute \src "ls180.v:2746.47-2746.82" cell $eq $eq$ls180.v:2746$464 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'11 connect \Y $eq$ls180.v:2746$464_Y end attribute \src "ls180.v:2746.145-2746.183" cell $eq $eq$ls180.v:2746$465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:2746$465_Y end attribute \src "ls180.v:2746.220-2746.258" cell $eq $eq$ls180.v:2746$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:2746$468_Y end attribute \src "ls180.v:2746.295-2746.333" cell $eq $eq$ls180.v:2746$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:2746$471_Y end attribute \src "ls180.v:2751.39-2751.77" cell $eq $eq$ls180.v:2751$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$480_Y end attribute \src "ls180.v:2751.83-2751.118" cell $eq $eq$ls180.v:2751$481 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'0 connect \Y $eq$ls180.v:2751$481_Y end attribute \src "ls180.v:2751.181-2751.219" cell $eq $eq$ls180.v:2751$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$482_Y end attribute \src "ls180.v:2751.256-2751.294" cell $eq $eq$ls180.v:2751$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$485_Y end attribute \src "ls180.v:2751.331-2751.369" cell $eq $eq$ls180.v:2751$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$488_Y end attribute \src "ls180.v:2751.413-2751.451" cell $eq $eq$ls180.v:2751$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$496_Y end attribute \src "ls180.v:2751.457-2751.492" cell $eq $eq$ls180.v:2751$497 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'1 connect \Y $eq$ls180.v:2751$497_Y end attribute \src "ls180.v:2751.555-2751.593" cell $eq $eq$ls180.v:2751$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$498_Y end attribute \src "ls180.v:2751.630-2751.668" cell $eq $eq$ls180.v:2751$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$501_Y end attribute \src "ls180.v:2751.705-2751.743" cell $eq $eq$ls180.v:2751$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$504_Y end attribute \src "ls180.v:2751.787-2751.825" cell $eq $eq$ls180.v:2751$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$512_Y end attribute \src "ls180.v:2751.831-2751.866" cell $eq $eq$ls180.v:2751$513 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'10 connect \Y $eq$ls180.v:2751$513_Y end attribute \src "ls180.v:2751.929-2751.967" cell $eq $eq$ls180.v:2751$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$514_Y end attribute \src "ls180.v:2751.1004-2751.1042" cell $eq $eq$ls180.v:2751$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$517_Y end attribute \src "ls180.v:2751.1079-2751.1117" cell $eq $eq$ls180.v:2751$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$520_Y end attribute \src "ls180.v:2751.1161-2751.1199" cell $eq $eq$ls180.v:2751$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$528_Y end attribute \src "ls180.v:2751.1205-2751.1240" cell $eq $eq$ls180.v:2751$529 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'11 connect \Y $eq$ls180.v:2751$529_Y end attribute \src "ls180.v:2751.1303-2751.1341" cell $eq $eq$ls180.v:2751$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$530_Y end attribute \src "ls180.v:2751.1378-2751.1416" cell $eq $eq$ls180.v:2751$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$533_Y end attribute \src "ls180.v:2751.1453-2751.1491" cell $eq $eq$ls180.v:2751$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:2751$536_Y end attribute \src "ls180.v:2810.24-2810.47" cell $eq $eq$ls180.v:2810$549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_sel connect \B 1'0 connect \Y $eq$ls180.v:2810$549_Y end attribute \src "ls180.v:2817.11-2817.36" cell $eq $eq$ls180.v:2817$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \converter_counter connect \B 1'1 connect \Y $eq$ls180.v:2817$554_Y end attribute \src "ls180.v:3074.84-3074.109" cell $eq $eq$ls180.v:3074$626 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'0 connect \Y $eq$ls180.v:3074$626_Y end attribute \src "ls180.v:3075.84-3075.109" cell $eq $eq$ls180.v:3075$628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'1 connect \Y $eq$ls180.v:3075$628_Y end attribute \src "ls180.v:3076.84-3076.109" cell $eq $eq$ls180.v:3076$630 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 2'10 connect \Y $eq$ls180.v:3076$630_Y end attribute \src "ls180.v:3077.84-3077.109" cell $eq $eq$ls180.v:3077$632 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'0 connect \Y $eq$ls180.v:3077$632_Y end attribute \src "ls180.v:3078.84-3078.109" cell $eq $eq$ls180.v:3078$634 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 1'1 connect \Y $eq$ls180.v:3078$634_Y end attribute \src "ls180.v:3079.84-3079.109" cell $eq $eq$ls180.v:3079$636 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_grant connect \B 2'10 connect \Y $eq$ls180.v:3079$636_Y end attribute \src "ls180.v:3083.31-3083.67" cell $eq $eq$ls180.v:3083$639 parameter \A_SIGNED 0 parameter \A_WIDTH 23 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:7] connect \B 1'0 connect \Y $eq$ls180.v:3083$639_Y end attribute \src "ls180.v:3084.31-3084.68" cell $eq $eq$ls180.v:3084$640 parameter \A_SIGNED 0 parameter \A_WIDTH 25 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:5] connect \B 4'1110 connect \Y $eq$ls180.v:3084$640_Y end attribute \src "ls180.v:3085.31-3085.76" cell $eq $eq$ls180.v:3085$641 parameter \A_SIGNED 0 parameter \A_WIDTH 27 parameter \B_SIGNED 0 parameter \B_WIDTH 27 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:3] connect \B 27'110000000000000100000000000 connect \Y $eq$ls180.v:3085$641_Y end attribute \src "ls180.v:3086.31-3086.74" cell $eq $eq$ls180.v:3086$642 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 20 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:10] connect \B 20'11000000000000010001 connect \Y $eq$ls180.v:3086$642_Y end attribute \src "ls180.v:3087.31-3087.69" cell $eq $eq$ls180.v:3087$643 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:23] connect \B 7'1001000 connect \Y $eq$ls180.v:3087$643_Y end attribute \src "ls180.v:3088.31-3088.73" cell $eq $eq$ls180.v:3088$644 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_adr [29:14] connect \B 16'1100000000000000 connect \Y $eq$ls180.v:3088$644_Y end attribute \src "ls180.v:3152.28-3152.53" cell $eq $eq$ls180.v:3152$676 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_count connect \B 1'0 connect \Y $eq$ls180.v:3152$676_Y end attribute \src "ls180.v:3153.36-3153.85" cell $eq $eq$ls180.v:3153$677 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [13:9] connect \B 1'0 connect \Y $eq$ls180.v:3153$677_Y end attribute \src "ls180.v:3155.109-3155.157" cell $eq $eq$ls180.v:3155$679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'0 connect \Y $eq$ls180.v:3155$679_Y end attribute \src "ls180.v:3156.112-3156.160" cell $eq $eq$ls180.v:3156$683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'0 connect \Y $eq$ls180.v:3156$683_Y end attribute \src "ls180.v:3158.111-3158.159" cell $eq $eq$ls180.v:3158$686 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'1 connect \Y $eq$ls180.v:3158$686_Y end attribute \src "ls180.v:3159.114-3159.162" cell $eq $eq$ls180.v:3159$690 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 1'1 connect \Y $eq$ls180.v:3159$690_Y end attribute \src "ls180.v:3161.111-3161.159" cell $eq $eq$ls180.v:3161$693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'10 connect \Y $eq$ls180.v:3161$693_Y end attribute \src "ls180.v:3162.114-3162.162" cell $eq $eq$ls180.v:3162$697 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'10 connect \Y $eq$ls180.v:3162$697_Y end attribute \src "ls180.v:3164.111-3164.159" cell $eq $eq$ls180.v:3164$700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'11 connect \Y $eq$ls180.v:3164$700_Y end attribute \src "ls180.v:3165.114-3165.162" cell $eq $eq$ls180.v:3165$704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 2'11 connect \Y $eq$ls180.v:3165$704_Y end attribute \src "ls180.v:3167.111-3167.159" cell $eq $eq$ls180.v:3167$707 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'100 connect \Y $eq$ls180.v:3167$707_Y end attribute \src "ls180.v:3168.114-3168.162" cell $eq $eq$ls180.v:3168$711 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'100 connect \Y $eq$ls180.v:3168$711_Y end attribute \src "ls180.v:3170.114-3170.162" cell $eq $eq$ls180.v:3170$714 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'101 connect \Y $eq$ls180.v:3170$714_Y end attribute \src "ls180.v:3171.117-3171.165" cell $eq $eq$ls180.v:3171$718 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'101 connect \Y $eq$ls180.v:3171$718_Y end attribute \src "ls180.v:3173.114-3173.162" cell $eq $eq$ls180.v:3173$721 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'110 connect \Y $eq$ls180.v:3173$721_Y end attribute \src "ls180.v:3174.117-3174.165" cell $eq $eq$ls180.v:3174$725 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'110 connect \Y $eq$ls180.v:3174$725_Y end attribute \src "ls180.v:3176.114-3176.162" cell $eq $eq$ls180.v:3176$728 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'111 connect \Y $eq$ls180.v:3176$728_Y end attribute \src "ls180.v:3177.117-3177.165" cell $eq $eq$ls180.v:3177$732 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 3'111 connect \Y $eq$ls180.v:3177$732_Y end attribute \src "ls180.v:3179.114-3179.162" cell $eq $eq$ls180.v:3179$735 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 4'1000 connect \Y $eq$ls180.v:3179$735_Y end attribute \src "ls180.v:3180.117-3180.165" cell $eq $eq$ls180.v:3180$739 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_adr [3:0] connect \B 4'1000 connect \Y $eq$ls180.v:3180$739_Y end attribute \src "ls180.v:3191.36-3191.85" cell $eq $eq$ls180.v:3191$741 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [13:9] connect \B 3'110 connect \Y $eq$ls180.v:3191$741_Y end attribute \src "ls180.v:3193.106-3193.154" cell $eq $eq$ls180.v:3193$743 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'0 connect \Y $eq$ls180.v:3193$743_Y end attribute \src "ls180.v:3194.109-3194.157" cell $eq $eq$ls180.v:3194$747 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'0 connect \Y $eq$ls180.v:3194$747_Y end attribute \src "ls180.v:3196.105-3196.153" cell $eq $eq$ls180.v:3196$750 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'1 connect \Y $eq$ls180.v:3196$750_Y end attribute \src "ls180.v:3197.108-3197.156" cell $eq $eq$ls180.v:3197$754 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 1'1 connect \Y $eq$ls180.v:3197$754_Y end attribute \src "ls180.v:3199.107-3199.155" cell $eq $eq$ls180.v:3199$757 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 2'10 connect \Y $eq$ls180.v:3199$757_Y end attribute \src "ls180.v:3200.110-3200.158" cell $eq $eq$ls180.v:3200$761 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_adr [1:0] connect \B 2'10 connect \Y $eq$ls180.v:3200$761_Y end attribute \src "ls180.v:3205.36-3205.85" cell $eq $eq$ls180.v:3205$763 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [13:9] connect \B 3'111 connect \Y $eq$ls180.v:3205$763_Y end attribute \src "ls180.v:3207.106-3207.154" cell $eq $eq$ls180.v:3207$765 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'0 connect \Y $eq$ls180.v:3207$765_Y end attribute \src "ls180.v:3208.109-3208.157" cell $eq $eq$ls180.v:3208$769 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'0 connect \Y $eq$ls180.v:3208$769_Y end attribute \src "ls180.v:3210.105-3210.153" cell $eq $eq$ls180.v:3210$772 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'1 connect \Y $eq$ls180.v:3210$772_Y end attribute \src "ls180.v:3211.108-3211.156" cell $eq $eq$ls180.v:3211$776 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 1'1 connect \Y $eq$ls180.v:3211$776_Y end attribute \src "ls180.v:3213.107-3213.155" cell $eq $eq$ls180.v:3213$779 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 2'10 connect \Y $eq$ls180.v:3213$779_Y end attribute \src "ls180.v:3214.110-3214.158" cell $eq $eq$ls180.v:3214$783 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_adr [1:0] connect \B 2'10 connect \Y $eq$ls180.v:3214$783_Y end attribute \src "ls180.v:3219.36-3219.85" cell $eq $eq$ls180.v:3219$785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [13:9] connect \B 4'1000 connect \Y $eq$ls180.v:3219$785_Y end attribute \src "ls180.v:3221.105-3221.151" cell $eq $eq$ls180.v:3221$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'0 connect \Y $eq$ls180.v:3221$787_Y end attribute \src "ls180.v:3222.108-3222.154" cell $eq $eq$ls180.v:3222$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'0 connect \Y $eq$ls180.v:3222$791_Y end attribute \src "ls180.v:3224.104-3224.150" cell $eq $eq$ls180.v:3224$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'1 connect \Y $eq$ls180.v:3224$794_Y end attribute \src "ls180.v:3225.107-3225.153" cell $eq $eq$ls180.v:3225$798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_adr [0] connect \B 1'1 connect \Y $eq$ls180.v:3225$798_Y end attribute \src "ls180.v:3233.36-3233.85" cell $eq $eq$ls180.v:3233$800 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [13:9] connect \B 2'11 connect \Y $eq$ls180.v:3233$800_Y end attribute \src "ls180.v:3235.116-3235.164" cell $eq $eq$ls180.v:3235$802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'0 connect \Y $eq$ls180.v:3235$802_Y end attribute \src "ls180.v:3236.119-3236.167" cell $eq $eq$ls180.v:3236$806 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'0 connect \Y $eq$ls180.v:3236$806_Y end attribute \src "ls180.v:3238.120-3238.168" cell $eq $eq$ls180.v:3238$809 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'1 connect \Y $eq$ls180.v:3238$809_Y end attribute \src "ls180.v:3239.123-3239.171" cell $eq $eq$ls180.v:3239$813 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 1'1 connect \Y $eq$ls180.v:3239$813_Y end attribute \src "ls180.v:3241.101-3241.149" cell $eq $eq$ls180.v:3241$816 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'10 connect \Y $eq$ls180.v:3241$816_Y end attribute \src "ls180.v:3242.104-3242.152" cell $eq $eq$ls180.v:3242$820 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'10 connect \Y $eq$ls180.v:3242$820_Y end attribute \src "ls180.v:3244.120-3244.168" cell $eq $eq$ls180.v:3244$823 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'11 connect \Y $eq$ls180.v:3244$823_Y end attribute \src "ls180.v:3245.123-3245.171" cell $eq $eq$ls180.v:3245$827 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 2'11 connect \Y $eq$ls180.v:3245$827_Y end attribute \src "ls180.v:3247.120-3247.168" cell $eq $eq$ls180.v:3247$830 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'100 connect \Y $eq$ls180.v:3247$830_Y end attribute \src "ls180.v:3248.123-3248.171" cell $eq $eq$ls180.v:3248$834 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'100 connect \Y $eq$ls180.v:3248$834_Y end attribute \src "ls180.v:3250.121-3250.169" cell $eq $eq$ls180.v:3250$837 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'101 connect \Y $eq$ls180.v:3250$837_Y end attribute \src "ls180.v:3251.124-3251.172" cell $eq $eq$ls180.v:3251$841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'101 connect \Y $eq$ls180.v:3251$841_Y end attribute \src "ls180.v:3253.119-3253.167" cell $eq $eq$ls180.v:3253$844 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'110 connect \Y $eq$ls180.v:3253$844_Y end attribute \src "ls180.v:3254.122-3254.170" cell $eq $eq$ls180.v:3254$848 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'110 connect \Y $eq$ls180.v:3254$848_Y end attribute \src "ls180.v:3256.119-3256.167" cell $eq $eq$ls180.v:3256$851 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'111 connect \Y $eq$ls180.v:3256$851_Y end attribute \src "ls180.v:3257.122-3257.170" cell $eq $eq$ls180.v:3257$855 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 3'111 connect \Y $eq$ls180.v:3257$855_Y end attribute \src "ls180.v:3259.119-3259.167" cell $eq $eq$ls180.v:3259$858 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1000 connect \Y $eq$ls180.v:3259$858_Y end attribute \src "ls180.v:3260.122-3260.170" cell $eq $eq$ls180.v:3260$862 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1000 connect \Y $eq$ls180.v:3260$862_Y end attribute \src "ls180.v:3262.119-3262.167" cell $eq $eq$ls180.v:3262$865 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1001 connect \Y $eq$ls180.v:3262$865_Y end attribute \src "ls180.v:3263.122-3263.170" cell $eq $eq$ls180.v:3263$869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_adr [3:0] connect \B 4'1001 connect \Y $eq$ls180.v:3263$869_Y end attribute \src "ls180.v:3278.36-3278.85" cell $eq $eq$ls180.v:3278$871 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [13:9] connect \B 2'10 connect \Y $eq$ls180.v:3278$871_Y end attribute \src "ls180.v:3280.108-3280.156" cell $eq $eq$ls180.v:3280$873 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'0 connect \Y $eq$ls180.v:3280$873_Y end attribute \src "ls180.v:3281.111-3281.159" cell $eq $eq$ls180.v:3281$877 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'0 connect \Y $eq$ls180.v:3281$877_Y end attribute \src "ls180.v:3283.108-3283.156" cell $eq $eq$ls180.v:3283$880 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'1 connect \Y $eq$ls180.v:3283$880_Y end attribute \src "ls180.v:3284.111-3284.159" cell $eq $eq$ls180.v:3284$884 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 1'1 connect \Y $eq$ls180.v:3284$884_Y end attribute \src "ls180.v:3286.108-3286.156" cell $eq $eq$ls180.v:3286$887 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'10 connect \Y $eq$ls180.v:3286$887_Y end attribute \src "ls180.v:3287.111-3287.159" cell $eq $eq$ls180.v:3287$891 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'10 connect \Y $eq$ls180.v:3287$891_Y end attribute \src "ls180.v:3289.108-3289.156" cell $eq $eq$ls180.v:3289$894 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'11 connect \Y $eq$ls180.v:3289$894_Y end attribute \src "ls180.v:3290.111-3290.159" cell $eq $eq$ls180.v:3290$898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 2'11 connect \Y $eq$ls180.v:3290$898_Y end attribute \src "ls180.v:3292.110-3292.158" cell $eq $eq$ls180.v:3292$901 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'100 connect \Y $eq$ls180.v:3292$901_Y end attribute \src "ls180.v:3293.113-3293.161" cell $eq $eq$ls180.v:3293$905 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'100 connect \Y $eq$ls180.v:3293$905_Y end attribute \src "ls180.v:3295.110-3295.158" cell $eq $eq$ls180.v:3295$908 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'101 connect \Y $eq$ls180.v:3295$908_Y end attribute \src "ls180.v:3296.113-3296.161" cell $eq $eq$ls180.v:3296$912 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'101 connect \Y $eq$ls180.v:3296$912_Y end attribute \src "ls180.v:3298.110-3298.158" cell $eq $eq$ls180.v:3298$915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'110 connect \Y $eq$ls180.v:3298$915_Y end attribute \src "ls180.v:3299.113-3299.161" cell $eq $eq$ls180.v:3299$919 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'110 connect \Y $eq$ls180.v:3299$919_Y end attribute \src "ls180.v:3301.110-3301.158" cell $eq $eq$ls180.v:3301$922 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'111 connect \Y $eq$ls180.v:3301$922_Y end attribute \src "ls180.v:3302.113-3302.161" cell $eq $eq$ls180.v:3302$926 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 3'111 connect \Y $eq$ls180.v:3302$926_Y end attribute \src "ls180.v:3304.106-3304.154" cell $eq $eq$ls180.v:3304$929 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1000 connect \Y $eq$ls180.v:3304$929_Y end attribute \src "ls180.v:3305.109-3305.157" cell $eq $eq$ls180.v:3305$933 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1000 connect \Y $eq$ls180.v:3305$933_Y end attribute \src "ls180.v:3307.116-3307.164" cell $eq $eq$ls180.v:3307$936 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1001 connect \Y $eq$ls180.v:3307$936_Y end attribute \src "ls180.v:3308.119-3308.167" cell $eq $eq$ls180.v:3308$940 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1001 connect \Y $eq$ls180.v:3308$940_Y end attribute \src "ls180.v:3310.109-3310.158" cell $eq $eq$ls180.v:3310$943 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1010 connect \Y $eq$ls180.v:3310$943_Y end attribute \src "ls180.v:3311.112-3311.161" cell $eq $eq$ls180.v:3311$947 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1010 connect \Y $eq$ls180.v:3311$947_Y end attribute \src "ls180.v:3313.109-3313.158" cell $eq $eq$ls180.v:3313$950 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1011 connect \Y $eq$ls180.v:3313$950_Y end attribute \src "ls180.v:3314.112-3314.161" cell $eq $eq$ls180.v:3314$954 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1011 connect \Y $eq$ls180.v:3314$954_Y end attribute \src "ls180.v:3316.109-3316.158" cell $eq $eq$ls180.v:3316$957 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1100 connect \Y $eq$ls180.v:3316$957_Y end attribute \src "ls180.v:3317.112-3317.161" cell $eq $eq$ls180.v:3317$961 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1100 connect \Y $eq$ls180.v:3317$961_Y end attribute \src "ls180.v:3319.109-3319.158" cell $eq $eq$ls180.v:3319$964 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1101 connect \Y $eq$ls180.v:3319$964_Y end attribute \src "ls180.v:3320.112-3320.161" cell $eq $eq$ls180.v:3320$968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1101 connect \Y $eq$ls180.v:3320$968_Y end attribute \src "ls180.v:3322.113-3322.162" cell $eq $eq$ls180.v:3322$971 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1110 connect \Y $eq$ls180.v:3322$971_Y end attribute \src "ls180.v:3323.116-3323.165" cell $eq $eq$ls180.v:3323$975 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1110 connect \Y $eq$ls180.v:3323$975_Y end attribute \src "ls180.v:3325.114-3325.163" cell $eq $eq$ls180.v:3325$978 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1111 connect \Y $eq$ls180.v:3325$978_Y end attribute \src "ls180.v:3326.117-3326.166" cell $eq $eq$ls180.v:3326$982 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 4'1111 connect \Y $eq$ls180.v:3326$982_Y end attribute \src "ls180.v:3328.113-3328.162" cell $eq $eq$ls180.v:3328$985 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 5'10000 connect \Y $eq$ls180.v:3328$985_Y end attribute \src "ls180.v:3329.116-3329.165" cell $eq $eq$ls180.v:3329$989 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_adr [4:0] connect \B 5'10000 connect \Y $eq$ls180.v:3329$989_Y end attribute \src "ls180.v:3346.36-3346.85" cell $eq $eq$ls180.v:3346$991 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [13:9] connect \B 3'101 connect \Y $eq$ls180.v:3346$991_Y end attribute \src "ls180.v:3348.86-3348.134" cell $eq $eq$ls180.v:3348$993 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'0 connect \Y $eq$ls180.v:3348$993_Y end attribute \src "ls180.v:3349.89-3349.137" cell $eq $eq$ls180.v:3349$997 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'0 connect \Y $eq$ls180.v:3349$997_Y end attribute \src "ls180.v:3351.109-3351.157" cell $eq $eq$ls180.v:3351$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'1 connect \Y $eq$ls180.v:3351$1000_Y end attribute \src "ls180.v:3352.112-3352.160" cell $eq $eq$ls180.v:3352$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 1'1 connect \Y $eq$ls180.v:3352$1004_Y end attribute \src "ls180.v:3354.110-3354.158" cell $eq $eq$ls180.v:3354$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'10 connect \Y $eq$ls180.v:3354$1007_Y end attribute \src "ls180.v:3355.113-3355.161" cell $eq $eq$ls180.v:3355$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'10 connect \Y $eq$ls180.v:3355$1011_Y end attribute \src "ls180.v:3357.101-3357.149" cell $eq $eq$ls180.v:3357$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'11 connect \Y $eq$ls180.v:3357$1014_Y end attribute \src "ls180.v:3358.104-3358.152" cell $eq $eq$ls180.v:3358$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 2'11 connect \Y $eq$ls180.v:3358$1018_Y end attribute \src "ls180.v:3360.102-3360.150" cell $eq $eq$ls180.v:3360$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'100 connect \Y $eq$ls180.v:3360$1021_Y end attribute \src "ls180.v:3361.105-3361.153" cell $eq $eq$ls180.v:3361$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'100 connect \Y $eq$ls180.v:3361$1025_Y end attribute \src "ls180.v:3363.113-3363.161" cell $eq $eq$ls180.v:3363$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'101 connect \Y $eq$ls180.v:3363$1028_Y end attribute \src "ls180.v:3364.116-3364.164" cell $eq $eq$ls180.v:3364$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'101 connect \Y $eq$ls180.v:3364$1032_Y end attribute \src "ls180.v:3366.110-3366.158" cell $eq $eq$ls180.v:3366$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'110 connect \Y $eq$ls180.v:3366$1035_Y end attribute \src "ls180.v:3367.113-3367.161" cell $eq $eq$ls180.v:3367$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'110 connect \Y $eq$ls180.v:3367$1039_Y end attribute \src "ls180.v:3369.109-3369.157" cell $eq $eq$ls180.v:3369$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'111 connect \Y $eq$ls180.v:3369$1042_Y end attribute \src "ls180.v:3370.112-3370.160" cell $eq $eq$ls180.v:3370$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_adr [2:0] connect \B 3'111 connect \Y $eq$ls180.v:3370$1046_Y end attribute \src "ls180.v:3380.36-3380.85" cell $eq $eq$ls180.v:3380$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [13:9] connect \B 3'100 connect \Y $eq$ls180.v:3380$1048_Y end attribute \src "ls180.v:3382.115-3382.163" cell $eq $eq$ls180.v:3382$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'0 connect \Y $eq$ls180.v:3382$1050_Y end attribute \src "ls180.v:3383.118-3383.166" cell $eq $eq$ls180.v:3383$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'0 connect \Y $eq$ls180.v:3383$1054_Y end attribute \src "ls180.v:3385.115-3385.163" cell $eq $eq$ls180.v:3385$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'1 connect \Y $eq$ls180.v:3385$1057_Y end attribute \src "ls180.v:3386.118-3386.166" cell $eq $eq$ls180.v:3386$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 1'1 connect \Y $eq$ls180.v:3386$1061_Y end attribute \src "ls180.v:3388.115-3388.163" cell $eq $eq$ls180.v:3388$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'10 connect \Y $eq$ls180.v:3388$1064_Y end attribute \src "ls180.v:3389.118-3389.166" cell $eq $eq$ls180.v:3389$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'10 connect \Y $eq$ls180.v:3389$1068_Y end attribute \src "ls180.v:3391.115-3391.163" cell $eq $eq$ls180.v:3391$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'11 connect \Y $eq$ls180.v:3391$1071_Y end attribute \src "ls180.v:3392.118-3392.166" cell $eq $eq$ls180.v:3392$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_adr [1:0] connect \B 2'11 connect \Y $eq$ls180.v:3392$1075_Y end attribute \src "ls180.v:3752.28-3752.63" cell $eq $eq$ls180.v:3752$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'0 connect \Y $eq$ls180.v:3752$1105_Y end attribute \src "ls180.v:3752.126-3752.164" cell $eq $eq$ls180.v:3752$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:3752$1106_Y end attribute \src "ls180.v:3752.201-3752.239" cell $eq $eq$ls180.v:3752$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:3752$1109_Y end attribute \src "ls180.v:3752.276-3752.314" cell $eq $eq$ls180.v:3752$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:3752$1112_Y end attribute \src "ls180.v:3776.28-3776.63" cell $eq $eq$ls180.v:3776$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 1'1 connect \Y $eq$ls180.v:3776$1121_Y end attribute \src "ls180.v:3776.126-3776.164" cell $eq $eq$ls180.v:3776$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:3776$1122_Y end attribute \src "ls180.v:3776.201-3776.239" cell $eq $eq$ls180.v:3776$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:3776$1125_Y end attribute \src "ls180.v:3776.276-3776.314" cell $eq $eq$ls180.v:3776$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:3776$1128_Y end attribute \src "ls180.v:3800.28-3800.63" cell $eq $eq$ls180.v:3800$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'10 connect \Y $eq$ls180.v:3800$1137_Y end attribute \src "ls180.v:3800.126-3800.164" cell $eq $eq$ls180.v:3800$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:3800$1138_Y end attribute \src "ls180.v:3800.201-3800.239" cell $eq $eq$ls180.v:3800$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:3800$1141_Y end attribute \src "ls180.v:3800.276-3800.314" cell $eq $eq$ls180.v:3800$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:3800$1144_Y end attribute \src "ls180.v:3824.28-3824.63" cell $eq $eq$ls180.v:3824$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_addr [10:9] connect \B 2'11 connect \Y $eq$ls180.v:3824$1153_Y end attribute \src "ls180.v:3824.126-3824.164" cell $eq $eq$ls180.v:3824$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:3824$1154_Y end attribute \src "ls180.v:3824.201-3824.239" cell $eq $eq$ls180.v:3824$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:3824$1157_Y end attribute \src "ls180.v:3824.276-3824.314" cell $eq $eq$ls180.v:3824$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:3824$1160_Y end attribute \src "ls180.v:4360.8-4360.33" cell $eq $eq$ls180.v:4360$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_value connect \B 1'0 connect \Y $eq$ls180.v:4360$1264_Y end attribute \src "ls180.v:4395.8-4395.37" cell $eq $eq$ls180.v:4395$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_postponer_count connect \B 1'0 connect \Y $eq$ls180.v:4395$1275_Y end attribute \src "ls180.v:4415.33-4415.64" cell $eq $eq$ls180.v:4415$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 1'0 connect \Y $eq$ls180.v:4415$1278_Y end attribute \src "ls180.v:4422.7-4422.38" cell $eq $eq$ls180.v:4422$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 2'10 connect \Y $eq$ls180.v:4422$1280_Y end attribute \src "ls180.v:4429.7-4429.38" cell $eq $eq$ls180.v:4429$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 4'1000 connect \Y $eq$ls180.v:4429$1281_Y end attribute \src "ls180.v:4437.7-4437.38" cell $eq $eq$ls180.v:4437$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 4'1000 connect \Y $eq$ls180.v:4437$1282_Y end attribute \src "ls180.v:4489.9-4489.49" cell $eq $eq$ls180.v:4489$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_count connect \B 1'1 connect \Y $eq$ls180.v:4489$1300_Y end attribute \src "ls180.v:4535.9-4535.49" cell $eq $eq$ls180.v:4535$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_count connect \B 1'1 connect \Y $eq$ls180.v:4535$1316_Y end attribute \src "ls180.v:4581.9-4581.49" cell $eq $eq$ls180.v:4581$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_count connect \B 1'1 connect \Y $eq$ls180.v:4581$1332_Y end attribute \src "ls180.v:4627.9-4627.49" cell $eq $eq$ls180.v:4627$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_count connect \B 1'1 connect \Y $eq$ls180.v:4627$1348_Y end attribute \src "ls180.v:4777.9-4777.36" cell $eq $eq$ls180.v:4777$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_tccdcon_count connect \B 1'1 connect \Y $eq$ls180.v:4777$1360_Y end attribute \src "ls180.v:4792.9-4792.36" cell $eq $eq$ls180.v:4792$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_twtrcon_count connect \B 1'1 connect \Y $eq$ls180.v:4792$1363_Y end attribute \src "ls180.v:4798.54-4798.92" cell $eq $eq$ls180.v:4798$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:4798$1364_Y end attribute \src "ls180.v:4798.136-4798.174" cell $eq $eq$ls180.v:4798$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:4798$1367_Y end attribute \src "ls180.v:4798.218-4798.256" cell $eq $eq$ls180.v:4798$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:4798$1370_Y end attribute \src "ls180.v:4798.300-4798.338" cell $eq $eq$ls180.v:4798$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:4798$1373_Y end attribute \src "ls180.v:4799.55-4799.93" cell $eq $eq$ls180.v:4799$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin0_grant connect \B 1'0 connect \Y $eq$ls180.v:4799$1376_Y end attribute \src "ls180.v:4799.137-4799.175" cell $eq $eq$ls180.v:4799$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin1_grant connect \B 1'0 connect \Y $eq$ls180.v:4799$1379_Y end attribute \src "ls180.v:4799.219-4799.257" cell $eq $eq$ls180.v:4799$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin2_grant connect \B 1'0 connect \Y $eq$ls180.v:4799$1382_Y end attribute \src "ls180.v:4799.301-4799.339" cell $eq $eq$ls180.v:4799$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_roundrobin3_grant connect \B 1'0 connect \Y $eq$ls180.v:4799$1385_Y end attribute \src "ls180.v:4834.9-4834.37" cell $eq $eq$ls180.v:4834$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \uart_phy_tx_bitcount connect \B 4'1000 connect \Y $eq$ls180.v:4834$1397_Y end attribute \src "ls180.v:4837.10-4837.38" cell $eq $eq$ls180.v:4837$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \uart_phy_tx_bitcount connect \B 4'1001 connect \Y $eq$ls180.v:4837$1398_Y end attribute \src "ls180.v:4863.9-4863.37" cell $eq $eq$ls180.v:4863$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_rx_bitcount connect \B 1'0 connect \Y $eq$ls180.v:4863$1404_Y end attribute \src "ls180.v:4868.10-4868.38" cell $eq $eq$ls180.v:4868$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \uart_phy_rx_bitcount connect \B 4'1001 connect \Y $eq$ls180.v:4868$1405_Y end attribute \src "ls180.v:5502.28-5502.31" cell $memrd $memrd$\mem$ls180.v:5502$1463 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" parameter \TRANSPARENT 0 parameter \WIDTH 32 connect \ADDR \memadr connect \CLK 1'x connect \DATA $memrd$\mem$ls180.v:5502$1463_DATA connect \EN 1'x end attribute \src "ls180.v:5522.20-5522.25" cell $memrd $memrd$\mem_1$ls180.v:5522$1489 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" parameter \TRANSPARENT 0 parameter \WIDTH 32 connect \ADDR \memadr_1 connect \CLK 1'x connect \DATA $memrd$\mem_1$ls180.v:5522$1489_DATA connect \EN 1'x end attribute \src "ls180.v:5533.12-5533.19" cell $memrd $memrd$\storage$ls180.v:5533$1497 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x connect \DATA $memrd$\storage$ls180.v:5533$1497_DATA connect \EN 1'x end attribute \src "ls180.v:5540.63-5540.70" cell $memrd $memrd$\storage$ls180.v:5540$1499 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x connect \DATA $memrd$\storage$ls180.v:5540$1499_DATA connect \EN 1'x end attribute \src "ls180.v:5547.14-5547.23" cell $memrd $memrd$\storage_1$ls180.v:5547$1507 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x connect \DATA $memrd$\storage_1$ls180.v:5547$1507_DATA connect \EN 1'x end attribute \src "ls180.v:5554.63-5554.72" cell $memrd $memrd$\storage_1$ls180.v:5554$1509 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x connect \DATA $memrd$\storage_1$ls180.v:5554$1509_DATA connect \EN 1'x end attribute \src "ls180.v:5561.14-5561.23" cell $memrd $memrd$\storage_2$ls180.v:5561$1517 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x connect \DATA $memrd$\storage_2$ls180.v:5561$1517_DATA connect \EN 1'x end attribute \src "ls180.v:5568.63-5568.72" cell $memrd $memrd$\storage_2$ls180.v:5568$1519 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x connect \DATA $memrd$\storage_2$ls180.v:5568$1519_DATA connect \EN 1'x end attribute \src "ls180.v:5575.14-5575.23" cell $memrd $memrd$\storage_3$ls180.v:5575$1527 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x connect \DATA $memrd$\storage_3$ls180.v:5575$1527_DATA connect \EN 1'x end attribute \src "ls180.v:5582.63-5582.72" cell $memrd $memrd$\storage_3$ls180.v:5582$1529 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" parameter \TRANSPARENT 0 parameter \WIDTH 25 connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x connect \DATA $memrd$\storage_3$ls180.v:5582$1529_DATA connect \EN 1'x end attribute \src "ls180.v:5590.14-5590.23" cell $memrd $memrd$\storage_4$ls180.v:5590$1537 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" parameter \TRANSPARENT 0 parameter \WIDTH 10 connect \ADDR \tx_fifo_wrport_adr connect \CLK 1'x connect \DATA $memrd$\storage_4$ls180.v:5590$1537_DATA connect \EN 1'x end attribute \src "ls180.v:5595.15-5595.24" cell $memrd $memrd$\storage_4$ls180.v:5595$1539 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" parameter \TRANSPARENT 0 parameter \WIDTH 10 connect \ADDR \tx_fifo_rdport_adr connect \CLK 1'x connect \DATA $memrd$\storage_4$ls180.v:5595$1539_DATA connect \EN 1'x end attribute \src "ls180.v:5607.14-5607.23" cell $memrd $memrd$\storage_5$ls180.v:5607$1547 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" parameter \TRANSPARENT 0 parameter \WIDTH 10 connect \ADDR \rx_fifo_wrport_adr connect \CLK 1'x connect \DATA $memrd$\storage_5$ls180.v:5607$1547_DATA connect \EN 1'x end attribute \src "ls180.v:5612.15-5612.24" cell $memrd $memrd$\storage_5$ls180.v:5612$1549 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" parameter \TRANSPARENT 0 parameter \WIDTH 10 connect \ADDR \rx_fifo_rdport_adr connect \CLK 1'x connect \DATA $memrd$\storage_5$ls180.v:5612$1549_DATA connect \EN 1'x end attribute \src "ls180.v:1702.36-1702.61" cell $ne $ne$ls180.v:1702$63 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_value connect \B 1'0 connect \Y $ne$ls180.v:1702$63_Y end attribute \src "ls180.v:1873.60-1873.89" cell $ne $ne$ls180.v:1873$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'0 connect \Y $ne$ls180.v:1873$90_Y end attribute \src "ls180.v:1934.8-1934.132" cell $ne $ne$ls180.v:1934$109 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] connect \Y $ne$ls180.v:1934$109_Y end attribute \src "ls180.v:1966.70-1966.123" cell $ne $ne$ls180.v:1966$116 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 connect \Y $ne$ls180.v:1966$116_Y end attribute \src "ls180.v:1967.70-1967.123" cell $ne $ne$ls180.v:1967$117 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 connect \Y $ne$ls180.v:1967$117_Y end attribute \src "ls180.v:2091.8-2091.132" cell $ne $ne$ls180.v:2091$139 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] connect \Y $ne$ls180.v:2091$139_Y end attribute \src "ls180.v:2123.70-2123.123" cell $ne $ne$ls180.v:2123$146 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 connect \Y $ne$ls180.v:2123$146_Y end attribute \src "ls180.v:2124.70-2124.123" cell $ne $ne$ls180.v:2124$147 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 connect \Y $ne$ls180.v:2124$147_Y end attribute \src "ls180.v:2248.8-2248.132" cell $ne $ne$ls180.v:2248$169 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] connect \Y $ne$ls180.v:2248$169_Y end attribute \src "ls180.v:2280.70-2280.123" cell $ne $ne$ls180.v:2280$176 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 connect \Y $ne$ls180.v:2280$176_Y end attribute \src "ls180.v:2281.70-2281.123" cell $ne $ne$ls180.v:2281$177 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 connect \Y $ne$ls180.v:2281$177_Y end attribute \src "ls180.v:2405.8-2405.132" cell $ne $ne$ls180.v:2405$199 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] connect \Y $ne$ls180.v:2405$199_Y end attribute \src "ls180.v:2437.70-2437.123" cell $ne $ne$ls180.v:2437$206 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 connect \Y $ne$ls180.v:2437$206_Y end attribute \src "ls180.v:2438.70-2438.123" cell $ne $ne$ls180.v:2438$207 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 connect \Y $ne$ls180.v:2438$207_Y end attribute \src "ls180.v:2930.37-2930.60" cell $ne $ne$ls180.v:2930$605 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \tx_fifo_level0 connect \B 5'10000 connect \Y $ne$ls180.v:2930$605_Y end attribute \src "ls180.v:2931.37-2931.59" cell $ne $ne$ls180.v:2931$606 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_level0 connect \B 1'0 connect \Y $ne$ls180.v:2931$606_Y end attribute \src "ls180.v:2960.37-2960.60" cell $ne $ne$ls180.v:2960$616 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \rx_fifo_level0 connect \B 5'10000 connect \Y $ne$ls180.v:2960$616_Y end attribute \src "ls180.v:2961.37-2961.59" cell $ne $ne$ls180.v:2961$617 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_level0 connect \B 1'0 connect \Y $ne$ls180.v:2961$617_Y end attribute \src "ls180.v:3056.99-3056.143" cell $ne $ne$ls180.v:3056$624 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresocsim_wishbone_sel connect \B 1'0 connect \Y $ne$ls180.v:3056$624_Y end attribute \src "ls180.v:4350.7-4350.47" cell $ne $ne$ls180.v:4350$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 connect \Y $ne$ls180.v:4350$1259_Y end attribute \src "ls180.v:4404.9-4404.38" cell $ne $ne$ls180.v:4404$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'0 connect \Y $ne$ls180.v:4404$1276_Y end attribute \src "ls180.v:4440.8-4440.39" cell $ne $ne$ls180.v:4440$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_counter connect \B 1'0 connect \Y $ne$ls180.v:4440$1283_Y end attribute \src "ls180.v:1510.40-1510.70" cell $not $not$ls180.v:1510$17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_ibus_cyc connect \Y $not$ls180.v:1510$17_Y end attribute \src "ls180.v:1549.56-1549.84" cell $not $not$ls180.v:1549$22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_skip connect \Y $not$ls180.v:1549$22_Y end attribute \src "ls180.v:1550.56-1550.84" cell $not $not$ls180.v:1550$23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter0_skip connect \Y $not$ls180.v:1550$23_Y end attribute \src "ls180.v:1570.40-1570.70" cell $not $not$ls180.v:1570$28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_dbus_cyc connect \Y $not$ls180.v:1570$28_Y end attribute \src "ls180.v:1609.56-1609.84" cell $not $not$ls180.v:1609$33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_skip connect \Y $not$ls180.v:1609$33_Y end attribute \src "ls180.v:1610.56-1610.84" cell $not $not$ls180.v:1610$34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter1_skip connect \Y $not$ls180.v:1610$34_Y end attribute \src "ls180.v:1630.40-1630.73" cell $not $not$ls180.v:1630$39 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_libresoc_jtag_wb_cyc connect \Y $not$ls180.v:1630$39_Y end attribute \src "ls180.v:1669.56-1669.84" cell $not $not$ls180.v:1669$44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_skip connect \Y $not$ls180.v:1669$44_Y end attribute \src "ls180.v:1670.56-1670.84" cell $not $not$ls180.v:1670$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_converter2_skip connect \Y $not$ls180.v:1670$45_Y end attribute \src "ls180.v:1822.29-1822.54" cell $not $not$ls180.v:1822$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [0] connect \Y $not$ls180.v:1822$82_Y end attribute \src "ls180.v:1823.26-1823.51" cell $not $not$ls180.v:1823$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [1] connect \Y $not$ls180.v:1823$83_Y end attribute \src "ls180.v:1824.27-1824.52" cell $not $not$ls180.v:1824$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [2] connect \Y $not$ls180.v:1824$84_Y end attribute \src "ls180.v:1825.27-1825.52" cell $not $not$ls180.v:1825$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_command_storage [3] connect \Y $not$ls180.v:1825$85_Y end attribute \src "ls180.v:1867.28-1867.46" cell $not $not$ls180.v:1867$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_timer_done0 connect \Y $not$ls180.v:1867$88_Y end attribute \src "ls180.v:1968.53-1968.96" cell $not $not$ls180.v:1968$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_source_valid connect \Y $not$ls180.v:1968$118_Y end attribute \src "ls180.v:2022.9-2022.40" cell $not $not$ls180.v:2022$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_refresh_req connect \Y $not$ls180.v:2022$123_Y end attribute \src "ls180.v:2125.53-2125.96" cell $not $not$ls180.v:2125$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_source_valid connect \Y $not$ls180.v:2125$148_Y end attribute \src "ls180.v:2179.9-2179.40" cell $not $not$ls180.v:2179$153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_refresh_req connect \Y $not$ls180.v:2179$153_Y end attribute \src "ls180.v:2282.53-2282.96" cell $not $not$ls180.v:2282$178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_source_valid connect \Y $not$ls180.v:2282$178_Y end attribute \src "ls180.v:2336.9-2336.40" cell $not $not$ls180.v:2336$183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_refresh_req connect \Y $not$ls180.v:2336$183_Y end attribute \src "ls180.v:2439.53-2439.96" cell $not $not$ls180.v:2439$208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_source_valid connect \Y $not$ls180.v:2439$208_Y end attribute \src "ls180.v:2493.9-2493.40" cell $not $not$ls180.v:2493$213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_refresh_req connect \Y $not$ls180.v:2493$213_Y end attribute \src "ls180.v:2535.129-2535.162" cell $not $not$ls180.v:2535$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas connect \Y $not$ls180.v:2535$216_Y end attribute \src "ls180.v:2535.168-2535.200" cell $not $not$ls180.v:2535$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we connect \Y $not$ls180.v:2535$218_Y end attribute \src "ls180.v:2536.129-2536.162" cell $not $not$ls180.v:2536$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas connect \Y $not$ls180.v:2536$222_Y end attribute \src "ls180.v:2536.168-2536.200" cell $not $not$ls180.v:2536$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we connect \Y $not$ls180.v:2536$224_Y end attribute \src "ls180.v:2552.38-2552.63" cell $not $not$ls180.v:2552$252 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \sdram_interface_wdata_we connect \Y $not$ls180.v:2552$252_Y end attribute \src "ls180.v:2555.180-2555.215" cell $not $not$ls180.v:2555$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_cas connect \Y $not$ls180.v:2555$255_Y end attribute \src "ls180.v:2555.221-2555.255" cell $not $not$ls180.v:2555$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_we connect \Y $not$ls180.v:2555$257_Y end attribute \src "ls180.v:2555.139-2555.257" cell $not $not$ls180.v:2555$259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2555$258_Y connect \Y $not$ls180.v:2555$259_Y end attribute \src "ls180.v:2556.180-2556.215" cell $not $not$ls180.v:2556$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_cas connect \Y $not$ls180.v:2556$268_Y end attribute \src "ls180.v:2556.221-2556.255" cell $not $not$ls180.v:2556$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_we connect \Y $not$ls180.v:2556$270_Y end attribute \src "ls180.v:2556.139-2556.257" cell $not $not$ls180.v:2556$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2556$271_Y connect \Y $not$ls180.v:2556$272_Y end attribute \src "ls180.v:2557.180-2557.215" cell $not $not$ls180.v:2557$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_cas connect \Y $not$ls180.v:2557$281_Y end attribute \src "ls180.v:2557.221-2557.255" cell $not $not$ls180.v:2557$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_we connect \Y $not$ls180.v:2557$283_Y end attribute \src "ls180.v:2557.139-2557.257" cell $not $not$ls180.v:2557$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2557$284_Y connect \Y $not$ls180.v:2557$285_Y end attribute \src "ls180.v:2558.180-2558.215" cell $not $not$ls180.v:2558$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_cas connect \Y $not$ls180.v:2558$294_Y end attribute \src "ls180.v:2558.221-2558.255" cell $not $not$ls180.v:2558$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_we connect \Y $not$ls180.v:2558$296_Y end attribute \src "ls180.v:2558.139-2558.257" cell $not $not$ls180.v:2558$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2558$297_Y connect \Y $not$ls180.v:2558$298_Y end attribute \src "ls180.v:2585.61-2585.88" cell $not $not$ls180.v:2585$309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_valid connect \Y $not$ls180.v:2585$309_Y end attribute \src "ls180.v:2588.180-2588.215" cell $not $not$ls180.v:2588$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_cas connect \Y $not$ls180.v:2588$313_Y end attribute \src "ls180.v:2588.221-2588.255" cell $not $not$ls180.v:2588$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_payload_we connect \Y $not$ls180.v:2588$315_Y end attribute \src "ls180.v:2588.139-2588.257" cell $not $not$ls180.v:2588$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2588$316_Y connect \Y $not$ls180.v:2588$317_Y end attribute \src "ls180.v:2589.180-2589.215" cell $not $not$ls180.v:2589$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_cas connect \Y $not$ls180.v:2589$326_Y end attribute \src "ls180.v:2589.221-2589.255" cell $not $not$ls180.v:2589$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_payload_we connect \Y $not$ls180.v:2589$328_Y end attribute \src "ls180.v:2589.139-2589.257" cell $not $not$ls180.v:2589$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2589$329_Y connect \Y $not$ls180.v:2589$330_Y end attribute \src "ls180.v:2590.180-2590.215" cell $not $not$ls180.v:2590$339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_cas connect \Y $not$ls180.v:2590$339_Y end attribute \src "ls180.v:2590.221-2590.255" cell $not $not$ls180.v:2590$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_payload_we connect \Y $not$ls180.v:2590$341_Y end attribute \src "ls180.v:2590.139-2590.257" cell $not $not$ls180.v:2590$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2590$342_Y connect \Y $not$ls180.v:2590$343_Y end attribute \src "ls180.v:2591.180-2591.215" cell $not $not$ls180.v:2591$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_cas connect \Y $not$ls180.v:2591$352_Y end attribute \src "ls180.v:2591.221-2591.255" cell $not $not$ls180.v:2591$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_payload_we connect \Y $not$ls180.v:2591$354_Y end attribute \src "ls180.v:2591.139-2591.257" cell $not $not$ls180.v:2591$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2591$355_Y connect \Y $not$ls180.v:2591$356_Y end attribute \src "ls180.v:2654.61-2654.88" cell $not $not$ls180.v:2654$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_valid connect \Y $not$ls180.v:2654$395_Y end attribute \src "ls180.v:2675.97-2675.130" cell $not $not$ls180.v:2675$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas connect \Y $not$ls180.v:2675$398_Y end attribute \src "ls180.v:2675.136-2675.168" cell $not $not$ls180.v:2675$400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we connect \Y $not$ls180.v:2675$400_Y end attribute \src "ls180.v:2675.58-2675.170" cell $not $not$ls180.v:2675$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2675$401_Y connect \Y $not$ls180.v:2675$402_Y end attribute \src "ls180.v:2683.11-2683.33" cell $not $not$ls180.v:2683$405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_write_available connect \Y $not$ls180.v:2683$405_Y end attribute \src "ls180.v:2713.97-2713.130" cell $not $not$ls180.v:2713$407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_cas connect \Y $not$ls180.v:2713$407_Y end attribute \src "ls180.v:2713.136-2713.168" cell $not $not$ls180.v:2713$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_we connect \Y $not$ls180.v:2713$409_Y end attribute \src "ls180.v:2713.58-2713.170" cell $not $not$ls180.v:2713$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2713$410_Y connect \Y $not$ls180.v:2713$411_Y end attribute \src "ls180.v:2721.11-2721.32" cell $not $not$ls180.v:2721$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_read_available connect \Y $not$ls180.v:2721$414_Y end attribute \src "ls180.v:2731.87-2731.336" cell $not $not$ls180.v:2731$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2731$425_Y connect \Y $not$ls180.v:2731$426_Y end attribute \src "ls180.v:2732.40-2732.68" cell $not $not$ls180.v:2732$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_valid connect \Y $not$ls180.v:2732$429_Y end attribute \src "ls180.v:2732.73-2732.100" cell $not $not$ls180.v:2732$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank0_lock connect \Y $not$ls180.v:2732$430_Y end attribute \src "ls180.v:2736.87-2736.336" cell $not $not$ls180.v:2736$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2736$441_Y connect \Y $not$ls180.v:2736$442_Y end attribute \src "ls180.v:2737.40-2737.68" cell $not $not$ls180.v:2737$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_valid connect \Y $not$ls180.v:2737$445_Y end attribute \src "ls180.v:2737.73-2737.100" cell $not $not$ls180.v:2737$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank1_lock connect \Y $not$ls180.v:2737$446_Y end attribute \src "ls180.v:2741.87-2741.336" cell $not $not$ls180.v:2741$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2741$457_Y connect \Y $not$ls180.v:2741$458_Y end attribute \src "ls180.v:2742.40-2742.68" cell $not $not$ls180.v:2742$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_valid connect \Y $not$ls180.v:2742$461_Y end attribute \src "ls180.v:2742.73-2742.100" cell $not $not$ls180.v:2742$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank2_lock connect \Y $not$ls180.v:2742$462_Y end attribute \src "ls180.v:2746.87-2746.336" cell $not $not$ls180.v:2746$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2746$473_Y connect \Y $not$ls180.v:2746$474_Y end attribute \src "ls180.v:2747.40-2747.68" cell $not $not$ls180.v:2747$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_valid connect \Y $not$ls180.v:2747$477_Y end attribute \src "ls180.v:2747.73-2747.100" cell $not $not$ls180.v:2747$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_interface_bank3_lock connect \Y $not$ls180.v:2747$478_Y end attribute \src "ls180.v:2751.123-2751.372" cell $not $not$ls180.v:2751$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$490_Y connect \Y $not$ls180.v:2751$491_Y end attribute \src "ls180.v:2751.497-2751.746" cell $not $not$ls180.v:2751$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$506_Y connect \Y $not$ls180.v:2751$507_Y end attribute \src "ls180.v:2751.871-2751.1120" cell $not $not$ls180.v:2751$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$522_Y connect \Y $not$ls180.v:2751$523_Y end attribute \src "ls180.v:2751.1245-2751.1494" cell $not $not$ls180.v:2751$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$538_Y connect \Y $not$ls180.v:2751$539_Y end attribute \src "ls180.v:2773.27-2773.40" cell $not $not$ls180.v:2773$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wb_sdram_cyc connect \Y $not$ls180.v:2773$545_Y end attribute \src "ls180.v:2812.25-2812.40" cell $not $not$ls180.v:2812$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \converter_skip connect \Y $not$ls180.v:2812$550_Y end attribute \src "ls180.v:2813.25-2813.40" cell $not $not$ls180.v:2813$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \converter_skip connect \Y $not$ls180.v:2813$551_Y end attribute \src "ls180.v:2838.22-2838.38" cell $not $not$ls180.v:2838$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_cyc connect \Y $not$ls180.v:2838$557_Y end attribute \src "ls180.v:2839.25-2839.40" cell $not $not$ls180.v:2839$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_we connect \Y $not$ls180.v:2839$558_Y end attribute \src "ls180.v:2840.65-2840.78" cell $not $not$ls180.v:2840$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cmd_consumed connect \Y $not$ls180.v:2840$560_Y end attribute \src "ls180.v:2841.87-2841.102" cell $not $not$ls180.v:2841$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wdata_consumed connect \Y $not$ls180.v:2841$564_Y end attribute \src "ls180.v:2842.63-2842.83" cell $not $not$ls180.v:2842$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_payload_we connect \Y $not$ls180.v:2842$567_Y end attribute \src "ls180.v:2843.71-2843.86" cell $not $not$ls180.v:2843$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_we connect \Y $not$ls180.v:2843$570_Y end attribute \src "ls180.v:2859.25-2859.44" cell $not $not$ls180.v:2859$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_sink_ready connect \Y $not$ls180.v:2859$579_Y end attribute \src "ls180.v:2860.26-2860.47" cell $not $not$ls180.v:2860$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_source_valid connect \Y $not$ls180.v:2860$580_Y end attribute \src "ls180.v:2866.22-2866.41" cell $not $not$ls180.v:2866$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_sink_ready connect \Y $not$ls180.v:2866$581_Y end attribute \src "ls180.v:2872.26-2872.47" cell $not $not$ls180.v:2872$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_source_valid connect \Y $not$ls180.v:2872$582_Y end attribute \src "ls180.v:2873.25-2873.44" cell $not $not$ls180.v:2873$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_sink_ready connect \Y $not$ls180.v:2873$583_Y end attribute \src "ls180.v:2876.22-2876.43" cell $not $not$ls180.v:2876$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_source_valid connect \Y $not$ls180.v:2876$586_Y end attribute \src "ls180.v:2914.61-2914.78" cell $not $not$ls180.v:2914$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_readable connect \Y $not$ls180.v:2914$596_Y end attribute \src "ls180.v:2944.61-2944.78" cell $not $not$ls180.v:2944$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_readable connect \Y $not$ls180.v:2944$607_Y end attribute \src "ls180.v:3139.81-3139.104" cell $not $not$ls180.v:3139$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_shared_ack connect \Y $not$ls180.v:3139$657_Y end attribute \src "ls180.v:3156.71-3156.106" cell $not $not$ls180.v:3156$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3156$681_Y end attribute \src "ls180.v:3159.73-3159.108" cell $not $not$ls180.v:3159$688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3159$688_Y end attribute \src "ls180.v:3162.73-3162.108" cell $not $not$ls180.v:3162$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3162$695_Y end attribute \src "ls180.v:3165.73-3165.108" cell $not $not$ls180.v:3165$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3165$702_Y end attribute \src "ls180.v:3168.73-3168.108" cell $not $not$ls180.v:3168$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3168$709_Y end attribute \src "ls180.v:3171.76-3171.111" cell $not $not$ls180.v:3171$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3171$716_Y end attribute \src "ls180.v:3174.76-3174.111" cell $not $not$ls180.v:3174$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3174$723_Y end attribute \src "ls180.v:3177.76-3177.111" cell $not $not$ls180.v:3177$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3177$730_Y end attribute \src "ls180.v:3180.76-3180.111" cell $not $not$ls180.v:3180$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_bank_bus_we connect \Y $not$ls180.v:3180$737_Y end attribute \src "ls180.v:3194.68-3194.103" cell $not $not$ls180.v:3194$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_we connect \Y $not$ls180.v:3194$745_Y end attribute \src "ls180.v:3197.67-3197.102" cell $not $not$ls180.v:3197$752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_we connect \Y $not$ls180.v:3197$752_Y end attribute \src "ls180.v:3200.69-3200.104" cell $not $not$ls180.v:3200$759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_bank_bus_we connect \Y $not$ls180.v:3200$759_Y end attribute \src "ls180.v:3208.68-3208.103" cell $not $not$ls180.v:3208$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_we connect \Y $not$ls180.v:3208$767_Y end attribute \src "ls180.v:3211.67-3211.102" cell $not $not$ls180.v:3211$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_we connect \Y $not$ls180.v:3211$774_Y end attribute \src "ls180.v:3214.69-3214.104" cell $not $not$ls180.v:3214$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_bank_bus_we connect \Y $not$ls180.v:3214$781_Y end attribute \src "ls180.v:3222.67-3222.102" cell $not $not$ls180.v:3222$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_we connect \Y $not$ls180.v:3222$789_Y end attribute \src "ls180.v:3225.66-3225.101" cell $not $not$ls180.v:3225$796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface3_bank_bus_we connect \Y $not$ls180.v:3225$796_Y end attribute \src "ls180.v:3236.78-3236.113" cell $not $not$ls180.v:3236$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3236$804_Y end attribute \src "ls180.v:3239.82-3239.117" cell $not $not$ls180.v:3239$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3239$811_Y end attribute \src "ls180.v:3242.63-3242.98" cell $not $not$ls180.v:3242$818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3242$818_Y end attribute \src "ls180.v:3245.82-3245.117" cell $not $not$ls180.v:3245$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3245$825_Y end attribute \src "ls180.v:3248.82-3248.117" cell $not $not$ls180.v:3248$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3248$832_Y end attribute \src "ls180.v:3251.83-3251.118" cell $not $not$ls180.v:3251$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3251$839_Y end attribute \src "ls180.v:3254.81-3254.116" cell $not $not$ls180.v:3254$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3254$846_Y end attribute \src "ls180.v:3257.81-3257.116" cell $not $not$ls180.v:3257$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3257$853_Y end attribute \src "ls180.v:3260.81-3260.116" cell $not $not$ls180.v:3260$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3260$860_Y end attribute \src "ls180.v:3263.81-3263.116" cell $not $not$ls180.v:3263$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface4_bank_bus_we connect \Y $not$ls180.v:3263$867_Y end attribute \src "ls180.v:3281.70-3281.105" cell $not $not$ls180.v:3281$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3281$875_Y end attribute \src "ls180.v:3284.70-3284.105" cell $not $not$ls180.v:3284$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3284$882_Y end attribute \src "ls180.v:3287.70-3287.105" cell $not $not$ls180.v:3287$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3287$889_Y end attribute \src "ls180.v:3290.70-3290.105" cell $not $not$ls180.v:3290$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3290$896_Y end attribute \src "ls180.v:3293.72-3293.107" cell $not $not$ls180.v:3293$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3293$903_Y end attribute \src "ls180.v:3296.72-3296.107" cell $not $not$ls180.v:3296$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3296$910_Y end attribute \src "ls180.v:3299.72-3299.107" cell $not $not$ls180.v:3299$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3299$917_Y end attribute \src "ls180.v:3302.72-3302.107" cell $not $not$ls180.v:3302$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3302$924_Y end attribute \src "ls180.v:3305.68-3305.103" cell $not $not$ls180.v:3305$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3305$931_Y end attribute \src "ls180.v:3308.78-3308.113" cell $not $not$ls180.v:3308$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3308$938_Y end attribute \src "ls180.v:3311.71-3311.106" cell $not $not$ls180.v:3311$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3311$945_Y end attribute \src "ls180.v:3314.71-3314.106" cell $not $not$ls180.v:3314$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3314$952_Y end attribute \src "ls180.v:3317.71-3317.106" cell $not $not$ls180.v:3317$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3317$959_Y end attribute \src "ls180.v:3320.71-3320.106" cell $not $not$ls180.v:3320$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3320$966_Y end attribute \src "ls180.v:3323.75-3323.110" cell $not $not$ls180.v:3323$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3323$973_Y end attribute \src "ls180.v:3326.76-3326.111" cell $not $not$ls180.v:3326$980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3326$980_Y end attribute \src "ls180.v:3329.75-3329.110" cell $not $not$ls180.v:3329$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface5_bank_bus_we connect \Y $not$ls180.v:3329$987_Y end attribute \src "ls180.v:3349.48-3349.83" cell $not $not$ls180.v:3349$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3349$995_Y end attribute \src "ls180.v:3352.71-3352.106" cell $not $not$ls180.v:3352$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3352$1002_Y end attribute \src "ls180.v:3355.72-3355.107" cell $not $not$ls180.v:3355$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3355$1009_Y end attribute \src "ls180.v:3358.63-3358.98" cell $not $not$ls180.v:3358$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3358$1016_Y end attribute \src "ls180.v:3361.64-3361.99" cell $not $not$ls180.v:3361$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3361$1023_Y end attribute \src "ls180.v:3364.75-3364.110" cell $not $not$ls180.v:3364$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3364$1030_Y end attribute \src "ls180.v:3367.72-3367.107" cell $not $not$ls180.v:3367$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3367$1037_Y end attribute \src "ls180.v:3370.71-3370.106" cell $not $not$ls180.v:3370$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface6_bank_bus_we connect \Y $not$ls180.v:3370$1044_Y end attribute \src "ls180.v:3383.77-3383.112" cell $not $not$ls180.v:3383$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we connect \Y $not$ls180.v:3383$1052_Y end attribute \src "ls180.v:3386.77-3386.112" cell $not $not$ls180.v:3386$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we connect \Y $not$ls180.v:3386$1059_Y end attribute \src "ls180.v:3389.77-3389.112" cell $not $not$ls180.v:3389$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we connect \Y $not$ls180.v:3389$1066_Y end attribute \src "ls180.v:3392.77-3392.112" cell $not $not$ls180.v:3392$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface7_bank_bus_we connect \Y $not$ls180.v:3392$1073_Y end attribute \src "ls180.v:3752.68-3752.317" cell $not $not$ls180.v:3752$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3752$1114_Y connect \Y $not$ls180.v:3752$1115_Y end attribute \src "ls180.v:3776.68-3776.317" cell $not $not$ls180.v:3776$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3776$1130_Y connect \Y $not$ls180.v:3776$1131_Y end attribute \src "ls180.v:3800.68-3800.317" cell $not $not$ls180.v:3800$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3800$1146_Y connect \Y $not$ls180.v:3800$1147_Y end attribute \src "ls180.v:3824.68-3824.317" cell $not $not$ls180.v:3824$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3824$1162_Y connect \Y $not$ls180.v:3824$1163_Y end attribute \src "ls180.v:4356.62-4356.86" cell $not $not$ls180.v:4356$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_ack connect \Y $not$ls180.v:4356$1262_Y end attribute \src "ls180.v:4375.8-4375.33" cell $not $not$ls180.v:4375$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_zero_trigger connect \Y $not$ls180.v:4375$1266_Y end attribute \src "ls180.v:4379.54-4379.74" cell $not $not$ls180.v:4379$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ram_bus_ram_bus_ack connect \Y $not$ls180.v:4379$1269_Y end attribute \src "ls180.v:4387.27-4387.45" cell $not $not$ls180.v:4387$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_timer_done0 connect \Y $not$ls180.v:4387$1271_Y end attribute \src "ls180.v:4457.126-4457.174" cell $not $not$ls180.v:4457$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4457$1286_Y end attribute \src "ls180.v:4463.126-4463.174" cell $not $not$ls180.v:4463$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4463$1291_Y end attribute \src "ls180.v:4464.8-4464.56" cell $not $not$ls180.v:4464$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_do_read connect \Y $not$ls180.v:4464$1293_Y end attribute \src "ls180.v:4472.8-4472.51" cell $not $not$ls180.v:4472$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_source_valid connect \Y $not$ls180.v:4472$1296_Y end attribute \src "ls180.v:4487.8-4487.41" cell $not $not$ls180.v:4487$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_twtpcon_ready connect \Y $not$ls180.v:4487$1298_Y end attribute \src "ls180.v:4503.126-4503.174" cell $not $not$ls180.v:4503$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4503$1302_Y end attribute \src "ls180.v:4509.126-4509.174" cell $not $not$ls180.v:4509$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4509$1307_Y end attribute \src "ls180.v:4510.8-4510.56" cell $not $not$ls180.v:4510$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_do_read connect \Y $not$ls180.v:4510$1309_Y end attribute \src "ls180.v:4518.8-4518.51" cell $not $not$ls180.v:4518$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_source_valid connect \Y $not$ls180.v:4518$1312_Y end attribute \src "ls180.v:4533.8-4533.41" cell $not $not$ls180.v:4533$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_twtpcon_ready connect \Y $not$ls180.v:4533$1314_Y end attribute \src "ls180.v:4549.126-4549.174" cell $not $not$ls180.v:4549$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4549$1318_Y end attribute \src "ls180.v:4555.126-4555.174" cell $not $not$ls180.v:4555$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4555$1323_Y end attribute \src "ls180.v:4556.8-4556.56" cell $not $not$ls180.v:4556$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_do_read connect \Y $not$ls180.v:4556$1325_Y end attribute \src "ls180.v:4564.8-4564.51" cell $not $not$ls180.v:4564$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_source_valid connect \Y $not$ls180.v:4564$1328_Y end attribute \src "ls180.v:4579.8-4579.41" cell $not $not$ls180.v:4579$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_twtpcon_ready connect \Y $not$ls180.v:4579$1330_Y end attribute \src "ls180.v:4595.126-4595.174" cell $not $not$ls180.v:4595$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4595$1334_Y end attribute \src "ls180.v:4601.126-4601.174" cell $not $not$ls180.v:4601$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace connect \Y $not$ls180.v:4601$1339_Y end attribute \src "ls180.v:4602.8-4602.56" cell $not $not$ls180.v:4602$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_do_read connect \Y $not$ls180.v:4602$1341_Y end attribute \src "ls180.v:4610.8-4610.51" cell $not $not$ls180.v:4610$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_source_valid connect \Y $not$ls180.v:4610$1344_Y end attribute \src "ls180.v:4625.8-4625.41" cell $not $not$ls180.v:4625$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_twtpcon_ready connect \Y $not$ls180.v:4625$1346_Y end attribute \src "ls180.v:4633.7-4633.17" cell $not $not$ls180.v:4633$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_en0 connect \Y $not$ls180.v:4633$1349_Y end attribute \src "ls180.v:4636.8-4636.24" cell $not $not$ls180.v:4636$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_max_time0 connect \Y $not$ls180.v:4636$1350_Y end attribute \src "ls180.v:4640.7-4640.17" cell $not $not$ls180.v:4640$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_en1 connect \Y $not$ls180.v:4640$1352_Y end attribute \src "ls180.v:4643.8-4643.24" cell $not $not$ls180.v:4643$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_max_time1 connect \Y $not$ls180.v:4643$1353_Y end attribute \src "ls180.v:4762.25-4762.38" cell $not $not$ls180.v:4762$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \array_muxed2 connect \Y $not$ls180.v:4762$1355_Y end attribute \src "ls180.v:4763.25-4763.38" cell $not $not$ls180.v:4763$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \array_muxed3 connect \Y $not$ls180.v:4763$1356_Y end attribute \src "ls180.v:4764.24-4764.37" cell $not $not$ls180.v:4764$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \array_muxed4 connect \Y $not$ls180.v:4764$1357_Y end attribute \src "ls180.v:4775.8-4775.28" cell $not $not$ls180.v:4775$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_tccdcon_ready connect \Y $not$ls180.v:4775$1358_Y end attribute \src "ls180.v:4790.8-4790.28" cell $not $not$ls180.v:4790$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_twtrcon_ready connect \Y $not$ls180.v:4790$1361_Y end attribute \src "ls180.v:4826.31-4826.48" cell $not $not$ls180.v:4826$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_tx_busy connect \Y $not$ls180.v:4826$1391_Y end attribute \src "ls180.v:4826.54-4826.74" cell $not $not$ls180.v:4826$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_sink_ready connect \Y $not$ls180.v:4826$1393_Y end attribute \src "ls180.v:4855.7-4855.24" cell $not $not$ls180.v:4855$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_rx_busy connect \Y $not$ls180.v:4855$1400_Y end attribute \src "ls180.v:4856.9-4856.21" cell $not $not$ls180.v:4856$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \uart_phy_rx connect \Y $not$ls180.v:4856$1401_Y end attribute \src "ls180.v:4889.8-4889.19" cell $not $not$ls180.v:4889$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_trigger connect \Y $not$ls180.v:4889$1407_Y end attribute \src "ls180.v:4896.8-4896.19" cell $not $not$ls180.v:4896$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_trigger connect \Y $not$ls180.v:4896$1409_Y end attribute \src "ls180.v:4906.60-4906.76" cell $not $not$ls180.v:4906$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_replace connect \Y $not$ls180.v:4906$1412_Y end attribute \src "ls180.v:4912.60-4912.76" cell $not $not$ls180.v:4912$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_replace connect \Y $not$ls180.v:4912$1417_Y end attribute \src "ls180.v:4913.8-4913.24" cell $not $not$ls180.v:4913$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_do_read connect \Y $not$ls180.v:4913$1419_Y end attribute \src "ls180.v:4928.60-4928.76" cell $not $not$ls180.v:4928$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_replace connect \Y $not$ls180.v:4928$1423_Y end attribute \src "ls180.v:4934.60-4934.76" cell $not $not$ls180.v:4934$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_replace connect \Y $not$ls180.v:4934$1428_Y end attribute \src "ls180.v:4935.8-4935.24" cell $not $not$ls180.v:4935$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_do_read connect \Y $not$ls180.v:4935$1430_Y end attribute \src "ls180.v:4969.9-4969.32" cell $not $not$ls180.v:4969$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_request [0] connect \Y $not$ls180.v:4969$1433_Y end attribute \src "ls180.v:4980.9-4980.32" cell $not $not$ls180.v:4980$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_request [1] connect \Y $not$ls180.v:4980$1434_Y end attribute \src "ls180.v:4991.9-4991.32" cell $not $not$ls180.v:4991$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_request [2] connect \Y $not$ls180.v:4991$1435_Y end attribute \src "ls180.v:5004.8-5004.25" cell $not $not$ls180.v:5004$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_done connect \Y $not$ls180.v:5004$1436_Y end attribute \src "ls180.v:1551.10-1551.86" cell $or $or$ls180.v:1551$24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_converted_interface_ack connect \B \libresocsim_converter0_skip connect \Y $or$ls180.v:1551$24_Y end attribute \src "ls180.v:1611.10-1611.86" cell $or $or$ls180.v:1611$35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_converted_interface_ack connect \B \libresocsim_converter1_skip connect \Y $or$ls180.v:1611$35_Y end attribute \src "ls180.v:1671.10-1671.86" cell $or $or$ls180.v:1671$46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_converted_interface_ack connect \B \libresocsim_converter2_skip connect \Y $or$ls180.v:1671$46_Y end attribute \src "ls180.v:1873.34-1873.90" cell $or $or$ls180.v:1873$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_start0 connect \B $ne$ls180.v:1873$90_Y connect \Y $or$ls180.v:1873$91_Y end attribute \src "ls180.v:1916.54-1916.125" cell $or $or$ls180.v:1916$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_req_wdata_ready connect \B \sdram_bankmachine0_req_rdata_valid connect \Y $or$ls180.v:1916$95_Y end attribute \src "ls180.v:1917.39-1917.136" cell $or $or$ls180.v:1917$96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine0_cmd_buffer_source_valid connect \Y $or$ls180.v:1917$96_Y end attribute \src "ls180.v:1925.40-1925.155" cell $or $or$ls180.v:1925$100 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 connect \A $sshl$ls180.v:1925$99_Y connect \B { 4'0000 \sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } connect \Y $or$ls180.v:1925$100_Y end attribute \src "ls180.v:1962.117-1962.225" cell $or $or$ls180.v:1962$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \sdram_bankmachine0_cmd_buffer_lookahead_replace connect \Y $or$ls180.v:1962$113_Y end attribute \src "ls180.v:1968.52-1968.142" cell $or $or$ls180.v:1968$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:1968$118_Y connect \B \sdram_bankmachine0_cmd_buffer_source_ready connect \Y $or$ls180.v:1968$119_Y end attribute \src "ls180.v:2073.54-2073.125" cell $or $or$ls180.v:2073$125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_req_wdata_ready connect \B \sdram_bankmachine1_req_rdata_valid connect \Y $or$ls180.v:2073$125_Y end attribute \src "ls180.v:2074.39-2074.136" cell $or $or$ls180.v:2074$126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine1_cmd_buffer_source_valid connect \Y $or$ls180.v:2074$126_Y end attribute \src "ls180.v:2082.40-2082.155" cell $or $or$ls180.v:2082$130 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 connect \A $sshl$ls180.v:2082$129_Y connect \B { 4'0000 \sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } connect \Y $or$ls180.v:2082$130_Y end attribute \src "ls180.v:2119.117-2119.225" cell $or $or$ls180.v:2119$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \sdram_bankmachine1_cmd_buffer_lookahead_replace connect \Y $or$ls180.v:2119$143_Y end attribute \src "ls180.v:2125.52-2125.142" cell $or $or$ls180.v:2125$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2125$148_Y connect \B \sdram_bankmachine1_cmd_buffer_source_ready connect \Y $or$ls180.v:2125$149_Y end attribute \src "ls180.v:2230.54-2230.125" cell $or $or$ls180.v:2230$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_req_wdata_ready connect \B \sdram_bankmachine2_req_rdata_valid connect \Y $or$ls180.v:2230$155_Y end attribute \src "ls180.v:2231.39-2231.136" cell $or $or$ls180.v:2231$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine2_cmd_buffer_source_valid connect \Y $or$ls180.v:2231$156_Y end attribute \src "ls180.v:2239.40-2239.155" cell $or $or$ls180.v:2239$160 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 connect \A $sshl$ls180.v:2239$159_Y connect \B { 4'0000 \sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } connect \Y $or$ls180.v:2239$160_Y end attribute \src "ls180.v:2276.117-2276.225" cell $or $or$ls180.v:2276$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \sdram_bankmachine2_cmd_buffer_lookahead_replace connect \Y $or$ls180.v:2276$173_Y end attribute \src "ls180.v:2282.52-2282.142" cell $or $or$ls180.v:2282$179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2282$178_Y connect \B \sdram_bankmachine2_cmd_buffer_source_ready connect \Y $or$ls180.v:2282$179_Y end attribute \src "ls180.v:2387.54-2387.125" cell $or $or$ls180.v:2387$185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_req_wdata_ready connect \B \sdram_bankmachine3_req_rdata_valid connect \Y $or$ls180.v:2387$185_Y end attribute \src "ls180.v:2388.39-2388.136" cell $or $or$ls180.v:2388$186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \sdram_bankmachine3_cmd_buffer_source_valid connect \Y $or$ls180.v:2388$186_Y end attribute \src "ls180.v:2396.40-2396.155" cell $or $or$ls180.v:2396$190 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 connect \A $sshl$ls180.v:2396$189_Y connect \B { 4'0000 \sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } connect \Y $or$ls180.v:2396$190_Y end attribute \src "ls180.v:2433.117-2433.225" cell $or $or$ls180.v:2433$203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \sdram_bankmachine3_cmd_buffer_lookahead_replace connect \Y $or$ls180.v:2433$203_Y end attribute \src "ls180.v:2439.52-2439.142" cell $or $or$ls180.v:2439$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2439$208_Y connect \B \sdram_bankmachine3_cmd_buffer_source_ready connect \Y $or$ls180.v:2439$209_Y end attribute \src "ls180.v:2538.92-2538.168" cell $or $or$ls180.v:2538$229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_payload_is_write connect \B \sdram_choose_req_cmd_payload_is_read connect \Y $or$ls180.v:2538$229_Y end attribute \src "ls180.v:2541.34-2541.179" cell $or $or$ls180.v:2541$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2541$233_Y connect \B $and$ls180.v:2541$234_Y connect \Y $or$ls180.v:2541$235_Y end attribute \src "ls180.v:2541.33-2541.254" cell $or $or$ls180.v:2541$237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2541$235_Y connect \B $and$ls180.v:2541$236_Y connect \Y $or$ls180.v:2541$237_Y end attribute \src "ls180.v:2541.32-2541.329" cell $or $or$ls180.v:2541$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2541$237_Y connect \B $and$ls180.v:2541$238_Y connect \Y $or$ls180.v:2541$239_Y end attribute \src "ls180.v:2542.35-2542.182" cell $or $or$ls180.v:2542$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2542$240_Y connect \B $and$ls180.v:2542$241_Y connect \Y $or$ls180.v:2542$242_Y end attribute \src "ls180.v:2542.34-2542.258" cell $or $or$ls180.v:2542$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2542$242_Y connect \B $and$ls180.v:2542$243_Y connect \Y $or$ls180.v:2542$244_Y end attribute \src "ls180.v:2542.33-2542.334" cell $or $or$ls180.v:2542$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2542$244_Y connect \B $and$ls180.v:2542$245_Y connect \Y $or$ls180.v:2542$246_Y end attribute \src "ls180.v:2555.138-2555.292" cell $or $or$ls180.v:2555$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2555$259_Y connect \B \sdram_choose_cmd_want_activates connect \Y $or$ls180.v:2555$260_Y end attribute \src "ls180.v:2555.65-2555.446" cell $or $or$ls180.v:2555$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2555$261_Y connect \B $and$ls180.v:2555$264_Y connect \Y $or$ls180.v:2555$265_Y end attribute \src "ls180.v:2556.138-2556.292" cell $or $or$ls180.v:2556$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2556$272_Y connect \B \sdram_choose_cmd_want_activates connect \Y $or$ls180.v:2556$273_Y end attribute \src "ls180.v:2556.65-2556.446" cell $or $or$ls180.v:2556$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2556$274_Y connect \B $and$ls180.v:2556$277_Y connect \Y $or$ls180.v:2556$278_Y end attribute \src "ls180.v:2557.138-2557.292" cell $or $or$ls180.v:2557$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2557$285_Y connect \B \sdram_choose_cmd_want_activates connect \Y $or$ls180.v:2557$286_Y end attribute \src "ls180.v:2557.65-2557.446" cell $or $or$ls180.v:2557$291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2557$287_Y connect \B $and$ls180.v:2557$290_Y connect \Y $or$ls180.v:2557$291_Y end attribute \src "ls180.v:2558.138-2558.292" cell $or $or$ls180.v:2558$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2558$298_Y connect \B \sdram_choose_cmd_want_activates connect \Y $or$ls180.v:2558$299_Y end attribute \src "ls180.v:2558.65-2558.446" cell $or $or$ls180.v:2558$304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2558$300_Y connect \B $and$ls180.v:2558$303_Y connect \Y $or$ls180.v:2558$304_Y end attribute \src "ls180.v:2585.31-2585.89" cell $or $or$ls180.v:2585$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_cmd_cmd_ready connect \B $not$ls180.v:2585$309_Y connect \Y $or$ls180.v:2585$310_Y end attribute \src "ls180.v:2588.138-2588.292" cell $or $or$ls180.v:2588$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2588$317_Y connect \B \sdram_choose_req_want_activates connect \Y $or$ls180.v:2588$318_Y end attribute \src "ls180.v:2588.65-2588.446" cell $or $or$ls180.v:2588$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2588$319_Y connect \B $and$ls180.v:2588$322_Y connect \Y $or$ls180.v:2588$323_Y end attribute \src "ls180.v:2589.138-2589.292" cell $or $or$ls180.v:2589$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2589$330_Y connect \B \sdram_choose_req_want_activates connect \Y $or$ls180.v:2589$331_Y end attribute \src "ls180.v:2589.65-2589.446" cell $or $or$ls180.v:2589$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2589$332_Y connect \B $and$ls180.v:2589$335_Y connect \Y $or$ls180.v:2589$336_Y end attribute \src "ls180.v:2590.138-2590.292" cell $or $or$ls180.v:2590$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2590$343_Y connect \B \sdram_choose_req_want_activates connect \Y $or$ls180.v:2590$344_Y end attribute \src "ls180.v:2590.65-2590.446" cell $or $or$ls180.v:2590$349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2590$345_Y connect \B $and$ls180.v:2590$348_Y connect \Y $or$ls180.v:2590$349_Y end attribute \src "ls180.v:2591.138-2591.292" cell $or $or$ls180.v:2591$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2591$356_Y connect \B \sdram_choose_req_want_activates connect \Y $or$ls180.v:2591$357_Y end attribute \src "ls180.v:2591.65-2591.446" cell $or $or$ls180.v:2591$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2591$358_Y connect \B $and$ls180.v:2591$361_Y connect \Y $or$ls180.v:2591$362_Y end attribute \src "ls180.v:2654.31-2654.89" cell $or $or$ls180.v:2654$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_choose_req_cmd_ready connect \B $not$ls180.v:2654$395_Y connect \Y $or$ls180.v:2654$396_Y end attribute \src "ls180.v:2675.57-2675.191" cell $or $or$ls180.v:2675$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2675$402_Y connect \B \sdram_ras_allowed connect \Y $or$ls180.v:2675$403_Y end attribute \src "ls180.v:2683.10-2683.52" cell $or $or$ls180.v:2683$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2683$405_Y connect \B \sdram_max_time1 connect \Y $or$ls180.v:2683$406_Y end attribute \src "ls180.v:2713.57-2713.191" cell $or $or$ls180.v:2713$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2713$411_Y connect \B \sdram_ras_allowed connect \Y $or$ls180.v:2713$412_Y end attribute \src "ls180.v:2721.10-2721.51" cell $or $or$ls180.v:2721$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2721$414_Y connect \B \sdram_max_time0 connect \Y $or$ls180.v:2721$415_Y end attribute \src "ls180.v:2731.91-2731.185" cell $or $or$ls180.v:2731$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked0 connect \B $and$ls180.v:2731$418_Y connect \Y $or$ls180.v:2731$419_Y end attribute \src "ls180.v:2731.90-2731.260" cell $or $or$ls180.v:2731$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2731$419_Y connect \B $and$ls180.v:2731$421_Y connect \Y $or$ls180.v:2731$422_Y end attribute \src "ls180.v:2731.89-2731.335" cell $or $or$ls180.v:2731$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2731$422_Y connect \B $and$ls180.v:2731$424_Y connect \Y $or$ls180.v:2731$425_Y end attribute \src "ls180.v:2736.91-2736.185" cell $or $or$ls180.v:2736$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked1 connect \B $and$ls180.v:2736$434_Y connect \Y $or$ls180.v:2736$435_Y end attribute \src "ls180.v:2736.90-2736.260" cell $or $or$ls180.v:2736$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2736$435_Y connect \B $and$ls180.v:2736$437_Y connect \Y $or$ls180.v:2736$438_Y end attribute \src "ls180.v:2736.89-2736.335" cell $or $or$ls180.v:2736$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2736$438_Y connect \B $and$ls180.v:2736$440_Y connect \Y $or$ls180.v:2736$441_Y end attribute \src "ls180.v:2741.91-2741.185" cell $or $or$ls180.v:2741$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked2 connect \B $and$ls180.v:2741$450_Y connect \Y $or$ls180.v:2741$451_Y end attribute \src "ls180.v:2741.90-2741.260" cell $or $or$ls180.v:2741$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2741$451_Y connect \B $and$ls180.v:2741$453_Y connect \Y $or$ls180.v:2741$454_Y end attribute \src "ls180.v:2741.89-2741.335" cell $or $or$ls180.v:2741$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2741$454_Y connect \B $and$ls180.v:2741$456_Y connect \Y $or$ls180.v:2741$457_Y end attribute \src "ls180.v:2746.91-2746.185" cell $or $or$ls180.v:2746$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked3 connect \B $and$ls180.v:2746$466_Y connect \Y $or$ls180.v:2746$467_Y end attribute \src "ls180.v:2746.90-2746.260" cell $or $or$ls180.v:2746$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2746$467_Y connect \B $and$ls180.v:2746$469_Y connect \Y $or$ls180.v:2746$470_Y end attribute \src "ls180.v:2746.89-2746.335" cell $or $or$ls180.v:2746$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2746$470_Y connect \B $and$ls180.v:2746$472_Y connect \Y $or$ls180.v:2746$473_Y end attribute \src "ls180.v:2751.127-2751.221" cell $or $or$ls180.v:2751$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked0 connect \B $and$ls180.v:2751$483_Y connect \Y $or$ls180.v:2751$484_Y end attribute \src "ls180.v:2751.126-2751.296" cell $or $or$ls180.v:2751$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$484_Y connect \B $and$ls180.v:2751$486_Y connect \Y $or$ls180.v:2751$487_Y end attribute \src "ls180.v:2751.125-2751.371" cell $or $or$ls180.v:2751$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$487_Y connect \B $and$ls180.v:2751$489_Y connect \Y $or$ls180.v:2751$490_Y end attribute \src "ls180.v:2751.29-2751.406" cell $or $or$ls180.v:2751$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 connect \B $and$ls180.v:2751$494_Y connect \Y $or$ls180.v:2751$495_Y end attribute \src "ls180.v:2751.501-2751.595" cell $or $or$ls180.v:2751$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked1 connect \B $and$ls180.v:2751$499_Y connect \Y $or$ls180.v:2751$500_Y end attribute \src "ls180.v:2751.500-2751.670" cell $or $or$ls180.v:2751$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$500_Y connect \B $and$ls180.v:2751$502_Y connect \Y $or$ls180.v:2751$503_Y end attribute \src "ls180.v:2751.499-2751.745" cell $or $or$ls180.v:2751$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$503_Y connect \B $and$ls180.v:2751$505_Y connect \Y $or$ls180.v:2751$506_Y end attribute \src "ls180.v:2751.28-2751.780" cell $or $or$ls180.v:2751$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$495_Y connect \B $and$ls180.v:2751$510_Y connect \Y $or$ls180.v:2751$511_Y end attribute \src "ls180.v:2751.875-2751.969" cell $or $or$ls180.v:2751$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked2 connect \B $and$ls180.v:2751$515_Y connect \Y $or$ls180.v:2751$516_Y end attribute \src "ls180.v:2751.874-2751.1044" cell $or $or$ls180.v:2751$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$516_Y connect \B $and$ls180.v:2751$518_Y connect \Y $or$ls180.v:2751$519_Y end attribute \src "ls180.v:2751.873-2751.1119" cell $or $or$ls180.v:2751$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$519_Y connect \B $and$ls180.v:2751$521_Y connect \Y $or$ls180.v:2751$522_Y end attribute \src "ls180.v:2751.27-2751.1154" cell $or $or$ls180.v:2751$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$511_Y connect \B $and$ls180.v:2751$526_Y connect \Y $or$ls180.v:2751$527_Y end attribute \src "ls180.v:2751.1249-2751.1343" cell $or $or$ls180.v:2751$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked3 connect \B $and$ls180.v:2751$531_Y connect \Y $or$ls180.v:2751$532_Y end attribute \src "ls180.v:2751.1248-2751.1418" cell $or $or$ls180.v:2751$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$532_Y connect \B $and$ls180.v:2751$534_Y connect \Y $or$ls180.v:2751$535_Y end attribute \src "ls180.v:2751.1247-2751.1493" cell $or $or$ls180.v:2751$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$535_Y connect \B $and$ls180.v:2751$537_Y connect \Y $or$ls180.v:2751$538_Y end attribute \src "ls180.v:2751.26-2751.1528" cell $or $or$ls180.v:2751$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:2751$527_Y connect \B $and$ls180.v:2751$542_Y connect \Y $or$ls180.v:2751$543_Y end attribute \src "ls180.v:2814.10-2814.42" cell $or $or$ls180.v:2814$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_ack connect \B \converter_skip connect \Y $or$ls180.v:2814$552_Y end attribute \src "ls180.v:2841.30-2841.59" cell $or $or$ls180.v:2841$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \cmd_consumed connect \Y $or$ls180.v:2841$562_Y end attribute \src "ls180.v:2842.29-2842.58" cell $or $or$ls180.v:2842$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \port_cmd_valid connect \B \cmd_consumed connect \Y $or$ls180.v:2842$566_Y end attribute \src "ls180.v:2843.38-2843.100" cell $or $or$ls180.v:2843$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2843$569_Y connect \B $and$ls180.v:2843$571_Y connect \Y $or$ls180.v:2843$572_Y end attribute \src "ls180.v:2844.19-2844.67" cell $or $or$ls180.v:2844$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2844$574_Y connect \B \cmd_consumed connect \Y $or$ls180.v:2844$575_Y end attribute \src "ls180.v:2845.21-2845.75" cell $or $or$ls180.v:2845$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2845$576_Y connect \B \wdata_consumed connect \Y $or$ls180.v:2845$577_Y end attribute \src "ls180.v:2875.32-2875.59" cell $or $or$ls180.v:2875$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_clear connect \B $and$ls180.v:2875$584_Y connect \Y $or$ls180.v:2875$585_Y end attribute \src "ls180.v:2899.15-2899.124" cell $or $or$ls180.v:2899$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$ls180.v:2899$593_Y connect \B $and$ls180.v:2899$594_Y connect \Y $or$ls180.v:2899$595_Y end attribute \src "ls180.v:2914.60-2914.92" cell $or $or$ls180.v:2914$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2914$596_Y connect \B \tx_fifo_re connect \Y $or$ls180.v:2914$597_Y end attribute \src "ls180.v:2925.52-2925.95" cell $or $or$ls180.v:2925$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \tx_fifo_syncfifo_writable connect \B \tx_fifo_replace connect \Y $or$ls180.v:2925$602_Y end attribute \src "ls180.v:2944.60-2944.92" cell $or $or$ls180.v:2944$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:2944$607_Y connect \B \rx_fifo_re connect \Y $or$ls180.v:2944$608_Y end attribute \src "ls180.v:2955.52-2955.95" cell $or $or$ls180.v:2955$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rx_fifo_syncfifo_writable connect \B \rx_fifo_replace connect \Y $or$ls180.v:2955$613_Y end attribute \src "ls180.v:3138.38-3138.83" cell $or $or$ls180.v:3138$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_err connect \B \ram_bus_ram_bus_err connect \Y $or$ls180.v:3138$651_Y end attribute \src "ls180.v:3138.37-3138.120" cell $or $or$ls180.v:3138$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3138$651_Y connect \B \libresocsim_libresoc_xics_icp_err connect \Y $or$ls180.v:3138$652_Y end attribute \src "ls180.v:3138.36-3138.157" cell $or $or$ls180.v:3138$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3138$652_Y connect \B \libresocsim_libresoc_xics_ics_err connect \Y $or$ls180.v:3138$653_Y end attribute \src "ls180.v:3138.35-3138.173" cell $or $or$ls180.v:3138$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3138$653_Y connect \B \wb_sdram_err connect \Y $or$ls180.v:3138$654_Y end attribute \src "ls180.v:3138.34-3138.213" cell $or $or$ls180.v:3138$655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3138$654_Y connect \B \libresocsim_libresocsim_wishbone_err connect \Y $or$ls180.v:3138$655_Y end attribute \src "ls180.v:3144.33-3144.78" cell $or $or$ls180.v:3144$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_ram_bus_ack connect \B \ram_bus_ram_bus_ack connect \Y $or$ls180.v:3144$660_Y end attribute \src "ls180.v:3144.32-3144.115" cell $or $or$ls180.v:3144$661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3144$660_Y connect \B \libresocsim_libresoc_xics_icp_ack connect \Y $or$ls180.v:3144$661_Y end attribute \src "ls180.v:3144.31-3144.152" cell $or $or$ls180.v:3144$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3144$661_Y connect \B \libresocsim_libresoc_xics_ics_ack connect \Y $or$ls180.v:3144$662_Y end attribute \src "ls180.v:3144.30-3144.168" cell $or $or$ls180.v:3144$663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3144$662_Y connect \B \wb_sdram_ack connect \Y $or$ls180.v:3144$663_Y end attribute \src "ls180.v:3144.29-3144.208" cell $or $or$ls180.v:3144$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3144$663_Y connect \B \libresocsim_libresocsim_wishbone_ack connect \Y $or$ls180.v:3144$664_Y end attribute \src "ls180.v:3145.35-3145.158" cell $or $or$ls180.v:3145$667 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A $and$ls180.v:3145$665_Y connect \B $and$ls180.v:3145$666_Y connect \Y $or$ls180.v:3145$667_Y end attribute \src "ls180.v:3145.34-3145.234" cell $or $or$ls180.v:3145$669 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A $or$ls180.v:3145$667_Y connect \B $and$ls180.v:3145$668_Y connect \Y $or$ls180.v:3145$669_Y end attribute \src "ls180.v:3145.33-3145.310" cell $or $or$ls180.v:3145$671 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A $or$ls180.v:3145$669_Y connect \B $and$ls180.v:3145$670_Y connect \Y $or$ls180.v:3145$671_Y end attribute \src "ls180.v:3145.32-3145.365" cell $or $or$ls180.v:3145$673 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A $or$ls180.v:3145$671_Y connect \B $and$ls180.v:3145$672_Y connect \Y $or$ls180.v:3145$673_Y end attribute \src "ls180.v:3145.31-3145.444" cell $or $or$ls180.v:3145$675 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A $or$ls180.v:3145$673_Y connect \B $and$ls180.v:3145$674_Y connect \Y $or$ls180.v:3145$675_Y end attribute \src "ls180.v:3425.52-3425.129" cell $or $or$ls180.v:3425$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A \libresocsim_interface0_bank_bus_dat_r connect \B \libresocsim_interface1_bank_bus_dat_r connect \Y $or$ls180.v:3425$1077_Y end attribute \src "ls180.v:3425.51-3425.170" cell $or $or$ls180.v:3425$1078 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A $or$ls180.v:3425$1077_Y connect \B \libresocsim_interface2_bank_bus_dat_r connect \Y $or$ls180.v:3425$1078_Y end attribute \src "ls180.v:3425.50-3425.211" cell $or $or$ls180.v:3425$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A $or$ls180.v:3425$1078_Y connect \B \libresocsim_interface3_bank_bus_dat_r connect \Y $or$ls180.v:3425$1079_Y end attribute \src "ls180.v:3425.49-3425.252" cell $or $or$ls180.v:3425$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A $or$ls180.v:3425$1079_Y connect \B \libresocsim_interface4_bank_bus_dat_r connect \Y $or$ls180.v:3425$1080_Y end attribute \src "ls180.v:3425.48-3425.293" cell $or $or$ls180.v:3425$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A $or$ls180.v:3425$1080_Y connect \B \libresocsim_interface5_bank_bus_dat_r connect \Y $or$ls180.v:3425$1081_Y end attribute \src "ls180.v:3425.47-3425.334" cell $or $or$ls180.v:3425$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A $or$ls180.v:3425$1081_Y connect \B \libresocsim_interface6_bank_bus_dat_r connect \Y $or$ls180.v:3425$1082_Y end attribute \src "ls180.v:3425.46-3425.375" cell $or $or$ls180.v:3425$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A $or$ls180.v:3425$1082_Y connect \B \libresocsim_interface7_bank_bus_dat_r connect \Y $or$ls180.v:3425$1083_Y end attribute \src "ls180.v:3752.72-3752.166" cell $or $or$ls180.v:3752$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked0 connect \B $and$ls180.v:3752$1107_Y connect \Y $or$ls180.v:3752$1108_Y end attribute \src "ls180.v:3752.71-3752.241" cell $or $or$ls180.v:3752$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3752$1108_Y connect \B $and$ls180.v:3752$1110_Y connect \Y $or$ls180.v:3752$1111_Y end attribute \src "ls180.v:3752.70-3752.316" cell $or $or$ls180.v:3752$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3752$1111_Y connect \B $and$ls180.v:3752$1113_Y connect \Y $or$ls180.v:3752$1114_Y end attribute \src "ls180.v:3776.72-3776.166" cell $or $or$ls180.v:3776$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked1 connect \B $and$ls180.v:3776$1123_Y connect \Y $or$ls180.v:3776$1124_Y end attribute \src "ls180.v:3776.71-3776.241" cell $or $or$ls180.v:3776$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3776$1124_Y connect \B $and$ls180.v:3776$1126_Y connect \Y $or$ls180.v:3776$1127_Y end attribute \src "ls180.v:3776.70-3776.316" cell $or $or$ls180.v:3776$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3776$1127_Y connect \B $and$ls180.v:3776$1129_Y connect \Y $or$ls180.v:3776$1130_Y end attribute \src "ls180.v:3800.72-3800.166" cell $or $or$ls180.v:3800$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked2 connect \B $and$ls180.v:3800$1139_Y connect \Y $or$ls180.v:3800$1140_Y end attribute \src "ls180.v:3800.71-3800.241" cell $or $or$ls180.v:3800$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3800$1140_Y connect \B $and$ls180.v:3800$1142_Y connect \Y $or$ls180.v:3800$1143_Y end attribute \src "ls180.v:3800.70-3800.316" cell $or $or$ls180.v:3800$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3800$1143_Y connect \B $and$ls180.v:3800$1145_Y connect \Y $or$ls180.v:3800$1146_Y end attribute \src "ls180.v:3824.72-3824.166" cell $or $or$ls180.v:3824$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \subfragments_locked3 connect \B $and$ls180.v:3824$1155_Y connect \Y $or$ls180.v:3824$1156_Y end attribute \src "ls180.v:3824.71-3824.241" cell $or $or$ls180.v:3824$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3824$1156_Y connect \B $and$ls180.v:3824$1158_Y connect \Y $or$ls180.v:3824$1159_Y end attribute \src "ls180.v:3824.70-3824.316" cell $or $or$ls180.v:3824$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:3824$1159_Y connect \B $and$ls180.v:3824$1161_Y connect \Y $or$ls180.v:3824$1162_Y end attribute \src "ls180.v:4277.15-4277.58" cell $or $or$ls180.v:4277$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [0] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4277$1216_Y end attribute \src "ls180.v:4278.15-4278.58" cell $or $or$ls180.v:4278$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [1] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4278$1217_Y end attribute \src "ls180.v:4279.15-4279.58" cell $or $or$ls180.v:4279$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [2] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4279$1218_Y end attribute \src "ls180.v:4280.15-4280.58" cell $or $or$ls180.v:4280$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [3] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4280$1219_Y end attribute \src "ls180.v:4281.15-4281.58" cell $or $or$ls180.v:4281$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [4] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4281$1220_Y end attribute \src "ls180.v:4282.15-4282.58" cell $or $or$ls180.v:4282$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [5] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4282$1221_Y end attribute \src "ls180.v:4283.15-4283.58" cell $or $or$ls180.v:4283$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [6] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4283$1222_Y end attribute \src "ls180.v:4284.15-4284.58" cell $or $or$ls180.v:4284$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [7] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4284$1223_Y end attribute \src "ls180.v:4285.15-4285.58" cell $or $or$ls180.v:4285$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [8] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4285$1224_Y end attribute \src "ls180.v:4286.15-4286.58" cell $or $or$ls180.v:4286$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [9] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4286$1225_Y end attribute \src "ls180.v:4287.16-4287.60" cell $or $or$ls180.v:4287$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [10] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4287$1226_Y end attribute \src "ls180.v:4288.16-4288.60" cell $or $or$ls180.v:4288$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [11] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4288$1227_Y end attribute \src "ls180.v:4289.16-4289.60" cell $or $or$ls180.v:4289$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [12] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4289$1228_Y end attribute \src "ls180.v:4290.16-4290.60" cell $or $or$ls180.v:4290$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [13] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4290$1229_Y end attribute \src "ls180.v:4291.16-4291.60" cell $or $or$ls180.v:4291$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [14] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4291$1230_Y end attribute \src "ls180.v:4292.16-4292.60" cell $or $or$ls180.v:4292$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [15] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4292$1231_Y end attribute \src "ls180.v:4293.16-4293.60" cell $or $or$ls180.v:4293$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [16] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4293$1232_Y end attribute \src "ls180.v:4294.16-4294.60" cell $or $or$ls180.v:4294$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [17] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4294$1233_Y end attribute \src "ls180.v:4295.16-4295.60" cell $or $or$ls180.v:4295$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [18] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4295$1234_Y end attribute \src "ls180.v:4296.16-4296.60" cell $or $or$ls180.v:4296$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [19] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4296$1235_Y end attribute \src "ls180.v:4297.16-4297.60" cell $or $or$ls180.v:4297$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [20] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4297$1236_Y end attribute \src "ls180.v:4298.16-4298.60" cell $or $or$ls180.v:4298$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [21] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4298$1237_Y end attribute \src "ls180.v:4299.16-4299.60" cell $or $or$ls180.v:4299$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [22] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4299$1238_Y end attribute \src "ls180.v:4300.16-4300.60" cell $or $or$ls180.v:4300$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [23] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4300$1239_Y end attribute \src "ls180.v:4301.16-4301.60" cell $or $or$ls180.v:4301$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [24] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4301$1240_Y end attribute \src "ls180.v:4302.16-4302.60" cell $or $or$ls180.v:4302$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [25] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4302$1241_Y end attribute \src "ls180.v:4303.16-4303.60" cell $or $or$ls180.v:4303$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [26] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4303$1242_Y end attribute \src "ls180.v:4304.16-4304.60" cell $or $or$ls180.v:4304$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [27] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4304$1243_Y end attribute \src "ls180.v:4305.16-4305.60" cell $or $or$ls180.v:4305$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [28] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4305$1244_Y end attribute \src "ls180.v:4306.16-4306.60" cell $or $or$ls180.v:4306$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [29] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4306$1245_Y end attribute \src "ls180.v:4307.16-4307.60" cell $or $or$ls180.v:4307$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [30] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4307$1246_Y end attribute \src "ls180.v:4308.16-4308.60" cell $or $or$ls180.v:4308$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [31] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4308$1247_Y end attribute \src "ls180.v:4309.16-4309.60" cell $or $or$ls180.v:4309$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [32] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4309$1248_Y end attribute \src "ls180.v:4310.16-4310.60" cell $or $or$ls180.v:4310$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [33] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4310$1249_Y end attribute \src "ls180.v:4311.16-4311.60" cell $or $or$ls180.v:4311$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [34] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4311$1250_Y end attribute \src "ls180.v:4312.16-4312.60" cell $or $or$ls180.v:4312$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [35] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4312$1251_Y end attribute \src "ls180.v:4313.16-4313.60" cell $or $or$ls180.v:4313$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [36] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4313$1252_Y end attribute \src "ls180.v:4314.16-4314.60" cell $or $or$ls180.v:4314$1253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [37] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4314$1253_Y end attribute \src "ls180.v:4315.16-4315.60" cell $or $or$ls180.v:4315$1254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [38] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4315$1254_Y end attribute \src "ls180.v:4316.16-4316.60" cell $or $or$ls180.v:4316$1255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nc_1 [39] connect \B \libresocsim_libresoc_interrupt [0] connect \Y $or$ls180.v:4316$1255_Y end attribute \src "ls180.v:4317.7-4317.83" cell $or $or$ls180.v:4317$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface0_converted_interface_ack connect \B \libresocsim_converter0_skip connect \Y $or$ls180.v:4317$1256_Y end attribute \src "ls180.v:4328.7-4328.83" cell $or $or$ls180.v:4328$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface1_converted_interface_ack connect \B \libresocsim_converter1_skip connect \Y $or$ls180.v:4328$1257_Y end attribute \src "ls180.v:4339.7-4339.83" cell $or $or$ls180.v:4339$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \libresocsim_interface2_converted_interface_ack connect \B \libresocsim_converter2_skip connect \Y $or$ls180.v:4339$1258_Y end attribute \src "ls180.v:4472.7-4472.97" cell $or $or$ls180.v:4472$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4472$1296_Y connect \B \sdram_bankmachine0_cmd_buffer_source_ready connect \Y $or$ls180.v:4472$1297_Y end attribute \src "ls180.v:4518.7-4518.97" cell $or $or$ls180.v:4518$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4518$1312_Y connect \B \sdram_bankmachine1_cmd_buffer_source_ready connect \Y $or$ls180.v:4518$1313_Y end attribute \src "ls180.v:4564.7-4564.97" cell $or $or$ls180.v:4564$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4564$1328_Y connect \B \sdram_bankmachine2_cmd_buffer_source_ready connect \Y $or$ls180.v:4564$1329_Y end attribute \src "ls180.v:4610.7-4610.97" cell $or $or$ls180.v:4610$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $not$ls180.v:4610$1344_Y connect \B \sdram_bankmachine3_cmd_buffer_source_ready connect \Y $or$ls180.v:4610$1345_Y end attribute \src "ls180.v:4798.45-4798.130" cell $or $or$ls180.v:4798$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 connect \B $and$ls180.v:4798$1365_Y connect \Y $or$ls180.v:4798$1366_Y end attribute \src "ls180.v:4798.44-4798.212" cell $or $or$ls180.v:4798$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:4798$1366_Y connect \B $and$ls180.v:4798$1368_Y connect \Y $or$ls180.v:4798$1369_Y end attribute \src "ls180.v:4798.43-4798.294" cell $or $or$ls180.v:4798$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:4798$1369_Y connect \B $and$ls180.v:4798$1371_Y connect \Y $or$ls180.v:4798$1372_Y end attribute \src "ls180.v:4798.42-4798.376" cell $or $or$ls180.v:4798$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:4798$1372_Y connect \B $and$ls180.v:4798$1374_Y connect \Y $or$ls180.v:4798$1375_Y end attribute \src "ls180.v:4799.46-4799.131" cell $or $or$ls180.v:4799$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 connect \B $and$ls180.v:4799$1377_Y connect \Y $or$ls180.v:4799$1378_Y end attribute \src "ls180.v:4799.45-4799.213" cell $or $or$ls180.v:4799$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:4799$1378_Y connect \B $and$ls180.v:4799$1380_Y connect \Y $or$ls180.v:4799$1381_Y end attribute \src "ls180.v:4799.44-4799.295" cell $or $or$ls180.v:4799$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:4799$1381_Y connect \B $and$ls180.v:4799$1383_Y connect \Y $or$ls180.v:4799$1384_Y end attribute \src "ls180.v:4799.43-4799.377" cell $or $or$ls180.v:4799$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $or$ls180.v:4799$1384_Y connect \B $and$ls180.v:4799$1386_Y connect \Y $or$ls180.v:4799$1387_Y end attribute \src "ls180.v:4803.7-4803.39" cell $or $or$ls180.v:4803$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \litedram_wb_ack connect \B \converter_skip connect \Y $or$ls180.v:4803$1388_Y end attribute \src "ls180.v:5711.8-5711.46" cell $or $or$ls180.v:5711$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \libresocsim_libresoc_reset connect \Y $or$ls180.v:5711$1550_Y end attribute \src "ls180.v:1925.41-1925.84" cell $sshl $sshl$ls180.v:1925$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine0_auto_precharge connect \B 4'1010 connect \Y $sshl$ls180.v:1925$99_Y end attribute \src "ls180.v:2082.41-2082.84" cell $sshl $sshl$ls180.v:2082$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine1_auto_precharge connect \B 4'1010 connect \Y $sshl$ls180.v:2082$129_Y end attribute \src "ls180.v:2239.41-2239.84" cell $sshl $sshl$ls180.v:2239$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine2_auto_precharge connect \B 4'1010 connect \Y $sshl$ls180.v:2239$159_Y end attribute \src "ls180.v:2396.41-2396.84" cell $sshl $sshl$ls180.v:2396$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 13 connect \A \sdram_bankmachine3_auto_precharge connect \B 4'1010 connect \Y $sshl$ls180.v:2396$189_Y end attribute \src "ls180.v:1956.58-1956.112" cell $sub $sub$ls180.v:1956$112 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $sub$ls180.v:1956$112_Y end attribute \src "ls180.v:2113.58-2113.112" cell $sub $sub$ls180.v:2113$142 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $sub$ls180.v:2113$142_Y end attribute \src "ls180.v:2270.58-2270.112" cell $sub $sub$ls180.v:2270$172 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $sub$ls180.v:2270$172_Y end attribute \src "ls180.v:2427.58-2427.112" cell $sub $sub$ls180.v:2427$202 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 connect \Y $sub$ls180.v:2427$202_Y end attribute \src "ls180.v:2833.33-2833.65" cell $sub $sub$ls180.v:2833$556 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 parameter \B_WIDTH 31 parameter \Y_WIDTH 31 connect \A \litedram_wb_adr connect \B 31'1001000000000000000000000000000 connect \Y $sub$ls180.v:2833$556_Y end attribute \src "ls180.v:2919.26-2919.48" cell $sub $sub$ls180.v:2919$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \tx_fifo_produce connect \B 1'1 connect \Y $sub$ls180.v:2919$601_Y end attribute \src "ls180.v:2949.26-2949.48" cell $sub $sub$ls180.v:2949$612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \rx_fifo_produce connect \B 1'1 connect \Y $sub$ls180.v:2949$612_Y end attribute \src "ls180.v:4363.26-4363.50" cell $sub $sub$ls180.v:4363$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 32 connect \A \libresocsim_value connect \B 1'1 connect \Y $sub$ls180.v:4363$1265_Y end attribute \src "ls180.v:4388.26-4388.51" cell $sub $sub$ls180.v:4388$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 connect \A \sdram_timer_count1 connect \B 1'1 connect \Y $sub$ls180.v:4388$1273_Y end attribute \src "ls180.v:4394.29-4394.57" cell $sub $sub$ls180.v:4394$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_postponer_count connect \B 1'1 connect \Y $sub$ls180.v:4394$1274_Y end attribute \src "ls180.v:4405.31-4405.59" cell $sub $sub$ls180.v:4405$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_sequencer_count connect \B 1'1 connect \Y $sub$ls180.v:4405$1277_Y end attribute \src "ls180.v:4469.54-4469.106" cell $sub $sub$ls180.v:4469$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $sub$ls180.v:4469$1295_Y end attribute \src "ls180.v:4488.41-4488.80" cell $sub $sub$ls180.v:4488$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine0_twtpcon_count connect \B 1'1 connect \Y $sub$ls180.v:4488$1299_Y end attribute \src "ls180.v:4515.54-4515.106" cell $sub $sub$ls180.v:4515$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $sub$ls180.v:4515$1311_Y end attribute \src "ls180.v:4534.41-4534.80" cell $sub $sub$ls180.v:4534$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine1_twtpcon_count connect \B 1'1 connect \Y $sub$ls180.v:4534$1315_Y end attribute \src "ls180.v:4561.54-4561.106" cell $sub $sub$ls180.v:4561$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $sub$ls180.v:4561$1327_Y end attribute \src "ls180.v:4580.41-4580.80" cell $sub $sub$ls180.v:4580$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine2_twtpcon_count connect \B 1'1 connect \Y $sub$ls180.v:4580$1331_Y end attribute \src "ls180.v:4607.54-4607.106" cell $sub $sub$ls180.v:4607$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 connect \Y $sub$ls180.v:4607$1343_Y end attribute \src "ls180.v:4626.41-4626.80" cell $sub $sub$ls180.v:4626$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_bankmachine3_twtpcon_count connect \B 1'1 connect \Y $sub$ls180.v:4626$1347_Y end attribute \src "ls180.v:4637.20-4637.38" cell $sub $sub$ls180.v:4637$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \sdram_time0 connect \B 1'1 connect \Y $sub$ls180.v:4637$1351_Y end attribute \src "ls180.v:4644.20-4644.38" cell $sub $sub$ls180.v:4644$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 connect \A \sdram_time1 connect \B 1'1 connect \Y $sub$ls180.v:4644$1354_Y end attribute \src "ls180.v:4776.28-4776.54" cell $sub $sub$ls180.v:4776$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sdram_tccdcon_count connect \B 1'1 connect \Y $sub$ls180.v:4776$1359_Y end attribute \src "ls180.v:4791.28-4791.54" cell $sub $sub$ls180.v:4791$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \sdram_twtrcon_count connect \B 1'1 connect \Y $sub$ls180.v:4791$1362_Y end attribute \src "ls180.v:4918.23-4918.44" cell $sub $sub$ls180.v:4918$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \tx_fifo_level0 connect \B 1'1 connect \Y $sub$ls180.v:4918$1421_Y end attribute \src "ls180.v:4940.23-4940.44" cell $sub $sub$ls180.v:4940$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 connect \A \rx_fifo_level0 connect \B 1'1 connect \Y $sub$ls180.v:4940$1432_Y end attribute \src "ls180.v:5005.26-5005.50" cell $sub $sub$ls180.v:5005$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 20 connect \A \libresocsim_count connect \B 1'1 connect \Y $sub$ls180.v:5005$1437_Y end attribute \module_not_derived 1 attribute \src "ls180.v:5618.13-5941.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \libresocsim_libresoc_jtag_tdi connect \TAP_bus__tdo \libresocsim_libresoc_jtag_tdo connect \TAP_bus__tms \libresocsim_libresoc_jtag_tms connect \busy_o \libresocsim_libresoc0 connect \clk \sys_clk_1 connect \core_bigendian_i 1'0 connect \dbus__ack \libresocsim_libresoc_dbus_ack connect \dbus__adr \libresocsim_libresoc_dbus_adr connect \dbus__bte 1'0 connect \dbus__cti 1'0 connect \dbus__cyc \libresocsim_libresoc_dbus_cyc connect \dbus__dat_r \libresocsim_libresoc_dbus_dat_r connect \dbus__dat_w \libresocsim_libresoc_dbus_dat_w connect \dbus__err \libresocsim_libresoc_dbus_err connect \dbus__sel \libresocsim_libresoc_dbus_sel connect \dbus__stb \libresocsim_libresoc_dbus_stb connect \dbus__we \libresocsim_libresoc_dbus_we connect \eint_0__core__i \libresocsim_libresoc_constraintmanager_eint_0 connect \eint_0__pad__i \eint_0 connect \eint_1__core__i \libresocsim_libresoc_constraintmanager_eint_1 connect \eint_1__pad__i \eint_1 connect \eint_2__core__i \libresocsim_libresoc_constraintmanager_eint_2 connect \eint_2__pad__i \eint_2 connect \gpio_e10__core__i \libresocsim_libresoc_constraintmanager_gpio_i [10] connect \gpio_e10__core__o \libresocsim_libresoc_constraintmanager_gpio_o [10] connect \gpio_e10__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [10] connect \gpio_e10__pad__i \gpio_i [10] connect \gpio_e10__pad__o \gpio_o [10] connect \gpio_e10__pad__oe \gpio_oe [10] connect \gpio_e11__core__i \libresocsim_libresoc_constraintmanager_gpio_i [11] connect \gpio_e11__core__o \libresocsim_libresoc_constraintmanager_gpio_o [11] connect \gpio_e11__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [11] connect \gpio_e11__pad__i \gpio_i [11] connect \gpio_e11__pad__o \gpio_o [11] connect \gpio_e11__pad__oe \gpio_oe [11] connect \gpio_e12__core__i \libresocsim_libresoc_constraintmanager_gpio_i [12] connect \gpio_e12__core__o \libresocsim_libresoc_constraintmanager_gpio_o [12] connect \gpio_e12__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [12] connect \gpio_e12__pad__i \gpio_i [12] connect \gpio_e12__pad__o \gpio_o [12] connect \gpio_e12__pad__oe \gpio_oe [12] connect \gpio_e13__core__i \libresocsim_libresoc_constraintmanager_gpio_i [13] connect \gpio_e13__core__o \libresocsim_libresoc_constraintmanager_gpio_o [13] connect \gpio_e13__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [13] connect \gpio_e13__pad__i \gpio_i [13] connect \gpio_e13__pad__o \gpio_o [13] connect \gpio_e13__pad__oe \gpio_oe [13] connect \gpio_e14__core__i \libresocsim_libresoc_constraintmanager_gpio_i [14] connect \gpio_e14__core__o \libresocsim_libresoc_constraintmanager_gpio_o [14] connect \gpio_e14__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [14] connect \gpio_e14__pad__i \gpio_i [14] connect \gpio_e14__pad__o \gpio_o [14] connect \gpio_e14__pad__oe \gpio_oe [14] connect \gpio_e15__core__i \libresocsim_libresoc_constraintmanager_gpio_i [15] connect \gpio_e15__core__o \libresocsim_libresoc_constraintmanager_gpio_o [15] connect \gpio_e15__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [15] connect \gpio_e15__pad__i \gpio_i [15] connect \gpio_e15__pad__o \gpio_o [15] connect \gpio_e15__pad__oe \gpio_oe [15] connect \gpio_e8__core__i \libresocsim_libresoc_constraintmanager_gpio_i [8] connect \gpio_e8__core__o \libresocsim_libresoc_constraintmanager_gpio_o [8] connect \gpio_e8__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [8] connect \gpio_e8__pad__i \gpio_i [8] connect \gpio_e8__pad__o \gpio_o [8] connect \gpio_e8__pad__oe \gpio_oe [8] connect \gpio_e9__core__i \libresocsim_libresoc_constraintmanager_gpio_i [9] connect \gpio_e9__core__o \libresocsim_libresoc_constraintmanager_gpio_o [9] connect \gpio_e9__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [9] connect \gpio_e9__pad__i \gpio_i [9] connect \gpio_e9__pad__o \gpio_o [9] connect \gpio_e9__pad__oe \gpio_oe [9] connect \gpio_s0__core__i \libresocsim_libresoc_constraintmanager_gpio_i [0] connect \gpio_s0__core__o \libresocsim_libresoc_constraintmanager_gpio_o [0] connect \gpio_s0__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [0] connect \gpio_s0__pad__i \gpio_i [0] connect \gpio_s0__pad__o \gpio_o [0] connect \gpio_s0__pad__oe \gpio_oe [0] connect \gpio_s1__core__i \libresocsim_libresoc_constraintmanager_gpio_i [1] connect \gpio_s1__core__o \libresocsim_libresoc_constraintmanager_gpio_o [1] connect \gpio_s1__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [1] connect \gpio_s1__pad__i \gpio_i [1] connect \gpio_s1__pad__o \gpio_o [1] connect \gpio_s1__pad__oe \gpio_oe [1] connect \gpio_s2__core__i \libresocsim_libresoc_constraintmanager_gpio_i [2] connect \gpio_s2__core__o \libresocsim_libresoc_constraintmanager_gpio_o [2] connect \gpio_s2__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [2] connect \gpio_s2__pad__i \gpio_i [2] connect \gpio_s2__pad__o \gpio_o [2] connect \gpio_s2__pad__oe \gpio_oe [2] connect \gpio_s3__core__i \libresocsim_libresoc_constraintmanager_gpio_i [3] connect \gpio_s3__core__o \libresocsim_libresoc_constraintmanager_gpio_o [3] connect \gpio_s3__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [3] connect \gpio_s3__pad__i \gpio_i [3] connect \gpio_s3__pad__o \gpio_o [3] connect \gpio_s3__pad__oe \gpio_oe [3] connect \gpio_s4__core__i \libresocsim_libresoc_constraintmanager_gpio_i [4] connect \gpio_s4__core__o \libresocsim_libresoc_constraintmanager_gpio_o [4] connect \gpio_s4__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [4] connect \gpio_s4__pad__i \gpio_i [4] connect \gpio_s4__pad__o \gpio_o [4] connect \gpio_s4__pad__oe \gpio_oe [4] connect \gpio_s5__core__i \libresocsim_libresoc_constraintmanager_gpio_i [5] connect \gpio_s5__core__o \libresocsim_libresoc_constraintmanager_gpio_o [5] connect \gpio_s5__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [5] connect \gpio_s5__pad__i \gpio_i [5] connect \gpio_s5__pad__o \gpio_o [5] connect \gpio_s5__pad__oe \gpio_oe [5] connect \gpio_s6__core__i \libresocsim_libresoc_constraintmanager_gpio_i [6] connect \gpio_s6__core__o \libresocsim_libresoc_constraintmanager_gpio_o [6] connect \gpio_s6__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [6] connect \gpio_s6__pad__i \gpio_i [6] connect \gpio_s6__pad__o \gpio_o [6] connect \gpio_s6__pad__oe \gpio_oe [6] connect \gpio_s7__core__i \libresocsim_libresoc_constraintmanager_gpio_i [7] connect \gpio_s7__core__o \libresocsim_libresoc_constraintmanager_gpio_o [7] connect \gpio_s7__core__oe \libresocsim_libresoc_constraintmanager_gpio_oe [7] connect \gpio_s7__pad__i \gpio_i [7] connect \gpio_s7__pad__o \gpio_o [7] connect \gpio_s7__pad__oe \gpio_oe [7] connect \ibus__ack \libresocsim_libresoc_ibus_ack connect \ibus__adr \libresocsim_libresoc_ibus_adr connect \ibus__bte 1'0 connect \ibus__cti 1'0 connect \ibus__cyc \libresocsim_libresoc_ibus_cyc connect \ibus__dat_r \libresocsim_libresoc_ibus_dat_r connect \ibus__dat_w \libresocsim_libresoc_ibus_dat_w connect \ibus__err \libresocsim_libresoc_ibus_err connect \ibus__sel \libresocsim_libresoc_ibus_sel connect \ibus__stb \libresocsim_libresoc_ibus_stb connect \ibus__we \libresocsim_libresoc_ibus_we connect \icp_wb__ack \libresocsim_libresoc_xics_icp_ack connect \icp_wb__adr \libresocsim_libresoc_xics_icp_adr connect \icp_wb__cyc \libresocsim_libresoc_xics_icp_cyc connect \icp_wb__dat_r \libresocsim_libresoc_xics_icp_dat_r connect \icp_wb__dat_w \libresocsim_libresoc_xics_icp_dat_w connect \icp_wb__err \libresocsim_libresoc_xics_icp_err connect \icp_wb__sel \libresocsim_libresoc_xics_icp_sel connect \icp_wb__stb \libresocsim_libresoc_xics_icp_stb connect \icp_wb__we \libresocsim_libresoc_xics_icp_we connect \ics_wb__ack \libresocsim_libresoc_xics_ics_ack connect \ics_wb__adr \libresocsim_libresoc_xics_ics_adr connect \ics_wb__cyc \libresocsim_libresoc_xics_ics_cyc connect \ics_wb__dat_r \libresocsim_libresoc_xics_ics_dat_r connect \ics_wb__dat_w \libresocsim_libresoc_xics_ics_dat_w connect \ics_wb__err \libresocsim_libresoc_xics_ics_err connect \ics_wb__sel \libresocsim_libresoc_xics_ics_sel connect \ics_wb__stb \libresocsim_libresoc_xics_ics_stb connect \ics_wb__we \libresocsim_libresoc_xics_ics_we connect \int_level_i \libresocsim_libresoc_interrupt connect \jtag_wb__ack \libresocsim_libresoc_jtag_wb_ack connect \jtag_wb__adr \libresocsim_libresoc_jtag_wb_adr connect \jtag_wb__cyc \libresocsim_libresoc_jtag_wb_cyc connect \jtag_wb__dat_r \libresocsim_libresoc_jtag_wb_dat_r connect \jtag_wb__dat_w \libresocsim_libresoc_jtag_wb_dat_w connect \jtag_wb__err \libresocsim_libresoc_jtag_wb_err connect \jtag_wb__sel \libresocsim_libresoc_jtag_wb_sel connect \jtag_wb__stb \libresocsim_libresoc_jtag_wb_stb connect \jtag_wb__we \libresocsim_libresoc_jtag_wb_we connect \memerr_o \libresocsim_libresoc1 connect \mspi0_clk__core__o \libresocsim_libresoc_constraintmanager_spimaster_clk connect \mspi0_clk__pad__o \spimaster_clk connect \mspi0_cs_n__core__o \libresocsim_libresoc_constraintmanager_spimaster_cs_n connect \mspi0_cs_n__pad__o \spimaster_cs_n connect \mspi0_miso__core__i \libresocsim_libresoc_constraintmanager_spimaster_miso connect \mspi0_miso__pad__i \spimaster_miso connect \mspi0_mosi__core__o \libresocsim_libresoc_constraintmanager_spimaster_mosi connect \mspi0_mosi__pad__o \spimaster_mosi connect \mtwi_scl__core__o \libresocsim_libresoc_constraintmanager_i2c_scl connect \mtwi_scl__pad__o \i2c_scl connect \mtwi_sda__core__i \libresocsim_libresoc_constraintmanager_i2c_sda_i connect \mtwi_sda__core__o \libresocsim_libresoc_constraintmanager_i2c_sda_o connect \mtwi_sda__core__oe \libresocsim_libresoc_constraintmanager_i2c_sda_oe connect \mtwi_sda__pad__i \i2c_sda_i connect \mtwi_sda__pad__o \i2c_sda_o connect \mtwi_sda__pad__oe \i2c_sda_oe connect \pc_i 1'0 connect \pc_i_ok 1'0 connect \pc_o \libresocsim_libresoc2 connect \rst $or$ls180.v:5711$1550_Y connect \sdr_a_0__core__o \libresocsim_libresoc_constraintmanager_sdram_a [0] connect \sdr_a_0__pad__o \sdram_a [0] connect \sdr_a_10__core__o \libresocsim_libresoc_constraintmanager_sdram_a [10] connect \sdr_a_10__pad__o \sdram_a [10] connect \sdr_a_11__core__o \libresocsim_libresoc_constraintmanager_sdram_a [11] connect \sdr_a_11__pad__o \sdram_a [11] connect \sdr_a_12__core__o \libresocsim_libresoc_constraintmanager_sdram_a [12] connect \sdr_a_12__pad__o \sdram_a [12] connect \sdr_a_1__core__o \libresocsim_libresoc_constraintmanager_sdram_a [1] connect \sdr_a_1__pad__o \sdram_a [1] connect \sdr_a_2__core__o \libresocsim_libresoc_constraintmanager_sdram_a [2] connect \sdr_a_2__pad__o \sdram_a [2] connect \sdr_a_3__core__o \libresocsim_libresoc_constraintmanager_sdram_a [3] connect \sdr_a_3__pad__o \sdram_a [3] connect \sdr_a_4__core__o \libresocsim_libresoc_constraintmanager_sdram_a [4] connect \sdr_a_4__pad__o \sdram_a [4] connect \sdr_a_5__core__o \libresocsim_libresoc_constraintmanager_sdram_a [5] connect \sdr_a_5__pad__o \sdram_a [5] connect \sdr_a_6__core__o \libresocsim_libresoc_constraintmanager_sdram_a [6] connect \sdr_a_6__pad__o \sdram_a [6] connect \sdr_a_7__core__o \libresocsim_libresoc_constraintmanager_sdram_a [7] connect \sdr_a_7__pad__o \sdram_a [7] connect \sdr_a_8__core__o \libresocsim_libresoc_constraintmanager_sdram_a [8] connect \sdr_a_8__pad__o \sdram_a [8] connect \sdr_a_9__core__o \libresocsim_libresoc_constraintmanager_sdram_a [9] connect \sdr_a_9__pad__o \sdram_a [9] connect \sdr_ba_0__core__o \libresocsim_libresoc_constraintmanager_sdram_ba [0] connect \sdr_ba_0__pad__o \sdram_ba [0] connect \sdr_ba_1__core__o \libresocsim_libresoc_constraintmanager_sdram_ba [1] connect \sdr_ba_1__pad__o \sdram_ba [1] connect \sdr_cas_n__core__o \libresocsim_libresoc_constraintmanager_sdram_cas_n connect \sdr_cas_n__pad__o \sdram_cas_n connect \sdr_cke__core__o \libresocsim_libresoc_constraintmanager_sdram_cke connect \sdr_cke__pad__o \sdram_cke connect \sdr_clock__core__o \libresocsim_libresoc_constraintmanager_sdram_clock connect \sdr_clock__pad__o \sdram_clock connect \sdr_cs_n__core__o \libresocsim_libresoc_constraintmanager_sdram_cs_n connect \sdr_cs_n__pad__o \sdram_cs_n connect \sdr_dm_0__core__o \libresocsim_libresoc_constraintmanager_sdram_dm [0] connect \sdr_dm_0__pad__o \sdram_dm [0] connect \sdr_dm_1__core__o \libresocsim_libresoc_constraintmanager_sdram_dm [1] connect \sdr_dm_1__pad__o \sdram_dm [1] connect \sdr_dq_0__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [0] connect \sdr_dq_0__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [0] connect \sdr_dq_0__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_0__pad__i \sdram_dq_i [0] connect \sdr_dq_0__pad__o \sdram_dq_o [0] connect \sdr_dq_0__pad__oe \sdram_dq_oe connect \sdr_dq_10__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [10] connect \sdr_dq_10__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [10] connect \sdr_dq_10__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_10__pad__i \sdram_dq_i [10] connect \sdr_dq_10__pad__o \sdram_dq_o [10] connect \sdr_dq_10__pad__oe \sdram_dq_oe connect \sdr_dq_11__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [11] connect \sdr_dq_11__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [11] connect \sdr_dq_11__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_11__pad__i \sdram_dq_i [11] connect \sdr_dq_11__pad__o \sdram_dq_o [11] connect \sdr_dq_11__pad__oe \sdram_dq_oe connect \sdr_dq_12__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [12] connect \sdr_dq_12__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [12] connect \sdr_dq_12__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_12__pad__i \sdram_dq_i [12] connect \sdr_dq_12__pad__o \sdram_dq_o [12] connect \sdr_dq_12__pad__oe \sdram_dq_oe connect \sdr_dq_13__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [13] connect \sdr_dq_13__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [13] connect \sdr_dq_13__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_13__pad__i \sdram_dq_i [13] connect \sdr_dq_13__pad__o \sdram_dq_o [13] connect \sdr_dq_13__pad__oe \sdram_dq_oe connect \sdr_dq_14__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [14] connect \sdr_dq_14__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [14] connect \sdr_dq_14__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_14__pad__i \sdram_dq_i [14] connect \sdr_dq_14__pad__o \sdram_dq_o [14] connect \sdr_dq_14__pad__oe \sdram_dq_oe connect \sdr_dq_15__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [15] connect \sdr_dq_15__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [15] connect \sdr_dq_15__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_15__pad__i \sdram_dq_i [15] connect \sdr_dq_15__pad__o \sdram_dq_o [15] connect \sdr_dq_15__pad__oe \sdram_dq_oe connect \sdr_dq_1__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [1] connect \sdr_dq_1__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [1] connect \sdr_dq_1__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_1__pad__i \sdram_dq_i [1] connect \sdr_dq_1__pad__o \sdram_dq_o [1] connect \sdr_dq_1__pad__oe \sdram_dq_oe connect \sdr_dq_2__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [2] connect \sdr_dq_2__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [2] connect \sdr_dq_2__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_2__pad__i \sdram_dq_i [2] connect \sdr_dq_2__pad__o \sdram_dq_o [2] connect \sdr_dq_2__pad__oe \sdram_dq_oe connect \sdr_dq_3__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [3] connect \sdr_dq_3__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [3] connect \sdr_dq_3__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_3__pad__i \sdram_dq_i [3] connect \sdr_dq_3__pad__o \sdram_dq_o [3] connect \sdr_dq_3__pad__oe \sdram_dq_oe connect \sdr_dq_4__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [4] connect \sdr_dq_4__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [4] connect \sdr_dq_4__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_4__pad__i \sdram_dq_i [4] connect \sdr_dq_4__pad__o \sdram_dq_o [4] connect \sdr_dq_4__pad__oe \sdram_dq_oe connect \sdr_dq_5__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [5] connect \sdr_dq_5__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [5] connect \sdr_dq_5__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_5__pad__i \sdram_dq_i [5] connect \sdr_dq_5__pad__o \sdram_dq_o [5] connect \sdr_dq_5__pad__oe \sdram_dq_oe connect \sdr_dq_6__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [6] connect \sdr_dq_6__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [6] connect \sdr_dq_6__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_6__pad__i \sdram_dq_i [6] connect \sdr_dq_6__pad__o \sdram_dq_o [6] connect \sdr_dq_6__pad__oe \sdram_dq_oe connect \sdr_dq_7__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [7] connect \sdr_dq_7__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [7] connect \sdr_dq_7__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_7__pad__i \sdram_dq_i [7] connect \sdr_dq_7__pad__o \sdram_dq_o [7] connect \sdr_dq_7__pad__oe \sdram_dq_oe connect \sdr_dq_8__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [8] connect \sdr_dq_8__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [8] connect \sdr_dq_8__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_8__pad__i \sdram_dq_i [8] connect \sdr_dq_8__pad__o \sdram_dq_o [8] connect \sdr_dq_8__pad__oe \sdram_dq_oe connect \sdr_dq_9__core__i \libresocsim_libresoc_constraintmanager_sdram_dq_i [9] connect \sdr_dq_9__core__o \libresocsim_libresoc_constraintmanager_sdram_dq_o [9] connect \sdr_dq_9__core__oe \libresocsim_libresoc_constraintmanager_sdram_dq_oe connect \sdr_dq_9__pad__i \sdram_dq_i [9] connect \sdr_dq_9__pad__o \sdram_dq_o [9] connect \sdr_dq_9__pad__oe \sdram_dq_oe connect \sdr_ras_n__core__o \libresocsim_libresoc_constraintmanager_sdram_ras_n connect \sdr_ras_n__pad__o \sdram_ras_n connect \sdr_we_n__core__o \libresocsim_libresoc_constraintmanager_sdram_we_n connect \sdr_we_n__pad__o \sdram_we_n end attribute \src "ls180.v:0.0-0.0" process $proc$ls180.v:0$2061 sync always sync init end attribute \src "ls180.v:0.0-0.0" process $proc$ls180.v:0$2062 sync always sync init end attribute \src "ls180.v:1002.5-1002.41" process $proc$ls180.v:1002$1948 assign { } { } assign $1\subfragments_converter0_state[0:0] 1'0 sync always sync init update \subfragments_converter0_state $1\subfragments_converter0_state[0:0] end attribute \src "ls180.v:1003.5-1003.46" process $proc$ls180.v:1003$1949 assign { } { } assign $1\subfragments_converter0_next_state[0:0] 1'0 sync always sync init update \subfragments_converter0_next_state $1\subfragments_converter0_next_state[0:0] end attribute \src "ls180.v:1004.5-1004.77" process $proc$ls180.v:1004$1950 assign { } { } assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 sync always sync init update \libresocsim_converter0_counter_subfragments_converter0_next_value $1\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] end attribute \src "ls180.v:1005.5-1005.80" process $proc$ls180.v:1005$1951 assign { } { } assign $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 sync always sync init update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $1\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] end attribute \src "ls180.v:1006.5-1006.41" process $proc$ls180.v:1006$1952 assign { } { } assign $1\subfragments_converter1_state[0:0] 1'0 sync always sync init update \subfragments_converter1_state $1\subfragments_converter1_state[0:0] end attribute \src "ls180.v:1007.5-1007.46" process $proc$ls180.v:1007$1953 assign { } { } assign $1\subfragments_converter1_next_state[0:0] 1'0 sync always sync init update \subfragments_converter1_next_state $1\subfragments_converter1_next_state[0:0] end attribute \src "ls180.v:1008.5-1008.77" process $proc$ls180.v:1008$1954 assign { } { } assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 sync always sync init update \libresocsim_converter1_counter_subfragments_converter1_next_value $1\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] end attribute \src "ls180.v:1009.5-1009.80" process $proc$ls180.v:1009$1955 assign { } { } assign $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 sync always sync init update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $1\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] end attribute \src "ls180.v:101.5-101.44" process $proc$ls180.v:101$1562 assign { } { } assign $0\libresocsim_libresoc_jtag_wb_err[0:0] 1'0 sync always update \libresocsim_libresoc_jtag_wb_err $0\libresocsim_libresoc_jtag_wb_err[0:0] sync init end attribute \src "ls180.v:1010.5-1010.41" process $proc$ls180.v:1010$1956 assign { } { } assign $1\subfragments_converter2_state[0:0] 1'0 sync always sync init update \subfragments_converter2_state $1\subfragments_converter2_state[0:0] end attribute \src "ls180.v:1011.5-1011.46" process $proc$ls180.v:1011$1957 assign { } { } assign $1\subfragments_converter2_next_state[0:0] 1'0 sync always sync init update \subfragments_converter2_next_state $1\subfragments_converter2_next_state[0:0] end attribute \src "ls180.v:1012.5-1012.77" process $proc$ls180.v:1012$1958 assign { } { } assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 sync always sync init update \libresocsim_converter2_counter_subfragments_converter2_next_value $1\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] end attribute \src "ls180.v:1013.5-1013.80" process $proc$ls180.v:1013$1959 assign { } { } assign $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0 sync always sync init update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $1\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] end attribute \src "ls180.v:1014.11-1014.46" process $proc$ls180.v:1014$1960 assign { } { } assign $1\subfragments_refresher_state[1:0] 2'00 sync always sync init update \subfragments_refresher_state $1\subfragments_refresher_state[1:0] end attribute \src "ls180.v:1015.11-1015.51" process $proc$ls180.v:1015$1961 assign { } { } assign $1\subfragments_refresher_next_state[1:0] 2'00 sync always sync init update \subfragments_refresher_next_state $1\subfragments_refresher_next_state[1:0] end attribute \src "ls180.v:1016.11-1016.49" process $proc$ls180.v:1016$1962 assign { } { } assign $1\subfragments_bankmachine0_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine0_state $1\subfragments_bankmachine0_state[2:0] end attribute \src "ls180.v:1017.11-1017.54" process $proc$ls180.v:1017$1963 assign { } { } assign $1\subfragments_bankmachine0_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine0_next_state $1\subfragments_bankmachine0_next_state[2:0] end attribute \src "ls180.v:1018.11-1018.49" process $proc$ls180.v:1018$1964 assign { } { } assign $1\subfragments_bankmachine1_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine1_state $1\subfragments_bankmachine1_state[2:0] end attribute \src "ls180.v:1019.11-1019.54" process $proc$ls180.v:1019$1965 assign { } { } assign $1\subfragments_bankmachine1_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine1_next_state $1\subfragments_bankmachine1_next_state[2:0] end attribute \src "ls180.v:1020.11-1020.49" process $proc$ls180.v:1020$1966 assign { } { } assign $1\subfragments_bankmachine2_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine2_state $1\subfragments_bankmachine2_state[2:0] end attribute \src "ls180.v:1021.11-1021.54" process $proc$ls180.v:1021$1967 assign { } { } assign $1\subfragments_bankmachine2_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine2_next_state $1\subfragments_bankmachine2_next_state[2:0] end attribute \src "ls180.v:1022.11-1022.49" process $proc$ls180.v:1022$1968 assign { } { } assign $1\subfragments_bankmachine3_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine3_state $1\subfragments_bankmachine3_state[2:0] end attribute \src "ls180.v:1023.11-1023.54" process $proc$ls180.v:1023$1969 assign { } { } assign $1\subfragments_bankmachine3_next_state[2:0] 3'000 sync always sync init update \subfragments_bankmachine3_next_state $1\subfragments_bankmachine3_next_state[2:0] end attribute \src "ls180.v:1024.11-1024.48" process $proc$ls180.v:1024$1970 assign { } { } assign $1\subfragments_multiplexer_state[2:0] 3'000 sync always sync init update \subfragments_multiplexer_state $1\subfragments_multiplexer_state[2:0] end attribute \src "ls180.v:1025.11-1025.53" process $proc$ls180.v:1025$1971 assign { } { } assign $1\subfragments_multiplexer_next_state[2:0] 3'000 sync always sync init update \subfragments_multiplexer_next_state $1\subfragments_multiplexer_next_state[2:0] end attribute \src "ls180.v:1038.5-1038.32" process $proc$ls180.v:1038$1972 assign { } { } assign $0\subfragments_locked0[0:0] 1'0 sync always update \subfragments_locked0 $0\subfragments_locked0[0:0] sync init end attribute \src "ls180.v:1039.5-1039.32" process $proc$ls180.v:1039$1973 assign { } { } assign $0\subfragments_locked1[0:0] 1'0 sync always update \subfragments_locked1 $0\subfragments_locked1[0:0] sync init end attribute \src "ls180.v:1040.5-1040.32" process $proc$ls180.v:1040$1974 assign { } { } assign $0\subfragments_locked2[0:0] 1'0 sync always update \subfragments_locked2 $0\subfragments_locked2[0:0] sync init end attribute \src "ls180.v:1041.5-1041.32" process $proc$ls180.v:1041$1975 assign { } { } assign $0\subfragments_locked3[0:0] 1'0 sync always update \subfragments_locked3 $0\subfragments_locked3[0:0] sync init end attribute \src "ls180.v:1042.5-1042.47" process $proc$ls180.v:1042$1976 assign { } { } assign $1\subfragments_new_master_wdata_ready[0:0] 1'0 sync always sync init update \subfragments_new_master_wdata_ready $1\subfragments_new_master_wdata_ready[0:0] end attribute \src "ls180.v:1043.5-1043.48" process $proc$ls180.v:1043$1977 assign { } { } assign $1\subfragments_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid0 $1\subfragments_new_master_rdata_valid0[0:0] end attribute \src "ls180.v:1044.5-1044.48" process $proc$ls180.v:1044$1978 assign { } { } assign $1\subfragments_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid1 $1\subfragments_new_master_rdata_valid1[0:0] end attribute \src "ls180.v:1045.5-1045.48" process $proc$ls180.v:1045$1979 assign { } { } assign $1\subfragments_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid2 $1\subfragments_new_master_rdata_valid2[0:0] end attribute \src "ls180.v:1046.5-1046.48" process $proc$ls180.v:1046$1980 assign { } { } assign $1\subfragments_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \subfragments_new_master_rdata_valid3 $1\subfragments_new_master_rdata_valid3[0:0] end attribute \src "ls180.v:1047.5-1047.30" process $proc$ls180.v:1047$1981 assign { } { } assign $1\subfragments_state[0:0] 1'0 sync always sync init update \subfragments_state $1\subfragments_state[0:0] end attribute \src "ls180.v:1048.5-1048.35" process $proc$ls180.v:1048$1982 assign { } { } assign $1\subfragments_next_state[0:0] 1'0 sync always sync init update \subfragments_next_state $1\subfragments_next_state[0:0] end attribute \src "ls180.v:1049.5-1049.53" process $proc$ls180.v:1049$1983 assign { } { } assign $1\converter_counter_subfragments_next_value[0:0] 1'0 sync always sync init update \converter_counter_subfragments_next_value $1\converter_counter_subfragments_next_value[0:0] end attribute \src "ls180.v:1050.5-1050.56" process $proc$ls180.v:1050$1984 assign { } { } assign $1\converter_counter_subfragments_next_value_ce[0:0] 1'0 sync always sync init update \converter_counter_subfragments_next_value_ce $1\converter_counter_subfragments_next_value_ce[0:0] end attribute \src "ls180.v:1051.12-1051.47" process $proc$ls180.v:1051$1985 assign { } { } assign $1\libresocsim_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \libresocsim_libresocsim_adr $1\libresocsim_libresocsim_adr[13:0] end attribute \src "ls180.v:1052.5-1052.38" process $proc$ls180.v:1052$1986 assign { } { } assign $1\libresocsim_libresocsim_we[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_we $1\libresocsim_libresocsim_we[0:0] end attribute \src "ls180.v:1053.11-1053.47" process $proc$ls180.v:1053$1987 assign { } { } assign $1\libresocsim_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \libresocsim_libresocsim_dat_w $1\libresocsim_libresocsim_dat_w[7:0] end attribute \src "ls180.v:1057.12-1057.58" process $proc$ls180.v:1057$1988 assign { } { } assign $1\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init update \libresocsim_libresocsim_wishbone_dat_r $1\libresocsim_libresocsim_wishbone_dat_r[31:0] end attribute \src "ls180.v:1061.5-1061.48" process $proc$ls180.v:1061$1989 assign { } { } assign $1\libresocsim_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_wishbone_ack $1\libresocsim_libresocsim_wishbone_ack[0:0] end attribute \src "ls180.v:1065.5-1065.48" process $proc$ls180.v:1065$1990 assign { } { } assign $0\libresocsim_libresocsim_wishbone_err[0:0] 1'0 sync always update \libresocsim_libresocsim_wishbone_err $0\libresocsim_libresocsim_wishbone_err[0:0] sync init end attribute \src "ls180.v:1068.12-1068.44" process $proc$ls180.v:1068$1991 assign { } { } assign $1\libresocsim_shared_dat_r[31:0] 0 sync always sync init update \libresocsim_shared_dat_r $1\libresocsim_shared_dat_r[31:0] end attribute \src "ls180.v:1072.5-1072.34" process $proc$ls180.v:1072$1992 assign { } { } assign $1\libresocsim_shared_ack[0:0] 1'0 sync always sync init update \libresocsim_shared_ack $1\libresocsim_shared_ack[0:0] end attribute \src "ls180.v:1078.11-1078.35" process $proc$ls180.v:1078$1993 assign { } { } assign $1\libresocsim_grant[1:0] 2'00 sync always sync init update \libresocsim_grant $1\libresocsim_grant[1:0] end attribute \src "ls180.v:1079.11-1079.39" process $proc$ls180.v:1079$1994 assign { } { } assign $1\libresocsim_slave_sel[5:0] 6'000000 sync always sync init update \libresocsim_slave_sel $1\libresocsim_slave_sel[5:0] end attribute \src "ls180.v:1080.11-1080.41" process $proc$ls180.v:1080$1995 assign { } { } assign $1\libresocsim_slave_sel_r[5:0] 6'000000 sync always sync init update \libresocsim_slave_sel_r $1\libresocsim_slave_sel_r[5:0] end attribute \src "ls180.v:1081.5-1081.29" process $proc$ls180.v:1081$1996 assign { } { } assign $1\libresocsim_error[0:0] 1'0 sync always sync init update \libresocsim_error $1\libresocsim_error[0:0] end attribute \src "ls180.v:1084.12-1084.43" process $proc$ls180.v:1084$1997 assign { } { } assign $1\libresocsim_count[19:0] 20'11110100001001000000 sync always sync init update \libresocsim_count $1\libresocsim_count[19:0] end attribute \src "ls180.v:1088.11-1088.55" process $proc$ls180.v:1088$1998 assign { } { } assign $1\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface0_bank_bus_dat_r $1\libresocsim_interface0_bank_bus_dat_r[7:0] end attribute \src "ls180.v:109.12-109.66" process $proc$ls180.v:109$1563 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] 13'0000000000000 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_a $1\libresocsim_libresoc_constraintmanager_sdram_a[12:0] end attribute \src "ls180.v:111.12-111.69" process $proc$ls180.v:111$1564 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] 16'0000000000000000 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] end attribute \src "ls180.v:112.5-112.62" process $proc$ls180.v:112$1565 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] end attribute \src "ls180.v:1129.11-1129.55" process $proc$ls180.v:1129$1999 assign { } { } assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0] end attribute \src "ls180.v:113.5-113.61" process $proc$ls180.v:113$1566 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_we_n $1\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] end attribute \src "ls180.v:114.5-114.62" process $proc$ls180.v:114$1567 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] end attribute \src "ls180.v:1146.11-1146.55" process $proc$ls180.v:1146$2000 assign { } { } assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0] end attribute \src "ls180.v:115.5-115.62" process $proc$ls180.v:115$1568 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] end attribute \src "ls180.v:116.5-116.61" process $proc$ls180.v:116$1569 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] end attribute \src "ls180.v:1163.11-1163.55" process $proc$ls180.v:1163$2001 assign { } { } assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0] end attribute \src "ls180.v:117.5-117.60" process $proc$ls180.v:117$1570 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_cke $1\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] end attribute \src "ls180.v:1176.11-1176.55" process $proc$ls180.v:1176$2002 assign { } { } assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0] end attribute \src "ls180.v:118.11-118.65" process $proc$ls180.v:118$1571 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] 2'00 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_ba $1\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] end attribute \src "ls180.v:119.11-119.65" process $proc$ls180.v:119$1572 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] 2'00 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_dm $1\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] end attribute \src "ls180.v:120.5-120.62" process $proc$ls180.v:120$1573 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] 1'0 sync always sync init update \libresocsim_libresoc_constraintmanager_sdram_clock $1\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] end attribute \src "ls180.v:121.5-121.64" process $proc$ls180.v:121$1574 assign { } { } assign $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] 1'0 sync always update \libresocsim_libresoc_constraintmanager_spimaster_clk $0\libresocsim_libresoc_constraintmanager_spimaster_clk[0:0] sync init end attribute \src "ls180.v:1217.11-1217.55" process $proc$ls180.v:1217$2003 assign { } { } assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0] end attribute \src "ls180.v:122.5-122.65" process $proc$ls180.v:122$1575 assign { } { } assign $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] 1'0 sync always update \libresocsim_libresoc_constraintmanager_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_spimaster_mosi[0:0] sync init end attribute \src "ls180.v:123.5-123.65" process $proc$ls180.v:123$1576 assign { } { } assign $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] 1'0 sync always update \libresocsim_libresoc_constraintmanager_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_spimaster_cs_n[0:0] sync init end attribute \src "ls180.v:1282.11-1282.55" process $proc$ls180.v:1282$2004 assign { } { } assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0] end attribute \src "ls180.v:130.12-130.65" process $proc$ls180.v:130$1577 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] 16'0000000000000000 sync always sync init update \libresocsim_libresoc_constraintmanager_gpio_o $1\libresocsim_libresoc_constraintmanager_gpio_o[15:0] end attribute \src "ls180.v:1307.11-1307.55" process $proc$ls180.v:1307$2005 assign { } { } assign $1\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0] end attribute \src "ls180.v:131.12-131.66" process $proc$ls180.v:131$1578 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] 16'0000000000000000 sync always sync init update \libresocsim_libresoc_constraintmanager_gpio_oe $1\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] end attribute \src "ls180.v:132.5-132.58" process $proc$ls180.v:132$1579 assign { } { } assign $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 sync always sync init update \libresocsim_libresoc_constraintmanager_uart_tx $1\libresocsim_libresoc_constraintmanager_uart_tx[0:0] end attribute \src "ls180.v:1329.11-1329.35" process $proc$ls180.v:1329$2006 assign { } { } assign $1\libresocsim_state[1:0] 2'00 sync always sync init update \libresocsim_state $1\libresocsim_state[1:0] end attribute \src "ls180.v:133.5-133.58" process $proc$ls180.v:133$1580 assign { } { } assign $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] 1'0 sync always update \libresocsim_libresoc_constraintmanager_uart_rx $0\libresocsim_libresoc_constraintmanager_uart_rx[0:0] sync init end attribute \src "ls180.v:1330.11-1330.40" process $proc$ls180.v:1330$2007 assign { } { } assign $1\libresocsim_next_state[1:0] 2'00 sync always sync init update \libresocsim_next_state $1\libresocsim_next_state[1:0] end attribute \src "ls180.v:1331.11-1331.71" process $proc$ls180.v:1331$2008 assign { } { } assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 sync always sync init update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] end attribute \src "ls180.v:1332.5-1332.68" process $proc$ls180.v:1332$2009 assign { } { } assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] end attribute \src "ls180.v:1333.12-1333.71" process $proc$ls180.v:1333$2010 assign { } { } assign $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 sync always sync init update \libresocsim_libresocsim_adr_libresocsim_next_value1 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] end attribute \src "ls180.v:1334.5-1334.66" process $proc$ls180.v:1334$2011 assign { } { } assign $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] end attribute \src "ls180.v:1335.5-1335.62" process $proc$ls180.v:1335$2012 assign { } { } assign $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_we_libresocsim_next_value2 $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] end attribute \src "ls180.v:1336.5-1336.65" process $proc$ls180.v:1336$2013 assign { } { } assign $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 sync always sync init update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end attribute \src "ls180.v:1337.5-1337.28" process $proc$ls180.v:1337$2014 assign { } { } assign $1\rhs_array_muxed0[0:0] 1'0 sync always sync init update \rhs_array_muxed0 $1\rhs_array_muxed0[0:0] end attribute \src "ls180.v:1338.12-1338.36" process $proc$ls180.v:1338$2015 assign { } { } assign $1\rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \rhs_array_muxed1 $1\rhs_array_muxed1[12:0] end attribute \src "ls180.v:1339.11-1339.34" process $proc$ls180.v:1339$2016 assign { } { } assign $1\rhs_array_muxed2[1:0] 2'00 sync always sync init update \rhs_array_muxed2 $1\rhs_array_muxed2[1:0] end attribute \src "ls180.v:1340.5-1340.28" process $proc$ls180.v:1340$2017 assign { } { } assign $1\rhs_array_muxed3[0:0] 1'0 sync always sync init update \rhs_array_muxed3 $1\rhs_array_muxed3[0:0] end attribute \src "ls180.v:1341.5-1341.28" process $proc$ls180.v:1341$2018 assign { } { } assign $1\rhs_array_muxed4[0:0] 1'0 sync always sync init update \rhs_array_muxed4 $1\rhs_array_muxed4[0:0] end attribute \src "ls180.v:1342.5-1342.28" process $proc$ls180.v:1342$2019 assign { } { } assign $1\rhs_array_muxed5[0:0] 1'0 sync always sync init update \rhs_array_muxed5 $1\rhs_array_muxed5[0:0] end attribute \src "ls180.v:1343.5-1343.26" process $proc$ls180.v:1343$2020 assign { } { } assign $1\t_array_muxed0[0:0] 1'0 sync always sync init update \t_array_muxed0 $1\t_array_muxed0[0:0] end attribute \src "ls180.v:1344.5-1344.26" process $proc$ls180.v:1344$2021 assign { } { } assign $1\t_array_muxed1[0:0] 1'0 sync always sync init update \t_array_muxed1 $1\t_array_muxed1[0:0] end attribute \src "ls180.v:1345.5-1345.26" process $proc$ls180.v:1345$2022 assign { } { } assign $1\t_array_muxed2[0:0] 1'0 sync always sync init update \t_array_muxed2 $1\t_array_muxed2[0:0] end attribute \src "ls180.v:1346.5-1346.28" process $proc$ls180.v:1346$2023 assign { } { } assign $1\rhs_array_muxed6[0:0] 1'0 sync always sync init update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0] end attribute \src "ls180.v:1347.12-1347.36" process $proc$ls180.v:1347$2024 assign { } { } assign $1\rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \rhs_array_muxed7 $1\rhs_array_muxed7[12:0] end attribute \src "ls180.v:1348.11-1348.34" process $proc$ls180.v:1348$2025 assign { } { } assign $1\rhs_array_muxed8[1:0] 2'00 sync always sync init update \rhs_array_muxed8 $1\rhs_array_muxed8[1:0] end attribute \src "ls180.v:1349.5-1349.28" process $proc$ls180.v:1349$2026 assign { } { } assign $1\rhs_array_muxed9[0:0] 1'0 sync always sync init update \rhs_array_muxed9 $1\rhs_array_muxed9[0:0] end attribute \src "ls180.v:1350.5-1350.29" process $proc$ls180.v:1350$2027 assign { } { } assign $1\rhs_array_muxed10[0:0] 1'0 sync always sync init update \rhs_array_muxed10 $1\rhs_array_muxed10[0:0] end attribute \src "ls180.v:1351.5-1351.29" process $proc$ls180.v:1351$2028 assign { } { } assign $1\rhs_array_muxed11[0:0] 1'0 sync always sync init update \rhs_array_muxed11 $1\rhs_array_muxed11[0:0] end attribute \src "ls180.v:1352.5-1352.26" process $proc$ls180.v:1352$2029 assign { } { } assign $1\t_array_muxed3[0:0] 1'0 sync always sync init update \t_array_muxed3 $1\t_array_muxed3[0:0] end attribute \src "ls180.v:1353.5-1353.26" process $proc$ls180.v:1353$2030 assign { } { } assign $1\t_array_muxed4[0:0] 1'0 sync always sync init update \t_array_muxed4 $1\t_array_muxed4[0:0] end attribute \src "ls180.v:1354.5-1354.26" process $proc$ls180.v:1354$2031 assign { } { } assign $1\t_array_muxed5[0:0] 1'0 sync always sync init update \t_array_muxed5 $1\t_array_muxed5[0:0] end attribute \src "ls180.v:1355.12-1355.37" process $proc$ls180.v:1355$2032 assign { } { } assign $1\rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed12 $1\rhs_array_muxed12[21:0] end attribute \src "ls180.v:1356.5-1356.29" process $proc$ls180.v:1356$2033 assign { } { } assign $1\rhs_array_muxed13[0:0] 1'0 sync always sync init update \rhs_array_muxed13 $1\rhs_array_muxed13[0:0] end attribute \src "ls180.v:1357.5-1357.29" process $proc$ls180.v:1357$2034 assign { } { } assign $1\rhs_array_muxed14[0:0] 1'0 sync always sync init update \rhs_array_muxed14 $1\rhs_array_muxed14[0:0] end attribute \src "ls180.v:1358.12-1358.37" process $proc$ls180.v:1358$2035 assign { } { } assign $1\rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed15 $1\rhs_array_muxed15[21:0] end attribute \src "ls180.v:1359.5-1359.29" process $proc$ls180.v:1359$2036 assign { } { } assign $1\rhs_array_muxed16[0:0] 1'0 sync always sync init update \rhs_array_muxed16 $1\rhs_array_muxed16[0:0] end attribute \src "ls180.v:1360.5-1360.29" process $proc$ls180.v:1360$2037 assign { } { } assign $1\rhs_array_muxed17[0:0] 1'0 sync always sync init update \rhs_array_muxed17 $1\rhs_array_muxed17[0:0] end attribute \src "ls180.v:1361.12-1361.37" process $proc$ls180.v:1361$2038 assign { } { } assign $1\rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed18 $1\rhs_array_muxed18[21:0] end attribute \src "ls180.v:1362.5-1362.29" process $proc$ls180.v:1362$2039 assign { } { } assign $1\rhs_array_muxed19[0:0] 1'0 sync always sync init update \rhs_array_muxed19 $1\rhs_array_muxed19[0:0] end attribute \src "ls180.v:1363.5-1363.29" process $proc$ls180.v:1363$2040 assign { } { } assign $1\rhs_array_muxed20[0:0] 1'0 sync always sync init update \rhs_array_muxed20 $1\rhs_array_muxed20[0:0] end attribute \src "ls180.v:1364.12-1364.37" process $proc$ls180.v:1364$2041 assign { } { } assign $1\rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \rhs_array_muxed21 $1\rhs_array_muxed21[21:0] end attribute \src "ls180.v:1365.5-1365.29" process $proc$ls180.v:1365$2042 assign { } { } assign $1\rhs_array_muxed22[0:0] 1'0 sync always sync init update \rhs_array_muxed22 $1\rhs_array_muxed22[0:0] end attribute \src "ls180.v:1366.5-1366.29" process $proc$ls180.v:1366$2043 assign { } { } assign $1\rhs_array_muxed23[0:0] 1'0 sync always sync init update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0] end attribute \src "ls180.v:1367.12-1367.37" process $proc$ls180.v:1367$2044 assign { } { } assign $1\rhs_array_muxed24[29:0] 30'000000000000000000000000000000 sync always sync init update \rhs_array_muxed24 $1\rhs_array_muxed24[29:0] end attribute \src "ls180.v:1368.12-1368.37" process $proc$ls180.v:1368$2045 assign { } { } assign $1\rhs_array_muxed25[31:0] 0 sync always sync init update \rhs_array_muxed25 $1\rhs_array_muxed25[31:0] end attribute \src "ls180.v:1369.11-1369.35" process $proc$ls180.v:1369$2046 assign { } { } assign $1\rhs_array_muxed26[3:0] 4'0000 sync always sync init update \rhs_array_muxed26 $1\rhs_array_muxed26[3:0] end attribute \src "ls180.v:137.12-137.66" process $proc$ls180.v:137$1581 assign { } { } assign $1\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \libresocsim_interface0_converted_interface_adr $1\libresocsim_interface0_converted_interface_adr[29:0] end attribute \src "ls180.v:1370.5-1370.29" process $proc$ls180.v:1370$2047 assign { } { } assign $1\rhs_array_muxed27[0:0] 1'0 sync always sync init update \rhs_array_muxed27 $1\rhs_array_muxed27[0:0] end attribute \src "ls180.v:1371.5-1371.29" process $proc$ls180.v:1371$2048 assign { } { } assign $1\rhs_array_muxed28[0:0] 1'0 sync always sync init update \rhs_array_muxed28 $1\rhs_array_muxed28[0:0] end attribute \src "ls180.v:1372.5-1372.29" process $proc$ls180.v:1372$2049 assign { } { } assign $1\rhs_array_muxed29[0:0] 1'0 sync always sync init update \rhs_array_muxed29 $1\rhs_array_muxed29[0:0] end attribute \src "ls180.v:1373.11-1373.35" process $proc$ls180.v:1373$2050 assign { } { } assign $1\rhs_array_muxed30[2:0] 3'000 sync always sync init update \rhs_array_muxed30 $1\rhs_array_muxed30[2:0] end attribute \src "ls180.v:1374.11-1374.35" process $proc$ls180.v:1374$2051 assign { } { } assign $1\rhs_array_muxed31[1:0] 2'00 sync always sync init update \rhs_array_muxed31 $1\rhs_array_muxed31[1:0] end attribute \src "ls180.v:1375.11-1375.30" process $proc$ls180.v:1375$2052 assign { } { } assign $1\array_muxed0[1:0] 2'00 sync always sync init update \array_muxed0 $1\array_muxed0[1:0] end attribute \src "ls180.v:1376.12-1376.32" process $proc$ls180.v:1376$2053 assign { } { } assign $1\array_muxed1[12:0] 13'0000000000000 sync always sync init update \array_muxed1 $1\array_muxed1[12:0] end attribute \src "ls180.v:1377.5-1377.24" process $proc$ls180.v:1377$2054 assign { } { } assign $1\array_muxed2[0:0] 1'0 sync always sync init update \array_muxed2 $1\array_muxed2[0:0] end attribute \src "ls180.v:1378.5-1378.24" process $proc$ls180.v:1378$2055 assign { } { } assign $1\array_muxed3[0:0] 1'0 sync always sync init update \array_muxed3 $1\array_muxed3[0:0] end attribute \src "ls180.v:1379.5-1379.24" process $proc$ls180.v:1379$2056 assign { } { } assign $1\array_muxed4[0:0] 1'0 sync always sync init update \array_muxed4 $1\array_muxed4[0:0] end attribute \src "ls180.v:138.12-138.68" process $proc$ls180.v:138$1582 assign { } { } assign $1\libresocsim_interface0_converted_interface_dat_w[31:0] 0 sync always sync init update \libresocsim_interface0_converted_interface_dat_w $1\libresocsim_interface0_converted_interface_dat_w[31:0] end attribute \src "ls180.v:1380.5-1380.24" process $proc$ls180.v:1380$2057 assign { } { } assign $1\array_muxed5[0:0] 1'0 sync always sync init update \array_muxed5 $1\array_muxed5[0:0] end attribute \src "ls180.v:1381.5-1381.24" process $proc$ls180.v:1381$2058 assign { } { } assign $1\array_muxed6[0:0] 1'0 sync always sync init update \array_muxed6 $1\array_muxed6[0:0] end attribute \src "ls180.v:140.11-140.64" process $proc$ls180.v:140$1583 assign { } { } assign $1\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 sync always sync init update \libresocsim_interface0_converted_interface_sel $1\libresocsim_interface0_converted_interface_sel[3:0] end attribute \src "ls180.v:141.5-141.58" process $proc$ls180.v:141$1584 assign { } { } assign $1\libresocsim_interface0_converted_interface_cyc[0:0] 1'0 sync always sync init update \libresocsim_interface0_converted_interface_cyc $1\libresocsim_interface0_converted_interface_cyc[0:0] end attribute \src "ls180.v:142.5-142.58" process $proc$ls180.v:142$1585 assign { } { } assign $1\libresocsim_interface0_converted_interface_stb[0:0] 1'0 sync always sync init update \libresocsim_interface0_converted_interface_stb $1\libresocsim_interface0_converted_interface_stb[0:0] end attribute \src "ls180.v:1438.32-1438.44" process $proc$ls180.v:1438$2059 assign { } { } assign $1\regs0[0:0] 1'0 sync always sync init update \regs0 $1\regs0[0:0] end attribute \src "ls180.v:1439.32-1439.44" process $proc$ls180.v:1439$2060 assign { } { } assign $1\regs1[0:0] 1'0 sync always sync init update \regs1 $1\regs1[0:0] end attribute \src "ls180.v:144.5-144.57" process $proc$ls180.v:144$1586 assign { } { } assign $1\libresocsim_interface0_converted_interface_we[0:0] 1'0 sync always sync init update \libresocsim_interface0_converted_interface_we $1\libresocsim_interface0_converted_interface_we[0:0] end attribute \src "ls180.v:145.11-145.64" process $proc$ls180.v:145$1587 assign { } { } assign $0\libresocsim_interface0_converted_interface_cti[2:0] 3'000 sync always update \libresocsim_interface0_converted_interface_cti $0\libresocsim_interface0_converted_interface_cti[2:0] sync init end attribute \src "ls180.v:146.11-146.64" process $proc$ls180.v:146$1588 assign { } { } assign $0\libresocsim_interface0_converted_interface_bte[1:0] 2'00 sync always update \libresocsim_interface0_converted_interface_bte $0\libresocsim_interface0_converted_interface_bte[1:0] sync init end attribute \src "ls180.v:148.5-148.39" process $proc$ls180.v:148$1589 assign { } { } assign $1\libresocsim_converter0_skip[0:0] 1'0 sync always sync init update \libresocsim_converter0_skip $1\libresocsim_converter0_skip[0:0] end attribute \src "ls180.v:149.5-149.42" process $proc$ls180.v:149$1590 assign { } { } assign $1\libresocsim_converter0_counter[0:0] 1'0 sync always sync init update \libresocsim_converter0_counter $1\libresocsim_converter0_counter[0:0] end attribute \src "ls180.v:1490.1-1495.4" process $proc$ls180.v:1490$15 assign { } { } assign { } { } assign $0\eint_tmp[2:0] [0] \libresocsim_libresoc_constraintmanager_eint_0 assign $0\eint_tmp[2:0] [1] \libresocsim_libresoc_constraintmanager_eint_1 assign $0\eint_tmp[2:0] [2] \libresocsim_libresoc_constraintmanager_eint_2 sync always update \eint_tmp $0\eint_tmp[2:0] end attribute \src "ls180.v:1502.1-1509.4" process $proc$ls180.v:1502$16 assign { } { } assign $0\libresocsim_libresoc_interrupt[15:0] [12:2] 11'00000000000 assign $0\libresocsim_libresoc_interrupt[15:0] [13] \eint_tmp [0] assign $0\libresocsim_libresoc_interrupt[15:0] [14] \eint_tmp [1] assign $0\libresocsim_libresoc_interrupt[15:0] [15] \eint_tmp [2] assign $0\libresocsim_libresoc_interrupt[15:0] [0] \libresocsim_irq assign $0\libresocsim_libresoc_interrupt[15:0] [1] \irq sync always update \libresocsim_libresoc_interrupt $0\libresocsim_libresoc_interrupt[15:0] end attribute \src "ls180.v:151.12-151.48" process $proc$ls180.v:151$1591 assign { } { } assign $1\libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \libresocsim_converter0_dat_r $1\libresocsim_converter0_dat_r[63:0] end attribute \src "ls180.v:1511.1-1521.4" process $proc$ls180.v:1511$18 assign { } { } assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] 0 attribute \src "ls180.v:1513.2-1520.9" switch \libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] \libresocsim_libresoc_ibus_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface0_converted_interface_dat_w[31:0] \libresocsim_libresoc_ibus_dat_w [63:32] case end sync always update \libresocsim_interface0_converted_interface_dat_w $0\libresocsim_interface0_converted_interface_dat_w[31:0] end attribute \src "ls180.v:152.12-152.66" process $proc$ls180.v:152$1592 assign { } { } assign $1\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \libresocsim_interface1_converted_interface_adr $1\libresocsim_interface1_converted_interface_adr[29:0] end attribute \src "ls180.v:1523.1-1569.4" process $proc$ls180.v:1523$19 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_cyc[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_stb[0:0] 1'0 assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_we[0:0] 1'0 assign $0\libresocsim_converter0_skip[0:0] 1'0 assign $0\libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign { } { } assign $0\libresocsim_interface0_converted_interface_sel[3:0] 4'0000 assign $0\subfragments_converter0_next_state[0:0] \subfragments_converter0_state attribute \src "ls180.v:1535.2-1568.9" switch \subfragments_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface0_converted_interface_adr[29:0] { \libresocsim_libresoc_ibus_adr \libresocsim_converter0_counter } attribute \src "ls180.v:1538.4-1545.11" switch \libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\libresocsim_interface0_converted_interface_sel[3:0] \libresocsim_libresoc_ibus_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface0_converted_interface_sel[3:0] \libresocsim_libresoc_ibus_sel [7:4] case end attribute \src "ls180.v:1546.4-1559.7" switch $and$ls180.v:1546$20_Y attribute \src "ls180.v:1546.8-1546.71" case 1'1 assign $0\libresocsim_converter0_skip[0:0] $eq$ls180.v:1547$21_Y assign $0\libresocsim_interface0_converted_interface_we[0:0] \libresocsim_libresoc_ibus_we assign $0\libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:1549$22_Y assign $0\libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:1550$23_Y attribute \src "ls180.v:1551.5-1558.8" switch $or$ls180.v:1551$24_Y attribute \src "ls180.v:1551.9-1551.87" case 1'1 assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1552$25_Y assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 attribute \src "ls180.v:1554.6-1557.9" switch $eq$ls180.v:1554$26_Y attribute \src "ls180.v:1554.10-1554.50" case 1'1 assign $0\libresocsim_libresoc_ibus_ack[0:0] 1'1 assign $0\subfragments_converter0_next_state[0:0] 1'0 case end case end case end attribute \src "ls180.v:0.0-0.0" case assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] 1'0 assign $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 attribute \src "ls180.v:1564.4-1566.7" switch $and$ls180.v:1564$27_Y attribute \src "ls180.v:1564.8-1564.71" case 1'1 assign $0\subfragments_converter0_next_state[0:0] 1'1 case end end sync always update \libresocsim_libresoc_ibus_ack $0\libresocsim_libresoc_ibus_ack[0:0] update \libresocsim_interface0_converted_interface_adr $0\libresocsim_interface0_converted_interface_adr[29:0] update \libresocsim_interface0_converted_interface_sel $0\libresocsim_interface0_converted_interface_sel[3:0] update \libresocsim_interface0_converted_interface_cyc $0\libresocsim_interface0_converted_interface_cyc[0:0] update \libresocsim_interface0_converted_interface_stb $0\libresocsim_interface0_converted_interface_stb[0:0] update \libresocsim_interface0_converted_interface_we $0\libresocsim_interface0_converted_interface_we[0:0] update \libresocsim_converter0_skip $0\libresocsim_converter0_skip[0:0] update \subfragments_converter0_next_state $0\subfragments_converter0_next_state[0:0] update \libresocsim_converter0_counter_subfragments_converter0_next_value $0\libresocsim_converter0_counter_subfragments_converter0_next_value[0:0] update \libresocsim_converter0_counter_subfragments_converter0_next_value_ce $0\libresocsim_converter0_counter_subfragments_converter0_next_value_ce[0:0] end attribute \src "ls180.v:153.12-153.68" process $proc$ls180.v:153$1593 assign { } { } assign $1\libresocsim_interface1_converted_interface_dat_w[31:0] 0 sync always sync init update \libresocsim_interface1_converted_interface_dat_w $1\libresocsim_interface1_converted_interface_dat_w[31:0] end attribute \src "ls180.v:155.11-155.64" process $proc$ls180.v:155$1594 assign { } { } assign $1\libresocsim_interface1_converted_interface_sel[3:0] 4'0000 sync always sync init update \libresocsim_interface1_converted_interface_sel $1\libresocsim_interface1_converted_interface_sel[3:0] end attribute \src "ls180.v:156.5-156.58" process $proc$ls180.v:156$1595 assign { } { } assign $1\libresocsim_interface1_converted_interface_cyc[0:0] 1'0 sync always sync init update \libresocsim_interface1_converted_interface_cyc $1\libresocsim_interface1_converted_interface_cyc[0:0] end attribute \src "ls180.v:157.5-157.58" process $proc$ls180.v:157$1596 assign { } { } assign $1\libresocsim_interface1_converted_interface_stb[0:0] 1'0 sync always sync init update \libresocsim_interface1_converted_interface_stb $1\libresocsim_interface1_converted_interface_stb[0:0] end attribute \src "ls180.v:1571.1-1581.4" process $proc$ls180.v:1571$29 assign { } { } assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] 0 attribute \src "ls180.v:1573.2-1580.9" switch \libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] \libresocsim_libresoc_dbus_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface1_converted_interface_dat_w[31:0] \libresocsim_libresoc_dbus_dat_w [63:32] case end sync always update \libresocsim_interface1_converted_interface_dat_w $0\libresocsim_interface1_converted_interface_dat_w[31:0] end attribute \src "ls180.v:1583.1-1629.4" process $proc$ls180.v:1583$30 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\libresocsim_converter1_skip[0:0] 1'0 assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'0 assign $0\libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign $0\libresocsim_interface1_converted_interface_sel[3:0] 4'0000 assign $0\libresocsim_interface1_converted_interface_cyc[0:0] 1'0 assign { } { } assign $0\libresocsim_interface1_converted_interface_stb[0:0] 1'0 assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 assign $0\libresocsim_interface1_converted_interface_we[0:0] 1'0 assign $0\subfragments_converter1_next_state[0:0] \subfragments_converter1_state attribute \src "ls180.v:1595.2-1628.9" switch \subfragments_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface1_converted_interface_adr[29:0] { \libresocsim_libresoc_dbus_adr \libresocsim_converter1_counter } attribute \src "ls180.v:1598.4-1605.11" switch \libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\libresocsim_interface1_converted_interface_sel[3:0] \libresocsim_libresoc_dbus_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface1_converted_interface_sel[3:0] \libresocsim_libresoc_dbus_sel [7:4] case end attribute \src "ls180.v:1606.4-1619.7" switch $and$ls180.v:1606$31_Y attribute \src "ls180.v:1606.8-1606.71" case 1'1 assign $0\libresocsim_converter1_skip[0:0] $eq$ls180.v:1607$32_Y assign $0\libresocsim_interface1_converted_interface_we[0:0] \libresocsim_libresoc_dbus_we assign $0\libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:1609$33_Y assign $0\libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:1610$34_Y attribute \src "ls180.v:1611.5-1618.8" switch $or$ls180.v:1611$35_Y attribute \src "ls180.v:1611.9-1611.87" case 1'1 assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1612$36_Y assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 attribute \src "ls180.v:1614.6-1617.9" switch $eq$ls180.v:1614$37_Y attribute \src "ls180.v:1614.10-1614.50" case 1'1 assign $0\libresocsim_libresoc_dbus_ack[0:0] 1'1 assign $0\subfragments_converter1_next_state[0:0] 1'0 case end case end case end attribute \src "ls180.v:0.0-0.0" case assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] 1'0 assign $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 attribute \src "ls180.v:1624.4-1626.7" switch $and$ls180.v:1624$38_Y attribute \src "ls180.v:1624.8-1624.71" case 1'1 assign $0\subfragments_converter1_next_state[0:0] 1'1 case end end sync always update \libresocsim_libresoc_dbus_ack $0\libresocsim_libresoc_dbus_ack[0:0] update \libresocsim_interface1_converted_interface_adr $0\libresocsim_interface1_converted_interface_adr[29:0] update \libresocsim_interface1_converted_interface_sel $0\libresocsim_interface1_converted_interface_sel[3:0] update \libresocsim_interface1_converted_interface_cyc $0\libresocsim_interface1_converted_interface_cyc[0:0] update \libresocsim_interface1_converted_interface_stb $0\libresocsim_interface1_converted_interface_stb[0:0] update \libresocsim_interface1_converted_interface_we $0\libresocsim_interface1_converted_interface_we[0:0] update \libresocsim_converter1_skip $0\libresocsim_converter1_skip[0:0] update \subfragments_converter1_next_state $0\subfragments_converter1_next_state[0:0] update \libresocsim_converter1_counter_subfragments_converter1_next_value $0\libresocsim_converter1_counter_subfragments_converter1_next_value[0:0] update \libresocsim_converter1_counter_subfragments_converter1_next_value_ce $0\libresocsim_converter1_counter_subfragments_converter1_next_value_ce[0:0] end attribute \src "ls180.v:159.5-159.57" process $proc$ls180.v:159$1597 assign { } { } assign $1\libresocsim_interface1_converted_interface_we[0:0] 1'0 sync always sync init update \libresocsim_interface1_converted_interface_we $1\libresocsim_interface1_converted_interface_we[0:0] end attribute \src "ls180.v:160.11-160.64" process $proc$ls180.v:160$1598 assign { } { } assign $0\libresocsim_interface1_converted_interface_cti[2:0] 3'000 sync always update \libresocsim_interface1_converted_interface_cti $0\libresocsim_interface1_converted_interface_cti[2:0] sync init end attribute \src "ls180.v:161.11-161.64" process $proc$ls180.v:161$1599 assign { } { } assign $0\libresocsim_interface1_converted_interface_bte[1:0] 2'00 sync always update \libresocsim_interface1_converted_interface_bte $0\libresocsim_interface1_converted_interface_bte[1:0] sync init end attribute \src "ls180.v:163.5-163.39" process $proc$ls180.v:163$1600 assign { } { } assign $1\libresocsim_converter1_skip[0:0] 1'0 sync always sync init update \libresocsim_converter1_skip $1\libresocsim_converter1_skip[0:0] end attribute \src "ls180.v:1631.1-1641.4" process $proc$ls180.v:1631$40 assign { } { } assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] 0 attribute \src "ls180.v:1633.2-1640.9" switch \libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] \libresocsim_libresoc_jtag_wb_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface2_converted_interface_dat_w[31:0] \libresocsim_libresoc_jtag_wb_dat_w [63:32] case end sync always update \libresocsim_interface2_converted_interface_dat_w $0\libresocsim_interface2_converted_interface_dat_w[31:0] end attribute \src "ls180.v:164.5-164.42" process $proc$ls180.v:164$1601 assign { } { } assign $1\libresocsim_converter1_counter[0:0] 1'0 sync always sync init update \libresocsim_converter1_counter $1\libresocsim_converter1_counter[0:0] end attribute \src "ls180.v:1643.1-1689.4" process $proc$ls180.v:1643$41 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 assign $0\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign $0\libresocsim_interface2_converted_interface_sel[3:0] 4'0000 assign $0\libresocsim_interface2_converted_interface_cyc[0:0] 1'0 assign $0\libresocsim_interface2_converted_interface_stb[0:0] 1'0 assign { } { } assign $0\libresocsim_interface2_converted_interface_we[0:0] 1'0 assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'0 assign $0\libresocsim_converter2_skip[0:0] 1'0 assign $0\subfragments_converter2_next_state[0:0] \subfragments_converter2_state attribute \src "ls180.v:1655.2-1688.9" switch \subfragments_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface2_converted_interface_adr[29:0] { \libresocsim_libresoc_jtag_wb_adr \libresocsim_converter2_counter } attribute \src "ls180.v:1658.4-1665.11" switch \libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\libresocsim_interface2_converted_interface_sel[3:0] \libresocsim_libresoc_jtag_wb_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface2_converted_interface_sel[3:0] \libresocsim_libresoc_jtag_wb_sel [7:4] case end attribute \src "ls180.v:1666.4-1679.7" switch $and$ls180.v:1666$42_Y attribute \src "ls180.v:1666.8-1666.77" case 1'1 assign $0\libresocsim_converter2_skip[0:0] $eq$ls180.v:1667$43_Y assign $0\libresocsim_interface2_converted_interface_we[0:0] \libresocsim_libresoc_jtag_wb_we assign $0\libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:1669$44_Y assign $0\libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:1670$45_Y attribute \src "ls180.v:1671.5-1678.8" switch $or$ls180.v:1671$46_Y attribute \src "ls180.v:1671.9-1671.87" case 1'1 assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1672$47_Y assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1 attribute \src "ls180.v:1674.6-1677.9" switch $eq$ls180.v:1674$48_Y attribute \src "ls180.v:1674.10-1674.50" case 1'1 assign $0\libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 assign $0\subfragments_converter2_next_state[0:0] 1'0 case end case end case end attribute \src "ls180.v:0.0-0.0" case assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] 1'0 assign $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] 1'1 attribute \src "ls180.v:1684.4-1686.7" switch $and$ls180.v:1684$49_Y attribute \src "ls180.v:1684.8-1684.77" case 1'1 assign $0\subfragments_converter2_next_state[0:0] 1'1 case end end sync always update \libresocsim_libresoc_jtag_wb_ack $0\libresocsim_libresoc_jtag_wb_ack[0:0] update \libresocsim_interface2_converted_interface_adr $0\libresocsim_interface2_converted_interface_adr[29:0] update \libresocsim_interface2_converted_interface_sel $0\libresocsim_interface2_converted_interface_sel[3:0] update \libresocsim_interface2_converted_interface_cyc $0\libresocsim_interface2_converted_interface_cyc[0:0] update \libresocsim_interface2_converted_interface_stb $0\libresocsim_interface2_converted_interface_stb[0:0] update \libresocsim_interface2_converted_interface_we $0\libresocsim_interface2_converted_interface_we[0:0] update \libresocsim_converter2_skip $0\libresocsim_converter2_skip[0:0] update \subfragments_converter2_next_state $0\subfragments_converter2_next_state[0:0] update \libresocsim_converter2_counter_subfragments_converter2_next_value $0\libresocsim_converter2_counter_subfragments_converter2_next_value[0:0] update \libresocsim_converter2_counter_subfragments_converter2_next_value_ce $0\libresocsim_converter2_counter_subfragments_converter2_next_value_ce[0:0] end attribute \src "ls180.v:166.12-166.48" process $proc$ls180.v:166$1602 assign { } { } assign $1\libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \libresocsim_converter1_dat_r $1\libresocsim_converter1_dat_r[63:0] end attribute \src "ls180.v:167.12-167.66" process $proc$ls180.v:167$1603 assign { } { } assign $1\libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \libresocsim_interface2_converted_interface_adr $1\libresocsim_interface2_converted_interface_adr[29:0] end attribute \src "ls180.v:168.12-168.68" process $proc$ls180.v:168$1604 assign { } { } assign $1\libresocsim_interface2_converted_interface_dat_w[31:0] 0 sync always sync init update \libresocsim_interface2_converted_interface_dat_w $1\libresocsim_interface2_converted_interface_dat_w[31:0] end attribute \src "ls180.v:1692.1-1698.4" process $proc$ls180.v:1692$50 assign { } { } assign { } { } assign $0\libresocsim_we[3:0] [0] $and$ls180.v:1694$53_Y assign $0\libresocsim_we[3:0] [1] $and$ls180.v:1695$56_Y assign $0\libresocsim_we[3:0] [2] $and$ls180.v:1696$59_Y assign $0\libresocsim_we[3:0] [3] $and$ls180.v:1697$62_Y sync always update \libresocsim_we $0\libresocsim_we[3:0] end attribute \src "ls180.v:170.11-170.64" process $proc$ls180.v:170$1605 assign { } { } assign $1\libresocsim_interface2_converted_interface_sel[3:0] 4'0000 sync always sync init update \libresocsim_interface2_converted_interface_sel $1\libresocsim_interface2_converted_interface_sel[3:0] end attribute \src "ls180.v:1704.1-1709.4" process $proc$ls180.v:1704$64 assign { } { } assign $0\libresocsim_zero_clear[0:0] 1'0 attribute \src "ls180.v:1706.2-1708.5" switch $and$ls180.v:1706$65_Y attribute \src "ls180.v:1706.6-1706.80" case 1'1 assign $0\libresocsim_zero_clear[0:0] 1'1 case end sync always update \libresocsim_zero_clear $0\libresocsim_zero_clear[0:0] end attribute \src "ls180.v:171.5-171.58" process $proc$ls180.v:171$1606 assign { } { } assign $1\libresocsim_interface2_converted_interface_cyc[0:0] 1'0 sync always sync init update \libresocsim_interface2_converted_interface_cyc $1\libresocsim_interface2_converted_interface_cyc[0:0] end attribute \src "ls180.v:1713.1-1719.4" process $proc$ls180.v:1713$67 assign { } { } assign { } { } assign $0\ram_we[3:0] [0] $and$ls180.v:1715$70_Y assign $0\ram_we[3:0] [1] $and$ls180.v:1716$73_Y assign $0\ram_we[3:0] [2] $and$ls180.v:1717$76_Y assign $0\ram_we[3:0] [3] $and$ls180.v:1718$79_Y sync always update \ram_we $0\ram_we[3:0] end attribute \src "ls180.v:172.5-172.58" process $proc$ls180.v:172$1607 assign { } { } assign $1\libresocsim_interface2_converted_interface_stb[0:0] 1'0 sync always sync init update \libresocsim_interface2_converted_interface_stb $1\libresocsim_interface2_converted_interface_stb[0:0] end attribute \src "ls180.v:174.5-174.57" process $proc$ls180.v:174$1608 assign { } { } assign $1\libresocsim_interface2_converted_interface_we[0:0] 1'0 sync always sync init update \libresocsim_interface2_converted_interface_we $1\libresocsim_interface2_converted_interface_we[0:0] end attribute \src "ls180.v:175.11-175.64" process $proc$ls180.v:175$1609 assign { } { } assign $0\libresocsim_interface2_converted_interface_cti[2:0] 3'000 sync always update \libresocsim_interface2_converted_interface_cti $0\libresocsim_interface2_converted_interface_cti[2:0] sync init end attribute \src "ls180.v:1758.1-1812.4" process $proc$ls180.v:1758$80 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_slave_p0_rddata[15:0] 16'0000000000000000 assign $0\sdram_slave_p0_rddata_valid[0:0] 1'0 assign $0\sdram_master_p0_address[12:0] 13'0000000000000 assign $0\sdram_master_p0_bank[1:0] 2'00 assign $0\sdram_master_p0_cas_n[0:0] 1'1 assign $0\sdram_master_p0_cs_n[0:0] 1'1 assign $0\sdram_master_p0_ras_n[0:0] 1'1 assign $0\sdram_master_p0_we_n[0:0] 1'1 assign $0\sdram_master_p0_cke[0:0] 1'0 assign $0\sdram_master_p0_odt[0:0] 1'0 assign $0\sdram_master_p0_reset_n[0:0] 1'0 assign $0\sdram_master_p0_act_n[0:0] 1'1 assign $0\sdram_inti_p0_rddata[15:0] 16'0000000000000000 assign $0\sdram_master_p0_wrdata[15:0] 16'0000000000000000 assign $0\sdram_inti_p0_rddata_valid[0:0] 1'0 assign $0\sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\sdram_master_p0_rddata_en[0:0] 1'0 attribute \src "ls180.v:1777.2-1811.5" switch \sdram_sel attribute \src "ls180.v:1777.6-1777.15" case 1'1 assign $0\sdram_master_p0_address[12:0] \sdram_slave_p0_address assign $0\sdram_master_p0_bank[1:0] \sdram_slave_p0_bank assign $0\sdram_master_p0_cas_n[0:0] \sdram_slave_p0_cas_n assign $0\sdram_master_p0_cs_n[0:0] \sdram_slave_p0_cs_n assign $0\sdram_master_p0_ras_n[0:0] \sdram_slave_p0_ras_n assign $0\sdram_master_p0_we_n[0:0] \sdram_slave_p0_we_n assign $0\sdram_master_p0_cke[0:0] \sdram_slave_p0_cke assign $0\sdram_master_p0_odt[0:0] \sdram_slave_p0_odt assign $0\sdram_master_p0_reset_n[0:0] \sdram_slave_p0_reset_n assign $0\sdram_master_p0_act_n[0:0] \sdram_slave_p0_act_n assign $0\sdram_master_p0_wrdata[15:0] \sdram_slave_p0_wrdata assign $0\sdram_master_p0_wrdata_en[0:0] \sdram_slave_p0_wrdata_en assign $0\sdram_master_p0_wrdata_mask[1:0] \sdram_slave_p0_wrdata_mask assign $0\sdram_master_p0_rddata_en[0:0] \sdram_slave_p0_rddata_en assign $0\sdram_slave_p0_rddata[15:0] \sdram_master_p0_rddata assign $0\sdram_slave_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid attribute \src "ls180.v:1794.6-1794.10" case assign $0\sdram_master_p0_address[12:0] \sdram_inti_p0_address assign $0\sdram_master_p0_bank[1:0] \sdram_inti_p0_bank assign $0\sdram_master_p0_cas_n[0:0] \sdram_inti_p0_cas_n assign $0\sdram_master_p0_cs_n[0:0] \sdram_inti_p0_cs_n assign $0\sdram_master_p0_ras_n[0:0] \sdram_inti_p0_ras_n assign $0\sdram_master_p0_we_n[0:0] \sdram_inti_p0_we_n assign $0\sdram_master_p0_cke[0:0] \sdram_inti_p0_cke assign $0\sdram_master_p0_odt[0:0] \sdram_inti_p0_odt assign $0\sdram_master_p0_reset_n[0:0] \sdram_inti_p0_reset_n assign $0\sdram_master_p0_act_n[0:0] \sdram_inti_p0_act_n assign $0\sdram_master_p0_wrdata[15:0] \sdram_inti_p0_wrdata assign $0\sdram_master_p0_wrdata_en[0:0] \sdram_inti_p0_wrdata_en assign $0\sdram_master_p0_wrdata_mask[1:0] \sdram_inti_p0_wrdata_mask assign $0\sdram_master_p0_rddata_en[0:0] \sdram_inti_p0_rddata_en assign $0\sdram_inti_p0_rddata[15:0] \sdram_master_p0_rddata assign $0\sdram_inti_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid end sync always update \sdram_inti_p0_rddata $0\sdram_inti_p0_rddata[15:0] update \sdram_inti_p0_rddata_valid $0\sdram_inti_p0_rddata_valid[0:0] update \sdram_slave_p0_rddata $0\sdram_slave_p0_rddata[15:0] update \sdram_slave_p0_rddata_valid $0\sdram_slave_p0_rddata_valid[0:0] update \sdram_master_p0_address $0\sdram_master_p0_address[12:0] update \sdram_master_p0_bank $0\sdram_master_p0_bank[1:0] update \sdram_master_p0_cas_n $0\sdram_master_p0_cas_n[0:0] update \sdram_master_p0_cs_n $0\sdram_master_p0_cs_n[0:0] update \sdram_master_p0_ras_n $0\sdram_master_p0_ras_n[0:0] update \sdram_master_p0_we_n $0\sdram_master_p0_we_n[0:0] update \sdram_master_p0_cke $0\sdram_master_p0_cke[0:0] update \sdram_master_p0_odt $0\sdram_master_p0_odt[0:0] update \sdram_master_p0_reset_n $0\sdram_master_p0_reset_n[0:0] update \sdram_master_p0_act_n $0\sdram_master_p0_act_n[0:0] update \sdram_master_p0_wrdata $0\sdram_master_p0_wrdata[15:0] update \sdram_master_p0_wrdata_en $0\sdram_master_p0_wrdata_en[0:0] update \sdram_master_p0_wrdata_mask $0\sdram_master_p0_wrdata_mask[1:0] update \sdram_master_p0_rddata_en $0\sdram_master_p0_rddata_en[0:0] end attribute \src "ls180.v:176.11-176.64" process $proc$ls180.v:176$1610 assign { } { } assign $0\libresocsim_interface2_converted_interface_bte[1:0] 2'00 sync always update \libresocsim_interface2_converted_interface_bte $0\libresocsim_interface2_converted_interface_bte[1:0] sync init end attribute \src "ls180.v:178.5-178.39" process $proc$ls180.v:178$1611 assign { } { } assign $1\libresocsim_converter2_skip[0:0] 1'0 sync always sync init update \libresocsim_converter2_skip $1\libresocsim_converter2_skip[0:0] end attribute \src "ls180.v:179.5-179.42" process $proc$ls180.v:179$1612 assign { } { } assign $1\libresocsim_converter2_counter[0:0] 1'0 sync always sync init update \libresocsim_converter2_counter $1\libresocsim_converter2_counter[0:0] end attribute \src "ls180.v:181.12-181.48" process $proc$ls180.v:181$1613 assign { } { } assign $1\libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \libresocsim_converter2_dat_r $1\libresocsim_converter2_dat_r[63:0] end attribute \src "ls180.v:1816.1-1832.4" process $proc$ls180.v:1816$81 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_inti_p0_cas_n[0:0] 1'1 assign $0\sdram_inti_p0_cs_n[0:0] 1'1 assign $0\sdram_inti_p0_ras_n[0:0] 1'1 assign $0\sdram_inti_p0_we_n[0:0] 1'1 attribute \src "ls180.v:1821.2-1831.5" switch \sdram_command_issue_re attribute \src "ls180.v:1821.6-1821.28" case 1'1 assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1822$82_Y assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1823$83_Y assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1824$84_Y assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1825$85_Y attribute \src "ls180.v:1826.6-1826.10" case assign $0\sdram_inti_p0_cs_n[0:0] 1'1 assign $0\sdram_inti_p0_we_n[0:0] 1'1 assign $0\sdram_inti_p0_cas_n[0:0] 1'1 assign $0\sdram_inti_p0_ras_n[0:0] 1'1 end sync always update \sdram_inti_p0_cas_n $0\sdram_inti_p0_cas_n[0:0] update \sdram_inti_p0_cs_n $0\sdram_inti_p0_cs_n[0:0] update \sdram_inti_p0_ras_n $0\sdram_inti_p0_ras_n[0:0] update \sdram_inti_p0_we_n $0\sdram_inti_p0_we_n[0:0] end attribute \src "ls180.v:1875.1-1905.4" process $proc$ls180.v:1875$94 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_cmd_last[0:0] 1'0 assign $0\sdram_sequencer_start0[0:0] 1'0 assign { } { } assign $0\sdram_cmd_valid[0:0] 1'0 assign $0\subfragments_refresher_next_state[1:0] \subfragments_refresher_state attribute \src "ls180.v:1881.2-1904.9" switch \subfragments_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\sdram_cmd_valid[0:0] 1'1 attribute \src "ls180.v:1884.4-1887.7" switch \sdram_cmd_ready attribute \src "ls180.v:1884.8-1884.23" case 1'1 assign $0\sdram_sequencer_start0[0:0] 1'1 assign $0\subfragments_refresher_next_state[1:0] 2'10 case end attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\sdram_cmd_valid[0:0] 1'1 attribute \src "ls180.v:1891.4-1895.7" switch \sdram_sequencer_done0 attribute \src "ls180.v:1891.8-1891.29" case 1'1 assign $0\sdram_cmd_valid[0:0] 1'0 assign $0\sdram_cmd_last[0:0] 1'1 assign $0\subfragments_refresher_next_state[1:0] 2'00 case end attribute \src "ls180.v:0.0-0.0" case attribute \src "ls180.v:1898.4-1902.7" switch 1'1 attribute \src "ls180.v:1898.8-1898.12" case 1'1 attribute \src "ls180.v:1899.5-1901.8" switch \sdram_wants_refresh attribute \src "ls180.v:1899.9-1899.28" case 1'1 assign $0\subfragments_refresher_next_state[1:0] 2'01 case end case end end sync always update \sdram_cmd_valid $0\sdram_cmd_valid[0:0] update \sdram_cmd_last $0\sdram_cmd_last[0:0] update \sdram_sequencer_start0 $0\sdram_sequencer_start0[0:0] update \subfragments_refresher_next_state $0\subfragments_refresher_next_state[1:0] end attribute \src "ls180.v:188.5-188.35" process $proc$ls180.v:188$1614 assign { } { } assign $1\libresocsim_ram_bus_ack[0:0] 1'0 sync always sync init update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0] end attribute \src "ls180.v:192.5-192.35" process $proc$ls180.v:192$1615 assign { } { } assign $0\libresocsim_ram_bus_err[0:0] 1'0 sync always update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0] sync init end attribute \src "ls180.v:1920.1-1927.4" process $proc$ls180.v:1920$98 assign { } { } assign $0\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 attribute \src "ls180.v:1922.2-1926.5" switch \sdram_bankmachine0_row_col_n_addr_sel attribute \src "ls180.v:1922.6-1922.43" case 1'1 assign $0\sdram_bankmachine0_cmd_payload_a[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] attribute \src "ls180.v:1924.6-1924.10" case assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1925$100_Y end sync always update \sdram_bankmachine0_cmd_payload_a $0\sdram_bankmachine0_cmd_payload_a[12:0] end attribute \src "ls180.v:1931.1-1938.4" process $proc$ls180.v:1931$107 assign { } { } assign $0\sdram_bankmachine0_auto_precharge[0:0] 1'0 attribute \src "ls180.v:1933.2-1937.5" switch $and$ls180.v:1933$108_Y attribute \src "ls180.v:1933.6-1933.105" case 1'1 attribute \src "ls180.v:1934.3-1936.6" switch $ne$ls180.v:1934$109_Y attribute \src "ls180.v:1934.7-1934.133" case 1'1 assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1935$110_Y case end case end sync always update \sdram_bankmachine0_auto_precharge $0\sdram_bankmachine0_auto_precharge[0:0] end attribute \src "ls180.v:195.11-195.32" process $proc$ls180.v:195$1616 assign { } { } assign $1\libresocsim_we[3:0] 4'0000 sync always sync init update \libresocsim_we $1\libresocsim_we[3:0] end attribute \src "ls180.v:1953.1-1960.4" process $proc$ls180.v:1953$111 assign { } { } assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 attribute \src "ls180.v:1955.2-1959.5" switch \sdram_bankmachine0_cmd_buffer_lookahead_replace attribute \src "ls180.v:1955.6-1955.53" case 1'1 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1956$112_Y attribute \src "ls180.v:1957.6-1957.10" case assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:1969.1-2062.4" process $proc$ls180.v:1969$120 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 assign $0\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign { } { } assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'0 assign $0\sdram_bankmachine0_row_open[0:0] 1'0 assign $0\sdram_bankmachine0_row_close[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 assign $0\subfragments_bankmachine0_next_state[2:0] \subfragments_bankmachine0_state attribute \src "ls180.v:1985.2-2061.9" switch \subfragments_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine0_row_close[0:0] 1'1 attribute \src "ls180.v:1987.4-1995.7" switch $and$ls180.v:1987$121_Y attribute \src "ls180.v:1987.8-1987.77" case 1'1 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:1989.5-1991.8" switch \sdram_bankmachine0_cmd_ready attribute \src "ls180.v:1989.9-1989.37" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case end case end attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine0_row_close[0:0] 1'1 attribute \src "ls180.v:1999.4-2001.7" switch $and$ls180.v:1999$122_Y attribute \src "ls180.v:1999.8-1999.77" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 attribute \src "ls180.v:2005.4-2014.7" switch \sdram_bankmachine0_trccon_ready attribute \src "ls180.v:2005.8-2005.39" case 1'1 assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine0_row_open[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 attribute \src "ls180.v:2010.5-2012.8" switch \sdram_bankmachine0_cmd_ready attribute \src "ls180.v:2010.9-2010.37" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\sdram_bankmachine0_row_close[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:2017.4-2019.7" switch \sdram_bankmachine0_twtpcon_ready attribute \src "ls180.v:2017.8-2017.40" case 1'1 assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end attribute \src "ls180.v:2022.4-2024.7" switch $not$ls180.v:2022$123_Y attribute \src "ls180.v:2022.8-2022.41" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\subfragments_bankmachine0_next_state[2:0] 3'011 attribute \src "ls180.v:0.0-0.0" case 3'110 assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case attribute \src "ls180.v:2033.4-2059.7" switch \sdram_bankmachine0_refresh_req attribute \src "ls180.v:2033.8-2033.38" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'100 attribute \src "ls180.v:2035.8-2035.12" case attribute \src "ls180.v:2036.5-2058.8" switch \sdram_bankmachine0_cmd_buffer_source_valid attribute \src "ls180.v:2036.9-2036.51" case 1'1 attribute \src "ls180.v:2037.6-2057.9" switch \sdram_bankmachine0_row_opened attribute \src "ls180.v:2037.10-2037.39" case 1'1 attribute \src "ls180.v:2038.7-2054.10" switch \sdram_bankmachine0_row_hit attribute \src "ls180.v:2038.11-2038.37" case 1'1 assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 attribute \src "ls180.v:2040.8-2047.11" switch \sdram_bankmachine0_cmd_buffer_source_payload_we attribute \src "ls180.v:2040.12-2040.59" case 1'1 assign $0\sdram_bankmachine0_req_wdata_ready[0:0] \sdram_bankmachine0_cmd_ready assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 attribute \src "ls180.v:2044.12-2044.16" case assign $0\sdram_bankmachine0_req_rdata_valid[0:0] \sdram_bankmachine0_cmd_ready assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end attribute \src "ls180.v:2049.8-2051.11" switch $and$ls180.v:2049$124_Y attribute \src "ls180.v:2049.12-2049.78" case 1'1 assign $0\subfragments_bankmachine0_next_state[2:0] 3'010 case end attribute \src "ls180.v:2052.11-2052.15" case assign $0\subfragments_bankmachine0_next_state[2:0] 3'001 end attribute \src "ls180.v:2055.10-2055.14" case assign $0\subfragments_bankmachine0_next_state[2:0] 3'011 end case end end end sync always update \sdram_bankmachine0_req_wdata_ready $0\sdram_bankmachine0_req_wdata_ready[0:0] update \sdram_bankmachine0_req_rdata_valid $0\sdram_bankmachine0_req_rdata_valid[0:0] update \sdram_bankmachine0_refresh_gnt $0\sdram_bankmachine0_refresh_gnt[0:0] update \sdram_bankmachine0_cmd_valid $0\sdram_bankmachine0_cmd_valid[0:0] update \sdram_bankmachine0_cmd_payload_cas $0\sdram_bankmachine0_cmd_payload_cas[0:0] update \sdram_bankmachine0_cmd_payload_ras $0\sdram_bankmachine0_cmd_payload_ras[0:0] update \sdram_bankmachine0_cmd_payload_we $0\sdram_bankmachine0_cmd_payload_we[0:0] update \sdram_bankmachine0_cmd_payload_is_cmd $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] update \sdram_bankmachine0_cmd_payload_is_read $0\sdram_bankmachine0_cmd_payload_is_read[0:0] update \sdram_bankmachine0_cmd_payload_is_write $0\sdram_bankmachine0_cmd_payload_is_write[0:0] update \sdram_bankmachine0_row_open $0\sdram_bankmachine0_row_open[0:0] update \sdram_bankmachine0_row_close $0\sdram_bankmachine0_row_close[0:0] update \sdram_bankmachine0_row_col_n_addr_sel $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] update \subfragments_bankmachine0_next_state $0\subfragments_bankmachine0_next_state[2:0] end attribute \src "ls180.v:197.12-197.44" process $proc$ls180.v:197$1617 assign { } { } assign $1\libresocsim_load_storage[31:0] 0 sync always sync init update \libresocsim_load_storage $1\libresocsim_load_storage[31:0] end attribute \src "ls180.v:198.5-198.31" process $proc$ls180.v:198$1618 assign { } { } assign $1\libresocsim_load_re[0:0] 1'0 sync always sync init update \libresocsim_load_re $1\libresocsim_load_re[0:0] end attribute \src "ls180.v:199.12-199.46" process $proc$ls180.v:199$1619 assign { } { } assign $1\libresocsim_reload_storage[31:0] 0 sync always sync init update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0] end attribute \src "ls180.v:200.5-200.33" process $proc$ls180.v:200$1620 assign { } { } assign $1\libresocsim_reload_re[0:0] 1'0 sync always sync init update \libresocsim_reload_re $1\libresocsim_reload_re[0:0] end attribute \src "ls180.v:201.5-201.34" process $proc$ls180.v:201$1621 assign { } { } assign $1\libresocsim_en_storage[0:0] 1'0 sync always sync init update \libresocsim_en_storage $1\libresocsim_en_storage[0:0] end attribute \src "ls180.v:202.5-202.29" process $proc$ls180.v:202$1622 assign { } { } assign $1\libresocsim_en_re[0:0] 1'0 sync always sync init update \libresocsim_en_re $1\libresocsim_en_re[0:0] end attribute \src "ls180.v:203.5-203.44" process $proc$ls180.v:203$1623 assign { } { } assign $1\libresocsim_update_value_storage[0:0] 1'0 sync always sync init update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0] end attribute \src "ls180.v:204.5-204.39" process $proc$ls180.v:204$1624 assign { } { } assign $1\libresocsim_update_value_re[0:0] 1'0 sync always sync init update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0] end attribute \src "ls180.v:205.12-205.44" process $proc$ls180.v:205$1625 assign { } { } assign $1\libresocsim_value_status[31:0] 0 sync always sync init update \libresocsim_value_status $1\libresocsim_value_status[31:0] end attribute \src "ls180.v:2077.1-2084.4" process $proc$ls180.v:2077$128 assign { } { } assign $0\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 attribute \src "ls180.v:2079.2-2083.5" switch \sdram_bankmachine1_row_col_n_addr_sel attribute \src "ls180.v:2079.6-2079.43" case 1'1 assign $0\sdram_bankmachine1_cmd_payload_a[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] attribute \src "ls180.v:2081.6-2081.10" case assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2082$130_Y end sync always update \sdram_bankmachine1_cmd_payload_a $0\sdram_bankmachine1_cmd_payload_a[12:0] end attribute \src "ls180.v:2088.1-2095.4" process $proc$ls180.v:2088$137 assign { } { } assign $0\sdram_bankmachine1_auto_precharge[0:0] 1'0 attribute \src "ls180.v:2090.2-2094.5" switch $and$ls180.v:2090$138_Y attribute \src "ls180.v:2090.6-2090.105" case 1'1 attribute \src "ls180.v:2091.3-2093.6" switch $ne$ls180.v:2091$139_Y attribute \src "ls180.v:2091.7-2091.133" case 1'1 assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2092$140_Y case end case end sync always update \sdram_bankmachine1_auto_precharge $0\sdram_bankmachine1_auto_precharge[0:0] end attribute \src "ls180.v:209.5-209.36" process $proc$ls180.v:209$1626 assign { } { } assign $1\libresocsim_zero_pending[0:0] 1'0 sync always sync init update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0] end attribute \src "ls180.v:211.5-211.34" process $proc$ls180.v:211$1627 assign { } { } assign $1\libresocsim_zero_clear[0:0] 1'0 sync always sync init update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0] end attribute \src "ls180.v:2110.1-2117.4" process $proc$ls180.v:2110$141 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 attribute \src "ls180.v:2112.2-2116.5" switch \sdram_bankmachine1_cmd_buffer_lookahead_replace attribute \src "ls180.v:2112.6-2112.53" case 1'1 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2113$142_Y attribute \src "ls180.v:2114.6-2114.10" case assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:212.5-212.40" process $proc$ls180.v:212$1628 assign { } { } assign $1\libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0] end attribute \src "ls180.v:2126.1-2219.4" process $proc$ls180.v:2126$150 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 assign { } { } assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\sdram_bankmachine1_row_open[0:0] 1'0 assign $0\sdram_bankmachine1_row_close[0:0] 1'0 assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 assign $0\subfragments_bankmachine1_next_state[2:0] \subfragments_bankmachine1_state attribute \src "ls180.v:2142.2-2218.9" switch \subfragments_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine1_row_close[0:0] 1'1 attribute \src "ls180.v:2144.4-2152.7" switch $and$ls180.v:2144$151_Y attribute \src "ls180.v:2144.8-2144.77" case 1'1 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:2146.5-2148.8" switch \sdram_bankmachine1_cmd_ready attribute \src "ls180.v:2146.9-2146.37" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 case end case end attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine1_row_close[0:0] 1'1 attribute \src "ls180.v:2156.4-2158.7" switch $and$ls180.v:2156$152_Y attribute \src "ls180.v:2156.8-2156.77" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 attribute \src "ls180.v:2162.4-2171.7" switch \sdram_bankmachine1_trccon_ready attribute \src "ls180.v:2162.8-2162.39" case 1'1 assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine1_row_open[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 attribute \src "ls180.v:2167.5-2169.8" switch \sdram_bankmachine1_cmd_ready attribute \src "ls180.v:2167.9-2167.37" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\sdram_bankmachine1_row_close[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:2174.4-2176.7" switch \sdram_bankmachine1_twtpcon_ready attribute \src "ls180.v:2174.8-2174.40" case 1'1 assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end attribute \src "ls180.v:2179.4-2181.7" switch $not$ls180.v:2179$153_Y attribute \src "ls180.v:2179.8-2179.41" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\subfragments_bankmachine1_next_state[2:0] 3'011 attribute \src "ls180.v:0.0-0.0" case 3'110 assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case attribute \src "ls180.v:2190.4-2216.7" switch \sdram_bankmachine1_refresh_req attribute \src "ls180.v:2190.8-2190.38" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'100 attribute \src "ls180.v:2192.8-2192.12" case attribute \src "ls180.v:2193.5-2215.8" switch \sdram_bankmachine1_cmd_buffer_source_valid attribute \src "ls180.v:2193.9-2193.51" case 1'1 attribute \src "ls180.v:2194.6-2214.9" switch \sdram_bankmachine1_row_opened attribute \src "ls180.v:2194.10-2194.39" case 1'1 attribute \src "ls180.v:2195.7-2211.10" switch \sdram_bankmachine1_row_hit attribute \src "ls180.v:2195.11-2195.37" case 1'1 assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 attribute \src "ls180.v:2197.8-2204.11" switch \sdram_bankmachine1_cmd_buffer_source_payload_we attribute \src "ls180.v:2197.12-2197.59" case 1'1 assign $0\sdram_bankmachine1_req_wdata_ready[0:0] \sdram_bankmachine1_cmd_ready assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 attribute \src "ls180.v:2201.12-2201.16" case assign $0\sdram_bankmachine1_req_rdata_valid[0:0] \sdram_bankmachine1_cmd_ready assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end attribute \src "ls180.v:2206.8-2208.11" switch $and$ls180.v:2206$154_Y attribute \src "ls180.v:2206.12-2206.78" case 1'1 assign $0\subfragments_bankmachine1_next_state[2:0] 3'010 case end attribute \src "ls180.v:2209.11-2209.15" case assign $0\subfragments_bankmachine1_next_state[2:0] 3'001 end attribute \src "ls180.v:2212.10-2212.14" case assign $0\subfragments_bankmachine1_next_state[2:0] 3'011 end case end end end sync always update \sdram_bankmachine1_req_wdata_ready $0\sdram_bankmachine1_req_wdata_ready[0:0] update \sdram_bankmachine1_req_rdata_valid $0\sdram_bankmachine1_req_rdata_valid[0:0] update \sdram_bankmachine1_refresh_gnt $0\sdram_bankmachine1_refresh_gnt[0:0] update \sdram_bankmachine1_cmd_valid $0\sdram_bankmachine1_cmd_valid[0:0] update \sdram_bankmachine1_cmd_payload_cas $0\sdram_bankmachine1_cmd_payload_cas[0:0] update \sdram_bankmachine1_cmd_payload_ras $0\sdram_bankmachine1_cmd_payload_ras[0:0] update \sdram_bankmachine1_cmd_payload_we $0\sdram_bankmachine1_cmd_payload_we[0:0] update \sdram_bankmachine1_cmd_payload_is_cmd $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] update \sdram_bankmachine1_cmd_payload_is_read $0\sdram_bankmachine1_cmd_payload_is_read[0:0] update \sdram_bankmachine1_cmd_payload_is_write $0\sdram_bankmachine1_cmd_payload_is_write[0:0] update \sdram_bankmachine1_row_open $0\sdram_bankmachine1_row_open[0:0] update \sdram_bankmachine1_row_close $0\sdram_bankmachine1_row_close[0:0] update \sdram_bankmachine1_row_col_n_addr_sel $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] update \subfragments_bankmachine1_next_state $0\subfragments_bankmachine1_next_state[2:0] end attribute \src "ls180.v:221.5-221.44" process $proc$ls180.v:221$1629 assign { } { } assign $1\libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0] end attribute \src "ls180.v:222.5-222.39" process $proc$ls180.v:222$1630 assign { } { } assign $1\libresocsim_eventmanager_re[0:0] 1'0 sync always sync init update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0] end attribute \src "ls180.v:223.12-223.37" process $proc$ls180.v:223$1631 assign { } { } assign $1\libresocsim_value[31:0] 0 sync always sync init update \libresocsim_value $1\libresocsim_value[31:0] end attribute \src "ls180.v:2234.1-2241.4" process $proc$ls180.v:2234$158 assign { } { } assign $0\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 attribute \src "ls180.v:2236.2-2240.5" switch \sdram_bankmachine2_row_col_n_addr_sel attribute \src "ls180.v:2236.6-2236.43" case 1'1 assign $0\sdram_bankmachine2_cmd_payload_a[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] attribute \src "ls180.v:2238.6-2238.10" case assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2239$160_Y end sync always update \sdram_bankmachine2_cmd_payload_a $0\sdram_bankmachine2_cmd_payload_a[12:0] end attribute \src "ls180.v:2245.1-2252.4" process $proc$ls180.v:2245$167 assign { } { } assign $0\sdram_bankmachine2_auto_precharge[0:0] 1'0 attribute \src "ls180.v:2247.2-2251.5" switch $and$ls180.v:2247$168_Y attribute \src "ls180.v:2247.6-2247.105" case 1'1 attribute \src "ls180.v:2248.3-2250.6" switch $ne$ls180.v:2248$169_Y attribute \src "ls180.v:2248.7-2248.133" case 1'1 assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2249$170_Y case end case end sync always update \sdram_bankmachine2_auto_precharge $0\sdram_bankmachine2_auto_precharge[0:0] end attribute \src "ls180.v:2267.1-2274.4" process $proc$ls180.v:2267$171 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 attribute \src "ls180.v:2269.2-2273.5" switch \sdram_bankmachine2_cmd_buffer_lookahead_replace attribute \src "ls180.v:2269.6-2269.53" case 1'1 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2270$172_Y attribute \src "ls180.v:2271.6-2271.10" case assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:2283.1-2376.4" process $proc$ls180.v:2283$180 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_bankmachine2_row_open[0:0] 1'0 assign $0\sdram_bankmachine2_row_close[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 assign $0\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0 assign { } { } assign $0\subfragments_bankmachine2_next_state[2:0] \subfragments_bankmachine2_state attribute \src "ls180.v:2299.2-2375.9" switch \subfragments_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine2_row_close[0:0] 1'1 attribute \src "ls180.v:2301.4-2309.7" switch $and$ls180.v:2301$181_Y attribute \src "ls180.v:2301.8-2301.77" case 1'1 assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:2303.5-2305.8" switch \sdram_bankmachine2_cmd_ready attribute \src "ls180.v:2303.9-2303.37" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case end case end attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine2_row_close[0:0] 1'1 attribute \src "ls180.v:2313.4-2315.7" switch $and$ls180.v:2313$182_Y attribute \src "ls180.v:2313.8-2313.77" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 attribute \src "ls180.v:2319.4-2328.7" switch \sdram_bankmachine2_trccon_ready attribute \src "ls180.v:2319.8-2319.39" case 1'1 assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine2_row_open[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 attribute \src "ls180.v:2324.5-2326.8" switch \sdram_bankmachine2_cmd_ready attribute \src "ls180.v:2324.9-2324.37" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\sdram_bankmachine2_row_close[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:2331.4-2333.7" switch \sdram_bankmachine2_twtpcon_ready attribute \src "ls180.v:2331.8-2331.40" case 1'1 assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end attribute \src "ls180.v:2336.4-2338.7" switch $not$ls180.v:2336$183_Y attribute \src "ls180.v:2336.8-2336.41" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\subfragments_bankmachine2_next_state[2:0] 3'011 attribute \src "ls180.v:0.0-0.0" case 3'110 assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case attribute \src "ls180.v:2347.4-2373.7" switch \sdram_bankmachine2_refresh_req attribute \src "ls180.v:2347.8-2347.38" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'100 attribute \src "ls180.v:2349.8-2349.12" case attribute \src "ls180.v:2350.5-2372.8" switch \sdram_bankmachine2_cmd_buffer_source_valid attribute \src "ls180.v:2350.9-2350.51" case 1'1 attribute \src "ls180.v:2351.6-2371.9" switch \sdram_bankmachine2_row_opened attribute \src "ls180.v:2351.10-2351.39" case 1'1 attribute \src "ls180.v:2352.7-2368.10" switch \sdram_bankmachine2_row_hit attribute \src "ls180.v:2352.11-2352.37" case 1'1 assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 attribute \src "ls180.v:2354.8-2361.11" switch \sdram_bankmachine2_cmd_buffer_source_payload_we attribute \src "ls180.v:2354.12-2354.59" case 1'1 assign $0\sdram_bankmachine2_req_wdata_ready[0:0] \sdram_bankmachine2_cmd_ready assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 attribute \src "ls180.v:2358.12-2358.16" case assign $0\sdram_bankmachine2_req_rdata_valid[0:0] \sdram_bankmachine2_cmd_ready assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end attribute \src "ls180.v:2363.8-2365.11" switch $and$ls180.v:2363$184_Y attribute \src "ls180.v:2363.12-2363.78" case 1'1 assign $0\subfragments_bankmachine2_next_state[2:0] 3'010 case end attribute \src "ls180.v:2366.11-2366.15" case assign $0\subfragments_bankmachine2_next_state[2:0] 3'001 end attribute \src "ls180.v:2369.10-2369.14" case assign $0\subfragments_bankmachine2_next_state[2:0] 3'011 end case end end end sync always update \sdram_bankmachine2_req_wdata_ready $0\sdram_bankmachine2_req_wdata_ready[0:0] update \sdram_bankmachine2_req_rdata_valid $0\sdram_bankmachine2_req_rdata_valid[0:0] update \sdram_bankmachine2_refresh_gnt $0\sdram_bankmachine2_refresh_gnt[0:0] update \sdram_bankmachine2_cmd_valid $0\sdram_bankmachine2_cmd_valid[0:0] update \sdram_bankmachine2_cmd_payload_cas $0\sdram_bankmachine2_cmd_payload_cas[0:0] update \sdram_bankmachine2_cmd_payload_ras $0\sdram_bankmachine2_cmd_payload_ras[0:0] update \sdram_bankmachine2_cmd_payload_we $0\sdram_bankmachine2_cmd_payload_we[0:0] update \sdram_bankmachine2_cmd_payload_is_cmd $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] update \sdram_bankmachine2_cmd_payload_is_read $0\sdram_bankmachine2_cmd_payload_is_read[0:0] update \sdram_bankmachine2_cmd_payload_is_write $0\sdram_bankmachine2_cmd_payload_is_write[0:0] update \sdram_bankmachine2_row_open $0\sdram_bankmachine2_row_open[0:0] update \sdram_bankmachine2_row_close $0\sdram_bankmachine2_row_close[0:0] update \sdram_bankmachine2_row_col_n_addr_sel $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] update \subfragments_bankmachine2_next_state $0\subfragments_bankmachine2_next_state[2:0] end attribute \src "ls180.v:230.5-230.31" process $proc$ls180.v:230$1632 assign { } { } assign $1\ram_bus_ram_bus_ack[0:0] 1'0 sync always sync init update \ram_bus_ram_bus_ack $1\ram_bus_ram_bus_ack[0:0] end attribute \src "ls180.v:234.5-234.31" process $proc$ls180.v:234$1633 assign { } { } assign $0\ram_bus_ram_bus_err[0:0] 1'0 sync always update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0] sync init end attribute \src "ls180.v:237.11-237.24" process $proc$ls180.v:237$1634 assign { } { } assign $1\ram_we[3:0] 4'0000 sync always sync init update \ram_we $1\ram_we[3:0] end attribute \src "ls180.v:2391.1-2398.4" process $proc$ls180.v:2391$188 assign { } { } assign $0\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 attribute \src "ls180.v:2393.2-2397.5" switch \sdram_bankmachine3_row_col_n_addr_sel attribute \src "ls180.v:2393.6-2393.43" case 1'1 assign $0\sdram_bankmachine3_cmd_payload_a[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] attribute \src "ls180.v:2395.6-2395.10" case assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2396$190_Y end sync always update \sdram_bankmachine3_cmd_payload_a $0\sdram_bankmachine3_cmd_payload_a[12:0] end attribute \src "ls180.v:2402.1-2409.4" process $proc$ls180.v:2402$197 assign { } { } assign $0\sdram_bankmachine3_auto_precharge[0:0] 1'0 attribute \src "ls180.v:2404.2-2408.5" switch $and$ls180.v:2404$198_Y attribute \src "ls180.v:2404.6-2404.105" case 1'1 attribute \src "ls180.v:2405.3-2407.6" switch $ne$ls180.v:2405$199_Y attribute \src "ls180.v:2405.7-2405.133" case 1'1 assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2406$200_Y case end case end sync always update \sdram_bankmachine3_auto_precharge $0\sdram_bankmachine3_auto_precharge[0:0] end attribute \src "ls180.v:242.5-242.19" process $proc$ls180.v:242$1635 assign { } { } assign $1\int_rst[0:0] 1'1 sync always sync init update \int_rst $1\int_rst[0:0] end attribute \src "ls180.v:2424.1-2431.4" process $proc$ls180.v:2424$201 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 attribute \src "ls180.v:2426.2-2430.5" switch \sdram_bankmachine3_cmd_buffer_lookahead_replace attribute \src "ls180.v:2426.6-2426.53" case 1'1 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2427$202_Y attribute \src "ls180.v:2428.6-2428.10" case assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:2440.1-2533.4" process $proc$ls180.v:2440$210 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'0 assign $0\sdram_bankmachine3_row_open[0:0] 1'0 assign $0\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 assign $0\sdram_bankmachine3_row_close[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign { } { } assign $0\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\subfragments_bankmachine3_next_state[2:0] \subfragments_bankmachine3_state attribute \src "ls180.v:2456.2-2532.9" switch \subfragments_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_bankmachine3_row_close[0:0] 1'1 attribute \src "ls180.v:2458.4-2466.7" switch $and$ls180.v:2458$211_Y attribute \src "ls180.v:2458.8-2458.77" case 1'1 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:2460.5-2462.8" switch \sdram_bankmachine3_cmd_ready attribute \src "ls180.v:2460.9-2460.37" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 case end case end attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_bankmachine3_row_close[0:0] 1'1 attribute \src "ls180.v:2470.4-2472.7" switch $and$ls180.v:2470$212_Y attribute \src "ls180.v:2470.8-2470.77" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 attribute \src "ls180.v:2476.4-2485.7" switch \sdram_bankmachine3_trccon_ready attribute \src "ls180.v:2476.8-2476.39" case 1'1 assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\sdram_bankmachine3_row_open[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 attribute \src "ls180.v:2481.5-2483.8" switch \sdram_bankmachine3_cmd_ready attribute \src "ls180.v:2481.9-2481.37" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\sdram_bankmachine3_row_close[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 attribute \src "ls180.v:2488.4-2490.7" switch \sdram_bankmachine3_twtpcon_ready attribute \src "ls180.v:2488.8-2488.40" case 1'1 assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end attribute \src "ls180.v:2493.4-2495.7" switch $not$ls180.v:2493$213_Y attribute \src "ls180.v:2493.8-2493.41" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\subfragments_bankmachine3_next_state[2:0] 3'011 attribute \src "ls180.v:0.0-0.0" case 3'110 assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case attribute \src "ls180.v:2504.4-2530.7" switch \sdram_bankmachine3_refresh_req attribute \src "ls180.v:2504.8-2504.38" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'100 attribute \src "ls180.v:2506.8-2506.12" case attribute \src "ls180.v:2507.5-2529.8" switch \sdram_bankmachine3_cmd_buffer_source_valid attribute \src "ls180.v:2507.9-2507.51" case 1'1 attribute \src "ls180.v:2508.6-2528.9" switch \sdram_bankmachine3_row_opened attribute \src "ls180.v:2508.10-2508.39" case 1'1 attribute \src "ls180.v:2509.7-2525.10" switch \sdram_bankmachine3_row_hit attribute \src "ls180.v:2509.11-2509.37" case 1'1 assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 attribute \src "ls180.v:2511.8-2518.11" switch \sdram_bankmachine3_cmd_buffer_source_payload_we attribute \src "ls180.v:2511.12-2511.59" case 1'1 assign $0\sdram_bankmachine3_req_wdata_ready[0:0] \sdram_bankmachine3_cmd_ready assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 attribute \src "ls180.v:2515.12-2515.16" case assign $0\sdram_bankmachine3_req_rdata_valid[0:0] \sdram_bankmachine3_cmd_ready assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end attribute \src "ls180.v:2520.8-2522.11" switch $and$ls180.v:2520$214_Y attribute \src "ls180.v:2520.12-2520.78" case 1'1 assign $0\subfragments_bankmachine3_next_state[2:0] 3'010 case end attribute \src "ls180.v:2523.11-2523.15" case assign $0\subfragments_bankmachine3_next_state[2:0] 3'001 end attribute \src "ls180.v:2526.10-2526.14" case assign $0\subfragments_bankmachine3_next_state[2:0] 3'011 end case end end end sync always update \sdram_bankmachine3_req_wdata_ready $0\sdram_bankmachine3_req_wdata_ready[0:0] update \sdram_bankmachine3_req_rdata_valid $0\sdram_bankmachine3_req_rdata_valid[0:0] update \sdram_bankmachine3_refresh_gnt $0\sdram_bankmachine3_refresh_gnt[0:0] update \sdram_bankmachine3_cmd_valid $0\sdram_bankmachine3_cmd_valid[0:0] update \sdram_bankmachine3_cmd_payload_cas $0\sdram_bankmachine3_cmd_payload_cas[0:0] update \sdram_bankmachine3_cmd_payload_ras $0\sdram_bankmachine3_cmd_payload_ras[0:0] update \sdram_bankmachine3_cmd_payload_we $0\sdram_bankmachine3_cmd_payload_we[0:0] update \sdram_bankmachine3_cmd_payload_is_cmd $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] update \sdram_bankmachine3_cmd_payload_is_read $0\sdram_bankmachine3_cmd_payload_is_read[0:0] update \sdram_bankmachine3_cmd_payload_is_write $0\sdram_bankmachine3_cmd_payload_is_write[0:0] update \sdram_bankmachine3_row_open $0\sdram_bankmachine3_row_open[0:0] update \sdram_bankmachine3_row_close $0\sdram_bankmachine3_row_close[0:0] update \sdram_bankmachine3_row_col_n_addr_sel $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] update \subfragments_bankmachine3_next_state $0\subfragments_bankmachine3_next_state[2:0] end attribute \src "ls180.v:2553.1-2559.4" process $proc$ls180.v:2553$253 assign { } { } assign { } { } assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2555$266_Y assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2556$279_Y assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2557$292_Y assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2558$305_Y sync always update \sdram_choose_cmd_valids $0\sdram_choose_cmd_valids[3:0] end attribute \src "ls180.v:2567.1-2572.4" process $proc$ls180.v:2567$306 assign { } { } assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 attribute \src "ls180.v:2569.2-2571.5" switch \sdram_choose_cmd_cmd_valid attribute \src "ls180.v:2569.6-2569.32" case 1'1 assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] \t_array_muxed0 case end sync always update \sdram_choose_cmd_cmd_payload_cas $0\sdram_choose_cmd_cmd_payload_cas[0:0] end attribute \src "ls180.v:257.12-257.33" process $proc$ls180.v:257$1636 assign { } { } assign $1\dfi_p0_rddata[15:0] 16'0000000000000000 sync always sync init update \dfi_p0_rddata $1\dfi_p0_rddata[15:0] end attribute \src "ls180.v:2573.1-2578.4" process $proc$ls180.v:2573$307 assign { } { } assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 attribute \src "ls180.v:2575.2-2577.5" switch \sdram_choose_cmd_cmd_valid attribute \src "ls180.v:2575.6-2575.32" case 1'1 assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] \t_array_muxed1 case end sync always update \sdram_choose_cmd_cmd_payload_ras $0\sdram_choose_cmd_cmd_payload_ras[0:0] end attribute \src "ls180.v:2579.1-2584.4" process $proc$ls180.v:2579$308 assign { } { } assign $0\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 attribute \src "ls180.v:2581.2-2583.5" switch \sdram_choose_cmd_cmd_valid attribute \src "ls180.v:2581.6-2581.32" case 1'1 assign $0\sdram_choose_cmd_cmd_payload_we[0:0] \t_array_muxed2 case end sync always update \sdram_choose_cmd_cmd_payload_we $0\sdram_choose_cmd_cmd_payload_we[0:0] end attribute \src "ls180.v:258.5-258.31" process $proc$ls180.v:258$1637 assign { } { } assign $1\dfi_p0_rddata_valid[0:0] 1'0 sync always sync init update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0] end attribute \src "ls180.v:2586.1-2592.4" process $proc$ls180.v:2586$311 assign { } { } assign { } { } assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2588$324_Y assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2589$337_Y assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2590$350_Y assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2591$363_Y sync always update \sdram_choose_req_valids $0\sdram_choose_req_valids[3:0] end attribute \src "ls180.v:259.11-259.27" process $proc$ls180.v:259$1638 assign { } { } assign $1\rddata_en[2:0] 3'000 sync always sync init update \rddata_en $1\rddata_en[2:0] end attribute \src "ls180.v:2600.1-2605.4" process $proc$ls180.v:2600$364 assign { } { } assign $0\sdram_choose_req_cmd_payload_cas[0:0] 1'0 attribute \src "ls180.v:2602.2-2604.5" switch \sdram_choose_req_cmd_valid attribute \src "ls180.v:2602.6-2602.32" case 1'1 assign $0\sdram_choose_req_cmd_payload_cas[0:0] \t_array_muxed3 case end sync always update \sdram_choose_req_cmd_payload_cas $0\sdram_choose_req_cmd_payload_cas[0:0] end attribute \src "ls180.v:2606.1-2611.4" process $proc$ls180.v:2606$365 assign { } { } assign $0\sdram_choose_req_cmd_payload_ras[0:0] 1'0 attribute \src "ls180.v:2608.2-2610.5" switch \sdram_choose_req_cmd_valid attribute \src "ls180.v:2608.6-2608.32" case 1'1 assign $0\sdram_choose_req_cmd_payload_ras[0:0] \t_array_muxed4 case end sync always update \sdram_choose_req_cmd_payload_ras $0\sdram_choose_req_cmd_payload_ras[0:0] end attribute \src "ls180.v:2612.1-2617.4" process $proc$ls180.v:2612$366 assign { } { } assign $0\sdram_choose_req_cmd_payload_we[0:0] 1'0 attribute \src "ls180.v:2614.2-2616.5" switch \sdram_choose_req_cmd_valid attribute \src "ls180.v:2614.6-2614.32" case 1'1 assign $0\sdram_choose_req_cmd_payload_we[0:0] \t_array_muxed5 case end sync always update \sdram_choose_req_cmd_payload_we $0\sdram_choose_req_cmd_payload_we[0:0] end attribute \src "ls180.v:2618.1-2626.4" process $proc$ls180.v:2618$367 assign { } { } assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'0 attribute \src "ls180.v:2620.2-2622.5" switch $and$ls180.v:2620$370_Y attribute \src "ls180.v:2620.6-2620.100" case 1'1 assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 case end attribute \src "ls180.v:2623.2-2625.5" switch $and$ls180.v:2623$373_Y attribute \src "ls180.v:2623.6-2623.100" case 1'1 assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 case end sync always update \sdram_bankmachine0_cmd_ready $0\sdram_bankmachine0_cmd_ready[0:0] end attribute \src "ls180.v:262.5-262.31" process $proc$ls180.v:262$1639 assign { } { } assign $1\sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0] end attribute \src "ls180.v:2627.1-2635.4" process $proc$ls180.v:2627$374 assign { } { } assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'0 attribute \src "ls180.v:2629.2-2631.5" switch $and$ls180.v:2629$377_Y attribute \src "ls180.v:2629.6-2629.100" case 1'1 assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 case end attribute \src "ls180.v:2632.2-2634.5" switch $and$ls180.v:2632$380_Y attribute \src "ls180.v:2632.6-2632.100" case 1'1 assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 case end sync always update \sdram_bankmachine1_cmd_ready $0\sdram_bankmachine1_cmd_ready[0:0] end attribute \src "ls180.v:263.5-263.30" process $proc$ls180.v:263$1640 assign { } { } assign $1\sdram_inti_p0_cs_n[0:0] 1'1 sync always sync init update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0] end attribute \src "ls180.v:2636.1-2644.4" process $proc$ls180.v:2636$381 assign { } { } assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'0 attribute \src "ls180.v:2638.2-2640.5" switch $and$ls180.v:2638$384_Y attribute \src "ls180.v:2638.6-2638.100" case 1'1 assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 case end attribute \src "ls180.v:2641.2-2643.5" switch $and$ls180.v:2641$387_Y attribute \src "ls180.v:2641.6-2641.100" case 1'1 assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 case end sync always update \sdram_bankmachine2_cmd_ready $0\sdram_bankmachine2_cmd_ready[0:0] end attribute \src "ls180.v:264.5-264.31" process $proc$ls180.v:264$1641 assign { } { } assign $1\sdram_inti_p0_ras_n[0:0] 1'1 sync always sync init update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0] end attribute \src "ls180.v:2645.1-2653.4" process $proc$ls180.v:2645$388 assign { } { } assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'0 attribute \src "ls180.v:2647.2-2649.5" switch $and$ls180.v:2647$391_Y attribute \src "ls180.v:2647.6-2647.100" case 1'1 assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 case end attribute \src "ls180.v:2650.2-2652.5" switch $and$ls180.v:2650$394_Y attribute \src "ls180.v:2650.6-2650.100" case 1'1 assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 case end sync always update \sdram_bankmachine3_cmd_ready $0\sdram_bankmachine3_cmd_ready[0:0] end attribute \src "ls180.v:265.5-265.30" process $proc$ls180.v:265$1642 assign { } { } assign $1\sdram_inti_p0_we_n[0:0] 1'1 sync always sync init update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0] end attribute \src "ls180.v:2658.1-2730.4" process $proc$ls180.v:2658$397 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_cmd_ready[0:0] 1'0 assign { } { } assign $0\sdram_choose_req_cmd_ready[0:0] 1'0 assign $0\sdram_steerer_sel[1:0] 2'00 assign $0\sdram_en0[0:0] 1'0 assign { } { } assign $0\sdram_en1[0:0] 1'0 assign $0\sdram_choose_req_want_reads[0:0] 1'0 assign $0\sdram_choose_req_want_writes[0:0] 1'0 assign $0\sdram_choose_req_want_activates[0:0] \sdram_ras_allowed assign $0\subfragments_multiplexer_next_state[2:0] \subfragments_multiplexer_state attribute \src "ls180.v:2670.2-2729.9" switch \subfragments_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\sdram_en1[0:0] 1'1 assign $0\sdram_choose_req_want_writes[0:0] 1'1 assign $0\sdram_steerer_sel[1:0] 2'10 attribute \src "ls180.v:2674.4-2680.7" switch 1'1 attribute \src "ls180.v:2674.8-2674.12" case 1'1 assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2675$404_Y case end attribute \src "ls180.v:2682.4-2686.7" switch \sdram_read_available attribute \src "ls180.v:2682.8-2682.28" case 1'1 attribute \src "ls180.v:2683.5-2685.8" switch $or$ls180.v:2683$406_Y attribute \src "ls180.v:2683.9-2683.53" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'011 case end case end attribute \src "ls180.v:2687.4-2689.7" switch \sdram_go_to_refresh attribute \src "ls180.v:2687.8-2687.27" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\sdram_steerer_sel[1:0] 2'11 assign $0\sdram_cmd_ready[0:0] 1'1 attribute \src "ls180.v:2694.4-2696.7" switch \sdram_cmd_last attribute \src "ls180.v:2694.8-2694.22" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 attribute \src "ls180.v:2699.4-2701.7" switch \sdram_twtrcon_ready attribute \src "ls180.v:2699.8-2699.27" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\subfragments_multiplexer_next_state[2:0] 3'101 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\subfragments_multiplexer_next_state[2:0] 3'001 attribute \src "ls180.v:0.0-0.0" case assign $0\sdram_en0[0:0] 1'1 assign $0\sdram_choose_req_want_reads[0:0] 1'1 assign $0\sdram_steerer_sel[1:0] 2'10 attribute \src "ls180.v:2712.4-2718.7" switch 1'1 attribute \src "ls180.v:2712.8-2712.12" case 1'1 assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2713$413_Y case end attribute \src "ls180.v:2720.4-2724.7" switch \sdram_write_available attribute \src "ls180.v:2720.8-2720.29" case 1'1 attribute \src "ls180.v:2721.5-2723.8" switch $or$ls180.v:2721$415_Y attribute \src "ls180.v:2721.9-2721.52" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'100 case end case end attribute \src "ls180.v:2725.4-2727.7" switch \sdram_go_to_refresh attribute \src "ls180.v:2725.8-2725.27" case 1'1 assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case end end sync always update \sdram_cmd_ready $0\sdram_cmd_ready[0:0] update \sdram_choose_req_want_reads $0\sdram_choose_req_want_reads[0:0] update \sdram_choose_req_want_writes $0\sdram_choose_req_want_writes[0:0] update \sdram_choose_req_want_activates $0\sdram_choose_req_want_activates[0:0] update \sdram_choose_req_cmd_ready $0\sdram_choose_req_cmd_ready[0:0] update \sdram_steerer_sel $0\sdram_steerer_sel[1:0] update \sdram_en0 $0\sdram_en0[0:0] update \sdram_en1 $0\sdram_en1[0:0] update \subfragments_multiplexer_next_state $0\subfragments_multiplexer_next_state[2:0] end attribute \src "ls180.v:269.5-269.31" process $proc$ls180.v:269$1643 assign { } { } assign $0\sdram_inti_p0_act_n[0:0] 1'1 sync always update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0] sync init end attribute \src "ls180.v:274.12-274.40" process $proc$ls180.v:274$1644 assign { } { } assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always sync init update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0] end attribute \src "ls180.v:275.5-275.38" process $proc$ls180.v:275$1645 assign { } { } assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0] end attribute \src "ls180.v:2754.1-2767.4" process $proc$ls180.v:2754$544 assign { } { } assign { } { } assign $0\sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\sdram_interface_wdata_we[1:0] 2'00 attribute \src "ls180.v:2757.2-2766.9" switch \subfragments_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\sdram_interface_wdata[15:0] \port_wdata_payload_data assign $0\sdram_interface_wdata_we[1:0] \port_wdata_payload_we attribute \src "ls180.v:0.0-0.0" case assign $0\sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\sdram_interface_wdata_we[1:0] 2'00 end sync always update \sdram_interface_wdata $0\sdram_interface_wdata[15:0] update \sdram_interface_wdata_we $0\sdram_interface_wdata_we[1:0] end attribute \src "ls180.v:2774.1-2784.4" process $proc$ls180.v:2774$546 assign { } { } assign $0\litedram_wb_dat_w[15:0] 16'0000000000000000 attribute \src "ls180.v:2776.2-2783.9" switch \converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\litedram_wb_dat_w[15:0] \wb_sdram_dat_w [15:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\litedram_wb_dat_w[15:0] \wb_sdram_dat_w [31:16] case end sync always update \litedram_wb_dat_w $0\litedram_wb_dat_w[15:0] end attribute \src "ls180.v:2786.1-2832.4" process $proc$ls180.v:2786$547 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\converter_counter_subfragments_next_value[0:0] 1'0 assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'0 assign $0\litedram_wb_we[0:0] 1'0 assign $0\converter_skip[0:0] 1'0 assign $0\wb_sdram_ack[0:0] 1'0 assign $0\litedram_wb_adr[29:0] 30'000000000000000000000000000000 assign $0\litedram_wb_sel[1:0] 2'00 assign $0\litedram_wb_cyc[0:0] 1'0 assign { } { } assign $0\litedram_wb_stb[0:0] 1'0 assign $0\subfragments_next_state[0:0] \subfragments_state attribute \src "ls180.v:2798.2-2831.9" switch \subfragments_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\litedram_wb_adr[29:0] { \wb_sdram_adr [28:0] \converter_counter } attribute \src "ls180.v:2801.4-2808.11" switch \converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [1:0] attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [3:2] case end attribute \src "ls180.v:2809.4-2822.7" switch $and$ls180.v:2809$548_Y attribute \src "ls180.v:2809.8-2809.37" case 1'1 assign $0\converter_skip[0:0] $eq$ls180.v:2810$549_Y assign $0\litedram_wb_we[0:0] \wb_sdram_we assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2812$550_Y assign $0\litedram_wb_stb[0:0] $not$ls180.v:2813$551_Y attribute \src "ls180.v:2814.5-2821.8" switch $or$ls180.v:2814$552_Y attribute \src "ls180.v:2814.9-2814.43" case 1'1 assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2815$553_Y assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 attribute \src "ls180.v:2817.6-2820.9" switch $eq$ls180.v:2817$554_Y attribute \src "ls180.v:2817.10-2817.37" case 1'1 assign $0\wb_sdram_ack[0:0] 1'1 assign $0\subfragments_next_state[0:0] 1'0 case end case end case end attribute \src "ls180.v:0.0-0.0" case assign $0\converter_counter_subfragments_next_value[0:0] 1'0 assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 attribute \src "ls180.v:2827.4-2829.7" switch $and$ls180.v:2827$555_Y attribute \src "ls180.v:2827.8-2827.37" case 1'1 assign $0\subfragments_next_state[0:0] 1'1 case end end sync always update \wb_sdram_ack $0\wb_sdram_ack[0:0] update \litedram_wb_adr $0\litedram_wb_adr[29:0] update \litedram_wb_sel $0\litedram_wb_sel[1:0] update \litedram_wb_cyc $0\litedram_wb_cyc[0:0] update \litedram_wb_stb $0\litedram_wb_stb[0:0] update \litedram_wb_we $0\litedram_wb_we[0:0] update \converter_skip $0\converter_skip[0:0] update \subfragments_next_state $0\subfragments_next_state[0:0] update \converter_counter_subfragments_next_value $0\converter_counter_subfragments_next_value[0:0] update \converter_counter_subfragments_next_value_ce $0\converter_counter_subfragments_next_value_ce[0:0] end attribute \src "ls180.v:2877.1-2882.4" process $proc$ls180.v:2877$587 assign { } { } assign $0\tx_clear[0:0] 1'0 attribute \src "ls180.v:2879.2-2881.5" switch $and$ls180.v:2879$588_Y attribute \src "ls180.v:2879.6-2879.59" case 1'1 assign $0\tx_clear[0:0] 1'1 case end sync always update \tx_clear $0\tx_clear[0:0] end attribute \src "ls180.v:2883.1-2887.4" process $proc$ls180.v:2883$589 assign { } { } assign { } { } assign $0\eventmanager_status_w[1:0] [0] \tx_status assign $0\eventmanager_status_w[1:0] [1] \rx_status sync always update \eventmanager_status_w $0\eventmanager_status_w[1:0] end attribute \src "ls180.v:2888.1-2893.4" process $proc$ls180.v:2888$590 assign { } { } assign $0\rx_clear[0:0] 1'0 attribute \src "ls180.v:2890.2-2892.5" switch $and$ls180.v:2890$591_Y attribute \src "ls180.v:2890.6-2890.59" case 1'1 assign $0\rx_clear[0:0] 1'1 case end sync always update \rx_clear $0\rx_clear[0:0] end attribute \src "ls180.v:2894.1-2898.4" process $proc$ls180.v:2894$592 assign { } { } assign { } { } assign $0\eventmanager_pending_w[1:0] [0] \tx_pending assign $0\eventmanager_pending_w[1:0] [1] \rx_pending sync always update \eventmanager_pending_w $0\eventmanager_pending_w[1:0] end attribute \src "ls180.v:290.12-290.41" process $proc$ls180.v:290$1646 assign { } { } assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always sync init update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0] end attribute \src "ls180.v:291.5-291.39" process $proc$ls180.v:291$1647 assign { } { } assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0] end attribute \src "ls180.v:2916.1-2923.4" process $proc$ls180.v:2916$600 assign { } { } assign $0\tx_fifo_wrport_adr[3:0] 4'0000 attribute \src "ls180.v:2918.2-2922.5" switch \tx_fifo_replace attribute \src "ls180.v:2918.6-2918.21" case 1'1 assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2919$601_Y attribute \src "ls180.v:2920.6-2920.10" case assign $0\tx_fifo_wrport_adr[3:0] \tx_fifo_produce end sync always update \tx_fifo_wrport_adr $0\tx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:292.12-292.43" process $proc$ls180.v:292$1648 assign { } { } assign $1\sdram_master_p0_address[12:0] 13'0000000000000 sync always sync init update \sdram_master_p0_address $1\sdram_master_p0_address[12:0] end attribute \src "ls180.v:293.11-293.38" process $proc$ls180.v:293$1649 assign { } { } assign $1\sdram_master_p0_bank[1:0] 2'00 sync always sync init update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0] end attribute \src "ls180.v:294.5-294.33" process $proc$ls180.v:294$1650 assign { } { } assign $1\sdram_master_p0_cas_n[0:0] 1'1 sync always sync init update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0] end attribute \src "ls180.v:2946.1-2953.4" process $proc$ls180.v:2946$611 assign { } { } assign $0\rx_fifo_wrport_adr[3:0] 4'0000 attribute \src "ls180.v:2948.2-2952.5" switch \rx_fifo_replace attribute \src "ls180.v:2948.6-2948.21" case 1'1 assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2949$612_Y attribute \src "ls180.v:2950.6-2950.10" case assign $0\rx_fifo_wrport_adr[3:0] \rx_fifo_produce end sync always update \rx_fifo_wrport_adr $0\rx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:295.5-295.32" process $proc$ls180.v:295$1651 assign { } { } assign $1\sdram_master_p0_cs_n[0:0] 1'1 sync always sync init update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0] end attribute \src "ls180.v:296.5-296.33" process $proc$ls180.v:296$1652 assign { } { } assign $1\sdram_master_p0_ras_n[0:0] 1'1 sync always sync init update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0] end attribute \src "ls180.v:2962.1-2972.4" process $proc$ls180.v:2962$618 assign { } { } assign { } { } assign $0\gpio0_pads_gpio0i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [0] assign $0\gpio0_pads_gpio0i[7:0] [1] \libresocsim_libresoc_constraintmanager_gpio_i [1] assign $0\gpio0_pads_gpio0i[7:0] [2] \libresocsim_libresoc_constraintmanager_gpio_i [2] assign $0\gpio0_pads_gpio0i[7:0] [3] \libresocsim_libresoc_constraintmanager_gpio_i [3] assign $0\gpio0_pads_gpio0i[7:0] [4] \libresocsim_libresoc_constraintmanager_gpio_i [4] assign $0\gpio0_pads_gpio0i[7:0] [5] \libresocsim_libresoc_constraintmanager_gpio_i [5] assign $0\gpio0_pads_gpio0i[7:0] [6] \libresocsim_libresoc_constraintmanager_gpio_i [6] assign $0\gpio0_pads_gpio0i[7:0] [7] \libresocsim_libresoc_constraintmanager_gpio_i [7] sync always update \gpio0_pads_gpio0i $0\gpio0_pads_gpio0i[7:0] end attribute \src "ls180.v:297.5-297.32" process $proc$ls180.v:297$1653 assign { } { } assign $1\sdram_master_p0_we_n[0:0] 1'1 sync always sync init update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0] end attribute \src "ls180.v:2973.1-2983.4" process $proc$ls180.v:2973$619 assign { } { } assign { } { } assign $0\gpio1_pads_gpio1i[7:0] [0] \libresocsim_libresoc_constraintmanager_gpio_i [8] assign $0\gpio1_pads_gpio1i[7:0] [1] \libresocsim_libresoc_constraintmanager_gpio_i [9] assign $0\gpio1_pads_gpio1i[7:0] [2] \libresocsim_libresoc_constraintmanager_gpio_i [10] assign $0\gpio1_pads_gpio1i[7:0] [3] \libresocsim_libresoc_constraintmanager_gpio_i [11] assign $0\gpio1_pads_gpio1i[7:0] [4] \libresocsim_libresoc_constraintmanager_gpio_i [12] assign $0\gpio1_pads_gpio1i[7:0] [5] \libresocsim_libresoc_constraintmanager_gpio_i [13] assign $0\gpio1_pads_gpio1i[7:0] [6] \libresocsim_libresoc_constraintmanager_gpio_i [14] assign $0\gpio1_pads_gpio1i[7:0] [7] \libresocsim_libresoc_constraintmanager_gpio_i [15] sync always update \gpio1_pads_gpio1i $0\gpio1_pads_gpio1i[7:0] end attribute \src "ls180.v:298.5-298.31" process $proc$ls180.v:298$1654 assign { } { } assign $1\sdram_master_p0_cke[0:0] 1'0 sync always sync init update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0] end attribute \src "ls180.v:2984.1-3002.4" process $proc$ls180.v:2984$620 assign { } { } assign { } { } assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [0] \gpio0_pads_gpio0o [0] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [1] \gpio0_pads_gpio0o [1] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [2] \gpio0_pads_gpio0o [2] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [3] \gpio0_pads_gpio0o [3] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [4] \gpio0_pads_gpio0o [4] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [5] \gpio0_pads_gpio0o [5] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [6] \gpio0_pads_gpio0o [6] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [7] \gpio0_pads_gpio0o [7] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [8] \gpio1_pads_gpio1o [0] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [9] \gpio1_pads_gpio1o [1] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [10] \gpio1_pads_gpio1o [2] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [11] \gpio1_pads_gpio1o [3] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [12] \gpio1_pads_gpio1o [4] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [13] \gpio1_pads_gpio1o [5] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [14] \gpio1_pads_gpio1o [6] assign $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] [15] \gpio1_pads_gpio1o [7] sync always update \libresocsim_libresoc_constraintmanager_gpio_o $0\libresocsim_libresoc_constraintmanager_gpio_o[15:0] end attribute \src "ls180.v:299.5-299.31" process $proc$ls180.v:299$1655 assign { } { } assign $1\sdram_master_p0_odt[0:0] 1'0 sync always sync init update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0] end attribute \src "ls180.v:300.5-300.35" process $proc$ls180.v:300$1656 assign { } { } assign $1\sdram_master_p0_reset_n[0:0] 1'0 sync always sync init update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0] end attribute \src "ls180.v:3003.1-3021.4" process $proc$ls180.v:3003$621 assign { } { } assign { } { } assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [0] \gpio0_pads_gpio0oe [0] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [1] \gpio0_pads_gpio0oe [1] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [2] \gpio0_pads_gpio0oe [2] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [3] \gpio0_pads_gpio0oe [3] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [4] \gpio0_pads_gpio0oe [4] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [5] \gpio0_pads_gpio0oe [5] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [6] \gpio0_pads_gpio0oe [6] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [7] \gpio0_pads_gpio0oe [7] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [8] \gpio1_pads_gpio1oe [0] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [9] \gpio1_pads_gpio1oe [1] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [10] \gpio1_pads_gpio1oe [2] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [11] \gpio1_pads_gpio1oe [3] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [12] \gpio1_pads_gpio1oe [4] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [13] \gpio1_pads_gpio1oe [5] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [14] \gpio1_pads_gpio1oe [6] assign $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] [15] \gpio1_pads_gpio1oe [7] sync always update \libresocsim_libresoc_constraintmanager_gpio_oe $0\libresocsim_libresoc_constraintmanager_gpio_oe[15:0] end attribute \src "ls180.v:301.5-301.33" process $proc$ls180.v:301$1657 assign { } { } assign $1\sdram_master_p0_act_n[0:0] 1'1 sync always sync init update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0] end attribute \src "ls180.v:302.12-302.42" process $proc$ls180.v:302$1658 assign { } { } assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always sync init update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0] end attribute \src "ls180.v:3026.1-3062.4" process $proc$ls180.v:3026$622 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'0 assign { } { } assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 assign $0\libresocsim_next_state[1:0] \libresocsim_state attribute \src "ls180.v:3037.2-3061.9" switch \libresocsim_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1 assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1 assign $0\libresocsim_next_state[1:0] 2'10 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'1 assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \libresocsim_libresocsim_dat_r } assign $0\libresocsim_next_state[1:0] 2'00 attribute \src "ls180.v:0.0-0.0" case assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] \libresocsim_libresocsim_wishbone_dat_w [7:0] assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'1 attribute \src "ls180.v:3053.4-3059.7" switch $and$ls180.v:3053$623_Y attribute \src "ls180.v:3053.8-3053.85" case 1'1 assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] \libresocsim_libresocsim_wishbone_adr [13:0] assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1 assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3056$625_Y assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1 assign $0\libresocsim_next_state[1:0] 2'01 case end end sync always update \libresocsim_libresocsim_wishbone_dat_r $0\libresocsim_libresocsim_wishbone_dat_r[31:0] update \libresocsim_libresocsim_wishbone_ack $0\libresocsim_libresocsim_wishbone_ack[0:0] update \libresocsim_next_state $0\libresocsim_next_state[1:0] update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] update \libresocsim_libresocsim_adr_libresocsim_next_value1 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] update \libresocsim_libresocsim_we_libresocsim_next_value2 $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end attribute \src "ls180.v:303.5-303.37" process $proc$ls180.v:303$1659 assign { } { } assign $1\sdram_master_p0_wrdata_en[0:0] 1'0 sync always sync init update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0] end attribute \src "ls180.v:304.11-304.45" process $proc$ls180.v:304$1660 assign { } { } assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00 sync always sync init update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0] end attribute \src "ls180.v:305.5-305.37" process $proc$ls180.v:305$1661 assign { } { } assign $1\sdram_master_p0_rddata_en[0:0] 1'0 sync always sync init update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0] end attribute \src "ls180.v:3081.1-3089.4" process $proc$ls180.v:3081$638 assign { } { } assign { } { } assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3083$639_Y assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3084$640_Y assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3085$641_Y assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3086$642_Y assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3087$643_Y assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3088$644_Y sync always update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0] end attribute \src "ls180.v:312.11-312.31" process $proc$ls180.v:312$1662 assign { } { } assign $1\sdram_storage[3:0] 4'0001 sync always sync init update \sdram_storage $1\sdram_storage[3:0] end attribute \src "ls180.v:313.5-313.20" process $proc$ls180.v:313$1663 assign { } { } assign $1\sdram_re[0:0] 1'0 sync always sync init update \sdram_re $1\sdram_re[0:0] end attribute \src "ls180.v:314.11-314.39" process $proc$ls180.v:314$1664 assign { } { } assign $1\sdram_command_storage[5:0] 6'000000 sync always sync init update \sdram_command_storage $1\sdram_command_storage[5:0] end attribute \src "ls180.v:3140.1-3151.4" process $proc$ls180.v:3140$659 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\libresocsim_error[0:0] 1'0 assign { } { } assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3144$664_Y assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3145$675_Y attribute \src "ls180.v:3146.2-3150.5" switch \libresocsim_done attribute \src "ls180.v:3146.6-3146.22" case 1'1 assign $0\libresocsim_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\libresocsim_shared_ack[0:0] 1'1 assign $0\libresocsim_error[0:0] 1'1 case end sync always update \libresocsim_shared_dat_r $0\libresocsim_shared_dat_r[31:0] update \libresocsim_shared_ack $0\libresocsim_shared_ack[0:0] update \libresocsim_error $0\libresocsim_error[0:0] end attribute \src "ls180.v:315.5-315.28" process $proc$ls180.v:315$1665 assign { } { } assign $1\sdram_command_re[0:0] 1'0 sync always sync init update \sdram_command_re $1\sdram_command_re[0:0] end attribute \src "ls180.v:319.5-319.33" process $proc$ls180.v:319$1666 assign { } { } assign $0\sdram_command_issue_w[0:0] 1'0 sync always update \sdram_command_issue_w $0\sdram_command_issue_w[0:0] sync init end attribute \src "ls180.v:320.12-320.41" process $proc$ls180.v:320$1667 assign { } { } assign $1\sdram_address_storage[12:0] 13'0000000000000 sync always sync init update \sdram_address_storage $1\sdram_address_storage[12:0] end attribute \src "ls180.v:321.5-321.28" process $proc$ls180.v:321$1668 assign { } { } assign $1\sdram_address_re[0:0] 1'0 sync always sync init update \sdram_address_re $1\sdram_address_re[0:0] end attribute \src "ls180.v:322.11-322.40" process $proc$ls180.v:322$1669 assign { } { } assign $1\sdram_baddress_storage[1:0] 2'00 sync always sync init update \sdram_baddress_storage $1\sdram_baddress_storage[1:0] end attribute \src "ls180.v:323.5-323.29" process $proc$ls180.v:323$1670 assign { } { } assign $1\sdram_baddress_re[0:0] 1'0 sync always sync init update \sdram_baddress_re $1\sdram_baddress_re[0:0] end attribute \src "ls180.v:324.12-324.40" process $proc$ls180.v:324$1671 assign { } { } assign $1\sdram_wrdata_storage[15:0] 16'0000000000000000 sync always sync init update \sdram_wrdata_storage $1\sdram_wrdata_storage[15:0] end attribute \src "ls180.v:325.5-325.27" process $proc$ls180.v:325$1672 assign { } { } assign $1\sdram_wrdata_re[0:0] 1'0 sync always sync init update \sdram_wrdata_re $1\sdram_wrdata_re[0:0] end attribute \src "ls180.v:326.12-326.32" process $proc$ls180.v:326$1673 assign { } { } assign $1\sdram_status[15:0] 16'0000000000000000 sync always sync init update \sdram_status $1\sdram_status[15:0] end attribute \src "ls180.v:3426.1-3442.4" process $proc$ls180.v:3426$1084 assign { } { } assign $0\rhs_array_muxed0[0:0] 1'0 attribute \src "ls180.v:3428.2-3441.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [0] attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [1] attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [2] attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [3] end sync always update \rhs_array_muxed0 $0\rhs_array_muxed0[0:0] end attribute \src "ls180.v:3443.1-3459.4" process $proc$ls180.v:3443$1085 assign { } { } assign $0\rhs_array_muxed1[12:0] 13'0000000000000 attribute \src "ls180.v:3445.2-3458.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine0_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine1_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine2_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine3_cmd_payload_a end sync always update \rhs_array_muxed1 $0\rhs_array_muxed1[12:0] end attribute \src "ls180.v:3460.1-3476.4" process $proc$ls180.v:3460$1086 assign { } { } assign $0\rhs_array_muxed2[1:0] 2'00 attribute \src "ls180.v:3462.2-3475.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine0_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine1_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine2_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine3_cmd_payload_ba end sync always update \rhs_array_muxed2 $0\rhs_array_muxed2[1:0] end attribute \src "ls180.v:3477.1-3493.4" process $proc$ls180.v:3477$1087 assign { } { } assign $0\rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:3479.2-3492.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine0_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine3_cmd_payload_is_read end sync always update \rhs_array_muxed3 $0\rhs_array_muxed3[0:0] end attribute \src "ls180.v:3494.1-3510.4" process $proc$ls180.v:3494$1088 assign { } { } assign $0\rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:3496.2-3509.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine0_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine1_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine2_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine3_cmd_payload_is_write end sync always update \rhs_array_muxed4 $0\rhs_array_muxed4[0:0] end attribute \src "ls180.v:3511.1-3527.4" process $proc$ls180.v:3511$1089 assign { } { } assign $0\rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:3513.2-3526.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine0_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine1_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine2_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine3_cmd_payload_is_cmd end sync always update \rhs_array_muxed5 $0\rhs_array_muxed5[0:0] end attribute \src "ls180.v:3528.1-3544.4" process $proc$ls180.v:3528$1090 assign { } { } assign $0\t_array_muxed0[0:0] 1'0 attribute \src "ls180.v:3530.2-3543.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\t_array_muxed0[0:0] \sdram_bankmachine0_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\t_array_muxed0[0:0] \sdram_bankmachine1_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\t_array_muxed0[0:0] \sdram_bankmachine2_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case assign $0\t_array_muxed0[0:0] \sdram_bankmachine3_cmd_payload_cas end sync always update \t_array_muxed0 $0\t_array_muxed0[0:0] end attribute \src "ls180.v:3545.1-3561.4" process $proc$ls180.v:3545$1091 assign { } { } assign $0\t_array_muxed1[0:0] 1'0 attribute \src "ls180.v:3547.2-3560.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\t_array_muxed1[0:0] \sdram_bankmachine0_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\t_array_muxed1[0:0] \sdram_bankmachine1_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\t_array_muxed1[0:0] \sdram_bankmachine2_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case assign $0\t_array_muxed1[0:0] \sdram_bankmachine3_cmd_payload_ras end sync always update \t_array_muxed1 $0\t_array_muxed1[0:0] end attribute \src "ls180.v:356.12-356.41" process $proc$ls180.v:356$1674 assign { } { } assign $1\sdram_interface_wdata[15:0] 16'0000000000000000 sync always sync init update \sdram_interface_wdata $1\sdram_interface_wdata[15:0] end attribute \src "ls180.v:3562.1-3578.4" process $proc$ls180.v:3562$1092 assign { } { } assign $0\t_array_muxed2[0:0] 1'0 attribute \src "ls180.v:3564.2-3577.9" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\t_array_muxed2[0:0] \sdram_bankmachine0_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\t_array_muxed2[0:0] \sdram_bankmachine1_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\t_array_muxed2[0:0] \sdram_bankmachine2_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case assign $0\t_array_muxed2[0:0] \sdram_bankmachine3_cmd_payload_we end sync always update \t_array_muxed2 $0\t_array_muxed2[0:0] end attribute \src "ls180.v:357.11-357.42" process $proc$ls180.v:357$1675 assign { } { } assign $1\sdram_interface_wdata_we[1:0] 2'00 sync always sync init update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0] end attribute \src "ls180.v:3579.1-3595.4" process $proc$ls180.v:3579$1093 assign { } { } assign $0\rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:3581.2-3594.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [0] attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [1] attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [2] attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [3] end sync always update \rhs_array_muxed6 $0\rhs_array_muxed6[0:0] end attribute \src "ls180.v:359.12-359.40" process $proc$ls180.v:359$1676 assign { } { } assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000 sync always sync init update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0] end attribute \src "ls180.v:3596.1-3612.4" process $proc$ls180.v:3596$1094 assign { } { } assign $0\rhs_array_muxed7[12:0] 13'0000000000000 attribute \src "ls180.v:3598.2-3611.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine0_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine1_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine2_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine3_cmd_payload_a end sync always update \rhs_array_muxed7 $0\rhs_array_muxed7[12:0] end attribute \src "ls180.v:360.11-360.35" process $proc$ls180.v:360$1677 assign { } { } assign $1\sdram_dfi_p0_bank[1:0] 2'00 sync always sync init update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0] end attribute \src "ls180.v:361.5-361.30" process $proc$ls180.v:361$1678 assign { } { } assign $1\sdram_dfi_p0_cas_n[0:0] 1'1 sync always sync init update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0] end attribute \src "ls180.v:3613.1-3629.4" process $proc$ls180.v:3613$1095 assign { } { } assign $0\rhs_array_muxed8[1:0] 2'00 attribute \src "ls180.v:3615.2-3628.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine0_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine1_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine2_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine3_cmd_payload_ba end sync always update \rhs_array_muxed8 $0\rhs_array_muxed8[1:0] end attribute \src "ls180.v:362.5-362.29" process $proc$ls180.v:362$1679 assign { } { } assign $1\sdram_dfi_p0_cs_n[0:0] 1'1 sync always sync init update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0] end attribute \src "ls180.v:363.5-363.30" process $proc$ls180.v:363$1680 assign { } { } assign $1\sdram_dfi_p0_ras_n[0:0] 1'1 sync always sync init update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0] end attribute \src "ls180.v:3630.1-3646.4" process $proc$ls180.v:3630$1096 assign { } { } assign $0\rhs_array_muxed9[0:0] 1'0 attribute \src "ls180.v:3632.2-3645.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine0_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine3_cmd_payload_is_read end sync always update \rhs_array_muxed9 $0\rhs_array_muxed9[0:0] end attribute \src "ls180.v:364.5-364.29" process $proc$ls180.v:364$1681 assign { } { } assign $1\sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0] end attribute \src "ls180.v:3647.1-3663.4" process $proc$ls180.v:3647$1097 assign { } { } assign $0\rhs_array_muxed10[0:0] 1'0 attribute \src "ls180.v:3649.2-3662.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine0_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine1_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine2_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine3_cmd_payload_is_write end sync always update \rhs_array_muxed10 $0\rhs_array_muxed10[0:0] end attribute \src "ls180.v:3664.1-3680.4" process $proc$ls180.v:3664$1098 assign { } { } assign $0\rhs_array_muxed11[0:0] 1'0 attribute \src "ls180.v:3666.2-3679.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine0_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine1_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine2_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine3_cmd_payload_is_cmd end sync always update \rhs_array_muxed11 $0\rhs_array_muxed11[0:0] end attribute \src "ls180.v:368.5-368.30" process $proc$ls180.v:368$1682 assign { } { } assign $0\sdram_dfi_p0_act_n[0:0] 1'1 sync always update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0] sync init end attribute \src "ls180.v:3681.1-3697.4" process $proc$ls180.v:3681$1099 assign { } { } assign $0\t_array_muxed3[0:0] 1'0 attribute \src "ls180.v:3683.2-3696.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\t_array_muxed3[0:0] \sdram_bankmachine0_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\t_array_muxed3[0:0] \sdram_bankmachine1_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\t_array_muxed3[0:0] \sdram_bankmachine2_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case assign $0\t_array_muxed3[0:0] \sdram_bankmachine3_cmd_payload_cas end sync always update \t_array_muxed3 $0\t_array_muxed3[0:0] end attribute \src "ls180.v:3698.1-3714.4" process $proc$ls180.v:3698$1100 assign { } { } assign $0\t_array_muxed4[0:0] 1'0 attribute \src "ls180.v:3700.2-3713.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\t_array_muxed4[0:0] \sdram_bankmachine0_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\t_array_muxed4[0:0] \sdram_bankmachine1_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\t_array_muxed4[0:0] \sdram_bankmachine2_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case assign $0\t_array_muxed4[0:0] \sdram_bankmachine3_cmd_payload_ras end sync always update \t_array_muxed4 $0\t_array_muxed4[0:0] end attribute \src "ls180.v:370.5-370.34" process $proc$ls180.v:370$1683 assign { } { } assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0] end attribute \src "ls180.v:3715.1-3731.4" process $proc$ls180.v:3715$1101 assign { } { } assign $0\t_array_muxed5[0:0] 1'0 attribute \src "ls180.v:3717.2-3730.9" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\t_array_muxed5[0:0] \sdram_bankmachine0_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\t_array_muxed5[0:0] \sdram_bankmachine1_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\t_array_muxed5[0:0] \sdram_bankmachine2_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case assign $0\t_array_muxed5[0:0] \sdram_bankmachine3_cmd_payload_we end sync always update \t_array_muxed5 $0\t_array_muxed5[0:0] end attribute \src "ls180.v:372.5-372.34" process $proc$ls180.v:372$1684 assign { } { } assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0 sync always sync init update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0] end attribute \src "ls180.v:3732.1-3739.4" process $proc$ls180.v:3732$1102 assign { } { } assign $0\rhs_array_muxed12[21:0] 22'0000000000000000000000 attribute \src "ls180.v:3734.2-3738.9" switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed12[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always update \rhs_array_muxed12 $0\rhs_array_muxed12[21:0] end attribute \src "ls180.v:3740.1-3747.4" process $proc$ls180.v:3740$1103 assign { } { } assign $0\rhs_array_muxed13[0:0] 1'0 attribute \src "ls180.v:3742.2-3746.9" switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed13[0:0] \port_cmd_payload_we end sync always update \rhs_array_muxed13 $0\rhs_array_muxed13[0:0] end attribute \src "ls180.v:3748.1-3755.4" process $proc$ls180.v:3748$1104 assign { } { } assign $0\rhs_array_muxed14[0:0] 1'0 attribute \src "ls180.v:3750.2-3754.9" switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3752$1117_Y end sync always update \rhs_array_muxed14 $0\rhs_array_muxed14[0:0] end attribute \src "ls180.v:375.5-375.27" process $proc$ls180.v:375$1685 assign { } { } assign $1\sdram_cmd_valid[0:0] 1'0 sync always sync init update \sdram_cmd_valid $1\sdram_cmd_valid[0:0] end attribute \src "ls180.v:3756.1-3763.4" process $proc$ls180.v:3756$1118 assign { } { } assign $0\rhs_array_muxed15[21:0] 22'0000000000000000000000 attribute \src "ls180.v:3758.2-3762.9" switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed15[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always update \rhs_array_muxed15 $0\rhs_array_muxed15[21:0] end attribute \src "ls180.v:376.5-376.27" process $proc$ls180.v:376$1686 assign { } { } assign $1\sdram_cmd_ready[0:0] 1'0 sync always sync init update \sdram_cmd_ready $1\sdram_cmd_ready[0:0] end attribute \src "ls180.v:3764.1-3771.4" process $proc$ls180.v:3764$1119 assign { } { } assign $0\rhs_array_muxed16[0:0] 1'0 attribute \src "ls180.v:3766.2-3770.9" switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed16[0:0] \port_cmd_payload_we end sync always update \rhs_array_muxed16 $0\rhs_array_muxed16[0:0] end attribute \src "ls180.v:377.5-377.26" process $proc$ls180.v:377$1687 assign { } { } assign $1\sdram_cmd_last[0:0] 1'0 sync always sync init update \sdram_cmd_last $1\sdram_cmd_last[0:0] end attribute \src "ls180.v:3772.1-3779.4" process $proc$ls180.v:3772$1120 assign { } { } assign $0\rhs_array_muxed17[0:0] 1'0 attribute \src "ls180.v:3774.2-3778.9" switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3776$1133_Y end sync always update \rhs_array_muxed17 $0\rhs_array_muxed17[0:0] end attribute \src "ls180.v:378.12-378.39" process $proc$ls180.v:378$1688 assign { } { } assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0] end attribute \src "ls180.v:3780.1-3787.4" process $proc$ls180.v:3780$1134 assign { } { } assign $0\rhs_array_muxed18[21:0] 22'0000000000000000000000 attribute \src "ls180.v:3782.2-3786.9" switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed18[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always update \rhs_array_muxed18 $0\rhs_array_muxed18[21:0] end attribute \src "ls180.v:3788.1-3795.4" process $proc$ls180.v:3788$1135 assign { } { } assign $0\rhs_array_muxed19[0:0] 1'0 attribute \src "ls180.v:3790.2-3794.9" switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed19[0:0] \port_cmd_payload_we end sync always update \rhs_array_muxed19 $0\rhs_array_muxed19[0:0] end attribute \src "ls180.v:379.11-379.38" process $proc$ls180.v:379$1689 assign { } { } assign $1\sdram_cmd_payload_ba[1:0] 2'00 sync always sync init update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0] end attribute \src "ls180.v:3796.1-3803.4" process $proc$ls180.v:3796$1136 assign { } { } assign $0\rhs_array_muxed20[0:0] 1'0 attribute \src "ls180.v:3798.2-3802.9" switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3800$1149_Y end sync always update \rhs_array_muxed20 $0\rhs_array_muxed20[0:0] end attribute \src "ls180.v:380.5-380.33" process $proc$ls180.v:380$1690 assign { } { } assign $1\sdram_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0] end attribute \src "ls180.v:3804.1-3811.4" process $proc$ls180.v:3804$1150 assign { } { } assign $0\rhs_array_muxed21[21:0] 22'0000000000000000000000 attribute \src "ls180.v:3806.2-3810.9" switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed21[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always update \rhs_array_muxed21 $0\rhs_array_muxed21[21:0] end attribute \src "ls180.v:381.5-381.33" process $proc$ls180.v:381$1691 assign { } { } assign $1\sdram_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0] end attribute \src "ls180.v:3812.1-3819.4" process $proc$ls180.v:3812$1151 assign { } { } assign $0\rhs_array_muxed22[0:0] 1'0 attribute \src "ls180.v:3814.2-3818.9" switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed22[0:0] \port_cmd_payload_we end sync always update \rhs_array_muxed22 $0\rhs_array_muxed22[0:0] end attribute \src "ls180.v:382.5-382.32" process $proc$ls180.v:382$1692 assign { } { } assign $1\sdram_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0] end attribute \src "ls180.v:3820.1-3827.4" process $proc$ls180.v:3820$1152 assign { } { } assign $0\rhs_array_muxed23[0:0] 1'0 attribute \src "ls180.v:3822.2-3826.9" switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3824$1165_Y end sync always update \rhs_array_muxed23 $0\rhs_array_muxed23[0:0] end attribute \src "ls180.v:3828.1-3841.4" process $proc$ls180.v:3828$1166 assign { } { } assign $0\rhs_array_muxed24[29:0] 30'000000000000000000000000000000 attribute \src "ls180.v:3830.2-3840.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed24[29:0] \libresocsim_interface0_converted_interface_adr attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed24[29:0] \libresocsim_interface1_converted_interface_adr attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed24[29:0] \libresocsim_interface2_converted_interface_adr end sync always update \rhs_array_muxed24 $0\rhs_array_muxed24[29:0] end attribute \src "ls180.v:383.5-383.37" process $proc$ls180.v:383$1693 assign { } { } assign $0\sdram_cmd_payload_is_read[0:0] 1'0 sync always update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0] sync init end attribute \src "ls180.v:384.5-384.38" process $proc$ls180.v:384$1694 assign { } { } assign $0\sdram_cmd_payload_is_write[0:0] 1'0 sync always update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0] sync init end attribute \src "ls180.v:3842.1-3855.4" process $proc$ls180.v:3842$1167 assign { } { } assign $0\rhs_array_muxed25[31:0] 0 attribute \src "ls180.v:3844.2-3854.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed25[31:0] \libresocsim_interface0_converted_interface_dat_w attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed25[31:0] \libresocsim_interface1_converted_interface_dat_w attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed25[31:0] \libresocsim_interface2_converted_interface_dat_w end sync always update \rhs_array_muxed25 $0\rhs_array_muxed25[31:0] end attribute \src "ls180.v:3856.1-3869.4" process $proc$ls180.v:3856$1168 assign { } { } assign $0\rhs_array_muxed26[3:0] 4'0000 attribute \src "ls180.v:3858.2-3868.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed26[3:0] \libresocsim_interface0_converted_interface_sel attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed26[3:0] \libresocsim_interface1_converted_interface_sel attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed26[3:0] \libresocsim_interface2_converted_interface_sel end sync always update \rhs_array_muxed26 $0\rhs_array_muxed26[3:0] end attribute \src "ls180.v:3870.1-3883.4" process $proc$ls180.v:3870$1169 assign { } { } assign $0\rhs_array_muxed27[0:0] 1'0 attribute \src "ls180.v:3872.2-3882.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed27[0:0] \libresocsim_interface0_converted_interface_cyc attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed27[0:0] \libresocsim_interface1_converted_interface_cyc attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed27[0:0] \libresocsim_interface2_converted_interface_cyc end sync always update \rhs_array_muxed27 $0\rhs_array_muxed27[0:0] end attribute \src "ls180.v:3884.1-3897.4" process $proc$ls180.v:3884$1170 assign { } { } assign $0\rhs_array_muxed28[0:0] 1'0 attribute \src "ls180.v:3886.2-3896.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed28[0:0] \libresocsim_interface0_converted_interface_stb attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed28[0:0] \libresocsim_interface1_converted_interface_stb attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed28[0:0] \libresocsim_interface2_converted_interface_stb end sync always update \rhs_array_muxed28 $0\rhs_array_muxed28[0:0] end attribute \src "ls180.v:3898.1-3911.4" process $proc$ls180.v:3898$1171 assign { } { } assign $0\rhs_array_muxed29[0:0] 1'0 attribute \src "ls180.v:3900.2-3910.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed29[0:0] \libresocsim_interface0_converted_interface_we attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed29[0:0] \libresocsim_interface1_converted_interface_we attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed29[0:0] \libresocsim_interface2_converted_interface_we end sync always update \rhs_array_muxed29 $0\rhs_array_muxed29[0:0] end attribute \src "ls180.v:390.11-390.39" process $proc$ls180.v:390$1695 assign { } { } assign $1\sdram_timer_count1[9:0] 10'1100001101 sync always sync init update \sdram_timer_count1 $1\sdram_timer_count1[9:0] end attribute \src "ls180.v:3912.1-3925.4" process $proc$ls180.v:3912$1172 assign { } { } assign $0\rhs_array_muxed30[2:0] 3'000 attribute \src "ls180.v:3914.2-3924.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed30[2:0] \libresocsim_interface0_converted_interface_cti attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed30[2:0] \libresocsim_interface1_converted_interface_cti attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed30[2:0] \libresocsim_interface2_converted_interface_cti end sync always update \rhs_array_muxed30 $0\rhs_array_muxed30[2:0] end attribute \src "ls180.v:392.5-392.33" process $proc$ls180.v:392$1696 assign { } { } assign $1\sdram_postponer_req_o[0:0] 1'0 sync always sync init update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0] end attribute \src "ls180.v:3926.1-3939.4" process $proc$ls180.v:3926$1173 assign { } { } assign $0\rhs_array_muxed31[1:0] 2'00 attribute \src "ls180.v:3928.2-3938.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\rhs_array_muxed31[1:0] \libresocsim_interface0_converted_interface_bte attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\rhs_array_muxed31[1:0] \libresocsim_interface1_converted_interface_bte attribute \src "ls180.v:0.0-0.0" case assign $0\rhs_array_muxed31[1:0] \libresocsim_interface2_converted_interface_bte end sync always update \rhs_array_muxed31 $0\rhs_array_muxed31[1:0] end attribute \src "ls180.v:393.5-393.33" process $proc$ls180.v:393$1697 assign { } { } assign $1\sdram_postponer_count[0:0] 1'0 sync always sync init update \sdram_postponer_count $1\sdram_postponer_count[0:0] end attribute \src "ls180.v:394.5-394.34" process $proc$ls180.v:394$1698 assign { } { } assign $1\sdram_sequencer_start0[0:0] 1'0 sync always sync init update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0] end attribute \src "ls180.v:3940.1-3956.4" process $proc$ls180.v:3940$1174 assign { } { } assign $0\array_muxed0[1:0] 2'00 attribute \src "ls180.v:3942.2-3955.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed0[1:0] \sdram_nop_ba attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\array_muxed0[1:0] \sdram_choose_req_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\array_muxed0[1:0] \sdram_choose_req_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case assign $0\array_muxed0[1:0] \sdram_cmd_payload_ba end sync always update \array_muxed0 $0\array_muxed0[1:0] end attribute \src "ls180.v:3957.1-3973.4" process $proc$ls180.v:3957$1175 assign { } { } assign $0\array_muxed1[12:0] 13'0000000000000 attribute \src "ls180.v:3959.2-3972.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed1[12:0] \sdram_nop_a attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\array_muxed1[12:0] \sdram_choose_req_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\array_muxed1[12:0] \sdram_choose_req_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case assign $0\array_muxed1[12:0] \sdram_cmd_payload_a end sync always update \array_muxed1 $0\array_muxed1[12:0] end attribute \src "ls180.v:397.5-397.33" process $proc$ls180.v:397$1699 assign { } { } assign $1\sdram_sequencer_done1[0:0] 1'0 sync always sync init update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0] end attribute \src "ls180.v:3974.1-3990.4" process $proc$ls180.v:3974$1176 assign { } { } assign $0\array_muxed2[0:0] 1'0 attribute \src "ls180.v:3976.2-3989.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\array_muxed2[0:0] $and$ls180.v:3981$1178_Y attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\array_muxed2[0:0] $and$ls180.v:3984$1180_Y attribute \src "ls180.v:0.0-0.0" case assign $0\array_muxed2[0:0] $and$ls180.v:3987$1182_Y end sync always update \array_muxed2 $0\array_muxed2[0:0] end attribute \src "ls180.v:398.11-398.41" process $proc$ls180.v:398$1700 assign { } { } assign $1\sdram_sequencer_counter[3:0] 4'0000 sync always sync init update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0] end attribute \src "ls180.v:399.5-399.33" process $proc$ls180.v:399$1701 assign { } { } assign $1\sdram_sequencer_count[0:0] 1'0 sync always sync init update \sdram_sequencer_count $1\sdram_sequencer_count[0:0] end attribute \src "ls180.v:3991.1-4007.4" process $proc$ls180.v:3991$1183 assign { } { } assign $0\array_muxed3[0:0] 1'0 attribute \src "ls180.v:3993.2-4006.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\array_muxed3[0:0] $and$ls180.v:3998$1185_Y attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\array_muxed3[0:0] $and$ls180.v:4001$1187_Y attribute \src "ls180.v:0.0-0.0" case assign $0\array_muxed3[0:0] $and$ls180.v:4004$1189_Y end sync always update \array_muxed3 $0\array_muxed3[0:0] end attribute \src "ls180.v:4008.1-4024.4" process $proc$ls180.v:4008$1190 assign { } { } assign $0\array_muxed4[0:0] 1'0 attribute \src "ls180.v:4010.2-4023.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\array_muxed4[0:0] $and$ls180.v:4015$1192_Y attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\array_muxed4[0:0] $and$ls180.v:4018$1194_Y attribute \src "ls180.v:0.0-0.0" case assign $0\array_muxed4[0:0] $and$ls180.v:4021$1196_Y end sync always update \array_muxed4 $0\array_muxed4[0:0] end attribute \src "ls180.v:4025.1-4041.4" process $proc$ls180.v:4025$1197 assign { } { } assign $0\array_muxed5[0:0] 1'0 attribute \src "ls180.v:4027.2-4040.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\array_muxed5[0:0] $and$ls180.v:4032$1199_Y attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\array_muxed5[0:0] $and$ls180.v:4035$1201_Y attribute \src "ls180.v:0.0-0.0" case assign $0\array_muxed5[0:0] $and$ls180.v:4038$1203_Y end sync always update \array_muxed5 $0\array_muxed5[0:0] end attribute \src "ls180.v:4042.1-4058.4" process $proc$ls180.v:4042$1204 assign { } { } assign $0\array_muxed6[0:0] 1'0 attribute \src "ls180.v:4044.2-4057.9" switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\array_muxed6[0:0] $and$ls180.v:4049$1206_Y attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\array_muxed6[0:0] $and$ls180.v:4052$1208_Y attribute \src "ls180.v:0.0-0.0" case assign $0\array_muxed6[0:0] $and$ls180.v:4055$1210_Y end sync always update \array_muxed6 $0\array_muxed6[0:0] end attribute \src "ls180.v:405.5-405.46" process $proc$ls180.v:405$1702 assign { } { } assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0] end attribute \src "ls180.v:406.5-406.46" process $proc$ls180.v:406$1703 assign { } { } assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0] end attribute \src "ls180.v:408.5-408.42" process $proc$ls180.v:408$1704 assign { } { } assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0] end attribute \src "ls180.v:409.5-409.40" process $proc$ls180.v:409$1705 assign { } { } assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0] end attribute \src "ls180.v:410.5-410.40" process $proc$ls180.v:410$1706 assign { } { } assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0] end attribute \src "ls180.v:411.12-411.52" process $proc$ls180.v:411$1707 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0] end attribute \src "ls180.v:413.5-413.46" process $proc$ls180.v:413$1708 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0] end attribute \src "ls180.v:414.5-414.46" process $proc$ls180.v:414$1709 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0] end attribute \src "ls180.v:415.5-415.45" process $proc$ls180.v:415$1710 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0] end attribute \src "ls180.v:416.5-416.49" process $proc$ls180.v:416$1711 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:4165.1-4167.4" process $proc$ls180.v:4165$1211 assign { } { } assign $0\int_rst[0:0] \sys_rst sync posedge \por_clk update \int_rst $0\int_rst[0:0] end attribute \src "ls180.v:4169.1-4274.4" process $proc$ls180.v:4169$1212 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [0] \dfi_p0_address [0] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [1] \dfi_p0_address [1] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [2] \dfi_p0_address [2] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [3] \dfi_p0_address [3] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [4] \dfi_p0_address [4] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [5] \dfi_p0_address [5] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [6] \dfi_p0_address [6] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [7] \dfi_p0_address [7] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [8] \dfi_p0_address [8] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [9] \dfi_p0_address [9] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [10] \dfi_p0_address [10] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [11] \dfi_p0_address [11] assign $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] [12] \dfi_p0_address [12] assign $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] [0] \dfi_p0_bank [0] assign $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] [1] \dfi_p0_bank [1] assign $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] \dfi_p0_cas_n assign $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] \dfi_p0_ras_n assign $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] \dfi_p0_we_n assign $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] \dfi_p0_cke assign $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] \dfi_p0_cs_n assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] \dfi_p0_wrdata_en assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [0] \dfi_p0_wrdata [0] assign $0\dfi_p0_rddata[15:0] [0] \libresocsim_libresoc_constraintmanager_sdram_dq_i [0] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [1] \dfi_p0_wrdata [1] assign $0\dfi_p0_rddata[15:0] [1] \libresocsim_libresoc_constraintmanager_sdram_dq_i [1] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [2] \dfi_p0_wrdata [2] assign $0\dfi_p0_rddata[15:0] [2] \libresocsim_libresoc_constraintmanager_sdram_dq_i [2] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [3] \dfi_p0_wrdata [3] assign $0\dfi_p0_rddata[15:0] [3] \libresocsim_libresoc_constraintmanager_sdram_dq_i [3] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [4] \dfi_p0_wrdata [4] assign $0\dfi_p0_rddata[15:0] [4] \libresocsim_libresoc_constraintmanager_sdram_dq_i [4] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [5] \dfi_p0_wrdata [5] assign $0\dfi_p0_rddata[15:0] [5] \libresocsim_libresoc_constraintmanager_sdram_dq_i [5] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [6] \dfi_p0_wrdata [6] assign $0\dfi_p0_rddata[15:0] [6] \libresocsim_libresoc_constraintmanager_sdram_dq_i [6] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [7] \dfi_p0_wrdata [7] assign $0\dfi_p0_rddata[15:0] [7] \libresocsim_libresoc_constraintmanager_sdram_dq_i [7] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [8] \dfi_p0_wrdata [8] assign $0\dfi_p0_rddata[15:0] [8] \libresocsim_libresoc_constraintmanager_sdram_dq_i [8] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [9] \dfi_p0_wrdata [9] assign $0\dfi_p0_rddata[15:0] [9] \libresocsim_libresoc_constraintmanager_sdram_dq_i [9] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [10] \dfi_p0_wrdata [10] assign $0\dfi_p0_rddata[15:0] [10] \libresocsim_libresoc_constraintmanager_sdram_dq_i [10] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [11] \dfi_p0_wrdata [11] assign $0\dfi_p0_rddata[15:0] [11] \libresocsim_libresoc_constraintmanager_sdram_dq_i [11] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [12] \dfi_p0_wrdata [12] assign $0\dfi_p0_rddata[15:0] [12] \libresocsim_libresoc_constraintmanager_sdram_dq_i [12] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [13] \dfi_p0_wrdata [13] assign $0\dfi_p0_rddata[15:0] [13] \libresocsim_libresoc_constraintmanager_sdram_dq_i [13] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [14] \dfi_p0_wrdata [14] assign $0\dfi_p0_rddata[15:0] [14] \libresocsim_libresoc_constraintmanager_sdram_dq_i [14] assign $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] [15] \dfi_p0_wrdata [15] assign $0\dfi_p0_rddata[15:0] [15] \libresocsim_libresoc_constraintmanager_sdram_dq_i [15] assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [0] $and$ls180.v:4223$1213_Y assign $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] [1] $and$ls180.v:4224$1214_Y assign $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] \sys_clk_1 assign $0\gpio0_pads_gpio0oe[7:0] [0] \gpio0_oe_storage [0] assign $0\gpio0_pads_gpio0o[7:0] [0] \gpio0_out_storage [0] assign $0\gpio0_status[7:0] [0] \gpio0_pads_gpio0i [0] assign $0\gpio0_pads_gpio0oe[7:0] [1] \gpio0_oe_storage [1] assign $0\gpio0_pads_gpio0o[7:0] [1] \gpio0_out_storage [1] assign $0\gpio0_status[7:0] [1] \gpio0_pads_gpio0i [1] assign $0\gpio0_pads_gpio0oe[7:0] [2] \gpio0_oe_storage [2] assign $0\gpio0_pads_gpio0o[7:0] [2] \gpio0_out_storage [2] assign $0\gpio0_status[7:0] [2] \gpio0_pads_gpio0i [2] assign $0\gpio0_pads_gpio0oe[7:0] [3] \gpio0_oe_storage [3] assign $0\gpio0_pads_gpio0o[7:0] [3] \gpio0_out_storage [3] assign $0\gpio0_status[7:0] [3] \gpio0_pads_gpio0i [3] assign $0\gpio0_pads_gpio0oe[7:0] [4] \gpio0_oe_storage [4] assign $0\gpio0_pads_gpio0o[7:0] [4] \gpio0_out_storage [4] assign $0\gpio0_status[7:0] [4] \gpio0_pads_gpio0i [4] assign $0\gpio0_pads_gpio0oe[7:0] [5] \gpio0_oe_storage [5] assign $0\gpio0_pads_gpio0o[7:0] [5] \gpio0_out_storage [5] assign $0\gpio0_status[7:0] [5] \gpio0_pads_gpio0i [5] assign $0\gpio0_pads_gpio0oe[7:0] [6] \gpio0_oe_storage [6] assign $0\gpio0_pads_gpio0o[7:0] [6] \gpio0_out_storage [6] assign $0\gpio0_status[7:0] [6] \gpio0_pads_gpio0i [6] assign $0\gpio0_pads_gpio0oe[7:0] [7] \gpio0_oe_storage [7] assign $0\gpio0_pads_gpio0o[7:0] [7] \gpio0_out_storage [7] assign $0\gpio0_status[7:0] [7] \gpio0_pads_gpio0i [7] assign $0\gpio1_pads_gpio1oe[7:0] [0] \gpio1_oe_storage [0] assign $0\gpio1_pads_gpio1o[7:0] [0] \gpio1_out_storage [0] assign $0\gpio1_status[7:0] [0] \gpio1_pads_gpio1i [0] assign $0\gpio1_pads_gpio1oe[7:0] [1] \gpio1_oe_storage [1] assign $0\gpio1_pads_gpio1o[7:0] [1] \gpio1_out_storage [1] assign $0\gpio1_status[7:0] [1] \gpio1_pads_gpio1i [1] assign $0\gpio1_pads_gpio1oe[7:0] [2] \gpio1_oe_storage [2] assign $0\gpio1_pads_gpio1o[7:0] [2] \gpio1_out_storage [2] assign $0\gpio1_status[7:0] [2] \gpio1_pads_gpio1i [2] assign $0\gpio1_pads_gpio1oe[7:0] [3] \gpio1_oe_storage [3] assign $0\gpio1_pads_gpio1o[7:0] [3] \gpio1_out_storage [3] assign $0\gpio1_status[7:0] [3] \gpio1_pads_gpio1i [3] assign $0\gpio1_pads_gpio1oe[7:0] [4] \gpio1_oe_storage [4] assign $0\gpio1_pads_gpio1o[7:0] [4] \gpio1_out_storage [4] assign $0\gpio1_status[7:0] [4] \gpio1_pads_gpio1i [4] assign $0\gpio1_pads_gpio1oe[7:0] [5] \gpio1_oe_storage [5] assign $0\gpio1_pads_gpio1o[7:0] [5] \gpio1_out_storage [5] assign $0\gpio1_status[7:0] [5] \gpio1_pads_gpio1i [5] assign $0\gpio1_pads_gpio1oe[7:0] [6] \gpio1_oe_storage [6] assign $0\gpio1_pads_gpio1o[7:0] [6] \gpio1_out_storage [6] assign $0\gpio1_status[7:0] [6] \gpio1_pads_gpio1i [6] assign $0\gpio1_pads_gpio1oe[7:0] [7] \gpio1_oe_storage [7] assign $0\gpio1_pads_gpio1o[7:0] [7] \gpio1_out_storage [7] assign $0\gpio1_status[7:0] [7] \gpio1_pads_gpio1i [7] sync posedge \sdrio_clk update \libresocsim_libresoc_constraintmanager_sdram_a $0\libresocsim_libresoc_constraintmanager_sdram_a[12:0] update \libresocsim_libresoc_constraintmanager_sdram_dq_o $0\libresocsim_libresoc_constraintmanager_sdram_dq_o[15:0] update \libresocsim_libresoc_constraintmanager_sdram_dq_oe $0\libresocsim_libresoc_constraintmanager_sdram_dq_oe[0:0] update \libresocsim_libresoc_constraintmanager_sdram_we_n $0\libresocsim_libresoc_constraintmanager_sdram_we_n[0:0] update \libresocsim_libresoc_constraintmanager_sdram_ras_n $0\libresocsim_libresoc_constraintmanager_sdram_ras_n[0:0] update \libresocsim_libresoc_constraintmanager_sdram_cas_n $0\libresocsim_libresoc_constraintmanager_sdram_cas_n[0:0] update \libresocsim_libresoc_constraintmanager_sdram_cs_n $0\libresocsim_libresoc_constraintmanager_sdram_cs_n[0:0] update \libresocsim_libresoc_constraintmanager_sdram_cke $0\libresocsim_libresoc_constraintmanager_sdram_cke[0:0] update \libresocsim_libresoc_constraintmanager_sdram_ba $0\libresocsim_libresoc_constraintmanager_sdram_ba[1:0] update \libresocsim_libresoc_constraintmanager_sdram_dm $0\libresocsim_libresoc_constraintmanager_sdram_dm[1:0] update \libresocsim_libresoc_constraintmanager_sdram_clock $0\libresocsim_libresoc_constraintmanager_sdram_clock[0:0] update \dfi_p0_rddata $0\dfi_p0_rddata[15:0] update \gpio0_status $0\gpio0_status[7:0] update \gpio0_pads_gpio0o $0\gpio0_pads_gpio0o[7:0] update \gpio0_pads_gpio0oe $0\gpio0_pads_gpio0oe[7:0] update \gpio1_status $0\gpio1_status[7:0] update \gpio1_pads_gpio1o $0\gpio1_pads_gpio1o[7:0] update \gpio1_pads_gpio1oe $0\gpio1_pads_gpio1oe[7:0] end attribute \src "ls180.v:417.5-417.50" process $proc$ls180.v:417$1712 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_is_read $1\sdram_bankmachine0_cmd_payload_is_read[0:0] end attribute \src "ls180.v:418.5-418.51" process $proc$ls180.v:418$1713 assign { } { } assign $1\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_payload_is_write $1\sdram_bankmachine0_cmd_payload_is_write[0:0] end attribute \src "ls180.v:419.5-419.45" process $proc$ls180.v:419$1714 assign { } { } assign $1\sdram_bankmachine0_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine0_auto_precharge $1\sdram_bankmachine0_auto_precharge[0:0] end attribute \src "ls180.v:42.5-42.37" process $proc$ls180.v:42$1551 assign { } { } assign $1\libresocsim_reset_storage[0:0] 1'0 sync always sync init update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0] end attribute \src "ls180.v:422.5-422.62" process $proc$ls180.v:422$1715 assign { } { } assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init end attribute \src "ls180.v:423.5-423.61" process $proc$ls180.v:423$1716 assign { } { } assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init end attribute \src "ls180.v:4276.1-5486.4" process $proc$ls180.v:4276$1215 assign $0\libresocsim_reset_storage[0:0] \libresocsim_reset_storage assign { } { } assign $0\libresocsim_scratch_storage[31:0] \libresocsim_scratch_storage assign { } { } assign $0\libresocsim_bus_errors[31:0] \libresocsim_bus_errors assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \libresocsim_libresoc_constraintmanager_uart_tx assign $0\libresocsim_converter0_counter[0:0] \libresocsim_converter0_counter assign $0\libresocsim_converter0_dat_r[63:0] \libresocsim_converter0_dat_r assign $0\libresocsim_converter1_counter[0:0] \libresocsim_converter1_counter assign $0\libresocsim_converter1_dat_r[63:0] \libresocsim_converter1_dat_r assign $0\libresocsim_converter2_counter[0:0] \libresocsim_converter2_counter assign $0\libresocsim_converter2_dat_r[63:0] \libresocsim_converter2_dat_r assign { } { } assign $0\libresocsim_load_storage[31:0] \libresocsim_load_storage assign { } { } assign $0\libresocsim_reload_storage[31:0] \libresocsim_reload_storage assign { } { } assign $0\libresocsim_en_storage[0:0] \libresocsim_en_storage assign { } { } assign $0\libresocsim_update_value_storage[0:0] \libresocsim_update_value_storage assign { } { } assign $0\libresocsim_value_status[31:0] \libresocsim_value_status assign $0\libresocsim_zero_pending[0:0] \libresocsim_zero_pending assign { } { } assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_eventmanager_storage assign { } { } assign $0\libresocsim_value[31:0] \libresocsim_value assign { } { } assign { } { } assign { } { } assign $0\sdram_storage[3:0] \sdram_storage assign { } { } assign $0\sdram_command_storage[5:0] \sdram_command_storage assign { } { } assign $0\sdram_address_storage[12:0] \sdram_address_storage assign { } { } assign $0\sdram_baddress_storage[1:0] \sdram_baddress_storage assign { } { } assign $0\sdram_wrdata_storage[15:0] \sdram_wrdata_storage assign { } { } assign $0\sdram_status[15:0] \sdram_status assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sdram_timer_count1[9:0] \sdram_timer_count1 assign { } { } assign $0\sdram_postponer_count[0:0] \sdram_postponer_count assign { } { } assign $0\sdram_sequencer_counter[3:0] \sdram_sequencer_counter assign $0\sdram_sequencer_count[0:0] \sdram_sequencer_count assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine0_cmd_buffer_lookahead_level assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_consume assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_source_valid assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_source_first assign $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] \sdram_bankmachine0_cmd_buffer_source_last assign $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine0_cmd_buffer_source_payload_we assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_row assign $0\sdram_bankmachine0_row_opened[0:0] \sdram_bankmachine0_row_opened assign $0\sdram_bankmachine0_twtpcon_ready[0:0] \sdram_bankmachine0_twtpcon_ready assign $0\sdram_bankmachine0_twtpcon_count[2:0] \sdram_bankmachine0_twtpcon_count assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine1_cmd_buffer_lookahead_level assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_consume assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_source_valid assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_source_first assign $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] \sdram_bankmachine1_cmd_buffer_source_last assign $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine1_cmd_buffer_source_payload_we assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_row assign $0\sdram_bankmachine1_row_opened[0:0] \sdram_bankmachine1_row_opened assign $0\sdram_bankmachine1_twtpcon_ready[0:0] \sdram_bankmachine1_twtpcon_ready assign $0\sdram_bankmachine1_twtpcon_count[2:0] \sdram_bankmachine1_twtpcon_count assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine2_cmd_buffer_lookahead_level assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_consume assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_source_valid assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_source_first assign $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] \sdram_bankmachine2_cmd_buffer_source_last assign $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine2_cmd_buffer_source_payload_we assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_row assign $0\sdram_bankmachine2_row_opened[0:0] \sdram_bankmachine2_row_opened assign $0\sdram_bankmachine2_twtpcon_ready[0:0] \sdram_bankmachine2_twtpcon_ready assign $0\sdram_bankmachine2_twtpcon_count[2:0] \sdram_bankmachine2_twtpcon_count assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine3_cmd_buffer_lookahead_level assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_consume assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_source_valid assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_source_first assign $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] \sdram_bankmachine3_cmd_buffer_source_last assign $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine3_cmd_buffer_source_payload_we assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_row assign $0\sdram_bankmachine3_row_opened[0:0] \sdram_bankmachine3_row_opened assign $0\sdram_bankmachine3_twtpcon_ready[0:0] \sdram_bankmachine3_twtpcon_ready assign $0\sdram_bankmachine3_twtpcon_count[2:0] \sdram_bankmachine3_twtpcon_count assign $0\sdram_choose_cmd_grant[1:0] \sdram_choose_cmd_grant assign $0\sdram_choose_req_grant[1:0] \sdram_choose_req_grant assign $0\sdram_tccdcon_ready[0:0] \sdram_tccdcon_ready assign $0\sdram_tccdcon_count[0:0] \sdram_tccdcon_count assign $0\sdram_twtrcon_ready[0:0] \sdram_twtrcon_ready assign $0\sdram_twtrcon_count[2:0] \sdram_twtrcon_count assign $0\sdram_time0[4:0] \sdram_time0 assign $0\sdram_time1[3:0] \sdram_time1 assign $0\converter_counter[0:0] \converter_counter assign $0\converter_dat_r[31:0] \converter_dat_r assign $0\cmd_consumed[0:0] \cmd_consumed assign $0\wdata_consumed[0:0] \wdata_consumed assign $0\uart_phy_storage[31:0] \uart_phy_storage assign { } { } assign { } { } assign $0\uart_phy_uart_clk_txen[0:0] \uart_phy_uart_clk_txen assign $0\uart_phy_phase_accumulator_tx[31:0] \uart_phy_phase_accumulator_tx assign $0\uart_phy_tx_reg[7:0] \uart_phy_tx_reg assign $0\uart_phy_tx_bitcount[3:0] \uart_phy_tx_bitcount assign $0\uart_phy_tx_busy[0:0] \uart_phy_tx_busy assign { } { } assign $0\uart_phy_source_payload_data[7:0] \uart_phy_source_payload_data assign $0\uart_phy_uart_clk_rxen[0:0] \uart_phy_uart_clk_rxen assign $0\uart_phy_phase_accumulator_rx[31:0] \uart_phy_phase_accumulator_rx assign { } { } assign $0\uart_phy_rx_reg[7:0] \uart_phy_rx_reg assign $0\uart_phy_rx_bitcount[3:0] \uart_phy_rx_bitcount assign $0\uart_phy_rx_busy[0:0] \uart_phy_rx_busy assign $0\tx_pending[0:0] \tx_pending assign { } { } assign $0\rx_pending[0:0] \rx_pending assign { } { } assign $0\eventmanager_storage[1:0] \eventmanager_storage assign { } { } assign $0\tx_fifo_readable[0:0] \tx_fifo_readable assign $0\tx_fifo_level0[4:0] \tx_fifo_level0 assign $0\tx_fifo_produce[3:0] \tx_fifo_produce assign $0\tx_fifo_consume[3:0] \tx_fifo_consume assign $0\rx_fifo_readable[0:0] \rx_fifo_readable assign $0\rx_fifo_level0[4:0] \rx_fifo_level0 assign $0\rx_fifo_produce[3:0] \rx_fifo_produce assign $0\rx_fifo_consume[3:0] \rx_fifo_consume assign $0\gpio0_oe_storage[7:0] \gpio0_oe_storage assign { } { } assign $0\gpio0_out_storage[7:0] \gpio0_out_storage assign { } { } assign $0\gpio1_oe_storage[7:0] \gpio1_oe_storage assign { } { } assign $0\gpio1_out_storage[7:0] \gpio1_out_storage assign { } { } assign { } { } assign $0\i2c_storage[2:0] \i2c_storage assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w assign $0\libresocsim_grant[1:0] \libresocsim_grant assign { } { } assign $0\libresocsim_count[19:0] \libresocsim_count assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\dummy[39:0] [0] $or$ls180.v:4277$1216_Y assign $0\dummy[39:0] [1] $or$ls180.v:4278$1217_Y assign $0\dummy[39:0] [2] $or$ls180.v:4279$1218_Y assign $0\dummy[39:0] [3] $or$ls180.v:4280$1219_Y assign $0\dummy[39:0] [4] $or$ls180.v:4281$1220_Y assign $0\dummy[39:0] [5] $or$ls180.v:4282$1221_Y assign $0\dummy[39:0] [6] $or$ls180.v:4283$1222_Y assign $0\dummy[39:0] [7] $or$ls180.v:4284$1223_Y assign $0\dummy[39:0] [8] $or$ls180.v:4285$1224_Y assign $0\dummy[39:0] [9] $or$ls180.v:4286$1225_Y assign $0\dummy[39:0] [10] $or$ls180.v:4287$1226_Y assign $0\dummy[39:0] [11] $or$ls180.v:4288$1227_Y assign $0\dummy[39:0] [12] $or$ls180.v:4289$1228_Y assign $0\dummy[39:0] [13] $or$ls180.v:4290$1229_Y assign $0\dummy[39:0] [14] $or$ls180.v:4291$1230_Y assign $0\dummy[39:0] [15] $or$ls180.v:4292$1231_Y assign $0\dummy[39:0] [16] $or$ls180.v:4293$1232_Y assign $0\dummy[39:0] [17] $or$ls180.v:4294$1233_Y assign $0\dummy[39:0] [18] $or$ls180.v:4295$1234_Y assign $0\dummy[39:0] [19] $or$ls180.v:4296$1235_Y assign $0\dummy[39:0] [20] $or$ls180.v:4297$1236_Y assign $0\dummy[39:0] [21] $or$ls180.v:4298$1237_Y assign $0\dummy[39:0] [22] $or$ls180.v:4299$1238_Y assign $0\dummy[39:0] [23] $or$ls180.v:4300$1239_Y assign $0\dummy[39:0] [24] $or$ls180.v:4301$1240_Y assign $0\dummy[39:0] [25] $or$ls180.v:4302$1241_Y assign $0\dummy[39:0] [26] $or$ls180.v:4303$1242_Y assign $0\dummy[39:0] [27] $or$ls180.v:4304$1243_Y assign $0\dummy[39:0] [28] $or$ls180.v:4305$1244_Y assign $0\dummy[39:0] [29] $or$ls180.v:4306$1245_Y assign $0\dummy[39:0] [30] $or$ls180.v:4307$1246_Y assign $0\dummy[39:0] [31] $or$ls180.v:4308$1247_Y assign $0\dummy[39:0] [32] $or$ls180.v:4309$1248_Y assign $0\dummy[39:0] [33] $or$ls180.v:4310$1249_Y assign $0\dummy[39:0] [34] $or$ls180.v:4311$1250_Y assign $0\dummy[39:0] [35] $or$ls180.v:4312$1251_Y assign $0\dummy[39:0] [36] $or$ls180.v:4313$1252_Y assign $0\dummy[39:0] [37] $or$ls180.v:4314$1253_Y assign $0\dummy[39:0] [38] $or$ls180.v:4315$1254_Y assign $0\dummy[39:0] [39] $or$ls180.v:4316$1255_Y assign $0\subfragments_converter0_state[0:0] \subfragments_converter0_next_state assign $0\subfragments_converter1_state[0:0] \subfragments_converter1_next_state assign $0\subfragments_converter2_state[0:0] \subfragments_converter2_next_state assign $0\libresocsim_ram_bus_ack[0:0] 1'0 assign $0\libresocsim_zero_old_trigger[0:0] \libresocsim_zero_trigger assign $0\ram_bus_ram_bus_ack[0:0] 1'0 assign $0\rddata_en[2:0] { \rddata_en [1:0] \dfi_p0_rddata_en } assign $0\dfi_p0_rddata_valid[0:0] \rddata_en [2] assign $0\sdram_postponer_req_o[0:0] 1'0 assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\sdram_cmd_payload_ba[1:0] 2'00 assign $0\sdram_cmd_payload_cas[0:0] 1'0 assign $0\sdram_cmd_payload_ras[0:0] 1'0 assign $0\sdram_cmd_payload_we[0:0] 1'0 assign $0\sdram_sequencer_done1[0:0] 1'0 assign $0\subfragments_refresher_state[1:0] \subfragments_refresher_next_state assign $0\subfragments_bankmachine0_state[2:0] \subfragments_bankmachine0_next_state assign $0\subfragments_bankmachine1_state[2:0] \subfragments_bankmachine1_next_state assign $0\subfragments_bankmachine2_state[2:0] \subfragments_bankmachine2_next_state assign $0\subfragments_bankmachine3_state[2:0] \subfragments_bankmachine3_next_state assign $0\sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\sdram_dfi_p0_bank[1:0] \array_muxed0 assign $0\sdram_dfi_p0_address[12:0] \array_muxed1 assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4762$1355_Y assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4763$1356_Y assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4764$1357_Y assign $0\sdram_dfi_p0_rddata_en[0:0] \array_muxed5 assign $0\sdram_dfi_p0_wrdata_en[0:0] \array_muxed6 assign $0\subfragments_multiplexer_state[2:0] \subfragments_multiplexer_next_state assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4798$1375_Y assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4799$1387_Y assign $0\subfragments_new_master_rdata_valid1[0:0] \subfragments_new_master_rdata_valid0 assign $0\subfragments_new_master_rdata_valid2[0:0] \subfragments_new_master_rdata_valid1 assign $0\subfragments_new_master_rdata_valid3[0:0] \subfragments_new_master_rdata_valid2 assign $0\subfragments_state[0:0] \subfragments_next_state assign $0\uart_phy_sink_ready[0:0] 1'0 assign $0\uart_phy_source_valid[0:0] 1'0 assign $0\uart_phy_rx_r[0:0] \uart_phy_rx assign $0\tx_old_trigger[0:0] \tx_trigger assign $0\rx_old_trigger[0:0] \rx_trigger assign $0\libresocsim_state[1:0] \libresocsim_next_state assign $0\libresocsim_slave_sel_r[5:0] \libresocsim_slave_sel assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000 assign $0\libresocsim_reset_re[0:0] \libresocsim_csrbank0_reset0_re assign $0\libresocsim_scratch_re[0:0] \libresocsim_csrbank0_scratch0_re assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000 assign $0\gpio0_oe_re[0:0] \libresocsim_csrbank1_oe0_re assign $0\gpio0_out_re[0:0] \libresocsim_csrbank1_out0_re assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000 assign $0\gpio1_oe_re[0:0] \libresocsim_csrbank2_oe0_re assign $0\gpio1_out_re[0:0] \libresocsim_csrbank2_out0_re assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000 assign $0\i2c_re[0:0] \libresocsim_csrbank3_w0_re assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000 assign $0\sdram_re[0:0] \libresocsim_csrbank4_dfii_control0_re assign $0\sdram_command_re[0:0] \libresocsim_csrbank4_dfii_pi0_command0_re assign $0\sdram_address_re[0:0] \libresocsim_csrbank4_dfii_pi0_address0_re assign $0\sdram_baddress_re[0:0] \libresocsim_csrbank4_dfii_pi0_baddress0_re assign $0\sdram_wrdata_re[0:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_re assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 assign $0\libresocsim_load_re[0:0] \libresocsim_csrbank5_load0_re assign $0\libresocsim_reload_re[0:0] \libresocsim_csrbank5_reload0_re assign $0\libresocsim_en_re[0:0] \libresocsim_csrbank5_en0_re assign $0\libresocsim_update_value_re[0:0] \libresocsim_csrbank5_update_value0_re assign $0\libresocsim_eventmanager_re[0:0] \libresocsim_csrbank5_ev_enable0_re assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 assign $0\eventmanager_re[0:0] \libresocsim_csrbank6_ev_enable0_re assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000 assign $0\uart_phy_re[0:0] \libresocsim_csrbank7_tuning_word0_re assign $0\regs0[0:0] \libresocsim_libresoc_constraintmanager_uart_rx assign $0\regs1[0:0] \regs0 attribute \src "ls180.v:4317.2-4319.5" switch $or$ls180.v:4317$1256_Y attribute \src "ls180.v:4317.6-4317.84" case 1'1 assign $0\libresocsim_converter0_dat_r[63:0] \libresocsim_libresoc_ibus_dat_r case end attribute \src "ls180.v:4321.2-4323.5" switch \libresocsim_converter0_counter_subfragments_converter0_next_value_ce attribute \src "ls180.v:4321.6-4321.74" case 1'1 assign $0\libresocsim_converter0_counter[0:0] \libresocsim_converter0_counter_subfragments_converter0_next_value case end attribute \src "ls180.v:4324.2-4327.5" switch \libresocsim_converter0_reset attribute \src "ls180.v:4324.6-4324.34" case 1'1 assign $0\libresocsim_converter0_counter[0:0] 1'0 assign $0\subfragments_converter0_state[0:0] 1'0 case end attribute \src "ls180.v:4328.2-4330.5" switch $or$ls180.v:4328$1257_Y attribute \src "ls180.v:4328.6-4328.84" case 1'1 assign $0\libresocsim_converter1_dat_r[63:0] \libresocsim_libresoc_dbus_dat_r case end attribute \src "ls180.v:4332.2-4334.5" switch \libresocsim_converter1_counter_subfragments_converter1_next_value_ce attribute \src "ls180.v:4332.6-4332.74" case 1'1 assign $0\libresocsim_converter1_counter[0:0] \libresocsim_converter1_counter_subfragments_converter1_next_value case end attribute \src "ls180.v:4335.2-4338.5" switch \libresocsim_converter1_reset attribute \src "ls180.v:4335.6-4335.34" case 1'1 assign $0\libresocsim_converter1_counter[0:0] 1'0 assign $0\subfragments_converter1_state[0:0] 1'0 case end attribute \src "ls180.v:4339.2-4341.5" switch $or$ls180.v:4339$1258_Y attribute \src "ls180.v:4339.6-4339.84" case 1'1 assign $0\libresocsim_converter2_dat_r[63:0] \libresocsim_libresoc_jtag_wb_dat_r case end attribute \src "ls180.v:4343.2-4345.5" switch \libresocsim_converter2_counter_subfragments_converter2_next_value_ce attribute \src "ls180.v:4343.6-4343.74" case 1'1 assign $0\libresocsim_converter2_counter[0:0] \libresocsim_converter2_counter_subfragments_converter2_next_value case end attribute \src "ls180.v:4346.2-4349.5" switch \libresocsim_converter2_reset attribute \src "ls180.v:4346.6-4346.34" case 1'1 assign $0\libresocsim_converter2_counter[0:0] 1'0 assign $0\subfragments_converter2_state[0:0] 1'0 case end attribute \src "ls180.v:4350.2-4354.5" switch $ne$ls180.v:4350$1259_Y attribute \src "ls180.v:4350.6-4350.48" case 1'1 attribute \src "ls180.v:4351.3-4353.6" switch \libresocsim_bus_error attribute \src "ls180.v:4351.7-4351.28" case 1'1 assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4352$1260_Y case end case end attribute \src "ls180.v:4356.2-4358.5" switch $and$ls180.v:4356$1263_Y attribute \src "ls180.v:4356.6-4356.88" case 1'1 assign $0\libresocsim_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:4359.2-4367.5" switch \libresocsim_en_storage attribute \src "ls180.v:4359.6-4359.28" case 1'1 attribute \src "ls180.v:4360.3-4364.6" switch $eq$ls180.v:4360$1264_Y attribute \src "ls180.v:4360.7-4360.34" case 1'1 assign $0\libresocsim_value[31:0] \libresocsim_reload_storage attribute \src "ls180.v:4362.7-4362.11" case assign $0\libresocsim_value[31:0] $sub$ls180.v:4363$1265_Y end attribute \src "ls180.v:4365.6-4365.10" case assign $0\libresocsim_value[31:0] \libresocsim_load_storage end attribute \src "ls180.v:4368.2-4370.5" switch \libresocsim_update_value_re attribute \src "ls180.v:4368.6-4368.33" case 1'1 assign $0\libresocsim_value_status[31:0] \libresocsim_value case end attribute \src "ls180.v:4371.2-4373.5" switch \libresocsim_zero_clear attribute \src "ls180.v:4371.6-4371.28" case 1'1 assign $0\libresocsim_zero_pending[0:0] 1'0 case end attribute \src "ls180.v:4375.2-4377.5" switch $and$ls180.v:4375$1267_Y attribute \src "ls180.v:4375.6-4375.66" case 1'1 assign $0\libresocsim_zero_pending[0:0] 1'1 case end attribute \src "ls180.v:4379.2-4381.5" switch $and$ls180.v:4379$1270_Y attribute \src "ls180.v:4379.6-4379.76" case 1'1 assign $0\ram_bus_ram_bus_ack[0:0] 1'1 case end attribute \src "ls180.v:4384.2-4386.5" switch \sdram_inti_p0_rddata_valid attribute \src "ls180.v:4384.6-4384.32" case 1'1 assign $0\sdram_status[15:0] \sdram_inti_p0_rddata case end attribute \src "ls180.v:4387.2-4391.5" switch $and$ls180.v:4387$1272_Y attribute \src "ls180.v:4387.6-4387.47" case 1'1 assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4388$1273_Y attribute \src "ls180.v:4389.6-4389.10" case assign $0\sdram_timer_count1[9:0] 10'1100001101 end attribute \src "ls180.v:4393.2-4399.5" switch \sdram_postponer_req_i attribute \src "ls180.v:4393.6-4393.27" case 1'1 assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4394$1274_Y attribute \src "ls180.v:4395.3-4398.6" switch $eq$ls180.v:4395$1275_Y attribute \src "ls180.v:4395.7-4395.38" case 1'1 assign $0\sdram_postponer_count[0:0] 1'0 assign $0\sdram_postponer_req_o[0:0] 1'1 case end case end attribute \src "ls180.v:4400.2-4408.5" switch \sdram_sequencer_start0 attribute \src "ls180.v:4400.6-4400.28" case 1'1 assign $0\sdram_sequencer_count[0:0] 1'0 attribute \src "ls180.v:4402.6-4402.10" case attribute \src "ls180.v:4403.3-4407.6" switch \sdram_sequencer_done1 attribute \src "ls180.v:4403.7-4403.28" case 1'1 attribute \src "ls180.v:4404.4-4406.7" switch $ne$ls180.v:4404$1276_Y attribute \src "ls180.v:4404.8-4404.39" case 1'1 assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4405$1277_Y case end case end end attribute \src "ls180.v:4415.2-4421.5" switch $and$ls180.v:4415$1279_Y attribute \src "ls180.v:4415.6-4415.66" case 1'1 assign $0\sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\sdram_cmd_payload_ba[1:0] 2'00 assign $0\sdram_cmd_payload_cas[0:0] 1'0 assign $0\sdram_cmd_payload_ras[0:0] 1'1 assign $0\sdram_cmd_payload_we[0:0] 1'1 case end attribute \src "ls180.v:4422.2-4428.5" switch $eq$ls180.v:4422$1280_Y attribute \src "ls180.v:4422.6-4422.39" case 1'1 assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\sdram_cmd_payload_ba[1:0] 2'00 assign $0\sdram_cmd_payload_cas[0:0] 1'1 assign $0\sdram_cmd_payload_ras[0:0] 1'1 assign $0\sdram_cmd_payload_we[0:0] 1'0 case end attribute \src "ls180.v:4429.2-4436.5" switch $eq$ls180.v:4429$1281_Y attribute \src "ls180.v:4429.6-4429.39" case 1'1 assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\sdram_cmd_payload_ba[1:0] 2'00 assign $0\sdram_cmd_payload_cas[0:0] 1'0 assign $0\sdram_cmd_payload_ras[0:0] 1'0 assign $0\sdram_cmd_payload_we[0:0] 1'0 assign $0\sdram_sequencer_done1[0:0] 1'1 case end attribute \src "ls180.v:4437.2-4447.5" switch $eq$ls180.v:4437$1282_Y attribute \src "ls180.v:4437.6-4437.39" case 1'1 assign $0\sdram_sequencer_counter[3:0] 4'0000 attribute \src "ls180.v:4439.6-4439.10" case attribute \src "ls180.v:4440.3-4446.6" switch $ne$ls180.v:4440$1283_Y attribute \src "ls180.v:4440.7-4440.40" case 1'1 assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4441$1284_Y attribute \src "ls180.v:4442.7-4442.11" case attribute \src "ls180.v:4443.4-4445.7" switch \sdram_sequencer_start1 attribute \src "ls180.v:4443.8-4443.30" case 1'1 assign $0\sdram_sequencer_counter[3:0] 4'0001 case end end end attribute \src "ls180.v:4449.2-4456.5" switch \sdram_bankmachine0_row_close attribute \src "ls180.v:4449.6-4449.34" case 1'1 assign $0\sdram_bankmachine0_row_opened[0:0] 1'0 attribute \src "ls180.v:4451.6-4451.10" case attribute \src "ls180.v:4452.3-4455.6" switch \sdram_bankmachine0_row_open attribute \src "ls180.v:4452.7-4452.34" case 1'1 assign $0\sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end attribute \src "ls180.v:4457.2-4459.5" switch $and$ls180.v:4457$1287_Y attribute \src "ls180.v:4457.6-4457.176" case 1'1 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4458$1288_Y case end attribute \src "ls180.v:4460.2-4462.5" switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4460.6-4460.53" case 1'1 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4461$1289_Y case end attribute \src "ls180.v:4463.2-4471.5" switch $and$ls180.v:4463$1292_Y attribute \src "ls180.v:4463.6-4463.176" case 1'1 attribute \src "ls180.v:4464.3-4466.6" switch $not$ls180.v:4464$1293_Y attribute \src "ls180.v:4464.7-4464.57" case 1'1 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4465$1294_Y case end attribute \src "ls180.v:4467.6-4467.10" case attribute \src "ls180.v:4468.3-4470.6" switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4468.7-4468.54" case 1'1 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4469$1295_Y case end end attribute \src "ls180.v:4472.2-4478.5" switch $or$ls180.v:4472$1297_Y attribute \src "ls180.v:4472.6-4472.98" case 1'1 assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_sink_valid assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_sink_first assign $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] \sdram_bankmachine0_cmd_buffer_sink_last assign $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine0_cmd_buffer_sink_payload_we assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_sink_payload_addr case end attribute \src "ls180.v:4479.2-4493.5" switch \sdram_bankmachine0_twtpcon_valid attribute \src "ls180.v:4479.6-4479.38" case 1'1 assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'100 attribute \src "ls180.v:4481.3-4485.6" switch 1'0 attribute \src "ls180.v:4483.7-4483.11" case assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end attribute \src "ls180.v:4486.6-4486.10" case attribute \src "ls180.v:4487.3-4492.6" switch $not$ls180.v:4487$1298_Y attribute \src "ls180.v:4487.7-4487.42" case 1'1 assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4488$1299_Y attribute \src "ls180.v:4489.4-4491.7" switch $eq$ls180.v:4489$1300_Y attribute \src "ls180.v:4489.8-4489.50" case 1'1 assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case end case end end attribute \src "ls180.v:4495.2-4502.5" switch \sdram_bankmachine1_row_close attribute \src "ls180.v:4495.6-4495.34" case 1'1 assign $0\sdram_bankmachine1_row_opened[0:0] 1'0 attribute \src "ls180.v:4497.6-4497.10" case attribute \src "ls180.v:4498.3-4501.6" switch \sdram_bankmachine1_row_open attribute \src "ls180.v:4498.7-4498.34" case 1'1 assign $0\sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end attribute \src "ls180.v:4503.2-4505.5" switch $and$ls180.v:4503$1303_Y attribute \src "ls180.v:4503.6-4503.176" case 1'1 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4504$1304_Y case end attribute \src "ls180.v:4506.2-4508.5" switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4506.6-4506.53" case 1'1 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4507$1305_Y case end attribute \src "ls180.v:4509.2-4517.5" switch $and$ls180.v:4509$1308_Y attribute \src "ls180.v:4509.6-4509.176" case 1'1 attribute \src "ls180.v:4510.3-4512.6" switch $not$ls180.v:4510$1309_Y attribute \src "ls180.v:4510.7-4510.57" case 1'1 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4511$1310_Y case end attribute \src "ls180.v:4513.6-4513.10" case attribute \src "ls180.v:4514.3-4516.6" switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4514.7-4514.54" case 1'1 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4515$1311_Y case end end attribute \src "ls180.v:4518.2-4524.5" switch $or$ls180.v:4518$1313_Y attribute \src "ls180.v:4518.6-4518.98" case 1'1 assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_sink_valid assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_sink_first assign $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] \sdram_bankmachine1_cmd_buffer_sink_last assign $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine1_cmd_buffer_sink_payload_we assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_sink_payload_addr case end attribute \src "ls180.v:4525.2-4539.5" switch \sdram_bankmachine1_twtpcon_valid attribute \src "ls180.v:4525.6-4525.38" case 1'1 assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'100 attribute \src "ls180.v:4527.3-4531.6" switch 1'0 attribute \src "ls180.v:4529.7-4529.11" case assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end attribute \src "ls180.v:4532.6-4532.10" case attribute \src "ls180.v:4533.3-4538.6" switch $not$ls180.v:4533$1314_Y attribute \src "ls180.v:4533.7-4533.42" case 1'1 assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4534$1315_Y attribute \src "ls180.v:4535.4-4537.7" switch $eq$ls180.v:4535$1316_Y attribute \src "ls180.v:4535.8-4535.50" case 1'1 assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case end case end end attribute \src "ls180.v:4541.2-4548.5" switch \sdram_bankmachine2_row_close attribute \src "ls180.v:4541.6-4541.34" case 1'1 assign $0\sdram_bankmachine2_row_opened[0:0] 1'0 attribute \src "ls180.v:4543.6-4543.10" case attribute \src "ls180.v:4544.3-4547.6" switch \sdram_bankmachine2_row_open attribute \src "ls180.v:4544.7-4544.34" case 1'1 assign $0\sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end attribute \src "ls180.v:4549.2-4551.5" switch $and$ls180.v:4549$1319_Y attribute \src "ls180.v:4549.6-4549.176" case 1'1 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4550$1320_Y case end attribute \src "ls180.v:4552.2-4554.5" switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4552.6-4552.53" case 1'1 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4553$1321_Y case end attribute \src "ls180.v:4555.2-4563.5" switch $and$ls180.v:4555$1324_Y attribute \src "ls180.v:4555.6-4555.176" case 1'1 attribute \src "ls180.v:4556.3-4558.6" switch $not$ls180.v:4556$1325_Y attribute \src "ls180.v:4556.7-4556.57" case 1'1 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4557$1326_Y case end attribute \src "ls180.v:4559.6-4559.10" case attribute \src "ls180.v:4560.3-4562.6" switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4560.7-4560.54" case 1'1 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4561$1327_Y case end end attribute \src "ls180.v:4564.2-4570.5" switch $or$ls180.v:4564$1329_Y attribute \src "ls180.v:4564.6-4564.98" case 1'1 assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_sink_valid assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_sink_first assign $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] \sdram_bankmachine2_cmd_buffer_sink_last assign $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine2_cmd_buffer_sink_payload_we assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_sink_payload_addr case end attribute \src "ls180.v:4571.2-4585.5" switch \sdram_bankmachine2_twtpcon_valid attribute \src "ls180.v:4571.6-4571.38" case 1'1 assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'100 attribute \src "ls180.v:4573.3-4577.6" switch 1'0 attribute \src "ls180.v:4575.7-4575.11" case assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end attribute \src "ls180.v:4578.6-4578.10" case attribute \src "ls180.v:4579.3-4584.6" switch $not$ls180.v:4579$1330_Y attribute \src "ls180.v:4579.7-4579.42" case 1'1 assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4580$1331_Y attribute \src "ls180.v:4581.4-4583.7" switch $eq$ls180.v:4581$1332_Y attribute \src "ls180.v:4581.8-4581.50" case 1'1 assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case end case end end attribute \src "ls180.v:4587.2-4594.5" switch \sdram_bankmachine3_row_close attribute \src "ls180.v:4587.6-4587.34" case 1'1 assign $0\sdram_bankmachine3_row_opened[0:0] 1'0 attribute \src "ls180.v:4589.6-4589.10" case attribute \src "ls180.v:4590.3-4593.6" switch \sdram_bankmachine3_row_open attribute \src "ls180.v:4590.7-4590.34" case 1'1 assign $0\sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end attribute \src "ls180.v:4595.2-4597.5" switch $and$ls180.v:4595$1335_Y attribute \src "ls180.v:4595.6-4595.176" case 1'1 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4596$1336_Y case end attribute \src "ls180.v:4598.2-4600.5" switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4598.6-4598.53" case 1'1 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4599$1337_Y case end attribute \src "ls180.v:4601.2-4609.5" switch $and$ls180.v:4601$1340_Y attribute \src "ls180.v:4601.6-4601.176" case 1'1 attribute \src "ls180.v:4602.3-4604.6" switch $not$ls180.v:4602$1341_Y attribute \src "ls180.v:4602.7-4602.57" case 1'1 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4603$1342_Y case end attribute \src "ls180.v:4605.6-4605.10" case attribute \src "ls180.v:4606.3-4608.6" switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read attribute \src "ls180.v:4606.7-4606.54" case 1'1 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4607$1343_Y case end end attribute \src "ls180.v:4610.2-4616.5" switch $or$ls180.v:4610$1345_Y attribute \src "ls180.v:4610.6-4610.98" case 1'1 assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_sink_valid assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_sink_first assign $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] \sdram_bankmachine3_cmd_buffer_sink_last assign $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine3_cmd_buffer_sink_payload_we assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_sink_payload_addr case end attribute \src "ls180.v:4617.2-4631.5" switch \sdram_bankmachine3_twtpcon_valid attribute \src "ls180.v:4617.6-4617.38" case 1'1 assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'100 attribute \src "ls180.v:4619.3-4623.6" switch 1'0 attribute \src "ls180.v:4621.7-4621.11" case assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end attribute \src "ls180.v:4624.6-4624.10" case attribute \src "ls180.v:4625.3-4630.6" switch $not$ls180.v:4625$1346_Y attribute \src "ls180.v:4625.7-4625.42" case 1'1 assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4626$1347_Y attribute \src "ls180.v:4627.4-4629.7" switch $eq$ls180.v:4627$1348_Y attribute \src "ls180.v:4627.8-4627.50" case 1'1 assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case end case end end attribute \src "ls180.v:4633.2-4639.5" switch $not$ls180.v:4633$1349_Y attribute \src "ls180.v:4633.6-4633.18" case 1'1 assign $0\sdram_time0[4:0] 5'11111 attribute \src "ls180.v:4635.6-4635.10" case attribute \src "ls180.v:4636.3-4638.6" switch $not$ls180.v:4636$1350_Y attribute \src "ls180.v:4636.7-4636.25" case 1'1 assign $0\sdram_time0[4:0] $sub$ls180.v:4637$1351_Y case end end attribute \src "ls180.v:4640.2-4646.5" switch $not$ls180.v:4640$1352_Y attribute \src "ls180.v:4640.6-4640.18" case 1'1 assign $0\sdram_time1[3:0] 4'1111 attribute \src "ls180.v:4642.6-4642.10" case attribute \src "ls180.v:4643.3-4645.6" switch $not$ls180.v:4643$1353_Y attribute \src "ls180.v:4643.7-4643.25" case 1'1 assign $0\sdram_time1[3:0] $sub$ls180.v:4644$1354_Y case end end attribute \src "ls180.v:4647.2-4702.5" switch \sdram_choose_cmd_ce attribute \src "ls180.v:4647.6-4647.25" case 1'1 attribute \src "ls180.v:4648.3-4701.10" switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 attribute \src "ls180.v:4650.5-4660.8" switch \sdram_choose_cmd_request [1] attribute \src "ls180.v:4650.9-4650.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'01 attribute \src "ls180.v:4652.9-4652.13" case attribute \src "ls180.v:4653.6-4659.9" switch \sdram_choose_cmd_request [2] attribute \src "ls180.v:4653.10-4653.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'10 attribute \src "ls180.v:4655.10-4655.14" case attribute \src "ls180.v:4656.7-4658.10" switch \sdram_choose_cmd_request [3] attribute \src "ls180.v:4656.11-4656.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'11 case end end end attribute \src "ls180.v:0.0-0.0" case 2'01 attribute \src "ls180.v:4663.5-4673.8" switch \sdram_choose_cmd_request [2] attribute \src "ls180.v:4663.9-4663.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'10 attribute \src "ls180.v:4665.9-4665.13" case attribute \src "ls180.v:4666.6-4672.9" switch \sdram_choose_cmd_request [3] attribute \src "ls180.v:4666.10-4666.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'11 attribute \src "ls180.v:4668.10-4668.14" case attribute \src "ls180.v:4669.7-4671.10" switch \sdram_choose_cmd_request [0] attribute \src "ls180.v:4669.11-4669.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'00 case end end end attribute \src "ls180.v:0.0-0.0" case 2'10 attribute \src "ls180.v:4676.5-4686.8" switch \sdram_choose_cmd_request [3] attribute \src "ls180.v:4676.9-4676.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'11 attribute \src "ls180.v:4678.9-4678.13" case attribute \src "ls180.v:4679.6-4685.9" switch \sdram_choose_cmd_request [0] attribute \src "ls180.v:4679.10-4679.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'00 attribute \src "ls180.v:4681.10-4681.14" case attribute \src "ls180.v:4682.7-4684.10" switch \sdram_choose_cmd_request [1] attribute \src "ls180.v:4682.11-4682.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'01 case end end end attribute \src "ls180.v:0.0-0.0" case 2'11 attribute \src "ls180.v:4689.5-4699.8" switch \sdram_choose_cmd_request [0] attribute \src "ls180.v:4689.9-4689.36" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'00 attribute \src "ls180.v:4691.9-4691.13" case attribute \src "ls180.v:4692.6-4698.9" switch \sdram_choose_cmd_request [1] attribute \src "ls180.v:4692.10-4692.37" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'01 attribute \src "ls180.v:4694.10-4694.14" case attribute \src "ls180.v:4695.7-4697.10" switch \sdram_choose_cmd_request [2] attribute \src "ls180.v:4695.11-4695.38" case 1'1 assign $0\sdram_choose_cmd_grant[1:0] 2'10 case end end end case end case end attribute \src "ls180.v:4703.2-4758.5" switch \sdram_choose_req_ce attribute \src "ls180.v:4703.6-4703.25" case 1'1 attribute \src "ls180.v:4704.3-4757.10" switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 attribute \src "ls180.v:4706.5-4716.8" switch \sdram_choose_req_request [1] attribute \src "ls180.v:4706.9-4706.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'01 attribute \src "ls180.v:4708.9-4708.13" case attribute \src "ls180.v:4709.6-4715.9" switch \sdram_choose_req_request [2] attribute \src "ls180.v:4709.10-4709.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'10 attribute \src "ls180.v:4711.10-4711.14" case attribute \src "ls180.v:4712.7-4714.10" switch \sdram_choose_req_request [3] attribute \src "ls180.v:4712.11-4712.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'11 case end end end attribute \src "ls180.v:0.0-0.0" case 2'01 attribute \src "ls180.v:4719.5-4729.8" switch \sdram_choose_req_request [2] attribute \src "ls180.v:4719.9-4719.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'10 attribute \src "ls180.v:4721.9-4721.13" case attribute \src "ls180.v:4722.6-4728.9" switch \sdram_choose_req_request [3] attribute \src "ls180.v:4722.10-4722.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'11 attribute \src "ls180.v:4724.10-4724.14" case attribute \src "ls180.v:4725.7-4727.10" switch \sdram_choose_req_request [0] attribute \src "ls180.v:4725.11-4725.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'00 case end end end attribute \src "ls180.v:0.0-0.0" case 2'10 attribute \src "ls180.v:4732.5-4742.8" switch \sdram_choose_req_request [3] attribute \src "ls180.v:4732.9-4732.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'11 attribute \src "ls180.v:4734.9-4734.13" case attribute \src "ls180.v:4735.6-4741.9" switch \sdram_choose_req_request [0] attribute \src "ls180.v:4735.10-4735.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'00 attribute \src "ls180.v:4737.10-4737.14" case attribute \src "ls180.v:4738.7-4740.10" switch \sdram_choose_req_request [1] attribute \src "ls180.v:4738.11-4738.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'01 case end end end attribute \src "ls180.v:0.0-0.0" case 2'11 attribute \src "ls180.v:4745.5-4755.8" switch \sdram_choose_req_request [0] attribute \src "ls180.v:4745.9-4745.36" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'00 attribute \src "ls180.v:4747.9-4747.13" case attribute \src "ls180.v:4748.6-4754.9" switch \sdram_choose_req_request [1] attribute \src "ls180.v:4748.10-4748.37" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'01 attribute \src "ls180.v:4750.10-4750.14" case attribute \src "ls180.v:4751.7-4753.10" switch \sdram_choose_req_request [2] attribute \src "ls180.v:4751.11-4751.38" case 1'1 assign $0\sdram_choose_req_grant[1:0] 2'10 case end end end case end case end attribute \src "ls180.v:4767.2-4781.5" switch \sdram_tccdcon_valid attribute \src "ls180.v:4767.6-4767.25" case 1'1 assign $0\sdram_tccdcon_count[0:0] 1'0 attribute \src "ls180.v:4769.3-4773.6" switch 1'1 attribute \src "ls180.v:4769.7-4769.11" case 1'1 assign $0\sdram_tccdcon_ready[0:0] 1'1 case end attribute \src "ls180.v:4774.6-4774.10" case attribute \src "ls180.v:4775.3-4780.6" switch $not$ls180.v:4775$1358_Y attribute \src "ls180.v:4775.7-4775.29" case 1'1 assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4776$1359_Y attribute \src "ls180.v:4777.4-4779.7" switch $eq$ls180.v:4777$1360_Y attribute \src "ls180.v:4777.8-4777.37" case 1'1 assign $0\sdram_tccdcon_ready[0:0] 1'1 case end case end end attribute \src "ls180.v:4782.2-4796.5" switch \sdram_twtrcon_valid attribute \src "ls180.v:4782.6-4782.25" case 1'1 assign $0\sdram_twtrcon_count[2:0] 3'100 attribute \src "ls180.v:4784.3-4788.6" switch 1'0 attribute \src "ls180.v:4786.7-4786.11" case assign $0\sdram_twtrcon_ready[0:0] 1'0 end attribute \src "ls180.v:4789.6-4789.10" case attribute \src "ls180.v:4790.3-4795.6" switch $not$ls180.v:4790$1361_Y attribute \src "ls180.v:4790.7-4790.29" case 1'1 assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4791$1362_Y attribute \src "ls180.v:4792.4-4794.7" switch $eq$ls180.v:4792$1363_Y attribute \src "ls180.v:4792.8-4792.37" case 1'1 assign $0\sdram_twtrcon_ready[0:0] 1'1 case end case end end attribute \src "ls180.v:4803.2-4805.5" switch $or$ls180.v:4803$1388_Y attribute \src "ls180.v:4803.6-4803.40" case 1'1 assign $0\converter_dat_r[31:0] \wb_sdram_dat_r case end attribute \src "ls180.v:4807.2-4809.5" switch \converter_counter_subfragments_next_value_ce attribute \src "ls180.v:4807.6-4807.50" case 1'1 assign $0\converter_counter[0:0] \converter_counter_subfragments_next_value case end attribute \src "ls180.v:4810.2-4813.5" switch \converter_reset attribute \src "ls180.v:4810.6-4810.21" case 1'1 assign $0\converter_counter[0:0] 1'0 assign $0\subfragments_state[0:0] 1'0 case end attribute \src "ls180.v:4814.2-4824.5" switch \litedram_wb_ack attribute \src "ls180.v:4814.6-4814.21" case 1'1 assign $0\cmd_consumed[0:0] 1'0 assign $0\wdata_consumed[0:0] 1'0 attribute \src "ls180.v:4817.6-4817.10" case attribute \src "ls180.v:4818.3-4820.6" switch $and$ls180.v:4818$1389_Y attribute \src "ls180.v:4818.7-4818.40" case 1'1 assign $0\cmd_consumed[0:0] 1'1 case end attribute \src "ls180.v:4821.3-4823.6" switch $and$ls180.v:4821$1390_Y attribute \src "ls180.v:4821.7-4821.44" case 1'1 assign $0\wdata_consumed[0:0] 1'1 case end end attribute \src "ls180.v:4826.2-4847.5" switch $and$ls180.v:4826$1394_Y attribute \src "ls180.v:4826.6-4826.76" case 1'1 assign $0\uart_phy_tx_reg[7:0] \uart_phy_sink_payload_data assign $0\uart_phy_tx_bitcount[3:0] 4'0000 assign $0\uart_phy_tx_busy[0:0] 1'1 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'0 attribute \src "ls180.v:4831.6-4831.10" case attribute \src "ls180.v:4832.3-4846.6" switch $and$ls180.v:4832$1395_Y attribute \src "ls180.v:4832.7-4832.50" case 1'1 assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4833$1396_Y attribute \src "ls180.v:4834.4-4845.7" switch $eq$ls180.v:4834$1397_Y attribute \src "ls180.v:4834.8-4834.38" case 1'1 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 attribute \src "ls180.v:4836.8-4836.12" case attribute \src "ls180.v:4837.5-4844.8" switch $eq$ls180.v:4837$1398_Y attribute \src "ls180.v:4837.9-4837.39" case 1'1 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 assign $0\uart_phy_tx_busy[0:0] 1'0 assign $0\uart_phy_sink_ready[0:0] 1'1 attribute \src "ls180.v:4841.9-4841.13" case assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] \uart_phy_tx_reg [0] assign $0\uart_phy_tx_reg[7:0] { 1'0 \uart_phy_tx_reg [7:1] } end end case end end attribute \src "ls180.v:4848.2-4852.5" switch \uart_phy_tx_busy attribute \src "ls180.v:4848.6-4848.22" case 1'1 assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4849$1399_Y attribute \src "ls180.v:4850.6-4850.10" case assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } { 1'0 \uart_phy_storage } end attribute \src "ls180.v:4855.2-4879.5" switch $not$ls180.v:4855$1400_Y attribute \src "ls180.v:4855.6-4855.25" case 1'1 attribute \src "ls180.v:4856.3-4859.6" switch $and$ls180.v:4856$1402_Y attribute \src "ls180.v:4856.7-4856.39" case 1'1 assign $0\uart_phy_rx_busy[0:0] 1'1 assign $0\uart_phy_rx_bitcount[3:0] 4'0000 case end attribute \src "ls180.v:4860.6-4860.10" case attribute \src "ls180.v:4861.3-4878.6" switch \uart_phy_uart_clk_rxen attribute \src "ls180.v:4861.7-4861.29" case 1'1 assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4862$1403_Y attribute \src "ls180.v:4863.4-4877.7" switch $eq$ls180.v:4863$1404_Y attribute \src "ls180.v:4863.8-4863.38" case 1'1 attribute \src "ls180.v:4864.5-4866.8" switch \uart_phy_rx attribute \src "ls180.v:4864.9-4864.20" case 1'1 assign $0\uart_phy_rx_busy[0:0] 1'0 case end attribute \src "ls180.v:4867.8-4867.12" case attribute \src "ls180.v:4868.5-4876.8" switch $eq$ls180.v:4868$1405_Y attribute \src "ls180.v:4868.9-4868.39" case 1'1 assign $0\uart_phy_rx_busy[0:0] 1'0 attribute \src "ls180.v:4870.6-4873.9" switch \uart_phy_rx attribute \src "ls180.v:4870.10-4870.21" case 1'1 assign $0\uart_phy_source_payload_data[7:0] \uart_phy_rx_reg assign $0\uart_phy_source_valid[0:0] 1'1 case end attribute \src "ls180.v:4874.9-4874.13" case assign $0\uart_phy_rx_reg[7:0] { \uart_phy_rx \uart_phy_rx_reg [7:1] } end end case end end attribute \src "ls180.v:4880.2-4884.5" switch \uart_phy_rx_busy attribute \src "ls180.v:4880.6-4880.22" case 1'1 assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4881$1406_Y attribute \src "ls180.v:4882.6-4882.10" case assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end attribute \src "ls180.v:4885.2-4887.5" switch \tx_clear attribute \src "ls180.v:4885.6-4885.14" case 1'1 assign $0\tx_pending[0:0] 1'0 case end attribute \src "ls180.v:4889.2-4891.5" switch $and$ls180.v:4889$1408_Y attribute \src "ls180.v:4889.6-4889.38" case 1'1 assign $0\tx_pending[0:0] 1'1 case end attribute \src "ls180.v:4892.2-4894.5" switch \rx_clear attribute \src "ls180.v:4892.6-4892.14" case 1'1 assign $0\rx_pending[0:0] 1'0 case end attribute \src "ls180.v:4896.2-4898.5" switch $and$ls180.v:4896$1410_Y attribute \src "ls180.v:4896.6-4896.38" case 1'1 assign $0\rx_pending[0:0] 1'1 case end attribute \src "ls180.v:4899.2-4905.5" switch \tx_fifo_syncfifo_re attribute \src "ls180.v:4899.6-4899.25" case 1'1 assign $0\tx_fifo_readable[0:0] 1'1 attribute \src "ls180.v:4901.6-4901.10" case attribute \src "ls180.v:4902.3-4904.6" switch \tx_fifo_re attribute \src "ls180.v:4902.7-4902.17" case 1'1 assign $0\tx_fifo_readable[0:0] 1'0 case end end attribute \src "ls180.v:4906.2-4908.5" switch $and$ls180.v:4906$1413_Y attribute \src "ls180.v:4906.6-4906.78" case 1'1 assign $0\tx_fifo_produce[3:0] $add$ls180.v:4907$1414_Y case end attribute \src "ls180.v:4909.2-4911.5" switch \tx_fifo_do_read attribute \src "ls180.v:4909.6-4909.21" case 1'1 assign $0\tx_fifo_consume[3:0] $add$ls180.v:4910$1415_Y case end attribute \src "ls180.v:4912.2-4920.5" switch $and$ls180.v:4912$1418_Y attribute \src "ls180.v:4912.6-4912.78" case 1'1 attribute \src "ls180.v:4913.3-4915.6" switch $not$ls180.v:4913$1419_Y attribute \src "ls180.v:4913.7-4913.25" case 1'1 assign $0\tx_fifo_level0[4:0] $add$ls180.v:4914$1420_Y case end attribute \src "ls180.v:4916.6-4916.10" case attribute \src "ls180.v:4917.3-4919.6" switch \tx_fifo_do_read attribute \src "ls180.v:4917.7-4917.22" case 1'1 assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4918$1421_Y case end end attribute \src "ls180.v:4921.2-4927.5" switch \rx_fifo_syncfifo_re attribute \src "ls180.v:4921.6-4921.25" case 1'1 assign $0\rx_fifo_readable[0:0] 1'1 attribute \src "ls180.v:4923.6-4923.10" case attribute \src "ls180.v:4924.3-4926.6" switch \rx_fifo_re attribute \src "ls180.v:4924.7-4924.17" case 1'1 assign $0\rx_fifo_readable[0:0] 1'0 case end end attribute \src "ls180.v:4928.2-4930.5" switch $and$ls180.v:4928$1424_Y attribute \src "ls180.v:4928.6-4928.78" case 1'1 assign $0\rx_fifo_produce[3:0] $add$ls180.v:4929$1425_Y case end attribute \src "ls180.v:4931.2-4933.5" switch \rx_fifo_do_read attribute \src "ls180.v:4931.6-4931.21" case 1'1 assign $0\rx_fifo_consume[3:0] $add$ls180.v:4932$1426_Y case end attribute \src "ls180.v:4934.2-4942.5" switch $and$ls180.v:4934$1429_Y attribute \src "ls180.v:4934.6-4934.78" case 1'1 attribute \src "ls180.v:4935.3-4937.6" switch $not$ls180.v:4935$1430_Y attribute \src "ls180.v:4935.7-4935.25" case 1'1 assign $0\rx_fifo_level0[4:0] $add$ls180.v:4936$1431_Y case end attribute \src "ls180.v:4938.6-4938.10" case attribute \src "ls180.v:4939.3-4941.6" switch \rx_fifo_do_read attribute \src "ls180.v:4939.7-4939.22" case 1'1 assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4940$1432_Y case end end attribute \src "ls180.v:4943.2-4956.5" switch \reset attribute \src "ls180.v:4943.6-4943.11" case 1'1 assign $0\tx_pending[0:0] 1'0 assign $0\tx_old_trigger[0:0] 1'0 assign $0\rx_pending[0:0] 1'0 assign $0\rx_old_trigger[0:0] 1'0 assign $0\tx_fifo_readable[0:0] 1'0 assign $0\tx_fifo_level0[4:0] 5'00000 assign $0\tx_fifo_produce[3:0] 4'0000 assign $0\tx_fifo_consume[3:0] 4'0000 assign $0\rx_fifo_readable[0:0] 1'0 assign $0\rx_fifo_level0[4:0] 5'00000 assign $0\rx_fifo_produce[3:0] 4'0000 assign $0\rx_fifo_consume[3:0] 4'0000 case end attribute \src "ls180.v:4958.2-4960.5" switch \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 attribute \src "ls180.v:4958.6-4958.62" case 1'1 assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w_libresocsim_next_value0 case end attribute \src "ls180.v:4961.2-4963.5" switch \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 attribute \src "ls180.v:4961.6-4961.60" case 1'1 assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr_libresocsim_next_value1 case end attribute \src "ls180.v:4964.2-4966.5" switch \libresocsim_libresocsim_we_libresocsim_next_value_ce2 attribute \src "ls180.v:4964.6-4964.59" case 1'1 assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we_libresocsim_next_value2 case end attribute \src "ls180.v:4967.2-5001.9" switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 attribute \src "ls180.v:4969.4-4977.7" switch $not$ls180.v:4969$1433_Y attribute \src "ls180.v:4969.8-4969.33" case 1'1 attribute \src "ls180.v:4970.5-4976.8" switch \libresocsim_request [1] attribute \src "ls180.v:4970.9-4970.31" case 1'1 assign $0\libresocsim_grant[1:0] 2'01 attribute \src "ls180.v:4972.9-4972.13" case attribute \src "ls180.v:4973.6-4975.9" switch \libresocsim_request [2] attribute \src "ls180.v:4973.10-4973.32" case 1'1 assign $0\libresocsim_grant[1:0] 2'10 case end end case end attribute \src "ls180.v:0.0-0.0" case 2'01 attribute \src "ls180.v:4980.4-4988.7" switch $not$ls180.v:4980$1434_Y attribute \src "ls180.v:4980.8-4980.33" case 1'1 attribute \src "ls180.v:4981.5-4987.8" switch \libresocsim_request [2] attribute \src "ls180.v:4981.9-4981.31" case 1'1 assign $0\libresocsim_grant[1:0] 2'10 attribute \src "ls180.v:4983.9-4983.13" case attribute \src "ls180.v:4984.6-4986.9" switch \libresocsim_request [0] attribute \src "ls180.v:4984.10-4984.32" case 1'1 assign $0\libresocsim_grant[1:0] 2'00 case end end case end attribute \src "ls180.v:0.0-0.0" case 2'10 attribute \src "ls180.v:4991.4-4999.7" switch $not$ls180.v:4991$1435_Y attribute \src "ls180.v:4991.8-4991.33" case 1'1 attribute \src "ls180.v:4992.5-4998.8" switch \libresocsim_request [0] attribute \src "ls180.v:4992.9-4992.31" case 1'1 assign $0\libresocsim_grant[1:0] 2'00 attribute \src "ls180.v:4994.9-4994.13" case attribute \src "ls180.v:4995.6-4997.9" switch \libresocsim_request [1] attribute \src "ls180.v:4995.10-4995.32" case 1'1 assign $0\libresocsim_grant[1:0] 2'01 case end end case end case end attribute \src "ls180.v:5003.2-5009.5" switch \libresocsim_wait attribute \src "ls180.v:5003.6-5003.22" case 1'1 attribute \src "ls180.v:5004.3-5006.6" switch $not$ls180.v:5004$1436_Y attribute \src "ls180.v:5004.7-5004.26" case 1'1 assign $0\libresocsim_count[19:0] $sub$ls180.v:5005$1437_Y case end attribute \src "ls180.v:5007.6-5007.10" case assign $0\libresocsim_count[19:0] 20'11110100001001000000 end attribute \src "ls180.v:5011.2-5041.5" switch \libresocsim_csrbank0_sel attribute \src "ls180.v:5011.6-5011.30" case 1'1 attribute \src "ls180.v:5012.3-5040.10" switch \libresocsim_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank0_reset0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch3_w attribute \src "ls180.v:0.0-0.0" case 4'0010 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch2_w attribute \src "ls180.v:0.0-0.0" case 4'0011 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch1_w attribute \src "ls180.v:0.0-0.0" case 4'0100 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors3_w attribute \src "ls180.v:0.0-0.0" case 4'0110 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors2_w attribute \src "ls180.v:0.0-0.0" case 4'0111 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors1_w attribute \src "ls180.v:0.0-0.0" case 4'1000 assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors0_w case end case end attribute \src "ls180.v:5042.2-5044.5" switch \libresocsim_csrbank0_reset0_re attribute \src "ls180.v:5042.6-5042.36" case 1'1 assign $0\libresocsim_reset_storage[0:0] \libresocsim_csrbank0_reset0_r case end attribute \src "ls180.v:5046.2-5048.5" switch \libresocsim_csrbank0_scratch3_re attribute \src "ls180.v:5046.6-5046.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [31:24] \libresocsim_csrbank0_scratch3_r case end attribute \src "ls180.v:5049.2-5051.5" switch \libresocsim_csrbank0_scratch2_re attribute \src "ls180.v:5049.6-5049.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [23:16] \libresocsim_csrbank0_scratch2_r case end attribute \src "ls180.v:5052.2-5054.5" switch \libresocsim_csrbank0_scratch1_re attribute \src "ls180.v:5052.6-5052.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [15:8] \libresocsim_csrbank0_scratch1_r case end attribute \src "ls180.v:5055.2-5057.5" switch \libresocsim_csrbank0_scratch0_re attribute \src "ls180.v:5055.6-5055.38" case 1'1 assign $0\libresocsim_scratch_storage[31:0] [7:0] \libresocsim_csrbank0_scratch0_r case end attribute \src "ls180.v:5060.2-5072.5" switch \libresocsim_csrbank1_sel attribute \src "ls180.v:5060.6-5060.30" case 1'1 attribute \src "ls180.v:5061.3-5071.10" switch \libresocsim_interface1_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_oe0_w attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_in_w attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_out0_w case end case end attribute \src "ls180.v:5073.2-5075.5" switch \libresocsim_csrbank1_oe0_re attribute \src "ls180.v:5073.6-5073.33" case 1'1 assign $0\gpio0_oe_storage[7:0] \libresocsim_csrbank1_oe0_r case end attribute \src "ls180.v:5077.2-5079.5" switch \libresocsim_csrbank1_out0_re attribute \src "ls180.v:5077.6-5077.34" case 1'1 assign $0\gpio0_out_storage[7:0] \libresocsim_csrbank1_out0_r case end attribute \src "ls180.v:5082.2-5094.5" switch \libresocsim_csrbank2_sel attribute \src "ls180.v:5082.6-5082.30" case 1'1 attribute \src "ls180.v:5083.3-5093.10" switch \libresocsim_interface2_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_oe0_w attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_in_w attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_out0_w case end case end attribute \src "ls180.v:5095.2-5097.5" switch \libresocsim_csrbank2_oe0_re attribute \src "ls180.v:5095.6-5095.33" case 1'1 assign $0\gpio1_oe_storage[7:0] \libresocsim_csrbank2_oe0_r case end attribute \src "ls180.v:5099.2-5101.5" switch \libresocsim_csrbank2_out0_re attribute \src "ls180.v:5099.6-5099.34" case 1'1 assign $0\gpio1_out_storage[7:0] \libresocsim_csrbank2_out0_r case end attribute \src "ls180.v:5104.2-5113.5" switch \libresocsim_csrbank3_sel attribute \src "ls180.v:5104.6-5104.30" case 1'1 attribute \src "ls180.v:5105.3-5112.10" switch \libresocsim_interface3_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" case 1'0 assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] { 5'00000 \libresocsim_csrbank3_w0_w } attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank3_r_w } case end case end attribute \src "ls180.v:5114.2-5116.5" switch \libresocsim_csrbank3_w0_re attribute \src "ls180.v:5114.6-5114.32" case 1'1 assign $0\i2c_storage[2:0] \libresocsim_csrbank3_w0_r case end attribute \src "ls180.v:5119.2-5152.5" switch \libresocsim_csrbank4_sel attribute \src "ls180.v:5119.6-5119.30" case 1'1 attribute \src "ls180.v:5120.3-5151.10" switch \libresocsim_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 4'0000 \libresocsim_csrbank4_dfii_control0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 2'00 \libresocsim_csrbank4_dfii_pi0_command0_w } attribute \src "ls180.v:0.0-0.0" case 4'0010 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 7'0000000 \sdram_command_issue_w } attribute \src "ls180.v:0.0-0.0" case 4'0011 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 3'000 \libresocsim_csrbank4_dfii_pi0_address1_w } attribute \src "ls180.v:0.0-0.0" case 4'0100 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_address0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 6'000000 \libresocsim_csrbank4_dfii_pi0_baddress0_w } attribute \src "ls180.v:0.0-0.0" case 4'0110 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_wrdata1_w attribute \src "ls180.v:0.0-0.0" case 4'0111 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_w attribute \src "ls180.v:0.0-0.0" case 4'1000 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_rddata1_w attribute \src "ls180.v:0.0-0.0" case 4'1001 assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_rddata0_w case end case end attribute \src "ls180.v:5153.2-5155.5" switch \libresocsim_csrbank4_dfii_control0_re attribute \src "ls180.v:5153.6-5153.43" case 1'1 assign $0\sdram_storage[3:0] \libresocsim_csrbank4_dfii_control0_r case end attribute \src "ls180.v:5157.2-5159.5" switch \libresocsim_csrbank4_dfii_pi0_command0_re attribute \src "ls180.v:5157.6-5157.47" case 1'1 assign $0\sdram_command_storage[5:0] \libresocsim_csrbank4_dfii_pi0_command0_r case end attribute \src "ls180.v:5161.2-5163.5" switch \libresocsim_csrbank4_dfii_pi0_address1_re attribute \src "ls180.v:5161.6-5161.47" case 1'1 assign $0\sdram_address_storage[12:0] [12:8] \libresocsim_csrbank4_dfii_pi0_address1_r case end attribute \src "ls180.v:5164.2-5166.5" switch \libresocsim_csrbank4_dfii_pi0_address0_re attribute \src "ls180.v:5164.6-5164.47" case 1'1 assign $0\sdram_address_storage[12:0] [7:0] \libresocsim_csrbank4_dfii_pi0_address0_r case end attribute \src "ls180.v:5168.2-5170.5" switch \libresocsim_csrbank4_dfii_pi0_baddress0_re attribute \src "ls180.v:5168.6-5168.48" case 1'1 assign $0\sdram_baddress_storage[1:0] \libresocsim_csrbank4_dfii_pi0_baddress0_r case end attribute \src "ls180.v:5172.2-5174.5" switch \libresocsim_csrbank4_dfii_pi0_wrdata1_re attribute \src "ls180.v:5172.6-5172.46" case 1'1 assign $0\sdram_wrdata_storage[15:0] [15:8] \libresocsim_csrbank4_dfii_pi0_wrdata1_r case end attribute \src "ls180.v:5175.2-5177.5" switch \libresocsim_csrbank4_dfii_pi0_wrdata0_re attribute \src "ls180.v:5175.6-5175.46" case 1'1 assign $0\sdram_wrdata_storage[15:0] [7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_r case end attribute \src "ls180.v:5180.2-5234.5" switch \libresocsim_csrbank5_sel attribute \src "ls180.v:5180.6-5180.30" case 1'1 attribute \src "ls180.v:5181.3-5233.10" switch \libresocsim_interface5_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load3_w attribute \src "ls180.v:0.0-0.0" case 5'00001 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load2_w attribute \src "ls180.v:0.0-0.0" case 5'00010 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load1_w attribute \src "ls180.v:0.0-0.0" case 5'00011 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load0_w attribute \src "ls180.v:0.0-0.0" case 5'00100 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload3_w attribute \src "ls180.v:0.0-0.0" case 5'00101 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload2_w attribute \src "ls180.v:0.0-0.0" case 5'00110 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload1_w attribute \src "ls180.v:0.0-0.0" case 5'00111 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload0_w attribute \src "ls180.v:0.0-0.0" case 5'01000 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_en0_w } attribute \src "ls180.v:0.0-0.0" case 5'01001 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_update_value0_w } attribute \src "ls180.v:0.0-0.0" case 5'01010 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value3_w attribute \src "ls180.v:0.0-0.0" case 5'01011 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value2_w attribute \src "ls180.v:0.0-0.0" case 5'01100 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value1_w attribute \src "ls180.v:0.0-0.0" case 5'01101 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value0_w attribute \src "ls180.v:0.0-0.0" case 5'01110 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 5'01111 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 5'10000 assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_ev_enable0_w } case end case end attribute \src "ls180.v:5235.2-5237.5" switch \libresocsim_csrbank5_load3_re attribute \src "ls180.v:5235.6-5235.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [31:24] \libresocsim_csrbank5_load3_r case end attribute \src "ls180.v:5238.2-5240.5" switch \libresocsim_csrbank5_load2_re attribute \src "ls180.v:5238.6-5238.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [23:16] \libresocsim_csrbank5_load2_r case end attribute \src "ls180.v:5241.2-5243.5" switch \libresocsim_csrbank5_load1_re attribute \src "ls180.v:5241.6-5241.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [15:8] \libresocsim_csrbank5_load1_r case end attribute \src "ls180.v:5244.2-5246.5" switch \libresocsim_csrbank5_load0_re attribute \src "ls180.v:5244.6-5244.35" case 1'1 assign $0\libresocsim_load_storage[31:0] [7:0] \libresocsim_csrbank5_load0_r case end attribute \src "ls180.v:5248.2-5250.5" switch \libresocsim_csrbank5_reload3_re attribute \src "ls180.v:5248.6-5248.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [31:24] \libresocsim_csrbank5_reload3_r case end attribute \src "ls180.v:5251.2-5253.5" switch \libresocsim_csrbank5_reload2_re attribute \src "ls180.v:5251.6-5251.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [23:16] \libresocsim_csrbank5_reload2_r case end attribute \src "ls180.v:5254.2-5256.5" switch \libresocsim_csrbank5_reload1_re attribute \src "ls180.v:5254.6-5254.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [15:8] \libresocsim_csrbank5_reload1_r case end attribute \src "ls180.v:5257.2-5259.5" switch \libresocsim_csrbank5_reload0_re attribute \src "ls180.v:5257.6-5257.37" case 1'1 assign $0\libresocsim_reload_storage[31:0] [7:0] \libresocsim_csrbank5_reload0_r case end attribute \src "ls180.v:5261.2-5263.5" switch \libresocsim_csrbank5_en0_re attribute \src "ls180.v:5261.6-5261.33" case 1'1 assign $0\libresocsim_en_storage[0:0] \libresocsim_csrbank5_en0_r case end attribute \src "ls180.v:5265.2-5267.5" switch \libresocsim_csrbank5_update_value0_re attribute \src "ls180.v:5265.6-5265.43" case 1'1 assign $0\libresocsim_update_value_storage[0:0] \libresocsim_csrbank5_update_value0_r case end attribute \src "ls180.v:5269.2-5271.5" switch \libresocsim_csrbank5_ev_enable0_re attribute \src "ls180.v:5269.6-5269.40" case 1'1 assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_csrbank5_ev_enable0_r case end attribute \src "ls180.v:5274.2-5301.5" switch \libresocsim_csrbank6_sel attribute \src "ls180.v:5274.6-5274.30" case 1'1 attribute \src "ls180.v:5275.3-5300.10" switch \libresocsim_interface6_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] \rxtx_w attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_txfull_w } attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_rxempty_w } attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \libresocsim_csrbank6_ev_enable0_w } attribute \src "ls180.v:0.0-0.0" case 3'110 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_txempty_w } attribute \src "ls180.v:0.0-0.0" case 3'111 assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_rxfull_w } case end case end attribute \src "ls180.v:5302.2-5304.5" switch \libresocsim_csrbank6_ev_enable0_re attribute \src "ls180.v:5302.6-5302.40" case 1'1 assign $0\eventmanager_storage[1:0] \libresocsim_csrbank6_ev_enable0_r case end attribute \src "ls180.v:5307.2-5322.5" switch \libresocsim_csrbank7_sel attribute \src "ls180.v:5307.6-5307.30" case 1'1 attribute \src "ls180.v:5308.3-5321.10" switch \libresocsim_interface7_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word3_w attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word2_w attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word1_w attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word0_w case end case end attribute \src "ls180.v:5323.2-5325.5" switch \libresocsim_csrbank7_tuning_word3_re attribute \src "ls180.v:5323.6-5323.42" case 1'1 assign $0\uart_phy_storage[31:0] [31:24] \libresocsim_csrbank7_tuning_word3_r case end attribute \src "ls180.v:5326.2-5328.5" switch \libresocsim_csrbank7_tuning_word2_re attribute \src "ls180.v:5326.6-5326.42" case 1'1 assign $0\uart_phy_storage[31:0] [23:16] \libresocsim_csrbank7_tuning_word2_r case end attribute \src "ls180.v:5329.2-5331.5" switch \libresocsim_csrbank7_tuning_word1_re attribute \src "ls180.v:5329.6-5329.42" case 1'1 assign $0\uart_phy_storage[31:0] [15:8] \libresocsim_csrbank7_tuning_word1_r case end attribute \src "ls180.v:5332.2-5334.5" switch \libresocsim_csrbank7_tuning_word0_re attribute \src "ls180.v:5332.6-5332.42" case 1'1 assign $0\uart_phy_storage[31:0] [7:0] \libresocsim_csrbank7_tuning_word0_r case end attribute \src "ls180.v:5336.2-5483.5" switch \sys_rst_1 attribute \src "ls180.v:5336.6-5336.15" case 1'1 assign $0\libresocsim_reset_storage[0:0] 1'0 assign $0\libresocsim_reset_re[0:0] 1'0 assign $0\libresocsim_scratch_storage[31:0] 305419896 assign $0\libresocsim_scratch_re[0:0] 1'0 assign $0\libresocsim_bus_errors[31:0] 0 assign $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] 1'1 assign $0\libresocsim_converter0_counter[0:0] 1'0 assign $0\libresocsim_converter1_counter[0:0] 1'0 assign $0\libresocsim_converter2_counter[0:0] 1'0 assign $0\libresocsim_ram_bus_ack[0:0] 1'0 assign $0\libresocsim_load_storage[31:0] 0 assign $0\libresocsim_load_re[0:0] 1'0 assign $0\libresocsim_reload_storage[31:0] 0 assign $0\libresocsim_reload_re[0:0] 1'0 assign $0\libresocsim_en_storage[0:0] 1'0 assign $0\libresocsim_en_re[0:0] 1'0 assign $0\libresocsim_update_value_storage[0:0] 1'0 assign $0\libresocsim_update_value_re[0:0] 1'0 assign $0\libresocsim_value_status[31:0] 0 assign $0\libresocsim_zero_pending[0:0] 1'0 assign $0\libresocsim_zero_old_trigger[0:0] 1'0 assign $0\libresocsim_eventmanager_storage[0:0] 1'0 assign $0\libresocsim_eventmanager_re[0:0] 1'0 assign $0\libresocsim_value[31:0] 0 assign $0\ram_bus_ram_bus_ack[0:0] 1'0 assign $0\dfi_p0_rddata_valid[0:0] 1'0 assign $0\rddata_en[2:0] 3'000 assign $0\sdram_storage[3:0] 4'0001 assign $0\sdram_re[0:0] 1'0 assign $0\sdram_command_storage[5:0] 6'000000 assign $0\sdram_command_re[0:0] 1'0 assign $0\sdram_address_re[0:0] 1'0 assign $0\sdram_baddress_re[0:0] 1'0 assign $0\sdram_wrdata_re[0:0] 1'0 assign $0\sdram_status[15:0] 16'0000000000000000 assign $0\sdram_dfi_p0_address[12:0] 13'0000000000000 assign $0\sdram_dfi_p0_bank[1:0] 2'00 assign $0\sdram_dfi_p0_cas_n[0:0] 1'1 assign $0\sdram_dfi_p0_cs_n[0:0] 1'1 assign $0\sdram_dfi_p0_ras_n[0:0] 1'1 assign $0\sdram_dfi_p0_we_n[0:0] 1'1 assign $0\sdram_dfi_p0_wrdata_en[0:0] 1'0 assign $0\sdram_dfi_p0_rddata_en[0:0] 1'0 assign $0\sdram_timer_count1[9:0] 10'1100001101 assign $0\sdram_postponer_req_o[0:0] 1'0 assign $0\sdram_postponer_count[0:0] 1'0 assign $0\sdram_sequencer_done1[0:0] 1'0 assign $0\sdram_sequencer_counter[3:0] 4'0000 assign $0\sdram_sequencer_count[0:0] 1'0 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 assign $0\sdram_bankmachine0_row[12:0] 13'0000000000000 assign $0\sdram_bankmachine0_row_opened[0:0] 1'0 assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'000 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 assign $0\sdram_bankmachine1_row[12:0] 13'0000000000000 assign $0\sdram_bankmachine1_row_opened[0:0] 1'0 assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'000 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 assign $0\sdram_bankmachine2_row[12:0] 13'0000000000000 assign $0\sdram_bankmachine2_row_opened[0:0] 1'0 assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'000 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 assign $0\sdram_bankmachine3_row[12:0] 13'0000000000000 assign $0\sdram_bankmachine3_row_opened[0:0] 1'0 assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'000 assign $0\sdram_choose_cmd_grant[1:0] 2'00 assign $0\sdram_choose_req_grant[1:0] 2'00 assign $0\sdram_tccdcon_ready[0:0] 1'0 assign $0\sdram_tccdcon_count[0:0] 1'0 assign $0\sdram_twtrcon_ready[0:0] 1'0 assign $0\sdram_twtrcon_count[2:0] 3'000 assign $0\sdram_time0[4:0] 5'00000 assign $0\sdram_time1[3:0] 4'0000 assign $0\converter_counter[0:0] 1'0 assign $0\cmd_consumed[0:0] 1'0 assign $0\wdata_consumed[0:0] 1'0 assign $0\uart_phy_storage[31:0] 9895604 assign $0\uart_phy_re[0:0] 1'0 assign $0\uart_phy_sink_ready[0:0] 1'0 assign $0\uart_phy_uart_clk_txen[0:0] 1'0 assign $0\uart_phy_tx_busy[0:0] 1'0 assign $0\uart_phy_source_valid[0:0] 1'0 assign $0\uart_phy_uart_clk_rxen[0:0] 1'0 assign $0\uart_phy_rx_r[0:0] 1'0 assign $0\uart_phy_rx_busy[0:0] 1'0 assign $0\tx_pending[0:0] 1'0 assign $0\tx_old_trigger[0:0] 1'0 assign $0\rx_pending[0:0] 1'0 assign $0\rx_old_trigger[0:0] 1'0 assign $0\eventmanager_storage[1:0] 2'00 assign $0\eventmanager_re[0:0] 1'0 assign $0\tx_fifo_readable[0:0] 1'0 assign $0\tx_fifo_level0[4:0] 5'00000 assign $0\tx_fifo_produce[3:0] 4'0000 assign $0\tx_fifo_consume[3:0] 4'0000 assign $0\rx_fifo_readable[0:0] 1'0 assign $0\rx_fifo_level0[4:0] 5'00000 assign $0\rx_fifo_produce[3:0] 4'0000 assign $0\rx_fifo_consume[3:0] 4'0000 assign $0\gpio0_oe_storage[7:0] 8'00000000 assign $0\gpio0_oe_re[0:0] 1'0 assign $0\gpio0_out_storage[7:0] 8'00000000 assign $0\gpio0_out_re[0:0] 1'0 assign $0\gpio1_oe_storage[7:0] 8'00000000 assign $0\gpio1_oe_re[0:0] 1'0 assign $0\gpio1_out_storage[7:0] 8'00000000 assign $0\gpio1_out_re[0:0] 1'0 assign $0\dummy[39:0] 40'0000000000000000000000000000000000000000 assign $0\i2c_storage[2:0] 3'000 assign $0\i2c_re[0:0] 1'0 assign $0\subfragments_converter0_state[0:0] 1'0 assign $0\subfragments_converter1_state[0:0] 1'0 assign $0\subfragments_converter2_state[0:0] 1'0 assign $0\subfragments_refresher_state[1:0] 2'00 assign $0\subfragments_bankmachine0_state[2:0] 3'000 assign $0\subfragments_bankmachine1_state[2:0] 3'000 assign $0\subfragments_bankmachine2_state[2:0] 3'000 assign $0\subfragments_bankmachine3_state[2:0] 3'000 assign $0\subfragments_multiplexer_state[2:0] 3'000 assign $0\subfragments_new_master_wdata_ready[0:0] 1'0 assign $0\subfragments_new_master_rdata_valid0[0:0] 1'0 assign $0\subfragments_new_master_rdata_valid1[0:0] 1'0 assign $0\subfragments_new_master_rdata_valid2[0:0] 1'0 assign $0\subfragments_new_master_rdata_valid3[0:0] 1'0 assign $0\subfragments_state[0:0] 1'0 assign $0\libresocsim_libresocsim_we[0:0] 1'0 assign $0\libresocsim_grant[1:0] 2'00 assign $0\libresocsim_slave_sel_r[5:0] 6'000000 assign $0\libresocsim_count[19:0] 20'11110100001001000000 assign $0\libresocsim_state[1:0] 2'00 case end sync posedge \sys_clk_1 update \libresocsim_reset_storage $0\libresocsim_reset_storage[0:0] update \libresocsim_reset_re $0\libresocsim_reset_re[0:0] update \libresocsim_scratch_storage $0\libresocsim_scratch_storage[31:0] update \libresocsim_scratch_re $0\libresocsim_scratch_re[0:0] update \libresocsim_bus_errors $0\libresocsim_bus_errors[31:0] update \libresocsim_libresoc_constraintmanager_uart_tx $0\libresocsim_libresoc_constraintmanager_uart_tx[0:0] update \libresocsim_converter0_counter $0\libresocsim_converter0_counter[0:0] update \libresocsim_converter0_dat_r $0\libresocsim_converter0_dat_r[63:0] update \libresocsim_converter1_counter $0\libresocsim_converter1_counter[0:0] update \libresocsim_converter1_dat_r $0\libresocsim_converter1_dat_r[63:0] update \libresocsim_converter2_counter $0\libresocsim_converter2_counter[0:0] update \libresocsim_converter2_dat_r $0\libresocsim_converter2_dat_r[63:0] update \libresocsim_ram_bus_ack $0\libresocsim_ram_bus_ack[0:0] update \libresocsim_load_storage $0\libresocsim_load_storage[31:0] update \libresocsim_load_re $0\libresocsim_load_re[0:0] update \libresocsim_reload_storage $0\libresocsim_reload_storage[31:0] update \libresocsim_reload_re $0\libresocsim_reload_re[0:0] update \libresocsim_en_storage $0\libresocsim_en_storage[0:0] update \libresocsim_en_re $0\libresocsim_en_re[0:0] update \libresocsim_update_value_storage $0\libresocsim_update_value_storage[0:0] update \libresocsim_update_value_re $0\libresocsim_update_value_re[0:0] update \libresocsim_value_status $0\libresocsim_value_status[31:0] update \libresocsim_zero_pending $0\libresocsim_zero_pending[0:0] update \libresocsim_zero_old_trigger $0\libresocsim_zero_old_trigger[0:0] update \libresocsim_eventmanager_storage $0\libresocsim_eventmanager_storage[0:0] update \libresocsim_eventmanager_re $0\libresocsim_eventmanager_re[0:0] update \libresocsim_value $0\libresocsim_value[31:0] update \ram_bus_ram_bus_ack $0\ram_bus_ram_bus_ack[0:0] update \dfi_p0_rddata_valid $0\dfi_p0_rddata_valid[0:0] update \rddata_en $0\rddata_en[2:0] update \sdram_storage $0\sdram_storage[3:0] update \sdram_re $0\sdram_re[0:0] update \sdram_command_storage $0\sdram_command_storage[5:0] update \sdram_command_re $0\sdram_command_re[0:0] update \sdram_address_storage $0\sdram_address_storage[12:0] update \sdram_address_re $0\sdram_address_re[0:0] update \sdram_baddress_storage $0\sdram_baddress_storage[1:0] update \sdram_baddress_re $0\sdram_baddress_re[0:0] update \sdram_wrdata_storage $0\sdram_wrdata_storage[15:0] update \sdram_wrdata_re $0\sdram_wrdata_re[0:0] update \sdram_status $0\sdram_status[15:0] update \sdram_dfi_p0_address $0\sdram_dfi_p0_address[12:0] update \sdram_dfi_p0_bank $0\sdram_dfi_p0_bank[1:0] update \sdram_dfi_p0_cas_n $0\sdram_dfi_p0_cas_n[0:0] update \sdram_dfi_p0_cs_n $0\sdram_dfi_p0_cs_n[0:0] update \sdram_dfi_p0_ras_n $0\sdram_dfi_p0_ras_n[0:0] update \sdram_dfi_p0_we_n $0\sdram_dfi_p0_we_n[0:0] update \sdram_dfi_p0_wrdata_en $0\sdram_dfi_p0_wrdata_en[0:0] update \sdram_dfi_p0_rddata_en $0\sdram_dfi_p0_rddata_en[0:0] update \sdram_cmd_payload_a $0\sdram_cmd_payload_a[12:0] update \sdram_cmd_payload_ba $0\sdram_cmd_payload_ba[1:0] update \sdram_cmd_payload_cas $0\sdram_cmd_payload_cas[0:0] update \sdram_cmd_payload_ras $0\sdram_cmd_payload_ras[0:0] update \sdram_cmd_payload_we $0\sdram_cmd_payload_we[0:0] update \sdram_timer_count1 $0\sdram_timer_count1[9:0] update \sdram_postponer_req_o $0\sdram_postponer_req_o[0:0] update \sdram_postponer_count $0\sdram_postponer_count[0:0] update \sdram_sequencer_done1 $0\sdram_sequencer_done1[0:0] update \sdram_sequencer_counter $0\sdram_sequencer_counter[3:0] update \sdram_sequencer_count $0\sdram_sequencer_count[0:0] update \sdram_bankmachine0_cmd_buffer_lookahead_level $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] update \sdram_bankmachine0_cmd_buffer_lookahead_produce $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] update \sdram_bankmachine0_cmd_buffer_lookahead_consume $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] update \sdram_bankmachine0_cmd_buffer_source_valid $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] update \sdram_bankmachine0_cmd_buffer_source_first $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] update \sdram_bankmachine0_cmd_buffer_source_last $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] update \sdram_bankmachine0_cmd_buffer_source_payload_we $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] update \sdram_bankmachine0_cmd_buffer_source_payload_addr $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] update \sdram_bankmachine0_row $0\sdram_bankmachine0_row[12:0] update \sdram_bankmachine0_row_opened $0\sdram_bankmachine0_row_opened[0:0] update \sdram_bankmachine0_twtpcon_ready $0\sdram_bankmachine0_twtpcon_ready[0:0] update \sdram_bankmachine0_twtpcon_count $0\sdram_bankmachine0_twtpcon_count[2:0] update \sdram_bankmachine1_cmd_buffer_lookahead_level $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] update \sdram_bankmachine1_cmd_buffer_lookahead_produce $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] update \sdram_bankmachine1_cmd_buffer_lookahead_consume $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] update \sdram_bankmachine1_cmd_buffer_source_valid $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] update \sdram_bankmachine1_cmd_buffer_source_first $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] update \sdram_bankmachine1_cmd_buffer_source_last $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] update \sdram_bankmachine1_cmd_buffer_source_payload_we $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] update \sdram_bankmachine1_cmd_buffer_source_payload_addr $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] update \sdram_bankmachine1_row $0\sdram_bankmachine1_row[12:0] update \sdram_bankmachine1_row_opened $0\sdram_bankmachine1_row_opened[0:0] update \sdram_bankmachine1_twtpcon_ready $0\sdram_bankmachine1_twtpcon_ready[0:0] update \sdram_bankmachine1_twtpcon_count $0\sdram_bankmachine1_twtpcon_count[2:0] update \sdram_bankmachine2_cmd_buffer_lookahead_level $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] update \sdram_bankmachine2_cmd_buffer_lookahead_produce $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] update \sdram_bankmachine2_cmd_buffer_lookahead_consume $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] update \sdram_bankmachine2_cmd_buffer_source_valid $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] update \sdram_bankmachine2_cmd_buffer_source_first $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] update \sdram_bankmachine2_cmd_buffer_source_last $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] update \sdram_bankmachine2_cmd_buffer_source_payload_we $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] update \sdram_bankmachine2_cmd_buffer_source_payload_addr $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] update \sdram_bankmachine2_row $0\sdram_bankmachine2_row[12:0] update \sdram_bankmachine2_row_opened $0\sdram_bankmachine2_row_opened[0:0] update \sdram_bankmachine2_twtpcon_ready $0\sdram_bankmachine2_twtpcon_ready[0:0] update \sdram_bankmachine2_twtpcon_count $0\sdram_bankmachine2_twtpcon_count[2:0] update \sdram_bankmachine3_cmd_buffer_lookahead_level $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] update \sdram_bankmachine3_cmd_buffer_lookahead_produce $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] update \sdram_bankmachine3_cmd_buffer_lookahead_consume $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] update \sdram_bankmachine3_cmd_buffer_source_valid $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] update \sdram_bankmachine3_cmd_buffer_source_first $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] update \sdram_bankmachine3_cmd_buffer_source_last $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] update \sdram_bankmachine3_cmd_buffer_source_payload_we $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] update \sdram_bankmachine3_cmd_buffer_source_payload_addr $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] update \sdram_bankmachine3_row $0\sdram_bankmachine3_row[12:0] update \sdram_bankmachine3_row_opened $0\sdram_bankmachine3_row_opened[0:0] update \sdram_bankmachine3_twtpcon_ready $0\sdram_bankmachine3_twtpcon_ready[0:0] update \sdram_bankmachine3_twtpcon_count $0\sdram_bankmachine3_twtpcon_count[2:0] update \sdram_choose_cmd_grant $0\sdram_choose_cmd_grant[1:0] update \sdram_choose_req_grant $0\sdram_choose_req_grant[1:0] update \sdram_tccdcon_ready $0\sdram_tccdcon_ready[0:0] update \sdram_tccdcon_count $0\sdram_tccdcon_count[0:0] update \sdram_twtrcon_ready $0\sdram_twtrcon_ready[0:0] update \sdram_twtrcon_count $0\sdram_twtrcon_count[2:0] update \sdram_time0 $0\sdram_time0[4:0] update \sdram_time1 $0\sdram_time1[3:0] update \converter_counter $0\converter_counter[0:0] update \converter_dat_r $0\converter_dat_r[31:0] update \cmd_consumed $0\cmd_consumed[0:0] update \wdata_consumed $0\wdata_consumed[0:0] update \uart_phy_storage $0\uart_phy_storage[31:0] update \uart_phy_re $0\uart_phy_re[0:0] update \uart_phy_sink_ready $0\uart_phy_sink_ready[0:0] update \uart_phy_uart_clk_txen $0\uart_phy_uart_clk_txen[0:0] update \uart_phy_phase_accumulator_tx $0\uart_phy_phase_accumulator_tx[31:0] update \uart_phy_tx_reg $0\uart_phy_tx_reg[7:0] update \uart_phy_tx_bitcount $0\uart_phy_tx_bitcount[3:0] update \uart_phy_tx_busy $0\uart_phy_tx_busy[0:0] update \uart_phy_source_valid $0\uart_phy_source_valid[0:0] update \uart_phy_source_payload_data $0\uart_phy_source_payload_data[7:0] update \uart_phy_uart_clk_rxen $0\uart_phy_uart_clk_rxen[0:0] update \uart_phy_phase_accumulator_rx $0\uart_phy_phase_accumulator_rx[31:0] update \uart_phy_rx_r $0\uart_phy_rx_r[0:0] update \uart_phy_rx_reg $0\uart_phy_rx_reg[7:0] update \uart_phy_rx_bitcount $0\uart_phy_rx_bitcount[3:0] update \uart_phy_rx_busy $0\uart_phy_rx_busy[0:0] update \tx_pending $0\tx_pending[0:0] update \tx_old_trigger $0\tx_old_trigger[0:0] update \rx_pending $0\rx_pending[0:0] update \rx_old_trigger $0\rx_old_trigger[0:0] update \eventmanager_storage $0\eventmanager_storage[1:0] update \eventmanager_re $0\eventmanager_re[0:0] update \tx_fifo_readable $0\tx_fifo_readable[0:0] update \tx_fifo_level0 $0\tx_fifo_level0[4:0] update \tx_fifo_produce $0\tx_fifo_produce[3:0] update \tx_fifo_consume $0\tx_fifo_consume[3:0] update \rx_fifo_readable $0\rx_fifo_readable[0:0] update \rx_fifo_level0 $0\rx_fifo_level0[4:0] update \rx_fifo_produce $0\rx_fifo_produce[3:0] update \rx_fifo_consume $0\rx_fifo_consume[3:0] update \gpio0_oe_storage $0\gpio0_oe_storage[7:0] update \gpio0_oe_re $0\gpio0_oe_re[0:0] update \gpio0_out_storage $0\gpio0_out_storage[7:0] update \gpio0_out_re $0\gpio0_out_re[0:0] update \gpio1_oe_storage $0\gpio1_oe_storage[7:0] update \gpio1_oe_re $0\gpio1_oe_re[0:0] update \gpio1_out_storage $0\gpio1_out_storage[7:0] update \gpio1_out_re $0\gpio1_out_re[0:0] update \dummy $0\dummy[39:0] update \i2c_storage $0\i2c_storage[2:0] update \i2c_re $0\i2c_re[0:0] update \subfragments_converter0_state $0\subfragments_converter0_state[0:0] update \subfragments_converter1_state $0\subfragments_converter1_state[0:0] update \subfragments_converter2_state $0\subfragments_converter2_state[0:0] update \subfragments_refresher_state $0\subfragments_refresher_state[1:0] update \subfragments_bankmachine0_state $0\subfragments_bankmachine0_state[2:0] update \subfragments_bankmachine1_state $0\subfragments_bankmachine1_state[2:0] update \subfragments_bankmachine2_state $0\subfragments_bankmachine2_state[2:0] update \subfragments_bankmachine3_state $0\subfragments_bankmachine3_state[2:0] update \subfragments_multiplexer_state $0\subfragments_multiplexer_state[2:0] update \subfragments_new_master_wdata_ready $0\subfragments_new_master_wdata_ready[0:0] update \subfragments_new_master_rdata_valid0 $0\subfragments_new_master_rdata_valid0[0:0] update \subfragments_new_master_rdata_valid1 $0\subfragments_new_master_rdata_valid1[0:0] update \subfragments_new_master_rdata_valid2 $0\subfragments_new_master_rdata_valid2[0:0] update \subfragments_new_master_rdata_valid3 $0\subfragments_new_master_rdata_valid3[0:0] update \subfragments_state $0\subfragments_state[0:0] update \libresocsim_libresocsim_adr $0\libresocsim_libresocsim_adr[13:0] update \libresocsim_libresocsim_we $0\libresocsim_libresocsim_we[0:0] update \libresocsim_libresocsim_dat_w $0\libresocsim_libresocsim_dat_w[7:0] update \libresocsim_grant $0\libresocsim_grant[1:0] update \libresocsim_slave_sel_r $0\libresocsim_slave_sel_r[5:0] update \libresocsim_count $0\libresocsim_count[19:0] update \libresocsim_interface0_bank_bus_dat_r $0\libresocsim_interface0_bank_bus_dat_r[7:0] update \libresocsim_interface1_bank_bus_dat_r $0\libresocsim_interface1_bank_bus_dat_r[7:0] update \libresocsim_interface2_bank_bus_dat_r $0\libresocsim_interface2_bank_bus_dat_r[7:0] update \libresocsim_interface3_bank_bus_dat_r $0\libresocsim_interface3_bank_bus_dat_r[7:0] update \libresocsim_interface4_bank_bus_dat_r $0\libresocsim_interface4_bank_bus_dat_r[7:0] update \libresocsim_interface5_bank_bus_dat_r $0\libresocsim_interface5_bank_bus_dat_r[7:0] update \libresocsim_interface6_bank_bus_dat_r $0\libresocsim_interface6_bank_bus_dat_r[7:0] update \libresocsim_interface7_bank_bus_dat_r $0\libresocsim_interface7_bank_bus_dat_r[7:0] update \libresocsim_state $0\libresocsim_state[1:0] update \regs0 $0\regs0[0:0] update \regs1 $0\regs1[0:0] end attribute \src "ls180.v:43.5-43.32" process $proc$ls180.v:43$1552 assign { } { } assign $1\libresocsim_reset_re[0:0] 1'0 sync always sync init update \libresocsim_reset_re $1\libresocsim_reset_re[0:0] end attribute \src "ls180.v:438.11-438.63" process $proc$ls180.v:438$1717 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_level $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:439.5-439.59" process $proc$ls180.v:439$1718 assign { } { } assign $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine0_cmd_buffer_lookahead_replace $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init end attribute \src "ls180.v:44.12-44.55" process $proc$ls180.v:44$1553 assign { } { } assign $1\libresocsim_scratch_storage[31:0] 305419896 sync always sync init update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0] end attribute \src "ls180.v:440.11-440.65" process $proc$ls180.v:440$1719 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_produce $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:441.11-441.65" process $proc$ls180.v:441$1720 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_consume $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:442.11-442.68" process $proc$ls180.v:442$1721 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:45.5-45.34" process $proc$ls180.v:45$1554 assign { } { } assign $1\libresocsim_scratch_re[0:0] 1'0 sync always sync init update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0] end attribute \src "ls180.v:463.5-463.54" process $proc$ls180.v:463$1722 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_valid $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:465.5-465.54" process $proc$ls180.v:465$1723 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_first $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:466.5-466.53" process $proc$ls180.v:466$1724 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_last $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:467.5-467.59" process $proc$ls180.v:467$1725 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_payload_we $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:468.12-468.69" process $proc$ls180.v:468$1726 assign { } { } assign $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \sdram_bankmachine0_cmd_buffer_source_payload_addr $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:469.12-469.42" process $proc$ls180.v:469$1727 assign { } { } assign $1\sdram_bankmachine0_row[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine0_row $1\sdram_bankmachine0_row[12:0] end attribute \src "ls180.v:470.5-470.41" process $proc$ls180.v:470$1728 assign { } { } assign $1\sdram_bankmachine0_row_opened[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_opened $1\sdram_bankmachine0_row_opened[0:0] end attribute \src "ls180.v:472.5-472.39" process $proc$ls180.v:472$1729 assign { } { } assign $1\sdram_bankmachine0_row_open[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_open $1\sdram_bankmachine0_row_open[0:0] end attribute \src "ls180.v:473.5-473.40" process $proc$ls180.v:473$1730 assign { } { } assign $1\sdram_bankmachine0_row_close[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_close $1\sdram_bankmachine0_row_close[0:0] end attribute \src "ls180.v:474.5-474.49" process $proc$ls180.v:474$1731 assign { } { } assign $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \sdram_bankmachine0_row_col_n_addr_sel $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:476.32-476.71" process $proc$ls180.v:476$1732 assign { } { } assign $1\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine0_twtpcon_ready $1\sdram_bankmachine0_twtpcon_ready[0:0] end attribute \src "ls180.v:477.11-477.50" process $proc$ls180.v:477$1733 assign { } { } assign $1\sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always sync init update \sdram_bankmachine0_twtpcon_count $1\sdram_bankmachine0_twtpcon_count[2:0] end attribute \src "ls180.v:479.32-479.70" process $proc$ls180.v:479$1734 assign { } { } assign $0\sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always update \sdram_bankmachine0_trccon_ready $0\sdram_bankmachine0_trccon_ready[0:0] sync init end attribute \src "ls180.v:481.32-481.71" process $proc$ls180.v:481$1735 assign { } { } assign $0\sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine0_trascon_ready $0\sdram_bankmachine0_trascon_ready[0:0] sync init end attribute \src "ls180.v:487.5-487.46" process $proc$ls180.v:487$1736 assign { } { } assign $1\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine1_req_wdata_ready $1\sdram_bankmachine1_req_wdata_ready[0:0] end attribute \src "ls180.v:488.5-488.46" process $proc$ls180.v:488$1737 assign { } { } assign $1\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine1_req_rdata_valid $1\sdram_bankmachine1_req_rdata_valid[0:0] end attribute \src "ls180.v:490.5-490.42" process $proc$ls180.v:490$1738 assign { } { } assign $1\sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine1_refresh_gnt $1\sdram_bankmachine1_refresh_gnt[0:0] end attribute \src "ls180.v:491.5-491.40" process $proc$ls180.v:491$1739 assign { } { } assign $1\sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_valid $1\sdram_bankmachine1_cmd_valid[0:0] end attribute \src "ls180.v:492.5-492.40" process $proc$ls180.v:492$1740 assign { } { } assign $1\sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_ready $1\sdram_bankmachine1_cmd_ready[0:0] end attribute \src "ls180.v:493.12-493.52" process $proc$ls180.v:493$1741 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine1_cmd_payload_a $1\sdram_bankmachine1_cmd_payload_a[12:0] end attribute \src "ls180.v:495.5-495.46" process $proc$ls180.v:495$1742 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_cas $1\sdram_bankmachine1_cmd_payload_cas[0:0] end attribute \src "ls180.v:496.5-496.46" process $proc$ls180.v:496$1743 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_ras $1\sdram_bankmachine1_cmd_payload_ras[0:0] end attribute \src "ls180.v:497.5-497.45" process $proc$ls180.v:497$1744 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_we $1\sdram_bankmachine1_cmd_payload_we[0:0] end attribute \src "ls180.v:498.5-498.49" process $proc$ls180.v:498$1745 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_is_cmd $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:499.5-499.50" process $proc$ls180.v:499$1746 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_is_read $1\sdram_bankmachine1_cmd_payload_is_read[0:0] end attribute \src "ls180.v:50.12-50.42" process $proc$ls180.v:50$1555 assign { } { } assign $1\libresocsim_bus_errors[31:0] 0 sync always sync init update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0] end attribute \src "ls180.v:500.5-500.51" process $proc$ls180.v:500$1747 assign { } { } assign $1\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_payload_is_write $1\sdram_bankmachine1_cmd_payload_is_write[0:0] end attribute \src "ls180.v:501.5-501.45" process $proc$ls180.v:501$1748 assign { } { } assign $1\sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine1_auto_precharge $1\sdram_bankmachine1_auto_precharge[0:0] end attribute \src "ls180.v:504.5-504.62" process $proc$ls180.v:504$1749 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init end attribute \src "ls180.v:505.5-505.61" process $proc$ls180.v:505$1750 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init end attribute \src "ls180.v:52.12-52.50" process $proc$ls180.v:52$1556 assign { } { } assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 sync always sync init update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0] end attribute \src "ls180.v:520.11-520.63" process $proc$ls180.v:520$1751 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine1_cmd_buffer_lookahead_level $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:521.5-521.59" process $proc$ls180.v:521$1752 assign { } { } assign $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine1_cmd_buffer_lookahead_replace $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init end attribute \src "ls180.v:522.11-522.65" process $proc$ls180.v:522$1753 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine1_cmd_buffer_lookahead_produce $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:523.11-523.65" process $proc$ls180.v:523$1754 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine1_cmd_buffer_lookahead_consume $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:524.11-524.68" process $proc$ls180.v:524$1755 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:545.5-545.54" process $proc$ls180.v:545$1756 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:547.5-547.54" process $proc$ls180.v:547$1757 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:548.5-548.53" process $proc$ls180.v:548$1758 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:549.5-549.59" process $proc$ls180.v:549$1759 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:5490.1-5500.4" process $proc$ls180.v:5490$1438 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1439 $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 assign $0$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1440 $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 assign $0$memwr$\mem$ls180.v:5492$1_EN[31:0]$1441 $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 assign $0$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1442 $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 assign $0$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1443 $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 assign $0$memwr$\mem$ls180.v:5494$2_EN[31:0]$1444 $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 assign $0$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1445 $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 assign $0$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1446 $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 assign $0$memwr$\mem$ls180.v:5496$3_EN[31:0]$1447 $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 assign $0$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1448 $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 assign $0$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1449 $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 assign $0$memwr$\mem$ls180.v:5498$4_EN[31:0]$1450 $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 assign $0\memadr[6:0] \libresocsim_adr attribute \src "ls180.v:5491.2-5492.55" switch \libresocsim_we [0] attribute \src "ls180.v:5491.6-5491.23" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 \libresocsim_adr assign $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 { 24'000000000000000000000000 \libresocsim_dat_w [7:0] } assign $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 255 case assign $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 7'xxxxxxx assign $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 0 end attribute \src "ls180.v:5493.2-5494.57" switch \libresocsim_we [1] attribute \src "ls180.v:5493.6-5493.23" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 \libresocsim_adr assign $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 { 16'0000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx } assign $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 65280 case assign $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 7'xxxxxxx assign $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 0 end attribute \src "ls180.v:5495.2-5496.59" switch \libresocsim_we [2] attribute \src "ls180.v:5495.6-5495.23" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 \libresocsim_adr assign $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 { 8'00000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } assign $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 16711680 case assign $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 7'xxxxxxx assign $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 0 end attribute \src "ls180.v:5497.2-5498.59" switch \libresocsim_we [3] attribute \src "ls180.v:5497.6-5497.23" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 \libresocsim_adr assign $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 { \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } assign $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 32'11111111000000000000000000000000 case assign $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 7'xxxxxxx assign $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 0 end sync posedge \sys_clk_1 update \memadr $0\memadr[6:0] update $memwr$\mem$ls180.v:5492$1_ADDR $0$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1439 update $memwr$\mem$ls180.v:5492$1_DATA $0$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1440 update $memwr$\mem$ls180.v:5492$1_EN $0$memwr$\mem$ls180.v:5492$1_EN[31:0]$1441 update $memwr$\mem$ls180.v:5494$2_ADDR $0$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1442 update $memwr$\mem$ls180.v:5494$2_DATA $0$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1443 update $memwr$\mem$ls180.v:5494$2_EN $0$memwr$\mem$ls180.v:5494$2_EN[31:0]$1444 update $memwr$\mem$ls180.v:5496$3_ADDR $0$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1445 update $memwr$\mem$ls180.v:5496$3_DATA $0$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1446 update $memwr$\mem$ls180.v:5496$3_EN $0$memwr$\mem$ls180.v:5496$3_EN[31:0]$1447 update $memwr$\mem$ls180.v:5498$4_ADDR $0$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1448 update $memwr$\mem$ls180.v:5498$4_DATA $0$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1449 update $memwr$\mem$ls180.v:5498$4_EN $0$memwr$\mem$ls180.v:5498$4_EN[31:0]$1450 attribute \src "ls180.v:5492.3-5492.54" memwr \mem $1$memwr$\mem$ls180.v:5492$1_ADDR[6:0]$1451 $1$memwr$\mem$ls180.v:5492$1_DATA[31:0]$1452 $1$memwr$\mem$ls180.v:5492$1_EN[31:0]$1453 0' attribute \src "ls180.v:5494.3-5494.56" memwr \mem $1$memwr$\mem$ls180.v:5494$2_ADDR[6:0]$1454 $1$memwr$\mem$ls180.v:5494$2_DATA[31:0]$1455 $1$memwr$\mem$ls180.v:5494$2_EN[31:0]$1456 1'1 attribute \src "ls180.v:5496.3-5496.58" memwr \mem $1$memwr$\mem$ls180.v:5496$3_ADDR[6:0]$1457 $1$memwr$\mem$ls180.v:5496$3_DATA[31:0]$1458 $1$memwr$\mem$ls180.v:5496$3_EN[31:0]$1459 2'11 attribute \src "ls180.v:5498.3-5498.58" memwr \mem $1$memwr$\mem$ls180.v:5498$4_ADDR[6:0]$1460 $1$memwr$\mem$ls180.v:5498$4_DATA[31:0]$1461 $1$memwr$\mem$ls180.v:5498$4_EN[31:0]$1462 3'111 end attribute \src "ls180.v:550.12-550.69" process $proc$ls180.v:550$1760 assign { } { } assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:551.12-551.42" process $proc$ls180.v:551$1761 assign { } { } assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0] end attribute \src "ls180.v:5510.1-5520.4" process $proc$ls180.v:5510$1464 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1465 $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 assign $0$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1466 $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 assign $0$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1467 $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 assign $0$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1468 $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 assign $0$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1469 $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 assign $0$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1470 $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 assign $0$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1471 $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 assign $0$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1472 $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 assign $0$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1473 $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 assign $0$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1474 $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 assign $0$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1475 $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 assign $0$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1476 $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 assign $0\memadr_1[4:0] \ram_adr attribute \src "ls180.v:5511.2-5512.41" switch \ram_we [0] attribute \src "ls180.v:5511.6-5511.15" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 \ram_adr assign $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 { 24'000000000000000000000000 \ram_dat_w [7:0] } assign $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 255 case assign $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 5'xxxxx assign $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 0 end attribute \src "ls180.v:5513.2-5514.43" switch \ram_we [1] attribute \src "ls180.v:5513.6-5513.15" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 \ram_adr assign $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 { 16'0000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx } assign $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 65280 case assign $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 5'xxxxx assign $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 0 end attribute \src "ls180.v:5515.2-5516.45" switch \ram_we [2] attribute \src "ls180.v:5515.6-5515.15" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 \ram_adr assign $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 { 8'00000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } assign $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 16711680 case assign $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 5'xxxxx assign $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 0 end attribute \src "ls180.v:5517.2-5518.45" switch \ram_we [3] attribute \src "ls180.v:5517.6-5517.15" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 \ram_adr assign $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 { \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } assign $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 32'11111111000000000000000000000000 case assign $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 5'xxxxx assign $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 0 end sync posedge \sys_clk_1 update \memadr_1 $0\memadr_1[4:0] update $memwr$\mem_1$ls180.v:5512$5_ADDR $0$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1465 update $memwr$\mem_1$ls180.v:5512$5_DATA $0$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1466 update $memwr$\mem_1$ls180.v:5512$5_EN $0$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1467 update $memwr$\mem_1$ls180.v:5514$6_ADDR $0$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1468 update $memwr$\mem_1$ls180.v:5514$6_DATA $0$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1469 update $memwr$\mem_1$ls180.v:5514$6_EN $0$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1470 update $memwr$\mem_1$ls180.v:5516$7_ADDR $0$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1471 update $memwr$\mem_1$ls180.v:5516$7_DATA $0$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1472 update $memwr$\mem_1$ls180.v:5516$7_EN $0$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1473 update $memwr$\mem_1$ls180.v:5518$8_ADDR $0$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1474 update $memwr$\mem_1$ls180.v:5518$8_DATA $0$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1475 update $memwr$\mem_1$ls180.v:5518$8_EN $0$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1476 attribute \src "ls180.v:5512.3-5512.40" memwr \mem_1 $1$memwr$\mem_1$ls180.v:5512$5_ADDR[4:0]$1477 $1$memwr$\mem_1$ls180.v:5512$5_DATA[31:0]$1478 $1$memwr$\mem_1$ls180.v:5512$5_EN[31:0]$1479 0' attribute \src "ls180.v:5514.3-5514.42" memwr \mem_1 $1$memwr$\mem_1$ls180.v:5514$6_ADDR[4:0]$1480 $1$memwr$\mem_1$ls180.v:5514$6_DATA[31:0]$1481 $1$memwr$\mem_1$ls180.v:5514$6_EN[31:0]$1482 1'1 attribute \src "ls180.v:5516.3-5516.44" memwr \mem_1 $1$memwr$\mem_1$ls180.v:5516$7_ADDR[4:0]$1483 $1$memwr$\mem_1$ls180.v:5516$7_DATA[31:0]$1484 $1$memwr$\mem_1$ls180.v:5516$7_EN[31:0]$1485 2'11 attribute \src "ls180.v:5518.3-5518.44" memwr \mem_1 $1$memwr$\mem_1$ls180.v:5518$8_ADDR[4:0]$1486 $1$memwr$\mem_1$ls180.v:5518$8_DATA[31:0]$1487 $1$memwr$\mem_1$ls180.v:5518$8_EN[31:0]$1488 3'111 end attribute \src "ls180.v:552.5-552.41" process $proc$ls180.v:552$1762 assign { } { } assign $1\sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0] end attribute \src "ls180.v:5530.1-5534.4" process $proc$ls180.v:5530$1490 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1491 $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 assign $0$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1492 $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 assign $0$memwr$\storage$ls180.v:5532$9_EN[24:0]$1493 $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 assign $0\memdat[24:0] $memrd$\storage$ls180.v:5533$1497_DATA attribute \src "ls180.v:5531.2-5532.119" switch \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:5531.6-5531.55" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr assign $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w assign $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 25'1111111111111111111111111 case assign $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 3'xxx assign $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 25'xxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] update $memwr$\storage$ls180.v:5532$9_ADDR $0$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1491 update $memwr$\storage$ls180.v:5532$9_DATA $0$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1492 update $memwr$\storage$ls180.v:5532$9_EN $0$memwr$\storage$ls180.v:5532$9_EN[24:0]$1493 attribute \src "ls180.v:5532.3-5532.118" memwr \storage $1$memwr$\storage$ls180.v:5532$9_ADDR[2:0]$1494 $1$memwr$\storage$ls180.v:5532$9_DATA[24:0]$1495 $1$memwr$\storage$ls180.v:5532$9_EN[24:0]$1496 0' end attribute \src "ls180.v:5536.1-5537.4" process $proc$ls180.v:5536$1498 sync posedge \sys_clk_1 end attribute \src "ls180.v:554.5-554.39" process $proc$ls180.v:554$1763 assign { } { } assign $1\sdram_bankmachine1_row_open[0:0] 1'0 sync always sync init update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0] end attribute \src "ls180.v:5544.1-5548.4" process $proc$ls180.v:5544$1500 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1501 $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 assign $0$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1502 $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 assign $0$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1503 $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5547$1507_DATA attribute \src "ls180.v:5545.2-5546.121" switch \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:5545.6-5545.55" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr assign $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w assign $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 25'1111111111111111111111111 case assign $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 3'xxx assign $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 25'xxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] update $memwr$\storage_1$ls180.v:5546$10_ADDR $0$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1501 update $memwr$\storage_1$ls180.v:5546$10_DATA $0$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1502 update $memwr$\storage_1$ls180.v:5546$10_EN $0$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1503 attribute \src "ls180.v:5546.3-5546.120" memwr \storage_1 $1$memwr$\storage_1$ls180.v:5546$10_ADDR[2:0]$1504 $1$memwr$\storage_1$ls180.v:5546$10_DATA[24:0]$1505 $1$memwr$\storage_1$ls180.v:5546$10_EN[24:0]$1506 0' end attribute \src "ls180.v:555.5-555.40" process $proc$ls180.v:555$1764 assign { } { } assign $1\sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0] end attribute \src "ls180.v:5550.1-5551.4" process $proc$ls180.v:5550$1508 sync posedge \sys_clk_1 end attribute \src "ls180.v:5558.1-5562.4" process $proc$ls180.v:5558$1510 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1511 $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 assign $0$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1512 $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 assign $0$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1513 $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5561$1517_DATA attribute \src "ls180.v:5559.2-5560.121" switch \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:5559.6-5559.55" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr assign $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w assign $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 25'1111111111111111111111111 case assign $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 3'xxx assign $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 25'xxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] update $memwr$\storage_2$ls180.v:5560$11_ADDR $0$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1511 update $memwr$\storage_2$ls180.v:5560$11_DATA $0$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1512 update $memwr$\storage_2$ls180.v:5560$11_EN $0$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1513 attribute \src "ls180.v:5560.3-5560.120" memwr \storage_2 $1$memwr$\storage_2$ls180.v:5560$11_ADDR[2:0]$1514 $1$memwr$\storage_2$ls180.v:5560$11_DATA[24:0]$1515 $1$memwr$\storage_2$ls180.v:5560$11_EN[24:0]$1516 0' end attribute \src "ls180.v:556.5-556.49" process $proc$ls180.v:556$1765 assign { } { } assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:5564.1-5565.4" process $proc$ls180.v:5564$1518 sync posedge \sys_clk_1 end attribute \src "ls180.v:5572.1-5576.4" process $proc$ls180.v:5572$1520 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1521 $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 assign $0$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1522 $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 assign $0$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1523 $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5575$1527_DATA attribute \src "ls180.v:5573.2-5574.121" switch \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we attribute \src "ls180.v:5573.6-5573.55" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr assign $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w assign $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 25'1111111111111111111111111 case assign $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 3'xxx assign $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 25'xxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 25'0000000000000000000000000 end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] update $memwr$\storage_3$ls180.v:5574$12_ADDR $0$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1521 update $memwr$\storage_3$ls180.v:5574$12_DATA $0$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1522 update $memwr$\storage_3$ls180.v:5574$12_EN $0$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1523 attribute \src "ls180.v:5574.3-5574.120" memwr \storage_3 $1$memwr$\storage_3$ls180.v:5574$12_ADDR[2:0]$1524 $1$memwr$\storage_3$ls180.v:5574$12_DATA[24:0]$1525 $1$memwr$\storage_3$ls180.v:5574$12_EN[24:0]$1526 0' end attribute \src "ls180.v:5578.1-5579.4" process $proc$ls180.v:5578$1528 sync posedge \sys_clk_1 end attribute \src "ls180.v:558.32-558.71" process $proc$ls180.v:558$1766 assign { } { } assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0] end attribute \src "ls180.v:5587.1-5591.4" process $proc$ls180.v:5587$1530 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1531 $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 assign $0$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1532 $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 assign $0$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1533 $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5590$1537_DATA attribute \src "ls180.v:5588.2-5589.57" switch \tx_fifo_wrport_we attribute \src "ls180.v:5588.6-5588.23" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 \tx_fifo_wrport_adr assign $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 \tx_fifo_wrport_dat_w assign $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 10'1111111111 case assign $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 4'xxxx assign $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 10'xxxxxxxxxx assign $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 10'0000000000 end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] update $memwr$\storage_4$ls180.v:5589$13_ADDR $0$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1531 update $memwr$\storage_4$ls180.v:5589$13_DATA $0$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1532 update $memwr$\storage_4$ls180.v:5589$13_EN $0$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1533 attribute \src "ls180.v:5589.3-5589.56" memwr \storage_4 $1$memwr$\storage_4$ls180.v:5589$13_ADDR[3:0]$1534 $1$memwr$\storage_4$ls180.v:5589$13_DATA[9:0]$1535 $1$memwr$\storage_4$ls180.v:5589$13_EN[9:0]$1536 0' end attribute \src "ls180.v:559.11-559.50" process $proc$ls180.v:559$1767 assign { } { } assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always sync init update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0] end attribute \src "ls180.v:5593.1-5596.4" process $proc$ls180.v:5593$1538 assign $0\memdat_5[9:0] \memdat_5 attribute \src "ls180.v:5594.2-5595.45" switch \tx_fifo_rdport_re attribute \src "ls180.v:5594.6-5594.23" case 1'1 assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5595$1539_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end attribute \src "ls180.v:5604.1-5608.4" process $proc$ls180.v:5604$1540 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1541 $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 assign $0$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1542 $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 assign $0$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1543 $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5607$1547_DATA attribute \src "ls180.v:5605.2-5606.57" switch \rx_fifo_wrport_we attribute \src "ls180.v:5605.6-5605.23" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 \rx_fifo_wrport_adr assign $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 \rx_fifo_wrport_dat_w assign $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 10'1111111111 case assign $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 4'xxxx assign $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 10'xxxxxxxxxx assign $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 10'0000000000 end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] update $memwr$\storage_5$ls180.v:5606$14_ADDR $0$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1541 update $memwr$\storage_5$ls180.v:5606$14_DATA $0$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1542 update $memwr$\storage_5$ls180.v:5606$14_EN $0$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1543 attribute \src "ls180.v:5606.3-5606.56" memwr \storage_5 $1$memwr$\storage_5$ls180.v:5606$14_ADDR[3:0]$1544 $1$memwr$\storage_5$ls180.v:5606$14_DATA[9:0]$1545 $1$memwr$\storage_5$ls180.v:5606$14_EN[9:0]$1546 0' end attribute \src "ls180.v:561.32-561.70" process $proc$ls180.v:561$1768 assign { } { } assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0] sync init end attribute \src "ls180.v:5610.1-5613.4" process $proc$ls180.v:5610$1548 assign $0\memdat_7[9:0] \memdat_7 attribute \src "ls180.v:5611.2-5612.45" switch \rx_fifo_rdport_re attribute \src "ls180.v:5611.6-5611.23" case 1'1 assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5612$1549_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end attribute \src "ls180.v:563.32-563.71" process $proc$ls180.v:563$1769 assign { } { } assign $0\sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine1_trascon_ready $0\sdram_bankmachine1_trascon_ready[0:0] sync init end attribute \src "ls180.v:569.5-569.46" process $proc$ls180.v:569$1770 assign { } { } assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0] end attribute \src "ls180.v:570.5-570.46" process $proc$ls180.v:570$1771 assign { } { } assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0] end attribute \src "ls180.v:572.5-572.42" process $proc$ls180.v:572$1772 assign { } { } assign $1\sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine2_refresh_gnt $1\sdram_bankmachine2_refresh_gnt[0:0] end attribute \src "ls180.v:573.5-573.40" process $proc$ls180.v:573$1773 assign { } { } assign $1\sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_valid $1\sdram_bankmachine2_cmd_valid[0:0] end attribute \src "ls180.v:574.5-574.40" process $proc$ls180.v:574$1774 assign { } { } assign $1\sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_ready $1\sdram_bankmachine2_cmd_ready[0:0] end attribute \src "ls180.v:575.12-575.52" process $proc$ls180.v:575$1775 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine2_cmd_payload_a $1\sdram_bankmachine2_cmd_payload_a[12:0] end attribute \src "ls180.v:577.5-577.46" process $proc$ls180.v:577$1776 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_cas $1\sdram_bankmachine2_cmd_payload_cas[0:0] end attribute \src "ls180.v:578.5-578.46" process $proc$ls180.v:578$1777 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_ras $1\sdram_bankmachine2_cmd_payload_ras[0:0] end attribute \src "ls180.v:579.5-579.45" process $proc$ls180.v:579$1778 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_we $1\sdram_bankmachine2_cmd_payload_we[0:0] end attribute \src "ls180.v:580.5-580.49" process $proc$ls180.v:580$1779 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_is_cmd $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:581.5-581.50" process $proc$ls180.v:581$1780 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_is_read $1\sdram_bankmachine2_cmd_payload_is_read[0:0] end attribute \src "ls180.v:582.5-582.51" process $proc$ls180.v:582$1781 assign { } { } assign $1\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_payload_is_write $1\sdram_bankmachine2_cmd_payload_is_write[0:0] end attribute \src "ls180.v:583.5-583.45" process $proc$ls180.v:583$1782 assign { } { } assign $1\sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine2_auto_precharge $1\sdram_bankmachine2_auto_precharge[0:0] end attribute \src "ls180.v:586.5-586.62" process $proc$ls180.v:586$1783 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init end attribute \src "ls180.v:587.5-587.61" process $proc$ls180.v:587$1784 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init end attribute \src "ls180.v:59.5-59.41" process $proc$ls180.v:59$1557 assign { } { } assign $1\libresocsim_libresoc_dbus_ack[0:0] 1'0 sync always sync init update \libresocsim_libresoc_dbus_ack $1\libresocsim_libresoc_dbus_ack[0:0] end attribute \src "ls180.v:602.11-602.63" process $proc$ls180.v:602$1785 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_level $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:603.5-603.59" process $proc$ls180.v:603$1786 assign { } { } assign $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine2_cmd_buffer_lookahead_replace $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init end attribute \src "ls180.v:604.11-604.65" process $proc$ls180.v:604$1787 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_produce $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:605.11-605.65" process $proc$ls180.v:605$1788 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_consume $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:606.11-606.68" process $proc$ls180.v:606$1789 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:61.5-61.41" process $proc$ls180.v:61$1558 assign { } { } assign $0\libresocsim_libresoc_dbus_err[0:0] 1'0 sync always update \libresocsim_libresoc_dbus_err $0\libresocsim_libresoc_dbus_err[0:0] sync init end attribute \src "ls180.v:627.5-627.54" process $proc$ls180.v:627$1790 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_valid $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:629.5-629.54" process $proc$ls180.v:629$1791 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_first $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:630.5-630.53" process $proc$ls180.v:630$1792 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_last $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:631.5-631.59" process $proc$ls180.v:631$1793 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_payload_we $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:632.12-632.69" process $proc$ls180.v:632$1794 assign { } { } assign $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \sdram_bankmachine2_cmd_buffer_source_payload_addr $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:633.12-633.42" process $proc$ls180.v:633$1795 assign { } { } assign $1\sdram_bankmachine2_row[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine2_row $1\sdram_bankmachine2_row[12:0] end attribute \src "ls180.v:634.5-634.41" process $proc$ls180.v:634$1796 assign { } { } assign $1\sdram_bankmachine2_row_opened[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_opened $1\sdram_bankmachine2_row_opened[0:0] end attribute \src "ls180.v:636.5-636.39" process $proc$ls180.v:636$1797 assign { } { } assign $1\sdram_bankmachine2_row_open[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_open $1\sdram_bankmachine2_row_open[0:0] end attribute \src "ls180.v:637.5-637.40" process $proc$ls180.v:637$1798 assign { } { } assign $1\sdram_bankmachine2_row_close[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_close $1\sdram_bankmachine2_row_close[0:0] end attribute \src "ls180.v:638.5-638.49" process $proc$ls180.v:638$1799 assign { } { } assign $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \sdram_bankmachine2_row_col_n_addr_sel $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:640.32-640.71" process $proc$ls180.v:640$1800 assign { } { } assign $1\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine2_twtpcon_ready $1\sdram_bankmachine2_twtpcon_ready[0:0] end attribute \src "ls180.v:641.11-641.50" process $proc$ls180.v:641$1801 assign { } { } assign $1\sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always sync init update \sdram_bankmachine2_twtpcon_count $1\sdram_bankmachine2_twtpcon_count[2:0] end attribute \src "ls180.v:643.32-643.70" process $proc$ls180.v:643$1802 assign { } { } assign $0\sdram_bankmachine2_trccon_ready[0:0] 1'1 sync always update \sdram_bankmachine2_trccon_ready $0\sdram_bankmachine2_trccon_ready[0:0] sync init end attribute \src "ls180.v:645.32-645.71" process $proc$ls180.v:645$1803 assign { } { } assign $0\sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine2_trascon_ready $0\sdram_bankmachine2_trascon_ready[0:0] sync init end attribute \src "ls180.v:651.5-651.46" process $proc$ls180.v:651$1804 assign { } { } assign $1\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine3_req_wdata_ready $1\sdram_bankmachine3_req_wdata_ready[0:0] end attribute \src "ls180.v:652.5-652.46" process $proc$ls180.v:652$1805 assign { } { } assign $1\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine3_req_rdata_valid $1\sdram_bankmachine3_req_rdata_valid[0:0] end attribute \src "ls180.v:654.5-654.42" process $proc$ls180.v:654$1806 assign { } { } assign $1\sdram_bankmachine3_refresh_gnt[0:0] 1'0 sync always sync init update \sdram_bankmachine3_refresh_gnt $1\sdram_bankmachine3_refresh_gnt[0:0] end attribute \src "ls180.v:655.5-655.40" process $proc$ls180.v:655$1807 assign { } { } assign $1\sdram_bankmachine3_cmd_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_valid $1\sdram_bankmachine3_cmd_valid[0:0] end attribute \src "ls180.v:656.5-656.40" process $proc$ls180.v:656$1808 assign { } { } assign $1\sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_ready $1\sdram_bankmachine3_cmd_ready[0:0] end attribute \src "ls180.v:657.12-657.52" process $proc$ls180.v:657$1809 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine3_cmd_payload_a $1\sdram_bankmachine3_cmd_payload_a[12:0] end attribute \src "ls180.v:659.5-659.46" process $proc$ls180.v:659$1810 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_cas $1\sdram_bankmachine3_cmd_payload_cas[0:0] end attribute \src "ls180.v:660.5-660.46" process $proc$ls180.v:660$1811 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_ras $1\sdram_bankmachine3_cmd_payload_ras[0:0] end attribute \src "ls180.v:661.5-661.45" process $proc$ls180.v:661$1812 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_we $1\sdram_bankmachine3_cmd_payload_we[0:0] end attribute \src "ls180.v:662.5-662.49" process $proc$ls180.v:662$1813 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_is_cmd $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] end attribute \src "ls180.v:663.5-663.50" process $proc$ls180.v:663$1814 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_is_read $1\sdram_bankmachine3_cmd_payload_is_read[0:0] end attribute \src "ls180.v:664.5-664.51" process $proc$ls180.v:664$1815 assign { } { } assign $1\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_payload_is_write $1\sdram_bankmachine3_cmd_payload_is_write[0:0] end attribute \src "ls180.v:665.5-665.45" process $proc$ls180.v:665$1816 assign { } { } assign $1\sdram_bankmachine3_auto_precharge[0:0] 1'0 sync always sync init update \sdram_bankmachine3_auto_precharge $1\sdram_bankmachine3_auto_precharge[0:0] end attribute \src "ls180.v:668.5-668.62" process $proc$ls180.v:668$1817 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always update \sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init end attribute \src "ls180.v:669.5-669.61" process $proc$ls180.v:669$1818 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always update \sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init end attribute \src "ls180.v:68.5-68.41" process $proc$ls180.v:68$1559 assign { } { } assign $1\libresocsim_libresoc_ibus_ack[0:0] 1'0 sync always sync init update \libresocsim_libresoc_ibus_ack $1\libresocsim_libresoc_ibus_ack[0:0] end attribute \src "ls180.v:684.11-684.63" process $proc$ls180.v:684$1819 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_level $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end attribute \src "ls180.v:685.5-685.59" process $proc$ls180.v:685$1820 assign { } { } assign $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 sync always update \sdram_bankmachine3_cmd_buffer_lookahead_replace $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] sync init end attribute \src "ls180.v:686.11-686.65" process $proc$ls180.v:686$1821 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_produce $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end attribute \src "ls180.v:687.11-687.65" process $proc$ls180.v:687$1822 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_consume $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end attribute \src "ls180.v:688.11-688.68" process $proc$ls180.v:688$1823 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end attribute \src "ls180.v:70.5-70.41" process $proc$ls180.v:70$1560 assign { } { } assign $0\libresocsim_libresoc_ibus_err[0:0] 1'0 sync always update \libresocsim_libresoc_ibus_err $0\libresocsim_libresoc_ibus_err[0:0] sync init end attribute \src "ls180.v:709.5-709.54" process $proc$ls180.v:709$1824 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_valid $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] end attribute \src "ls180.v:711.5-711.54" process $proc$ls180.v:711$1825 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_first $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] end attribute \src "ls180.v:712.5-712.53" process $proc$ls180.v:712$1826 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_last $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] end attribute \src "ls180.v:713.5-713.59" process $proc$ls180.v:713$1827 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_payload_we $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end attribute \src "ls180.v:714.12-714.69" process $proc$ls180.v:714$1828 assign { } { } assign $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init update \sdram_bankmachine3_cmd_buffer_source_payload_addr $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end attribute \src "ls180.v:715.12-715.42" process $proc$ls180.v:715$1829 assign { } { } assign $1\sdram_bankmachine3_row[12:0] 13'0000000000000 sync always sync init update \sdram_bankmachine3_row $1\sdram_bankmachine3_row[12:0] end attribute \src "ls180.v:716.5-716.41" process $proc$ls180.v:716$1830 assign { } { } assign $1\sdram_bankmachine3_row_opened[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_opened $1\sdram_bankmachine3_row_opened[0:0] end attribute \src "ls180.v:718.5-718.39" process $proc$ls180.v:718$1831 assign { } { } assign $1\sdram_bankmachine3_row_open[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_open $1\sdram_bankmachine3_row_open[0:0] end attribute \src "ls180.v:719.5-719.40" process $proc$ls180.v:719$1832 assign { } { } assign $1\sdram_bankmachine3_row_close[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_close $1\sdram_bankmachine3_row_close[0:0] end attribute \src "ls180.v:720.5-720.49" process $proc$ls180.v:720$1833 assign { } { } assign $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always sync init update \sdram_bankmachine3_row_col_n_addr_sel $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] end attribute \src "ls180.v:722.32-722.71" process $proc$ls180.v:722$1834 assign { } { } assign $1\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always sync init update \sdram_bankmachine3_twtpcon_ready $1\sdram_bankmachine3_twtpcon_ready[0:0] end attribute \src "ls180.v:723.11-723.50" process $proc$ls180.v:723$1835 assign { } { } assign $1\sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always sync init update \sdram_bankmachine3_twtpcon_count $1\sdram_bankmachine3_twtpcon_count[2:0] end attribute \src "ls180.v:725.32-725.70" process $proc$ls180.v:725$1836 assign { } { } assign $0\sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always update \sdram_bankmachine3_trccon_ready $0\sdram_bankmachine3_trccon_ready[0:0] sync init end attribute \src "ls180.v:727.32-727.71" process $proc$ls180.v:727$1837 assign { } { } assign $0\sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always update \sdram_bankmachine3_trascon_ready $0\sdram_bankmachine3_trascon_ready[0:0] sync init end attribute \src "ls180.v:730.5-730.39" process $proc$ls180.v:730$1838 assign { } { } assign $0\sdram_choose_cmd_want_reads[0:0] 1'0 sync always update \sdram_choose_cmd_want_reads $0\sdram_choose_cmd_want_reads[0:0] sync init end attribute \src "ls180.v:731.5-731.40" process $proc$ls180.v:731$1839 assign { } { } assign $0\sdram_choose_cmd_want_writes[0:0] 1'0 sync always update \sdram_choose_cmd_want_writes $0\sdram_choose_cmd_want_writes[0:0] sync init end attribute \src "ls180.v:732.5-732.38" process $proc$ls180.v:732$1840 assign { } { } assign $0\sdram_choose_cmd_want_cmds[0:0] 1'0 sync always update \sdram_choose_cmd_want_cmds $0\sdram_choose_cmd_want_cmds[0:0] sync init end attribute \src "ls180.v:733.5-733.43" process $proc$ls180.v:733$1841 assign { } { } assign $0\sdram_choose_cmd_want_activates[0:0] 1'0 sync always update \sdram_choose_cmd_want_activates $0\sdram_choose_cmd_want_activates[0:0] sync init end attribute \src "ls180.v:735.5-735.38" process $proc$ls180.v:735$1842 assign { } { } assign $0\sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always update \sdram_choose_cmd_cmd_ready $0\sdram_choose_cmd_cmd_ready[0:0] sync init end attribute \src "ls180.v:738.5-738.44" process $proc$ls180.v:738$1843 assign { } { } assign $1\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_choose_cmd_cmd_payload_cas $1\sdram_choose_cmd_cmd_payload_cas[0:0] end attribute \src "ls180.v:739.5-739.44" process $proc$ls180.v:739$1844 assign { } { } assign $1\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_choose_cmd_cmd_payload_ras $1\sdram_choose_cmd_cmd_payload_ras[0:0] end attribute \src "ls180.v:740.5-740.43" process $proc$ls180.v:740$1845 assign { } { } assign $1\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_choose_cmd_cmd_payload_we $1\sdram_choose_cmd_cmd_payload_we[0:0] end attribute \src "ls180.v:744.11-744.41" process $proc$ls180.v:744$1846 assign { } { } assign $1\sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \sdram_choose_cmd_valids $1\sdram_choose_cmd_valids[3:0] end attribute \src "ls180.v:746.11-746.40" process $proc$ls180.v:746$1847 assign { } { } assign $1\sdram_choose_cmd_grant[1:0] 2'00 sync always sync init update \sdram_choose_cmd_grant $1\sdram_choose_cmd_grant[1:0] end attribute \src "ls180.v:748.5-748.39" process $proc$ls180.v:748$1848 assign { } { } assign $1\sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \sdram_choose_req_want_reads $1\sdram_choose_req_want_reads[0:0] end attribute \src "ls180.v:749.5-749.40" process $proc$ls180.v:749$1849 assign { } { } assign $1\sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \sdram_choose_req_want_writes $1\sdram_choose_req_want_writes[0:0] end attribute \src "ls180.v:751.5-751.43" process $proc$ls180.v:751$1850 assign { } { } assign $1\sdram_choose_req_want_activates[0:0] 1'0 sync always sync init update \sdram_choose_req_want_activates $1\sdram_choose_req_want_activates[0:0] end attribute \src "ls180.v:753.5-753.38" process $proc$ls180.v:753$1851 assign { } { } assign $1\sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_ready $1\sdram_choose_req_cmd_ready[0:0] end attribute \src "ls180.v:756.5-756.44" process $proc$ls180.v:756$1852 assign { } { } assign $1\sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_payload_cas $1\sdram_choose_req_cmd_payload_cas[0:0] end attribute \src "ls180.v:757.5-757.44" process $proc$ls180.v:757$1853 assign { } { } assign $1\sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_payload_ras $1\sdram_choose_req_cmd_payload_ras[0:0] end attribute \src "ls180.v:758.5-758.43" process $proc$ls180.v:758$1854 assign { } { } assign $1\sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \sdram_choose_req_cmd_payload_we $1\sdram_choose_req_cmd_payload_we[0:0] end attribute \src "ls180.v:762.11-762.41" process $proc$ls180.v:762$1855 assign { } { } assign $1\sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \sdram_choose_req_valids $1\sdram_choose_req_valids[3:0] end attribute \src "ls180.v:764.11-764.40" process $proc$ls180.v:764$1856 assign { } { } assign $1\sdram_choose_req_grant[1:0] 2'00 sync always sync init update \sdram_choose_req_grant $1\sdram_choose_req_grant[1:0] end attribute \src "ls180.v:766.12-766.31" process $proc$ls180.v:766$1857 assign { } { } assign $0\sdram_nop_a[12:0] 13'0000000000000 sync always update \sdram_nop_a $0\sdram_nop_a[12:0] sync init end attribute \src "ls180.v:767.11-767.30" process $proc$ls180.v:767$1858 assign { } { } assign $0\sdram_nop_ba[1:0] 2'00 sync always update \sdram_nop_ba $0\sdram_nop_ba[1:0] sync init end attribute \src "ls180.v:768.11-768.35" process $proc$ls180.v:768$1859 assign { } { } assign $1\sdram_steerer_sel[1:0] 2'00 sync always sync init update \sdram_steerer_sel $1\sdram_steerer_sel[1:0] end attribute \src "ls180.v:769.5-769.26" process $proc$ls180.v:769$1860 assign { } { } assign $0\sdram_steerer0[0:0] 1'1 sync always update \sdram_steerer0 $0\sdram_steerer0[0:0] sync init end attribute \src "ls180.v:770.5-770.26" process $proc$ls180.v:770$1861 assign { } { } assign $0\sdram_steerer1[0:0] 1'1 sync always update \sdram_steerer1 $0\sdram_steerer1[0:0] sync init end attribute \src "ls180.v:772.32-772.58" process $proc$ls180.v:772$1862 assign { } { } assign $0\sdram_trrdcon_ready[0:0] 1'1 sync always update \sdram_trrdcon_ready $0\sdram_trrdcon_ready[0:0] sync init end attribute \src "ls180.v:774.32-774.58" process $proc$ls180.v:774$1863 assign { } { } assign $0\sdram_tfawcon_ready[0:0] 1'1 sync always update \sdram_tfawcon_ready $0\sdram_tfawcon_ready[0:0] sync init end attribute \src "ls180.v:776.32-776.58" process $proc$ls180.v:776$1864 assign { } { } assign $1\sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \sdram_tccdcon_ready $1\sdram_tccdcon_ready[0:0] end attribute \src "ls180.v:777.5-777.31" process $proc$ls180.v:777$1865 assign { } { } assign $1\sdram_tccdcon_count[0:0] 1'0 sync always sync init update \sdram_tccdcon_count $1\sdram_tccdcon_count[0:0] end attribute \src "ls180.v:779.32-779.58" process $proc$ls180.v:779$1866 assign { } { } assign $1\sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \sdram_twtrcon_ready $1\sdram_twtrcon_ready[0:0] end attribute \src "ls180.v:780.11-780.37" process $proc$ls180.v:780$1867 assign { } { } assign $1\sdram_twtrcon_count[2:0] 3'000 sync always sync init update \sdram_twtrcon_count $1\sdram_twtrcon_count[2:0] end attribute \src "ls180.v:783.5-783.21" process $proc$ls180.v:783$1868 assign { } { } assign $1\sdram_en0[0:0] 1'0 sync always sync init update \sdram_en0 $1\sdram_en0[0:0] end attribute \src "ls180.v:785.11-785.29" process $proc$ls180.v:785$1869 assign { } { } assign $1\sdram_time0[4:0] 5'00000 sync always sync init update \sdram_time0 $1\sdram_time0[4:0] end attribute \src "ls180.v:786.5-786.21" process $proc$ls180.v:786$1870 assign { } { } assign $1\sdram_en1[0:0] 1'0 sync always sync init update \sdram_en1 $1\sdram_en1[0:0] end attribute \src "ls180.v:788.11-788.29" process $proc$ls180.v:788$1871 assign { } { } assign $1\sdram_time1[3:0] 4'0000 sync always sync init update \sdram_time1 $1\sdram_time1[3:0] end attribute \src "ls180.v:809.5-809.24" process $proc$ls180.v:809$1872 assign { } { } assign $1\wb_sdram_ack[0:0] 1'0 sync always sync init update \wb_sdram_ack $1\wb_sdram_ack[0:0] end attribute \src "ls180.v:813.5-813.24" process $proc$ls180.v:813$1873 assign { } { } assign $0\wb_sdram_err[0:0] 1'0 sync always update \wb_sdram_err $0\wb_sdram_err[0:0] sync init end attribute \src "ls180.v:814.12-814.35" process $proc$ls180.v:814$1874 assign { } { } assign $1\litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \litedram_wb_adr $1\litedram_wb_adr[29:0] end attribute \src "ls180.v:815.12-815.37" process $proc$ls180.v:815$1875 assign { } { } assign $1\litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \litedram_wb_dat_w $1\litedram_wb_dat_w[15:0] end attribute \src "ls180.v:817.11-817.33" process $proc$ls180.v:817$1876 assign { } { } assign $1\litedram_wb_sel[1:0] 2'00 sync always sync init update \litedram_wb_sel $1\litedram_wb_sel[1:0] end attribute \src "ls180.v:818.5-818.27" process $proc$ls180.v:818$1877 assign { } { } assign $1\litedram_wb_cyc[0:0] 1'0 sync always sync init update \litedram_wb_cyc $1\litedram_wb_cyc[0:0] end attribute \src "ls180.v:819.5-819.27" process $proc$ls180.v:819$1878 assign { } { } assign $1\litedram_wb_stb[0:0] 1'0 sync always sync init update \litedram_wb_stb $1\litedram_wb_stb[0:0] end attribute \src "ls180.v:821.5-821.26" process $proc$ls180.v:821$1879 assign { } { } assign $1\litedram_wb_we[0:0] 1'0 sync always sync init update \litedram_wb_we $1\litedram_wb_we[0:0] end attribute \src "ls180.v:822.5-822.26" process $proc$ls180.v:822$1880 assign { } { } assign $1\converter_skip[0:0] 1'0 sync always sync init update \converter_skip $1\converter_skip[0:0] end attribute \src "ls180.v:823.5-823.29" process $proc$ls180.v:823$1881 assign { } { } assign $1\converter_counter[0:0] 1'0 sync always sync init update \converter_counter $1\converter_counter[0:0] end attribute \src "ls180.v:825.12-825.35" process $proc$ls180.v:825$1882 assign { } { } assign $1\converter_dat_r[31:0] 0 sync always sync init update \converter_dat_r $1\converter_dat_r[31:0] end attribute \src "ls180.v:826.5-826.24" process $proc$ls180.v:826$1883 assign { } { } assign $1\cmd_consumed[0:0] 1'0 sync always sync init update \cmd_consumed $1\cmd_consumed[0:0] end attribute \src "ls180.v:827.5-827.26" process $proc$ls180.v:827$1884 assign { } { } assign $1\wdata_consumed[0:0] 1'0 sync always sync init update \wdata_consumed $1\wdata_consumed[0:0] end attribute \src "ls180.v:831.12-831.42" process $proc$ls180.v:831$1885 assign { } { } assign $1\uart_phy_storage[31:0] 9895604 sync always sync init update \uart_phy_storage $1\uart_phy_storage[31:0] end attribute \src "ls180.v:832.5-832.23" process $proc$ls180.v:832$1886 assign { } { } assign $1\uart_phy_re[0:0] 1'0 sync always sync init update \uart_phy_re $1\uart_phy_re[0:0] end attribute \src "ls180.v:834.5-834.31" process $proc$ls180.v:834$1887 assign { } { } assign $1\uart_phy_sink_ready[0:0] 1'0 sync always sync init update \uart_phy_sink_ready $1\uart_phy_sink_ready[0:0] end attribute \src "ls180.v:838.5-838.34" process $proc$ls180.v:838$1888 assign { } { } assign $1\uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init update \uart_phy_uart_clk_txen $1\uart_phy_uart_clk_txen[0:0] end attribute \src "ls180.v:839.12-839.49" process $proc$ls180.v:839$1889 assign { } { } assign $1\uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init update \uart_phy_phase_accumulator_tx $1\uart_phy_phase_accumulator_tx[31:0] end attribute \src "ls180.v:840.11-840.33" process $proc$ls180.v:840$1890 assign { } { } assign $1\uart_phy_tx_reg[7:0] 8'00000000 sync always sync init update \uart_phy_tx_reg $1\uart_phy_tx_reg[7:0] end attribute \src "ls180.v:841.11-841.38" process $proc$ls180.v:841$1891 assign { } { } assign $1\uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init update \uart_phy_tx_bitcount $1\uart_phy_tx_bitcount[3:0] end attribute \src "ls180.v:842.5-842.28" process $proc$ls180.v:842$1892 assign { } { } assign $1\uart_phy_tx_busy[0:0] 1'0 sync always sync init update \uart_phy_tx_busy $1\uart_phy_tx_busy[0:0] end attribute \src "ls180.v:843.5-843.33" process $proc$ls180.v:843$1893 assign { } { } assign $1\uart_phy_source_valid[0:0] 1'0 sync always sync init update \uart_phy_source_valid $1\uart_phy_source_valid[0:0] end attribute \src "ls180.v:845.5-845.33" process $proc$ls180.v:845$1894 assign { } { } assign $0\uart_phy_source_first[0:0] 1'0 sync always update \uart_phy_source_first $0\uart_phy_source_first[0:0] sync init end attribute \src "ls180.v:846.5-846.32" process $proc$ls180.v:846$1895 assign { } { } assign $0\uart_phy_source_last[0:0] 1'0 sync always update \uart_phy_source_last $0\uart_phy_source_last[0:0] sync init end attribute \src "ls180.v:847.11-847.46" process $proc$ls180.v:847$1896 assign { } { } assign $1\uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init update \uart_phy_source_payload_data $1\uart_phy_source_payload_data[7:0] end attribute \src "ls180.v:848.5-848.34" process $proc$ls180.v:848$1897 assign { } { } assign $1\uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init update \uart_phy_uart_clk_rxen $1\uart_phy_uart_clk_rxen[0:0] end attribute \src "ls180.v:849.12-849.49" process $proc$ls180.v:849$1898 assign { } { } assign $1\uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init update \uart_phy_phase_accumulator_rx $1\uart_phy_phase_accumulator_rx[31:0] end attribute \src "ls180.v:851.5-851.25" process $proc$ls180.v:851$1899 assign { } { } assign $1\uart_phy_rx_r[0:0] 1'0 sync always sync init update \uart_phy_rx_r $1\uart_phy_rx_r[0:0] end attribute \src "ls180.v:852.11-852.33" process $proc$ls180.v:852$1900 assign { } { } assign $1\uart_phy_rx_reg[7:0] 8'00000000 sync always sync init update \uart_phy_rx_reg $1\uart_phy_rx_reg[7:0] end attribute \src "ls180.v:853.11-853.38" process $proc$ls180.v:853$1901 assign { } { } assign $1\uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init update \uart_phy_rx_bitcount $1\uart_phy_rx_bitcount[3:0] end attribute \src "ls180.v:854.5-854.28" process $proc$ls180.v:854$1902 assign { } { } assign $1\uart_phy_rx_busy[0:0] 1'0 sync always sync init update \uart_phy_rx_busy $1\uart_phy_rx_busy[0:0] end attribute \src "ls180.v:865.5-865.22" process $proc$ls180.v:865$1903 assign { } { } assign $1\tx_pending[0:0] 1'0 sync always sync init update \tx_pending $1\tx_pending[0:0] end attribute \src "ls180.v:867.5-867.20" process $proc$ls180.v:867$1904 assign { } { } assign $1\tx_clear[0:0] 1'0 sync always sync init update \tx_clear $1\tx_clear[0:0] end attribute \src "ls180.v:868.5-868.26" process $proc$ls180.v:868$1905 assign { } { } assign $1\tx_old_trigger[0:0] 1'0 sync always sync init update \tx_old_trigger $1\tx_old_trigger[0:0] end attribute \src "ls180.v:870.5-870.22" process $proc$ls180.v:870$1906 assign { } { } assign $1\rx_pending[0:0] 1'0 sync always sync init update \rx_pending $1\rx_pending[0:0] end attribute \src "ls180.v:872.5-872.20" process $proc$ls180.v:872$1907 assign { } { } assign $1\rx_clear[0:0] 1'0 sync always sync init update \rx_clear $1\rx_clear[0:0] end attribute \src "ls180.v:873.5-873.26" process $proc$ls180.v:873$1908 assign { } { } assign $1\rx_old_trigger[0:0] 1'0 sync always sync init update \rx_old_trigger $1\rx_old_trigger[0:0] end attribute \src "ls180.v:877.11-877.39" process $proc$ls180.v:877$1909 assign { } { } assign $1\eventmanager_status_w[1:0] 2'00 sync always sync init update \eventmanager_status_w $1\eventmanager_status_w[1:0] end attribute \src "ls180.v:881.11-881.40" process $proc$ls180.v:881$1910 assign { } { } assign $1\eventmanager_pending_w[1:0] 2'00 sync always sync init update \eventmanager_pending_w $1\eventmanager_pending_w[1:0] end attribute \src "ls180.v:882.11-882.38" process $proc$ls180.v:882$1911 assign { } { } assign $1\eventmanager_storage[1:0] 2'00 sync always sync init update \eventmanager_storage $1\eventmanager_storage[1:0] end attribute \src "ls180.v:883.5-883.27" process $proc$ls180.v:883$1912 assign { } { } assign $1\eventmanager_re[0:0] 1'0 sync always sync init update \eventmanager_re $1\eventmanager_re[0:0] end attribute \src "ls180.v:900.5-900.30" process $proc$ls180.v:900$1913 assign { } { } assign $0\tx_fifo_sink_first[0:0] 1'0 sync always update \tx_fifo_sink_first $0\tx_fifo_sink_first[0:0] sync init end attribute \src "ls180.v:901.5-901.29" process $proc$ls180.v:901$1914 assign { } { } assign $0\tx_fifo_sink_last[0:0] 1'0 sync always update \tx_fifo_sink_last $0\tx_fifo_sink_last[0:0] sync init end attribute \src "ls180.v:909.5-909.28" process $proc$ls180.v:909$1915 assign { } { } assign $1\tx_fifo_readable[0:0] 1'0 sync always sync init update \tx_fifo_readable $1\tx_fifo_readable[0:0] end attribute \src "ls180.v:916.11-916.32" process $proc$ls180.v:916$1916 assign { } { } assign $1\tx_fifo_level0[4:0] 5'00000 sync always sync init update \tx_fifo_level0 $1\tx_fifo_level0[4:0] end attribute \src "ls180.v:917.5-917.27" process $proc$ls180.v:917$1917 assign { } { } assign $0\tx_fifo_replace[0:0] 1'0 sync always update \tx_fifo_replace $0\tx_fifo_replace[0:0] sync init end attribute \src "ls180.v:918.11-918.33" process $proc$ls180.v:918$1918 assign { } { } assign $1\tx_fifo_produce[3:0] 4'0000 sync always sync init update \tx_fifo_produce $1\tx_fifo_produce[3:0] end attribute \src "ls180.v:919.11-919.33" process $proc$ls180.v:919$1919 assign { } { } assign $1\tx_fifo_consume[3:0] 4'0000 sync always sync init update \tx_fifo_consume $1\tx_fifo_consume[3:0] end attribute \src "ls180.v:920.11-920.36" process $proc$ls180.v:920$1920 assign { } { } assign $1\tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \tx_fifo_wrport_adr $1\tx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:946.5-946.28" process $proc$ls180.v:946$1921 assign { } { } assign $1\rx_fifo_readable[0:0] 1'0 sync always sync init update \rx_fifo_readable $1\rx_fifo_readable[0:0] end attribute \src "ls180.v:953.11-953.32" process $proc$ls180.v:953$1922 assign { } { } assign $1\rx_fifo_level0[4:0] 5'00000 sync always sync init update \rx_fifo_level0 $1\rx_fifo_level0[4:0] end attribute \src "ls180.v:954.5-954.27" process $proc$ls180.v:954$1923 assign { } { } assign $0\rx_fifo_replace[0:0] 1'0 sync always update \rx_fifo_replace $0\rx_fifo_replace[0:0] sync init end attribute \src "ls180.v:955.11-955.33" process $proc$ls180.v:955$1924 assign { } { } assign $1\rx_fifo_produce[3:0] 4'0000 sync always sync init update \rx_fifo_produce $1\rx_fifo_produce[3:0] end attribute \src "ls180.v:956.11-956.33" process $proc$ls180.v:956$1925 assign { } { } assign $1\rx_fifo_consume[3:0] 4'0000 sync always sync init update \rx_fifo_consume $1\rx_fifo_consume[3:0] end attribute \src "ls180.v:957.11-957.36" process $proc$ls180.v:957$1926 assign { } { } assign $1\rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \rx_fifo_wrport_adr $1\rx_fifo_wrport_adr[3:0] end attribute \src "ls180.v:972.5-972.17" process $proc$ls180.v:972$1927 assign { } { } assign $0\reset[0:0] 1'0 sync always update \reset $0\reset[0:0] sync init end attribute \src "ls180.v:973.11-973.34" process $proc$ls180.v:973$1928 assign { } { } assign $1\gpio0_oe_storage[7:0] 8'00000000 sync always sync init update \gpio0_oe_storage $1\gpio0_oe_storage[7:0] end attribute \src "ls180.v:974.5-974.23" process $proc$ls180.v:974$1929 assign { } { } assign $1\gpio0_oe_re[0:0] 1'0 sync always sync init update \gpio0_oe_re $1\gpio0_oe_re[0:0] end attribute \src "ls180.v:975.11-975.30" process $proc$ls180.v:975$1930 assign { } { } assign $1\gpio0_status[7:0] 8'00000000 sync always sync init update \gpio0_status $1\gpio0_status[7:0] end attribute \src "ls180.v:977.11-977.35" process $proc$ls180.v:977$1931 assign { } { } assign $1\gpio0_out_storage[7:0] 8'00000000 sync always sync init update \gpio0_out_storage $1\gpio0_out_storage[7:0] end attribute \src "ls180.v:978.5-978.24" process $proc$ls180.v:978$1932 assign { } { } assign $1\gpio0_out_re[0:0] 1'0 sync always sync init update \gpio0_out_re $1\gpio0_out_re[0:0] end attribute \src "ls180.v:979.11-979.35" process $proc$ls180.v:979$1933 assign { } { } assign $1\gpio0_pads_gpio0i[7:0] 8'00000000 sync always sync init update \gpio0_pads_gpio0i $1\gpio0_pads_gpio0i[7:0] end attribute \src "ls180.v:980.11-980.35" process $proc$ls180.v:980$1934 assign { } { } assign $1\gpio0_pads_gpio0o[7:0] 8'00000000 sync always sync init update \gpio0_pads_gpio0o $1\gpio0_pads_gpio0o[7:0] end attribute \src "ls180.v:981.11-981.36" process $proc$ls180.v:981$1935 assign { } { } assign $1\gpio0_pads_gpio0oe[7:0] 8'00000000 sync always sync init update \gpio0_pads_gpio0oe $1\gpio0_pads_gpio0oe[7:0] end attribute \src "ls180.v:982.11-982.34" process $proc$ls180.v:982$1936 assign { } { } assign $1\gpio1_oe_storage[7:0] 8'00000000 sync always sync init update \gpio1_oe_storage $1\gpio1_oe_storage[7:0] end attribute \src "ls180.v:983.5-983.23" process $proc$ls180.v:983$1937 assign { } { } assign $1\gpio1_oe_re[0:0] 1'0 sync always sync init update \gpio1_oe_re $1\gpio1_oe_re[0:0] end attribute \src "ls180.v:984.11-984.30" process $proc$ls180.v:984$1938 assign { } { } assign $1\gpio1_status[7:0] 8'00000000 sync always sync init update \gpio1_status $1\gpio1_status[7:0] end attribute \src "ls180.v:986.11-986.35" process $proc$ls180.v:986$1939 assign { } { } assign $1\gpio1_out_storage[7:0] 8'00000000 sync always sync init update \gpio1_out_storage $1\gpio1_out_storage[7:0] end attribute \src "ls180.v:987.5-987.24" process $proc$ls180.v:987$1940 assign { } { } assign $1\gpio1_out_re[0:0] 1'0 sync always sync init update \gpio1_out_re $1\gpio1_out_re[0:0] end attribute \src "ls180.v:988.11-988.35" process $proc$ls180.v:988$1941 assign { } { } assign $1\gpio1_pads_gpio1i[7:0] 8'00000000 sync always sync init update \gpio1_pads_gpio1i $1\gpio1_pads_gpio1i[7:0] end attribute \src "ls180.v:989.11-989.35" process $proc$ls180.v:989$1942 assign { } { } assign $1\gpio1_pads_gpio1o[7:0] 8'00000000 sync always sync init update \gpio1_pads_gpio1o $1\gpio1_pads_gpio1o[7:0] end attribute \src "ls180.v:99.5-99.44" process $proc$ls180.v:99$1561 assign { } { } assign $1\libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 sync always sync init update \libresocsim_libresoc_jtag_wb_ack $1\libresocsim_libresoc_jtag_wb_ack[0:0] end attribute \src "ls180.v:990.11-990.36" process $proc$ls180.v:990$1943 assign { } { } assign $1\gpio1_pads_gpio1oe[7:0] 8'00000000 sync always sync init update \gpio1_pads_gpio1oe $1\gpio1_pads_gpio1oe[7:0] end attribute \src "ls180.v:991.11-991.26" process $proc$ls180.v:991$1944 assign { } { } assign $1\eint_tmp[2:0] 3'000 sync always sync init update \eint_tmp $1\eint_tmp[2:0] end attribute \src "ls180.v:993.12-993.25" process $proc$ls180.v:993$1945 assign { } { } assign $1\dummy[39:0] 40'0000000000000000000000000000000000000000 sync always sync init update \dummy $1\dummy[39:0] end attribute \src "ls180.v:997.11-997.29" process $proc$ls180.v:997$1946 assign { } { } assign $1\i2c_storage[2:0] 3'000 sync always sync init update \i2c_storage $1\i2c_storage[2:0] end attribute \src "ls180.v:998.5-998.18" process $proc$ls180.v:998$1947 assign { } { } assign $1\i2c_re[0:0] 1'0 sync always sync init update \i2c_re $1\i2c_re[0:0] end connect \libresocsim_libresoc_reset \libresocsim_reset connect \libresocsim_libresoc_jtag_tck \jtag_tck connect \libresocsim_libresoc_jtag_tms \jtag_tms connect \libresocsim_libresoc_jtag_tdi \jtag_tdi connect \jtag_tdo \libresocsim_libresoc_jtag_tdo connect \nc_1 \nc connect \libresocsim_bus_error \libresocsim_error connect \libresocsim_converter0_reset $not$ls180.v:1510$17_Y connect \libresocsim_libresoc_ibus_dat_r { \libresocsim_interface0_converted_interface_dat_r \libresocsim_converter0_dat_r [63:32] } connect \libresocsim_converter1_reset $not$ls180.v:1570$28_Y connect \libresocsim_libresoc_dbus_dat_r { \libresocsim_interface1_converted_interface_dat_r \libresocsim_converter1_dat_r [63:32] } connect \libresocsim_converter2_reset $not$ls180.v:1630$39_Y connect \libresocsim_libresoc_jtag_wb_dat_r { \libresocsim_interface2_converted_interface_dat_r \libresocsim_converter2_dat_r [63:32] } connect \libresocsim_reset \libresocsim_reset_re connect \libresocsim_bus_errors_status \libresocsim_bus_errors connect \libresocsim_adr \libresocsim_ram_bus_adr [6:0] connect \libresocsim_ram_bus_dat_r \libresocsim_dat_r connect \libresocsim_dat_w \libresocsim_ram_bus_dat_w connect \libresocsim_zero_trigger $ne$ls180.v:1702$63_Y connect \libresocsim_eventmanager_status_w \libresocsim_zero_status connect \libresocsim_eventmanager_pending_w \libresocsim_zero_pending connect \libresocsim_irq $and$ls180.v:1711$66_Y connect \libresocsim_zero_status \libresocsim_zero_trigger connect \ram_adr \ram_bus_ram_bus_adr [4:0] connect \ram_bus_ram_bus_dat_r \ram_dat_r connect \ram_dat_w \ram_bus_ram_bus_dat_w connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk connect \sys_rst_1 \int_rst connect \dfi_p0_address \sdram_master_p0_address connect \dfi_p0_bank \sdram_master_p0_bank connect \dfi_p0_cas_n \sdram_master_p0_cas_n connect \dfi_p0_cs_n \sdram_master_p0_cs_n connect \dfi_p0_ras_n \sdram_master_p0_ras_n connect \dfi_p0_we_n \sdram_master_p0_we_n connect \dfi_p0_cke \sdram_master_p0_cke connect \dfi_p0_odt \sdram_master_p0_odt connect \dfi_p0_reset_n \sdram_master_p0_reset_n connect \dfi_p0_act_n \sdram_master_p0_act_n connect \dfi_p0_wrdata \sdram_master_p0_wrdata connect \dfi_p0_wrdata_en \sdram_master_p0_wrdata_en connect \dfi_p0_wrdata_mask \sdram_master_p0_wrdata_mask connect \dfi_p0_rddata_en \sdram_master_p0_rddata_en connect \sdram_master_p0_rddata \dfi_p0_rddata connect \sdram_master_p0_rddata_valid \dfi_p0_rddata_valid connect \sdram_slave_p0_address \sdram_dfi_p0_address connect \sdram_slave_p0_bank \sdram_dfi_p0_bank connect \sdram_slave_p0_cas_n \sdram_dfi_p0_cas_n connect \sdram_slave_p0_cs_n \sdram_dfi_p0_cs_n connect \sdram_slave_p0_ras_n \sdram_dfi_p0_ras_n connect \sdram_slave_p0_we_n \sdram_dfi_p0_we_n connect \sdram_slave_p0_cke \sdram_dfi_p0_cke connect \sdram_slave_p0_odt \sdram_dfi_p0_odt connect \sdram_slave_p0_reset_n \sdram_dfi_p0_reset_n connect \sdram_slave_p0_act_n \sdram_dfi_p0_act_n connect \sdram_slave_p0_wrdata \sdram_dfi_p0_wrdata connect \sdram_slave_p0_wrdata_en \sdram_dfi_p0_wrdata_en connect \sdram_slave_p0_wrdata_mask \sdram_dfi_p0_wrdata_mask connect \sdram_slave_p0_rddata_en \sdram_dfi_p0_rddata_en connect \sdram_dfi_p0_rddata \sdram_slave_p0_rddata connect \sdram_dfi_p0_rddata_valid \sdram_slave_p0_rddata_valid connect \sdram_inti_p0_cke \sdram_cke_1 connect \sdram_inti_p0_odt \sdram_odt connect \sdram_inti_p0_reset_n \sdram_reset_n connect \sdram_inti_p0_address \sdram_address_storage connect \sdram_inti_p0_bank \sdram_baddress_storage connect \sdram_inti_p0_wrdata_en $and$ls180.v:1835$86_Y connect \sdram_inti_p0_rddata_en $and$ls180.v:1836$87_Y connect \sdram_inti_p0_wrdata \sdram_wrdata_storage connect \sdram_inti_p0_wrdata_mask 2'00 connect \sdram_bankmachine0_req_valid \sdram_interface_bank0_valid connect \sdram_interface_bank0_ready \sdram_bankmachine0_req_ready connect \sdram_bankmachine0_req_we \sdram_interface_bank0_we connect \sdram_bankmachine0_req_addr \sdram_interface_bank0_addr connect \sdram_interface_bank0_lock \sdram_bankmachine0_req_lock connect \sdram_interface_bank0_wdata_ready \sdram_bankmachine0_req_wdata_ready connect \sdram_interface_bank0_rdata_valid \sdram_bankmachine0_req_rdata_valid connect \sdram_bankmachine1_req_valid \sdram_interface_bank1_valid connect \sdram_interface_bank1_ready \sdram_bankmachine1_req_ready connect \sdram_bankmachine1_req_we \sdram_interface_bank1_we connect \sdram_bankmachine1_req_addr \sdram_interface_bank1_addr connect \sdram_interface_bank1_lock \sdram_bankmachine1_req_lock connect \sdram_interface_bank1_wdata_ready \sdram_bankmachine1_req_wdata_ready connect \sdram_interface_bank1_rdata_valid \sdram_bankmachine1_req_rdata_valid connect \sdram_bankmachine2_req_valid \sdram_interface_bank2_valid connect \sdram_interface_bank2_ready \sdram_bankmachine2_req_ready connect \sdram_bankmachine2_req_we \sdram_interface_bank2_we connect \sdram_bankmachine2_req_addr \sdram_interface_bank2_addr connect \sdram_interface_bank2_lock \sdram_bankmachine2_req_lock connect \sdram_interface_bank2_wdata_ready \sdram_bankmachine2_req_wdata_ready connect \sdram_interface_bank2_rdata_valid \sdram_bankmachine2_req_rdata_valid connect \sdram_bankmachine3_req_valid \sdram_interface_bank3_valid connect \sdram_interface_bank3_ready \sdram_bankmachine3_req_ready connect \sdram_bankmachine3_req_we \sdram_interface_bank3_we connect \sdram_bankmachine3_req_addr \sdram_interface_bank3_addr connect \sdram_interface_bank3_lock \sdram_bankmachine3_req_lock connect \sdram_interface_bank3_wdata_ready \sdram_bankmachine3_req_wdata_ready connect \sdram_interface_bank3_rdata_valid \sdram_bankmachine3_req_rdata_valid connect \sdram_timer_wait $not$ls180.v:1867$88_Y connect \sdram_postponer_req_i \sdram_timer_done0 connect \sdram_wants_refresh \sdram_postponer_req_o connect \sdram_timer_done1 $eq$ls180.v:1870$89_Y connect \sdram_timer_done0 \sdram_timer_done1 connect \sdram_timer_count0 \sdram_timer_count1 connect \sdram_sequencer_start1 $or$ls180.v:1873$91_Y connect \sdram_sequencer_done0 $and$ls180.v:1874$93_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \sdram_bankmachine0_req_valid connect \sdram_bankmachine0_req_ready \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine0_req_we connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine0_req_addr connect \sdram_bankmachine0_cmd_buffer_sink_valid \sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \sdram_bankmachine0_cmd_buffer_lookahead_source_ready \sdram_bankmachine0_cmd_buffer_sink_ready connect \sdram_bankmachine0_cmd_buffer_sink_first \sdram_bankmachine0_cmd_buffer_lookahead_source_first connect \sdram_bankmachine0_cmd_buffer_sink_last \sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \sdram_bankmachine0_cmd_buffer_sink_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine0_cmd_buffer_sink_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1916$95_Y connect \sdram_bankmachine0_req_lock $or$ls180.v:1917$96_Y connect \sdram_bankmachine0_row_hit $eq$ls180.v:1918$97_Y connect \sdram_bankmachine0_cmd_payload_ba 2'00 connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1928$102_Y connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1929$104_Y connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1930$106_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_sink_first connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_sink_last connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr connect \sdram_bankmachine0_cmd_buffer_lookahead_source_valid \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \sdram_bankmachine0_cmd_buffer_lookahead_source_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first connect \sdram_bankmachine0_cmd_buffer_lookahead_source_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1962$114_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1963$115_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine0_cmd_buffer_lookahead_consume connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1966$116_Y connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1967$117_Y connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1968$119_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \sdram_bankmachine1_req_valid connect \sdram_bankmachine1_req_ready \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine1_req_we connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine1_req_addr connect \sdram_bankmachine1_cmd_buffer_sink_valid \sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \sdram_bankmachine1_cmd_buffer_lookahead_source_ready \sdram_bankmachine1_cmd_buffer_sink_ready connect \sdram_bankmachine1_cmd_buffer_sink_first \sdram_bankmachine1_cmd_buffer_lookahead_source_first connect \sdram_bankmachine1_cmd_buffer_sink_last \sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \sdram_bankmachine1_cmd_buffer_sink_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine1_cmd_buffer_sink_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2073$125_Y connect \sdram_bankmachine1_req_lock $or$ls180.v:2074$126_Y connect \sdram_bankmachine1_row_hit $eq$ls180.v:2075$127_Y connect \sdram_bankmachine1_cmd_payload_ba 2'01 connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2085$132_Y connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2086$134_Y connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2087$136_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_sink_first connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_sink_last connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr connect \sdram_bankmachine1_cmd_buffer_lookahead_source_valid \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \sdram_bankmachine1_cmd_buffer_lookahead_source_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first connect \sdram_bankmachine1_cmd_buffer_lookahead_source_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2119$144_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2120$145_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine1_cmd_buffer_lookahead_consume connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2123$146_Y connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2124$147_Y connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2125$149_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \sdram_bankmachine2_req_valid connect \sdram_bankmachine2_req_ready \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine2_req_we connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine2_req_addr connect \sdram_bankmachine2_cmd_buffer_sink_valid \sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \sdram_bankmachine2_cmd_buffer_lookahead_source_ready \sdram_bankmachine2_cmd_buffer_sink_ready connect \sdram_bankmachine2_cmd_buffer_sink_first \sdram_bankmachine2_cmd_buffer_lookahead_source_first connect \sdram_bankmachine2_cmd_buffer_sink_last \sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \sdram_bankmachine2_cmd_buffer_sink_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine2_cmd_buffer_sink_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2230$155_Y connect \sdram_bankmachine2_req_lock $or$ls180.v:2231$156_Y connect \sdram_bankmachine2_row_hit $eq$ls180.v:2232$157_Y connect \sdram_bankmachine2_cmd_payload_ba 2'10 connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2242$162_Y connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2243$164_Y connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2244$166_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_sink_first connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_sink_last connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr connect \sdram_bankmachine2_cmd_buffer_lookahead_source_valid \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \sdram_bankmachine2_cmd_buffer_lookahead_source_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first connect \sdram_bankmachine2_cmd_buffer_lookahead_source_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2276$174_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2277$175_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine2_cmd_buffer_lookahead_consume connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2280$176_Y connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2281$177_Y connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2282$179_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \sdram_bankmachine3_req_valid connect \sdram_bankmachine3_req_ready \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine3_req_we connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine3_req_addr connect \sdram_bankmachine3_cmd_buffer_sink_valid \sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \sdram_bankmachine3_cmd_buffer_lookahead_source_ready \sdram_bankmachine3_cmd_buffer_sink_ready connect \sdram_bankmachine3_cmd_buffer_sink_first \sdram_bankmachine3_cmd_buffer_lookahead_source_first connect \sdram_bankmachine3_cmd_buffer_sink_last \sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \sdram_bankmachine3_cmd_buffer_sink_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \sdram_bankmachine3_cmd_buffer_sink_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2387$185_Y connect \sdram_bankmachine3_req_lock $or$ls180.v:2388$186_Y connect \sdram_bankmachine3_row_hit $eq$ls180.v:2389$187_Y connect \sdram_bankmachine3_cmd_payload_ba 2'11 connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2399$192_Y connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2400$194_Y connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2401$196_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_sink_first connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_sink_last connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr connect \sdram_bankmachine3_cmd_buffer_lookahead_source_valid \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \sdram_bankmachine3_cmd_buffer_lookahead_source_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first connect \sdram_bankmachine3_cmd_buffer_lookahead_source_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2433$204_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2434$205_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine3_cmd_buffer_lookahead_consume connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2437$206_Y connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2438$207_Y connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2439$209_Y connect \sdram_choose_req_want_cmds 1'1 connect \sdram_trrdcon_valid $and$ls180.v:2535$220_Y connect \sdram_tfawcon_valid $and$ls180.v:2536$226_Y connect \sdram_ras_allowed $and$ls180.v:2537$227_Y connect \sdram_tccdcon_valid $and$ls180.v:2538$230_Y connect \sdram_cas_allowed \sdram_tccdcon_ready connect \sdram_twtrcon_valid $and$ls180.v:2540$232_Y connect \sdram_read_available $or$ls180.v:2541$239_Y connect \sdram_write_available $or$ls180.v:2542$246_Y connect \sdram_max_time0 $eq$ls180.v:2543$247_Y connect \sdram_max_time1 $eq$ls180.v:2544$248_Y connect \sdram_bankmachine0_refresh_req \sdram_cmd_valid connect \sdram_bankmachine1_refresh_req \sdram_cmd_valid connect \sdram_bankmachine2_refresh_req \sdram_cmd_valid connect \sdram_bankmachine3_refresh_req \sdram_cmd_valid connect \sdram_go_to_refresh $and$ls180.v:2549$251_Y connect \sdram_interface_rdata \sdram_dfi_p0_rddata connect \sdram_dfi_p0_wrdata \sdram_interface_wdata connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2552$252_Y connect \sdram_choose_cmd_request \sdram_choose_cmd_valids connect \sdram_choose_cmd_cmd_valid \rhs_array_muxed0 connect \sdram_choose_cmd_cmd_payload_a \rhs_array_muxed1 connect \sdram_choose_cmd_cmd_payload_ba \rhs_array_muxed2 connect \sdram_choose_cmd_cmd_payload_is_read \rhs_array_muxed3 connect \sdram_choose_cmd_cmd_payload_is_write \rhs_array_muxed4 connect \sdram_choose_cmd_cmd_payload_is_cmd \rhs_array_muxed5 connect \sdram_choose_cmd_ce $or$ls180.v:2585$310_Y connect \sdram_choose_req_request \sdram_choose_req_valids connect \sdram_choose_req_cmd_valid \rhs_array_muxed6 connect \sdram_choose_req_cmd_payload_a \rhs_array_muxed7 connect \sdram_choose_req_cmd_payload_ba \rhs_array_muxed8 connect \sdram_choose_req_cmd_payload_is_read \rhs_array_muxed9 connect \sdram_choose_req_cmd_payload_is_write \rhs_array_muxed10 connect \sdram_choose_req_cmd_payload_is_cmd \rhs_array_muxed11 connect \sdram_choose_req_ce $or$ls180.v:2654$396_Y connect \sdram_dfi_p0_reset_n 1'1 connect \sdram_dfi_p0_cke \sdram_steerer0 connect \sdram_dfi_p0_odt \sdram_steerer1 connect \subfragments_roundrobin0_request $and$ls180.v:2731$428_Y connect \subfragments_roundrobin0_ce $and$ls180.v:2732$431_Y connect \sdram_interface_bank0_addr \rhs_array_muxed12 connect \sdram_interface_bank0_we \rhs_array_muxed13 connect \sdram_interface_bank0_valid \rhs_array_muxed14 connect \subfragments_roundrobin1_request $and$ls180.v:2736$444_Y connect \subfragments_roundrobin1_ce $and$ls180.v:2737$447_Y connect \sdram_interface_bank1_addr \rhs_array_muxed15 connect \sdram_interface_bank1_we \rhs_array_muxed16 connect \sdram_interface_bank1_valid \rhs_array_muxed17 connect \subfragments_roundrobin2_request $and$ls180.v:2741$460_Y connect \subfragments_roundrobin2_ce $and$ls180.v:2742$463_Y connect \sdram_interface_bank2_addr \rhs_array_muxed18 connect \sdram_interface_bank2_we \rhs_array_muxed19 connect \sdram_interface_bank2_valid \rhs_array_muxed20 connect \subfragments_roundrobin3_request $and$ls180.v:2746$476_Y connect \subfragments_roundrobin3_ce $and$ls180.v:2747$479_Y connect \sdram_interface_bank3_addr \rhs_array_muxed21 connect \sdram_interface_bank3_we \rhs_array_muxed22 connect \sdram_interface_bank3_valid \rhs_array_muxed23 connect \port_cmd_ready $or$ls180.v:2751$543_Y connect \port_wdata_ready \subfragments_new_master_wdata_ready connect \port_rdata_valid \subfragments_new_master_rdata_valid3 connect \port_rdata_payload_data \sdram_interface_rdata connect \subfragments_roundrobin0_grant 1'0 connect \subfragments_roundrobin1_grant 1'0 connect \subfragments_roundrobin2_grant 1'0 connect \subfragments_roundrobin3_grant 1'0 connect \converter_reset $not$ls180.v:2773$545_Y connect \wb_sdram_dat_r { \litedram_wb_dat_r \converter_dat_r [31:16] } connect \port_cmd_payload_addr $sub$ls180.v:2833$556_Y [23:0] connect \port_cmd_payload_we \litedram_wb_we connect \port_wdata_payload_data \litedram_wb_dat_w connect \port_wdata_payload_we \litedram_wb_sel connect \litedram_wb_dat_r \port_rdata_payload_data connect \port_flush $not$ls180.v:2838$557_Y connect \port_cmd_last $not$ls180.v:2839$558_Y connect \port_cmd_valid $and$ls180.v:2840$561_Y connect \port_wdata_valid $and$ls180.v:2841$565_Y connect \port_rdata_ready $and$ls180.v:2842$568_Y connect \litedram_wb_ack $and$ls180.v:2843$573_Y connect \ack_cmd $or$ls180.v:2844$575_Y connect \ack_wdata $or$ls180.v:2845$577_Y connect \ack_rdata $and$ls180.v:2846$578_Y connect \uart_sink_valid \uart_phy_source_valid connect \uart_phy_source_ready \uart_sink_ready connect \uart_sink_first \uart_phy_source_first connect \uart_sink_last \uart_phy_source_last connect \uart_sink_payload_data \uart_phy_source_payload_data connect \uart_phy_sink_valid \uart_source_valid connect \uart_source_ready \uart_phy_sink_ready connect \uart_phy_sink_first \uart_source_first connect \uart_phy_sink_last \uart_source_last connect \uart_phy_sink_payload_data \uart_source_payload_data connect \tx_fifo_sink_valid \rxtx_re connect \tx_fifo_sink_payload_data \rxtx_r connect \txfull_status $not$ls180.v:2859$579_Y connect \txempty_status $not$ls180.v:2860$580_Y connect \uart_source_valid \tx_fifo_source_valid connect \tx_fifo_source_ready \uart_source_ready connect \uart_source_first \tx_fifo_source_first connect \uart_source_last \tx_fifo_source_last connect \uart_source_payload_data \tx_fifo_source_payload_data connect \tx_trigger $not$ls180.v:2866$581_Y connect \rx_fifo_sink_valid \uart_sink_valid connect \uart_sink_ready \rx_fifo_sink_ready connect \rx_fifo_sink_first \uart_sink_first connect \rx_fifo_sink_last \uart_sink_last connect \rx_fifo_sink_payload_data \uart_sink_payload_data connect \rxempty_status $not$ls180.v:2872$582_Y connect \rxfull_status $not$ls180.v:2873$583_Y connect \rxtx_w \rx_fifo_source_payload_data connect \rx_fifo_source_ready $or$ls180.v:2875$585_Y connect \rx_trigger $not$ls180.v:2876$586_Y connect \irq $or$ls180.v:2899$595_Y connect \tx_status \tx_trigger connect \rx_status \rx_trigger connect \tx_fifo_syncfifo_din { \tx_fifo_fifo_in_last \tx_fifo_fifo_in_first \tx_fifo_fifo_in_payload_data } connect { \tx_fifo_fifo_out_last \tx_fifo_fifo_out_first \tx_fifo_fifo_out_payload_data } \tx_fifo_syncfifo_dout connect \tx_fifo_sink_ready \tx_fifo_syncfifo_writable connect \tx_fifo_syncfifo_we \tx_fifo_sink_valid connect \tx_fifo_fifo_in_first \tx_fifo_sink_first connect \tx_fifo_fifo_in_last \tx_fifo_sink_last connect \tx_fifo_fifo_in_payload_data \tx_fifo_sink_payload_data connect \tx_fifo_source_valid \tx_fifo_readable connect \tx_fifo_source_first \tx_fifo_fifo_out_first connect \tx_fifo_source_last \tx_fifo_fifo_out_last connect \tx_fifo_source_payload_data \tx_fifo_fifo_out_payload_data connect \tx_fifo_re \tx_fifo_source_ready connect \tx_fifo_syncfifo_re $and$ls180.v:2914$598_Y connect \tx_fifo_level1 $add$ls180.v:2915$599_Y connect \tx_fifo_wrport_dat_w \tx_fifo_syncfifo_din connect \tx_fifo_wrport_we $and$ls180.v:2925$603_Y connect \tx_fifo_do_read $and$ls180.v:2926$604_Y connect \tx_fifo_rdport_adr \tx_fifo_consume connect \tx_fifo_syncfifo_dout \tx_fifo_rdport_dat_r connect \tx_fifo_rdport_re \tx_fifo_do_read connect \tx_fifo_syncfifo_writable $ne$ls180.v:2930$605_Y connect \tx_fifo_syncfifo_readable $ne$ls180.v:2931$606_Y connect \rx_fifo_syncfifo_din { \rx_fifo_fifo_in_last \rx_fifo_fifo_in_first \rx_fifo_fifo_in_payload_data } connect { \rx_fifo_fifo_out_last \rx_fifo_fifo_out_first \rx_fifo_fifo_out_payload_data } \rx_fifo_syncfifo_dout connect \rx_fifo_sink_ready \rx_fifo_syncfifo_writable connect \rx_fifo_syncfifo_we \rx_fifo_sink_valid connect \rx_fifo_fifo_in_first \rx_fifo_sink_first connect \rx_fifo_fifo_in_last \rx_fifo_sink_last connect \rx_fifo_fifo_in_payload_data \rx_fifo_sink_payload_data connect \rx_fifo_source_valid \rx_fifo_readable connect \rx_fifo_source_first \rx_fifo_fifo_out_first connect \rx_fifo_source_last \rx_fifo_fifo_out_last connect \rx_fifo_source_payload_data \rx_fifo_fifo_out_payload_data connect \rx_fifo_re \rx_fifo_source_ready connect \rx_fifo_syncfifo_re $and$ls180.v:2944$609_Y connect \rx_fifo_level1 $add$ls180.v:2945$610_Y connect \rx_fifo_wrport_dat_w \rx_fifo_syncfifo_din connect \rx_fifo_wrport_we $and$ls180.v:2955$614_Y connect \rx_fifo_do_read $and$ls180.v:2956$615_Y connect \rx_fifo_rdport_adr \rx_fifo_consume connect \rx_fifo_syncfifo_dout \rx_fifo_rdport_dat_r connect \rx_fifo_rdport_re \rx_fifo_do_read connect \rx_fifo_syncfifo_writable $ne$ls180.v:2960$616_Y connect \rx_fifo_syncfifo_readable $ne$ls180.v:2961$617_Y connect \libresocsim_libresoc_constraintmanager_i2c_scl \i2c_scl_1 connect \libresocsim_libresoc_constraintmanager_i2c_sda_oe \i2c_oe connect \libresocsim_libresoc_constraintmanager_i2c_sda_o \i2c_sda0 connect \i2c_sda1 \libresocsim_libresoc_constraintmanager_i2c_sda_i connect \libresocsim_shared_adr \rhs_array_muxed24 connect \libresocsim_shared_dat_w \rhs_array_muxed25 connect \libresocsim_shared_sel \rhs_array_muxed26 connect \libresocsim_shared_cyc \rhs_array_muxed27 connect \libresocsim_shared_stb \rhs_array_muxed28 connect \libresocsim_shared_we \rhs_array_muxed29 connect \libresocsim_shared_cti \rhs_array_muxed30 connect \libresocsim_shared_bte \rhs_array_muxed31 connect \libresocsim_interface0_converted_interface_dat_r \libresocsim_shared_dat_r connect \libresocsim_interface1_converted_interface_dat_r \libresocsim_shared_dat_r connect \libresocsim_interface2_converted_interface_dat_r \libresocsim_shared_dat_r connect \libresocsim_interface0_converted_interface_ack $and$ls180.v:3074$627_Y connect \libresocsim_interface1_converted_interface_ack $and$ls180.v:3075$629_Y connect \libresocsim_interface2_converted_interface_ack $and$ls180.v:3076$631_Y connect \libresocsim_interface0_converted_interface_err $and$ls180.v:3077$633_Y connect \libresocsim_interface1_converted_interface_err $and$ls180.v:3078$635_Y connect \libresocsim_interface2_converted_interface_err $and$ls180.v:3079$637_Y connect \libresocsim_request { \libresocsim_interface2_converted_interface_cyc \libresocsim_interface1_converted_interface_cyc \libresocsim_interface0_converted_interface_cyc } connect \libresocsim_ram_bus_adr \libresocsim_shared_adr connect \libresocsim_ram_bus_dat_w \libresocsim_shared_dat_w connect \libresocsim_ram_bus_sel \libresocsim_shared_sel connect \libresocsim_ram_bus_stb \libresocsim_shared_stb connect \libresocsim_ram_bus_we \libresocsim_shared_we connect \libresocsim_ram_bus_cti \libresocsim_shared_cti connect \libresocsim_ram_bus_bte \libresocsim_shared_bte connect \ram_bus_ram_bus_adr \libresocsim_shared_adr connect \ram_bus_ram_bus_dat_w \libresocsim_shared_dat_w connect \ram_bus_ram_bus_sel \libresocsim_shared_sel connect \ram_bus_ram_bus_stb \libresocsim_shared_stb connect \ram_bus_ram_bus_we \libresocsim_shared_we connect \ram_bus_ram_bus_cti \libresocsim_shared_cti connect \ram_bus_ram_bus_bte \libresocsim_shared_bte connect \libresocsim_libresoc_xics_icp_adr \libresocsim_shared_adr connect \libresocsim_libresoc_xics_icp_dat_w \libresocsim_shared_dat_w connect \libresocsim_libresoc_xics_icp_sel \libresocsim_shared_sel connect \libresocsim_libresoc_xics_icp_stb \libresocsim_shared_stb connect \libresocsim_libresoc_xics_icp_we \libresocsim_shared_we connect \libresocsim_libresoc_xics_icp_cti \libresocsim_shared_cti connect \libresocsim_libresoc_xics_icp_bte \libresocsim_shared_bte connect \libresocsim_libresoc_xics_ics_adr \libresocsim_shared_adr connect \libresocsim_libresoc_xics_ics_dat_w \libresocsim_shared_dat_w connect \libresocsim_libresoc_xics_ics_sel \libresocsim_shared_sel connect \libresocsim_libresoc_xics_ics_stb \libresocsim_shared_stb connect \libresocsim_libresoc_xics_ics_we \libresocsim_shared_we connect \libresocsim_libresoc_xics_ics_cti \libresocsim_shared_cti connect \libresocsim_libresoc_xics_ics_bte \libresocsim_shared_bte connect \wb_sdram_adr \libresocsim_shared_adr connect \wb_sdram_dat_w \libresocsim_shared_dat_w connect \wb_sdram_sel \libresocsim_shared_sel connect \wb_sdram_stb \libresocsim_shared_stb connect \wb_sdram_we \libresocsim_shared_we connect \wb_sdram_cti \libresocsim_shared_cti connect \wb_sdram_bte \libresocsim_shared_bte connect \libresocsim_libresocsim_wishbone_adr \libresocsim_shared_adr connect \libresocsim_libresocsim_wishbone_dat_w \libresocsim_shared_dat_w connect \libresocsim_libresocsim_wishbone_sel \libresocsim_shared_sel connect \libresocsim_libresocsim_wishbone_stb \libresocsim_shared_stb connect \libresocsim_libresocsim_wishbone_we \libresocsim_shared_we connect \libresocsim_libresocsim_wishbone_cti \libresocsim_shared_cti connect \libresocsim_libresocsim_wishbone_bte \libresocsim_shared_bte connect \libresocsim_ram_bus_cyc $and$ls180.v:3132$645_Y connect \ram_bus_ram_bus_cyc $and$ls180.v:3133$646_Y connect \libresocsim_libresoc_xics_icp_cyc $and$ls180.v:3134$647_Y connect \libresocsim_libresoc_xics_ics_cyc $and$ls180.v:3135$648_Y connect \wb_sdram_cyc $and$ls180.v:3136$649_Y connect \libresocsim_libresocsim_wishbone_cyc $and$ls180.v:3137$650_Y connect \libresocsim_shared_err $or$ls180.v:3138$655_Y connect \libresocsim_wait $and$ls180.v:3139$658_Y connect \libresocsim_done $eq$ls180.v:3152$676_Y connect \libresocsim_csrbank0_sel $eq$ls180.v:3153$677_Y connect \libresocsim_csrbank0_reset0_r \libresocsim_interface0_bank_bus_dat_w [0] connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3155$680_Y connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3156$684_Y connect \libresocsim_csrbank0_scratch3_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3158$687_Y connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3159$691_Y connect \libresocsim_csrbank0_scratch2_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3161$694_Y connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3162$698_Y connect \libresocsim_csrbank0_scratch1_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3164$701_Y connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3165$705_Y connect \libresocsim_csrbank0_scratch0_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3167$708_Y connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3168$712_Y connect \libresocsim_csrbank0_bus_errors3_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3170$715_Y connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3171$719_Y connect \libresocsim_csrbank0_bus_errors2_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3173$722_Y connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3174$726_Y connect \libresocsim_csrbank0_bus_errors1_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3176$729_Y connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3177$733_Y connect \libresocsim_csrbank0_bus_errors0_r \libresocsim_interface0_bank_bus_dat_w connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3179$736_Y connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3180$740_Y connect \libresocsim_csrbank0_reset0_w \libresocsim_reset_storage connect \libresocsim_csrbank0_scratch3_w \libresocsim_scratch_storage [31:24] connect \libresocsim_csrbank0_scratch2_w \libresocsim_scratch_storage [23:16] connect \libresocsim_csrbank0_scratch1_w \libresocsim_scratch_storage [15:8] connect \libresocsim_csrbank0_scratch0_w \libresocsim_scratch_storage [7:0] connect \libresocsim_csrbank0_bus_errors3_w \libresocsim_bus_errors_status [31:24] connect \libresocsim_csrbank0_bus_errors2_w \libresocsim_bus_errors_status [23:16] connect \libresocsim_csrbank0_bus_errors1_w \libresocsim_bus_errors_status [15:8] connect \libresocsim_csrbank0_bus_errors0_w \libresocsim_bus_errors_status [7:0] connect \libresocsim_bus_errors_we \libresocsim_csrbank0_bus_errors0_we connect \libresocsim_csrbank1_sel $eq$ls180.v:3191$741_Y connect \libresocsim_csrbank1_oe0_r \libresocsim_interface1_bank_bus_dat_w connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3193$744_Y connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3194$748_Y connect \libresocsim_csrbank1_in_r \libresocsim_interface1_bank_bus_dat_w connect \libresocsim_csrbank1_in_re $and$ls180.v:3196$751_Y connect \libresocsim_csrbank1_in_we $and$ls180.v:3197$755_Y connect \libresocsim_csrbank1_out0_r \libresocsim_interface1_bank_bus_dat_w connect \libresocsim_csrbank1_out0_re $and$ls180.v:3199$758_Y connect \libresocsim_csrbank1_out0_we $and$ls180.v:3200$762_Y connect \libresocsim_csrbank1_oe0_w \gpio0_oe_storage connect \libresocsim_csrbank1_in_w \gpio0_status connect \gpio0_we \libresocsim_csrbank1_in_we connect \libresocsim_csrbank1_out0_w \gpio0_out_storage connect \libresocsim_csrbank2_sel $eq$ls180.v:3205$763_Y connect \libresocsim_csrbank2_oe0_r \libresocsim_interface2_bank_bus_dat_w connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3207$766_Y connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3208$770_Y connect \libresocsim_csrbank2_in_r \libresocsim_interface2_bank_bus_dat_w connect \libresocsim_csrbank2_in_re $and$ls180.v:3210$773_Y connect \libresocsim_csrbank2_in_we $and$ls180.v:3211$777_Y connect \libresocsim_csrbank2_out0_r \libresocsim_interface2_bank_bus_dat_w connect \libresocsim_csrbank2_out0_re $and$ls180.v:3213$780_Y connect \libresocsim_csrbank2_out0_we $and$ls180.v:3214$784_Y connect \libresocsim_csrbank2_oe0_w \gpio1_oe_storage connect \libresocsim_csrbank2_in_w \gpio1_status connect \gpio1_we \libresocsim_csrbank2_in_we connect \libresocsim_csrbank2_out0_w \gpio1_out_storage connect \libresocsim_csrbank3_sel $eq$ls180.v:3219$785_Y connect \libresocsim_csrbank3_w0_r \libresocsim_interface3_bank_bus_dat_w [2:0] connect \libresocsim_csrbank3_w0_re $and$ls180.v:3221$788_Y connect \libresocsim_csrbank3_w0_we $and$ls180.v:3222$792_Y connect \libresocsim_csrbank3_r_r \libresocsim_interface3_bank_bus_dat_w [0] connect \libresocsim_csrbank3_r_re $and$ls180.v:3224$795_Y connect \libresocsim_csrbank3_r_we $and$ls180.v:3225$799_Y connect \i2c_scl_1 \i2c_storage [0] connect \i2c_oe \i2c_storage [1] connect \i2c_sda0 \i2c_storage [2] connect \libresocsim_csrbank3_w0_w \i2c_storage connect \i2c_status \i2c_sda1 connect \libresocsim_csrbank3_r_w \i2c_status connect \i2c_we \libresocsim_csrbank3_r_we connect \libresocsim_csrbank4_sel $eq$ls180.v:3233$800_Y connect \libresocsim_csrbank4_dfii_control0_r \libresocsim_interface4_bank_bus_dat_w [3:0] connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3235$803_Y connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3236$807_Y connect \libresocsim_csrbank4_dfii_pi0_command0_r \libresocsim_interface4_bank_bus_dat_w [5:0] connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3238$810_Y connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3239$814_Y connect \sdram_command_issue_r \libresocsim_interface4_bank_bus_dat_w [0] connect \sdram_command_issue_re $and$ls180.v:3241$817_Y connect \sdram_command_issue_we $and$ls180.v:3242$821_Y connect \libresocsim_csrbank4_dfii_pi0_address1_r \libresocsim_interface4_bank_bus_dat_w [4:0] connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3244$824_Y connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3245$828_Y connect \libresocsim_csrbank4_dfii_pi0_address0_r \libresocsim_interface4_bank_bus_dat_w connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3247$831_Y connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3248$835_Y connect \libresocsim_csrbank4_dfii_pi0_baddress0_r \libresocsim_interface4_bank_bus_dat_w [1:0] connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3250$838_Y connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3251$842_Y connect \libresocsim_csrbank4_dfii_pi0_wrdata1_r \libresocsim_interface4_bank_bus_dat_w connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3253$845_Y connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3254$849_Y connect \libresocsim_csrbank4_dfii_pi0_wrdata0_r \libresocsim_interface4_bank_bus_dat_w connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3256$852_Y connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3257$856_Y connect \libresocsim_csrbank4_dfii_pi0_rddata1_r \libresocsim_interface4_bank_bus_dat_w connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3259$859_Y connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3260$863_Y connect \libresocsim_csrbank4_dfii_pi0_rddata0_r \libresocsim_interface4_bank_bus_dat_w connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3262$866_Y connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3263$870_Y connect \sdram_sel \sdram_storage [0] connect \sdram_cke_1 \sdram_storage [1] connect \sdram_odt \sdram_storage [2] connect \sdram_reset_n \sdram_storage [3] connect \libresocsim_csrbank4_dfii_control0_w \sdram_storage connect \libresocsim_csrbank4_dfii_pi0_command0_w \sdram_command_storage connect \libresocsim_csrbank4_dfii_pi0_address1_w \sdram_address_storage [12:8] connect \libresocsim_csrbank4_dfii_pi0_address0_w \sdram_address_storage [7:0] connect \libresocsim_csrbank4_dfii_pi0_baddress0_w \sdram_baddress_storage connect \libresocsim_csrbank4_dfii_pi0_wrdata1_w \sdram_wrdata_storage [15:8] connect \libresocsim_csrbank4_dfii_pi0_wrdata0_w \sdram_wrdata_storage [7:0] connect \libresocsim_csrbank4_dfii_pi0_rddata1_w \sdram_status [15:8] connect \libresocsim_csrbank4_dfii_pi0_rddata0_w \sdram_status [7:0] connect \sdram_we \libresocsim_csrbank4_dfii_pi0_rddata0_we connect \libresocsim_csrbank5_sel $eq$ls180.v:3278$871_Y connect \libresocsim_csrbank5_load3_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_load3_re $and$ls180.v:3280$874_Y connect \libresocsim_csrbank5_load3_we $and$ls180.v:3281$878_Y connect \libresocsim_csrbank5_load2_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_load2_re $and$ls180.v:3283$881_Y connect \libresocsim_csrbank5_load2_we $and$ls180.v:3284$885_Y connect \libresocsim_csrbank5_load1_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_load1_re $and$ls180.v:3286$888_Y connect \libresocsim_csrbank5_load1_we $and$ls180.v:3287$892_Y connect \libresocsim_csrbank5_load0_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_load0_re $and$ls180.v:3289$895_Y connect \libresocsim_csrbank5_load0_we $and$ls180.v:3290$899_Y connect \libresocsim_csrbank5_reload3_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3292$902_Y connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3293$906_Y connect \libresocsim_csrbank5_reload2_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3295$909_Y connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3296$913_Y connect \libresocsim_csrbank5_reload1_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3298$916_Y connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3299$920_Y connect \libresocsim_csrbank5_reload0_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3301$923_Y connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3302$927_Y connect \libresocsim_csrbank5_en0_r \libresocsim_interface5_bank_bus_dat_w [0] connect \libresocsim_csrbank5_en0_re $and$ls180.v:3304$930_Y connect \libresocsim_csrbank5_en0_we $and$ls180.v:3305$934_Y connect \libresocsim_csrbank5_update_value0_r \libresocsim_interface5_bank_bus_dat_w [0] connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3307$937_Y connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3308$941_Y connect \libresocsim_csrbank5_value3_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_value3_re $and$ls180.v:3310$944_Y connect \libresocsim_csrbank5_value3_we $and$ls180.v:3311$948_Y connect \libresocsim_csrbank5_value2_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_value2_re $and$ls180.v:3313$951_Y connect \libresocsim_csrbank5_value2_we $and$ls180.v:3314$955_Y connect \libresocsim_csrbank5_value1_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_value1_re $and$ls180.v:3316$958_Y connect \libresocsim_csrbank5_value1_we $and$ls180.v:3317$962_Y connect \libresocsim_csrbank5_value0_r \libresocsim_interface5_bank_bus_dat_w connect \libresocsim_csrbank5_value0_re $and$ls180.v:3319$965_Y connect \libresocsim_csrbank5_value0_we $and$ls180.v:3320$969_Y connect \libresocsim_eventmanager_status_r \libresocsim_interface5_bank_bus_dat_w [0] connect \libresocsim_eventmanager_status_re $and$ls180.v:3322$972_Y connect \libresocsim_eventmanager_status_we $and$ls180.v:3323$976_Y connect \libresocsim_eventmanager_pending_r \libresocsim_interface5_bank_bus_dat_w [0] connect \libresocsim_eventmanager_pending_re $and$ls180.v:3325$979_Y connect \libresocsim_eventmanager_pending_we $and$ls180.v:3326$983_Y connect \libresocsim_csrbank5_ev_enable0_r \libresocsim_interface5_bank_bus_dat_w [0] connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3328$986_Y connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3329$990_Y connect \libresocsim_csrbank5_load3_w \libresocsim_load_storage [31:24] connect \libresocsim_csrbank5_load2_w \libresocsim_load_storage [23:16] connect \libresocsim_csrbank5_load1_w \libresocsim_load_storage [15:8] connect \libresocsim_csrbank5_load0_w \libresocsim_load_storage [7:0] connect \libresocsim_csrbank5_reload3_w \libresocsim_reload_storage [31:24] connect \libresocsim_csrbank5_reload2_w \libresocsim_reload_storage [23:16] connect \libresocsim_csrbank5_reload1_w \libresocsim_reload_storage [15:8] connect \libresocsim_csrbank5_reload0_w \libresocsim_reload_storage [7:0] connect \libresocsim_csrbank5_en0_w \libresocsim_en_storage connect \libresocsim_csrbank5_update_value0_w \libresocsim_update_value_storage connect \libresocsim_csrbank5_value3_w \libresocsim_value_status [31:24] connect \libresocsim_csrbank5_value2_w \libresocsim_value_status [23:16] connect \libresocsim_csrbank5_value1_w \libresocsim_value_status [15:8] connect \libresocsim_csrbank5_value0_w \libresocsim_value_status [7:0] connect \libresocsim_value_we \libresocsim_csrbank5_value0_we connect \libresocsim_csrbank5_ev_enable0_w \libresocsim_eventmanager_storage connect \libresocsim_csrbank6_sel $eq$ls180.v:3346$991_Y connect \rxtx_r \libresocsim_interface6_bank_bus_dat_w connect \rxtx_re $and$ls180.v:3348$994_Y connect \rxtx_we $and$ls180.v:3349$998_Y connect \libresocsim_csrbank6_txfull_r \libresocsim_interface6_bank_bus_dat_w [0] connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3351$1001_Y connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3352$1005_Y connect \libresocsim_csrbank6_rxempty_r \libresocsim_interface6_bank_bus_dat_w [0] connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3354$1008_Y connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3355$1012_Y connect \eventmanager_status_r \libresocsim_interface6_bank_bus_dat_w [1:0] connect \eventmanager_status_re $and$ls180.v:3357$1015_Y connect \eventmanager_status_we $and$ls180.v:3358$1019_Y connect \eventmanager_pending_r \libresocsim_interface6_bank_bus_dat_w [1:0] connect \eventmanager_pending_re $and$ls180.v:3360$1022_Y connect \eventmanager_pending_we $and$ls180.v:3361$1026_Y connect \libresocsim_csrbank6_ev_enable0_r \libresocsim_interface6_bank_bus_dat_w [1:0] connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3363$1029_Y connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3364$1033_Y connect \libresocsim_csrbank6_txempty_r \libresocsim_interface6_bank_bus_dat_w [0] connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3366$1036_Y connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3367$1040_Y connect \libresocsim_csrbank6_rxfull_r \libresocsim_interface6_bank_bus_dat_w [0] connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3369$1043_Y connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3370$1047_Y connect \libresocsim_csrbank6_txfull_w \txfull_status connect \txfull_we \libresocsim_csrbank6_txfull_we connect \libresocsim_csrbank6_rxempty_w \rxempty_status connect \rxempty_we \libresocsim_csrbank6_rxempty_we connect \libresocsim_csrbank6_ev_enable0_w \eventmanager_storage connect \libresocsim_csrbank6_txempty_w \txempty_status connect \txempty_we \libresocsim_csrbank6_txempty_we connect \libresocsim_csrbank6_rxfull_w \rxfull_status connect \rxfull_we \libresocsim_csrbank6_rxfull_we connect \libresocsim_csrbank7_sel $eq$ls180.v:3380$1048_Y connect \libresocsim_csrbank7_tuning_word3_r \libresocsim_interface7_bank_bus_dat_w connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3382$1051_Y connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3383$1055_Y connect \libresocsim_csrbank7_tuning_word2_r \libresocsim_interface7_bank_bus_dat_w connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3385$1058_Y connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3386$1062_Y connect \libresocsim_csrbank7_tuning_word1_r \libresocsim_interface7_bank_bus_dat_w connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3388$1065_Y connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3389$1069_Y connect \libresocsim_csrbank7_tuning_word0_r \libresocsim_interface7_bank_bus_dat_w connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3391$1072_Y connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3392$1076_Y connect \libresocsim_csrbank7_tuning_word3_w \uart_phy_storage [31:24] connect \libresocsim_csrbank7_tuning_word2_w \uart_phy_storage [23:16] connect \libresocsim_csrbank7_tuning_word1_w \uart_phy_storage [15:8] connect \libresocsim_csrbank7_tuning_word0_w \uart_phy_storage [7:0] connect \libresocsim_csr_interconnect_adr \libresocsim_libresocsim_adr connect \libresocsim_csr_interconnect_we \libresocsim_libresocsim_we connect \libresocsim_csr_interconnect_dat_w \libresocsim_libresocsim_dat_w connect \libresocsim_libresocsim_dat_r \libresocsim_csr_interconnect_dat_r connect \libresocsim_interface0_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface1_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface2_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface3_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface4_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface5_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface6_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface7_bank_bus_adr \libresocsim_csr_interconnect_adr connect \libresocsim_interface0_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface1_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface2_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface3_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface4_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface5_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface6_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface7_bank_bus_we \libresocsim_csr_interconnect_we connect \libresocsim_interface0_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface1_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface2_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface3_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface4_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface5_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface6_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_interface7_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3425$1083_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 connect \sdrio_clk_3 \sys_clk_1 connect \sdrio_clk_4 \sys_clk_1 connect \sdrio_clk_5 \sys_clk_1 connect \sdrio_clk_6 \sys_clk_1 connect \sdrio_clk_7 \sys_clk_1 connect \sdrio_clk_8 \sys_clk_1 connect \sdrio_clk_9 \sys_clk_1 connect \sdrio_clk_10 \sys_clk_1 connect \sdrio_clk_11 \sys_clk_1 connect \sdrio_clk_12 \sys_clk_1 connect \sdrio_clk_13 \sys_clk_1 connect \sdrio_clk_14 \sys_clk_1 connect \sdrio_clk_15 \sys_clk_1 connect \sdrio_clk_16 \sys_clk_1 connect \sdrio_clk_17 \sys_clk_1 connect \sdrio_clk_18 \sys_clk_1 connect \sdrio_clk_19 \sys_clk_1 connect \sdrio_clk_20 \sys_clk_1 connect \sdrio_clk_21 \sys_clk_1 connect \sdrio_clk_22 \sys_clk_1 connect \sdrio_clk_23 \sys_clk_1 connect \sdrio_clk_24 \sys_clk_1 connect \sdrio_clk_25 \sys_clk_1 connect \sdrio_clk_26 \sys_clk_1 connect \sdrio_clk_27 \sys_clk_1 connect \sdrio_clk_28 \sys_clk_1 connect \sdrio_clk_29 \sys_clk_1 connect \sdrio_clk_30 \sys_clk_1 connect \sdrio_clk_31 \sys_clk_1 connect \sdrio_clk_32 \sys_clk_1 connect \sdrio_clk_33 \sys_clk_1 connect \sdrio_clk_34 \sys_clk_1 connect \sdrio_clk_35 \sys_clk_1 connect \sdrio_clk_36 \sys_clk_1 connect \sdrio_clk_37 \sys_clk_1 connect \sdrio_clk_38 \sys_clk_1 connect \sdrio_clk_39 \sys_clk_1 connect \sdrio_clk_40 \sys_clk_1 connect \sdrio_clk_41 \sys_clk_1 connect \sdrio_clk_42 \sys_clk_1 connect \sdrio_clk_43 \sys_clk_1 connect \sdrio_clk_44 \sys_clk_1 connect \sdrio_clk_45 \sys_clk_1 connect \sdrio_clk_46 \sys_clk_1 connect \sdrio_clk_47 \sys_clk_1 connect \sdrio_clk_48 \sys_clk_1 connect \sdrio_clk_49 \sys_clk_1 connect \sdrio_clk_50 \sys_clk_1 connect \sdrio_clk_51 \sys_clk_1 connect \sdrio_clk_52 \sys_clk_1 connect \sdrio_clk_53 \sys_clk_1 connect \sdrio_clk_54 \sys_clk_1 connect \sdrio_clk_55 \sys_clk_1 connect \uart_phy_rx \regs1 connect \sdrio_clk_56 \sys_clk_1 connect \sdrio_clk_57 \sys_clk_1 connect \sdrio_clk_58 \sys_clk_1 connect \sdrio_clk_59 \sys_clk_1 connect \sdrio_clk_60 \sys_clk_1 connect \sdrio_clk_61 \sys_clk_1 connect \sdrio_clk_62 \sys_clk_1 connect \sdrio_clk_63 \sys_clk_1 connect \sdrio_clk_64 \sys_clk_1 connect \sdrio_clk_65 \sys_clk_1 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 connect \sdrio_clk_69 \sys_clk_1 connect \sdrio_clk_70 \sys_clk_1 connect \sdrio_clk_71 \sys_clk_1 connect \sdrio_clk_72 \sys_clk_1 connect \sdrio_clk_73 \sys_clk_1 connect \sdrio_clk_74 \sys_clk_1 connect \sdrio_clk_75 \sys_clk_1 connect \sdrio_clk_76 \sys_clk_1 connect \sdrio_clk_77 \sys_clk_1 connect \sdrio_clk_78 \sys_clk_1 connect \sdrio_clk_79 \sys_clk_1 connect \sdrio_clk_80 \sys_clk_1 connect \sdrio_clk_81 \sys_clk_1 connect \sdrio_clk_82 \sys_clk_1 connect \sdrio_clk_83 \sys_clk_1 connect \sdrio_clk_84 \sys_clk_1 connect \sdrio_clk_85 \sys_clk_1 connect \sdrio_clk_86 \sys_clk_1 connect \sdrio_clk_87 \sys_clk_1 connect \sdrio_clk_88 \sys_clk_1 connect \sdrio_clk_89 \sys_clk_1 connect \sdrio_clk_90 \sys_clk_1 connect \sdrio_clk_91 \sys_clk_1 connect \sdrio_clk_92 \sys_clk_1 connect \sdrio_clk_93 \sys_clk_1 connect \sdrio_clk_94 \sys_clk_1 connect \sdrio_clk_95 \sys_clk_1 connect \sdrio_clk_96 \sys_clk_1 connect \sdrio_clk_97 \sys_clk_1 connect \sdrio_clk_98 \sys_clk_1 connect \sdrio_clk_99 \sys_clk_1 connect \sdrio_clk_100 \sys_clk_1 connect \sdrio_clk_101 \sys_clk_1 connect \sdrio_clk_102 \sys_clk_1 connect \sdrio_clk_103 \sys_clk_1 connect \libresocsim_dat_r $memrd$\mem$ls180.v:5502$1463_DATA connect \ram_dat_r $memrd$\mem_1$ls180.v:5522$1489_DATA connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5540$1499_DATA connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5554$1509_DATA connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5568$1519_DATA connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5582$1529_DATA connect \tx_fifo_wrport_dat_r \memdat_4 connect \tx_fifo_rdport_dat_r \memdat_5 connect \rx_fifo_wrport_dat_r \memdat_6 connect \rx_fifo_rdport_dat_r \memdat_7 end attribute \src "libresoc.v:146901.1-146959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l attribute \src "libresoc.v:146902.7-146902.20" wire $0\initial[0:0] attribute \src "libresoc.v:146947.3-146955.6" wire $0\q_int$next[0:0]$7081 attribute \src "libresoc.v:146945.3-146946.27" wire $0\q_int[0:0] attribute \src "libresoc.v:146947.3-146955.6" wire $1\q_int$next[0:0]$7082 attribute \src "libresoc.v:146924.7-146924.19" wire $1\q_int[0:0] attribute \src "libresoc.v:146937.17-146937.96" wire $and$libresoc.v:146937$7071_Y attribute \src "libresoc.v:146942.17-146942.96" wire $and$libresoc.v:146942$7076_Y attribute \src "libresoc.v:146939.18-146939.93" wire $not$libresoc.v:146939$7073_Y attribute \src "libresoc.v:146941.17-146941.92" wire $not$libresoc.v:146941$7075_Y attribute \src "libresoc.v:146944.17-146944.92" wire $not$libresoc.v:146944$7078_Y attribute \src "libresoc.v:146938.18-146938.98" wire $or$libresoc.v:146938$7072_Y attribute \src "libresoc.v:146940.18-146940.99" wire $or$libresoc.v:146940$7074_Y attribute \src "libresoc.v:146943.17-146943.97" wire $or$libresoc.v:146943$7077_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:146902.7-146902.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:146937$7071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:146937$7071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:146942$7076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:146942$7076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:146939$7073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd connect \Y $not$libresoc.v:146939$7073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:146941$7075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd connect \Y $not$libresoc.v:146941$7075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:146944$7078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd connect \Y $not$libresoc.v:146944$7078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:146938$7072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd connect \Y $or$libresoc.v:146938$7072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:146940$7074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int connect \Y $or$libresoc.v:146940$7074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:146943$7077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd connect \Y $or$libresoc.v:146943$7077_Y end attribute \src "libresoc.v:146902.7-146902.20" process $proc$libresoc.v:146902$7083 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:146924.7-146924.19" process $proc$libresoc.v:146924$7084 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:146945.3-146946.27" process $proc$libresoc.v:146945$7079 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:146947.3-146955.6" process $proc$libresoc.v:146947$7080 assign { } { } assign { } { } assign $0\q_int$next[0:0]$7081 $1\q_int$next[0:0]$7082 attribute \src "libresoc.v:146948.5-146948.29" switch \initial attribute \src "libresoc.v:146948.9-146948.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$7082 1'0 case assign $1\q_int$next[0:0]$7082 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$7081 end connect \$9 $and$libresoc.v:146937$7071_Y connect \$11 $or$libresoc.v:146938$7072_Y connect \$13 $not$libresoc.v:146939$7073_Y connect \$15 $or$libresoc.v:146940$7074_Y connect \$1 $not$libresoc.v:146941$7075_Y connect \$3 $and$libresoc.v:146942$7076_Y connect \$5 $or$libresoc.v:146943$7077_Y connect \$7 $not$libresoc.v:146944$7078_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end attribute \src "libresoc.v:146963.1-147497.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $0\dbus__adr$next[44:0]$7170 attribute \src "libresoc.v:147201.3-147202.35" wire width 45 $0\dbus__adr[44:0] attribute \src "libresoc.v:147211.3-147238.6" wire $0\dbus__cyc$next[0:0]$7144 attribute \src "libresoc.v:147209.3-147210.35" wire $0\dbus__cyc[0:0] attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $0\dbus__dat_w$next[63:0]$7180 attribute \src "libresoc.v:147197.3-147198.39" wire width 64 $0\dbus__dat_w[63:0] attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $0\dbus__sel$next[7:0]$7158 attribute \src "libresoc.v:147205.3-147206.35" wire width 8 $0\dbus__sel[7:0] attribute \src "libresoc.v:147239.3-147266.6" wire $0\dbus__stb$next[0:0]$7150 attribute \src "libresoc.v:147207.3-147208.35" wire $0\dbus__stb[0:0] attribute \src "libresoc.v:147377.3-147402.6" wire $0\dbus__we$next[0:0]$7175 attribute \src "libresoc.v:147199.3-147200.33" wire $0\dbus__we[0:0] attribute \src "libresoc.v:146964.7-146964.20" wire $0\initial[0:0] attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $0\m_badaddr_o$next[44:0]$7195 attribute \src "libresoc.v:147191.3-147192.39" wire width 45 $0\m_badaddr_o[44:0] attribute \src "libresoc.v:147277.3-147294.6" wire $0\m_busy_o[0:0] attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $0\m_ld_data_o$next[63:0]$7164 attribute \src "libresoc.v:147203.3-147204.39" wire width 64 $0\m_ld_data_o[63:0] attribute \src "libresoc.v:147429.3-147451.6" wire $0\m_load_err_o$next[0:0]$7185 attribute \src "libresoc.v:147195.3-147196.41" wire $0\m_load_err_o[0:0] attribute \src "libresoc.v:147452.3-147474.6" wire $0\m_store_err_o$next[0:0]$7190 attribute \src "libresoc.v:147193.3-147194.43" wire $0\m_store_err_o[0:0] attribute \src "libresoc.v:147267.3-147276.6" wire $0\x_busy_o[0:0] attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $1\dbus__adr$next[44:0]$7171 attribute \src "libresoc.v:147069.14-147069.42" wire width 45 $1\dbus__adr[44:0] attribute \src "libresoc.v:147211.3-147238.6" wire $1\dbus__cyc$next[0:0]$7145 attribute \src "libresoc.v:147074.7-147074.23" wire $1\dbus__cyc[0:0] attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $1\dbus__dat_w$next[63:0]$7181 attribute \src "libresoc.v:147081.14-147081.48" wire width 64 $1\dbus__dat_w[63:0] attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $1\dbus__sel$next[7:0]$7159 attribute \src "libresoc.v:147088.13-147088.30" wire width 8 $1\dbus__sel[7:0] attribute \src "libresoc.v:147239.3-147266.6" wire $1\dbus__stb$next[0:0]$7151 attribute \src "libresoc.v:147093.7-147093.23" wire $1\dbus__stb[0:0] attribute \src "libresoc.v:147377.3-147402.6" wire $1\dbus__we$next[0:0]$7176 attribute \src "libresoc.v:147098.7-147098.22" wire $1\dbus__we[0:0] attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $1\m_badaddr_o$next[44:0]$7196 attribute \src "libresoc.v:147102.14-147102.44" wire width 45 $1\m_badaddr_o[44:0] attribute \src "libresoc.v:147277.3-147294.6" wire $1\m_busy_o[0:0] attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $1\m_ld_data_o$next[63:0]$7165 attribute \src "libresoc.v:147109.14-147109.48" wire width 64 $1\m_ld_data_o[63:0] attribute \src "libresoc.v:147429.3-147451.6" wire $1\m_load_err_o$next[0:0]$7186 attribute \src "libresoc.v:147113.7-147113.26" wire $1\m_load_err_o[0:0] attribute \src "libresoc.v:147452.3-147474.6" wire $1\m_store_err_o$next[0:0]$7191 attribute \src "libresoc.v:147119.7-147119.27" wire $1\m_store_err_o[0:0] attribute \src "libresoc.v:147267.3-147276.6" wire $1\x_busy_o[0:0] attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $2\dbus__adr$next[44:0]$7172 attribute \src "libresoc.v:147211.3-147238.6" wire $2\dbus__cyc$next[0:0]$7146 attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $2\dbus__dat_w$next[63:0]$7182 attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $2\dbus__sel$next[7:0]$7160 attribute \src "libresoc.v:147239.3-147266.6" wire $2\dbus__stb$next[0:0]$7152 attribute \src "libresoc.v:147377.3-147402.6" wire $2\dbus__we$next[0:0]$7177 attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $2\m_badaddr_o$next[44:0]$7197 attribute \src "libresoc.v:147277.3-147294.6" wire $2\m_busy_o[0:0] attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $2\m_ld_data_o$next[63:0]$7166 attribute \src "libresoc.v:147429.3-147451.6" wire $2\m_load_err_o$next[0:0]$7187 attribute \src "libresoc.v:147452.3-147474.6" wire $2\m_store_err_o$next[0:0]$7192 attribute \src "libresoc.v:147351.3-147376.6" wire width 45 $3\dbus__adr$next[44:0]$7173 attribute \src "libresoc.v:147211.3-147238.6" wire $3\dbus__cyc$next[0:0]$7147 attribute \src "libresoc.v:147403.3-147428.6" wire width 64 $3\dbus__dat_w$next[63:0]$7183 attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $3\dbus__sel$next[7:0]$7161 attribute \src "libresoc.v:147239.3-147266.6" wire $3\dbus__stb$next[0:0]$7153 attribute \src "libresoc.v:147377.3-147402.6" wire $3\dbus__we$next[0:0]$7178 attribute \src "libresoc.v:147475.3-147494.6" wire width 45 $3\m_badaddr_o$next[44:0]$7198 attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $3\m_ld_data_o$next[63:0]$7167 attribute \src "libresoc.v:147429.3-147451.6" wire $3\m_load_err_o$next[0:0]$7188 attribute \src "libresoc.v:147452.3-147474.6" wire $3\m_store_err_o$next[0:0]$7193 attribute \src "libresoc.v:147211.3-147238.6" wire $4\dbus__cyc$next[0:0]$7148 attribute \src "libresoc.v:147295.3-147325.6" wire width 8 $4\dbus__sel$next[7:0]$7162 attribute \src "libresoc.v:147239.3-147266.6" wire $4\dbus__stb$next[0:0]$7154 attribute \src "libresoc.v:147326.3-147350.6" wire width 64 $4\m_ld_data_o$next[63:0]$7168 attribute \src "libresoc.v:147147.18-147147.116" wire $and$libresoc.v:147147$7089_Y attribute \src "libresoc.v:147150.18-147150.111" wire $and$libresoc.v:147150$7092_Y attribute \src "libresoc.v:147155.18-147155.116" wire $and$libresoc.v:147155$7097_Y attribute \src "libresoc.v:147157.18-147157.111" wire $and$libresoc.v:147157$7099_Y attribute \src "libresoc.v:147159.17-147159.114" wire $and$libresoc.v:147159$7101_Y attribute \src "libresoc.v:147163.18-147163.116" wire $and$libresoc.v:147163$7105_Y attribute \src "libresoc.v:147165.18-147165.111" wire $and$libresoc.v:147165$7107_Y attribute \src "libresoc.v:147171.18-147171.116" wire $and$libresoc.v:147171$7113_Y attribute \src "libresoc.v:147173.18-147173.111" wire $and$libresoc.v:147173$7115_Y attribute \src "libresoc.v:147175.18-147175.116" wire $and$libresoc.v:147175$7117_Y attribute \src "libresoc.v:147177.18-147177.111" wire $and$libresoc.v:147177$7119_Y attribute \src "libresoc.v:147179.18-147179.116" wire $and$libresoc.v:147179$7121_Y attribute \src "libresoc.v:147181.17-147181.108" wire $and$libresoc.v:147181$7123_Y attribute \src "libresoc.v:147182.18-147182.111" wire $and$libresoc.v:147182$7124_Y attribute \src "libresoc.v:147183.18-147183.120" wire $and$libresoc.v:147183$7125_Y attribute \src "libresoc.v:147186.18-147186.120" wire $and$libresoc.v:147186$7128_Y attribute \src "libresoc.v:147188.18-147188.120" wire $and$libresoc.v:147188$7130_Y attribute \src "libresoc.v:147144.18-147144.110" wire $not$libresoc.v:147144$7086_Y attribute \src "libresoc.v:147149.18-147149.110" wire $not$libresoc.v:147149$7091_Y attribute \src "libresoc.v:147152.18-147152.110" wire $not$libresoc.v:147152$7094_Y attribute \src "libresoc.v:147156.18-147156.110" wire $not$libresoc.v:147156$7098_Y attribute \src "libresoc.v:147160.18-147160.110" wire $not$libresoc.v:147160$7102_Y attribute \src "libresoc.v:147164.18-147164.110" wire $not$libresoc.v:147164$7106_Y attribute \src "libresoc.v:147167.18-147167.110" wire $not$libresoc.v:147167$7109_Y attribute \src "libresoc.v:147170.17-147170.109" wire $not$libresoc.v:147170$7112_Y attribute \src "libresoc.v:147172.18-147172.110" wire $not$libresoc.v:147172$7114_Y attribute \src "libresoc.v:147176.18-147176.110" wire $not$libresoc.v:147176$7118_Y attribute \src "libresoc.v:147180.18-147180.110" wire $not$libresoc.v:147180$7122_Y attribute \src "libresoc.v:147184.18-147184.110" wire $not$libresoc.v:147184$7126_Y attribute \src "libresoc.v:147185.18-147185.109" wire $not$libresoc.v:147185$7127_Y attribute \src "libresoc.v:147187.18-147187.110" wire $not$libresoc.v:147187$7129_Y attribute \src "libresoc.v:147189.18-147189.110" wire $not$libresoc.v:147189$7131_Y attribute \src "libresoc.v:147143.17-147143.119" wire $or$libresoc.v:147143$7085_Y attribute \src "libresoc.v:147145.18-147145.110" wire $or$libresoc.v:147145$7087_Y attribute \src "libresoc.v:147146.18-147146.114" wire $or$libresoc.v:147146$7088_Y attribute \src "libresoc.v:147148.17-147148.113" wire $or$libresoc.v:147148$7090_Y attribute \src "libresoc.v:147151.18-147151.120" wire $or$libresoc.v:147151$7093_Y attribute \src "libresoc.v:147153.18-147153.111" wire $or$libresoc.v:147153$7095_Y attribute \src "libresoc.v:147154.18-147154.114" wire $or$libresoc.v:147154$7096_Y attribute \src "libresoc.v:147158.18-147158.120" wire $or$libresoc.v:147158$7100_Y attribute \src "libresoc.v:147161.18-147161.111" wire $or$libresoc.v:147161$7103_Y attribute \src "libresoc.v:147162.18-147162.114" wire $or$libresoc.v:147162$7104_Y attribute \src "libresoc.v:147166.18-147166.120" wire $or$libresoc.v:147166$7108_Y attribute \src "libresoc.v:147168.18-147168.111" wire $or$libresoc.v:147168$7110_Y attribute \src "libresoc.v:147169.18-147169.114" wire $or$libresoc.v:147169$7111_Y attribute \src "libresoc.v:147174.18-147174.114" wire $or$libresoc.v:147174$7116_Y attribute \src "libresoc.v:147178.18-147178.114" wire $or$libresoc.v:147178$7120_Y attribute \src "libresoc.v:147190.18-147190.127" wire $or$libresoc.v:147190$7132_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" wire \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 21 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 45 output 18 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 45 \dbus__adr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 12 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__cyc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 input 17 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 output 20 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 \dbus__dat_w$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 14 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 8 output 16 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 8 \dbus__sel$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 15 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__stb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next attribute \src "libresoc.v:146964.7-146964.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" wire \m_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 output 4 \m_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 \m_ld_data_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" wire \m_load_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" wire \m_load_err_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" wire \m_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" wire \m_store_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" wire \m_store_err_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" wire input 9 \m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 11 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 input 3 \x_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" wire output 6 \x_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" wire input 7 \x_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" wire width 8 input 2 \x_mask_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" wire width 64 input 5 \x_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" wire input 8 \x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:56" wire \x_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147147$7089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i connect \Y $and$libresoc.v:147147$7089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147150$7092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 connect \Y $and$libresoc.v:147150$7092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147155$7097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i connect \Y $and$libresoc.v:147155$7097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147157$7099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 connect \Y $and$libresoc.v:147157$7099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147159$7101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i connect \Y $and$libresoc.v:147159$7101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147163$7105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i connect \Y $and$libresoc.v:147163$7105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147165$7107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 connect \Y $and$libresoc.v:147165$7107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147171$7113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i connect \Y $and$libresoc.v:147171$7113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147173$7115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 connect \Y $and$libresoc.v:147173$7115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147175$7117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i connect \Y $and$libresoc.v:147175$7117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147177$7119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 connect \Y $and$libresoc.v:147177$7119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147179$7121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i connect \Y $and$libresoc.v:147179$7121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147181$7123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 connect \Y $and$libresoc.v:147181$7123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $and $and$libresoc.v:147182$7124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 connect \Y $and$libresoc.v:147182$7124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" cell $and $and$libresoc.v:147183$7125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err connect \Y $and$libresoc.v:147183$7125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" cell $and $and$libresoc.v:147186$7128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err connect \Y $and$libresoc.v:147186$7128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" cell $and $and$libresoc.v:147188$7130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err connect \Y $and$libresoc.v:147188$7130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $not $not$libresoc.v:147144$7086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i connect \Y $not$libresoc.v:147144$7086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $not $not$libresoc.v:147149$7091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i connect \Y $not$libresoc.v:147149$7091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $not $not$libresoc.v:147152$7094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i connect \Y $not$libresoc.v:147152$7094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $not $not$libresoc.v:147156$7098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i connect \Y $not$libresoc.v:147156$7098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $not $not$libresoc.v:147160$7102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i connect \Y $not$libresoc.v:147160$7102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $not $not$libresoc.v:147164$7106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i connect \Y $not$libresoc.v:147164$7106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $not $not$libresoc.v:147167$7109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i connect \Y $not$libresoc.v:147167$7109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $not $not$libresoc.v:147170$7112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i connect \Y $not$libresoc.v:147170$7112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $not $not$libresoc.v:147172$7114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i connect \Y $not$libresoc.v:147172$7114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $not $not$libresoc.v:147176$7118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i connect \Y $not$libresoc.v:147176$7118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $not $not$libresoc.v:147180$7122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i connect \Y $not$libresoc.v:147180$7122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" cell $not $not$libresoc.v:147184$7126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i connect \Y $not$libresoc.v:147184$7126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" cell $not $not$libresoc.v:147185$7127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we connect \Y $not$libresoc.v:147185$7127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" cell $not $not$libresoc.v:147187$7129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i connect \Y $not$libresoc.v:147187$7129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" cell $not $not$libresoc.v:147189$7131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i connect \Y $not$libresoc.v:147189$7131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147143$7085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err connect \Y $or$libresoc.v:147143$7085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147145$7087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 connect \Y $or$libresoc.v:147145$7087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $or $or$libresoc.v:147146$7088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i connect \Y $or$libresoc.v:147146$7088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $or $or$libresoc.v:147148$7090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i connect \Y $or$libresoc.v:147148$7090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147151$7093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err connect \Y $or$libresoc.v:147151$7093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147153$7095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 connect \Y $or$libresoc.v:147153$7095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $or $or$libresoc.v:147154$7096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i connect \Y $or$libresoc.v:147154$7096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147158$7100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err connect \Y $or$libresoc.v:147158$7100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147161$7103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 connect \Y $or$libresoc.v:147161$7103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $or $or$libresoc.v:147162$7104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i connect \Y $or$libresoc.v:147162$7104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147166$7108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err connect \Y $or$libresoc.v:147166$7108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" cell $or $or$libresoc.v:147168$7110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 connect \Y $or$libresoc.v:147168$7110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $or $or$libresoc.v:147169$7111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i connect \Y $or$libresoc.v:147169$7111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $or $or$libresoc.v:147174$7116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i connect \Y $or$libresoc.v:147174$7116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" cell $or $or$libresoc.v:147178$7120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i connect \Y $or$libresoc.v:147178$7120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" cell $or $or$libresoc.v:147190$7132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o connect \Y $or$libresoc.v:147190$7132_Y end attribute \src "libresoc.v:146964.7-146964.20" process $proc$libresoc.v:146964$7199 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:147069.14-147069.42" process $proc$libresoc.v:147069$7200 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end attribute \src "libresoc.v:147074.7-147074.23" process $proc$libresoc.v:147074$7201 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end attribute \src "libresoc.v:147081.14-147081.48" process $proc$libresoc.v:147081$7202 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end attribute \src "libresoc.v:147088.13-147088.30" process $proc$libresoc.v:147088$7203 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end attribute \src "libresoc.v:147093.7-147093.23" process $proc$libresoc.v:147093$7204 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end attribute \src "libresoc.v:147098.7-147098.22" process $proc$libresoc.v:147098$7205 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end attribute \src "libresoc.v:147102.14-147102.44" process $proc$libresoc.v:147102$7206 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end attribute \src "libresoc.v:147109.14-147109.48" process $proc$libresoc.v:147109$7207 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end attribute \src "libresoc.v:147113.7-147113.26" process $proc$libresoc.v:147113$7208 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end attribute \src "libresoc.v:147119.7-147119.27" process $proc$libresoc.v:147119$7209 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end attribute \src "libresoc.v:147191.3-147192.39" process $proc$libresoc.v:147191$7133 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end attribute \src "libresoc.v:147193.3-147194.43" process $proc$libresoc.v:147193$7134 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end attribute \src "libresoc.v:147195.3-147196.41" process $proc$libresoc.v:147195$7135 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end attribute \src "libresoc.v:147197.3-147198.39" process $proc$libresoc.v:147197$7136 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end attribute \src "libresoc.v:147199.3-147200.33" process $proc$libresoc.v:147199$7137 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end attribute \src "libresoc.v:147201.3-147202.35" process $proc$libresoc.v:147201$7138 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end attribute \src "libresoc.v:147203.3-147204.39" process $proc$libresoc.v:147203$7139 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end attribute \src "libresoc.v:147205.3-147206.35" process $proc$libresoc.v:147205$7140 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end attribute \src "libresoc.v:147207.3-147208.35" process $proc$libresoc.v:147207$7141 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end attribute \src "libresoc.v:147209.3-147210.35" process $proc$libresoc.v:147209$7142 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end attribute \src "libresoc.v:147211.3-147238.6" process $proc$libresoc.v:147211$7143 assign { } { } assign { } { } assign { } { } assign $0\dbus__cyc$next[0:0]$7144 $4\dbus__cyc$next[0:0]$7148 attribute \src "libresoc.v:147212.5-147212.29" switch \initial attribute \src "libresoc.v:147212.9-147212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbus__cyc$next[0:0]$7145 $2\dbus__cyc$next[0:0]$7146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\dbus__cyc$next[0:0]$7146 $3\dbus__cyc$next[0:0]$7147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dbus__cyc$next[0:0]$7147 1'0 case assign $3\dbus__cyc$next[0:0]$7147 \dbus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\dbus__cyc$next[0:0]$7146 1'1 case assign $2\dbus__cyc$next[0:0]$7146 \dbus__cyc end case assign $1\dbus__cyc$next[0:0]$7145 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\dbus__cyc$next[0:0]$7148 1'0 case assign $4\dbus__cyc$next[0:0]$7148 $1\dbus__cyc$next[0:0]$7145 end sync always update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7144 end attribute \src "libresoc.v:147239.3-147266.6" process $proc$libresoc.v:147239$7149 assign { } { } assign { } { } assign { } { } assign $0\dbus__stb$next[0:0]$7150 $4\dbus__stb$next[0:0]$7154 attribute \src "libresoc.v:147240.5-147240.29" switch \initial attribute \src "libresoc.v:147240.9-147240.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbus__stb$next[0:0]$7151 $2\dbus__stb$next[0:0]$7152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\dbus__stb$next[0:0]$7152 $3\dbus__stb$next[0:0]$7153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dbus__stb$next[0:0]$7153 1'0 case assign $3\dbus__stb$next[0:0]$7153 \dbus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\dbus__stb$next[0:0]$7152 1'1 case assign $2\dbus__stb$next[0:0]$7152 \dbus__stb end case assign $1\dbus__stb$next[0:0]$7151 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\dbus__stb$next[0:0]$7154 1'0 case assign $4\dbus__stb$next[0:0]$7154 $1\dbus__stb$next[0:0]$7151 end sync always update \dbus__stb$next $0\dbus__stb$next[0:0]$7150 end attribute \src "libresoc.v:147267.3-147276.6" process $proc$libresoc.v:147267$7155 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] attribute \src "libresoc.v:147268.5-147268.29" switch \initial attribute \src "libresoc.v:147268.9-147268.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\x_busy_o[0:0] \dbus__cyc case assign $1\x_busy_o[0:0] 1'0 end sync always update \x_busy_o $0\x_busy_o[0:0] end attribute \src "libresoc.v:147277.3-147294.6" process $proc$libresoc.v:147277$7156 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] attribute \src "libresoc.v:147278.5-147278.29" switch \initial attribute \src "libresoc.v:147278.9-147278.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\m_busy_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\m_busy_o[0:0] \dbus__cyc end case assign $1\m_busy_o[0:0] 1'0 end sync always update \m_busy_o $0\m_busy_o[0:0] end attribute \src "libresoc.v:147295.3-147325.6" process $proc$libresoc.v:147295$7157 assign { } { } assign { } { } assign { } { } assign $0\dbus__sel$next[7:0]$7158 $4\dbus__sel$next[7:0]$7162 attribute \src "libresoc.v:147296.5-147296.29" switch \initial attribute \src "libresoc.v:147296.9-147296.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbus__sel$next[7:0]$7159 $2\dbus__sel$next[7:0]$7160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$35 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\dbus__sel$next[7:0]$7160 $3\dbus__sel$next[7:0]$7161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dbus__sel$next[7:0]$7161 8'00000000 case assign $3\dbus__sel$next[7:0]$7161 \dbus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\dbus__sel$next[7:0]$7160 \x_mask_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\dbus__sel$next[7:0]$7160 8'00000000 end case assign $1\dbus__sel$next[7:0]$7159 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\dbus__sel$next[7:0]$7162 8'00000000 case assign $4\dbus__sel$next[7:0]$7162 $1\dbus__sel$next[7:0]$7159 end sync always update \dbus__sel$next $0\dbus__sel$next[7:0]$7158 end attribute \src "libresoc.v:147326.3-147350.6" process $proc$libresoc.v:147326$7163 assign { } { } assign { } { } assign { } { } assign $0\m_ld_data_o$next[63:0]$7164 $4\m_ld_data_o$next[63:0]$7168 attribute \src "libresoc.v:147327.5-147327.29" switch \initial attribute \src "libresoc.v:147327.9-147327.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\m_ld_data_o$next[63:0]$7165 $2\m_ld_data_o$next[63:0]$7166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\m_ld_data_o$next[63:0]$7166 $3\m_ld_data_o$next[63:0]$7167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\m_ld_data_o$next[63:0]$7167 \dbus__dat_r case assign $3\m_ld_data_o$next[63:0]$7167 \m_ld_data_o end case assign $2\m_ld_data_o$next[63:0]$7166 \m_ld_data_o end case assign $1\m_ld_data_o$next[63:0]$7165 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\m_ld_data_o$next[63:0]$7168 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $4\m_ld_data_o$next[63:0]$7168 $1\m_ld_data_o$next[63:0]$7165 end sync always update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7164 end attribute \src "libresoc.v:147351.3-147376.6" process $proc$libresoc.v:147351$7169 assign { } { } assign { } { } assign { } { } assign $0\dbus__adr$next[44:0]$7170 $3\dbus__adr$next[44:0]$7173 attribute \src "libresoc.v:147352.5-147352.29" switch \initial attribute \src "libresoc.v:147352.9-147352.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbus__adr$next[44:0]$7171 $2\dbus__adr$next[44:0]$7172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$63 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $2\dbus__adr$next[44:0]$7172 \dbus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\dbus__adr$next[44:0]$7172 \x_addr_i [47:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\dbus__adr$next[44:0]$7172 45'000000000000000000000000000000000000000000000 end case assign $1\dbus__adr$next[44:0]$7171 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dbus__adr$next[44:0]$7173 45'000000000000000000000000000000000000000000000 case assign $3\dbus__adr$next[44:0]$7173 $1\dbus__adr$next[44:0]$7171 end sync always update \dbus__adr$next $0\dbus__adr$next[44:0]$7170 end attribute \src "libresoc.v:147377.3-147402.6" process $proc$libresoc.v:147377$7174 assign { } { } assign { } { } assign { } { } assign $0\dbus__we$next[0:0]$7175 $3\dbus__we$next[0:0]$7178 attribute \src "libresoc.v:147378.5-147378.29" switch \initial attribute \src "libresoc.v:147378.9-147378.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbus__we$next[0:0]$7176 $2\dbus__we$next[0:0]$7177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$71 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $2\dbus__we$next[0:0]$7177 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\dbus__we$next[0:0]$7177 \x_st_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\dbus__we$next[0:0]$7177 1'0 end case assign $1\dbus__we$next[0:0]$7176 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dbus__we$next[0:0]$7178 1'0 case assign $3\dbus__we$next[0:0]$7178 $1\dbus__we$next[0:0]$7176 end sync always update \dbus__we$next $0\dbus__we$next[0:0]$7175 end attribute \src "libresoc.v:147403.3-147428.6" process $proc$libresoc.v:147403$7179 assign { } { } assign { } { } assign { } { } assign $0\dbus__dat_w$next[63:0]$7180 $3\dbus__dat_w$next[63:0]$7183 attribute \src "libresoc.v:147404.5-147404.29" switch \initial attribute \src "libresoc.v:147404.9-147404.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbus__dat_w$next[63:0]$7181 $2\dbus__dat_w$next[63:0]$7182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$79 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $2\dbus__dat_w$next[63:0]$7182 \dbus__dat_w attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\dbus__dat_w$next[63:0]$7182 \x_st_data_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\dbus__dat_w$next[63:0]$7182 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $1\dbus__dat_w$next[63:0]$7181 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dbus__dat_w$next[63:0]$7183 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\dbus__dat_w$next[63:0]$7183 $1\dbus__dat_w$next[63:0]$7181 end sync always update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7180 end attribute \src "libresoc.v:147429.3-147451.6" process $proc$libresoc.v:147429$7184 assign { } { } assign { } { } assign { } { } assign $0\m_load_err_o$next[0:0]$7185 $3\m_load_err_o$next[0:0]$7188 attribute \src "libresoc.v:147430.5-147430.29" switch \initial attribute \src "libresoc.v:147430.9-147430.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\m_load_err_o$next[0:0]$7186 $2\m_load_err_o$next[0:0]$7187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\m_load_err_o$next[0:0]$7187 \$85 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\m_load_err_o$next[0:0]$7187 1'0 case assign $2\m_load_err_o$next[0:0]$7187 \m_load_err_o end case assign $1\m_load_err_o$next[0:0]$7186 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\m_load_err_o$next[0:0]$7188 1'0 case assign $3\m_load_err_o$next[0:0]$7188 $1\m_load_err_o$next[0:0]$7186 end sync always update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7185 end attribute \src "libresoc.v:147452.3-147474.6" process $proc$libresoc.v:147452$7189 assign { } { } assign { } { } assign { } { } assign $0\m_store_err_o$next[0:0]$7190 $3\m_store_err_o$next[0:0]$7193 attribute \src "libresoc.v:147453.5-147453.29" switch \initial attribute \src "libresoc.v:147453.9-147453.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\m_store_err_o$next[0:0]$7191 $2\m_store_err_o$next[0:0]$7192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$89 \$87 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\m_store_err_o$next[0:0]$7192 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\m_store_err_o$next[0:0]$7192 1'0 case assign $2\m_store_err_o$next[0:0]$7192 \m_store_err_o end case assign $1\m_store_err_o$next[0:0]$7191 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\m_store_err_o$next[0:0]$7193 1'0 case assign $3\m_store_err_o$next[0:0]$7193 $1\m_store_err_o$next[0:0]$7191 end sync always update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7190 end attribute \src "libresoc.v:147475.3-147494.6" process $proc$libresoc.v:147475$7194 assign { } { } assign { } { } assign { } { } assign $0\m_badaddr_o$next[44:0]$7195 $3\m_badaddr_o$next[44:0]$7198 attribute \src "libresoc.v:147476.5-147476.29" switch \initial attribute \src "libresoc.v:147476.9-147476.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\m_badaddr_o$next[44:0]$7196 $2\m_badaddr_o$next[44:0]$7197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$93 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\m_badaddr_o$next[44:0]$7197 \dbus__adr case assign $2\m_badaddr_o$next[44:0]$7197 \m_badaddr_o end case assign $1\m_badaddr_o$next[44:0]$7196 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\m_badaddr_o$next[44:0]$7198 45'000000000000000000000000000000000000000000000 case assign $3\m_badaddr_o$next[44:0]$7198 $1\m_badaddr_o$next[44:0]$7196 end sync always update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7195 end connect \$9 $or$libresoc.v:147143$7085_Y connect \$11 $not$libresoc.v:147144$7086_Y connect \$13 $or$libresoc.v:147145$7087_Y connect \$15 $or$libresoc.v:147146$7088_Y connect \$17 $and$libresoc.v:147147$7089_Y connect \$1 $or$libresoc.v:147148$7090_Y connect \$19 $not$libresoc.v:147149$7091_Y connect \$21 $and$libresoc.v:147150$7092_Y connect \$23 $or$libresoc.v:147151$7093_Y connect \$25 $not$libresoc.v:147152$7094_Y connect \$27 $or$libresoc.v:147153$7095_Y connect \$29 $or$libresoc.v:147154$7096_Y connect \$31 $and$libresoc.v:147155$7097_Y connect \$33 $not$libresoc.v:147156$7098_Y connect \$35 $and$libresoc.v:147157$7099_Y connect \$37 $or$libresoc.v:147158$7100_Y connect \$3 $and$libresoc.v:147159$7101_Y connect \$39 $not$libresoc.v:147160$7102_Y connect \$41 $or$libresoc.v:147161$7103_Y connect \$43 $or$libresoc.v:147162$7104_Y connect \$45 $and$libresoc.v:147163$7105_Y connect \$47 $not$libresoc.v:147164$7106_Y connect \$49 $and$libresoc.v:147165$7107_Y connect \$51 $or$libresoc.v:147166$7108_Y connect \$53 $not$libresoc.v:147167$7109_Y connect \$55 $or$libresoc.v:147168$7110_Y connect \$57 $or$libresoc.v:147169$7111_Y connect \$5 $not$libresoc.v:147170$7112_Y connect \$59 $and$libresoc.v:147171$7113_Y connect \$61 $not$libresoc.v:147172$7114_Y connect \$63 $and$libresoc.v:147173$7115_Y connect \$65 $or$libresoc.v:147174$7116_Y connect \$67 $and$libresoc.v:147175$7117_Y connect \$69 $not$libresoc.v:147176$7118_Y connect \$71 $and$libresoc.v:147177$7119_Y connect \$73 $or$libresoc.v:147178$7120_Y connect \$75 $and$libresoc.v:147179$7121_Y connect \$77 $not$libresoc.v:147180$7122_Y connect \$7 $and$libresoc.v:147181$7123_Y connect \$79 $and$libresoc.v:147182$7124_Y connect \$81 $and$libresoc.v:147183$7125_Y connect \$83 $not$libresoc.v:147184$7126_Y connect \$85 $not$libresoc.v:147185$7127_Y connect \$87 $and$libresoc.v:147186$7128_Y connect \$89 $not$libresoc.v:147187$7129_Y connect \$91 $and$libresoc.v:147188$7130_Y connect \$93 $not$libresoc.v:147189$7131_Y connect \$95 $or$libresoc.v:147190$7132_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end attribute \src "libresoc.v:147501.1-148534.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main attribute \src "libresoc.v:148034.3-148056.6" wire width 64 $0\a_i[63:0] attribute \src "libresoc.v:148133.3-148159.6" wire $0\a_lt[0:0] attribute \src "libresoc.v:148486.3-148496.6" wire width 64 $0\a_n[63:0] attribute \src "libresoc.v:148456.3-148465.6" wire width 66 $0\add_a[65:0] attribute \src "libresoc.v:148466.3-148475.6" wire width 66 $0\add_b[65:0] attribute \src "libresoc.v:148476.3-148485.6" wire width 66 $0\add_o[65:0] attribute \src "libresoc.v:148300.3-148322.6" wire width 64 $0\b_i[63:0] attribute \src "libresoc.v:148282.3-148299.6" wire width 2 $0\ca[1:0] attribute \src "libresoc.v:148497.3-148507.6" wire $0\carry_32[0:0] attribute \src "libresoc.v:148508.3-148518.6" wire $0\carry_64[0:0] attribute \src "libresoc.v:148160.3-148193.6" wire width 4 $0\cr_a[3:0] attribute \src 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"libresoc.v:148194.3-148216.6" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:148424.3-148455.6" wire width 8 $1\eqs[7:0] attribute \src "libresoc.v:148024.3-148033.6" wire $1\is_32bit[0:0] attribute \src "libresoc.v:148095.3-148113.6" wire $1\msb_a[0:0] attribute \src "libresoc.v:148114.3-148132.6" wire $1\msb_b[0:0] attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $1\o[63:0] attribute \src "libresoc.v:148259.3-148281.6" wire $1\o_ok[0:0] attribute \src "libresoc.v:148353.3-148370.6" wire width 2 $1\ov[1:0] attribute \src "libresoc.v:148401.3-148423.6" wire width 8 $1\src1[7:0] attribute \src "libresoc.v:148068.3-148094.6" wire width 5 $1\tval[4:0] attribute \src "libresoc.v:148323.3-148337.6" wire width 2 $1\xer_ca$20[1:0]$7286 attribute \src "libresoc.v:148338.3-148352.6" wire $1\xer_ca_ok[0:0] attribute \src "libresoc.v:148371.3-148385.6" wire width 2 $1\xer_ov[1:0] attribute \src "libresoc.v:148386.3-148400.6" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:148057.3-148067.6" wire $1\zerohi[0:0] attribute \src "libresoc.v:148519.3-148529.6" wire $1\zerolo[0:0] attribute \src "libresoc.v:148034.3-148056.6" wire width 64 $2\a_i[63:0] attribute \src "libresoc.v:148133.3-148159.6" wire $2\a_lt[0:0] attribute \src "libresoc.v:148300.3-148322.6" wire width 64 $2\b_i[63:0] attribute \src "libresoc.v:148160.3-148193.6" wire width 2 $2\cr_a[3:2] attribute \src "libresoc.v:148095.3-148113.6" wire $2\msb_a[0:0] attribute \src "libresoc.v:148114.3-148132.6" wire $2\msb_b[0:0] attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $2\o[63:0] attribute \src "libresoc.v:148068.3-148094.6" wire width 5 $2\tval[4:0] attribute \src "libresoc.v:148133.3-148159.6" wire $3\a_lt[0:0] attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $3\o[63:0] attribute \src "libresoc.v:148068.3-148094.6" wire width 5 $3\tval[4:0] attribute \src "libresoc.v:148217.3-148258.6" wire width 64 $4\o[63:0] attribute \src "libresoc.v:147999.18-147999.105" wire width 67 $add$libresoc.v:147999$7246_Y attribute \src "libresoc.v:147973.19-147973.107" wire $and$libresoc.v:147973$7220_Y attribute \src "libresoc.v:147977.19-147977.107" wire $and$libresoc.v:147977$7224_Y attribute \src "libresoc.v:148010.18-148010.106" wire $and$libresoc.v:148010$7257_Y attribute \src "libresoc.v:148015.18-148015.106" wire $and$libresoc.v:148015$7262_Y attribute \src "libresoc.v:148018.18-148018.106" wire $and$libresoc.v:148018$7265_Y attribute \src "libresoc.v:148021.18-148021.106" wire $and$libresoc.v:148021$7268_Y attribute \src "libresoc.v:147964.19-147964.118" wire $eq$libresoc.v:147964$7211_Y attribute \src "libresoc.v:147965.19-147965.118" wire $eq$libresoc.v:147965$7212_Y attribute \src "libresoc.v:147966.19-147966.118" wire $eq$libresoc.v:147966$7213_Y attribute \src "libresoc.v:147978.19-147978.109" wire $eq$libresoc.v:147978$7225_Y attribute \src "libresoc.v:147979.19-147979.110" wire $eq$libresoc.v:147979$7226_Y attribute \src "libresoc.v:147980.19-147980.111" wire $eq$libresoc.v:147980$7227_Y attribute \src "libresoc.v:147981.19-147981.111" wire $eq$libresoc.v:147981$7228_Y attribute \src "libresoc.v:147982.19-147982.111" wire $eq$libresoc.v:147982$7229_Y attribute \src "libresoc.v:147983.19-147983.111" wire $eq$libresoc.v:147983$7230_Y attribute \src "libresoc.v:147984.19-147984.111" wire $eq$libresoc.v:147984$7231_Y attribute \src "libresoc.v:147985.19-147985.111" wire $eq$libresoc.v:147985$7232_Y attribute \src "libresoc.v:147986.18-147986.118" wire $eq$libresoc.v:147986$7233_Y attribute \src "libresoc.v:147988.18-147988.118" wire $eq$libresoc.v:147988$7235_Y attribute \src "libresoc.v:147989.18-147989.118" wire $eq$libresoc.v:147989$7236_Y attribute \src "libresoc.v:147990.18-147990.118" wire $eq$libresoc.v:147990$7237_Y attribute \src "libresoc.v:147991.18-147991.118" wire $eq$libresoc.v:147991$7238_Y attribute \src "libresoc.v:147993.18-147993.118" wire $eq$libresoc.v:147993$7240_Y attribute \src "libresoc.v:147994.18-147994.118" wire $eq$libresoc.v:147994$7241_Y attribute \src "libresoc.v:147996.18-147996.118" wire $eq$libresoc.v:147996$7243_Y attribute \src "libresoc.v:147997.18-147997.118" wire $eq$libresoc.v:147997$7244_Y attribute \src "libresoc.v:148011.18-148011.107" wire $ne$libresoc.v:148011$7258_Y attribute \src "libresoc.v:148022.18-148022.107" wire $ne$libresoc.v:148022$7269_Y attribute \src "libresoc.v:147972.19-147972.100" wire $not$libresoc.v:147972$7219_Y attribute \src "libresoc.v:147976.19-147976.100" wire $not$libresoc.v:147976$7223_Y attribute \src "libresoc.v:147987.18-147987.110" wire $not$libresoc.v:147987$7234_Y attribute \src "libresoc.v:148000.18-148000.97" wire width 64 $not$libresoc.v:148000$7247_Y attribute \src "libresoc.v:148005.18-148005.99" wire $not$libresoc.v:148005$7252_Y attribute \src "libresoc.v:148008.18-148008.99" wire $not$libresoc.v:148008$7255_Y attribute \src "libresoc.v:148012.18-148012.99" wire $not$libresoc.v:148012$7259_Y attribute \src "libresoc.v:148013.18-148013.99" wire $not$libresoc.v:148013$7260_Y attribute \src "libresoc.v:147992.18-147992.104" wire $or$libresoc.v:147992$7239_Y attribute \src "libresoc.v:147995.18-147995.104" wire $or$libresoc.v:147995$7242_Y attribute \src "libresoc.v:147998.18-147998.104" wire $or$libresoc.v:147998$7245_Y attribute \src "libresoc.v:148009.18-148009.110" wire $or$libresoc.v:148009$7256_Y attribute \src "libresoc.v:148014.18-148014.110" wire $or$libresoc.v:148014$7261_Y attribute \src "libresoc.v:148017.18-148017.110" wire $or$libresoc.v:148017$7264_Y attribute \src "libresoc.v:148020.18-148020.110" wire $or$libresoc.v:148020$7267_Y attribute \src "libresoc.v:147963.18-147963.98" wire $reduce_or$libresoc.v:147963$7210_Y attribute \src "libresoc.v:147967.19-147967.99" wire $reduce_or$libresoc.v:147967$7214_Y attribute \src "libresoc.v:148004.18-148004.99" wire $reduce_or$libresoc.v:148004$7251_Y attribute \src "libresoc.v:148007.18-148007.99" wire $reduce_or$libresoc.v:148007$7254_Y attribute \src "libresoc.v:148016.18-148016.121" wire $ternary$libresoc.v:148016$7263_Y attribute \src "libresoc.v:148019.18-148019.119" wire $ternary$libresoc.v:148019$7266_Y attribute \src "libresoc.v:148023.18-148023.123" wire $ternary$libresoc.v:148023$7270_Y attribute \src "libresoc.v:147968.19-147968.111" wire $xor$libresoc.v:147968$7215_Y attribute \src "libresoc.v:147969.19-147969.111" wire $xor$libresoc.v:147969$7216_Y attribute \src "libresoc.v:147970.19-147970.110" wire $xor$libresoc.v:147970$7217_Y attribute \src "libresoc.v:147971.19-147971.110" wire $xor$libresoc.v:147971$7218_Y attribute \src "libresoc.v:147974.19-147974.110" wire $xor$libresoc.v:147974$7221_Y attribute \src "libresoc.v:147975.19-147975.110" wire $xor$libresoc.v:147975$7222_Y attribute \src "libresoc.v:148001.18-148001.111" wire $xor$libresoc.v:148001$7248_Y attribute \src "libresoc.v:148002.18-148002.107" wire $xor$libresoc.v:148002$7249_Y attribute \src "libresoc.v:148003.18-148003.113" wire width 32 $xor$libresoc.v:148003$7250_Y attribute \src "libresoc.v:148006.18-148006.115" wire width 32 $xor$libresoc.v:148006$7253_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" wire \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" wire \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" wire \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" wire width 67 \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" wire width 67 \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" wire width 64 \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" wire \$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" wire width 32 \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" wire width 32 \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" wire \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:65" wire width 64 \a_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" wire \a_lt attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" wire width 64 \a_n attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" wire width 66 \add_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" wire width 66 \add_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" wire width 66 \add_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 26 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \alu_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 13 \alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 36 \alu_op__input_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 41 \alu_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \alu_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \alu_op__write_cr0$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" wire width 64 \b_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" wire width 2 \ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" wire \carry_32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" wire \carry_64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 44 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs attribute \src "libresoc.v:147502.7-147502.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" wire \msb_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" wire \msb_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 42 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" wire width 2 \ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" wire width 8 \src1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" wire width 5 \tval attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 22 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 46 \xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 48 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" wire \zerohi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" cell $add $add$libresoc.v:147999$7246 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 parameter \B_WIDTH 66 parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b connect \Y $add$libresoc.v:147999$7246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $and $and$libresoc.v:147973$7220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 connect \Y $and$libresoc.v:147973$7220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $and $and$libresoc.v:147977$7224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 connect \Y $and$libresoc.v:147977$7224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $and $and$libresoc.v:148010$7257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 connect \Y $and$libresoc.v:148010$7257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $and $and$libresoc.v:148015$7262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 connect \Y $and$libresoc.v:148015$7262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $and $and$libresoc.v:148018$7265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 connect \Y $and$libresoc.v:148018$7265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $and $and$libresoc.v:148021$7268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 connect \Y $and$libresoc.v:148021$7268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" cell $eq $eq$libresoc.v:147964$7211 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 connect \Y $eq$libresoc.v:147964$7211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" cell $eq $eq$libresoc.v:147965$7212 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 connect \Y $eq$libresoc.v:147965$7212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" cell $eq $eq$libresoc.v:147966$7213 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 connect \Y $eq$libresoc.v:147966$7213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147978$7225 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] connect \Y $eq$libresoc.v:147978$7225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147979$7226 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] connect \Y $eq$libresoc.v:147979$7226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147980$7227 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] connect \Y $eq$libresoc.v:147980$7227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147981$7228 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] connect \Y $eq$libresoc.v:147981$7228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147982$7229 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] connect \Y $eq$libresoc.v:147982$7229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147983$7230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] connect \Y $eq$libresoc.v:147983$7230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147984$7231 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] connect \Y $eq$libresoc.v:147984$7231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" cell $eq $eq$libresoc.v:147985$7232 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] connect \Y $eq$libresoc.v:147985$7232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" cell $eq $eq$libresoc.v:147986$7233 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:147986$7233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" cell $eq $eq$libresoc.v:147988$7235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:147988$7235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" cell $eq $eq$libresoc.v:147989$7236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:147989$7236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" cell $eq $eq$libresoc.v:147990$7237 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 connect \Y $eq$libresoc.v:147990$7237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" cell $eq $eq$libresoc.v:147991$7238 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:147991$7238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" cell $eq $eq$libresoc.v:147993$7240 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 connect \Y $eq$libresoc.v:147993$7240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" cell $eq $eq$libresoc.v:147994$7241 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:147994$7241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" cell $eq $eq$libresoc.v:147996$7243 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 connect \Y $eq$libresoc.v:147996$7243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" cell $eq $eq$libresoc.v:147997$7244 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:147997$7244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" cell $ne $ne$libresoc.v:148011$7258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b connect \Y $ne$libresoc.v:148011$7258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" cell $ne $ne$libresoc.v:148022$7269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b connect \Y $ne$libresoc.v:148022$7269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $not $not$libresoc.v:147972$7219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 connect \Y $not$libresoc.v:147972$7219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $not $not$libresoc.v:147976$7223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 connect \Y $not$libresoc.v:147976$7223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" cell $not $not$libresoc.v:147987$7234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] connect \Y $not$libresoc.v:147987$7234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" cell $not $not$libresoc.v:148000$7247 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \Y $not$libresoc.v:148000$7247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" cell $not $not$libresoc.v:148005$7252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 connect \Y $not$libresoc.v:148005$7252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" cell $not $not$libresoc.v:148008$7255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 connect \Y $not$libresoc.v:148008$7255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" cell $not $not$libresoc.v:148012$7259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt connect \Y $not$libresoc.v:148012$7259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" cell $not $not$libresoc.v:148013$7260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt connect \Y $not$libresoc.v:148013$7260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" cell $or $or$libresoc.v:147992$7239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 connect \Y $or$libresoc.v:147992$7239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" cell $or $or$libresoc.v:147995$7242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 connect \Y $or$libresoc.v:147995$7242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" cell $or $or$libresoc.v:147998$7245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 connect \Y $or$libresoc.v:147998$7245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $or $or$libresoc.v:148009$7256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi connect \Y $or$libresoc.v:148009$7256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $or $or$libresoc.v:148014$7261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi connect \Y $or$libresoc.v:148014$7261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $or $or$libresoc.v:148017$7264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi connect \Y $or$libresoc.v:148017$7264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" cell $or $or$libresoc.v:148020$7267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi connect \Y $or$libresoc.v:148020$7267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" cell $reduce_or $reduce_or$libresoc.v:147963$7210 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs connect \Y $reduce_or$libresoc.v:147963$7210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" cell $reduce_or $reduce_or$libresoc.v:147967$7214 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs connect \Y $reduce_or$libresoc.v:147967$7214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" cell $reduce_or $reduce_or$libresoc.v:148004$7251 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 connect \Y $reduce_or$libresoc.v:148004$7251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" cell $reduce_or $reduce_or$libresoc.v:148007$7254 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 connect \Y $reduce_or$libresoc.v:148007$7254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" cell $mux $ternary$libresoc.v:148016$7263 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit connect \Y $ternary$libresoc.v:148016$7263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" cell $mux $ternary$libresoc.v:148019$7266 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit connect \Y $ternary$libresoc.v:148019$7266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" cell $mux $ternary$libresoc.v:148023$7270 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit connect \Y $ternary$libresoc.v:148023$7270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" cell $xor $xor$libresoc.v:147968$7215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] connect \Y $xor$libresoc.v:147968$7215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" cell $xor $xor$libresoc.v:147969$7216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 connect \Y $xor$libresoc.v:147969$7216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $xor $xor$libresoc.v:147970$7217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] connect \Y $xor$libresoc.v:147970$7217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $xor $xor$libresoc.v:147971$7218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] connect \Y $xor$libresoc.v:147971$7218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $xor $xor$libresoc.v:147974$7221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] connect \Y $xor$libresoc.v:147974$7221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" cell $xor $xor$libresoc.v:147975$7222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] connect \Y $xor$libresoc.v:147975$7222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" cell $xor $xor$libresoc.v:148001$7248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] connect \Y $xor$libresoc.v:148001$7248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" cell $xor $xor$libresoc.v:148002$7249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] connect \Y $xor$libresoc.v:148002$7249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" cell $xor $xor$libresoc.v:148003$7250 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] connect \Y $xor$libresoc.v:148003$7250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" cell $xor $xor$libresoc.v:148006$7253 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] connect \Y $xor$libresoc.v:148006$7253_Y end attribute \src "libresoc.v:147502.7-147502.20" process $proc$libresoc.v:147502$7300 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:148024.3-148033.6" process $proc$libresoc.v:148024$7271 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] attribute \src "libresoc.v:148025.5-148025.29" switch \initial attribute \src "libresoc.v:148025.9-148025.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" switch \$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\is_32bit[0:0] \$24 case assign $1\is_32bit[0:0] 1'0 end sync always update \is_32bit $0\is_32bit[0:0] end attribute \src "libresoc.v:148034.3-148056.6" process $proc$libresoc.v:148034$7272 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] attribute \src "libresoc.v:148035.5-148035.29" switch \initial attribute \src "libresoc.v:148035.9-148035.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" switch { \is_32bit \$26 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\a_i[63:0] \ra attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\a_i[63:0] $2\a_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" switch \alu_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\a_i[63:0] \ra end sync always update \a_i $0\a_i[63:0] end attribute \src "libresoc.v:148057.3-148067.6" process $proc$libresoc.v:148057$7273 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] attribute \src "libresoc.v:148058.5-148058.29" switch \initial attribute \src "libresoc.v:148058.9-148058.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\zerohi[0:0] \$63 case assign $1\zerohi[0:0] 1'0 end sync always update \zerohi $0\zerohi[0:0] end attribute \src "libresoc.v:148068.3-148094.6" process $proc$libresoc.v:148068$7274 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] attribute \src "libresoc.v:148069.5-148069.29" switch \initial attribute \src "libresoc.v:148069.9-148069.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\tval[4:0] $2\tval[4:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 assign $2\tval[4:0] [2] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\tval[4:0] $3\tval[4:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } end end case assign $1\tval[4:0] 5'00000 end sync always update \tval $0\tval[4:0] end attribute \src "libresoc.v:148095.3-148113.6" process $proc$libresoc.v:148095$7275 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] attribute \src "libresoc.v:148096.5-148096.29" switch \initial attribute \src "libresoc.v:148096.9-148096.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\msb_a[0:0] $2\msb_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\msb_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\msb_a[0:0] \$83 end case assign $1\msb_a[0:0] 1'0 end sync always update \msb_a $0\msb_a[0:0] end attribute \src "libresoc.v:148114.3-148132.6" process $proc$libresoc.v:148114$7276 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] attribute \src "libresoc.v:148115.5-148115.29" switch \initial attribute \src "libresoc.v:148115.9-148115.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\msb_b[0:0] $2\msb_b[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\msb_b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\msb_b[0:0] \$89 end case assign $1\msb_b[0:0] 1'0 end sync always update \msb_b $0\msb_b[0:0] end attribute \src "libresoc.v:148133.3-148159.6" process $proc$libresoc.v:148133$7277 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] attribute \src "libresoc.v:148134.5-148134.29" switch \initial attribute \src "libresoc.v:148134.9-148134.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\a_lt[0:0] $2\a_lt[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\a_lt[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\a_lt[0:0] $3\a_lt[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\a_lt[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\a_lt[0:0] \$97 end end case assign $1\a_lt[0:0] 1'0 end sync always update \a_lt $0\a_lt[0:0] end attribute \src "libresoc.v:148160.3-148193.6" process $proc$libresoc.v:148160$7278 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] attribute \src "libresoc.v:148161.5-148161.29" switch \initial attribute \src "libresoc.v:148161.9-148161.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" switch \alu_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a[3:2] \tval [4:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cr_a[3:2] \tval [1:0] end attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign $1\cr_a[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0011111 assign $1\cr_a[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\cr_a[3:0] { 1'0 \$99 2'00 } case assign $1\cr_a[3:0] 4'0000 end sync always update \cr_a $0\cr_a[3:0] end attribute \src "libresoc.v:148194.3-148216.6" process $proc$libresoc.v:148194$7279 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] attribute \src "libresoc.v:148195.5-148195.29" switch \initial attribute \src "libresoc.v:148195.9-148195.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign $1\cr_a_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0011111 assign $1\cr_a_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\cr_a_ok[0:0] 1'1 case assign $1\cr_a_ok[0:0] 1'0 end sync always update \cr_a_ok $0\cr_a_ok[0:0] end attribute \src "libresoc.v:148217.3-148258.6" process $proc$libresoc.v:148217$7280 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] attribute \src "libresoc.v:148218.5-148218.29" switch \initial attribute \src "libresoc.v:148218.9-148218.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\o[63:0] \add_o [64:1] attribute \src "libresoc.v:0.0-0.0" case 7'0011111 assign { } { } assign { } { } assign { } { } assign $1\o[63:0] $4\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } case assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } case assign $3\o[63:0] $2\o[63:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } case assign $4\o[63:0] $3\o[63:0] end attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 assign $1\o[63:0] [0] \$107 case assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \o $0\o[63:0] end attribute \src "libresoc.v:148259.3-148281.6" process $proc$libresoc.v:148259$7281 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] attribute \src "libresoc.v:148260.5-148260.29" switch \initial attribute \src "libresoc.v:148260.9-148260.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0011111 assign { } { } assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\o_ok[0:0] 1'0 case assign $1\o_ok[0:0] 1'0 end sync always update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:148282.3-148299.6" process $proc$libresoc.v:148282$7282 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] attribute \src "libresoc.v:148283.5-148283.29" switch \initial attribute \src "libresoc.v:148283.9-148283.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\ca[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\ca[1:0] [0] \add_o [65] assign $1\ca[1:0] [1] \$111 case assign $1\ca[1:0] 2'00 end sync always update \ca $0\ca[1:0] end attribute \src "libresoc.v:148300.3-148322.6" process $proc$libresoc.v:148300$7283 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] attribute \src "libresoc.v:148301.5-148301.29" switch \initial attribute \src "libresoc.v:148301.9-148301.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" switch { \is_32bit \$28 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\b_i[63:0] \rb attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\b_i[63:0] $2\b_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" switch \alu_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\b_i[63:0] \rb end sync always update \b_i $0\b_i[63:0] end attribute \src "libresoc.v:148323.3-148337.6" process $proc$libresoc.v:148323$7284 assign { } { } assign { } { } assign $0\xer_ca$20[1:0]$7285 $1\xer_ca$20[1:0]$7286 attribute \src "libresoc.v:148324.5-148324.29" switch \initial attribute \src "libresoc.v:148324.9-148324.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\xer_ca$20[1:0]$7286 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ca$20[1:0]$7286 \ca case assign $1\xer_ca$20[1:0]$7286 2'00 end sync always update \xer_ca$20 $0\xer_ca$20[1:0]$7285 end attribute \src "libresoc.v:148338.3-148352.6" process $proc$libresoc.v:148338$7287 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] attribute \src "libresoc.v:148339.5-148339.29" switch \initial attribute \src "libresoc.v:148339.9-148339.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\xer_ca_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ca_ok[0:0] 1'1 case assign $1\xer_ca_ok[0:0] 1'0 end sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end attribute \src "libresoc.v:148353.3-148370.6" process $proc$libresoc.v:148353$7288 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] attribute \src "libresoc.v:148354.5-148354.29" switch \initial attribute \src "libresoc.v:148354.9-148354.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\ov[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\ov[1:0] [0] \$119 assign $1\ov[1:0] [1] \$127 case assign $1\ov[1:0] 2'00 end sync always update \ov $0\ov[1:0] end attribute \src "libresoc.v:148371.3-148385.6" process $proc$libresoc.v:148371$7289 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] attribute \src "libresoc.v:148372.5-148372.29" switch \initial attribute \src "libresoc.v:148372.9-148372.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\xer_ov[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ov[1:0] \ov case assign $1\xer_ov[1:0] 2'00 end sync always update \xer_ov $0\xer_ov[1:0] end attribute \src "libresoc.v:148386.3-148400.6" process $proc$libresoc.v:148386$7290 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] attribute \src "libresoc.v:148387.5-148387.29" switch \initial attribute \src "libresoc.v:148387.9-148387.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\xer_ov_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 case assign $1\xer_ov_ok[0:0] 1'0 end sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end attribute \src "libresoc.v:148401.3-148423.6" process $proc$libresoc.v:148401$7291 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] attribute \src "libresoc.v:148402.5-148402.29" switch \initial attribute \src "libresoc.v:148402.9-148402.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\src1[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign $1\src1[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0011111 assign $1\src1[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\src1[7:0] \ra [7:0] case assign $1\src1[7:0] 8'00000000 end sync always update \src1 $0\src1[7:0] end attribute \src "libresoc.v:148424.3-148455.6" process $proc$libresoc.v:148424$7292 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] attribute \src "libresoc.v:148425.5-148425.29" switch \initial attribute \src "libresoc.v:148425.9-148425.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign $1\eqs[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign $1\eqs[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0011111 assign $1\eqs[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\eqs[7:0] [0] \$129 assign $1\eqs[7:0] [1] \$131 assign $1\eqs[7:0] [2] \$133 assign $1\eqs[7:0] [3] \$135 assign $1\eqs[7:0] [4] \$137 assign $1\eqs[7:0] [5] \$139 assign $1\eqs[7:0] [6] \$141 assign $1\eqs[7:0] [7] \$143 case assign $1\eqs[7:0] 8'00000000 end sync always update \eqs $0\eqs[7:0] end attribute \src "libresoc.v:148456.3-148465.6" process $proc$libresoc.v:148456$7293 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] attribute \src "libresoc.v:148457.5-148457.29" switch \initial attribute \src "libresoc.v:148457.9-148457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } case assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 end sync always update \add_a $0\add_a[65:0] end attribute \src "libresoc.v:148466.3-148475.6" process $proc$libresoc.v:148466$7294 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] attribute \src "libresoc.v:148467.5-148467.29" switch \initial attribute \src "libresoc.v:148467.9-148467.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" switch \$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\add_b[65:0] { 1'0 \b_i 1'1 } case assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 end sync always update \add_b $0\add_b[65:0] end attribute \src "libresoc.v:148476.3-148485.6" process $proc$libresoc.v:148476$7295 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] attribute \src "libresoc.v:148477.5-148477.29" switch \initial attribute \src "libresoc.v:148477.9-148477.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" switch \$46 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\add_o[65:0] \$48 [65:0] case assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 end sync always update \add_o $0\add_o[65:0] end attribute \src "libresoc.v:148486.3-148496.6" process $proc$libresoc.v:148486$7296 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] attribute \src "libresoc.v:148487.5-148487.29" switch \initial attribute \src "libresoc.v:148487.9-148487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\a_n[63:0] \$51 case assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \a_n $0\a_n[63:0] end attribute \src "libresoc.v:148497.3-148507.6" process $proc$libresoc.v:148497$7297 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] attribute \src "libresoc.v:148498.5-148498.29" switch \initial attribute \src "libresoc.v:148498.9-148498.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\carry_32[0:0] \$55 case assign $1\carry_32[0:0] 1'0 end sync always update \carry_32 $0\carry_32[0:0] end attribute \src "libresoc.v:148508.3-148518.6" process $proc$libresoc.v:148508$7298 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] attribute \src "libresoc.v:148509.5-148509.29" switch \initial attribute \src "libresoc.v:148509.9-148509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\carry_64[0:0] \add_o [65] case assign $1\carry_64[0:0] 1'0 end sync always update \carry_64 $0\carry_64[0:0] end attribute \src "libresoc.v:148519.3-148529.6" process $proc$libresoc.v:148519$7299 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] attribute \src "libresoc.v:148520.5-148520.29" switch \initial attribute \src "libresoc.v:148520.9-148520.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\zerolo[0:0] \$57 case assign $1\zerolo[0:0] 1'0 end sync always update \zerolo $0\zerolo[0:0] end connect \$99 $reduce_or$libresoc.v:147963$7210_Y connect \$101 $eq$libresoc.v:147964$7211_Y connect \$103 $eq$libresoc.v:147965$7212_Y connect \$105 $eq$libresoc.v:147966$7213_Y connect \$107 $reduce_or$libresoc.v:147967$7214_Y connect \$109 $xor$libresoc.v:147968$7215_Y connect \$111 $xor$libresoc.v:147969$7216_Y connect \$113 $xor$libresoc.v:147970$7217_Y connect \$116 $xor$libresoc.v:147971$7218_Y connect \$115 $not$libresoc.v:147972$7219_Y connect \$119 $and$libresoc.v:147973$7220_Y connect \$121 $xor$libresoc.v:147974$7221_Y connect \$124 $xor$libresoc.v:147975$7222_Y connect \$123 $not$libresoc.v:147976$7223_Y connect \$127 $and$libresoc.v:147977$7224_Y connect \$129 $eq$libresoc.v:147978$7225_Y connect \$131 $eq$libresoc.v:147979$7226_Y connect \$133 $eq$libresoc.v:147980$7227_Y connect \$135 $eq$libresoc.v:147981$7228_Y connect \$137 $eq$libresoc.v:147982$7229_Y connect \$139 $eq$libresoc.v:147983$7230_Y connect \$141 $eq$libresoc.v:147984$7231_Y connect \$143 $eq$libresoc.v:147985$7232_Y connect \$22 $eq$libresoc.v:147986$7233_Y connect \$24 $not$libresoc.v:147987$7234_Y connect \$26 $eq$libresoc.v:147988$7235_Y connect \$28 $eq$libresoc.v:147989$7236_Y connect \$30 $eq$libresoc.v:147990$7237_Y connect \$32 $eq$libresoc.v:147991$7238_Y connect \$34 $or$libresoc.v:147992$7239_Y connect \$36 $eq$libresoc.v:147993$7240_Y connect \$38 $eq$libresoc.v:147994$7241_Y connect \$40 $or$libresoc.v:147995$7242_Y connect \$42 $eq$libresoc.v:147996$7243_Y connect \$44 $eq$libresoc.v:147997$7244_Y connect \$46 $or$libresoc.v:147998$7245_Y connect \$49 $add$libresoc.v:147999$7246_Y connect \$51 $not$libresoc.v:148000$7247_Y connect \$53 $xor$libresoc.v:148001$7248_Y connect \$55 $xor$libresoc.v:148002$7249_Y connect \$59 $xor$libresoc.v:148003$7250_Y connect \$58 $reduce_or$libresoc.v:148004$7251_Y connect \$57 $not$libresoc.v:148005$7252_Y connect \$65 $xor$libresoc.v:148006$7253_Y connect \$64 $reduce_or$libresoc.v:148007$7254_Y connect \$63 $not$libresoc.v:148008$7255_Y connect \$69 $or$libresoc.v:148009$7256_Y connect \$71 $and$libresoc.v:148010$7257_Y connect \$73 $ne$libresoc.v:148011$7258_Y connect \$75 $not$libresoc.v:148012$7259_Y connect \$77 $not$libresoc.v:148013$7260_Y connect \$79 $or$libresoc.v:148014$7261_Y connect \$81 $and$libresoc.v:148015$7262_Y connect \$83 $ternary$libresoc.v:148016$7263_Y connect \$85 $or$libresoc.v:148017$7264_Y connect \$87 $and$libresoc.v:148018$7265_Y connect \$89 $ternary$libresoc.v:148019$7266_Y connect \$91 $or$libresoc.v:148020$7267_Y connect \$93 $and$libresoc.v:148021$7268_Y connect \$95 $ne$libresoc.v:148022$7269_Y connect \$97 $ternary$libresoc.v:148023$7270_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end attribute \src "libresoc.v:148538.1-148952.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 attribute \src "libresoc.v:148539.7-148539.20" wire $0\initial[0:0] attribute \src "libresoc.v:148904.3-148934.6" wire width 4 $0\mode[3:0] attribute \src "libresoc.v:148869.3-148903.6" wire $0\o_ok[0:0] attribute \src "libresoc.v:148904.3-148934.6" wire width 4 $1\mode[3:0] attribute \src "libresoc.v:148869.3-148903.6" wire $1\o_ok[0:0] attribute \src "libresoc.v:148539.7-148539.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" wire \mb_extra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" wire width 5 \me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" wire width 4 \mode attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 40 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 41 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" wire \rotator_arith attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" wire \rotator_carry_out_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" wire \rotator_clear_left attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" wire \rotator_clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire \rotator_is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" wire width 5 \rotator_mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" wire \rotator_mb_extra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" wire width 5 \rotator_me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" wire width 64 \rotator_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" wire width 64 \rotator_result_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" wire \rotator_right_shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" wire width 64 \rotator_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" wire width 7 \rotator_shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire \rotator_sign_ext_rs attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 24 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 25 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \sr_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 33 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 17 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 39 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 43 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \xer_so$19 attribute \module_not_derived 1 attribute \src "libresoc.v:148853.11-148868.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o connect \clear_left \rotator_clear_left connect \clear_right \rotator_clear_right connect \is_32bit \rotator_is_32bit connect \mb \rotator_mb connect \mb_extra \rotator_mb_extra connect \me \rotator_me connect \ra \rotator_ra connect \result_o \rotator_result_o connect \right_shift \rotator_right_shift connect \rs \rotator_rs connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end attribute \src "libresoc.v:148539.7-148539.20" process $proc$libresoc.v:148539$7303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:148869.3-148903.6" process $proc$libresoc.v:148869$7301 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] attribute \src "libresoc.v:148870.5-148870.29" switch \initial attribute \src "libresoc.v:148870.9-148870.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" switch \sr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111100 assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0111101 assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0111000 assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0111001 assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0111010 assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0100000 assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o_ok[0:0] 1'0 end sync always update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:148904.3-148934.6" process $proc$libresoc.v:148904$7302 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] attribute \src "libresoc.v:148905.5-148905.29" switch \initial attribute \src "libresoc.v:148905.9-148905.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" switch \sr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111100 assign { } { } assign $1\mode[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'0111101 assign { } { } assign $1\mode[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" case 7'0111000 assign { } { } assign $1\mode[3:0] 4'0110 attribute \src "libresoc.v:0.0-0.0" case 7'0111001 assign { } { } assign $1\mode[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" case 7'0111010 assign { } { } assign $1\mode[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" case 7'0100000 assign { } { } assign $1\mode[3:0] 4'1000 case assign $1\mode[3:0] 4'0000 end sync always update \mode $0\mode[3:0] end connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \xer_so$19 \xer_so connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } connect \o \rotator_result_o connect { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode connect \rotator_arith \sr_op__is_signed connect \rotator_is_32bit \sr_op__is_32bit connect \rotator_shift \rb [6:0] connect \rotator_ra \ra connect \rotator_rs \rc connect \rotator_mb_extra \mb_extra connect \rotator_mb \mb connect \rotator_me \me connect \mb_extra \sr_op__insn [5] connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end attribute \src "libresoc.v:148956.1-149496.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 attribute \src "libresoc.v:149403.3-149426.6" wire $0\bc_taken[0:0] attribute \src "libresoc.v:149278.3-149289.6" wire width 64 $0\br_addr[63:0] attribute \src "libresoc.v:149290.3-149316.6" wire width 64 $0\br_imm_addr[63:0] attribute \src "libresoc.v:149317.3-149335.6" wire $0\br_taken[0:0] attribute \src "libresoc.v:149375.3-149389.6" wire $0\cr_bit[0:0] attribute \src "libresoc.v:149453.3-149473.6" wire width 64 $0\ctr_m[63:0] attribute \src "libresoc.v:149427.3-149439.6" wire width 64 $0\ctr_n[63:0] attribute \src "libresoc.v:149390.3-149402.6" wire $0\ctr_write[0:0] attribute \src "libresoc.v:149474.3-149486.6" wire $0\ctr_zero_bo1[0:0] attribute \src "libresoc.v:149440.3-149452.6" wire width 64 $0\fast1$10[63:0]$7336 attribute \src "libresoc.v:149336.3-149354.6" wire $0\fast1_ok[0:0] attribute \src "libresoc.v:149355.3-149364.6" wire width 64 $0\fast2$11[63:0]$7328 attribute \src "libresoc.v:149365.3-149374.6" wire $0\fast2_ok[0:0] attribute \src "libresoc.v:148957.7-148957.20" wire $0\initial[0:0] attribute \src "libresoc.v:149403.3-149426.6" wire $1\bc_taken[0:0] attribute \src "libresoc.v:149278.3-149289.6" wire width 64 $1\br_addr[63:0] attribute \src "libresoc.v:149290.3-149316.6" wire width 64 $1\br_imm_addr[63:0] attribute \src "libresoc.v:149317.3-149335.6" wire $1\br_taken[0:0] attribute \src "libresoc.v:149375.3-149389.6" wire $1\cr_bit[0:0] attribute \src "libresoc.v:149453.3-149473.6" wire width 64 $1\ctr_m[63:0] attribute \src "libresoc.v:149427.3-149439.6" wire width 64 $1\ctr_n[63:0] attribute \src "libresoc.v:149390.3-149402.6" wire $1\ctr_write[0:0] attribute \src "libresoc.v:149474.3-149486.6" wire $1\ctr_zero_bo1[0:0] attribute \src "libresoc.v:149440.3-149452.6" wire width 64 $1\fast1$10[63:0]$7337 attribute \src "libresoc.v:149336.3-149354.6" wire $1\fast1_ok[0:0] attribute \src "libresoc.v:149355.3-149364.6" wire width 64 $1\fast2$11[63:0]$7329 attribute \src "libresoc.v:149365.3-149374.6" wire $1\fast2_ok[0:0] attribute \src "libresoc.v:149403.3-149426.6" wire $2\bc_taken[0:0] attribute \src "libresoc.v:149290.3-149316.6" wire width 64 $2\br_imm_addr[63:0] attribute \src "libresoc.v:149453.3-149473.6" wire width 64 $2\ctr_m[63:0] attribute \src "libresoc.v:149262.18-149262.119" wire width 65 $add$libresoc.v:149262$7306_Y attribute \src "libresoc.v:149277.18-149277.113" wire width 65 $add$libresoc.v:149277$7322_Y attribute \src "libresoc.v:149269.18-149269.115" wire $and$libresoc.v:149269$7313_Y attribute \src "libresoc.v:149270.18-149270.117" wire $and$libresoc.v:149270$7314_Y attribute \src "libresoc.v:149276.18-149276.118" wire $and$libresoc.v:149276$7321_Y attribute \src "libresoc.v:149260.18-149260.120" wire $eq$libresoc.v:149260$7304_Y attribute \src "libresoc.v:149263.18-149263.111" wire $eq$libresoc.v:149263$7307_Y attribute \src "libresoc.v:149265.18-149265.111" wire $eq$libresoc.v:149265$7309_Y attribute \src "libresoc.v:149266.18-149266.111" wire $eq$libresoc.v:149266$7310_Y attribute \src "libresoc.v:149267.18-149267.109" wire $eq$libresoc.v:149267$7311_Y attribute \src "libresoc.v:149272.18-149272.98" wire width 64 $extend$libresoc.v:149272$7316_Y attribute \src "libresoc.v:149268.18-149268.104" wire $not$libresoc.v:149268$7312_Y attribute \src "libresoc.v:149275.18-149275.112" wire $not$libresoc.v:149275$7320_Y attribute \src "libresoc.v:149261.18-149261.116" wire $or$libresoc.v:149261$7305_Y attribute \src "libresoc.v:149264.18-149264.109" wire $or$libresoc.v:149264$7308_Y attribute \src "libresoc.v:149272.18-149272.98" wire width 64 $pos$libresoc.v:149272$7317_Y attribute \src "libresoc.v:149273.18-149273.103" wire $reduce_or$libresoc.v:149273$7318_Y attribute \src "libresoc.v:149271.18-149271.108" wire width 65 $sub$libresoc.v:149271$7315_Y attribute \src "libresoc.v:149274.18-149274.108" wire $xor$libresoc.v:149274$7319_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" wire width 65 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" wire width 65 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" wire width 65 \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" wire width 65 \$36 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" wire width 65 \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" wire width 65 \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" wire \bc_taken attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" wire width 2 \bi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" wire width 5 \bo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" wire width 64 \br_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" wire width 64 \br_imm_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 1 \br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 13 \br_op__cia$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 15 \br_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 17 \br_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \br_op__imm_data__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 16 \br_op__insn$5 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 14 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \br_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 19 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" wire \br_taken attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" wire \cr_bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" wire width 64 \ctr_m attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" wire width 64 \ctr_n attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" wire \ctr_write attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" wire \ctr_zero_bo1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 21 \fast1$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \fast2_ok attribute \src "libresoc.v:148957.7-148957.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 12 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 25 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" cell $add $add$libresoc.v:149262$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia connect \Y $add$libresoc.v:149262$7306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" cell $add $add$libresoc.v:149277$7322 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 connect \Y $add$libresoc.v:149277$7322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" cell $and $and$libresoc.v:149269$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 connect \Y $and$libresoc.v:149269$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" cell $and $and$libresoc.v:149270$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit connect \Y $and$libresoc.v:149270$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" cell $and $and$libresoc.v:149276$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 connect \Y $and$libresoc.v:149276$7321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" cell $eq $eq$libresoc.v:149260$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 connect \Y $eq$libresoc.v:149260$7304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" cell $eq $eq$libresoc.v:149263$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] connect \Y $eq$libresoc.v:149263$7307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" cell $eq $eq$libresoc.v:149265$7309 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 connect \Y $eq$libresoc.v:149265$7309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" cell $eq $eq$libresoc.v:149266$7310 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 connect \Y $eq$libresoc.v:149266$7310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" cell $eq $eq$libresoc.v:149267$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 connect \Y $eq$libresoc.v:149267$7311_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $extend$libresoc.v:149272$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] connect \Y $extend$libresoc.v:149272$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" cell $not $not$libresoc.v:149268$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit connect \Y $not$libresoc.v:149268$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" cell $not $not$libresoc.v:149275$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] connect \Y $not$libresoc.v:149275$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" cell $or $or$libresoc.v:149261$7305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 connect \Y $or$libresoc.v:149261$7305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" cell $or $or$libresoc.v:149264$7308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] connect \Y $or$libresoc.v:149264$7308_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $pos$libresoc.v:149272$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:149272$7316_Y connect \Y $pos$libresoc.v:149272$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" cell $reduce_or $reduce_or$libresoc.v:149273$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n connect \Y $reduce_or$libresoc.v:149273$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" cell $sub $sub$libresoc.v:149271$7315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 connect \Y $sub$libresoc.v:149271$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" cell $xor $xor$libresoc.v:149274$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 connect \Y $xor$libresoc.v:149274$7319_Y end attribute \src "libresoc.v:148957.7-148957.20" process $proc$libresoc.v:148957$7340 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:149278.3-149289.6" process $proc$libresoc.v:149278$7323 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] attribute \src "libresoc.v:149279.5-149279.29" switch \initial attribute \src "libresoc.v:149279.9-149279.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" switch \$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\br_addr[63:0] \br_imm_addr attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\br_addr[63:0] \$16 [63:0] end sync always update \br_addr $0\br_addr[63:0] end attribute \src "libresoc.v:149290.3-149316.6" process $proc$libresoc.v:149290$7324 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] attribute \src "libresoc.v:149291.5-149291.29" switch \initial attribute \src "libresoc.v:149291.9-149291.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000110 assign { } { } assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign { } { } assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } attribute \src "libresoc.v:0.0-0.0" case 7'0001000 assign { } { } assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" switch \$46 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } end case assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \br_imm_addr $0\br_imm_addr[63:0] end attribute \src "libresoc.v:149317.3-149335.6" process $proc$libresoc.v:149317$7325 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] attribute \src "libresoc.v:149318.5-149318.29" switch \initial attribute \src "libresoc.v:149318.9-149318.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000110 assign { } { } assign $1\br_taken[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign { } { } assign $1\br_taken[0:0] \bc_taken attribute \src "libresoc.v:0.0-0.0" case 7'0001000 assign { } { } assign $1\br_taken[0:0] \bc_taken case assign $1\br_taken[0:0] 1'0 end sync always update \br_taken $0\br_taken[0:0] end attribute \src "libresoc.v:149336.3-149354.6" process $proc$libresoc.v:149336$7326 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] attribute \src "libresoc.v:149337.5-149337.29" switch \initial attribute \src "libresoc.v:149337.9-149337.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000110 assign $1\fast1_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign { } { } assign $1\fast1_ok[0:0] \ctr_write attribute \src "libresoc.v:0.0-0.0" case 7'0001000 assign { } { } assign $1\fast1_ok[0:0] \ctr_write case assign $1\fast1_ok[0:0] 1'0 end sync always update \fast1_ok $0\fast1_ok[0:0] end attribute \src "libresoc.v:149355.3-149364.6" process $proc$libresoc.v:149355$7327 assign { } { } assign { } { } assign $0\fast2$11[63:0]$7328 $1\fast2$11[63:0]$7329 attribute \src "libresoc.v:149356.5-149356.29" switch \initial attribute \src "libresoc.v:149356.9-149356.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" switch \br_op__lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast2$11[63:0]$7329 \$48 [63:0] case assign $1\fast2$11[63:0]$7329 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fast2$11 $0\fast2$11[63:0]$7328 end attribute \src "libresoc.v:149365.3-149374.6" process $proc$libresoc.v:149365$7330 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] attribute \src "libresoc.v:149366.5-149366.29" switch \initial attribute \src "libresoc.v:149366.9-149366.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" switch \br_op__lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast2_ok[0:0] 1'1 case assign $1\fast2_ok[0:0] 1'0 end sync always update \fast2_ok $0\fast2_ok[0:0] end attribute \src "libresoc.v:149375.3-149389.6" process $proc$libresoc.v:149375$7331 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] attribute \src "libresoc.v:149376.5-149376.29" switch \initial attribute \src "libresoc.v:149376.9-149376.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" switch \bi attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\cr_bit[0:0] \cr_a [3] attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\cr_bit[0:0] \cr_a [2] attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\cr_bit[0:0] \cr_a [1] attribute \src "libresoc.v:0.0-0.0" case 2'-- assign { } { } assign $1\cr_bit[0:0] \cr_a [0] case assign $1\cr_bit[0:0] 1'0 end sync always update \cr_bit $0\cr_bit[0:0] end attribute \src "libresoc.v:149390.3-149402.6" process $proc$libresoc.v:149390$7332 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] attribute \src "libresoc.v:149391.5-149391.29" switch \initial attribute \src "libresoc.v:149391.9-149391.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $1\ctr_write[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ctr_write[0:0] 1'1 end sync always update \ctr_write $0\ctr_write[0:0] end attribute \src "libresoc.v:149403.3-149426.6" process $proc$libresoc.v:149403$7333 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] attribute \src "libresoc.v:149404.5-149404.29" switch \initial attribute \src "libresoc.v:149404.9-149404.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\bc_taken[0:0] \$21 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\bc_taken[0:0] $2\bc_taken[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" switch { \$27 \$25 \$23 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $2\bc_taken[0:0] \$31 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $2\bc_taken[0:0] \$33 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $2\bc_taken[0:0] \ctr_zero_bo1 case assign $2\bc_taken[0:0] 1'0 end end sync always update \bc_taken $0\bc_taken[0:0] end attribute \src "libresoc.v:149427.3-149439.6" process $proc$libresoc.v:149427$7334 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] attribute \src "libresoc.v:149428.5-149428.29" switch \initial attribute \src "libresoc.v:149428.9-149428.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ctr_n[63:0] \$35 [63:0] end sync always update \ctr_n $0\ctr_n[63:0] end attribute \src "libresoc.v:149440.3-149452.6" process $proc$libresoc.v:149440$7335 assign { } { } assign { } { } assign $0\fast1$10[63:0]$7336 $1\fast1$10[63:0]$7337 attribute \src "libresoc.v:149441.5-149441.29" switch \initial attribute \src "libresoc.v:149441.9-149441.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $1\fast1$10[63:0]$7337 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\fast1$10[63:0]$7337 \ctr_n end sync always update \fast1$10 $0\fast1$10[63:0]$7336 end attribute \src "libresoc.v:149453.3-149473.6" process $proc$libresoc.v:149453$7338 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] attribute \src "libresoc.v:149454.5-149454.29" switch \initial attribute \src "libresoc.v:149454.9-149454.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ctr_m[63:0] $2\ctr_m[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" switch \br_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ctr_m[63:0] \$38 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\ctr_m[63:0] \fast1 end end sync always update \ctr_m $0\ctr_m[63:0] end attribute \src "libresoc.v:149474.3-149486.6" process $proc$libresoc.v:149474$7339 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] attribute \src "libresoc.v:149475.5-149475.29" switch \initial attribute \src "libresoc.v:149475.9-149475.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $1\ctr_zero_bo1[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ctr_zero_bo1[0:0] \$42 end sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end connect \$12 $eq$libresoc.v:149260$7304_Y connect \$14 $or$libresoc.v:149261$7305_Y connect \$17 $add$libresoc.v:149262$7306_Y connect \$19 $eq$libresoc.v:149263$7307_Y connect \$21 $or$libresoc.v:149264$7308_Y connect \$23 $eq$libresoc.v:149265$7309_Y connect \$25 $eq$libresoc.v:149266$7310_Y connect \$27 $eq$libresoc.v:149267$7311_Y connect \$29 $not$libresoc.v:149268$7312_Y connect \$31 $and$libresoc.v:149269$7313_Y connect \$33 $and$libresoc.v:149270$7314_Y connect \$36 $sub$libresoc.v:149271$7315_Y connect \$38 $pos$libresoc.v:149272$7317_Y connect \$40 $reduce_or$libresoc.v:149273$7318_Y connect \$42 $xor$libresoc.v:149274$7319_Y connect \$44 $not$libresoc.v:149275$7320_Y connect \$46 $and$libresoc.v:149276$7321_Y connect \$49 $add$libresoc.v:149277$7322_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \muxid$1 \muxid connect \nia_ok \br_taken connect \nia \br_addr connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end attribute \src "libresoc.v:149500.1-150450.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 attribute \src "libresoc.v:150415.3-150426.6" wire width 64 $0\a[63:0] attribute \src "libresoc.v:149913.3-149924.6" wire width 64 $0\a_s[63:0] attribute \src "libresoc.v:150427.3-150438.6" wire width 64 $0\b[63:0] attribute \src "libresoc.v:150196.3-150207.6" wire width 64 $0\b_s[63:0] attribute \src "libresoc.v:149989.3-150020.6" wire width 64 $0\fast1$11[63:0]$7386 attribute \src "libresoc.v:150021.3-150052.6" wire $0\fast1_ok[0:0] attribute \src "libresoc.v:150053.3-150135.6" wire width 64 $0\fast2$12[63:0]$7391 attribute \src "libresoc.v:150136.3-150167.6" wire $0\fast2_ok[0:0] attribute \src "libresoc.v:149501.7-149501.20" wire $0\initial[0:0] attribute \src "libresoc.v:150208.3-150376.6" wire width 64 $0\msr[63:0] attribute \src "libresoc.v:150208.3-150376.6" wire $0\msr_ok[0:0] attribute \src "libresoc.v:149925.3-149956.6" wire width 64 $0\nia[63:0] attribute \src "libresoc.v:149957.3-149988.6" wire $0\nia_ok[0:0] attribute \src "libresoc.v:150377.3-150395.6" wire width 64 $0\o[63:0] attribute \src "libresoc.v:150396.3-150414.6" wire $0\o_ok[0:0] attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$60[0:0]$7405 attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$61[0:0]$7406 attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$62[0:0]$7407 attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$67[0:0]$7408 attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$68[0:0]$7409 attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$69[0:0]$7410 attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal$70[0:0]$7411 attribute \src "libresoc.v:150168.3-150195.6" wire $0\trapexc_$signal[0:0]$7404 attribute \src "libresoc.v:150053.3-150135.6" wire $10\fast2$12[19:19]$7401 attribute \src "libresoc.v:150208.3-150376.6" wire width 2 $10\msr[5:4] attribute \src "libresoc.v:150208.3-150376.6" wire $11\msr[15:15] attribute \src "libresoc.v:150208.3-150376.6" wire $12\msr[12:12] attribute \src "libresoc.v:150208.3-150376.6" wire $13\msr[60:60] attribute \src "libresoc.v:150208.3-150376.6" wire $14\msr[12:12] attribute \src "libresoc.v:150208.3-150376.6" wire $15\msr[12:12] attribute \src "libresoc.v:150208.3-150376.6" wire width 2 $16\msr[5:4] attribute \src "libresoc.v:150208.3-150376.6" wire $17\msr[15:15] attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $18\msr[34:32] attribute \src "libresoc.v:150415.3-150426.6" wire width 64 $1\a[63:0] attribute \src "libresoc.v:149913.3-149924.6" wire width 64 $1\a_s[63:0] attribute \src "libresoc.v:150427.3-150438.6" wire width 64 $1\b[63:0] attribute \src "libresoc.v:150196.3-150207.6" wire width 64 $1\b_s[63:0] attribute \src "libresoc.v:149989.3-150020.6" wire width 64 $1\fast1$11[63:0]$7387 attribute \src "libresoc.v:150021.3-150052.6" wire $1\fast1_ok[0:0] attribute \src "libresoc.v:150053.3-150135.6" wire width 64 $1\fast2$12[63:0]$7392 attribute \src "libresoc.v:150136.3-150167.6" wire $1\fast2_ok[0:0] attribute \src "libresoc.v:150208.3-150376.6" wire width 64 $1\msr[63:0] attribute \src "libresoc.v:150208.3-150376.6" wire $1\msr_ok[0:0] attribute \src "libresoc.v:149925.3-149956.6" wire width 64 $1\nia[63:0] attribute \src "libresoc.v:149957.3-149988.6" wire $1\nia_ok[0:0] attribute \src "libresoc.v:150377.3-150395.6" wire width 64 $1\o[63:0] attribute \src "libresoc.v:150396.3-150414.6" wire $1\o_ok[0:0] attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$60[0:0]$7413 attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$61[0:0]$7414 attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$62[0:0]$7415 attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$67[0:0]$7416 attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$68[0:0]$7417 attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$69[0:0]$7418 attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal$70[0:0]$7419 attribute \src "libresoc.v:150168.3-150195.6" wire $1\trapexc_$signal[0:0]$7412 attribute \src "libresoc.v:149989.3-150020.6" wire width 64 $2\fast1$11[63:0]$7388 attribute \src "libresoc.v:150021.3-150052.6" wire $2\fast1_ok[0:0] attribute \src "libresoc.v:150053.3-150135.6" wire width 64 $2\fast2$12[63:0]$7393 attribute \src "libresoc.v:150136.3-150167.6" wire $2\fast2_ok[0:0] attribute \src "libresoc.v:150208.3-150376.6" wire width 64 $2\msr[63:0] attribute \src "libresoc.v:150208.3-150376.6" wire $2\msr_ok[0:0] attribute \src "libresoc.v:149925.3-149956.6" wire width 64 $2\nia[63:0] attribute \src "libresoc.v:149957.3-149988.6" wire $2\nia_ok[0:0] attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$60[0:0]$7421 attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$61[0:0]$7422 attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$62[0:0]$7423 attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$67[0:0]$7424 attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$68[0:0]$7425 attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$69[0:0]$7426 attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal$70[0:0]$7427 attribute \src "libresoc.v:150168.3-150195.6" wire $2\trapexc_$signal[0:0]$7420 attribute \src "libresoc.v:150053.3-150135.6" wire $3\fast2$12[17:17]$7394 attribute \src "libresoc.v:150208.3-150376.6" wire width 11 $3\msr[11:1] attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$60[0:0]$7429 attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$61[0:0]$7430 attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$62[0:0]$7431 attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$67[0:0]$7432 attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$68[0:0]$7433 attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$69[0:0]$7434 attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal$70[0:0]$7435 attribute \src "libresoc.v:150168.3-150195.6" wire $3\trapexc_$signal[0:0]$7428 attribute \src "libresoc.v:150053.3-150135.6" wire $4\fast2$12[18:18]$7395 attribute \src "libresoc.v:150208.3-150376.6" wire width 47 $4\msr[59:13] attribute \src "libresoc.v:150053.3-150135.6" wire $5\fast2$12[20:20]$7396 attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $5\msr[63:61] attribute \src "libresoc.v:150053.3-150135.6" wire $6\fast2$12[16:16]$7397 attribute \src "libresoc.v:150208.3-150376.6" wire width 11 $6\msr[11:1] attribute \src "libresoc.v:150053.3-150135.6" wire width 2 $7\fast2$12[19:18]$7398 attribute \src "libresoc.v:150208.3-150376.6" wire width 47 $7\msr[59:13] attribute \src "libresoc.v:150053.3-150135.6" wire $8\fast2$12[28:28]$7399 attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $8\msr[63:61] attribute \src "libresoc.v:150053.3-150135.6" wire $9\fast2$12[30:30]$7400 attribute \src "libresoc.v:150208.3-150376.6" wire width 3 $9\msr[34:32] attribute \src "libresoc.v:149889.18-149889.113" wire width 65 $add$libresoc.v:149889$7357_Y attribute \src "libresoc.v:149883.18-149883.108" wire width 5 $and$libresoc.v:149883$7350_Y attribute \src "libresoc.v:149891.18-149891.118" wire width 8 $and$libresoc.v:149891$7359_Y attribute \src "libresoc.v:149893.18-149893.118" wire width 8 $and$libresoc.v:149893$7361_Y attribute \src "libresoc.v:149895.18-149895.118" wire width 8 $and$libresoc.v:149895$7363_Y attribute \src "libresoc.v:149897.18-149897.119" wire width 8 $and$libresoc.v:149897$7365_Y attribute \src "libresoc.v:149899.18-149899.119" wire width 8 $and$libresoc.v:149899$7367_Y attribute \src "libresoc.v:149901.18-149901.119" wire width 8 $and$libresoc.v:149901$7369_Y attribute \src "libresoc.v:149907.18-149907.106" wire $and$libresoc.v:149907$7376_Y attribute \src "libresoc.v:149912.18-149912.106" wire $and$libresoc.v:149912$7381_Y attribute \src "libresoc.v:149882.18-149882.100" wire $eq$libresoc.v:149882$7349_Y attribute \src "libresoc.v:149890.18-149890.119" wire $eq$libresoc.v:149890$7358_Y attribute \src "libresoc.v:149904.18-149904.121" wire $eq$libresoc.v:149904$7373_Y attribute \src "libresoc.v:149905.18-149905.121" wire $eq$libresoc.v:149905$7374_Y attribute \src "libresoc.v:149906.18-149906.111" wire $eq$libresoc.v:149906$7375_Y attribute \src "libresoc.v:149910.18-149910.121" wire $eq$libresoc.v:149910$7379_Y attribute \src "libresoc.v:149911.18-149911.114" wire $eq$libresoc.v:149911$7380_Y attribute \src "libresoc.v:149876.18-149876.95" wire width 64 $extend$libresoc.v:149876$7341_Y attribute \src "libresoc.v:149877.18-149877.95" wire width 64 $extend$libresoc.v:149877$7343_Y attribute \src "libresoc.v:149888.18-149888.100" wire width 64 $extend$libresoc.v:149888$7355_Y attribute \src "libresoc.v:149903.18-149903.109" wire width 65 $extend$libresoc.v:149903$7371_Y attribute \src "libresoc.v:149879.18-149879.121" wire $gt$libresoc.v:149879$7346_Y attribute \src "libresoc.v:149881.18-149881.99" wire $gt$libresoc.v:149881$7348_Y attribute \src "libresoc.v:149878.18-149878.121" wire $lt$libresoc.v:149878$7345_Y attribute \src "libresoc.v:149880.18-149880.99" wire $lt$libresoc.v:149880$7347_Y attribute \src "libresoc.v:149908.18-149908.112" wire $not$libresoc.v:149908$7377_Y attribute \src "libresoc.v:149909.18-149909.112" wire $not$libresoc.v:149909$7378_Y attribute \src "libresoc.v:149886.18-149886.106" wire $or$libresoc.v:149886$7353_Y attribute \src "libresoc.v:149876.18-149876.95" wire width 64 $pos$libresoc.v:149876$7342_Y attribute \src "libresoc.v:149877.18-149877.95" wire width 64 $pos$libresoc.v:149877$7344_Y attribute \src "libresoc.v:149888.18-149888.100" wire width 64 $pos$libresoc.v:149888$7356_Y attribute \src "libresoc.v:149903.18-149903.109" wire width 65 $pos$libresoc.v:149903$7372_Y attribute \src "libresoc.v:149884.18-149884.100" wire $reduce_or$libresoc.v:149884$7351_Y attribute \src "libresoc.v:149885.18-149885.113" wire $reduce_or$libresoc.v:149885$7352_Y attribute \src "libresoc.v:149892.18-149892.91" wire $reduce_or$libresoc.v:149892$7360_Y attribute \src "libresoc.v:149894.18-149894.91" wire $reduce_or$libresoc.v:149894$7362_Y attribute \src "libresoc.v:149896.18-149896.91" wire $reduce_or$libresoc.v:149896$7364_Y attribute \src "libresoc.v:149898.18-149898.91" wire $reduce_or$libresoc.v:149898$7366_Y attribute \src "libresoc.v:149900.18-149900.91" wire $reduce_or$libresoc.v:149900$7368_Y attribute \src "libresoc.v:149902.18-149902.91" wire $reduce_or$libresoc.v:149902$7370_Y attribute \src "libresoc.v:149887.18-149887.120" wire width 20 $sshl$libresoc.v:149887$7354_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" wire width 5 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" wire width 64 \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" wire width 20 \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" wire width 65 \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" wire width 65 \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" wire \$42 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" wire width 8 \$45 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" wire width 8 \$49 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" wire width 8 \$53 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" wire width 8 \$57 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" wire width 8 \$64 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" wire width 8 \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 65 \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" wire \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" wire width 64 \a_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:142" wire width 64 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:139" wire width 64 \b_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" wire \equal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 12 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 26 \fast1$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 28 \fast2$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u attribute \src "libresoc.v:149501.7-149501.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" wire \lt_u attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 32 \msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 34 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 14 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 30 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" wire \should_trap attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" wire width 5 \to attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" wire width 5 \trap_bits attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 17 \trap_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 9 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 23 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 18 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 8 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 output 22 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 7 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 21 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" cell $add $add$libresoc.v:149889$7357 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 connect \Y $add$libresoc.v:149889$7357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" cell $and $and$libresoc.v:149883$7350 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to connect \Y $and$libresoc.v:149883$7350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" cell $and $and$libresoc.v:149891$7359 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 connect \Y $and$libresoc.v:149891$7359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" cell $and $and$libresoc.v:149893$7361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 connect \Y $and$libresoc.v:149893$7361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" cell $and $and$libresoc.v:149895$7363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 connect \Y $and$libresoc.v:149895$7363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" cell $and $and$libresoc.v:149897$7365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 connect \Y $and$libresoc.v:149897$7365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" cell $and $and$libresoc.v:149899$7367 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 connect \Y $and$libresoc.v:149899$7367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" cell $and $and$libresoc.v:149901$7369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 connect \Y $and$libresoc.v:149901$7369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" cell $and $and$libresoc.v:149907$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 connect \Y $and$libresoc.v:149907$7376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" cell $and $and$libresoc.v:149912$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 connect \Y $and$libresoc.v:149912$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" cell $eq $eq$libresoc.v:149882$7349 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 1 connect \A \a connect \B \b connect \Y $eq$libresoc.v:149882$7349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" cell $eq $eq$libresoc.v:149890$7358 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 connect \Y $eq$libresoc.v:149890$7358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" cell $eq $eq$libresoc.v:149904$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 connect \Y $eq$libresoc.v:149904$7373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" cell $eq $eq$libresoc.v:149905$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 connect \Y $eq$libresoc.v:149905$7374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" cell $eq $eq$libresoc.v:149906$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 connect \Y $eq$libresoc.v:149906$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" cell $eq $eq$libresoc.v:149910$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 connect \Y $eq$libresoc.v:149910$7379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" cell $eq $eq$libresoc.v:149911$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 connect \Y $eq$libresoc.v:149911$7380_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $extend$libresoc.v:149876$7341 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] connect \Y $extend$libresoc.v:149876$7341_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $extend$libresoc.v:149877$7343 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] connect \Y $extend$libresoc.v:149877$7343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" cell $pos $extend$libresoc.v:149888$7355 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 connect \Y $extend$libresoc.v:149888$7355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" cell $pos $extend$libresoc.v:149903$7371 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr connect \Y $extend$libresoc.v:149903$7371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" cell $gt $gt$libresoc.v:149879$7346 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 parameter \B_WIDTH 64 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s connect \Y $gt$libresoc.v:149879$7346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" cell $gt $gt$libresoc.v:149881$7348 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 1 connect \A \a connect \B \b connect \Y $gt$libresoc.v:149881$7348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" cell $lt $lt$libresoc.v:149878$7345 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 parameter \B_WIDTH 64 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s connect \Y $lt$libresoc.v:149878$7345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" cell $lt $lt$libresoc.v:149880$7347 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 1 connect \A \a connect \B \b connect \Y $lt$libresoc.v:149880$7347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" cell $not $not$libresoc.v:149908$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] connect \Y $not$libresoc.v:149908$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" cell $not $not$libresoc.v:149909$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] connect \Y $not$libresoc.v:149909$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" cell $or $or$libresoc.v:149886$7353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 connect \Y $or$libresoc.v:149886$7353_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $pos$libresoc.v:149876$7342 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:149876$7341_Y connect \Y $pos$libresoc.v:149876$7342_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $pos$libresoc.v:149877$7344 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:149877$7343_Y connect \Y $pos$libresoc.v:149877$7344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" cell $pos $pos$libresoc.v:149888$7356 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:149888$7355_Y connect \Y $pos$libresoc.v:149888$7356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" cell $pos $pos$libresoc.v:149903$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:149903$7371_Y connect \Y $pos$libresoc.v:149903$7372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" cell $reduce_or $reduce_or$libresoc.v:149884$7351 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 connect \Y $reduce_or$libresoc.v:149884$7351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" cell $reduce_or $reduce_or$libresoc.v:149885$7352 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \Y $reduce_or$libresoc.v:149885$7352_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:149892$7360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 connect \Y $reduce_or$libresoc.v:149892$7360_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:149894$7362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 connect \Y $reduce_or$libresoc.v:149894$7362_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:149896$7364 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 connect \Y $reduce_or$libresoc.v:149896$7364_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:149898$7366 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 connect \Y $reduce_or$libresoc.v:149898$7366_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:149900$7368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 connect \Y $reduce_or$libresoc.v:149900$7368_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:149902$7370 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 connect \Y $reduce_or$libresoc.v:149902$7370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" cell $sshl $sshl$libresoc.v:149887$7354 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 connect \Y $sshl$libresoc.v:149887$7354_Y end attribute \src "libresoc.v:149501.7-149501.20" process $proc$libresoc.v:149501$7442 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:149913.3-149924.6" process $proc$libresoc.v:149913$7382 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] attribute \src "libresoc.v:149914.5-149914.29" switch \initial attribute \src "libresoc.v:149914.9-149914.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\a_s[63:0] \ra end sync always update \a_s $0\a_s[63:0] end attribute \src "libresoc.v:149925.3-149956.6" process $proc$libresoc.v:149925$7383 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] attribute \src "libresoc.v:149926.5-149926.29" switch \initial attribute \src "libresoc.v:149926.9-149926.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\nia[63:0] $2\nia[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\nia[63:0] \$35 case assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { } { } assign $1\nia[63:0] { \fast1 [63:2] 2'00 } attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 case assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \nia $0\nia[63:0] end attribute \src "libresoc.v:149957.3-149988.6" process $proc$libresoc.v:149957$7384 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] attribute \src "libresoc.v:149958.5-149958.29" switch \initial attribute \src "libresoc.v:149958.9-149958.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\nia_ok[0:0] $2\nia_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\nia_ok[0:0] 1'1 case assign $2\nia_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\nia_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign $1\nia_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { } { } assign $1\nia_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } assign $1\nia_ok[0:0] 1'1 case assign $1\nia_ok[0:0] 1'0 end sync always update \nia_ok $0\nia_ok[0:0] end attribute \src "libresoc.v:149989.3-150020.6" process $proc$libresoc.v:149989$7385 assign { } { } assign { } { } assign $0\fast1$11[63:0]$7386 $1\fast1$11[63:0]$7387 attribute \src "libresoc.v:149990.5-149990.29" switch \initial attribute \src "libresoc.v:149990.9-149990.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\fast1$11[63:0]$7387 $2\fast1$11[63:0]$7388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast1$11[63:0]$7388 \trap_op__cia case assign $2\fast1$11[63:0]$7388 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } assign $1\fast1$11[63:0]$7387 \$39 [63:0] case assign $1\fast1$11[63:0]$7387 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fast1$11 $0\fast1$11[63:0]$7386 end attribute \src "libresoc.v:150021.3-150052.6" process $proc$libresoc.v:150021$7389 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] attribute \src "libresoc.v:150022.5-150022.29" switch \initial attribute \src "libresoc.v:150022.9-150022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast1_ok[0:0] 1'1 case assign $2\fast1_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\fast1_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign $1\fast1_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign $1\fast1_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } assign $1\fast1_ok[0:0] 1'1 case assign $1\fast1_ok[0:0] 1'0 end sync always update \fast1_ok $0\fast1_ok[0:0] end attribute \src "libresoc.v:150053.3-150135.6" process $proc$libresoc.v:150053$7390 assign { } { } assign { } { } assign $0\fast2$12[63:0]$7391 $1\fast2$12[63:0]$7392 attribute \src "libresoc.v:150054.5-150054.29" switch \initial attribute \src "libresoc.v:150054.9-150054.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\fast2$12[63:0]$7392 $2\fast2$12[63:0]$7393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { $2\fast2$12[63:0]$7393 [29] $2\fast2$12[63:0]$7393 [27] $2\fast2$12[63:0]$7393 [21] } 3'000 assign $2\fast2$12[63:0]$7393 [15:0] \trap_op__msr [15:0] assign $2\fast2$12[63:0]$7393 [26:22] \trap_op__msr [26:22] assign $2\fast2$12[63:0]$7393 [63:31] \trap_op__msr [63:31] assign $2\fast2$12[63:0]$7393 [17] $3\fast2$12[17:17]$7394 assign { } { } assign $2\fast2$12[63:0]$7393 [20] $5\fast2$12[20:20]$7396 assign $2\fast2$12[63:0]$7393 [16] $6\fast2$12[16:16]$7397 assign $2\fast2$12[63:0]$7393 [18] $7\fast2$12[19:18]$7398 [0] assign $2\fast2$12[63:0]$7393 [28] $8\fast2$12[28:28]$7399 assign $2\fast2$12[63:0]$7393 [30] $9\fast2$12[30:30]$7400 assign $2\fast2$12[63:0]$7393 [19] $10\fast2$12[19:19]$7401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fast2$12[17:17]$7394 1'1 case assign $3\fast2$12[17:17]$7394 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\fast2$12[18:18]$7395 1'1 case assign $4\fast2$12[18:18]$7395 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\fast2$12[20:20]$7396 1'1 case assign $5\fast2$12[20:20]$7396 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\fast2$12[16:16]$7397 1'1 case assign $6\fast2$12[16:16]$7397 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign $9\fast2$12[30:30]$7400 \trapexc_$signal assign $8\fast2$12[28:28]$7399 \trapexc_$signal$60 assign $7\fast2$12[19:18]$7398 [1] \trapexc_$signal$61 assign $7\fast2$12[19:18]$7398 [0] \trapexc_$signal$62 case assign $7\fast2$12[19:18]$7398 { 1'0 $4\fast2$12[18:18]$7395 } assign $8\fast2$12[28:28]$7399 1'0 assign $9\fast2$12[30:30]$7400 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $10\fast2$12[19:19]$7401 1'1 case assign $10\fast2$12[19:19]$7401 $7\fast2$12[19:18]$7398 [1] end case assign $2\fast2$12[63:0]$7393 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } assign { $1\fast2$12[63:0]$7392 [30:27] $1\fast2$12[63:0]$7392 [21:16] } 10'0000000000 assign $1\fast2$12[63:0]$7392 [15:0] \trap_op__msr [15:0] assign $1\fast2$12[63:0]$7392 [26:22] \trap_op__msr [26:22] assign $1\fast2$12[63:0]$7392 [63:31] \trap_op__msr [63:31] case assign $1\fast2$12[63:0]$7392 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fast2$12 $0\fast2$12[63:0]$7391 end attribute \src "libresoc.v:150136.3-150167.6" process $proc$libresoc.v:150136$7402 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] attribute \src "libresoc.v:150137.5-150137.29" switch \initial attribute \src "libresoc.v:150137.9-150137.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast2_ok[0:0] 1'1 case assign $2\fast2_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\fast2_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign $1\fast2_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign $1\fast2_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } assign $1\fast2_ok[0:0] 1'1 case assign $1\fast2_ok[0:0] 1'0 end sync always update \fast2_ok $0\fast2_ok[0:0] end attribute \src "libresoc.v:150168.3-150195.6" process $proc$libresoc.v:150168$7403 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\trapexc_$signal[0:0]$7404 $1\trapexc_$signal[0:0]$7412 assign $0\trapexc_$signal$60[0:0]$7405 $1\trapexc_$signal$60[0:0]$7413 assign $0\trapexc_$signal$61[0:0]$7406 $1\trapexc_$signal$61[0:0]$7414 assign $0\trapexc_$signal$62[0:0]$7407 $1\trapexc_$signal$62[0:0]$7415 assign $0\trapexc_$signal$67[0:0]$7408 $1\trapexc_$signal$67[0:0]$7416 assign $0\trapexc_$signal$68[0:0]$7409 $1\trapexc_$signal$68[0:0]$7417 assign $0\trapexc_$signal$69[0:0]$7410 $1\trapexc_$signal$69[0:0]$7418 assign $0\trapexc_$signal$70[0:0]$7411 $1\trapexc_$signal$70[0:0]$7419 attribute \src "libresoc.v:150169.5-150169.29" switch \initial attribute \src "libresoc.v:150169.9-150169.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\trapexc_$signal[0:0]$7412 $2\trapexc_$signal[0:0]$7420 assign $1\trapexc_$signal$60[0:0]$7413 $2\trapexc_$signal$60[0:0]$7421 assign $1\trapexc_$signal$61[0:0]$7414 $2\trapexc_$signal$61[0:0]$7422 assign $1\trapexc_$signal$62[0:0]$7415 $2\trapexc_$signal$62[0:0]$7423 assign $1\trapexc_$signal$67[0:0]$7416 $2\trapexc_$signal$67[0:0]$7424 assign $1\trapexc_$signal$68[0:0]$7417 $2\trapexc_$signal$68[0:0]$7425 assign $1\trapexc_$signal$69[0:0]$7418 $2\trapexc_$signal$69[0:0]$7426 assign $1\trapexc_$signal$70[0:0]$7419 $2\trapexc_$signal$70[0:0]$7427 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\trapexc_$signal[0:0]$7420 $3\trapexc_$signal[0:0]$7428 assign $2\trapexc_$signal$60[0:0]$7421 $3\trapexc_$signal$60[0:0]$7429 assign $2\trapexc_$signal$61[0:0]$7422 $3\trapexc_$signal$61[0:0]$7430 assign $2\trapexc_$signal$62[0:0]$7423 $3\trapexc_$signal$62[0:0]$7431 assign $2\trapexc_$signal$67[0:0]$7424 $3\trapexc_$signal$67[0:0]$7432 assign $2\trapexc_$signal$68[0:0]$7425 $3\trapexc_$signal$68[0:0]$7433 assign $2\trapexc_$signal$69[0:0]$7426 $3\trapexc_$signal$69[0:0]$7434 assign $2\trapexc_$signal$70[0:0]$7427 $3\trapexc_$signal$70[0:0]$7435 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $3\trapexc_$signal$70[0:0]$7435 $3\trapexc_$signal$62[0:0]$7431 $3\trapexc_$signal$60[0:0]$7429 $3\trapexc_$signal$61[0:0]$7430 $3\trapexc_$signal[0:0]$7428 $3\trapexc_$signal$69[0:0]$7434 $3\trapexc_$signal$68[0:0]$7433 $3\trapexc_$signal$67[0:0]$7432 } \trap_op__ldst_exc case assign $3\trapexc_$signal[0:0]$7428 1'0 assign $3\trapexc_$signal$60[0:0]$7429 1'0 assign $3\trapexc_$signal$61[0:0]$7430 1'0 assign $3\trapexc_$signal$62[0:0]$7431 1'0 assign $3\trapexc_$signal$67[0:0]$7432 1'0 assign $3\trapexc_$signal$68[0:0]$7433 1'0 assign $3\trapexc_$signal$69[0:0]$7434 1'0 assign $3\trapexc_$signal$70[0:0]$7435 1'0 end case assign $2\trapexc_$signal[0:0]$7420 1'0 assign $2\trapexc_$signal$60[0:0]$7421 1'0 assign $2\trapexc_$signal$61[0:0]$7422 1'0 assign $2\trapexc_$signal$62[0:0]$7423 1'0 assign $2\trapexc_$signal$67[0:0]$7424 1'0 assign $2\trapexc_$signal$68[0:0]$7425 1'0 assign $2\trapexc_$signal$69[0:0]$7426 1'0 assign $2\trapexc_$signal$70[0:0]$7427 1'0 end case assign $1\trapexc_$signal[0:0]$7412 1'0 assign $1\trapexc_$signal$60[0:0]$7413 1'0 assign $1\trapexc_$signal$61[0:0]$7414 1'0 assign $1\trapexc_$signal$62[0:0]$7415 1'0 assign $1\trapexc_$signal$67[0:0]$7416 1'0 assign $1\trapexc_$signal$68[0:0]$7417 1'0 assign $1\trapexc_$signal$69[0:0]$7418 1'0 assign $1\trapexc_$signal$70[0:0]$7419 1'0 end sync always update \trapexc_$signal $0\trapexc_$signal[0:0]$7404 update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7405 update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7406 update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7407 update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7408 update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7409 update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7410 update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7411 end attribute \src "libresoc.v:150196.3-150207.6" process $proc$libresoc.v:150196$7436 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] attribute \src "libresoc.v:150197.5-150197.29" switch \initial attribute \src "libresoc.v:150197.9-150197.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\b_s[63:0] \rb end sync always update \b_s $0\b_s[63:0] end attribute \src "libresoc.v:150208.3-150376.6" process $proc$libresoc.v:150208$7437 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] attribute \src "libresoc.v:150209.5-150209.29" switch \initial attribute \src "libresoc.v:150209.9-150209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign { } { } assign $1\msr[63:0] $2\msr[63:0] assign $1\msr_ok[0:0] $2\msr_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } assign $2\msr[63:0] [63] 1'1 assign $2\msr[63:0] [15] 1'0 assign $2\msr[63:0] [14] 1'0 assign $2\msr[63:0] [5] 1'0 assign $2\msr[63:0] [4] 1'0 assign $2\msr[63:0] [1] 1'0 assign $2\msr[63:0] [0] 1'1 assign $2\msr[63:0] [11] 1'0 assign $2\msr[63:0] [8] 1'0 assign $2\msr[63:0] [23] 1'0 assign $2\msr[63:0] [32] 1'0 assign $2\msr[63:0] [25] 1'0 assign $2\msr[63:0] [13] 1'0 assign $2\msr[63:0] [3] 1'0 assign $2\msr[63:0] [10] 1'0 assign $2\msr[63:0] [9] 1'0 assign $2\msr[63:0] [58] 1'0 assign $2\msr_ok[0:0] 1'1 case assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\msr_ok[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign { } { } assign { } { } assign $1\msr[63:0] [0] \$75 [0] assign $1\msr[63:0] [11:1] $3\msr[11:1] assign $1\msr[63:0] [59:13] $4\msr[59:13] assign $1\msr[63:0] [63:61] $5\msr[63:61] assign $1\msr[63:0] [12] $12\msr[12:12] assign $1\msr[63:0] [60] $13\msr[60:60] assign $1\msr_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" switch \trap_op__insn [21] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\msr[11:1] [10:1] \$75 [11:2] assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } assign $5\msr[63:61] \$75 [63:61] assign $3\msr[11:1] [0] \ra [1] assign $4\msr[59:13] [2] \ra [15] attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } assign $5\msr[63:61] $8\msr[63:61] assign $3\msr[11:1] [4:3] $10\msr[5:4] assign $4\msr[59:13] [2] $11\msr[15:15] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign $6\msr[11:1] \ra [11:1] assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } assign $8\msr[63:61] \ra [63:61] assign $7\msr[59:13] [21:19] $9\msr[34:32] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" switch \$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\msr[34:32] \trap_op__msr [34:32] case assign $9\msr[34:32] \ra [34:32] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $7\msr[59:13] [46:19] \$75 [59:32] assign $8\msr[63:61] \$75 [63:61] assign $6\msr[11:1] \ra [11:1] assign $7\msr[59:13] [18:0] \ra [31:13] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" switch $7\msr[59:13] [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $11\msr[15:15] 1'1 assign $10\msr[5:4] [1] 1'1 assign $10\msr[5:4] [0] 1'1 case assign $10\msr[5:4] $6\msr[11:1] [4:3] assign $11\msr[15:15] $7\msr[59:13] [2] end end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $13\msr[60:60] \trap_op__msr [60] assign $12\msr[12:12] \trap_op__msr [12] case assign $12\msr[12:12] \$75 [12] assign $13\msr[60:60] \$75 [60] end attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\msr_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 assign { } { } assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } assign $1\msr[63:0] [26:22] \fast2 [26:22] assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } assign $1\msr[63:0] [12] $14\msr[12:12] assign $1\msr[63:0] [5:4] $16\msr[5:4] assign $1\msr[63:0] [15] $17\msr[15:15] assign $1\msr[63:0] [34:32] $18\msr[34:32] assign $1\msr_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $14\msr[12:12] $15\msr[12:12] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" switch \trap_op__msr [60] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $15\msr[12:12] \fast2 [12] attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $15\msr[12:12] \trap_op__msr [12] end case assign $14\msr[12:12] \fast2 [12] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" switch \fast2 [14] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $17\msr[15:15] 1'1 assign $16\msr[5:4] [1] 1'1 assign $16\msr[5:4] [0] 1'1 case assign $16\msr[5:4] \fast2 [5:4] assign $17\msr[15:15] \fast2 [15] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $18\msr[34:32] \trap_op__msr [34:32] case assign $18\msr[34:32] \fast2 [34:32] end attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } assign { } { } assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } assign $1\msr[63:0] [63] 1'1 assign $1\msr[63:0] [15] 1'0 assign $1\msr[63:0] [14] 1'0 assign $1\msr[63:0] [5] 1'0 assign $1\msr[63:0] [4] 1'0 assign $1\msr[63:0] [1] 1'0 assign $1\msr[63:0] [0] 1'1 assign $1\msr[63:0] [11] 1'0 assign $1\msr[63:0] [8] 1'0 assign $1\msr[63:0] [23] 1'0 assign $1\msr[63:0] [32] 1'0 assign $1\msr[63:0] [25] 1'0 assign $1\msr[63:0] [13] 1'0 assign $1\msr[63:0] [3] 1'0 assign $1\msr[63:0] [10] 1'0 assign $1\msr[63:0] [9] 1'0 assign $1\msr[63:0] [58] 1'0 assign $1\msr_ok[0:0] 1'1 case assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\msr_ok[0:0] 1'0 end sync always update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end attribute \src "libresoc.v:150377.3-150395.6" process $proc$libresoc.v:150377$7438 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] attribute \src "libresoc.v:150378.5-150378.29" switch \initial attribute \src "libresoc.v:150378.9-150378.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign { } { } assign $1\o[63:0] \trap_op__msr case assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \o $0\o[63:0] end attribute \src "libresoc.v:150396.3-150414.6" process $proc$libresoc.v:150396$7439 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] attribute \src "libresoc.v:150397.5-150397.29" switch \initial attribute \src "libresoc.v:150397.9-150397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign $1\o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 assign $1\o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 assign { } { } assign $1\o_ok[0:0] 1'1 case assign $1\o_ok[0:0] 1'0 end sync always update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:150415.3-150426.6" process $proc$libresoc.v:150415$7440 assign { } { } assign $0\a[63:0] $1\a[63:0] attribute \src "libresoc.v:150416.5-150416.29" switch \initial attribute \src "libresoc.v:150416.9-150416.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\a[63:0] \$13 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\a[63:0] \ra end sync always update \a $0\a[63:0] end attribute \src "libresoc.v:150427.3-150438.6" process $proc$libresoc.v:150427$7441 assign { } { } assign $0\b[63:0] $1\b[63:0] attribute \src "libresoc.v:150428.5-150428.29" switch \initial attribute \src "libresoc.v:150428.9-150428.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\b[63:0] \$15 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\b[63:0] \rb end sync always update \b $0\b[63:0] end connect \$13 $pos$libresoc.v:149876$7342_Y connect \$15 $pos$libresoc.v:149877$7344_Y connect \$17 $lt$libresoc.v:149878$7345_Y connect \$19 $gt$libresoc.v:149879$7346_Y connect \$21 $lt$libresoc.v:149880$7347_Y connect \$23 $gt$libresoc.v:149881$7348_Y connect \$25 $eq$libresoc.v:149882$7349_Y connect \$28 $and$libresoc.v:149883$7350_Y connect \$27 $reduce_or$libresoc.v:149884$7351_Y connect \$31 $reduce_or$libresoc.v:149885$7352_Y connect \$33 $or$libresoc.v:149886$7353_Y connect \$36 $sshl$libresoc.v:149887$7354_Y connect \$35 $pos$libresoc.v:149888$7356_Y connect \$40 $add$libresoc.v:149889$7357_Y connect \$42 $eq$libresoc.v:149890$7358_Y connect \$45 $and$libresoc.v:149891$7359_Y connect \$44 $reduce_or$libresoc.v:149892$7360_Y connect \$49 $and$libresoc.v:149893$7361_Y connect \$48 $reduce_or$libresoc.v:149894$7362_Y connect \$53 $and$libresoc.v:149895$7363_Y connect \$52 $reduce_or$libresoc.v:149896$7364_Y connect \$57 $and$libresoc.v:149897$7365_Y connect \$56 $reduce_or$libresoc.v:149898$7366_Y connect \$64 $and$libresoc.v:149899$7367_Y connect \$63 $reduce_or$libresoc.v:149900$7368_Y connect \$72 $and$libresoc.v:149901$7369_Y connect \$71 $reduce_or$libresoc.v:149902$7370_Y connect \$75 $pos$libresoc.v:149903$7372_Y connect \$77 $eq$libresoc.v:149904$7373_Y connect \$79 $eq$libresoc.v:149905$7374_Y connect \$81 $eq$libresoc.v:149906$7375_Y connect \$83 $and$libresoc.v:149907$7376_Y connect \$85 $not$libresoc.v:149908$7377_Y connect \$87 $not$libresoc.v:149909$7378_Y connect \$89 $eq$libresoc.v:149910$7379_Y connect \$91 $eq$libresoc.v:149911$7380_Y connect \$93 $and$libresoc.v:149912$7381_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid connect \should_trap \$33 connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } connect \equal \$25 connect \gt_u \$23 connect \lt_u \$21 connect \gt_s \$19 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end attribute \src "libresoc.v:150454.1-151443.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 attribute \src "libresoc.v:151362.3-151396.6" wire width 32 $0\a32[31:0] attribute \src "libresoc.v:151211.3-151237.6" wire width 64 $0\b[63:0] attribute \src "libresoc.v:151145.3-151183.6" wire width 64 $0\bpermd_rb[63:0] attribute \src "libresoc.v:151106.3-151144.6" wire width 64 $0\bpermd_rs[63:0] attribute \src "libresoc.v:151071.3-151105.6" wire width 64 $0\clz_sig_in[63:0] attribute \src "libresoc.v:151397.3-151439.6" wire width 64 $0\cntz_i[63:0] attribute \src "libresoc.v:151327.3-151361.6" wire $0\count_right[0:0] attribute \src "libresoc.v:150455.7-150455.20" wire $0\initial[0:0] attribute \src "libresoc.v:151016.3-151070.6" wire width 64 $0\o[63:0] attribute \src "libresoc.v:151016.3-151070.6" wire $0\o_ok[0:0] attribute \src "libresoc.v:151265.3-151295.6" wire $0\par0[0:0] attribute \src "libresoc.v:151296.3-151326.6" wire $0\par1[0:0] attribute \src "libresoc.v:151184.3-151210.6" wire width 64 $0\popcount_a[63:0] attribute \src "libresoc.v:151238.3-151264.6" wire width 64 $0\popcount_data_len[63:0] attribute \src "libresoc.v:151362.3-151396.6" wire width 32 $1\a32[31:0] attribute \src "libresoc.v:151211.3-151237.6" wire width 64 $1\b[63:0] attribute \src "libresoc.v:151145.3-151183.6" wire width 64 $1\bpermd_rb[63:0] attribute \src "libresoc.v:151106.3-151144.6" wire width 64 $1\bpermd_rs[63:0] attribute \src "libresoc.v:151071.3-151105.6" wire width 64 $1\clz_sig_in[63:0] attribute \src "libresoc.v:151397.3-151439.6" wire width 64 $1\cntz_i[63:0] attribute \src "libresoc.v:151327.3-151361.6" wire $1\count_right[0:0] attribute \src "libresoc.v:151016.3-151070.6" wire width 64 $1\o[63:0] attribute \src "libresoc.v:151016.3-151070.6" wire $1\o_ok[0:0] attribute \src "libresoc.v:151265.3-151295.6" wire $1\par0[0:0] attribute \src "libresoc.v:151296.3-151326.6" wire $1\par1[0:0] attribute \src "libresoc.v:151184.3-151210.6" wire width 64 $1\popcount_a[63:0] attribute \src "libresoc.v:151238.3-151264.6" wire width 64 $1\popcount_data_len[63:0] attribute \src "libresoc.v:151397.3-151439.6" wire width 64 $2\cntz_i[63:0] attribute \src "libresoc.v:151016.3-151070.6" wire width 64 $2\o[63:0] attribute \src "libresoc.v:150963.18-150963.103" wire width 64 $and$libresoc.v:150963$7489_Y attribute \src "libresoc.v:150922.18-150922.118" wire $eq$libresoc.v:150922$7443_Y attribute \src "libresoc.v:150923.19-150923.119" wire $eq$libresoc.v:150923$7444_Y attribute \src "libresoc.v:150924.19-150924.119" wire $eq$libresoc.v:150924$7445_Y attribute \src "libresoc.v:150925.19-150925.119" wire $eq$libresoc.v:150925$7446_Y attribute \src "libresoc.v:150926.19-150926.119" wire $eq$libresoc.v:150926$7447_Y attribute \src "libresoc.v:150927.19-150927.119" wire $eq$libresoc.v:150927$7448_Y attribute \src "libresoc.v:150928.19-150928.119" wire $eq$libresoc.v:150928$7449_Y attribute \src "libresoc.v:150929.19-150929.119" wire $eq$libresoc.v:150929$7450_Y attribute \src "libresoc.v:150930.19-150930.119" wire $eq$libresoc.v:150930$7451_Y attribute \src "libresoc.v:150931.19-150931.119" wire $eq$libresoc.v:150931$7452_Y attribute \src "libresoc.v:150932.19-150932.119" wire $eq$libresoc.v:150932$7453_Y attribute \src "libresoc.v:150933.19-150933.119" wire $eq$libresoc.v:150933$7454_Y attribute \src "libresoc.v:150934.19-150934.119" wire $eq$libresoc.v:150934$7455_Y attribute \src "libresoc.v:150935.19-150935.119" wire $eq$libresoc.v:150935$7456_Y attribute \src "libresoc.v:150936.19-150936.119" wire $eq$libresoc.v:150936$7457_Y attribute \src "libresoc.v:150937.19-150937.119" wire $eq$libresoc.v:150937$7458_Y attribute \src "libresoc.v:150938.19-150938.119" wire $eq$libresoc.v:150938$7459_Y attribute \src "libresoc.v:150939.19-150939.119" wire $eq$libresoc.v:150939$7460_Y attribute \src "libresoc.v:150940.19-150940.119" wire $eq$libresoc.v:150940$7461_Y attribute \src "libresoc.v:150941.19-150941.119" wire $eq$libresoc.v:150941$7462_Y attribute \src "libresoc.v:150942.19-150942.119" wire $eq$libresoc.v:150942$7463_Y attribute \src "libresoc.v:150943.19-150943.119" wire $eq$libresoc.v:150943$7464_Y attribute \src "libresoc.v:150944.19-150944.119" wire $eq$libresoc.v:150944$7465_Y attribute \src "libresoc.v:150945.19-150945.119" wire $eq$libresoc.v:150945$7466_Y attribute \src "libresoc.v:150946.19-150946.119" wire $eq$libresoc.v:150946$7467_Y attribute \src "libresoc.v:150947.19-150947.119" wire $eq$libresoc.v:150947$7468_Y attribute \src "libresoc.v:150948.19-150948.119" wire $eq$libresoc.v:150948$7469_Y attribute \src "libresoc.v:150949.19-150949.119" wire $eq$libresoc.v:150949$7470_Y attribute \src "libresoc.v:150950.19-150950.128" wire $eq$libresoc.v:150950$7471_Y attribute \src "libresoc.v:150966.18-150966.114" wire $eq$libresoc.v:150966$7492_Y attribute \src "libresoc.v:150967.18-150967.114" wire $eq$libresoc.v:150967$7493_Y attribute \src "libresoc.v:150968.18-150968.114" wire $eq$libresoc.v:150968$7494_Y attribute \src "libresoc.v:150969.18-150969.114" wire $eq$libresoc.v:150969$7495_Y attribute \src "libresoc.v:150970.18-150970.114" wire $eq$libresoc.v:150970$7496_Y attribute \src "libresoc.v:150971.18-150971.114" wire $eq$libresoc.v:150971$7497_Y attribute \src "libresoc.v:150972.18-150972.114" wire $eq$libresoc.v:150972$7498_Y attribute \src "libresoc.v:150973.18-150973.114" wire $eq$libresoc.v:150973$7499_Y attribute \src "libresoc.v:150974.18-150974.116" wire $eq$libresoc.v:150974$7500_Y attribute \src "libresoc.v:150975.18-150975.116" wire $eq$libresoc.v:150975$7501_Y attribute \src "libresoc.v:150976.18-150976.116" wire $eq$libresoc.v:150976$7502_Y attribute \src "libresoc.v:150977.18-150977.116" wire $eq$libresoc.v:150977$7503_Y attribute \src "libresoc.v:150978.18-150978.116" wire $eq$libresoc.v:150978$7504_Y attribute \src "libresoc.v:150979.18-150979.116" wire $eq$libresoc.v:150979$7505_Y attribute \src "libresoc.v:150980.18-150980.116" wire $eq$libresoc.v:150980$7506_Y attribute \src "libresoc.v:150981.18-150981.116" wire $eq$libresoc.v:150981$7507_Y attribute \src "libresoc.v:150982.18-150982.118" wire $eq$libresoc.v:150982$7508_Y attribute \src "libresoc.v:150983.18-150983.118" wire $eq$libresoc.v:150983$7509_Y attribute \src "libresoc.v:150984.18-150984.118" wire $eq$libresoc.v:150984$7510_Y attribute \src "libresoc.v:150985.18-150985.118" wire $eq$libresoc.v:150985$7511_Y attribute \src "libresoc.v:150986.18-150986.118" wire $eq$libresoc.v:150986$7512_Y attribute \src "libresoc.v:150987.18-150987.118" wire $eq$libresoc.v:150987$7513_Y attribute \src "libresoc.v:150988.18-150988.118" wire $eq$libresoc.v:150988$7514_Y attribute \src "libresoc.v:150989.18-150989.118" wire $eq$libresoc.v:150989$7515_Y attribute \src "libresoc.v:150990.18-150990.118" wire $eq$libresoc.v:150990$7516_Y attribute \src "libresoc.v:150991.18-150991.118" wire $eq$libresoc.v:150991$7517_Y attribute \src "libresoc.v:150992.18-150992.118" wire $eq$libresoc.v:150992$7518_Y attribute \src "libresoc.v:150993.18-150993.118" wire $eq$libresoc.v:150993$7519_Y attribute \src "libresoc.v:150994.18-150994.118" wire $eq$libresoc.v:150994$7520_Y attribute \src "libresoc.v:150995.18-150995.118" wire $eq$libresoc.v:150995$7521_Y attribute \src "libresoc.v:150996.18-150996.118" wire $eq$libresoc.v:150996$7522_Y attribute \src "libresoc.v:150997.18-150997.118" wire $eq$libresoc.v:150997$7523_Y attribute \src "libresoc.v:150998.18-150998.118" wire $eq$libresoc.v:150998$7524_Y attribute \src "libresoc.v:150999.18-150999.118" wire $eq$libresoc.v:150999$7525_Y attribute \src "libresoc.v:151000.18-151000.118" wire $eq$libresoc.v:151000$7526_Y attribute \src "libresoc.v:151001.18-151001.118" wire $eq$libresoc.v:151001$7527_Y attribute \src "libresoc.v:150952.19-150952.104" wire width 64 $extend$libresoc.v:150952$7473_Y attribute \src "libresoc.v:150954.19-150954.93" wire width 8 $extend$libresoc.v:150954$7476_Y attribute \src "libresoc.v:150956.19-150956.105" wire width 64 $extend$libresoc.v:150956$7479_Y attribute \src "libresoc.v:150957.19-150957.118" wire width 64 $extend$libresoc.v:150957$7481_Y attribute \src "libresoc.v:150961.19-150961.105" wire width 64 $extend$libresoc.v:150961$7486_Y attribute \src "libresoc.v:150964.18-150964.103" wire width 64 $or$libresoc.v:150964$7490_Y attribute \src "libresoc.v:150952.19-150952.104" wire width 64 $pos$libresoc.v:150952$7474_Y attribute \src "libresoc.v:150954.19-150954.93" wire width 8 $pos$libresoc.v:150954$7477_Y attribute \src "libresoc.v:150956.19-150956.105" wire width 64 $pos$libresoc.v:150956$7480_Y attribute \src "libresoc.v:150957.19-150957.118" wire width 64 $pos$libresoc.v:150957$7482_Y attribute \src "libresoc.v:150961.19-150961.105" wire width 64 $pos$libresoc.v:150961$7487_Y attribute \src "libresoc.v:150958.19-150958.131" wire $reduce_xor$libresoc.v:150958$7483_Y attribute \src "libresoc.v:150959.19-150959.133" wire $reduce_xor$libresoc.v:150959$7484_Y attribute \src "libresoc.v:150953.19-150953.112" wire width 8 $sub$libresoc.v:150953$7475_Y attribute \src "libresoc.v:150955.19-150955.135" wire width 8 $ternary$libresoc.v:150955$7478_Y attribute \src "libresoc.v:150960.19-150960.398" wire width 32 $ternary$libresoc.v:150960$7485_Y attribute \src "libresoc.v:150962.19-150962.621" wire width 64 $ternary$libresoc.v:150962$7488_Y attribute \src "libresoc.v:150951.19-150951.108" wire $xor$libresoc.v:150951$7472_Y attribute \src "libresoc.v:150965.18-150965.103" wire width 64 $xor$libresoc.v:150965$7491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" wire \$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" wire width 64 \$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" wire \$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" wire width 64 \$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" wire width 8 \$162 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 8 \$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" wire width 8 \$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" wire \$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" wire \$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" wire width 64 \$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" wire width 32 \$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" wire width 64 \$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" wire width 64 \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" wire width 64 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" wire width 32 \a32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" wire width 64 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" wire width 64 \bpermd_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" wire width 64 \bpermd_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 \bpermd_rs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 7 \clz_lz attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" wire width 64 \clz_sig_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right attribute \src "libresoc.v:150455.7-150455.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 33 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 40 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 41 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" wire \par0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" wire \par1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" wire width 64 \popcount_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 \popcount_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 \popcount_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" cell $and $and$libresoc.v:150963$7489 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb connect \Y $and$libresoc.v:150963$7489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150922$7443 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:150922$7443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150923$7444 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:150923$7444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150924$7445 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:150924$7445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150925$7446 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:150925$7446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150926$7447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150926$7447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150927$7448 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150927$7448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150928$7449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150928$7449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150929$7450 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150929$7450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150930$7451 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150930$7451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150931$7452 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150931$7452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150932$7453 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150932$7453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150933$7454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] connect \Y $eq$libresoc.v:150933$7454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150934$7455 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150934$7455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150935$7456 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150935$7456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150936$7457 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150936$7457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150937$7458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150937$7458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150938$7459 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150938$7459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150939$7460 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150939$7460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150940$7461 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150940$7461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150941$7462 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] connect \Y $eq$libresoc.v:150941$7462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150942$7463 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150942$7463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150943$7464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150943$7464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150944$7465 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150944$7465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150945$7466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150945$7466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150946$7467 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150946$7467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150947$7468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150947$7468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150948$7469 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150948$7469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150949$7470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] connect \Y $eq$libresoc.v:150949$7470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" cell $eq $eq$libresoc.v:150950$7471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 connect \Y $eq$libresoc.v:150950$7471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150966$7492 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150966$7492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150967$7493 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150967$7493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150968$7494 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150968$7494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150969$7495 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150969$7495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150970$7496 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150970$7496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150971$7497 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150971$7497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150972$7498 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150972$7498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150973$7499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] connect \Y $eq$libresoc.v:150973$7499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150974$7500 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150974$7500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150975$7501 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150975$7501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150976$7502 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150976$7502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150977$7503 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150977$7503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150978$7504 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150978$7504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150979$7505 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150979$7505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150980$7506 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150980$7506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150981$7507 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] connect \Y $eq$libresoc.v:150981$7507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150982$7508 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150982$7508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150983$7509 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150983$7509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150984$7510 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150984$7510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150985$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150985$7511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150986$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150986$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150987$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150987$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150988$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150988$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150989$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] connect \Y $eq$libresoc.v:150989$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150990$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150990$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150991$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150991$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150992$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150992$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150993$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150993$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150994$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150994$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150995$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150995$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150996$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150996$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150997$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] connect \Y $eq$libresoc.v:150997$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150998$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:150998$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:150999$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:150999$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:151000$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:151000$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" cell $eq $eq$libresoc.v:151001$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] connect \Y $eq$libresoc.v:151001$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" cell $pos $extend$libresoc.v:150952$7473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 connect \Y $extend$libresoc.v:150952$7473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" cell $pos $extend$libresoc.v:150954$7476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz connect \Y $extend$libresoc.v:150954$7476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" cell $pos $extend$libresoc.v:150956$7479 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 connect \Y $extend$libresoc.v:150956$7479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" cell $pos $extend$libresoc.v:150957$7481 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len connect \Y $extend$libresoc.v:150957$7481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" cell $pos $extend$libresoc.v:150961$7486 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 connect \Y $extend$libresoc.v:150961$7486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" cell $or $or$libresoc.v:150964$7490 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb connect \Y $or$libresoc.v:150964$7490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" cell $pos $pos$libresoc.v:150952$7474 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:150952$7473_Y connect \Y $pos$libresoc.v:150952$7474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" cell $pos $pos$libresoc.v:150954$7477 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:150954$7476_Y connect \Y $pos$libresoc.v:150954$7477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" cell $pos $pos$libresoc.v:150956$7480 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:150956$7479_Y connect \Y $pos$libresoc.v:150956$7480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" cell $pos $pos$libresoc.v:150957$7482 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:150957$7481_Y connect \Y $pos$libresoc.v:150957$7482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" cell $pos $pos$libresoc.v:150961$7487 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:150961$7486_Y connect \Y $pos$libresoc.v:150961$7487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" cell $reduce_xor $reduce_xor$libresoc.v:150958$7483 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } connect \Y $reduce_xor$libresoc.v:150958$7483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" cell $reduce_xor $reduce_xor$libresoc.v:150959$7484 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } connect \Y $reduce_xor$libresoc.v:150959$7484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" cell $sub $sub$libresoc.v:150953$7475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 connect \Y $sub$libresoc.v:150953$7475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" cell $mux $ternary$libresoc.v:150955$7478 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit connect \Y $ternary$libresoc.v:150955$7478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" cell $mux $ternary$libresoc.v:150960$7485 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right connect \Y $ternary$libresoc.v:150960$7485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" cell $mux $ternary$libresoc.v:150962$7488 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right connect \Y $ternary$libresoc.v:150962$7488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" cell $xor $xor$libresoc.v:150951$7472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 connect \Y $xor$libresoc.v:150951$7472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" cell $xor $xor$libresoc.v:150965$7491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb connect \Y $xor$libresoc.v:150965$7491_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:151002.10-151006.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 attribute \src "libresoc.v:151007.7-151010.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 attribute \src "libresoc.v:151011.12-151015.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end attribute \src "libresoc.v:150455.7-150455.20" process $proc$libresoc.v:150455$7540 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:151016.3-151070.6" process $proc$libresoc.v:151016$7528 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] attribute \src "libresoc.v:151017.5-151017.29" switch \initial attribute \src "libresoc.v:151017.9-151017.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] \$21 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] \$23 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] \$25 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] \popcount_o attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] $2\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" switch \$155 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o[63:0] \$157 attribute \src "libresoc.v:0.0-0.0" case assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 assign $2\o[63:0] [0] \par0 assign $2\o[63:0] [32] \par1 end attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] \$161 attribute \src "libresoc.v:0.0-0.0" case 7'0001001 assign $1\o_ok[0:0] 1'1 assign { } { } assign $1\o[63:0] \bpermd_ra attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\o_ok[0:0] 1'0 end sync always update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end attribute \src "libresoc.v:151071.3-151105.6" process $proc$libresoc.v:151071$7529 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] attribute \src "libresoc.v:151072.5-151072.29" switch \initial attribute \src "libresoc.v:151072.9-151072.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\clz_sig_in[63:0] \cntz_i case assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \clz_sig_in $0\clz_sig_in[63:0] end attribute \src "libresoc.v:151106.3-151144.6" process $proc$libresoc.v:151106$7530 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] attribute \src "libresoc.v:151107.5-151107.29" switch \initial attribute \src "libresoc.v:151107.9-151107.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001001 assign { } { } assign $1\bpermd_rs[63:0] \ra case assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \bpermd_rs $0\bpermd_rs[63:0] end attribute \src "libresoc.v:151145.3-151183.6" process $proc$libresoc.v:151145$7531 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] attribute \src "libresoc.v:151146.5-151146.29" switch \initial attribute \src "libresoc.v:151146.9-151146.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001001 assign { } { } assign $1\bpermd_rb[63:0] \rb case assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \bpermd_rb $0\bpermd_rb[63:0] end attribute \src "libresoc.v:151184.3-151210.6" process $proc$libresoc.v:151184$7532 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] attribute \src "libresoc.v:151185.5-151185.29" switch \initial attribute \src "libresoc.v:151185.9-151185.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\popcount_a[63:0] \ra case assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \popcount_a $0\popcount_a[63:0] end attribute \src "libresoc.v:151211.3-151237.6" process $proc$libresoc.v:151211$7533 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] attribute \src "libresoc.v:151212.5-151212.29" switch \initial attribute \src "libresoc.v:151212.9-151212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\b[63:0] \rb case assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \b $0\b[63:0] end attribute \src "libresoc.v:151238.3-151264.6" process $proc$libresoc.v:151238$7534 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] attribute \src "libresoc.v:151239.5-151239.29" switch \initial attribute \src "libresoc.v:151239.9-151239.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\popcount_data_len[63:0] \$169 case assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \popcount_data_len $0\popcount_data_len[63:0] end attribute \src "libresoc.v:151265.3-151295.6" process $proc$libresoc.v:151265$7535 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] attribute \src "libresoc.v:151266.5-151266.29" switch \initial attribute \src "libresoc.v:151266.9-151266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\par0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\par0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\par0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\par0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\par0[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign { } { } assign $1\par0[0:0] \$171 case assign $1\par0[0:0] 1'0 end sync always update \par0 $0\par0[0:0] end attribute \src "libresoc.v:151296.3-151326.6" process $proc$libresoc.v:151296$7536 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] attribute \src "libresoc.v:151297.5-151297.29" switch \initial attribute \src "libresoc.v:151297.9-151297.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\par1[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\par1[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\par1[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\par1[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\par1[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign { } { } assign $1\par1[0:0] \$173 case assign $1\par1[0:0] 1'0 end sync always update \par1 $0\par1[0:0] end attribute \src "libresoc.v:151327.3-151361.6" process $proc$libresoc.v:151327$7537 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] attribute \src "libresoc.v:151328.5-151328.29" switch \initial attribute \src "libresoc.v:151328.9-151328.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\count_right[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\count_right[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\count_right[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\count_right[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\count_right[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign $1\count_right[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\count_right[0:0] \logical_op__insn [10] case assign $1\count_right[0:0] 1'0 end sync always update \count_right $0\count_right[0:0] end attribute \src "libresoc.v:151362.3-151396.6" process $proc$libresoc.v:151362$7538 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] attribute \src "libresoc.v:151363.5-151363.29" switch \initial attribute \src "libresoc.v:151363.9-151363.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\a32[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\a32[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\a32[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\a32[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\a32[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign $1\a32[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\a32[31:0] \ra [31:0] case assign $1\a32[31:0] 0 end sync always update \a32 $0\a32[31:0] end attribute \src "libresoc.v:151397.3-151439.6" process $proc$libresoc.v:151397$7539 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] attribute \src "libresoc.v:151398.5-151398.29" switch \initial attribute \src "libresoc.v:151398.9-151398.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000100 assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110101 assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000011 assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001011 assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\cntz_i[63:0] $2\cntz_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cntz_i[63:0] \$175 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\cntz_i[63:0] \$179 end case assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \cntz_i $0\cntz_i[63:0] end connect \$99 $eq$libresoc.v:150922$7443_Y connect \$101 $eq$libresoc.v:150923$7444_Y connect \$103 $eq$libresoc.v:150924$7445_Y connect \$105 $eq$libresoc.v:150925$7446_Y connect \$107 $eq$libresoc.v:150926$7447_Y connect \$109 $eq$libresoc.v:150927$7448_Y connect \$111 $eq$libresoc.v:150928$7449_Y connect \$113 $eq$libresoc.v:150929$7450_Y connect \$115 $eq$libresoc.v:150930$7451_Y connect \$117 $eq$libresoc.v:150931$7452_Y connect \$119 $eq$libresoc.v:150932$7453_Y connect \$121 $eq$libresoc.v:150933$7454_Y connect \$123 $eq$libresoc.v:150934$7455_Y connect \$125 $eq$libresoc.v:150935$7456_Y connect \$127 $eq$libresoc.v:150936$7457_Y connect \$129 $eq$libresoc.v:150937$7458_Y connect \$131 $eq$libresoc.v:150938$7459_Y connect \$133 $eq$libresoc.v:150939$7460_Y connect \$135 $eq$libresoc.v:150940$7461_Y connect \$137 $eq$libresoc.v:150941$7462_Y connect \$139 $eq$libresoc.v:150942$7463_Y connect \$141 $eq$libresoc.v:150943$7464_Y connect \$143 $eq$libresoc.v:150944$7465_Y connect \$145 $eq$libresoc.v:150945$7466_Y connect \$147 $eq$libresoc.v:150946$7467_Y connect \$149 $eq$libresoc.v:150947$7468_Y connect \$151 $eq$libresoc.v:150948$7469_Y connect \$153 $eq$libresoc.v:150949$7470_Y connect \$155 $eq$libresoc.v:150950$7471_Y connect \$158 $xor$libresoc.v:150951$7472_Y connect \$157 $pos$libresoc.v:150952$7474_Y connect \$162 $sub$libresoc.v:150953$7475_Y connect \$164 $pos$libresoc.v:150954$7477_Y connect \$166 $ternary$libresoc.v:150955$7478_Y connect \$161 $pos$libresoc.v:150956$7480_Y connect \$169 $pos$libresoc.v:150957$7482_Y connect \$171 $reduce_xor$libresoc.v:150958$7483_Y connect \$173 $reduce_xor$libresoc.v:150959$7484_Y connect \$176 $ternary$libresoc.v:150960$7485_Y connect \$175 $pos$libresoc.v:150961$7487_Y connect \$179 $ternary$libresoc.v:150962$7488_Y connect \$21 $and$libresoc.v:150963$7489_Y connect \$23 $or$libresoc.v:150964$7490_Y connect \$25 $xor$libresoc.v:150965$7491_Y connect \$27 $eq$libresoc.v:150966$7492_Y connect \$29 $eq$libresoc.v:150967$7493_Y connect \$31 $eq$libresoc.v:150968$7494_Y connect \$33 $eq$libresoc.v:150969$7495_Y connect \$35 $eq$libresoc.v:150970$7496_Y connect \$37 $eq$libresoc.v:150971$7497_Y connect \$39 $eq$libresoc.v:150972$7498_Y connect \$41 $eq$libresoc.v:150973$7499_Y connect \$43 $eq$libresoc.v:150974$7500_Y connect \$45 $eq$libresoc.v:150975$7501_Y connect \$47 $eq$libresoc.v:150976$7502_Y connect \$49 $eq$libresoc.v:150977$7503_Y connect \$51 $eq$libresoc.v:150978$7504_Y connect \$53 $eq$libresoc.v:150979$7505_Y connect \$55 $eq$libresoc.v:150980$7506_Y connect \$57 $eq$libresoc.v:150981$7507_Y connect \$59 $eq$libresoc.v:150982$7508_Y connect \$61 $eq$libresoc.v:150983$7509_Y connect \$63 $eq$libresoc.v:150984$7510_Y connect \$65 $eq$libresoc.v:150985$7511_Y connect \$67 $eq$libresoc.v:150986$7512_Y connect \$69 $eq$libresoc.v:150987$7513_Y connect \$71 $eq$libresoc.v:150988$7514_Y connect \$73 $eq$libresoc.v:150989$7515_Y connect \$75 $eq$libresoc.v:150990$7516_Y connect \$77 $eq$libresoc.v:150991$7517_Y connect \$79 $eq$libresoc.v:150992$7518_Y connect \$81 $eq$libresoc.v:150993$7519_Y connect \$83 $eq$libresoc.v:150994$7520_Y connect \$85 $eq$libresoc.v:150995$7521_Y connect \$87 $eq$libresoc.v:150996$7522_Y connect \$89 $eq$libresoc.v:150997$7523_Y connect \$91 $eq$libresoc.v:150998$7524_Y connect \$93 $eq$libresoc.v:150999$7525_Y connect \$95 $eq$libresoc.v:151000$7526_Y connect \$97 $eq$libresoc.v:151001$7527_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end attribute \src "libresoc.v:151447.1-152050.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 attribute \src "libresoc.v:151837.3-151863.6" wire width 2 $0\BC[1:0] attribute \src "libresoc.v:151931.3-151945.6" wire width 2 $0\ba[1:0] attribute \src "libresoc.v:151946.3-151960.6" wire width 2 $0\bb[1:0] attribute \src "libresoc.v:151961.3-151985.6" wire $0\bit_a[0:0] attribute \src "libresoc.v:151986.3-152010.6" wire $0\bit_b[0:0] attribute \src "libresoc.v:152011.3-152025.6" wire $0\bit_o[0:0] attribute \src "libresoc.v:151916.3-151930.6" wire width 2 $0\bt[1:0] attribute \src "libresoc.v:151729.3-151763.6" wire width 4 $0\cr_a$6[3:0]$7555 attribute \src "libresoc.v:151729.3-151763.6" wire $0\cr_a_ok[0:0] attribute \src "libresoc.v:151864.3-151900.6" wire $0\cr_bit[0:0] attribute \src "libresoc.v:152026.3-152044.6" wire width 32 $0\full_cr$5[31:0]$7570 attribute \src "libresoc.v:151764.3-151782.6" wire $0\full_cr_ok[0:0] attribute \src "libresoc.v:151448.7-151448.20" wire $0\initial[0:0] attribute \src "libresoc.v:151901.3-151915.6" wire width 4 $0\lut[3:0] attribute \src "libresoc.v:151783.3-151836.6" wire width 64 $0\o[63:0] attribute \src "libresoc.v:151783.3-151836.6" wire $0\o_ok[0:0] attribute \src "libresoc.v:151837.3-151863.6" wire width 2 $1\BC[1:0] attribute \src "libresoc.v:151931.3-151945.6" wire width 2 $1\ba[1:0] attribute \src "libresoc.v:151946.3-151960.6" wire width 2 $1\bb[1:0] attribute \src "libresoc.v:151961.3-151985.6" wire $1\bit_a[0:0] attribute \src "libresoc.v:151986.3-152010.6" wire $1\bit_b[0:0] attribute \src "libresoc.v:152011.3-152025.6" wire $1\bit_o[0:0] attribute \src "libresoc.v:151916.3-151930.6" wire width 2 $1\bt[1:0] attribute \src "libresoc.v:151729.3-151763.6" wire width 4 $1\cr_a$6[3:0]$7556 attribute \src "libresoc.v:151729.3-151763.6" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:151864.3-151900.6" wire $1\cr_bit[0:0] attribute \src "libresoc.v:152026.3-152044.6" wire width 32 $1\full_cr$5[31:0]$7571 attribute \src "libresoc.v:151764.3-151782.6" wire $1\full_cr_ok[0:0] attribute \src "libresoc.v:151901.3-151915.6" wire width 4 $1\lut[3:0] attribute \src "libresoc.v:151783.3-151836.6" wire width 64 $1\o[63:0] attribute \src "libresoc.v:151783.3-151836.6" wire $1\o_ok[0:0] attribute \src "libresoc.v:151961.3-151985.6" wire $2\bit_a[0:0] attribute \src "libresoc.v:151986.3-152010.6" wire $2\bit_b[0:0] attribute \src "libresoc.v:151729.3-151763.6" wire width 4 $2\cr_a$6[3:0]$7557 attribute \src "libresoc.v:151864.3-151900.6" wire $2\cr_bit[0:0] attribute \src "libresoc.v:151783.3-151836.6" wire width 64 $2\o[63:0] attribute \src "libresoc.v:151725.18-151725.96" wire width 64 $extend$libresoc.v:151725$7547_Y attribute \src "libresoc.v:151727.18-151727.98" wire width 65 $extend$libresoc.v:151727$7550_Y attribute \src "libresoc.v:151728.17-151728.92" wire width 5 $extend$libresoc.v:151728$7552_Y attribute \src "libresoc.v:151725.18-151725.96" wire width 64 $pos$libresoc.v:151725$7548_Y attribute \src "libresoc.v:151727.18-151727.98" wire width 65 $pos$libresoc.v:151727$7551_Y attribute \src "libresoc.v:151728.17-151728.92" wire width 5 $pos$libresoc.v:151728$7553_Y attribute \src "libresoc.v:151719.18-151719.116" wire width 3 $sub$libresoc.v:151719$7541_Y attribute \src "libresoc.v:151720.18-151720.116" wire width 3 $sub$libresoc.v:151720$7542_Y attribute \src "libresoc.v:151721.18-151721.116" wire width 3 $sub$libresoc.v:151721$7543_Y attribute \src "libresoc.v:151722.18-151722.114" wire $ternary$libresoc.v:151722$7544_Y attribute \src "libresoc.v:151723.18-151723.115" wire $ternary$libresoc.v:151723$7545_Y attribute \src "libresoc.v:151724.18-151724.112" wire $ternary$libresoc.v:151724$7546_Y attribute \src "libresoc.v:151726.18-151726.108" wire width 64 $ternary$libresoc.v:151726$7549_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" wire width 3 \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" wire width 3 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" wire width 65 \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" wire width 64 \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" wire width 2 \BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" wire width 2 \ba attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" wire width 2 \bb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" wire \bit_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" wire \bit_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" wire \bit_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" wire width 2 \bt attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 7 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 18 \cr_a$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 19 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 8 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" wire \cr_bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 9 \cr_c attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \cr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 12 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 13 \cr_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 11 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 6 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \full_cr_ok attribute \src "libresoc.v:151448.7-151448.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 20 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 10 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 14 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 15 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 4 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:151725$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr connect \Y $extend$libresoc.v:151725$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" cell $pos $extend$libresoc.v:151727$7550 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 connect \Y $extend$libresoc.v:151727$7550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:151728$7552 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a connect \Y $extend$libresoc.v:151728$7552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:151725$7548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:151725$7547_Y connect \Y $pos$libresoc.v:151725$7548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" cell $pos $pos$libresoc.v:151727$7551 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:151727$7550_Y connect \Y $pos$libresoc.v:151727$7551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:151728$7553 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A $extend$libresoc.v:151728$7552_Y connect \Y $pos$libresoc.v:151728$7553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" cell $sub $sub$libresoc.v:151719$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] connect \Y $sub$libresoc.v:151719$7541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" cell $sub $sub$libresoc.v:151720$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] connect \Y $sub$libresoc.v:151720$7542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" cell $sub $sub$libresoc.v:151721$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] connect \Y $sub$libresoc.v:151721$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" cell $mux $ternary$libresoc.v:151722$7544 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a connect \Y $ternary$libresoc.v:151722$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" cell $mux $ternary$libresoc.v:151723$7545 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a connect \Y $ternary$libresoc.v:151723$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" cell $mux $ternary$libresoc.v:151724$7546 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b connect \Y $ternary$libresoc.v:151724$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" cell $mux $ternary$libresoc.v:151726$7549 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit connect \Y $ternary$libresoc.v:151726$7549_Y end attribute \src "libresoc.v:151448.7-151448.20" process $proc$libresoc.v:151448$7572 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:151729.3-151763.6" process $proc$libresoc.v:151729$7554 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] assign $0\cr_a$6[3:0]$7555 $1\cr_a$6[3:0]$7556 attribute \src "libresoc.v:151730.5-151730.29" switch \initial attribute \src "libresoc.v:151730.9-151730.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign { } { } assign { } { } assign $1\cr_a$6[3:0]$7556 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } assign $1\cr_a$6[3:0]$7556 $2\cr_a$6[3:0]$7557 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $2\cr_a$6[3:0]$7557 [3:1] \cr_c [3:1] assign $2\cr_a$6[3:0]$7557 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { $2\cr_a$6[3:0]$7557 [3:2] $2\cr_a$6[3:0]$7557 [0] } { \cr_c [3:2] \cr_c [0] } assign $2\cr_a$6[3:0]$7557 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { $2\cr_a$6[3:0]$7557 [3] $2\cr_a$6[3:0]$7557 [1:0] } { \cr_c [3] \cr_c [1:0] } assign $2\cr_a$6[3:0]$7557 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- assign $2\cr_a$6[3:0]$7557 [2:0] \cr_c [2:0] assign $2\cr_a$6[3:0]$7557 [3] \bit_o case assign $2\cr_a$6[3:0]$7557 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 assign $1\cr_a$6[3:0]$7556 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] update \cr_a$6 $0\cr_a$6[3:0]$7555 end attribute \src "libresoc.v:151764.3-151782.6" process $proc$libresoc.v:151764$7558 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] attribute \src "libresoc.v:151765.5-151765.29" switch \initial attribute \src "libresoc.v:151765.9-151765.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\full_cr_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign $1\full_cr_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } assign $1\full_cr_ok[0:0] 1'1 case assign $1\full_cr_ok[0:0] 1'0 end sync always update \full_cr_ok $0\full_cr_ok[0:0] end attribute \src "libresoc.v:151783.3-151836.6" process $proc$libresoc.v:151783$7559 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] attribute \src "libresoc.v:151784.5-151784.29" switch \initial attribute \src "libresoc.v:151784.9-151784.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\o_ok[0:0] 1'0 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign $1\o_ok[0:0] 1'0 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign $1\o_ok[0:0] 1'0 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0101101 assign { } { } assign { } { } assign $1\o[63:0] \$24 assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0100011 assign { } { } assign { } { } assign $1\o[63:0] \$26 [63:0] assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0111011 assign { } { } assign { } { } assign $1\o[63:0] $2\o[63:0] assign $1\o_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" switch { \cr_a [2] \cr_a [3] } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $1\o_ok[0:0] 1'0 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end attribute \src "libresoc.v:151837.3-151863.6" process $proc$libresoc.v:151837$7560 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] attribute \src "libresoc.v:151838.5-151838.29" switch \initial attribute \src "libresoc.v:151838.9-151838.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\BC[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign $1\BC[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign $1\BC[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0101101 assign $1\BC[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0100011 assign { } { } assign $1\BC[1:0] \cr_op__insn [7:6] case assign $1\BC[1:0] 2'00 end sync always update \BC $0\BC[1:0] end attribute \src "libresoc.v:151864.3-151900.6" process $proc$libresoc.v:151864$7561 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] attribute \src "libresoc.v:151865.5-151865.29" switch \initial attribute \src "libresoc.v:151865.9-151865.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\cr_bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign $1\cr_bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign $1\cr_bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0101101 assign $1\cr_bit[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0100011 assign { } { } assign $1\cr_bit[0:0] $2\cr_bit[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" switch \BC attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $2\cr_bit[0:0] \cr_a [3] attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $2\cr_bit[0:0] \cr_a [2] attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\cr_bit[0:0] \cr_a [1] attribute \src "libresoc.v:0.0-0.0" case 2'-- assign { } { } assign $2\cr_bit[0:0] \cr_a [0] case assign $2\cr_bit[0:0] 1'0 end case assign $1\cr_bit[0:0] 1'0 end sync always update \cr_bit $0\cr_bit[0:0] end attribute \src "libresoc.v:151901.3-151915.6" process $proc$libresoc.v:151901$7562 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] attribute \src "libresoc.v:151902.5-151902.29" switch \initial attribute \src "libresoc.v:151902.9-151902.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\lut[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\lut[3:0] \cr_op__insn [9:6] case assign $1\lut[3:0] 4'0000 end sync always update \lut $0\lut[3:0] end attribute \src "libresoc.v:151916.3-151930.6" process $proc$libresoc.v:151916$7563 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] attribute \src "libresoc.v:151917.5-151917.29" switch \initial attribute \src "libresoc.v:151917.9-151917.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\bt[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bt[1:0] \$9 [1:0] case assign $1\bt[1:0] 2'00 end sync always update \bt $0\bt[1:0] end attribute \src "libresoc.v:151931.3-151945.6" process $proc$libresoc.v:151931$7564 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] attribute \src "libresoc.v:151932.5-151932.29" switch \initial attribute \src "libresoc.v:151932.9-151932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\ba[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\ba[1:0] \$12 [1:0] case assign $1\ba[1:0] 2'00 end sync always update \ba $0\ba[1:0] end attribute \src "libresoc.v:151946.3-151960.6" process $proc$libresoc.v:151946$7565 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] attribute \src "libresoc.v:151947.5-151947.29" switch \initial attribute \src "libresoc.v:151947.9-151947.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\bb[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bb[1:0] \$15 [1:0] case assign $1\bb[1:0] 2'00 end sync always update \bb $0\bb[1:0] end attribute \src "libresoc.v:151961.3-151985.6" process $proc$libresoc.v:151961$7566 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] attribute \src "libresoc.v:151962.5-151962.29" switch \initial attribute \src "libresoc.v:151962.9-151962.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\bit_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_a[0:0] $2\bit_a[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" switch \ba attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $2\bit_a[0:0] \cr_a [0] attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $2\bit_a[0:0] \cr_a [1] attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\bit_a[0:0] \cr_a [2] attribute \src "libresoc.v:0.0-0.0" case 2'-- assign { } { } assign $2\bit_a[0:0] \cr_a [3] case assign $2\bit_a[0:0] 1'0 end case assign $1\bit_a[0:0] 1'0 end sync always update \bit_a $0\bit_a[0:0] end attribute \src "libresoc.v:151986.3-152010.6" process $proc$libresoc.v:151986$7567 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] attribute \src "libresoc.v:151987.5-151987.29" switch \initial attribute \src "libresoc.v:151987.9-151987.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\bit_b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_b[0:0] $2\bit_b[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" switch \bb attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $2\bit_b[0:0] \cr_b [0] attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $2\bit_b[0:0] \cr_b [1] attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $2\bit_b[0:0] \cr_b [2] attribute \src "libresoc.v:0.0-0.0" case 2'-- assign { } { } assign $2\bit_b[0:0] \cr_b [3] case assign $2\bit_b[0:0] 1'0 end case assign $1\bit_b[0:0] 1'0 end sync always update \bit_b $0\bit_b[0:0] end attribute \src "libresoc.v:152011.3-152025.6" process $proc$libresoc.v:152011$7568 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] attribute \src "libresoc.v:152012.5-152012.29" switch \initial attribute \src "libresoc.v:152012.9-152012.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\bit_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_o[0:0] \$22 case assign $1\bit_o[0:0] 1'0 end sync always update \bit_o $0\bit_o[0:0] end attribute \src "libresoc.v:152026.3-152044.6" process $proc$libresoc.v:152026$7569 assign { } { } assign { } { } assign $0\full_cr$5[31:0]$7570 $1\full_cr$5[31:0]$7571 attribute \src "libresoc.v:152027.5-152027.29" switch \initial attribute \src "libresoc.v:152027.9-152027.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0101010 assign $1\full_cr$5[31:0]$7571 0 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign $1\full_cr$5[31:0]$7571 0 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } assign $1\full_cr$5[31:0]$7571 \ra [31:0] case assign $1\full_cr$5[31:0]$7571 0 end sync always update \full_cr$5 $0\full_cr$5[31:0]$7570 end connect \$10 $sub$libresoc.v:151719$7541_Y connect \$13 $sub$libresoc.v:151720$7542_Y connect \$16 $sub$libresoc.v:151721$7543_Y connect \$18 $ternary$libresoc.v:151722$7544_Y connect \$20 $ternary$libresoc.v:151723$7545_Y connect \$22 $ternary$libresoc.v:151724$7546_Y connect \$24 $pos$libresoc.v:151725$7548_Y connect \$27 $ternary$libresoc.v:151726$7549_Y connect \$26 $pos$libresoc.v:151727$7551_Y connect \$7 $pos$libresoc.v:151728$7553_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end attribute \src "libresoc.v:152054.1-153215.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 attribute \src "libresoc.v:152786.3-152787.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:152784.3-152785.40" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:153127.3-153135.6" wire $0\alu_l_r_alu$next[0:0]$7778 attribute \src "libresoc.v:152712.3-152713.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 attribute \src "libresoc.v:152740.3-152741.65" wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 attribute \src "libresoc.v:152742.3-152743.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 attribute \src "libresoc.v:152744.3-152745.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7706 attribute \src "libresoc.v:152760.3-152761.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 attribute \src "libresoc.v:152738.3-152739.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 attribute \src "libresoc.v:152756.3-152757.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 attribute \src "libresoc.v:152758.3-152759.69" wire $0\alu_mul0_mul_op__is_signed[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 attribute \src "libresoc.v:152750.3-152751.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 attribute \src "libresoc.v:152752.3-152753.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 attribute \src "libresoc.v:152748.3-152749.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 attribute \src "libresoc.v:152746.3-152747.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 attribute \src "libresoc.v:152754.3-152755.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] attribute \src "libresoc.v:153118.3-153126.6" wire $0\alui_l_r_alui$next[0:0]$7775 attribute \src "libresoc.v:152714.3-152715.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:153000.3-153021.6" wire width 64 $0\data_r0__o$next[63:0]$7734 attribute \src "libresoc.v:152734.3-152735.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:153000.3-153021.6" wire $0\data_r0__o_ok$next[0:0]$7735 attribute \src "libresoc.v:152736.3-152737.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:153022.3-153043.6" wire width 4 $0\data_r1__cr_a$next[3:0]$7742 attribute \src "libresoc.v:152730.3-152731.43" wire width 4 $0\data_r1__cr_a[3:0] attribute \src "libresoc.v:153022.3-153043.6" wire $0\data_r1__cr_a_ok$next[0:0]$7743 attribute \src "libresoc.v:152732.3-152733.49" wire $0\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:153044.3-153065.6" wire width 2 $0\data_r2__xer_ov$next[1:0]$7750 attribute \src "libresoc.v:152726.3-152727.47" wire width 2 $0\data_r2__xer_ov[1:0] attribute \src "libresoc.v:153044.3-153065.6" wire $0\data_r2__xer_ov_ok$next[0:0]$7751 attribute \src "libresoc.v:152728.3-152729.53" wire $0\data_r2__xer_ov_ok[0:0] attribute \src "libresoc.v:153066.3-153087.6" wire $0\data_r3__xer_so$next[0:0]$7758 attribute \src "libresoc.v:152722.3-152723.47" wire $0\data_r3__xer_so[0:0] attribute \src "libresoc.v:153066.3-153087.6" wire $0\data_r3__xer_so_ok$next[0:0]$7759 attribute \src "libresoc.v:152724.3-152725.53" wire $0\data_r3__xer_so_ok[0:0] attribute \src "libresoc.v:153136.3-153145.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:153146.3-153155.6" wire width 4 $0\dest2_o[3:0] attribute \src "libresoc.v:153156.3-153165.6" wire width 2 $0\dest3_o[1:0] attribute \src "libresoc.v:153166.3-153175.6" wire $0\dest4_o[0:0] attribute \src "libresoc.v:152055.7-152055.20" wire $0\initial[0:0] attribute \src "libresoc.v:152922.3-152930.6" wire $0\opc_l_r_opc$next[0:0]$7688 attribute \src "libresoc.v:152770.3-152771.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:152913.3-152921.6" wire $0\opc_l_s_opc$next[0:0]$7685 attribute \src "libresoc.v:152772.3-152773.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:153176.3-153184.6" wire width 4 $0\prev_wr_go$next[3:0]$7785 attribute \src "libresoc.v:152782.3-152783.37" wire width 4 $0\prev_wr_go[3:0] attribute \src "libresoc.v:152867.3-152876.6" wire $0\req_done[0:0] attribute \src "libresoc.v:152958.3-152966.6" wire width 4 $0\req_l_r_req$next[3:0]$7700 attribute \src "libresoc.v:152762.3-152763.39" wire width 4 $0\req_l_r_req[3:0] attribute \src "libresoc.v:152949.3-152957.6" wire width 4 $0\req_l_s_req$next[3:0]$7697 attribute \src "libresoc.v:152764.3-152765.39" wire width 4 $0\req_l_s_req[3:0] attribute \src "libresoc.v:152886.3-152894.6" wire $0\rok_l_r_rdok$next[0:0]$7676 attribute \src "libresoc.v:152778.3-152779.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:152877.3-152885.6" wire $0\rok_l_s_rdok$next[0:0]$7673 attribute \src "libresoc.v:152780.3-152781.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:152904.3-152912.6" wire $0\rst_l_r_rst$next[0:0]$7682 attribute \src "libresoc.v:152774.3-152775.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:152895.3-152903.6" wire $0\rst_l_s_rst$next[0:0]$7679 attribute \src "libresoc.v:152776.3-152777.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:152940.3-152948.6" wire width 3 $0\src_l_r_src$next[2:0]$7694 attribute \src "libresoc.v:152766.3-152767.39" wire width 3 $0\src_l_r_src[2:0] attribute \src "libresoc.v:152931.3-152939.6" wire width 3 $0\src_l_s_src$next[2:0]$7691 attribute \src "libresoc.v:152768.3-152769.39" wire width 3 $0\src_l_s_src[2:0] attribute \src "libresoc.v:153088.3-153097.6" wire width 64 $0\src_r0$next[63:0]$7766 attribute \src "libresoc.v:152720.3-152721.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:153098.3-153107.6" wire width 64 $0\src_r1$next[63:0]$7769 attribute \src "libresoc.v:152718.3-152719.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:153108.3-153117.6" wire $0\src_r2$next[0:0]$7772 attribute \src "libresoc.v:152716.3-152717.29" wire $0\src_r2[0:0] attribute \src "libresoc.v:152179.7-152179.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:152189.7-152189.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:153127.3-153135.6" wire $1\alu_l_r_alu$next[0:0]$7779 attribute \src "libresoc.v:152197.7-152197.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 attribute \src "libresoc.v:152220.14-152220.49" wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 attribute \src "libresoc.v:152224.14-152224.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 attribute \src "libresoc.v:152228.7-152228.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7718 attribute \src "libresoc.v:152232.14-152232.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 attribute \src "libresoc.v:152311.13-152311.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 attribute \src "libresoc.v:152315.7-152315.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 attribute \src "libresoc.v:152319.7-152319.40" wire $1\alu_mul0_mul_op__is_signed[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 attribute \src "libresoc.v:152323.7-152323.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 attribute \src "libresoc.v:152327.7-152327.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 attribute \src "libresoc.v:152331.7-152331.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 attribute \src "libresoc.v:152335.7-152335.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 attribute \src "libresoc.v:152339.7-152339.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] attribute \src "libresoc.v:153118.3-153126.6" wire $1\alui_l_r_alui$next[0:0]$7776 attribute \src "libresoc.v:152369.7-152369.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:153000.3-153021.6" wire width 64 $1\data_r0__o$next[63:0]$7736 attribute \src "libresoc.v:152403.14-152403.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:153000.3-153021.6" wire $1\data_r0__o_ok$next[0:0]$7737 attribute \src "libresoc.v:152407.7-152407.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:153022.3-153043.6" wire width 4 $1\data_r1__cr_a$next[3:0]$7744 attribute \src "libresoc.v:152411.13-152411.33" wire width 4 $1\data_r1__cr_a[3:0] attribute \src "libresoc.v:153022.3-153043.6" wire $1\data_r1__cr_a_ok$next[0:0]$7745 attribute \src "libresoc.v:152415.7-152415.30" wire $1\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:153044.3-153065.6" wire width 2 $1\data_r2__xer_ov$next[1:0]$7752 attribute \src "libresoc.v:152419.13-152419.35" wire width 2 $1\data_r2__xer_ov[1:0] attribute \src "libresoc.v:153044.3-153065.6" wire $1\data_r2__xer_ov_ok$next[0:0]$7753 attribute \src "libresoc.v:152423.7-152423.32" wire $1\data_r2__xer_ov_ok[0:0] attribute \src "libresoc.v:153066.3-153087.6" wire $1\data_r3__xer_so$next[0:0]$7760 attribute \src "libresoc.v:152427.7-152427.29" wire $1\data_r3__xer_so[0:0] attribute \src "libresoc.v:153066.3-153087.6" wire $1\data_r3__xer_so_ok$next[0:0]$7761 attribute \src "libresoc.v:152431.7-152431.32" wire $1\data_r3__xer_so_ok[0:0] attribute \src "libresoc.v:153136.3-153145.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:153146.3-153155.6" wire width 4 $1\dest2_o[3:0] attribute \src "libresoc.v:153156.3-153165.6" wire width 2 $1\dest3_o[1:0] attribute \src "libresoc.v:153166.3-153175.6" wire $1\dest4_o[0:0] attribute \src "libresoc.v:152922.3-152930.6" wire $1\opc_l_r_opc$next[0:0]$7689 attribute \src "libresoc.v:152451.7-152451.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:152913.3-152921.6" wire $1\opc_l_s_opc$next[0:0]$7686 attribute \src "libresoc.v:152455.7-152455.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:153176.3-153184.6" wire width 4 $1\prev_wr_go$next[3:0]$7786 attribute \src "libresoc.v:152573.13-152573.30" wire width 4 $1\prev_wr_go[3:0] attribute \src "libresoc.v:152867.3-152876.6" wire $1\req_done[0:0] attribute \src "libresoc.v:152958.3-152966.6" wire width 4 $1\req_l_r_req$next[3:0]$7701 attribute \src "libresoc.v:152581.13-152581.31" wire width 4 $1\req_l_r_req[3:0] attribute \src "libresoc.v:152949.3-152957.6" wire width 4 $1\req_l_s_req$next[3:0]$7698 attribute \src "libresoc.v:152585.13-152585.31" wire width 4 $1\req_l_s_req[3:0] attribute \src "libresoc.v:152886.3-152894.6" wire $1\rok_l_r_rdok$next[0:0]$7677 attribute \src "libresoc.v:152597.7-152597.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:152877.3-152885.6" wire $1\rok_l_s_rdok$next[0:0]$7674 attribute \src "libresoc.v:152601.7-152601.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:152904.3-152912.6" wire $1\rst_l_r_rst$next[0:0]$7683 attribute \src "libresoc.v:152605.7-152605.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:152895.3-152903.6" wire $1\rst_l_s_rst$next[0:0]$7680 attribute \src "libresoc.v:152609.7-152609.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:152940.3-152948.6" wire width 3 $1\src_l_r_src$next[2:0]$7695 attribute \src "libresoc.v:152623.13-152623.31" wire width 3 $1\src_l_r_src[2:0] attribute \src "libresoc.v:152931.3-152939.6" wire width 3 $1\src_l_s_src$next[2:0]$7692 attribute \src "libresoc.v:152627.13-152627.31" wire width 3 $1\src_l_s_src[2:0] attribute \src "libresoc.v:153088.3-153097.6" wire width 64 $1\src_r0$next[63:0]$7767 attribute \src "libresoc.v:152633.14-152633.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:153098.3-153107.6" wire width 64 $1\src_r1$next[63:0]$7770 attribute \src "libresoc.v:152637.14-152637.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:153108.3-153117.6" wire $1\src_r2$next[0:0]$7773 attribute \src "libresoc.v:152641.7-152641.20" wire $1\src_r2[0:0] attribute \src "libresoc.v:152967.3-152999.6" wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 attribute \src "libresoc.v:152967.3-152999.6" wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 attribute \src "libresoc.v:153000.3-153021.6" wire width 64 $2\data_r0__o$next[63:0]$7738 attribute \src "libresoc.v:153000.3-153021.6" wire $2\data_r0__o_ok$next[0:0]$7739 attribute \src "libresoc.v:153022.3-153043.6" wire width 4 $2\data_r1__cr_a$next[3:0]$7746 attribute \src "libresoc.v:153022.3-153043.6" wire $2\data_r1__cr_a_ok$next[0:0]$7747 attribute \src "libresoc.v:153044.3-153065.6" wire width 2 $2\data_r2__xer_ov$next[1:0]$7754 attribute \src "libresoc.v:153044.3-153065.6" wire $2\data_r2__xer_ov_ok$next[0:0]$7755 attribute \src "libresoc.v:153066.3-153087.6" wire $2\data_r3__xer_so$next[0:0]$7762 attribute \src "libresoc.v:153066.3-153087.6" wire $2\data_r3__xer_so_ok$next[0:0]$7763 attribute \src "libresoc.v:153000.3-153021.6" wire $3\data_r0__o_ok$next[0:0]$7740 attribute \src "libresoc.v:153022.3-153043.6" wire $3\data_r1__cr_a_ok$next[0:0]$7748 attribute \src "libresoc.v:153044.3-153065.6" wire $3\data_r2__xer_ov_ok$next[0:0]$7756 attribute \src "libresoc.v:153066.3-153087.6" wire $3\data_r3__xer_so_ok$next[0:0]$7764 attribute \src "libresoc.v:152652.19-152652.113" wire width 3 $and$libresoc.v:152652$7573_Y attribute \src "libresoc.v:152653.19-152653.125" wire $and$libresoc.v:152653$7574_Y attribute \src "libresoc.v:152654.19-152654.125" wire $and$libresoc.v:152654$7575_Y attribute \src "libresoc.v:152655.19-152655.125" wire $and$libresoc.v:152655$7576_Y attribute \src "libresoc.v:152656.19-152656.125" wire $and$libresoc.v:152656$7577_Y attribute \src "libresoc.v:152657.18-152657.110" wire $and$libresoc.v:152657$7578_Y attribute \src "libresoc.v:152658.19-152658.149" wire width 4 $and$libresoc.v:152658$7579_Y attribute \src "libresoc.v:152659.19-152659.121" wire width 4 $and$libresoc.v:152659$7580_Y attribute \src "libresoc.v:152660.19-152660.127" wire $and$libresoc.v:152660$7581_Y attribute \src "libresoc.v:152661.19-152661.127" wire $and$libresoc.v:152661$7582_Y attribute \src "libresoc.v:152662.19-152662.127" wire $and$libresoc.v:152662$7583_Y attribute \src "libresoc.v:152663.19-152663.127" wire $and$libresoc.v:152663$7584_Y attribute \src "libresoc.v:152665.18-152665.98" wire $and$libresoc.v:152665$7586_Y attribute \src "libresoc.v:152667.18-152667.100" wire $and$libresoc.v:152667$7588_Y attribute \src "libresoc.v:152668.18-152668.160" wire width 4 $and$libresoc.v:152668$7589_Y attribute \src "libresoc.v:152670.18-152670.119" wire width 4 $and$libresoc.v:152670$7591_Y attribute \src "libresoc.v:152673.17-152673.123" wire $and$libresoc.v:152673$7594_Y attribute \src "libresoc.v:152674.18-152674.116" wire $and$libresoc.v:152674$7595_Y attribute \src "libresoc.v:152679.18-152679.113" wire $and$libresoc.v:152679$7600_Y attribute \src "libresoc.v:152680.18-152680.125" wire width 4 $and$libresoc.v:152680$7601_Y attribute \src "libresoc.v:152682.18-152682.112" wire $and$libresoc.v:152682$7603_Y attribute \src "libresoc.v:152684.18-152684.126" wire $and$libresoc.v:152684$7605_Y attribute \src "libresoc.v:152685.18-152685.126" wire $and$libresoc.v:152685$7606_Y attribute \src "libresoc.v:152686.18-152686.117" wire $and$libresoc.v:152686$7607_Y attribute \src "libresoc.v:152692.18-152692.130" wire $and$libresoc.v:152692$7613_Y attribute \src "libresoc.v:152693.18-152693.124" wire width 4 $and$libresoc.v:152693$7614_Y attribute \src "libresoc.v:152695.18-152695.116" wire $and$libresoc.v:152695$7616_Y attribute \src "libresoc.v:152696.18-152696.119" wire $and$libresoc.v:152696$7617_Y attribute \src "libresoc.v:152697.18-152697.121" wire $and$libresoc.v:152697$7618_Y attribute \src "libresoc.v:152698.18-152698.121" wire $and$libresoc.v:152698$7619_Y attribute \src "libresoc.v:152705.18-152705.134" wire $and$libresoc.v:152705$7626_Y attribute \src "libresoc.v:152707.18-152707.132" wire $and$libresoc.v:152707$7628_Y attribute \src "libresoc.v:152708.18-152708.149" wire width 3 $and$libresoc.v:152708$7629_Y attribute \src "libresoc.v:152710.18-152710.129" wire width 3 $and$libresoc.v:152710$7631_Y attribute \src "libresoc.v:152681.18-152681.113" wire $eq$libresoc.v:152681$7602_Y attribute \src "libresoc.v:152683.18-152683.119" wire $eq$libresoc.v:152683$7604_Y attribute \src "libresoc.v:152664.18-152664.97" wire $not$libresoc.v:152664$7585_Y attribute \src "libresoc.v:152666.18-152666.99" wire $not$libresoc.v:152666$7587_Y attribute \src "libresoc.v:152669.18-152669.113" wire width 4 $not$libresoc.v:152669$7590_Y attribute \src "libresoc.v:152672.18-152672.106" wire $not$libresoc.v:152672$7593_Y attribute \src "libresoc.v:152678.18-152678.120" wire $not$libresoc.v:152678$7599_Y attribute \src "libresoc.v:152689.17-152689.113" wire width 3 $not$libresoc.v:152689$7610_Y attribute \src "libresoc.v:152709.18-152709.131" wire $not$libresoc.v:152709$7630_Y attribute \src "libresoc.v:152711.18-152711.114" wire width 3 $not$libresoc.v:152711$7632_Y attribute \src "libresoc.v:152677.18-152677.112" wire $or$libresoc.v:152677$7598_Y attribute \src "libresoc.v:152687.18-152687.122" wire $or$libresoc.v:152687$7608_Y attribute \src "libresoc.v:152688.18-152688.124" wire $or$libresoc.v:152688$7609_Y attribute \src "libresoc.v:152690.18-152690.168" wire width 4 $or$libresoc.v:152690$7611_Y attribute \src "libresoc.v:152691.18-152691.155" wire width 3 $or$libresoc.v:152691$7612_Y attribute \src "libresoc.v:152694.18-152694.120" wire width 4 $or$libresoc.v:152694$7615_Y attribute \src "libresoc.v:152700.17-152700.117" wire width 3 $or$libresoc.v:152700$7621_Y attribute \src "libresoc.v:152706.17-152706.104" wire $reduce_and$libresoc.v:152706$7627_Y attribute \src "libresoc.v:152671.18-152671.106" wire $reduce_or$libresoc.v:152671$7592_Y attribute \src "libresoc.v:152675.18-152675.113" wire $reduce_or$libresoc.v:152675$7596_Y attribute \src "libresoc.v:152676.18-152676.112" wire $reduce_or$libresoc.v:152676$7597_Y attribute \src "libresoc.v:152699.18-152699.160" wire $ternary$libresoc.v:152699$7620_Y attribute \src "libresoc.v:152701.18-152701.172" wire width 64 $ternary$libresoc.v:152701$7622_Y attribute \src "libresoc.v:152702.18-152702.118" wire width 64 $ternary$libresoc.v:152702$7623_Y attribute \src "libresoc.v:152703.18-152703.115" wire width 64 $ternary$libresoc.v:152703$7624_Y attribute \src "libresoc.v:152704.18-152704.118" wire $ternary$libresoc.v:152704$7625_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 4 \$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 4 \$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$118 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 4 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 4 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 4 \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 4 \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 4 \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 3 \$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 4 \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 4 \$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 3 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_mul0_cr_a attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_mul0_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_mul0_mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_mul0_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_mul0_mul_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_mul0_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_mul0_mul_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_mul0_mul_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_mul0_mul_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_mul0_mul_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_mul0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_mul0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_mul0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_mul0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_mul0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_mul0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_mul0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_mul0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_mul0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_mul0_xer_so$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 4 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 32 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 15 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 14 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 18 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 17 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 3 input 16 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 24 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 23 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 4 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ov$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 25 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 27 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o attribute \src "libresoc.v:152055.7-152055.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 13 \oper_i_alu_mul0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \oper_i_alu_mul0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \oper_i_alu_mul0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \oper_i_alu_mul0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 4 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 4 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 4 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 20 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 19 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 21 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:152652$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 connect \Y $and$libresoc.v:152652$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:152653$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:152653$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:152654$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:152654$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:152655$7576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:152655$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:152656$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:152656$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:152657$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 connect \Y $and$libresoc.v:152657$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:152658$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } connect \Y $and$libresoc.v:152658$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:152659$7580 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:152659$7580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:152660$7581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:152660$7581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:152661$7582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:152661$7582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:152662$7583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:152662$7583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:152663$7584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o connect \Y $and$libresoc.v:152663$7584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:152665$7586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 connect \Y $and$libresoc.v:152665$7586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:152667$7588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 connect \Y $and$libresoc.v:152667$7588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:152668$7589 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:152668$7589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:152670$7591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 connect \Y $and$libresoc.v:152670$7591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:152673$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:152673$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:152674$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 connect \Y $and$libresoc.v:152674$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:152679$7600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 connect \Y $and$libresoc.v:152679$7600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:152680$7601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:152680$7601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:152682$7603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 connect \Y $and$libresoc.v:152682$7603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:152684$7605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i connect \Y $and$libresoc.v:152684$7605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:152685$7606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o connect \Y $and$libresoc.v:152685$7606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:152686$7607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o connect \Y $and$libresoc.v:152686$7607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:152692$7613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:152692$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:152693$7614 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:152693$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:152695$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:152695$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:152696$7617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:152696$7617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:152697$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:152697$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:152698$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:152698$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:152705$7626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:152705$7626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:152707$7628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:152707$7628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:152708$7629 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:152708$7629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:152710$7631 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } connect \Y $and$libresoc.v:152710$7631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:152681$7602 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 connect \Y $eq$libresoc.v:152681$7602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:152683$7604 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:152683$7604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:152664$7585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:152664$7585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:152666$7587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:152666$7587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:152669$7590 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:152669$7590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:152672$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 connect \Y $not$libresoc.v:152672$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:152678$7599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i connect \Y $not$libresoc.v:152678$7599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:152689$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:152689$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:152709$7630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok connect \Y $not$libresoc.v:152709$7630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:152711$7632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:152711$7632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:152677$7598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 connect \Y $or$libresoc.v:152677$7598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:152687$7608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:152687$7608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:152688$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:152688$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:152690$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:152690$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:152691$7612 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:152691$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:152694$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:152694$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:152700$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:152700$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:152706$7627 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 connect \Y $reduce_and$libresoc.v:152706$7627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:152671$7592 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 connect \Y $reduce_or$libresoc.v:152671$7592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:152675$7596 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:152675$7596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:152676$7597 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:152676$7597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:152699$7620 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok connect \Y $ternary$libresoc.v:152699$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:152701$7622 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok connect \Y $ternary$libresoc.v:152701$7622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:152702$7623 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] connect \Y $ternary$libresoc.v:152702$7623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:152703$7624 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel connect \Y $ternary$libresoc.v:152703$7624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:152704$7625 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:152704$7625_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:152788.15-152794.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:152795.12-152825.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \alu_mul0_cr_a connect \cr_a_ok \cr_a_ok connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok connect \mul_op__insn \alu_mul0_mul_op__insn connect \mul_op__insn_type \alu_mul0_mul_op__insn_type connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit connect \mul_op__is_signed \alu_mul0_mul_op__is_signed connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 connect \n_ready_i \alu_mul0_n_ready_i connect \n_valid_o \alu_mul0_n_valid_o connect \o \alu_mul0_o connect \o_ok \o_ok connect \p_ready_o \alu_mul0_p_ready_o connect \p_valid_i \alu_mul0_p_valid_i connect \ra \alu_mul0_ra connect \rb \alu_mul0_rb connect \xer_ov \alu_mul0_xer_ov connect \xer_ov_ok \xer_ov_ok connect \xer_so \alu_mul0_xer_so connect \xer_so$1 \alu_mul0_xer_so$1 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:152826.16-152832.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:152833.15-152839.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:152840.15-152846.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:152847.15-152853.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:152854.15-152859.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:152860.15-152866.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:152055.7-152055.20" process $proc$libresoc.v:152055$7787 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:152179.7-152179.24" process $proc$libresoc.v:152179$7788 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:152189.7-152189.26" process $proc$libresoc.v:152189$7789 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:152197.7-152197.25" process $proc$libresoc.v:152197$7790 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:152220.14-152220.49" process $proc$libresoc.v:152220$7791 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end attribute \src "libresoc.v:152224.14-152224.68" process $proc$libresoc.v:152224$7792 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end attribute \src "libresoc.v:152228.7-152228.43" process $proc$libresoc.v:152228$7793 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end attribute \src "libresoc.v:152232.14-152232.43" process $proc$libresoc.v:152232$7794 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end attribute \src "libresoc.v:152311.13-152311.47" process $proc$libresoc.v:152311$7795 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end attribute \src "libresoc.v:152315.7-152315.39" process $proc$libresoc.v:152315$7796 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end attribute \src "libresoc.v:152319.7-152319.40" process $proc$libresoc.v:152319$7797 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end attribute \src "libresoc.v:152323.7-152323.37" process $proc$libresoc.v:152323$7798 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end attribute \src "libresoc.v:152327.7-152327.37" process $proc$libresoc.v:152327$7799 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end attribute \src "libresoc.v:152331.7-152331.37" process $proc$libresoc.v:152331$7800 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end attribute \src "libresoc.v:152335.7-152335.37" process $proc$libresoc.v:152335$7801 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end attribute \src "libresoc.v:152339.7-152339.40" process $proc$libresoc.v:152339$7802 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end attribute \src "libresoc.v:152369.7-152369.27" process $proc$libresoc.v:152369$7803 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:152403.14-152403.47" process $proc$libresoc.v:152403$7804 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:152407.7-152407.27" process $proc$libresoc.v:152407$7805 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:152411.13-152411.33" process $proc$libresoc.v:152411$7806 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end attribute \src "libresoc.v:152415.7-152415.30" process $proc$libresoc.v:152415$7807 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:152419.13-152419.35" process $proc$libresoc.v:152419$7808 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end attribute \src "libresoc.v:152423.7-152423.32" process $proc$libresoc.v:152423$7809 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end attribute \src "libresoc.v:152427.7-152427.29" process $proc$libresoc.v:152427$7810 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end attribute \src "libresoc.v:152431.7-152431.32" process $proc$libresoc.v:152431$7811 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end attribute \src "libresoc.v:152451.7-152451.25" process $proc$libresoc.v:152451$7812 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:152455.7-152455.25" process $proc$libresoc.v:152455$7813 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:152573.13-152573.30" process $proc$libresoc.v:152573$7814 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end attribute \src "libresoc.v:152581.13-152581.31" process $proc$libresoc.v:152581$7815 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end attribute \src "libresoc.v:152585.13-152585.31" process $proc$libresoc.v:152585$7816 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end attribute \src "libresoc.v:152597.7-152597.26" process $proc$libresoc.v:152597$7817 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:152601.7-152601.26" process $proc$libresoc.v:152601$7818 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:152605.7-152605.25" process $proc$libresoc.v:152605$7819 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:152609.7-152609.25" process $proc$libresoc.v:152609$7820 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:152623.13-152623.31" process $proc$libresoc.v:152623$7821 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end attribute \src "libresoc.v:152627.13-152627.31" process $proc$libresoc.v:152627$7822 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end attribute \src "libresoc.v:152633.14-152633.43" process $proc$libresoc.v:152633$7823 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:152637.14-152637.43" process $proc$libresoc.v:152637$7824 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:152641.7-152641.20" process $proc$libresoc.v:152641$7825 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end attribute \src "libresoc.v:152712.3-152713.39" process $proc$libresoc.v:152712$7633 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:152714.3-152715.43" process $proc$libresoc.v:152714$7634 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:152716.3-152717.29" process $proc$libresoc.v:152716$7635 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end attribute \src "libresoc.v:152718.3-152719.29" process $proc$libresoc.v:152718$7636 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:152720.3-152721.29" process $proc$libresoc.v:152720$7637 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:152722.3-152723.47" process $proc$libresoc.v:152722$7638 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end attribute \src "libresoc.v:152724.3-152725.53" process $proc$libresoc.v:152724$7639 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end attribute \src "libresoc.v:152726.3-152727.47" process $proc$libresoc.v:152726$7640 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end attribute \src "libresoc.v:152728.3-152729.53" process $proc$libresoc.v:152728$7641 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end attribute \src "libresoc.v:152730.3-152731.43" process $proc$libresoc.v:152730$7642 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end attribute \src "libresoc.v:152732.3-152733.49" process $proc$libresoc.v:152732$7643 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:152734.3-152735.37" process $proc$libresoc.v:152734$7644 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:152736.3-152737.43" process $proc$libresoc.v:152736$7645 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:152738.3-152739.69" process $proc$libresoc.v:152738$7646 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end attribute \src "libresoc.v:152740.3-152741.65" process $proc$libresoc.v:152740$7647 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end attribute \src "libresoc.v:152742.3-152743.79" process $proc$libresoc.v:152742$7648 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end attribute \src "libresoc.v:152744.3-152745.75" process $proc$libresoc.v:152744$7649 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end attribute \src "libresoc.v:152746.3-152747.63" process $proc$libresoc.v:152746$7650 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end attribute \src "libresoc.v:152748.3-152749.63" process $proc$libresoc.v:152748$7651 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end attribute \src "libresoc.v:152750.3-152751.63" process $proc$libresoc.v:152750$7652 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end attribute \src "libresoc.v:152752.3-152753.63" process $proc$libresoc.v:152752$7653 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end attribute \src "libresoc.v:152754.3-152755.69" process $proc$libresoc.v:152754$7654 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end attribute \src "libresoc.v:152756.3-152757.67" process $proc$libresoc.v:152756$7655 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end attribute \src "libresoc.v:152758.3-152759.69" process $proc$libresoc.v:152758$7656 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end attribute \src "libresoc.v:152760.3-152761.59" process $proc$libresoc.v:152760$7657 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end attribute \src "libresoc.v:152762.3-152763.39" process $proc$libresoc.v:152762$7658 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end attribute \src "libresoc.v:152764.3-152765.39" process $proc$libresoc.v:152764$7659 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end attribute \src "libresoc.v:152766.3-152767.39" process $proc$libresoc.v:152766$7660 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end attribute \src "libresoc.v:152768.3-152769.39" process $proc$libresoc.v:152768$7661 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end attribute \src "libresoc.v:152770.3-152771.39" process $proc$libresoc.v:152770$7662 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:152772.3-152773.39" process $proc$libresoc.v:152772$7663 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:152774.3-152775.39" process $proc$libresoc.v:152774$7664 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:152776.3-152777.39" process $proc$libresoc.v:152776$7665 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:152778.3-152779.41" process $proc$libresoc.v:152778$7666 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:152780.3-152781.41" process $proc$libresoc.v:152780$7667 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:152782.3-152783.37" process $proc$libresoc.v:152782$7668 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end attribute \src "libresoc.v:152784.3-152785.40" process $proc$libresoc.v:152784$7669 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:152786.3-152787.25" process $proc$libresoc.v:152786$7670 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:152867.3-152876.6" process $proc$libresoc.v:152867$7671 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:152868.5-152868.29" switch \initial attribute \src "libresoc.v:152868.9-152868.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$46 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:152877.3-152885.6" process $proc$libresoc.v:152877$7672 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$7673 $1\rok_l_s_rdok$next[0:0]$7674 attribute \src "libresoc.v:152878.5-152878.29" switch \initial attribute \src "libresoc.v:152878.9-152878.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$7674 1'0 case assign $1\rok_l_s_rdok$next[0:0]$7674 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7673 end attribute \src "libresoc.v:152886.3-152894.6" process $proc$libresoc.v:152886$7675 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$7676 $1\rok_l_r_rdok$next[0:0]$7677 attribute \src "libresoc.v:152887.5-152887.29" switch \initial attribute \src "libresoc.v:152887.9-152887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$7677 1'1 case assign $1\rok_l_r_rdok$next[0:0]$7677 \$64 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7676 end attribute \src "libresoc.v:152895.3-152903.6" process $proc$libresoc.v:152895$7678 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$7679 $1\rst_l_s_rst$next[0:0]$7680 attribute \src "libresoc.v:152896.5-152896.29" switch \initial attribute \src "libresoc.v:152896.9-152896.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$7680 1'0 case assign $1\rst_l_s_rst$next[0:0]$7680 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7679 end attribute \src "libresoc.v:152904.3-152912.6" process $proc$libresoc.v:152904$7681 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$7682 $1\rst_l_r_rst$next[0:0]$7683 attribute \src "libresoc.v:152905.5-152905.29" switch \initial attribute \src "libresoc.v:152905.9-152905.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$7683 1'1 case assign $1\rst_l_r_rst$next[0:0]$7683 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7682 end attribute \src "libresoc.v:152913.3-152921.6" process $proc$libresoc.v:152913$7684 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$7685 $1\opc_l_s_opc$next[0:0]$7686 attribute \src "libresoc.v:152914.5-152914.29" switch \initial attribute \src "libresoc.v:152914.9-152914.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$7686 1'0 case assign $1\opc_l_s_opc$next[0:0]$7686 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7685 end attribute \src "libresoc.v:152922.3-152930.6" process $proc$libresoc.v:152922$7687 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$7688 $1\opc_l_r_opc$next[0:0]$7689 attribute \src "libresoc.v:152923.5-152923.29" switch \initial attribute \src "libresoc.v:152923.9-152923.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$7689 1'1 case assign $1\opc_l_r_opc$next[0:0]$7689 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7688 end attribute \src "libresoc.v:152931.3-152939.6" process $proc$libresoc.v:152931$7690 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$7691 $1\src_l_s_src$next[2:0]$7692 attribute \src "libresoc.v:152932.5-152932.29" switch \initial attribute \src "libresoc.v:152932.9-152932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[2:0]$7692 3'000 case assign $1\src_l_s_src$next[2:0]$7692 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7691 end attribute \src "libresoc.v:152940.3-152948.6" process $proc$libresoc.v:152940$7693 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$7694 $1\src_l_r_src$next[2:0]$7695 attribute \src "libresoc.v:152941.5-152941.29" switch \initial attribute \src "libresoc.v:152941.9-152941.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[2:0]$7695 3'111 case assign $1\src_l_r_src$next[2:0]$7695 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7694 end attribute \src "libresoc.v:152949.3-152957.6" process $proc$libresoc.v:152949$7696 assign { } { } assign { } { } assign $0\req_l_s_req$next[3:0]$7697 $1\req_l_s_req$next[3:0]$7698 attribute \src "libresoc.v:152950.5-152950.29" switch \initial attribute \src "libresoc.v:152950.9-152950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[3:0]$7698 4'0000 case assign $1\req_l_s_req$next[3:0]$7698 \$66 end sync always update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7697 end attribute \src "libresoc.v:152958.3-152966.6" process $proc$libresoc.v:152958$7699 assign { } { } assign { } { } assign $0\req_l_r_req$next[3:0]$7700 $1\req_l_r_req$next[3:0]$7701 attribute \src "libresoc.v:152959.5-152959.29" switch \initial attribute \src "libresoc.v:152959.9-152959.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[3:0]$7701 4'1111 case assign $1\req_l_r_req$next[3:0]$7701 \$68 end sync always update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7700 end attribute \src "libresoc.v:152967.3-152999.6" process $proc$libresoc.v:152967$7702 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 assign { } { } assign { } { } assign $0\alu_mul0_mul_op__insn$next[31:0]$7706 $1\alu_mul0_mul_op__insn$next[31:0]$7718 assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 attribute \src "libresoc.v:152968.5-152968.29" switch \initial attribute \src "libresoc.v:152968.9-152968.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_mul0_mul_op__insn$next[31:0]$7718 $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7715 \alu_mul0_mul_op__fn_unit assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 \alu_mul0_mul_op__imm_data__data assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 \alu_mul0_mul_op__imm_data__ok assign $1\alu_mul0_mul_op__insn$next[31:0]$7718 \alu_mul0_mul_op__insn assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7719 \alu_mul0_mul_op__insn_type assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7720 \alu_mul0_mul_op__is_32bit assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7721 \alu_mul0_mul_op__is_signed assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 \alu_mul0_mul_op__oe__oe assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 \alu_mul0_mul_op__oe__ok assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 \alu_mul0_mul_op__rc__ok assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 \alu_mul0_mul_op__rc__rc assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7726 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 1'0 assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 1'0 assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 1'0 assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 1'0 assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 1'0 case assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7727 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7716 assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7728 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7717 assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7729 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7722 assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7730 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7723 assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7731 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7724 assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7732 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7725 end sync always update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7703 update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7704 update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7705 update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7706 update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7707 update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7708 update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7709 update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7710 update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7711 update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7712 update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7713 update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7714 end attribute \src "libresoc.v:153000.3-153021.6" process $proc$libresoc.v:153000$7733 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$7734 $2\data_r0__o$next[63:0]$7738 assign { } { } assign $0\data_r0__o_ok$next[0:0]$7735 $3\data_r0__o_ok$next[0:0]$7740 attribute \src "libresoc.v:153001.5-153001.29" switch \initial attribute \src "libresoc.v:153001.9-153001.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$7737 $1\data_r0__o$next[63:0]$7736 } { \o_ok \alu_mul0_o } case assign $1\data_r0__o$next[63:0]$7736 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$7737 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$7739 $2\data_r0__o$next[63:0]$7738 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$7738 $1\data_r0__o$next[63:0]$7736 assign $2\data_r0__o_ok$next[0:0]$7739 $1\data_r0__o_ok$next[0:0]$7737 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$7740 1'0 case assign $3\data_r0__o_ok$next[0:0]$7740 $2\data_r0__o_ok$next[0:0]$7739 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$7734 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7735 end attribute \src "libresoc.v:153022.3-153043.6" process $proc$libresoc.v:153022$7741 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__cr_a$next[3:0]$7742 $2\data_r1__cr_a$next[3:0]$7746 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$7743 $3\data_r1__cr_a_ok$next[0:0]$7748 attribute \src "libresoc.v:153023.5-153023.29" switch \initial attribute \src "libresoc.v:153023.9-153023.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__cr_a_ok$next[0:0]$7745 $1\data_r1__cr_a$next[3:0]$7744 } { \cr_a_ok \alu_mul0_cr_a } case assign $1\data_r1__cr_a$next[3:0]$7744 \data_r1__cr_a assign $1\data_r1__cr_a_ok$next[0:0]$7745 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__cr_a_ok$next[0:0]$7747 $2\data_r1__cr_a$next[3:0]$7746 } 5'00000 case assign $2\data_r1__cr_a$next[3:0]$7746 $1\data_r1__cr_a$next[3:0]$7744 assign $2\data_r1__cr_a_ok$next[0:0]$7747 $1\data_r1__cr_a_ok$next[0:0]$7745 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__cr_a_ok$next[0:0]$7748 1'0 case assign $3\data_r1__cr_a_ok$next[0:0]$7748 $2\data_r1__cr_a_ok$next[0:0]$7747 end sync always update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7742 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7743 end attribute \src "libresoc.v:153044.3-153065.6" process $proc$libresoc.v:153044$7749 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__xer_ov$next[1:0]$7750 $2\data_r2__xer_ov$next[1:0]$7754 assign { } { } assign $0\data_r2__xer_ov_ok$next[0:0]$7751 $3\data_r2__xer_ov_ok$next[0:0]$7756 attribute \src "libresoc.v:153045.5-153045.29" switch \initial attribute \src "libresoc.v:153045.9-153045.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__xer_ov_ok$next[0:0]$7753 $1\data_r2__xer_ov$next[1:0]$7752 } { \xer_ov_ok \alu_mul0_xer_ov } case assign $1\data_r2__xer_ov$next[1:0]$7752 \data_r2__xer_ov assign $1\data_r2__xer_ov_ok$next[0:0]$7753 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__xer_ov_ok$next[0:0]$7755 $2\data_r2__xer_ov$next[1:0]$7754 } 3'000 case assign $2\data_r2__xer_ov$next[1:0]$7754 $1\data_r2__xer_ov$next[1:0]$7752 assign $2\data_r2__xer_ov_ok$next[0:0]$7755 $1\data_r2__xer_ov_ok$next[0:0]$7753 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__xer_ov_ok$next[0:0]$7756 1'0 case assign $3\data_r2__xer_ov_ok$next[0:0]$7756 $2\data_r2__xer_ov_ok$next[0:0]$7755 end sync always update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7750 update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7751 end attribute \src "libresoc.v:153066.3-153087.6" process $proc$libresoc.v:153066$7757 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r3__xer_so$next[0:0]$7758 $2\data_r3__xer_so$next[0:0]$7762 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$7759 $3\data_r3__xer_so_ok$next[0:0]$7764 attribute \src "libresoc.v:153067.5-153067.29" switch \initial attribute \src "libresoc.v:153067.9-153067.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r3__xer_so_ok$next[0:0]$7761 $1\data_r3__xer_so$next[0:0]$7760 } { \xer_so_ok \alu_mul0_xer_so } case assign $1\data_r3__xer_so$next[0:0]$7760 \data_r3__xer_so assign $1\data_r3__xer_so_ok$next[0:0]$7761 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r3__xer_so_ok$next[0:0]$7763 $2\data_r3__xer_so$next[0:0]$7762 } 2'00 case assign $2\data_r3__xer_so$next[0:0]$7762 $1\data_r3__xer_so$next[0:0]$7760 assign $2\data_r3__xer_so_ok$next[0:0]$7763 $1\data_r3__xer_so_ok$next[0:0]$7761 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r3__xer_so_ok$next[0:0]$7764 1'0 case assign $3\data_r3__xer_so_ok$next[0:0]$7764 $2\data_r3__xer_so_ok$next[0:0]$7763 end sync always update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7758 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7759 end attribute \src "libresoc.v:153088.3-153097.6" process $proc$libresoc.v:153088$7765 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$7766 $1\src_r0$next[63:0]$7767 attribute \src "libresoc.v:153089.5-153089.29" switch \initial attribute \src "libresoc.v:153089.9-153089.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$7767 \src1_i case assign $1\src_r0$next[63:0]$7767 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$7766 end attribute \src "libresoc.v:153098.3-153107.6" process $proc$libresoc.v:153098$7768 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$7769 $1\src_r1$next[63:0]$7770 attribute \src "libresoc.v:153099.5-153099.29" switch \initial attribute \src "libresoc.v:153099.9-153099.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$7770 \src_or_imm case assign $1\src_r1$next[63:0]$7770 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$7769 end attribute \src "libresoc.v:153108.3-153117.6" process $proc$libresoc.v:153108$7771 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$7772 $1\src_r2$next[0:0]$7773 attribute \src "libresoc.v:153109.5-153109.29" switch \initial attribute \src "libresoc.v:153109.9-153109.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[0:0]$7773 \src3_i case assign $1\src_r2$next[0:0]$7773 \src_r2 end sync always update \src_r2$next $0\src_r2$next[0:0]$7772 end attribute \src "libresoc.v:153118.3-153126.6" process $proc$libresoc.v:153118$7774 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$7775 $1\alui_l_r_alui$next[0:0]$7776 attribute \src "libresoc.v:153119.5-153119.29" switch \initial attribute \src "libresoc.v:153119.9-153119.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$7776 1'1 case assign $1\alui_l_r_alui$next[0:0]$7776 \$88 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7775 end attribute \src "libresoc.v:153127.3-153135.6" process $proc$libresoc.v:153127$7777 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$7778 $1\alu_l_r_alu$next[0:0]$7779 attribute \src "libresoc.v:153128.5-153128.29" switch \initial attribute \src "libresoc.v:153128.9-153128.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$7779 1'1 case assign $1\alu_l_r_alu$next[0:0]$7779 \$90 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7778 end attribute \src "libresoc.v:153136.3-153145.6" process $proc$libresoc.v:153136$7780 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:153137.5-153137.29" switch \initial attribute \src "libresoc.v:153137.9-153137.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$114 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:153146.3-153155.6" process $proc$libresoc.v:153146$7781 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] attribute \src "libresoc.v:153147.5-153147.29" switch \initial attribute \src "libresoc.v:153147.9-153147.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[3:0] \data_r1__cr_a case assign $1\dest2_o[3:0] 4'0000 end sync always update \dest2_o $0\dest2_o[3:0] end attribute \src "libresoc.v:153156.3-153165.6" process $proc$libresoc.v:153156$7782 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] attribute \src "libresoc.v:153157.5-153157.29" switch \initial attribute \src "libresoc.v:153157.9-153157.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$118 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[1:0] \data_r2__xer_ov case assign $1\dest3_o[1:0] 2'00 end sync always update \dest3_o $0\dest3_o[1:0] end attribute \src "libresoc.v:153166.3-153175.6" process $proc$libresoc.v:153166$7783 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] attribute \src "libresoc.v:153167.5-153167.29" switch \initial attribute \src "libresoc.v:153167.9-153167.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest4_o[0:0] \data_r3__xer_so case assign $1\dest4_o[0:0] 1'0 end sync always update \dest4_o $0\dest4_o[0:0] end attribute \src "libresoc.v:153176.3-153184.6" process $proc$libresoc.v:153176$7784 assign { } { } assign { } { } assign $0\prev_wr_go$next[3:0]$7785 $1\prev_wr_go$next[3:0]$7786 attribute \src "libresoc.v:153177.5-153177.29" switch \initial attribute \src "libresoc.v:153177.9-153177.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[3:0]$7786 4'0000 case assign $1\prev_wr_go$next[3:0]$7786 \$20 end sync always update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7785 end connect \$100 $and$libresoc.v:152652$7573_Y connect \$102 $and$libresoc.v:152653$7574_Y connect \$104 $and$libresoc.v:152654$7575_Y connect \$106 $and$libresoc.v:152655$7576_Y connect \$108 $and$libresoc.v:152656$7577_Y connect \$10 $and$libresoc.v:152657$7578_Y connect \$110 $and$libresoc.v:152658$7579_Y connect \$112 $and$libresoc.v:152659$7580_Y connect \$114 $and$libresoc.v:152660$7581_Y connect \$116 $and$libresoc.v:152661$7582_Y connect \$118 $and$libresoc.v:152662$7583_Y connect \$120 $and$libresoc.v:152663$7584_Y connect \$12 $not$libresoc.v:152664$7585_Y connect \$14 $and$libresoc.v:152665$7586_Y connect \$16 $not$libresoc.v:152666$7587_Y connect \$18 $and$libresoc.v:152667$7588_Y connect \$20 $and$libresoc.v:152668$7589_Y connect \$24 $not$libresoc.v:152669$7590_Y connect \$26 $and$libresoc.v:152670$7591_Y connect \$23 $reduce_or$libresoc.v:152671$7592_Y connect \$22 $not$libresoc.v:152672$7593_Y connect \$2 $and$libresoc.v:152673$7594_Y connect \$30 $and$libresoc.v:152674$7595_Y connect \$32 $reduce_or$libresoc.v:152675$7596_Y connect \$34 $reduce_or$libresoc.v:152676$7597_Y connect \$36 $or$libresoc.v:152677$7598_Y connect \$38 $not$libresoc.v:152678$7599_Y connect \$40 $and$libresoc.v:152679$7600_Y connect \$42 $and$libresoc.v:152680$7601_Y connect \$44 $eq$libresoc.v:152681$7602_Y connect \$46 $and$libresoc.v:152682$7603_Y connect \$48 $eq$libresoc.v:152683$7604_Y connect \$50 $and$libresoc.v:152684$7605_Y connect \$52 $and$libresoc.v:152685$7606_Y connect \$54 $and$libresoc.v:152686$7607_Y connect \$56 $or$libresoc.v:152687$7608_Y connect \$58 $or$libresoc.v:152688$7609_Y connect \$5 $not$libresoc.v:152689$7610_Y connect \$60 $or$libresoc.v:152690$7611_Y connect \$62 $or$libresoc.v:152691$7612_Y connect \$64 $and$libresoc.v:152692$7613_Y connect \$66 $and$libresoc.v:152693$7614_Y connect \$68 $or$libresoc.v:152694$7615_Y connect \$70 $and$libresoc.v:152695$7616_Y connect \$72 $and$libresoc.v:152696$7617_Y connect \$74 $and$libresoc.v:152697$7618_Y connect \$76 $and$libresoc.v:152698$7619_Y connect \$78 $ternary$libresoc.v:152699$7620_Y connect \$7 $or$libresoc.v:152700$7621_Y connect \$80 $ternary$libresoc.v:152701$7622_Y connect \$82 $ternary$libresoc.v:152702$7623_Y connect \$84 $ternary$libresoc.v:152703$7624_Y connect \$86 $ternary$libresoc.v:152704$7625_Y connect \$88 $and$libresoc.v:152705$7626_Y connect \$4 $reduce_and$libresoc.v:152706$7627_Y connect \$90 $and$libresoc.v:152707$7628_Y connect \$92 $and$libresoc.v:152708$7629_Y connect \$94 $not$libresoc.v:152709$7630_Y connect \$96 $and$libresoc.v:152710$7631_Y connect \$98 $not$libresoc.v:152711$7632_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 connect \cu_rd__rel_o \$100 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_mul0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_mul0_p_valid_i \alui_l_q_alui connect \alu_mul0_xer_so$1 \$86 connect \alu_mul0_rb \$84 connect \alu_mul0_ra \$82 connect \src_or_imm \$80 connect \src_sel \$78 connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } connect \reset_r \$62 connect \reset_w \$60 connect \rst_r \$58 connect \reset \$56 connect \wr_any \$36 connect \cu_done_o \$30 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$18 connect \alu_done_dly$next \alu_done connect \alu_done \alu_mul0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$14 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end attribute \src "libresoc.v:153219.1-153552.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 attribute \src "libresoc.v:153519.18-153519.116" wire $and$libresoc.v:153519$7827_Y attribute \src "libresoc.v:153521.18-153521.116" wire $and$libresoc.v:153521$7829_Y attribute \src "libresoc.v:153522.18-153522.117" wire $and$libresoc.v:153522$7830_Y attribute \src "libresoc.v:153523.18-153523.117" wire $and$libresoc.v:153523$7831_Y attribute \src "libresoc.v:153526.18-153526.95" wire width 65 $extend$libresoc.v:153526$7834_Y attribute \src "libresoc.v:153527.18-153527.91" wire width 65 $extend$libresoc.v:153527$7836_Y attribute \src "libresoc.v:153529.18-153529.95" wire width 65 $extend$libresoc.v:153529$7839_Y attribute \src "libresoc.v:153530.18-153530.91" wire width 65 $extend$libresoc.v:153530$7841_Y attribute \src "libresoc.v:153526.18-153526.95" wire width 65 $neg$libresoc.v:153526$7835_Y attribute \src "libresoc.v:153529.18-153529.95" wire width 65 $neg$libresoc.v:153529$7840_Y attribute \src "libresoc.v:153527.18-153527.91" wire width 65 $pos$libresoc.v:153527$7837_Y attribute \src "libresoc.v:153530.18-153530.91" wire width 65 $pos$libresoc.v:153530$7842_Y attribute \src "libresoc.v:153518.18-153518.125" wire $ternary$libresoc.v:153518$7826_Y attribute \src "libresoc.v:153520.18-153520.125" wire $ternary$libresoc.v:153520$7828_Y attribute \src "libresoc.v:153528.18-153528.112" wire width 65 $ternary$libresoc.v:153528$7838_Y attribute \src "libresoc.v:153531.18-153531.112" wire width 65 $ternary$libresoc.v:153531$7843_Y attribute \src "libresoc.v:153532.18-153532.116" wire width 32 $ternary$libresoc.v:153532$7844_Y attribute \src "libresoc.v:153533.18-153533.116" wire width 32 $ternary$libresoc.v:153533$7845_Y attribute \src "libresoc.v:153524.18-153524.106" wire $xor$libresoc.v:153524$7832_Y attribute \src "libresoc.v:153525.18-153525.110" wire $xor$libresoc.v:153525$7833_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" wire width 65 \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" wire width 65 \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 65 \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" wire width 65 \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" wire width 65 \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" wire width 65 \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 65 \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" wire width 65 \$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" wire width 64 \abs_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" wire width 64 \abs_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" wire \is_32bit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 28 \mul_op__insn$13 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 23 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 24 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 22 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 21 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 34 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire output 32 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire output 33 \neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 29 \ra$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 30 \rb$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" wire \sign32_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" wire \sign32_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" wire \sign_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" wire \sign_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 15 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" cell $and $and$libresoc.v:153519$7827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed connect \Y $and$libresoc.v:153519$7827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" cell $and $and$libresoc.v:153521$7829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed connect \Y $and$libresoc.v:153521$7829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" cell $and $and$libresoc.v:153522$7830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed connect \Y $and$libresoc.v:153522$7830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" cell $and $and$libresoc.v:153523$7831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed connect \Y $and$libresoc.v:153523$7831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" cell $pos $extend$libresoc.v:153526$7834 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra connect \Y $extend$libresoc.v:153526$7834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:153527$7836 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra connect \Y $extend$libresoc.v:153527$7836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" cell $pos $extend$libresoc.v:153529$7839 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb connect \Y $extend$libresoc.v:153529$7839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:153530$7841 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb connect \Y $extend$libresoc.v:153530$7841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" cell $neg $neg$libresoc.v:153526$7835 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:153526$7834_Y connect \Y $neg$libresoc.v:153526$7835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" cell $neg $neg$libresoc.v:153529$7840 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:153529$7839_Y connect \Y $neg$libresoc.v:153529$7840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:153527$7837 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:153527$7836_Y connect \Y $pos$libresoc.v:153527$7837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:153530$7842 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:153530$7841_Y connect \Y $pos$libresoc.v:153530$7842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" cell $mux $ternary$libresoc.v:153518$7826 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit connect \Y $ternary$libresoc.v:153518$7826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" cell $mux $ternary$libresoc.v:153520$7828 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit connect \Y $ternary$libresoc.v:153520$7828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" cell $mux $ternary$libresoc.v:153528$7838 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a connect \Y $ternary$libresoc.v:153528$7838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" cell $mux $ternary$libresoc.v:153531$7843 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b connect \Y $ternary$libresoc.v:153531$7843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" cell $mux $ternary$libresoc.v:153532$7844 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit connect \Y $ternary$libresoc.v:153532$7844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" cell $mux $ternary$libresoc.v:153533$7845 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit connect \Y $ternary$libresoc.v:153533$7845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" cell $xor $xor$libresoc.v:153524$7832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b connect \Y $xor$libresoc.v:153524$7832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" cell $xor $xor$libresoc.v:153525$7833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b connect \Y $xor$libresoc.v:153525$7833_Y end connect \$17 $ternary$libresoc.v:153518$7826_Y connect \$19 $and$libresoc.v:153519$7827_Y connect \$21 $ternary$libresoc.v:153520$7828_Y connect \$23 $and$libresoc.v:153521$7829_Y connect \$25 $and$libresoc.v:153522$7830_Y connect \$27 $and$libresoc.v:153523$7831_Y connect \$29 $xor$libresoc.v:153524$7832_Y connect \$31 $xor$libresoc.v:153525$7833_Y connect \$34 $neg$libresoc.v:153526$7835_Y connect \$36 $pos$libresoc.v:153527$7837_Y connect \$38 $ternary$libresoc.v:153528$7838_Y connect \$41 $neg$libresoc.v:153529$7840_Y connect \$43 $pos$libresoc.v:153530$7842_Y connect \$45 $ternary$libresoc.v:153531$7843_Y connect \$47 $ternary$libresoc.v:153532$7844_Y connect \$49 $ternary$libresoc.v:153533$7845_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$16 \xer_so connect \rb$15 [63:32] \$49 connect \rb$15 [31:0] \abs_b [31:0] connect \ra$14 [63:32] \$47 connect \ra$14 [31:0] \abs_a [31:0] connect \abs_b \$45 [63:0] connect \abs_a \$38 [63:0] connect \neg_res32 \$31 connect \neg_res \$29 connect \sign32_b \$27 connect \sign32_a \$25 connect \sign_b \$23 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end attribute \src "libresoc.v:153556.1-153819.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 attribute \src "libresoc.v:153812.18-153812.98" wire width 129 $extend$libresoc.v:153812$7847_Y attribute \src "libresoc.v:153811.18-153811.99" wire width 128 $mul$libresoc.v:153811$7846_Y attribute \src "libresoc.v:153812.18-153812.98" wire width 129 $pos$libresoc.v:153812$7848_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 128 \$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 21 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 22 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 30 \mul_op__insn$13 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 19 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 24 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 23 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 35 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 18 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire input 16 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire output 33 \neg_res$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire input 17 \neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire output 34 \neg_res32$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 output 31 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 15 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" cell $pos $extend$libresoc.v:153812$7847 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 connect \Y $extend$libresoc.v:153812$7847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" cell $mul $mul$libresoc.v:153811$7846 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb connect \Y $mul$libresoc.v:153811$7846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" cell $pos $pos$libresoc.v:153812$7848 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 connect \A $extend$libresoc.v:153812$7847_Y connect \Y $pos$libresoc.v:153812$7848_Y end connect \$18 $mul$libresoc.v:153811$7846_Y connect \$17 $pos$libresoc.v:153812$7848_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so connect \neg_res32$16 \neg_res32 connect \neg_res$15 \neg_res connect \o \$17 end attribute \src "libresoc.v:153823.1-154232.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 attribute \src "libresoc.v:153824.7-153824.20" wire $0\initial[0:0] attribute \src "libresoc.v:154161.3-154187.6" wire $0\mul_ov[0:0] attribute \src "libresoc.v:154123.3-154141.6" wire width 64 $0\o$14[63:0]$7865 attribute \src "libresoc.v:154142.3-154160.6" wire $0\o_ok[0:0] attribute \src "libresoc.v:154188.3-154206.6" wire width 2 $0\xer_ov[1:0] attribute \src "libresoc.v:154207.3-154225.6" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:154161.3-154187.6" wire $1\mul_ov[0:0] attribute \src "libresoc.v:154123.3-154141.6" wire width 64 $1\o$14[63:0]$7866 attribute \src "libresoc.v:154142.3-154160.6" wire $1\o_ok[0:0] attribute \src "libresoc.v:154188.3-154206.6" wire width 2 $1\xer_ov[1:0] attribute \src "libresoc.v:154207.3-154225.6" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:154161.3-154187.6" wire $2\mul_ov[0:0] attribute \src "libresoc.v:154117.18-154117.104" wire $and$libresoc.v:154117$7857_Y attribute \src "libresoc.v:154121.18-154121.104" wire $and$libresoc.v:154121$7861_Y attribute \src "libresoc.v:154111.18-154111.95" wire width 130 $extend$libresoc.v:154111$7849_Y attribute \src "libresoc.v:154112.18-154112.90" wire width 130 $extend$libresoc.v:154112$7851_Y attribute \src "libresoc.v:154122.18-154122.95" wire width 2 $extend$libresoc.v:154122$7862_Y attribute \src "libresoc.v:154111.18-154111.95" wire width 130 $neg$libresoc.v:154111$7850_Y attribute \src "libresoc.v:154116.18-154116.98" wire $not$libresoc.v:154116$7856_Y attribute \src "libresoc.v:154120.18-154120.98" wire $not$libresoc.v:154120$7860_Y attribute \src "libresoc.v:154112.18-154112.90" wire width 130 $pos$libresoc.v:154112$7852_Y attribute \src "libresoc.v:154122.18-154122.95" wire width 2 $pos$libresoc.v:154122$7863_Y attribute \src "libresoc.v:154115.18-154115.106" wire $reduce_and$libresoc.v:154115$7855_Y attribute \src "libresoc.v:154119.18-154119.107" wire $reduce_and$libresoc.v:154119$7859_Y attribute \src "libresoc.v:154114.18-154114.106" wire $reduce_or$libresoc.v:154114$7854_Y attribute \src "libresoc.v:154118.18-154118.107" wire $reduce_or$libresoc.v:154118$7858_Y attribute \src "libresoc.v:154113.18-154113.114" wire width 130 $ternary$libresoc.v:154113$7853_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 130 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 attribute \src "libresoc.v:153824.7-153824.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" wire width 129 \mul_o attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 18 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 28 \mul_op__insn$13 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 23 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 24 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 22 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 21 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" wire \mul_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 35 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire input 15 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 input 13 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 29 \o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 31 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 14 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \xer_so$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $and $and$libresoc.v:154117$7857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 connect \Y $and$libresoc.v:154117$7857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $and $and$libresoc.v:154121$7861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 connect \Y $and$libresoc.v:154121$7861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" cell $pos $extend$libresoc.v:154111$7849 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o connect \Y $extend$libresoc.v:154111$7849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:154112$7851 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o connect \Y $extend$libresoc.v:154112$7851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:154122$7862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so connect \Y $extend$libresoc.v:154122$7862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" cell $neg $neg$libresoc.v:154111$7850 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 connect \A $extend$libresoc.v:154111$7849_Y connect \Y $neg$libresoc.v:154111$7850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $not $not$libresoc.v:154116$7856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 connect \Y $not$libresoc.v:154116$7856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $not $not$libresoc.v:154120$7860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 connect \Y $not$libresoc.v:154120$7860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:154112$7852 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 connect \A $extend$libresoc.v:154112$7851_Y connect \Y $pos$libresoc.v:154112$7852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:154122$7863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A $extend$libresoc.v:154122$7862_Y connect \Y $pos$libresoc.v:154122$7863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $reduce_and $reduce_and$libresoc.v:154115$7855 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] connect \Y $reduce_and$libresoc.v:154115$7855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $reduce_and $reduce_and$libresoc.v:154119$7859 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] connect \Y $reduce_and$libresoc.v:154119$7859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" cell $reduce_or $reduce_or$libresoc.v:154114$7854 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] connect \Y $reduce_or$libresoc.v:154114$7854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" cell $reduce_or $reduce_or$libresoc.v:154118$7858 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] connect \Y $reduce_or$libresoc.v:154118$7858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" cell $mux $ternary$libresoc.v:154113$7853 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res connect \Y $ternary$libresoc.v:154113$7853_Y end attribute \src "libresoc.v:153824.7-153824.20" process $proc$libresoc.v:153824$7871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:154123.3-154141.6" process $proc$libresoc.v:154123$7864 assign { } { } assign { } { } assign $0\o$14[63:0]$7865 $1\o$14[63:0]$7866 attribute \src "libresoc.v:154124.5-154124.29" switch \initial attribute \src "libresoc.v:154124.9-154124.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } assign $1\o$14[63:0]$7866 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } assign $1\o$14[63:0]$7866 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\o$14[63:0]$7866 \mul_o [63:0] case assign $1\o$14[63:0]$7866 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \o$14 $0\o$14[63:0]$7865 end attribute \src "libresoc.v:154142.3-154160.6" process $proc$libresoc.v:154142$7867 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] attribute \src "libresoc.v:154143.5-154143.29" switch \initial attribute \src "libresoc.v:154143.9-154143.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\o_ok[0:0] 1'1 case assign $1\o_ok[0:0] 1'0 end sync always update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:154161.3-154187.6" process $proc$libresoc.v:154161$7868 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] attribute \src "libresoc.v:154162.5-154162.29" switch \initial attribute \src "libresoc.v:154162.9-154162.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign $1\mul_ov[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign $1\mul_ov[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\mul_ov[0:0] $2\mul_ov[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\mul_ov[0:0] \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\mul_ov[0:0] \$37 end case assign $1\mul_ov[0:0] 1'0 end sync always update \mul_ov $0\mul_ov[0:0] end attribute \src "libresoc.v:154188.3-154206.6" process $proc$libresoc.v:154188$7869 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] attribute \src "libresoc.v:154189.5-154189.29" switch \initial attribute \src "libresoc.v:154189.9-154189.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign $1\xer_ov[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign $1\xer_ov[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\xer_ov[1:0] { \mul_ov \mul_ov } case assign $1\xer_ov[1:0] 2'00 end sync always update \xer_ov $0\xer_ov[1:0] end attribute \src "libresoc.v:154207.3-154225.6" process $proc$libresoc.v:154207$7870 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] attribute \src "libresoc.v:154208.5-154208.29" switch \initial attribute \src "libresoc.v:154208.9-154208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign $1\xer_ov_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign $1\xer_ov_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 case assign $1\xer_ov_ok[0:0] 1'0 end sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end connect \$17 $neg$libresoc.v:154111$7850_Y connect \$19 $pos$libresoc.v:154112$7852_Y connect \$21 $ternary$libresoc.v:154113$7853_Y connect \$23 $reduce_or$libresoc.v:154114$7854_Y connect \$26 $reduce_and$libresoc.v:154115$7855_Y connect \$25 $not$libresoc.v:154116$7856_Y connect \$29 $and$libresoc.v:154117$7857_Y connect \$31 $reduce_or$libresoc.v:154118$7858_Y connect \$34 $reduce_and$libresoc.v:154119$7859_Y connect \$33 $not$libresoc.v:154120$7860_Y connect \$37 $and$libresoc.v:154121$7861_Y connect \$39 $pos$libresoc.v:154122$7863_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect { \xer_so_ok \xer_so$15 } \$39 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end attribute \src "libresoc.v:154236.1-155453.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 attribute \src "libresoc.v:154237.7-154237.20" wire $0\initial[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 14 $0\mul_op__fn_unit$next[13:0]$7900 attribute \src "libresoc.v:155195.3-155196.47" wire width 14 $0\mul_op__fn_unit[13:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 64 $0\mul_op__imm_data__data$next[63:0]$7901 attribute \src "libresoc.v:155197.3-155198.61" wire width 64 $0\mul_op__imm_data__data[63:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__imm_data__ok$next[0:0]$7902 attribute \src "libresoc.v:155199.3-155200.57" wire $0\mul_op__imm_data__ok[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 32 $0\mul_op__insn$next[31:0]$7903 attribute \src "libresoc.v:155215.3-155216.41" wire width 32 $0\mul_op__insn[31:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 7 $0\mul_op__insn_type$next[6:0]$7904 attribute \src "libresoc.v:155193.3-155194.51" wire width 7 $0\mul_op__insn_type[6:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__is_32bit$next[0:0]$7905 attribute \src "libresoc.v:155211.3-155212.49" wire $0\mul_op__is_32bit[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__is_signed$next[0:0]$7906 attribute \src "libresoc.v:155213.3-155214.51" wire $0\mul_op__is_signed[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__oe__oe$next[0:0]$7907 attribute \src "libresoc.v:155205.3-155206.45" wire $0\mul_op__oe__oe[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__oe__ok$next[0:0]$7908 attribute \src "libresoc.v:155207.3-155208.45" wire $0\mul_op__oe__ok[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__rc__ok$next[0:0]$7909 attribute \src "libresoc.v:155203.3-155204.45" wire $0\mul_op__rc__ok[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__rc__rc$next[0:0]$7910 attribute \src "libresoc.v:155201.3-155202.45" wire $0\mul_op__rc__rc[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $0\mul_op__write_cr0$next[0:0]$7911 attribute \src "libresoc.v:155209.3-155210.51" wire $0\mul_op__write_cr0[0:0] attribute \src "libresoc.v:155317.3-155329.6" wire width 2 $0\muxid$next[1:0]$7897 attribute \src "libresoc.v:155217.3-155218.27" wire width 2 $0\muxid[1:0] attribute \src "libresoc.v:155405.3-155417.6" wire $0\neg_res$next[0:0]$7940 attribute \src "libresoc.v:155418.3-155430.6" wire $0\neg_res32$next[0:0]$7943 attribute \src "libresoc.v:155183.3-155184.35" wire $0\neg_res32[0:0] attribute \src "libresoc.v:155185.3-155186.31" wire $0\neg_res[0:0] attribute \src "libresoc.v:155299.3-155316.6" wire $0\r_busy$next[0:0]$7893 attribute \src "libresoc.v:155219.3-155220.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:155366.3-155378.6" wire width 64 $0\ra$next[63:0]$7931 attribute \src "libresoc.v:155191.3-155192.21" wire width 64 $0\ra[63:0] attribute \src "libresoc.v:155379.3-155391.6" wire width 64 $0\rb$next[63:0]$7934 attribute \src "libresoc.v:155189.3-155190.21" wire width 64 $0\rb[63:0] attribute \src "libresoc.v:155392.3-155404.6" wire $0\xer_so$next[0:0]$7937 attribute \src "libresoc.v:155187.3-155188.29" wire $0\xer_so[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 14 $1\mul_op__fn_unit$next[13:0]$7912 attribute \src "libresoc.v:154753.14-154753.40" wire width 14 $1\mul_op__fn_unit[13:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 64 $1\mul_op__imm_data__data$next[63:0]$7913 attribute \src "libresoc.v:154792.14-154792.59" wire width 64 $1\mul_op__imm_data__data[63:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__imm_data__ok$next[0:0]$7914 attribute \src "libresoc.v:154801.7-154801.34" wire $1\mul_op__imm_data__ok[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 32 $1\mul_op__insn$next[31:0]$7915 attribute \src "libresoc.v:154810.14-154810.34" wire width 32 $1\mul_op__insn[31:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 7 $1\mul_op__insn_type$next[6:0]$7916 attribute \src "libresoc.v:154894.13-154894.38" wire width 7 $1\mul_op__insn_type[6:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__is_32bit$next[0:0]$7917 attribute \src "libresoc.v:155053.7-155053.30" wire $1\mul_op__is_32bit[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__is_signed$next[0:0]$7918 attribute \src "libresoc.v:155062.7-155062.31" wire $1\mul_op__is_signed[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__oe__oe$next[0:0]$7919 attribute \src "libresoc.v:155071.7-155071.28" wire $1\mul_op__oe__oe[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__oe__ok$next[0:0]$7920 attribute \src "libresoc.v:155080.7-155080.28" wire $1\mul_op__oe__ok[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__rc__ok$next[0:0]$7921 attribute \src "libresoc.v:155089.7-155089.28" wire $1\mul_op__rc__ok[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__rc__rc$next[0:0]$7922 attribute \src "libresoc.v:155098.7-155098.28" wire $1\mul_op__rc__rc[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire $1\mul_op__write_cr0$next[0:0]$7923 attribute \src "libresoc.v:155107.7-155107.31" wire $1\mul_op__write_cr0[0:0] attribute \src "libresoc.v:155317.3-155329.6" wire width 2 $1\muxid$next[1:0]$7898 attribute \src "libresoc.v:155116.13-155116.25" wire width 2 $1\muxid[1:0] attribute \src "libresoc.v:155405.3-155417.6" wire $1\neg_res$next[0:0]$7941 attribute \src "libresoc.v:155418.3-155430.6" wire $1\neg_res32$next[0:0]$7944 attribute \src "libresoc.v:155138.7-155138.23" wire $1\neg_res32[0:0] attribute \src "libresoc.v:155131.7-155131.21" wire $1\neg_res[0:0] attribute \src "libresoc.v:155299.3-155316.6" wire $1\r_busy$next[0:0]$7894 attribute \src "libresoc.v:155152.7-155152.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:155366.3-155378.6" wire width 64 $1\ra$next[63:0]$7932 attribute \src "libresoc.v:155157.14-155157.39" wire width 64 $1\ra[63:0] attribute \src "libresoc.v:155379.3-155391.6" wire width 64 $1\rb$next[63:0]$7935 attribute \src "libresoc.v:155166.14-155166.39" wire width 64 $1\rb[63:0] attribute \src "libresoc.v:155392.3-155404.6" wire $1\xer_so$next[0:0]$7938 attribute \src "libresoc.v:155175.7-155175.20" wire $1\xer_so[0:0] attribute \src "libresoc.v:155330.3-155365.6" wire width 64 $2\mul_op__imm_data__data$next[63:0]$7924 attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__imm_data__ok$next[0:0]$7925 attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__oe__oe$next[0:0]$7926 attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__oe__ok$next[0:0]$7927 attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__rc__ok$next[0:0]$7928 attribute \src "libresoc.v:155330.3-155365.6" wire $2\mul_op__rc__rc$next[0:0]$7929 attribute \src "libresoc.v:155299.3-155316.6" wire $2\r_busy$next[0:0]$7895 attribute \src "libresoc.v:155182.18-155182.118" wire $and$libresoc.v:155182$7872_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 40 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:154237.7-154237.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_mul_op__imm_data__data$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__imm_data__ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_mul_op__insn$29 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_mul_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__is_32bit$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__is_signed$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__oe__oe$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__oe__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__rc__ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__rc__rc$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_mul_op__write_cr0$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so$32 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul1_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul1_mul_op__fn_unit$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul1_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul1_mul_op__imm_data__data$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__imm_data__ok$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul1_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul1_mul_op__insn$45 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul1_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul1_mul_op__insn_type$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__is_32bit$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__is_signed$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__oe__oe$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__oe__ok$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__rc__ok$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__rc__rc$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul1_mul_op__write_cr0$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul1_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul1_muxid$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul1_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \mul1_neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul1_ra$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul1_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul1_rb$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul1_xer_so$48 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 6 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 26 \mul_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_op__fn_unit$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 27 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_op__imm_data__data$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 28 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__imm_data__ok$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 16 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 36 \mul_op__insn$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_op__insn$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 25 \mul_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 34 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_32bit$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 35 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_signed$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__oe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 31 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__ok$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 32 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__ok$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 30 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__rc$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 29 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 33 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 24 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire output 20 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \neg_res$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \neg_res$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire output 21 \neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \neg_res32$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \neg_res32$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 23 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 22 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 17 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 37 \ra$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 18 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 38 \rb$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 19 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 39 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:155182$7872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o connect \Y $and$libresoc.v:155182$7872_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:155221.14-155254.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 connect \mul_op__imm_data__data \input_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 connect \mul_op__insn \input_mul_op__insn connect \mul_op__insn$13 \input_mul_op__insn$29 connect \mul_op__insn_type \input_mul_op__insn_type connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 connect \mul_op__is_32bit \input_mul_op__is_32bit connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 connect \mul_op__is_signed \input_mul_op__is_signed connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 connect \mul_op__oe__oe \input_mul_op__oe__oe connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 connect \mul_op__oe__ok \input_mul_op__oe__ok connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 connect \mul_op__rc__ok \input_mul_op__rc__ok connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 connect \mul_op__rc__rc \input_mul_op__rc__rc connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 connect \mul_op__write_cr0 \input_mul_op__write_cr0 connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 connect \muxid \input_muxid connect \muxid$1 \input_muxid$17 connect \ra \input_ra connect \ra$14 \input_ra$30 connect \rb \input_rb connect \rb$15 \input_rb$31 connect \xer_so \input_xer_so connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 attribute \src "libresoc.v:155255.8-155290.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 connect \mul_op__insn \mul1_mul_op__insn connect \mul_op__insn$13 \mul1_mul_op__insn$45 connect \mul_op__insn_type \mul1_mul_op__insn_type connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 connect \mul_op__is_32bit \mul1_mul_op__is_32bit connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 connect \mul_op__is_signed \mul1_mul_op__is_signed connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 connect \mul_op__oe__oe \mul1_mul_op__oe__oe connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 connect \mul_op__oe__ok \mul1_mul_op__oe__ok connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 connect \mul_op__rc__ok \mul1_mul_op__rc__ok connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 connect \mul_op__rc__rc \mul1_mul_op__rc__rc connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 connect \muxid \mul1_muxid connect \muxid$1 \mul1_muxid$33 connect \neg_res \mul1_neg_res connect \neg_res32 \mul1_neg_res32 connect \ra \mul1_ra connect \ra$14 \mul1_ra$46 connect \rb \mul1_rb connect \rb$15 \mul1_rb$47 connect \xer_so \mul1_xer_so connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 attribute \src "libresoc.v:155291.10-155294.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:155295.10-155298.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:154237.7-154237.20" process $proc$libresoc.v:154237$7945 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:154753.14-154753.40" process $proc$libresoc.v:154753$7946 assign { } { } assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end attribute \src "libresoc.v:154792.14-154792.59" process $proc$libresoc.v:154792$7947 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end attribute \src "libresoc.v:154801.7-154801.34" process $proc$libresoc.v:154801$7948 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end attribute \src "libresoc.v:154810.14-154810.34" process $proc$libresoc.v:154810$7949 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end attribute \src "libresoc.v:154894.13-154894.38" process $proc$libresoc.v:154894$7950 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end attribute \src "libresoc.v:155053.7-155053.30" process $proc$libresoc.v:155053$7951 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end attribute \src "libresoc.v:155062.7-155062.31" process $proc$libresoc.v:155062$7952 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end attribute \src "libresoc.v:155071.7-155071.28" process $proc$libresoc.v:155071$7953 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end attribute \src "libresoc.v:155080.7-155080.28" process $proc$libresoc.v:155080$7954 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end attribute \src "libresoc.v:155089.7-155089.28" process $proc$libresoc.v:155089$7955 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end attribute \src "libresoc.v:155098.7-155098.28" process $proc$libresoc.v:155098$7956 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end attribute \src "libresoc.v:155107.7-155107.31" process $proc$libresoc.v:155107$7957 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end attribute \src "libresoc.v:155116.13-155116.25" process $proc$libresoc.v:155116$7958 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end attribute \src "libresoc.v:155131.7-155131.21" process $proc$libresoc.v:155131$7959 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end attribute \src "libresoc.v:155138.7-155138.23" process $proc$libresoc.v:155138$7960 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end attribute \src "libresoc.v:155152.7-155152.20" process $proc$libresoc.v:155152$7961 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:155157.14-155157.39" process $proc$libresoc.v:155157$7962 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end attribute \src "libresoc.v:155166.14-155166.39" process $proc$libresoc.v:155166$7963 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end attribute \src "libresoc.v:155175.7-155175.20" process $proc$libresoc.v:155175$7964 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end attribute \src "libresoc.v:155183.3-155184.35" process $proc$libresoc.v:155183$7873 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end attribute \src "libresoc.v:155185.3-155186.31" process $proc$libresoc.v:155185$7874 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end attribute \src "libresoc.v:155187.3-155188.29" process $proc$libresoc.v:155187$7875 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end attribute \src "libresoc.v:155189.3-155190.21" process $proc$libresoc.v:155189$7876 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end attribute \src "libresoc.v:155191.3-155192.21" process $proc$libresoc.v:155191$7877 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end attribute \src "libresoc.v:155193.3-155194.51" process $proc$libresoc.v:155193$7878 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end attribute \src "libresoc.v:155195.3-155196.47" process $proc$libresoc.v:155195$7879 assign { } { } assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end attribute \src "libresoc.v:155197.3-155198.61" process $proc$libresoc.v:155197$7880 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end attribute \src "libresoc.v:155199.3-155200.57" process $proc$libresoc.v:155199$7881 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end attribute \src "libresoc.v:155201.3-155202.45" process $proc$libresoc.v:155201$7882 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end attribute \src "libresoc.v:155203.3-155204.45" process $proc$libresoc.v:155203$7883 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end attribute \src "libresoc.v:155205.3-155206.45" process $proc$libresoc.v:155205$7884 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end attribute \src "libresoc.v:155207.3-155208.45" process $proc$libresoc.v:155207$7885 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end attribute \src "libresoc.v:155209.3-155210.51" process $proc$libresoc.v:155209$7886 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end attribute \src "libresoc.v:155211.3-155212.49" process $proc$libresoc.v:155211$7887 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end attribute \src "libresoc.v:155213.3-155214.51" process $proc$libresoc.v:155213$7888 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end attribute \src "libresoc.v:155215.3-155216.41" process $proc$libresoc.v:155215$7889 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end attribute \src "libresoc.v:155217.3-155218.27" process $proc$libresoc.v:155217$7890 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end attribute \src "libresoc.v:155219.3-155220.29" process $proc$libresoc.v:155219$7891 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:155299.3-155316.6" process $proc$libresoc.v:155299$7892 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$7893 $2\r_busy$next[0:0]$7895 attribute \src "libresoc.v:155300.5-155300.29" switch \initial attribute \src "libresoc.v:155300.9-155300.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$7894 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$7894 1'0 case assign $1\r_busy$next[0:0]$7894 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$7895 1'0 case assign $2\r_busy$next[0:0]$7895 $1\r_busy$next[0:0]$7894 end sync always update \r_busy$next $0\r_busy$next[0:0]$7893 end attribute \src "libresoc.v:155317.3-155329.6" process $proc$libresoc.v:155317$7896 assign { } { } assign { } { } assign $0\muxid$next[1:0]$7897 $1\muxid$next[1:0]$7898 attribute \src "libresoc.v:155318.5-155318.29" switch \initial attribute \src "libresoc.v:155318.9-155318.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$next[1:0]$7898 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$next[1:0]$7898 \muxid$52 case assign $1\muxid$next[1:0]$7898 \muxid end sync always update \muxid$next $0\muxid$next[1:0]$7897 end attribute \src "libresoc.v:155330.3-155365.6" process $proc$libresoc.v:155330$7899 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\mul_op__fn_unit$next[13:0]$7900 $1\mul_op__fn_unit$next[13:0]$7912 assign { } { } assign { } { } assign $0\mul_op__insn$next[31:0]$7903 $1\mul_op__insn$next[31:0]$7915 assign $0\mul_op__insn_type$next[6:0]$7904 $1\mul_op__insn_type$next[6:0]$7916 assign $0\mul_op__is_32bit$next[0:0]$7905 $1\mul_op__is_32bit$next[0:0]$7917 assign $0\mul_op__is_signed$next[0:0]$7906 $1\mul_op__is_signed$next[0:0]$7918 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\mul_op__write_cr0$next[0:0]$7911 $1\mul_op__write_cr0$next[0:0]$7923 assign $0\mul_op__imm_data__data$next[63:0]$7901 $2\mul_op__imm_data__data$next[63:0]$7924 assign $0\mul_op__imm_data__ok$next[0:0]$7902 $2\mul_op__imm_data__ok$next[0:0]$7925 assign $0\mul_op__oe__oe$next[0:0]$7907 $2\mul_op__oe__oe$next[0:0]$7926 assign $0\mul_op__oe__ok$next[0:0]$7908 $2\mul_op__oe__ok$next[0:0]$7927 assign $0\mul_op__rc__ok$next[0:0]$7909 $2\mul_op__rc__ok$next[0:0]$7928 assign $0\mul_op__rc__rc$next[0:0]$7910 $2\mul_op__rc__rc$next[0:0]$7929 attribute \src "libresoc.v:155331.5-155331.29" switch \initial attribute \src "libresoc.v:155331.9-155331.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\mul_op__insn$next[31:0]$7915 $1\mul_op__is_signed$next[0:0]$7918 $1\mul_op__is_32bit$next[0:0]$7917 $1\mul_op__write_cr0$next[0:0]$7923 $1\mul_op__oe__ok$next[0:0]$7920 $1\mul_op__oe__oe$next[0:0]$7919 $1\mul_op__rc__ok$next[0:0]$7921 $1\mul_op__rc__rc$next[0:0]$7922 $1\mul_op__imm_data__ok$next[0:0]$7914 $1\mul_op__imm_data__data$next[63:0]$7913 $1\mul_op__fn_unit$next[13:0]$7912 $1\mul_op__insn_type$next[6:0]$7916 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\mul_op__insn$next[31:0]$7915 $1\mul_op__is_signed$next[0:0]$7918 $1\mul_op__is_32bit$next[0:0]$7917 $1\mul_op__write_cr0$next[0:0]$7923 $1\mul_op__oe__ok$next[0:0]$7920 $1\mul_op__oe__oe$next[0:0]$7919 $1\mul_op__rc__ok$next[0:0]$7921 $1\mul_op__rc__rc$next[0:0]$7922 $1\mul_op__imm_data__ok$next[0:0]$7914 $1\mul_op__imm_data__data$next[63:0]$7913 $1\mul_op__fn_unit$next[13:0]$7912 $1\mul_op__insn_type$next[6:0]$7916 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case assign $1\mul_op__fn_unit$next[13:0]$7912 \mul_op__fn_unit assign $1\mul_op__imm_data__data$next[63:0]$7913 \mul_op__imm_data__data assign $1\mul_op__imm_data__ok$next[0:0]$7914 \mul_op__imm_data__ok assign $1\mul_op__insn$next[31:0]$7915 \mul_op__insn assign $1\mul_op__insn_type$next[6:0]$7916 \mul_op__insn_type assign $1\mul_op__is_32bit$next[0:0]$7917 \mul_op__is_32bit assign $1\mul_op__is_signed$next[0:0]$7918 \mul_op__is_signed assign $1\mul_op__oe__oe$next[0:0]$7919 \mul_op__oe__oe assign $1\mul_op__oe__ok$next[0:0]$7920 \mul_op__oe__ok assign $1\mul_op__rc__ok$next[0:0]$7921 \mul_op__rc__ok assign $1\mul_op__rc__rc$next[0:0]$7922 \mul_op__rc__rc assign $1\mul_op__write_cr0$next[0:0]$7923 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\mul_op__imm_data__data$next[63:0]$7924 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\mul_op__imm_data__ok$next[0:0]$7925 1'0 assign $2\mul_op__rc__rc$next[0:0]$7929 1'0 assign $2\mul_op__rc__ok$next[0:0]$7928 1'0 assign $2\mul_op__oe__oe$next[0:0]$7926 1'0 assign $2\mul_op__oe__ok$next[0:0]$7927 1'0 case assign $2\mul_op__imm_data__data$next[63:0]$7924 $1\mul_op__imm_data__data$next[63:0]$7913 assign $2\mul_op__imm_data__ok$next[0:0]$7925 $1\mul_op__imm_data__ok$next[0:0]$7914 assign $2\mul_op__oe__oe$next[0:0]$7926 $1\mul_op__oe__oe$next[0:0]$7919 assign $2\mul_op__oe__ok$next[0:0]$7927 $1\mul_op__oe__ok$next[0:0]$7920 assign $2\mul_op__rc__ok$next[0:0]$7928 $1\mul_op__rc__ok$next[0:0]$7921 assign $2\mul_op__rc__rc$next[0:0]$7929 $1\mul_op__rc__rc$next[0:0]$7922 end sync always update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7900 update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7901 update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7902 update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7903 update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7904 update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7905 update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7906 update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7907 update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7908 update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7909 update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7910 update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7911 end attribute \src "libresoc.v:155366.3-155378.6" process $proc$libresoc.v:155366$7930 assign { } { } assign { } { } assign $0\ra$next[63:0]$7931 $1\ra$next[63:0]$7932 attribute \src "libresoc.v:155367.5-155367.29" switch \initial attribute \src "libresoc.v:155367.9-155367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\ra$next[63:0]$7932 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\ra$next[63:0]$7932 \ra$65 case assign $1\ra$next[63:0]$7932 \ra end sync always update \ra$next $0\ra$next[63:0]$7931 end attribute \src "libresoc.v:155379.3-155391.6" process $proc$libresoc.v:155379$7933 assign { } { } assign { } { } assign $0\rb$next[63:0]$7934 $1\rb$next[63:0]$7935 attribute \src "libresoc.v:155380.5-155380.29" switch \initial attribute \src "libresoc.v:155380.9-155380.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\rb$next[63:0]$7935 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\rb$next[63:0]$7935 \rb$66 case assign $1\rb$next[63:0]$7935 \rb end sync always update \rb$next $0\rb$next[63:0]$7934 end attribute \src "libresoc.v:155392.3-155404.6" process $proc$libresoc.v:155392$7936 assign { } { } assign { } { } assign $0\xer_so$next[0:0]$7937 $1\xer_so$next[0:0]$7938 attribute \src "libresoc.v:155393.5-155393.29" switch \initial attribute \src "libresoc.v:155393.9-155393.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\xer_so$next[0:0]$7938 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\xer_so$next[0:0]$7938 \xer_so$67 case assign $1\xer_so$next[0:0]$7938 \xer_so end sync always update \xer_so$next $0\xer_so$next[0:0]$7937 end attribute \src "libresoc.v:155405.3-155417.6" process $proc$libresoc.v:155405$7939 assign { } { } assign { } { } assign $0\neg_res$next[0:0]$7940 $1\neg_res$next[0:0]$7941 attribute \src "libresoc.v:155406.5-155406.29" switch \initial attribute \src "libresoc.v:155406.9-155406.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\neg_res$next[0:0]$7941 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\neg_res$next[0:0]$7941 \neg_res$68 case assign $1\neg_res$next[0:0]$7941 \neg_res end sync always update \neg_res$next $0\neg_res$next[0:0]$7940 end attribute \src "libresoc.v:155418.3-155430.6" process $proc$libresoc.v:155418$7942 assign { } { } assign { } { } assign $0\neg_res32$next[0:0]$7943 $1\neg_res32$next[0:0]$7944 attribute \src "libresoc.v:155419.5-155419.29" switch \initial attribute \src "libresoc.v:155419.9-155419.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\neg_res32$next[0:0]$7944 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\neg_res32$next[0:0]$7944 \neg_res32$69 case assign $1\neg_res32$next[0:0]$7944 \neg_res32 end sync always update \neg_res32$next $0\neg_res32$next[0:0]$7943 end connect \$50 $and$libresoc.v:155182$7872_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 connect \neg_res$68 \mul1_neg_res connect \xer_so$67 \mul1_xer_so$48 connect \rb$66 \mul1_rb$47 connect \ra$65 \mul1_ra$46 connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } connect \muxid$52 \mul1_muxid$33 connect \p_valid_i_p_ready_o \$50 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$49 \p_valid_i connect \mul1_xer_so \input_xer_so$32 connect \mul1_rb \input_rb$31 connect \mul1_ra \input_ra$30 connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } connect \mul1_muxid \input_muxid$17 connect \input_xer_so \xer_so$16 connect \input_rb \rb$15 connect \input_ra \ra$14 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end attribute \src "libresoc.v:155457.1-156377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 attribute \src "libresoc.v:155458.7-155458.20" wire $0\initial[0:0] attribute \src "libresoc.v:156271.3-156306.6" wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8008 attribute \src "libresoc.v:156169.3-156170.53" wire width 14 $0\mul_op__fn_unit$3[13:0]$7976 attribute \src "libresoc.v:155749.14-155749.44" wire width 14 $0\mul_op__fn_unit$3[13:0]$8052 attribute \src "libresoc.v:156271.3-156306.6" wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8009 attribute \src "libresoc.v:156171.3-156172.67" wire width 64 $0\mul_op__imm_data__data$4[63:0]$7978 attribute \src "libresoc.v:155775.14-155775.63" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8054 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__imm_data__ok$5$next[0:0]$8010 attribute \src "libresoc.v:156173.3-156174.63" wire $0\mul_op__imm_data__ok$5[0:0]$7980 attribute \src "libresoc.v:155784.7-155784.38" wire $0\mul_op__imm_data__ok$5[0:0]$8056 attribute \src "libresoc.v:156271.3-156306.6" wire width 32 $0\mul_op__insn$13$next[31:0]$8011 attribute \src "libresoc.v:156189.3-156190.49" wire width 32 $0\mul_op__insn$13[31:0]$7996 attribute \src "libresoc.v:155791.14-155791.39" wire width 32 $0\mul_op__insn$13[31:0]$8058 attribute \src "libresoc.v:156271.3-156306.6" wire width 7 $0\mul_op__insn_type$2$next[6:0]$8012 attribute \src "libresoc.v:156167.3-156168.57" wire width 7 $0\mul_op__insn_type$2[6:0]$7974 attribute \src "libresoc.v:155950.13-155950.42" wire width 7 $0\mul_op__insn_type$2[6:0]$8060 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__is_32bit$11$next[0:0]$8013 attribute \src "libresoc.v:156185.3-156186.57" wire $0\mul_op__is_32bit$11[0:0]$7992 attribute \src "libresoc.v:156034.7-156034.35" wire $0\mul_op__is_32bit$11[0:0]$8062 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__is_signed$12$next[0:0]$8014 attribute \src "libresoc.v:156187.3-156188.59" wire $0\mul_op__is_signed$12[0:0]$7994 attribute \src "libresoc.v:156043.7-156043.36" wire $0\mul_op__is_signed$12[0:0]$8064 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__oe__oe$8$next[0:0]$8015 attribute \src "libresoc.v:156179.3-156180.51" wire $0\mul_op__oe__oe$8[0:0]$7986 attribute \src "libresoc.v:156054.7-156054.32" wire $0\mul_op__oe__oe$8[0:0]$8066 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__oe__ok$9$next[0:0]$8016 attribute \src "libresoc.v:156181.3-156182.51" wire $0\mul_op__oe__ok$9[0:0]$7988 attribute \src "libresoc.v:156063.7-156063.32" wire $0\mul_op__oe__ok$9[0:0]$8068 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__rc__ok$7$next[0:0]$8017 attribute \src "libresoc.v:156177.3-156178.51" wire $0\mul_op__rc__ok$7[0:0]$7984 attribute \src "libresoc.v:156072.7-156072.32" wire $0\mul_op__rc__ok$7[0:0]$8070 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__rc__rc$6$next[0:0]$8018 attribute \src "libresoc.v:156175.3-156176.51" wire $0\mul_op__rc__rc$6[0:0]$7982 attribute \src "libresoc.v:156081.7-156081.32" wire $0\mul_op__rc__rc$6[0:0]$8072 attribute \src "libresoc.v:156271.3-156306.6" wire $0\mul_op__write_cr0$10$next[0:0]$8019 attribute \src "libresoc.v:156183.3-156184.59" wire $0\mul_op__write_cr0$10[0:0]$7990 attribute \src "libresoc.v:156088.7-156088.36" wire $0\mul_op__write_cr0$10[0:0]$8074 attribute \src "libresoc.v:156258.3-156270.6" wire width 2 $0\muxid$1$next[1:0]$8005 attribute \src "libresoc.v:156191.3-156192.33" wire width 2 $0\muxid$1[1:0]$7998 attribute \src "libresoc.v:156097.13-156097.29" wire width 2 $0\muxid$1[1:0]$8076 attribute \src "libresoc.v:156333.3-156345.6" wire $0\neg_res$15$next[0:0]$8045 attribute \src "libresoc.v:156161.3-156162.39" wire $0\neg_res$15[0:0]$7969 attribute \src "libresoc.v:156112.7-156112.26" wire $0\neg_res$15[0:0]$8078 attribute \src "libresoc.v:156346.3-156358.6" wire $0\neg_res32$16$next[0:0]$8048 attribute \src "libresoc.v:156159.3-156160.43" wire $0\neg_res32$16[0:0]$7967 attribute \src "libresoc.v:156121.7-156121.28" wire $0\neg_res32$16[0:0]$8080 attribute \src "libresoc.v:156307.3-156319.6" wire width 129 $0\o$next[128:0]$8039 attribute \src "libresoc.v:156165.3-156166.19" wire width 129 $0\o[128:0] attribute \src "libresoc.v:156240.3-156257.6" wire $0\r_busy$next[0:0]$8001 attribute \src "libresoc.v:156193.3-156194.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:156320.3-156332.6" wire $0\xer_so$14$next[0:0]$8042 attribute \src "libresoc.v:156163.3-156164.37" wire $0\xer_so$14[0:0]$7971 attribute \src "libresoc.v:156153.7-156153.25" wire $0\xer_so$14[0:0]$8084 attribute \src "libresoc.v:156271.3-156306.6" wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8020 attribute \src "libresoc.v:156271.3-156306.6" wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8021 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__imm_data__ok$5$next[0:0]$8022 attribute \src "libresoc.v:156271.3-156306.6" wire width 32 $1\mul_op__insn$13$next[31:0]$8023 attribute \src "libresoc.v:156271.3-156306.6" wire width 7 $1\mul_op__insn_type$2$next[6:0]$8024 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__is_32bit$11$next[0:0]$8025 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__is_signed$12$next[0:0]$8026 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__oe__oe$8$next[0:0]$8027 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__oe__ok$9$next[0:0]$8028 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__rc__ok$7$next[0:0]$8029 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__rc__rc$6$next[0:0]$8030 attribute \src "libresoc.v:156271.3-156306.6" wire $1\mul_op__write_cr0$10$next[0:0]$8031 attribute \src "libresoc.v:156258.3-156270.6" wire width 2 $1\muxid$1$next[1:0]$8006 attribute \src "libresoc.v:156333.3-156345.6" wire $1\neg_res$15$next[0:0]$8046 attribute \src "libresoc.v:156346.3-156358.6" wire $1\neg_res32$16$next[0:0]$8049 attribute \src "libresoc.v:156307.3-156319.6" wire width 129 $1\o$next[128:0]$8040 attribute \src "libresoc.v:156128.15-156128.57" wire width 129 $1\o[128:0] attribute \src "libresoc.v:156240.3-156257.6" wire $1\r_busy$next[0:0]$8002 attribute \src "libresoc.v:156142.7-156142.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:156320.3-156332.6" wire $1\xer_so$14$next[0:0]$8043 attribute \src "libresoc.v:156271.3-156306.6" wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8032 attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__imm_data__ok$5$next[0:0]$8033 attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__oe__oe$8$next[0:0]$8034 attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__oe__ok$9$next[0:0]$8035 attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__rc__ok$7$next[0:0]$8036 attribute \src "libresoc.v:156271.3-156306.6" wire $2\mul_op__rc__rc$6$next[0:0]$8037 attribute \src "libresoc.v:156240.3-156257.6" wire $2\r_busy$next[0:0]$8003 attribute \src "libresoc.v:156158.18-156158.118" wire $and$libresoc.v:156158$7965_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 41 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:155458.7-155458.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul2_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul2_mul_op__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul2_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul2_mul_op__imm_data__data$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__imm_data__ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul2_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul2_mul_op__insn$29 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul2_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul2_mul_op__insn_type$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__is_32bit$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__is_signed$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__oe__oe$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__oe__ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__rc__ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__rc__rc$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul2_mul_op__write_cr0$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul2_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul2_muxid$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire \mul2_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \mul2_neg_res$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire \mul2_neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire \mul2_neg_res32$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul2_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \mul2_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul2_xer_so$30 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 26 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_op__fn_unit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_op__imm_data__data$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 27 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__imm_data__ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 16 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 36 \mul_op__insn$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_op__insn$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_op__insn$48 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 25 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_32bit$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_32bit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_signed$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_signed$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__oe$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__ok$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__rc$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 24 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 23 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 22 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" wire input 20 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire output 39 \neg_res$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \neg_res$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \neg_res$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" wire input 21 \neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire output 40 \neg_res32$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire \neg_res32$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire \neg_res32$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 output 37 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \o$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 17 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 19 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 38 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:156158$7965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o connect \Y $and$libresoc.v:156158$7965_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:156195.8-156231.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 connect \mul_op__insn \mul2_mul_op__insn connect \mul_op__insn$13 \mul2_mul_op__insn$29 connect \mul_op__insn_type \mul2_mul_op__insn_type connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 connect \mul_op__is_32bit \mul2_mul_op__is_32bit connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 connect \mul_op__is_signed \mul2_mul_op__is_signed connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 connect \mul_op__oe__oe \mul2_mul_op__oe__oe connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 connect \mul_op__oe__ok \mul2_mul_op__oe__ok connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 connect \mul_op__rc__ok \mul2_mul_op__rc__ok connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 connect \mul_op__rc__rc \mul2_mul_op__rc__rc connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 connect \muxid \mul2_muxid connect \muxid$1 \mul2_muxid$17 connect \neg_res \mul2_neg_res connect \neg_res$15 \mul2_neg_res$31 connect \neg_res32 \mul2_neg_res32 connect \neg_res32$16 \mul2_neg_res32$32 connect \o \mul2_o connect \ra \mul2_ra connect \rb \mul2_rb connect \xer_so \mul2_xer_so connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 attribute \src "libresoc.v:156232.10-156235.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:156236.10-156239.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:155458.7-155458.20" process $proc$libresoc.v:155458$8050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:155749.14-155749.44" process $proc$libresoc.v:155749$8051 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8052 14'00000000000000 sync always sync init update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8052 end attribute \src "libresoc.v:155775.14-155775.63" process $proc$libresoc.v:155775$8053 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8054 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8054 end attribute \src "libresoc.v:155784.7-155784.38" process $proc$libresoc.v:155784$8055 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8056 1'0 sync always sync init update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8056 end attribute \src "libresoc.v:155791.14-155791.39" process $proc$libresoc.v:155791$8057 assign { } { } assign $0\mul_op__insn$13[31:0]$8058 0 sync always sync init update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8058 end attribute \src "libresoc.v:155950.13-155950.42" process $proc$libresoc.v:155950$8059 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8060 7'0000000 sync always sync init update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8060 end attribute \src "libresoc.v:156034.7-156034.35" process $proc$libresoc.v:156034$8061 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8062 1'0 sync always sync init update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8062 end attribute \src "libresoc.v:156043.7-156043.36" process $proc$libresoc.v:156043$8063 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8064 1'0 sync always sync init update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8064 end attribute \src "libresoc.v:156054.7-156054.32" process $proc$libresoc.v:156054$8065 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8066 1'0 sync always sync init update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8066 end attribute \src "libresoc.v:156063.7-156063.32" process $proc$libresoc.v:156063$8067 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8068 1'0 sync always sync init update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8068 end attribute \src "libresoc.v:156072.7-156072.32" process $proc$libresoc.v:156072$8069 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8070 1'0 sync always sync init update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8070 end attribute \src "libresoc.v:156081.7-156081.32" process $proc$libresoc.v:156081$8071 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8072 1'0 sync always sync init update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8072 end attribute \src "libresoc.v:156088.7-156088.36" process $proc$libresoc.v:156088$8073 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8074 1'0 sync always sync init update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8074 end attribute \src "libresoc.v:156097.13-156097.29" process $proc$libresoc.v:156097$8075 assign { } { } assign $0\muxid$1[1:0]$8076 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8076 end attribute \src "libresoc.v:156112.7-156112.26" process $proc$libresoc.v:156112$8077 assign { } { } assign $0\neg_res$15[0:0]$8078 1'0 sync always sync init update \neg_res$15 $0\neg_res$15[0:0]$8078 end attribute \src "libresoc.v:156121.7-156121.28" process $proc$libresoc.v:156121$8079 assign { } { } assign $0\neg_res32$16[0:0]$8080 1'0 sync always sync init update \neg_res32$16 $0\neg_res32$16[0:0]$8080 end attribute \src "libresoc.v:156128.15-156128.57" process $proc$libresoc.v:156128$8081 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end attribute \src "libresoc.v:156142.7-156142.20" process $proc$libresoc.v:156142$8082 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:156153.7-156153.25" process $proc$libresoc.v:156153$8083 assign { } { } assign $0\xer_so$14[0:0]$8084 1'0 sync always sync init update \xer_so$14 $0\xer_so$14[0:0]$8084 end attribute \src "libresoc.v:156159.3-156160.43" process $proc$libresoc.v:156159$7966 assign { } { } assign $0\neg_res32$16[0:0]$7967 \neg_res32$16$next sync posedge \coresync_clk update \neg_res32$16 $0\neg_res32$16[0:0]$7967 end attribute \src "libresoc.v:156161.3-156162.39" process $proc$libresoc.v:156161$7968 assign { } { } assign $0\neg_res$15[0:0]$7969 \neg_res$15$next sync posedge \coresync_clk update \neg_res$15 $0\neg_res$15[0:0]$7969 end attribute \src "libresoc.v:156163.3-156164.37" process $proc$libresoc.v:156163$7970 assign { } { } assign $0\xer_so$14[0:0]$7971 \xer_so$14$next sync posedge \coresync_clk update \xer_so$14 $0\xer_so$14[0:0]$7971 end attribute \src "libresoc.v:156165.3-156166.19" process $proc$libresoc.v:156165$7972 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end attribute \src "libresoc.v:156167.3-156168.57" process $proc$libresoc.v:156167$7973 assign { } { } assign $0\mul_op__insn_type$2[6:0]$7974 \mul_op__insn_type$2$next sync posedge \coresync_clk update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7974 end attribute \src "libresoc.v:156169.3-156170.53" process $proc$libresoc.v:156169$7975 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$7976 \mul_op__fn_unit$3$next sync posedge \coresync_clk update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$7976 end attribute \src "libresoc.v:156171.3-156172.67" process $proc$libresoc.v:156171$7977 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$7978 \mul_op__imm_data__data$4$next sync posedge \coresync_clk update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7978 end attribute \src "libresoc.v:156173.3-156174.63" process $proc$libresoc.v:156173$7979 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$7980 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7980 end attribute \src "libresoc.v:156175.3-156176.51" process $proc$libresoc.v:156175$7981 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$7982 \mul_op__rc__rc$6$next sync posedge \coresync_clk update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7982 end attribute \src "libresoc.v:156177.3-156178.51" process $proc$libresoc.v:156177$7983 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$7984 \mul_op__rc__ok$7$next sync posedge \coresync_clk update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7984 end attribute \src "libresoc.v:156179.3-156180.51" process $proc$libresoc.v:156179$7985 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$7986 \mul_op__oe__oe$8$next sync posedge \coresync_clk update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7986 end attribute \src "libresoc.v:156181.3-156182.51" process $proc$libresoc.v:156181$7987 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$7988 \mul_op__oe__ok$9$next sync posedge \coresync_clk update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7988 end attribute \src "libresoc.v:156183.3-156184.59" process $proc$libresoc.v:156183$7989 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$7990 \mul_op__write_cr0$10$next sync posedge \coresync_clk update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7990 end attribute \src "libresoc.v:156185.3-156186.57" process $proc$libresoc.v:156185$7991 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$7992 \mul_op__is_32bit$11$next sync posedge \coresync_clk update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7992 end attribute \src "libresoc.v:156187.3-156188.59" process $proc$libresoc.v:156187$7993 assign { } { } assign $0\mul_op__is_signed$12[0:0]$7994 \mul_op__is_signed$12$next sync posedge \coresync_clk update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7994 end attribute \src "libresoc.v:156189.3-156190.49" process $proc$libresoc.v:156189$7995 assign { } { } assign $0\mul_op__insn$13[31:0]$7996 \mul_op__insn$13$next sync posedge \coresync_clk update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7996 end attribute \src "libresoc.v:156191.3-156192.33" process $proc$libresoc.v:156191$7997 assign { } { } assign $0\muxid$1[1:0]$7998 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$7998 end attribute \src "libresoc.v:156193.3-156194.29" process $proc$libresoc.v:156193$7999 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:156240.3-156257.6" process $proc$libresoc.v:156240$8000 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8001 $2\r_busy$next[0:0]$8003 attribute \src "libresoc.v:156241.5-156241.29" switch \initial attribute \src "libresoc.v:156241.9-156241.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$8002 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$8002 1'0 case assign $1\r_busy$next[0:0]$8002 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$8003 1'0 case assign $2\r_busy$next[0:0]$8003 $1\r_busy$next[0:0]$8002 end sync always update \r_busy$next $0\r_busy$next[0:0]$8001 end attribute \src "libresoc.v:156258.3-156270.6" process $proc$libresoc.v:156258$8004 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8005 $1\muxid$1$next[1:0]$8006 attribute \src "libresoc.v:156259.5-156259.29" switch \initial attribute \src "libresoc.v:156259.9-156259.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$8006 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$8006 \muxid$36 case assign $1\muxid$1$next[1:0]$8006 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$8005 end attribute \src "libresoc.v:156271.3-156306.6" process $proc$libresoc.v:156271$8007 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\mul_op__fn_unit$3$next[13:0]$8008 $1\mul_op__fn_unit$3$next[13:0]$8020 assign { } { } assign { } { } assign $0\mul_op__insn$13$next[31:0]$8011 $1\mul_op__insn$13$next[31:0]$8023 assign $0\mul_op__insn_type$2$next[6:0]$8012 $1\mul_op__insn_type$2$next[6:0]$8024 assign $0\mul_op__is_32bit$11$next[0:0]$8013 $1\mul_op__is_32bit$11$next[0:0]$8025 assign $0\mul_op__is_signed$12$next[0:0]$8014 $1\mul_op__is_signed$12$next[0:0]$8026 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\mul_op__write_cr0$10$next[0:0]$8019 $1\mul_op__write_cr0$10$next[0:0]$8031 assign $0\mul_op__imm_data__data$4$next[63:0]$8009 $2\mul_op__imm_data__data$4$next[63:0]$8032 assign $0\mul_op__imm_data__ok$5$next[0:0]$8010 $2\mul_op__imm_data__ok$5$next[0:0]$8033 assign $0\mul_op__oe__oe$8$next[0:0]$8015 $2\mul_op__oe__oe$8$next[0:0]$8034 assign $0\mul_op__oe__ok$9$next[0:0]$8016 $2\mul_op__oe__ok$9$next[0:0]$8035 assign $0\mul_op__rc__ok$7$next[0:0]$8017 $2\mul_op__rc__ok$7$next[0:0]$8036 assign $0\mul_op__rc__rc$6$next[0:0]$8018 $2\mul_op__rc__rc$6$next[0:0]$8037 attribute \src "libresoc.v:156272.5-156272.29" switch \initial attribute \src "libresoc.v:156272.9-156272.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\mul_op__insn$13$next[31:0]$8023 $1\mul_op__is_signed$12$next[0:0]$8026 $1\mul_op__is_32bit$11$next[0:0]$8025 $1\mul_op__write_cr0$10$next[0:0]$8031 $1\mul_op__oe__ok$9$next[0:0]$8028 $1\mul_op__oe__oe$8$next[0:0]$8027 $1\mul_op__rc__ok$7$next[0:0]$8029 $1\mul_op__rc__rc$6$next[0:0]$8030 $1\mul_op__imm_data__ok$5$next[0:0]$8022 $1\mul_op__imm_data__data$4$next[63:0]$8021 $1\mul_op__fn_unit$3$next[13:0]$8020 $1\mul_op__insn_type$2$next[6:0]$8024 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\mul_op__insn$13$next[31:0]$8023 $1\mul_op__is_signed$12$next[0:0]$8026 $1\mul_op__is_32bit$11$next[0:0]$8025 $1\mul_op__write_cr0$10$next[0:0]$8031 $1\mul_op__oe__ok$9$next[0:0]$8028 $1\mul_op__oe__oe$8$next[0:0]$8027 $1\mul_op__rc__ok$7$next[0:0]$8029 $1\mul_op__rc__rc$6$next[0:0]$8030 $1\mul_op__imm_data__ok$5$next[0:0]$8022 $1\mul_op__imm_data__data$4$next[63:0]$8021 $1\mul_op__fn_unit$3$next[13:0]$8020 $1\mul_op__insn_type$2$next[6:0]$8024 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case assign $1\mul_op__fn_unit$3$next[13:0]$8020 \mul_op__fn_unit$3 assign $1\mul_op__imm_data__data$4$next[63:0]$8021 \mul_op__imm_data__data$4 assign $1\mul_op__imm_data__ok$5$next[0:0]$8022 \mul_op__imm_data__ok$5 assign $1\mul_op__insn$13$next[31:0]$8023 \mul_op__insn$13 assign $1\mul_op__insn_type$2$next[6:0]$8024 \mul_op__insn_type$2 assign $1\mul_op__is_32bit$11$next[0:0]$8025 \mul_op__is_32bit$11 assign $1\mul_op__is_signed$12$next[0:0]$8026 \mul_op__is_signed$12 assign $1\mul_op__oe__oe$8$next[0:0]$8027 \mul_op__oe__oe$8 assign $1\mul_op__oe__ok$9$next[0:0]$8028 \mul_op__oe__ok$9 assign $1\mul_op__rc__ok$7$next[0:0]$8029 \mul_op__rc__ok$7 assign $1\mul_op__rc__rc$6$next[0:0]$8030 \mul_op__rc__rc$6 assign $1\mul_op__write_cr0$10$next[0:0]$8031 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\mul_op__imm_data__data$4$next[63:0]$8032 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\mul_op__imm_data__ok$5$next[0:0]$8033 1'0 assign $2\mul_op__rc__rc$6$next[0:0]$8037 1'0 assign $2\mul_op__rc__ok$7$next[0:0]$8036 1'0 assign $2\mul_op__oe__oe$8$next[0:0]$8034 1'0 assign $2\mul_op__oe__ok$9$next[0:0]$8035 1'0 case assign $2\mul_op__imm_data__data$4$next[63:0]$8032 $1\mul_op__imm_data__data$4$next[63:0]$8021 assign $2\mul_op__imm_data__ok$5$next[0:0]$8033 $1\mul_op__imm_data__ok$5$next[0:0]$8022 assign $2\mul_op__oe__oe$8$next[0:0]$8034 $1\mul_op__oe__oe$8$next[0:0]$8027 assign $2\mul_op__oe__ok$9$next[0:0]$8035 $1\mul_op__oe__ok$9$next[0:0]$8028 assign $2\mul_op__rc__ok$7$next[0:0]$8036 $1\mul_op__rc__ok$7$next[0:0]$8029 assign $2\mul_op__rc__rc$6$next[0:0]$8037 $1\mul_op__rc__rc$6$next[0:0]$8030 end sync always update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8008 update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8009 update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8010 update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8011 update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8012 update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8013 update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8014 update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8015 update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8016 update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8017 update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8018 update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8019 end attribute \src "libresoc.v:156307.3-156319.6" process $proc$libresoc.v:156307$8038 assign { } { } assign { } { } assign $0\o$next[128:0]$8039 $1\o$next[128:0]$8040 attribute \src "libresoc.v:156308.5-156308.29" switch \initial attribute \src "libresoc.v:156308.9-156308.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\o$next[128:0]$8040 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\o$next[128:0]$8040 \o$49 case assign $1\o$next[128:0]$8040 \o end sync always update \o$next $0\o$next[128:0]$8039 end attribute \src "libresoc.v:156320.3-156332.6" process $proc$libresoc.v:156320$8041 assign { } { } assign { } { } assign $0\xer_so$14$next[0:0]$8042 $1\xer_so$14$next[0:0]$8043 attribute \src "libresoc.v:156321.5-156321.29" switch \initial attribute \src "libresoc.v:156321.9-156321.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\xer_so$14$next[0:0]$8043 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\xer_so$14$next[0:0]$8043 \xer_so$50 case assign $1\xer_so$14$next[0:0]$8043 \xer_so$14 end sync always update \xer_so$14$next $0\xer_so$14$next[0:0]$8042 end attribute \src "libresoc.v:156333.3-156345.6" process $proc$libresoc.v:156333$8044 assign { } { } assign { } { } assign $0\neg_res$15$next[0:0]$8045 $1\neg_res$15$next[0:0]$8046 attribute \src "libresoc.v:156334.5-156334.29" switch \initial attribute \src "libresoc.v:156334.9-156334.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\neg_res$15$next[0:0]$8046 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\neg_res$15$next[0:0]$8046 \neg_res$51 case assign $1\neg_res$15$next[0:0]$8046 \neg_res$15 end sync always update \neg_res$15$next $0\neg_res$15$next[0:0]$8045 end attribute \src "libresoc.v:156346.3-156358.6" process $proc$libresoc.v:156346$8047 assign { } { } assign { } { } assign $0\neg_res32$16$next[0:0]$8048 $1\neg_res32$16$next[0:0]$8049 attribute \src "libresoc.v:156347.5-156347.29" switch \initial attribute \src "libresoc.v:156347.9-156347.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$52 case assign $1\neg_res32$16$next[0:0]$8049 \neg_res32$16 end sync always update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8048 end connect \$34 $and$libresoc.v:156158$7965_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 connect \neg_res$51 \mul2_neg_res$31 connect \xer_so$50 \mul2_xer_so$30 connect \o$49 \mul2_o connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } connect \muxid$36 \mul2_muxid$17 connect \p_valid_i_p_ready_o \$34 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$33 \p_valid_i connect \mul2_neg_res32 \neg_res32 connect \mul2_neg_res \neg_res connect \mul2_xer_so \xer_so connect \mul2_rb \rb connect \mul2_ra \ra connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end attribute \src "libresoc.v:156381.1-157677.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 attribute \src "libresoc.v:157595.3-157613.6" wire width 4 $0\cr_a$next[3:0]$8168 attribute \src "libresoc.v:157387.3-157388.25" wire width 4 $0\cr_a[3:0] attribute \src "libresoc.v:157595.3-157613.6" wire $0\cr_a_ok$next[0:0]$8169 attribute \src "libresoc.v:157389.3-157390.31" wire $0\cr_a_ok[0:0] attribute \src "libresoc.v:156382.7-156382.20" wire $0\initial[0:0] attribute \src "libresoc.v:157540.3-157575.6" wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8131 attribute \src "libresoc.v:157397.3-157398.53" wire width 14 $0\mul_op__fn_unit$3[13:0]$8099 attribute \src "libresoc.v:156693.14-156693.44" wire width 14 $0\mul_op__fn_unit$3[13:0]$8189 attribute \src "libresoc.v:157540.3-157575.6" wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8132 attribute \src "libresoc.v:157399.3-157400.67" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8101 attribute \src "libresoc.v:156717.14-156717.63" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8191 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__imm_data__ok$5$next[0:0]$8133 attribute \src "libresoc.v:157401.3-157402.63" wire $0\mul_op__imm_data__ok$5[0:0]$8103 attribute \src "libresoc.v:156726.7-156726.38" wire $0\mul_op__imm_data__ok$5[0:0]$8193 attribute \src "libresoc.v:157540.3-157575.6" wire width 32 $0\mul_op__insn$13$next[31:0]$8134 attribute \src "libresoc.v:157417.3-157418.49" wire width 32 $0\mul_op__insn$13[31:0]$8119 attribute \src "libresoc.v:156735.14-156735.39" wire width 32 $0\mul_op__insn$13[31:0]$8195 attribute \src "libresoc.v:157540.3-157575.6" wire width 7 $0\mul_op__insn_type$2$next[6:0]$8135 attribute \src "libresoc.v:157395.3-157396.57" wire width 7 $0\mul_op__insn_type$2[6:0]$8097 attribute \src "libresoc.v:156894.13-156894.42" wire width 7 $0\mul_op__insn_type$2[6:0]$8197 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__is_32bit$11$next[0:0]$8136 attribute \src "libresoc.v:157413.3-157414.57" wire $0\mul_op__is_32bit$11[0:0]$8115 attribute \src "libresoc.v:156978.7-156978.35" wire $0\mul_op__is_32bit$11[0:0]$8199 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__is_signed$12$next[0:0]$8137 attribute \src "libresoc.v:157415.3-157416.59" wire $0\mul_op__is_signed$12[0:0]$8117 attribute \src "libresoc.v:156987.7-156987.36" wire $0\mul_op__is_signed$12[0:0]$8201 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__oe__oe$8$next[0:0]$8138 attribute \src "libresoc.v:157407.3-157408.51" wire $0\mul_op__oe__oe$8[0:0]$8109 attribute \src "libresoc.v:156998.7-156998.32" wire $0\mul_op__oe__oe$8[0:0]$8203 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__oe__ok$9$next[0:0]$8139 attribute \src "libresoc.v:157409.3-157410.51" wire $0\mul_op__oe__ok$9[0:0]$8111 attribute \src "libresoc.v:157007.7-157007.32" wire $0\mul_op__oe__ok$9[0:0]$8205 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__rc__ok$7$next[0:0]$8140 attribute \src "libresoc.v:157405.3-157406.51" wire $0\mul_op__rc__ok$7[0:0]$8107 attribute \src "libresoc.v:157016.7-157016.32" wire $0\mul_op__rc__ok$7[0:0]$8207 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__rc__rc$6$next[0:0]$8141 attribute \src "libresoc.v:157403.3-157404.51" wire $0\mul_op__rc__rc$6[0:0]$8105 attribute \src "libresoc.v:157023.7-157023.32" wire $0\mul_op__rc__rc$6[0:0]$8209 attribute \src "libresoc.v:157540.3-157575.6" wire $0\mul_op__write_cr0$10$next[0:0]$8142 attribute \src "libresoc.v:157411.3-157412.59" wire $0\mul_op__write_cr0$10[0:0]$8113 attribute \src "libresoc.v:157032.7-157032.36" wire $0\mul_op__write_cr0$10[0:0]$8211 attribute \src "libresoc.v:157527.3-157539.6" wire width 2 $0\muxid$1$next[1:0]$8128 attribute \src "libresoc.v:157419.3-157420.33" wire width 2 $0\muxid$1[1:0]$8121 attribute \src "libresoc.v:157041.13-157041.29" wire width 2 $0\muxid$1[1:0]$8213 attribute \src "libresoc.v:157576.3-157594.6" wire width 64 $0\o$14$next[63:0]$8163 attribute \src "libresoc.v:157391.3-157392.27" wire width 64 $0\o$14[63:0]$8094 attribute \src "libresoc.v:157062.14-157062.43" wire width 64 $0\o$14[63:0]$8215 attribute \src "libresoc.v:157576.3-157594.6" wire $0\o_ok$next[0:0]$8162 attribute \src "libresoc.v:157393.3-157394.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:157509.3-157526.6" wire $0\r_busy$next[0:0]$8124 attribute \src "libresoc.v:157421.3-157422.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:157614.3-157632.6" wire width 2 $0\xer_ov$next[1:0]$8174 attribute \src "libresoc.v:157383.3-157384.29" wire width 2 $0\xer_ov[1:0] attribute \src "libresoc.v:157614.3-157632.6" wire $0\xer_ov_ok$next[0:0]$8175 attribute \src "libresoc.v:157385.3-157386.35" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:157633.3-157651.6" wire $0\xer_so$15$next[0:0]$8181 attribute \src "libresoc.v:157379.3-157380.37" wire $0\xer_so$15[0:0]$8087 attribute \src "libresoc.v:157364.7-157364.25" wire $0\xer_so$15[0:0]$8221 attribute \src "libresoc.v:157633.3-157651.6" wire $0\xer_so_ok$next[0:0]$8180 attribute \src "libresoc.v:157381.3-157382.35" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:157595.3-157613.6" wire width 4 $1\cr_a$next[3:0]$8170 attribute \src "libresoc.v:156391.13-156391.24" wire width 4 $1\cr_a[3:0] attribute \src "libresoc.v:157595.3-157613.6" wire $1\cr_a_ok$next[0:0]$8171 attribute \src "libresoc.v:156400.7-156400.21" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:157540.3-157575.6" wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8143 attribute \src "libresoc.v:157540.3-157575.6" wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8144 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__imm_data__ok$5$next[0:0]$8145 attribute \src "libresoc.v:157540.3-157575.6" wire width 32 $1\mul_op__insn$13$next[31:0]$8146 attribute \src "libresoc.v:157540.3-157575.6" wire width 7 $1\mul_op__insn_type$2$next[6:0]$8147 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__is_32bit$11$next[0:0]$8148 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__is_signed$12$next[0:0]$8149 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__oe__oe$8$next[0:0]$8150 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__oe__ok$9$next[0:0]$8151 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__rc__ok$7$next[0:0]$8152 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__rc__rc$6$next[0:0]$8153 attribute \src "libresoc.v:157540.3-157575.6" wire $1\mul_op__write_cr0$10$next[0:0]$8154 attribute \src "libresoc.v:157527.3-157539.6" wire width 2 $1\muxid$1$next[1:0]$8129 attribute \src "libresoc.v:157576.3-157594.6" wire width 64 $1\o$14$next[63:0]$8165 attribute \src "libresoc.v:157576.3-157594.6" wire $1\o_ok$next[0:0]$8164 attribute \src "libresoc.v:157069.7-157069.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:157509.3-157526.6" wire $1\r_busy$next[0:0]$8125 attribute \src "libresoc.v:157341.7-157341.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:157614.3-157632.6" wire width 2 $1\xer_ov$next[1:0]$8176 attribute \src "libresoc.v:157346.13-157346.26" wire width 2 $1\xer_ov[1:0] attribute \src "libresoc.v:157614.3-157632.6" wire $1\xer_ov_ok$next[0:0]$8177 attribute \src "libresoc.v:157353.7-157353.23" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:157633.3-157651.6" wire $1\xer_so$15$next[0:0]$8183 attribute \src "libresoc.v:157633.3-157651.6" wire $1\xer_so_ok$next[0:0]$8182 attribute \src "libresoc.v:157371.7-157371.23" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:157595.3-157613.6" wire $2\cr_a_ok$next[0:0]$8172 attribute \src "libresoc.v:157540.3-157575.6" wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8155 attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__imm_data__ok$5$next[0:0]$8156 attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__oe__oe$8$next[0:0]$8157 attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__oe__ok$9$next[0:0]$8158 attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__rc__ok$7$next[0:0]$8159 attribute \src "libresoc.v:157540.3-157575.6" wire $2\mul_op__rc__rc$6$next[0:0]$8160 attribute \src "libresoc.v:157576.3-157594.6" wire $2\o_ok$next[0:0]$8166 attribute \src "libresoc.v:157509.3-157526.6" wire $2\r_busy$next[0:0]$8126 attribute \src "libresoc.v:157614.3-157632.6" wire $2\xer_ov_ok$next[0:0]$8178 attribute \src "libresoc.v:157633.3-157651.6" wire $2\xer_so_ok$next[0:0]$8184 attribute \src "libresoc.v:157378.18-157378.118" wire $and$libresoc.v:157378$8085_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 44 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 38 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "libresoc.v:156382.7-156382.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul3_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul3_mul_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul3_mul_op__imm_data__data$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__imm_data__ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul3_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul3_mul_op__insn$28 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul3_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul3_mul_op__insn_type$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__is_32bit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__is_signed$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__oe__oe$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__oe__ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__rc__ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__rc__rc$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul3_mul_op__write_cr0$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul3_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \mul3_muxid$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire \mul3_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \mul3_o$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \mul3_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul3_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_xer_so$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \mul3_xer_so_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 25 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \mul_op__fn_unit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 26 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \mul_op__imm_data__data$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__imm_data__ok$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 16 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 35 \mul_op__insn$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_op__insn$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \mul_op__insn$70 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \mul_op__insn_type$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_32bit$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_signed$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__oe$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__ok$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__ok$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__rc__rc$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \mul_op__write_cr0$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 22 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 21 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" wire input 19 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire input 20 \neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" wire \neg_res32$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 input 17 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 36 \o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_mul_op__fn_unit$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_mul_op__imm_data__data$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__imm_data__ok$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_mul_op__insn$43 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_mul_op__insn_type$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__is_32bit$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__is_signed$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__oe__oe$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__oe__ok$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__rc__ok$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__rc__rc$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_mul_op__write_cr0$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 40 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 41 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 18 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \xer_so$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:157378$8085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o connect \Y $and$libresoc.v:157378$8085_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:157423.8-157459.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 connect \mul_op__insn \mul3_mul_op__insn connect \mul_op__insn$13 \mul3_mul_op__insn$28 connect \mul_op__insn_type \mul3_mul_op__insn_type connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 connect \mul_op__is_32bit \mul3_mul_op__is_32bit connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 connect \mul_op__is_signed \mul3_mul_op__is_signed connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 connect \mul_op__oe__oe \mul3_mul_op__oe__oe connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 connect \mul_op__oe__ok \mul3_mul_op__oe__ok connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 connect \mul_op__rc__ok \mul3_mul_op__rc__ok connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 connect \mul_op__rc__rc \mul3_mul_op__rc__rc connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 connect \muxid \mul3_muxid connect \muxid$1 \mul3_muxid$16 connect \neg_res \mul3_neg_res connect \o \mul3_o connect \o$14 \mul3_o$29 connect \o_ok \mul3_o_ok connect \xer_ov \mul3_xer_ov connect \xer_ov_ok \mul3_xer_ov_ok connect \xer_so \mul3_xer_so connect \xer_so$15 \mul3_xer_so$30 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:157460.10-157463.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:157464.16-157504.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 connect \cr_a_ok \output_cr_a_ok connect \mul_op__fn_unit \output_mul_op__fn_unit connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 connect \mul_op__imm_data__data \output_mul_op__imm_data__data connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 connect \mul_op__insn \output_mul_op__insn connect \mul_op__insn$13 \output_mul_op__insn$43 connect \mul_op__insn_type \output_mul_op__insn_type connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 connect \mul_op__is_32bit \output_mul_op__is_32bit connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 connect \mul_op__is_signed \output_mul_op__is_signed connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 connect \mul_op__oe__oe \output_mul_op__oe__oe connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 connect \mul_op__oe__ok \output_mul_op__oe__ok connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 connect \mul_op__rc__ok \output_mul_op__rc__ok connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 connect \mul_op__rc__rc \output_mul_op__rc__rc connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 connect \mul_op__write_cr0 \output_mul_op__write_cr0 connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 connect \muxid \output_muxid connect \muxid$1 \output_muxid$31 connect \o \output_o connect \o$14 \output_o$44 connect \o_ok \output_o_ok connect \o_ok$15 \output_o_ok$45 connect \xer_ov \output_xer_ov connect \xer_ov$17 \output_xer_ov$47 connect \xer_ov_ok \output_xer_ov_ok connect \xer_so \output_xer_so connect \xer_so$18 \output_xer_so$48 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:157505.10-157508.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:156382.7-156382.20" process $proc$libresoc.v:156382$8185 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:156391.13-156391.24" process $proc$libresoc.v:156391$8186 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end attribute \src "libresoc.v:156400.7-156400.21" process $proc$libresoc.v:156400$8187 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end attribute \src "libresoc.v:156693.14-156693.44" process $proc$libresoc.v:156693$8188 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8189 14'00000000000000 sync always sync init update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8189 end attribute \src "libresoc.v:156717.14-156717.63" process $proc$libresoc.v:156717$8190 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8191 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8191 end attribute \src "libresoc.v:156726.7-156726.38" process $proc$libresoc.v:156726$8192 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8193 1'0 sync always sync init update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8193 end attribute \src "libresoc.v:156735.14-156735.39" process $proc$libresoc.v:156735$8194 assign { } { } assign $0\mul_op__insn$13[31:0]$8195 0 sync always sync init update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8195 end attribute \src "libresoc.v:156894.13-156894.42" process $proc$libresoc.v:156894$8196 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8197 7'0000000 sync always sync init update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8197 end attribute \src "libresoc.v:156978.7-156978.35" process $proc$libresoc.v:156978$8198 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8199 1'0 sync always sync init update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8199 end attribute \src "libresoc.v:156987.7-156987.36" process $proc$libresoc.v:156987$8200 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8201 1'0 sync always sync init update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8201 end attribute \src "libresoc.v:156998.7-156998.32" process $proc$libresoc.v:156998$8202 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8203 1'0 sync always sync init update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8203 end attribute \src "libresoc.v:157007.7-157007.32" process $proc$libresoc.v:157007$8204 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8205 1'0 sync always sync init update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8205 end attribute \src "libresoc.v:157016.7-157016.32" process $proc$libresoc.v:157016$8206 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8207 1'0 sync always sync init update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8207 end attribute \src "libresoc.v:157023.7-157023.32" process $proc$libresoc.v:157023$8208 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8209 1'0 sync always sync init update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8209 end attribute \src "libresoc.v:157032.7-157032.36" process $proc$libresoc.v:157032$8210 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8211 1'0 sync always sync init update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8211 end attribute \src "libresoc.v:157041.13-157041.29" process $proc$libresoc.v:157041$8212 assign { } { } assign $0\muxid$1[1:0]$8213 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8213 end attribute \src "libresoc.v:157062.14-157062.43" process $proc$libresoc.v:157062$8214 assign { } { } assign $0\o$14[63:0]$8215 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$14 $0\o$14[63:0]$8215 end attribute \src "libresoc.v:157069.7-157069.18" process $proc$libresoc.v:157069$8216 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:157341.7-157341.20" process $proc$libresoc.v:157341$8217 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:157346.13-157346.26" process $proc$libresoc.v:157346$8218 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end attribute \src "libresoc.v:157353.7-157353.23" process $proc$libresoc.v:157353$8219 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end attribute \src "libresoc.v:157364.7-157364.25" process $proc$libresoc.v:157364$8220 assign { } { } assign $0\xer_so$15[0:0]$8221 1'0 sync always sync init update \xer_so$15 $0\xer_so$15[0:0]$8221 end attribute \src "libresoc.v:157371.7-157371.23" process $proc$libresoc.v:157371$8222 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end attribute \src "libresoc.v:157379.3-157380.37" process $proc$libresoc.v:157379$8086 assign { } { } assign $0\xer_so$15[0:0]$8087 \xer_so$15$next sync posedge \coresync_clk update \xer_so$15 $0\xer_so$15[0:0]$8087 end attribute \src "libresoc.v:157381.3-157382.35" process $proc$libresoc.v:157381$8088 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:157383.3-157384.29" process $proc$libresoc.v:157383$8089 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end attribute \src "libresoc.v:157385.3-157386.35" process $proc$libresoc.v:157385$8090 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end attribute \src "libresoc.v:157387.3-157388.25" process $proc$libresoc.v:157387$8091 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end attribute \src "libresoc.v:157389.3-157390.31" process $proc$libresoc.v:157389$8092 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end attribute \src "libresoc.v:157391.3-157392.27" process $proc$libresoc.v:157391$8093 assign { } { } assign $0\o$14[63:0]$8094 \o$14$next sync posedge \coresync_clk update \o$14 $0\o$14[63:0]$8094 end attribute \src "libresoc.v:157393.3-157394.25" process $proc$libresoc.v:157393$8095 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:157395.3-157396.57" process $proc$libresoc.v:157395$8096 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8097 \mul_op__insn_type$2$next sync posedge \coresync_clk update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8097 end attribute \src "libresoc.v:157397.3-157398.53" process $proc$libresoc.v:157397$8098 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8099 \mul_op__fn_unit$3$next sync posedge \coresync_clk update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8099 end attribute \src "libresoc.v:157399.3-157400.67" process $proc$libresoc.v:157399$8100 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8101 \mul_op__imm_data__data$4$next sync posedge \coresync_clk update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8101 end attribute \src "libresoc.v:157401.3-157402.63" process $proc$libresoc.v:157401$8102 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8103 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8103 end attribute \src "libresoc.v:157403.3-157404.51" process $proc$libresoc.v:157403$8104 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8105 \mul_op__rc__rc$6$next sync posedge \coresync_clk update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8105 end attribute \src "libresoc.v:157405.3-157406.51" process $proc$libresoc.v:157405$8106 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8107 \mul_op__rc__ok$7$next sync posedge \coresync_clk update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8107 end attribute \src "libresoc.v:157407.3-157408.51" process $proc$libresoc.v:157407$8108 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8109 \mul_op__oe__oe$8$next sync posedge \coresync_clk update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8109 end attribute \src "libresoc.v:157409.3-157410.51" process $proc$libresoc.v:157409$8110 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8111 \mul_op__oe__ok$9$next sync posedge \coresync_clk update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8111 end attribute \src "libresoc.v:157411.3-157412.59" process $proc$libresoc.v:157411$8112 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8113 \mul_op__write_cr0$10$next sync posedge \coresync_clk update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8113 end attribute \src "libresoc.v:157413.3-157414.57" process $proc$libresoc.v:157413$8114 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8115 \mul_op__is_32bit$11$next sync posedge \coresync_clk update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8115 end attribute \src "libresoc.v:157415.3-157416.59" process $proc$libresoc.v:157415$8116 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8117 \mul_op__is_signed$12$next sync posedge \coresync_clk update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8117 end attribute \src "libresoc.v:157417.3-157418.49" process $proc$libresoc.v:157417$8118 assign { } { } assign $0\mul_op__insn$13[31:0]$8119 \mul_op__insn$13$next sync posedge \coresync_clk update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8119 end attribute \src "libresoc.v:157419.3-157420.33" process $proc$libresoc.v:157419$8120 assign { } { } assign $0\muxid$1[1:0]$8121 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8121 end attribute \src "libresoc.v:157421.3-157422.29" process $proc$libresoc.v:157421$8122 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:157509.3-157526.6" process $proc$libresoc.v:157509$8123 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8124 $2\r_busy$next[0:0]$8126 attribute \src "libresoc.v:157510.5-157510.29" switch \initial attribute \src "libresoc.v:157510.9-157510.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$8125 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$8125 1'0 case assign $1\r_busy$next[0:0]$8125 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$8126 1'0 case assign $2\r_busy$next[0:0]$8126 $1\r_busy$next[0:0]$8125 end sync always update \r_busy$next $0\r_busy$next[0:0]$8124 end attribute \src "libresoc.v:157527.3-157539.6" process $proc$libresoc.v:157527$8127 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8128 $1\muxid$1$next[1:0]$8129 attribute \src "libresoc.v:157528.5-157528.29" switch \initial attribute \src "libresoc.v:157528.9-157528.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$8129 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$8129 \muxid$58 case assign $1\muxid$1$next[1:0]$8129 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$8128 end attribute \src "libresoc.v:157540.3-157575.6" process $proc$libresoc.v:157540$8130 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\mul_op__fn_unit$3$next[13:0]$8131 $1\mul_op__fn_unit$3$next[13:0]$8143 assign { } { } assign { } { } assign $0\mul_op__insn$13$next[31:0]$8134 $1\mul_op__insn$13$next[31:0]$8146 assign $0\mul_op__insn_type$2$next[6:0]$8135 $1\mul_op__insn_type$2$next[6:0]$8147 assign $0\mul_op__is_32bit$11$next[0:0]$8136 $1\mul_op__is_32bit$11$next[0:0]$8148 assign $0\mul_op__is_signed$12$next[0:0]$8137 $1\mul_op__is_signed$12$next[0:0]$8149 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\mul_op__write_cr0$10$next[0:0]$8142 $1\mul_op__write_cr0$10$next[0:0]$8154 assign $0\mul_op__imm_data__data$4$next[63:0]$8132 $2\mul_op__imm_data__data$4$next[63:0]$8155 assign $0\mul_op__imm_data__ok$5$next[0:0]$8133 $2\mul_op__imm_data__ok$5$next[0:0]$8156 assign $0\mul_op__oe__oe$8$next[0:0]$8138 $2\mul_op__oe__oe$8$next[0:0]$8157 assign $0\mul_op__oe__ok$9$next[0:0]$8139 $2\mul_op__oe__ok$9$next[0:0]$8158 assign $0\mul_op__rc__ok$7$next[0:0]$8140 $2\mul_op__rc__ok$7$next[0:0]$8159 assign $0\mul_op__rc__rc$6$next[0:0]$8141 $2\mul_op__rc__rc$6$next[0:0]$8160 attribute \src "libresoc.v:157541.5-157541.29" switch \initial attribute \src "libresoc.v:157541.9-157541.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\mul_op__insn$13$next[31:0]$8146 $1\mul_op__is_signed$12$next[0:0]$8149 $1\mul_op__is_32bit$11$next[0:0]$8148 $1\mul_op__write_cr0$10$next[0:0]$8154 $1\mul_op__oe__ok$9$next[0:0]$8151 $1\mul_op__oe__oe$8$next[0:0]$8150 $1\mul_op__rc__ok$7$next[0:0]$8152 $1\mul_op__rc__rc$6$next[0:0]$8153 $1\mul_op__imm_data__ok$5$next[0:0]$8145 $1\mul_op__imm_data__data$4$next[63:0]$8144 $1\mul_op__fn_unit$3$next[13:0]$8143 $1\mul_op__insn_type$2$next[6:0]$8147 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\mul_op__insn$13$next[31:0]$8146 $1\mul_op__is_signed$12$next[0:0]$8149 $1\mul_op__is_32bit$11$next[0:0]$8148 $1\mul_op__write_cr0$10$next[0:0]$8154 $1\mul_op__oe__ok$9$next[0:0]$8151 $1\mul_op__oe__oe$8$next[0:0]$8150 $1\mul_op__rc__ok$7$next[0:0]$8152 $1\mul_op__rc__rc$6$next[0:0]$8153 $1\mul_op__imm_data__ok$5$next[0:0]$8145 $1\mul_op__imm_data__data$4$next[63:0]$8144 $1\mul_op__fn_unit$3$next[13:0]$8143 $1\mul_op__insn_type$2$next[6:0]$8147 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case assign $1\mul_op__fn_unit$3$next[13:0]$8143 \mul_op__fn_unit$3 assign $1\mul_op__imm_data__data$4$next[63:0]$8144 \mul_op__imm_data__data$4 assign $1\mul_op__imm_data__ok$5$next[0:0]$8145 \mul_op__imm_data__ok$5 assign $1\mul_op__insn$13$next[31:0]$8146 \mul_op__insn$13 assign $1\mul_op__insn_type$2$next[6:0]$8147 \mul_op__insn_type$2 assign $1\mul_op__is_32bit$11$next[0:0]$8148 \mul_op__is_32bit$11 assign $1\mul_op__is_signed$12$next[0:0]$8149 \mul_op__is_signed$12 assign $1\mul_op__oe__oe$8$next[0:0]$8150 \mul_op__oe__oe$8 assign $1\mul_op__oe__ok$9$next[0:0]$8151 \mul_op__oe__ok$9 assign $1\mul_op__rc__ok$7$next[0:0]$8152 \mul_op__rc__ok$7 assign $1\mul_op__rc__rc$6$next[0:0]$8153 \mul_op__rc__rc$6 assign $1\mul_op__write_cr0$10$next[0:0]$8154 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\mul_op__imm_data__data$4$next[63:0]$8155 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\mul_op__imm_data__ok$5$next[0:0]$8156 1'0 assign $2\mul_op__rc__rc$6$next[0:0]$8160 1'0 assign $2\mul_op__rc__ok$7$next[0:0]$8159 1'0 assign $2\mul_op__oe__oe$8$next[0:0]$8157 1'0 assign $2\mul_op__oe__ok$9$next[0:0]$8158 1'0 case assign $2\mul_op__imm_data__data$4$next[63:0]$8155 $1\mul_op__imm_data__data$4$next[63:0]$8144 assign $2\mul_op__imm_data__ok$5$next[0:0]$8156 $1\mul_op__imm_data__ok$5$next[0:0]$8145 assign $2\mul_op__oe__oe$8$next[0:0]$8157 $1\mul_op__oe__oe$8$next[0:0]$8150 assign $2\mul_op__oe__ok$9$next[0:0]$8158 $1\mul_op__oe__ok$9$next[0:0]$8151 assign $2\mul_op__rc__ok$7$next[0:0]$8159 $1\mul_op__rc__ok$7$next[0:0]$8152 assign $2\mul_op__rc__rc$6$next[0:0]$8160 $1\mul_op__rc__rc$6$next[0:0]$8153 end sync always update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8131 update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8132 update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8133 update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8134 update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8135 update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8136 update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8137 update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8138 update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8139 update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8140 update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8141 update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8142 end attribute \src "libresoc.v:157576.3-157594.6" process $proc$libresoc.v:157576$8161 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$14$next[63:0]$8163 $1\o$14$next[63:0]$8165 assign $0\o_ok$next[0:0]$8162 $2\o_ok$next[0:0]$8166 attribute \src "libresoc.v:157577.5-157577.29" switch \initial attribute \src "libresoc.v:157577.9-157577.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$8164 $1\o$14$next[63:0]$8165 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$8164 $1\o$14$next[63:0]$8165 } { \o_ok$72 \o$71 } case assign $1\o_ok$next[0:0]$8164 \o_ok assign $1\o$14$next[63:0]$8165 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$8166 1'0 case assign $2\o_ok$next[0:0]$8166 $1\o_ok$next[0:0]$8164 end sync always update \o_ok$next $0\o_ok$next[0:0]$8162 update \o$14$next $0\o$14$next[63:0]$8163 end attribute \src "libresoc.v:157595.3-157613.6" process $proc$libresoc.v:157595$8167 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$next[3:0]$8168 $1\cr_a$next[3:0]$8170 assign { } { } assign $0\cr_a_ok$next[0:0]$8169 $2\cr_a_ok$next[0:0]$8172 attribute \src "libresoc.v:157596.5-157596.29" switch \initial attribute \src "libresoc.v:157596.9-157596.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$8171 $1\cr_a$next[3:0]$8170 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$8171 $1\cr_a$next[3:0]$8170 } { \cr_a_ok$74 \cr_a$73 } case assign $1\cr_a$next[3:0]$8170 \cr_a assign $1\cr_a_ok$next[0:0]$8171 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$next[0:0]$8172 1'0 case assign $2\cr_a_ok$next[0:0]$8172 $1\cr_a_ok$next[0:0]$8171 end sync always update \cr_a$next $0\cr_a$next[3:0]$8168 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8169 end attribute \src "libresoc.v:157614.3-157632.6" process $proc$libresoc.v:157614$8173 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ov$next[1:0]$8174 $1\xer_ov$next[1:0]$8176 assign { } { } assign $0\xer_ov_ok$next[0:0]$8175 $2\xer_ov_ok$next[0:0]$8178 attribute \src "libresoc.v:157615.5-157615.29" switch \initial attribute \src "libresoc.v:157615.9-157615.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$8177 $1\xer_ov$next[1:0]$8176 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$8177 $1\xer_ov$next[1:0]$8176 } { \xer_ov_ok$76 \xer_ov$75 } case assign $1\xer_ov$next[1:0]$8176 \xer_ov assign $1\xer_ov_ok$next[0:0]$8177 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ov_ok$next[0:0]$8178 1'0 case assign $2\xer_ov_ok$next[0:0]$8178 $1\xer_ov_ok$next[0:0]$8177 end sync always update \xer_ov$next $0\xer_ov$next[1:0]$8174 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8175 end attribute \src "libresoc.v:157633.3-157651.6" process $proc$libresoc.v:157633$8179 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_so$15$next[0:0]$8181 $1\xer_so$15$next[0:0]$8183 assign $0\xer_so_ok$next[0:0]$8180 $2\xer_so_ok$next[0:0]$8184 attribute \src "libresoc.v:157634.5-157634.29" switch \initial attribute \src "libresoc.v:157634.9-157634.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$8182 $1\xer_so$15$next[0:0]$8183 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$8182 $1\xer_so$15$next[0:0]$8183 } { \xer_so_ok$78 \xer_so$77 } case assign $1\xer_so_ok$next[0:0]$8182 \xer_so_ok assign $1\xer_so$15$next[0:0]$8183 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so_ok$next[0:0]$8184 1'0 case assign $2\xer_so_ok$next[0:0]$8184 $1\xer_so_ok$next[0:0]$8182 end sync always update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8180 update \xer_so$15$next $0\xer_so$15$next[0:0]$8181 end connect \$56 $and$libresoc.v:157378$8085_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } connect \muxid$58 \output_muxid$31 connect \p_valid_i_p_ready_o \$56 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$55 \p_valid_i connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } connect { \cr_a_ok$50 \output_cr_a } 5'00000 connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } connect \output_muxid \mul3_muxid$16 connect \neg_res32$49 \neg_res32 connect \mul3_neg_res \neg_res connect \mul3_xer_so \xer_so connect \mul3_o \o connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end attribute \src "libresoc.v:157681.1-157692.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n attribute \src "libresoc.v:157690.17-157690.111" wire $and$libresoc.v:157690$8223_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157690$8223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157690$8223_Y end connect \$1 $and$libresoc.v:157690$8223_Y connect \trigger \$1 end attribute \src "libresoc.v:157696.1-157707.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 attribute \src "libresoc.v:157705.17-157705.111" wire $and$libresoc.v:157705$8224_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157705$8224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157705$8224_Y end connect \$1 $and$libresoc.v:157705$8224_Y connect \trigger \$1 end attribute \src "libresoc.v:157711.1-157722.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 attribute \src "libresoc.v:157720.17-157720.111" wire $and$libresoc.v:157720$8225_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157720$8225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157720$8225_Y end connect \$1 $and$libresoc.v:157720$8225_Y connect \trigger \$1 end attribute \src "libresoc.v:157726.1-157737.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 attribute \src "libresoc.v:157735.17-157735.111" wire $and$libresoc.v:157735$8226_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157735$8226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157735$8226_Y end connect \$1 $and$libresoc.v:157735$8226_Y connect \trigger \$1 end attribute \src "libresoc.v:157741.1-157752.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 attribute \src "libresoc.v:157750.17-157750.111" wire $and$libresoc.v:157750$8227_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157750$8227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157750$8227_Y end connect \$1 $and$libresoc.v:157750$8227_Y connect \trigger \$1 end attribute \src "libresoc.v:157756.1-157767.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 attribute \src "libresoc.v:157765.17-157765.111" wire $and$libresoc.v:157765$8228_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157765$8228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157765$8228_Y end connect \$1 $and$libresoc.v:157765$8228_Y connect \trigger \$1 end attribute \src "libresoc.v:157771.1-157782.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 attribute \src "libresoc.v:157780.17-157780.111" wire $and$libresoc.v:157780$8229_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157780$8229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157780$8229_Y end connect \$1 $and$libresoc.v:157780$8229_Y connect \trigger \$1 end attribute \src "libresoc.v:157786.1-157797.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 attribute \src "libresoc.v:157795.17-157795.111" wire $and$libresoc.v:157795$8230_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157795$8230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157795$8230_Y end connect \$1 $and$libresoc.v:157795$8230_Y connect \trigger \$1 end attribute \src "libresoc.v:157801.1-157812.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 attribute \src "libresoc.v:157810.17-157810.111" wire $and$libresoc.v:157810$8231_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157810$8231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157810$8231_Y end connect \$1 $and$libresoc.v:157810$8231_Y connect \trigger \$1 end attribute \src "libresoc.v:157816.1-157827.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 attribute \src "libresoc.v:157825.17-157825.111" wire $and$libresoc.v:157825$8232_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157825$8232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157825$8232_Y end connect \$1 $and$libresoc.v:157825$8232_Y connect \trigger \$1 end attribute \src "libresoc.v:157831.1-157842.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 attribute \src "libresoc.v:157840.17-157840.111" wire $and$libresoc.v:157840$8233_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157840$8233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157840$8233_Y end connect \$1 $and$libresoc.v:157840$8233_Y connect \trigger \$1 end attribute \src "libresoc.v:157846.1-157857.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 attribute \src "libresoc.v:157855.17-157855.111" wire $and$libresoc.v:157855$8234_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157855$8234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157855$8234_Y end connect \$1 $and$libresoc.v:157855$8234_Y connect \trigger \$1 end attribute \src "libresoc.v:157861.1-157872.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 attribute \src "libresoc.v:157870.17-157870.111" wire $and$libresoc.v:157870$8235_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157870$8235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157870$8235_Y end connect \$1 $and$libresoc.v:157870$8235_Y connect \trigger \$1 end attribute \src "libresoc.v:157876.1-157887.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 attribute \src "libresoc.v:157885.17-157885.111" wire $and$libresoc.v:157885$8236_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157885$8236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157885$8236_Y end connect \$1 $and$libresoc.v:157885$8236_Y connect \trigger \$1 end attribute \src "libresoc.v:157891.1-157902.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 attribute \src "libresoc.v:157900.17-157900.111" wire $and$libresoc.v:157900$8237_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157900$8237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157900$8237_Y end connect \$1 $and$libresoc.v:157900$8237_Y connect \trigger \$1 end attribute \src "libresoc.v:157906.1-157917.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 attribute \src "libresoc.v:157915.17-157915.111" wire $and$libresoc.v:157915$8238_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157915$8238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157915$8238_Y end connect \$1 $and$libresoc.v:157915$8238_Y connect \trigger \$1 end attribute \src "libresoc.v:157921.1-157932.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 attribute \src "libresoc.v:157930.17-157930.111" wire $and$libresoc.v:157930$8239_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157930$8239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157930$8239_Y end connect \$1 $and$libresoc.v:157930$8239_Y connect \trigger \$1 end attribute \src "libresoc.v:157936.1-157947.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 attribute \src "libresoc.v:157945.17-157945.111" wire $and$libresoc.v:157945$8240_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157945$8240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157945$8240_Y end connect \$1 $and$libresoc.v:157945$8240_Y connect \trigger \$1 end attribute \src "libresoc.v:157951.1-157962.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 attribute \src "libresoc.v:157960.17-157960.111" wire $and$libresoc.v:157960$8241_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157960$8241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157960$8241_Y end connect \$1 $and$libresoc.v:157960$8241_Y connect \trigger \$1 end attribute \src "libresoc.v:157966.1-157977.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 attribute \src "libresoc.v:157975.17-157975.111" wire $and$libresoc.v:157975$8242_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157975$8242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157975$8242_Y end connect \$1 $and$libresoc.v:157975$8242_Y connect \trigger \$1 end attribute \src "libresoc.v:157981.1-157992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 attribute \src "libresoc.v:157990.17-157990.111" wire $and$libresoc.v:157990$8243_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:157990$8243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:157990$8243_Y end connect \$1 $and$libresoc.v:157990$8243_Y connect \trigger \$1 end attribute \src "libresoc.v:157996.1-158007.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 attribute \src "libresoc.v:158005.17-158005.111" wire $and$libresoc.v:158005$8244_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:158005$8244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:158005$8244_Y end connect \$1 $and$libresoc.v:158005$8244_Y connect \trigger \$1 end attribute \src "libresoc.v:158011.1-158022.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 attribute \src "libresoc.v:158020.17-158020.111" wire $and$libresoc.v:158020$8245_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:158020$8245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:158020$8245_Y end connect \$1 $and$libresoc.v:158020$8245_Y connect \trigger \$1 end attribute \src "libresoc.v:158026.1-158037.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 attribute \src "libresoc.v:158035.17-158035.111" wire $and$libresoc.v:158035$8246_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:158035$8246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:158035$8246_Y end connect \$1 $and$libresoc.v:158035$8246_Y connect \trigger \$1 end attribute \src "libresoc.v:158041.1-158052.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 attribute \src "libresoc.v:158050.17-158050.111" wire $and$libresoc.v:158050$8247_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:158050$8247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:158050$8247_Y end connect \$1 $and$libresoc.v:158050$8247_Y connect \trigger \$1 end attribute \src "libresoc.v:158056.1-158067.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 attribute \src "libresoc.v:158065.17-158065.111" wire $and$libresoc.v:158065$8248_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 1 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire input 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" cell $and $and$libresoc.v:158065$8248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:158065$8248_Y end connect \$1 $and$libresoc.v:158065$8248_Y connect \trigger \$1 end attribute \src "libresoc.v:158071.1-158129.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l attribute \src "libresoc.v:158072.7-158072.20" wire $0\initial[0:0] attribute \src "libresoc.v:158117.3-158125.6" wire $0\q_int$next[0:0]$8259 attribute \src "libresoc.v:158115.3-158116.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158117.3-158125.6" wire $1\q_int$next[0:0]$8260 attribute \src "libresoc.v:158094.7-158094.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158107.17-158107.96" wire $and$libresoc.v:158107$8249_Y attribute \src "libresoc.v:158112.17-158112.96" wire $and$libresoc.v:158112$8254_Y attribute \src "libresoc.v:158109.18-158109.93" wire $not$libresoc.v:158109$8251_Y attribute \src "libresoc.v:158111.17-158111.92" wire $not$libresoc.v:158111$8253_Y attribute \src "libresoc.v:158114.17-158114.92" wire $not$libresoc.v:158114$8256_Y attribute \src "libresoc.v:158108.18-158108.98" wire $or$libresoc.v:158108$8250_Y attribute \src "libresoc.v:158110.18-158110.99" wire $or$libresoc.v:158110$8252_Y attribute \src "libresoc.v:158113.17-158113.97" wire $or$libresoc.v:158113$8255_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158072.7-158072.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158107$8249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158107$8249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158112$8254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158112$8254_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158109$8251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158109$8251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158111$8253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158111$8253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158114$8256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158114$8256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158108$8250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158108$8250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158110$8252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158110$8252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158113$8255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158113$8255_Y end attribute \src "libresoc.v:158072.7-158072.20" process $proc$libresoc.v:158072$8261 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158094.7-158094.19" process $proc$libresoc.v:158094$8262 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158115.3-158116.27" process $proc$libresoc.v:158115$8257 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158117.3-158125.6" process $proc$libresoc.v:158117$8258 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8259 $1\q_int$next[0:0]$8260 attribute \src "libresoc.v:158118.5-158118.29" switch \initial attribute \src "libresoc.v:158118.9-158118.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8260 1'0 case assign $1\q_int$next[0:0]$8260 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8259 end connect \$9 $and$libresoc.v:158107$8249_Y connect \$11 $or$libresoc.v:158108$8250_Y connect \$13 $not$libresoc.v:158109$8251_Y connect \$15 $or$libresoc.v:158110$8252_Y connect \$1 $not$libresoc.v:158111$8253_Y connect \$3 $and$libresoc.v:158112$8254_Y connect \$5 $or$libresoc.v:158113$8255_Y connect \$7 $not$libresoc.v:158114$8256_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158133.1-158191.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 attribute \src "libresoc.v:158134.7-158134.20" wire $0\initial[0:0] attribute \src "libresoc.v:158179.3-158187.6" wire $0\q_int$next[0:0]$8273 attribute \src "libresoc.v:158177.3-158178.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158179.3-158187.6" wire $1\q_int$next[0:0]$8274 attribute \src "libresoc.v:158156.7-158156.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158169.17-158169.96" wire $and$libresoc.v:158169$8263_Y attribute \src "libresoc.v:158174.17-158174.96" wire $and$libresoc.v:158174$8268_Y attribute \src "libresoc.v:158171.18-158171.93" wire $not$libresoc.v:158171$8265_Y attribute \src "libresoc.v:158173.17-158173.92" wire $not$libresoc.v:158173$8267_Y attribute \src "libresoc.v:158176.17-158176.92" wire $not$libresoc.v:158176$8270_Y attribute \src "libresoc.v:158170.18-158170.98" wire $or$libresoc.v:158170$8264_Y attribute \src "libresoc.v:158172.18-158172.99" wire $or$libresoc.v:158172$8266_Y attribute \src "libresoc.v:158175.17-158175.97" wire $or$libresoc.v:158175$8269_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158134.7-158134.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158169$8263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158169$8263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158174$8268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158174$8268_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158171$8265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158171$8265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158173$8267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158173$8267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158176$8270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158176$8270_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158170$8264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158170$8264_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158172$8266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158172$8266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158175$8269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158175$8269_Y end attribute \src "libresoc.v:158134.7-158134.20" process $proc$libresoc.v:158134$8275 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158156.7-158156.19" process $proc$libresoc.v:158156$8276 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158177.3-158178.27" process $proc$libresoc.v:158177$8271 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158179.3-158187.6" process $proc$libresoc.v:158179$8272 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8273 $1\q_int$next[0:0]$8274 attribute \src "libresoc.v:158180.5-158180.29" switch \initial attribute \src "libresoc.v:158180.9-158180.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8274 1'0 case assign $1\q_int$next[0:0]$8274 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8273 end connect \$9 $and$libresoc.v:158169$8263_Y connect \$11 $or$libresoc.v:158170$8264_Y connect \$13 $not$libresoc.v:158171$8265_Y connect \$15 $or$libresoc.v:158172$8266_Y connect \$1 $not$libresoc.v:158173$8267_Y connect \$3 $and$libresoc.v:158174$8268_Y connect \$5 $or$libresoc.v:158175$8269_Y connect \$7 $not$libresoc.v:158176$8270_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158195.1-158253.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 attribute \src "libresoc.v:158196.7-158196.20" wire $0\initial[0:0] attribute \src "libresoc.v:158241.3-158249.6" wire $0\q_int$next[0:0]$8287 attribute \src "libresoc.v:158239.3-158240.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158241.3-158249.6" wire $1\q_int$next[0:0]$8288 attribute \src "libresoc.v:158218.7-158218.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158231.17-158231.96" wire $and$libresoc.v:158231$8277_Y attribute \src "libresoc.v:158236.17-158236.96" wire $and$libresoc.v:158236$8282_Y attribute \src "libresoc.v:158233.18-158233.93" wire $not$libresoc.v:158233$8279_Y attribute \src "libresoc.v:158235.17-158235.92" wire $not$libresoc.v:158235$8281_Y attribute \src "libresoc.v:158238.17-158238.92" wire $not$libresoc.v:158238$8284_Y attribute \src "libresoc.v:158232.18-158232.98" wire $or$libresoc.v:158232$8278_Y attribute \src "libresoc.v:158234.18-158234.99" wire $or$libresoc.v:158234$8280_Y attribute \src "libresoc.v:158237.17-158237.97" wire $or$libresoc.v:158237$8283_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158196.7-158196.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158231$8277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158231$8277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158236$8282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158236$8282_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158233$8279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158233$8279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158235$8281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158235$8281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158238$8284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158238$8284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158232$8278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158232$8278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158234$8280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158234$8280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158237$8283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158237$8283_Y end attribute \src "libresoc.v:158196.7-158196.20" process $proc$libresoc.v:158196$8289 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158218.7-158218.19" process $proc$libresoc.v:158218$8290 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158239.3-158240.27" process $proc$libresoc.v:158239$8285 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158241.3-158249.6" process $proc$libresoc.v:158241$8286 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8287 $1\q_int$next[0:0]$8288 attribute \src "libresoc.v:158242.5-158242.29" switch \initial attribute \src "libresoc.v:158242.9-158242.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8288 1'0 case assign $1\q_int$next[0:0]$8288 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8287 end connect \$9 $and$libresoc.v:158231$8277_Y connect \$11 $or$libresoc.v:158232$8278_Y connect \$13 $not$libresoc.v:158233$8279_Y connect \$15 $or$libresoc.v:158234$8280_Y connect \$1 $not$libresoc.v:158235$8281_Y connect \$3 $and$libresoc.v:158236$8282_Y connect \$5 $or$libresoc.v:158237$8283_Y connect \$7 $not$libresoc.v:158238$8284_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158257.1-158315.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 attribute \src "libresoc.v:158258.7-158258.20" wire $0\initial[0:0] attribute \src "libresoc.v:158303.3-158311.6" wire $0\q_int$next[0:0]$8301 attribute \src "libresoc.v:158301.3-158302.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158303.3-158311.6" wire $1\q_int$next[0:0]$8302 attribute \src "libresoc.v:158280.7-158280.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158293.17-158293.96" wire $and$libresoc.v:158293$8291_Y attribute \src "libresoc.v:158298.17-158298.96" wire $and$libresoc.v:158298$8296_Y attribute \src "libresoc.v:158295.18-158295.93" wire $not$libresoc.v:158295$8293_Y attribute \src "libresoc.v:158297.17-158297.92" wire $not$libresoc.v:158297$8295_Y attribute \src "libresoc.v:158300.17-158300.92" wire $not$libresoc.v:158300$8298_Y attribute \src "libresoc.v:158294.18-158294.98" wire $or$libresoc.v:158294$8292_Y attribute \src "libresoc.v:158296.18-158296.99" wire $or$libresoc.v:158296$8294_Y attribute \src "libresoc.v:158299.17-158299.97" wire $or$libresoc.v:158299$8297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158258.7-158258.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158293$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158293$8291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158298$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158298$8296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158295$8293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158295$8293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158297$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158297$8295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158300$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158300$8298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158294$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158294$8292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158296$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158296$8294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158299$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158299$8297_Y end attribute \src "libresoc.v:158258.7-158258.20" process $proc$libresoc.v:158258$8303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158280.7-158280.19" process $proc$libresoc.v:158280$8304 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158301.3-158302.27" process $proc$libresoc.v:158301$8299 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158303.3-158311.6" process $proc$libresoc.v:158303$8300 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8301 $1\q_int$next[0:0]$8302 attribute \src "libresoc.v:158304.5-158304.29" switch \initial attribute \src "libresoc.v:158304.9-158304.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8302 1'0 case assign $1\q_int$next[0:0]$8302 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8301 end connect \$9 $and$libresoc.v:158293$8291_Y connect \$11 $or$libresoc.v:158294$8292_Y connect \$13 $not$libresoc.v:158295$8293_Y connect \$15 $or$libresoc.v:158296$8294_Y connect \$1 $not$libresoc.v:158297$8295_Y connect \$3 $and$libresoc.v:158298$8296_Y connect \$5 $or$libresoc.v:158299$8297_Y connect \$7 $not$libresoc.v:158300$8298_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158319.1-158377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 attribute \src "libresoc.v:158320.7-158320.20" wire $0\initial[0:0] attribute \src "libresoc.v:158365.3-158373.6" wire $0\q_int$next[0:0]$8315 attribute \src "libresoc.v:158363.3-158364.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158365.3-158373.6" wire $1\q_int$next[0:0]$8316 attribute \src "libresoc.v:158342.7-158342.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158355.17-158355.96" wire $and$libresoc.v:158355$8305_Y attribute \src "libresoc.v:158360.17-158360.96" wire $and$libresoc.v:158360$8310_Y attribute \src "libresoc.v:158357.18-158357.93" wire $not$libresoc.v:158357$8307_Y attribute \src "libresoc.v:158359.17-158359.92" wire $not$libresoc.v:158359$8309_Y attribute \src "libresoc.v:158362.17-158362.92" wire $not$libresoc.v:158362$8312_Y attribute \src "libresoc.v:158356.18-158356.98" wire $or$libresoc.v:158356$8306_Y attribute \src "libresoc.v:158358.18-158358.99" wire $or$libresoc.v:158358$8308_Y attribute \src "libresoc.v:158361.17-158361.97" wire $or$libresoc.v:158361$8311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158320.7-158320.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158355$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158355$8305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158360$8310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158360$8310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158357$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158357$8307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158359$8309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158359$8309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158362$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158362$8312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158356$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158356$8306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158358$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158358$8308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158361$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158361$8311_Y end attribute \src "libresoc.v:158320.7-158320.20" process $proc$libresoc.v:158320$8317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158342.7-158342.19" process $proc$libresoc.v:158342$8318 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158363.3-158364.27" process $proc$libresoc.v:158363$8313 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158365.3-158373.6" process $proc$libresoc.v:158365$8314 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8315 $1\q_int$next[0:0]$8316 attribute \src "libresoc.v:158366.5-158366.29" switch \initial attribute \src "libresoc.v:158366.9-158366.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8316 1'0 case assign $1\q_int$next[0:0]$8316 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8315 end connect \$9 $and$libresoc.v:158355$8305_Y connect \$11 $or$libresoc.v:158356$8306_Y connect \$13 $not$libresoc.v:158357$8307_Y connect \$15 $or$libresoc.v:158358$8308_Y connect \$1 $not$libresoc.v:158359$8309_Y connect \$3 $and$libresoc.v:158360$8310_Y connect \$5 $or$libresoc.v:158361$8311_Y connect \$7 $not$libresoc.v:158362$8312_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158381.1-158439.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 attribute \src "libresoc.v:158382.7-158382.20" wire $0\initial[0:0] attribute \src "libresoc.v:158427.3-158435.6" wire $0\q_int$next[0:0]$8329 attribute \src "libresoc.v:158425.3-158426.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158427.3-158435.6" wire $1\q_int$next[0:0]$8330 attribute \src "libresoc.v:158404.7-158404.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158417.17-158417.96" wire $and$libresoc.v:158417$8319_Y attribute \src "libresoc.v:158422.17-158422.96" wire $and$libresoc.v:158422$8324_Y attribute \src "libresoc.v:158419.18-158419.93" wire $not$libresoc.v:158419$8321_Y attribute \src "libresoc.v:158421.17-158421.92" wire $not$libresoc.v:158421$8323_Y attribute \src "libresoc.v:158424.17-158424.92" wire $not$libresoc.v:158424$8326_Y attribute \src "libresoc.v:158418.18-158418.98" wire $or$libresoc.v:158418$8320_Y attribute \src "libresoc.v:158420.18-158420.99" wire $or$libresoc.v:158420$8322_Y attribute \src "libresoc.v:158423.17-158423.97" wire $or$libresoc.v:158423$8325_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158382.7-158382.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158417$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158417$8319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158422$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158422$8324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158419$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158419$8321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158421$8323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158421$8323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158424$8326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158424$8326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158418$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158418$8320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158420$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158420$8322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158423$8325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158423$8325_Y end attribute \src "libresoc.v:158382.7-158382.20" process $proc$libresoc.v:158382$8331 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158404.7-158404.19" process $proc$libresoc.v:158404$8332 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158425.3-158426.27" process $proc$libresoc.v:158425$8327 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158427.3-158435.6" process $proc$libresoc.v:158427$8328 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8329 $1\q_int$next[0:0]$8330 attribute \src "libresoc.v:158428.5-158428.29" switch \initial attribute \src "libresoc.v:158428.9-158428.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8330 1'0 case assign $1\q_int$next[0:0]$8330 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8329 end connect \$9 $and$libresoc.v:158417$8319_Y connect \$11 $or$libresoc.v:158418$8320_Y connect \$13 $not$libresoc.v:158419$8321_Y connect \$15 $or$libresoc.v:158420$8322_Y connect \$1 $not$libresoc.v:158421$8323_Y connect \$3 $and$libresoc.v:158422$8324_Y connect \$5 $or$libresoc.v:158423$8325_Y connect \$7 $not$libresoc.v:158424$8326_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158443.1-158501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 attribute \src "libresoc.v:158444.7-158444.20" wire $0\initial[0:0] attribute \src "libresoc.v:158489.3-158497.6" wire $0\q_int$next[0:0]$8343 attribute \src "libresoc.v:158487.3-158488.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158489.3-158497.6" wire $1\q_int$next[0:0]$8344 attribute \src "libresoc.v:158466.7-158466.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158479.17-158479.96" wire $and$libresoc.v:158479$8333_Y attribute \src "libresoc.v:158484.17-158484.96" wire $and$libresoc.v:158484$8338_Y attribute \src "libresoc.v:158481.18-158481.93" wire $not$libresoc.v:158481$8335_Y attribute \src "libresoc.v:158483.17-158483.92" wire $not$libresoc.v:158483$8337_Y attribute \src "libresoc.v:158486.17-158486.92" wire $not$libresoc.v:158486$8340_Y attribute \src "libresoc.v:158480.18-158480.98" wire $or$libresoc.v:158480$8334_Y attribute \src "libresoc.v:158482.18-158482.99" wire $or$libresoc.v:158482$8336_Y attribute \src "libresoc.v:158485.17-158485.97" wire $or$libresoc.v:158485$8339_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158444.7-158444.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158479$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158479$8333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158484$8338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158484$8338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158481$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158481$8335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158483$8337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158483$8337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158486$8340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158486$8340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158480$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158480$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158482$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158482$8336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158485$8339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158485$8339_Y end attribute \src "libresoc.v:158444.7-158444.20" process $proc$libresoc.v:158444$8345 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158466.7-158466.19" process $proc$libresoc.v:158466$8346 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158487.3-158488.27" process $proc$libresoc.v:158487$8341 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158489.3-158497.6" process $proc$libresoc.v:158489$8342 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8343 $1\q_int$next[0:0]$8344 attribute \src "libresoc.v:158490.5-158490.29" switch \initial attribute \src "libresoc.v:158490.9-158490.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8344 1'0 case assign $1\q_int$next[0:0]$8344 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8343 end connect \$9 $and$libresoc.v:158479$8333_Y connect \$11 $or$libresoc.v:158480$8334_Y connect \$13 $not$libresoc.v:158481$8335_Y connect \$15 $or$libresoc.v:158482$8336_Y connect \$1 $not$libresoc.v:158483$8337_Y connect \$3 $and$libresoc.v:158484$8338_Y connect \$5 $or$libresoc.v:158485$8339_Y connect \$7 $not$libresoc.v:158486$8340_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158505.1-158563.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 attribute \src "libresoc.v:158506.7-158506.20" wire $0\initial[0:0] attribute \src "libresoc.v:158551.3-158559.6" wire $0\q_int$next[0:0]$8357 attribute \src "libresoc.v:158549.3-158550.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158551.3-158559.6" wire $1\q_int$next[0:0]$8358 attribute \src "libresoc.v:158528.7-158528.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158541.17-158541.96" wire $and$libresoc.v:158541$8347_Y attribute \src "libresoc.v:158546.17-158546.96" wire $and$libresoc.v:158546$8352_Y attribute \src "libresoc.v:158543.18-158543.93" wire $not$libresoc.v:158543$8349_Y attribute \src "libresoc.v:158545.17-158545.92" wire $not$libresoc.v:158545$8351_Y attribute \src "libresoc.v:158548.17-158548.92" wire $not$libresoc.v:158548$8354_Y attribute \src "libresoc.v:158542.18-158542.98" wire $or$libresoc.v:158542$8348_Y attribute \src "libresoc.v:158544.18-158544.99" wire $or$libresoc.v:158544$8350_Y attribute \src "libresoc.v:158547.17-158547.97" wire $or$libresoc.v:158547$8353_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158506.7-158506.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158541$8347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158541$8347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158546$8352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158546$8352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158543$8349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158543$8349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158545$8351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158545$8351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158548$8354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158548$8354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158542$8348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158542$8348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158544$8350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158544$8350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158547$8353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158547$8353_Y end attribute \src "libresoc.v:158506.7-158506.20" process $proc$libresoc.v:158506$8359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158528.7-158528.19" process $proc$libresoc.v:158528$8360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158549.3-158550.27" process $proc$libresoc.v:158549$8355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158551.3-158559.6" process $proc$libresoc.v:158551$8356 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8357 $1\q_int$next[0:0]$8358 attribute \src "libresoc.v:158552.5-158552.29" switch \initial attribute \src "libresoc.v:158552.9-158552.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8358 1'0 case assign $1\q_int$next[0:0]$8358 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8357 end connect \$9 $and$libresoc.v:158541$8347_Y connect \$11 $or$libresoc.v:158542$8348_Y connect \$13 $not$libresoc.v:158543$8349_Y connect \$15 $or$libresoc.v:158544$8350_Y connect \$1 $not$libresoc.v:158545$8351_Y connect \$3 $and$libresoc.v:158546$8352_Y connect \$5 $or$libresoc.v:158547$8353_Y connect \$7 $not$libresoc.v:158548$8354_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158567.1-158625.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 attribute \src "libresoc.v:158568.7-158568.20" wire $0\initial[0:0] attribute \src "libresoc.v:158613.3-158621.6" wire $0\q_int$next[0:0]$8371 attribute \src "libresoc.v:158611.3-158612.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158613.3-158621.6" wire $1\q_int$next[0:0]$8372 attribute \src "libresoc.v:158590.7-158590.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158603.17-158603.96" wire $and$libresoc.v:158603$8361_Y attribute \src "libresoc.v:158608.17-158608.96" wire $and$libresoc.v:158608$8366_Y attribute \src "libresoc.v:158605.18-158605.93" wire $not$libresoc.v:158605$8363_Y attribute \src "libresoc.v:158607.17-158607.92" wire $not$libresoc.v:158607$8365_Y attribute \src "libresoc.v:158610.17-158610.92" wire $not$libresoc.v:158610$8368_Y attribute \src "libresoc.v:158604.18-158604.98" wire $or$libresoc.v:158604$8362_Y attribute \src "libresoc.v:158606.18-158606.99" wire $or$libresoc.v:158606$8364_Y attribute \src "libresoc.v:158609.17-158609.97" wire $or$libresoc.v:158609$8367_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158568.7-158568.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158603$8361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158603$8361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158608$8366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158608$8366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158605$8363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158605$8363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158607$8365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158607$8365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158610$8368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158610$8368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158604$8362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158604$8362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158606$8364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158606$8364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158609$8367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158609$8367_Y end attribute \src "libresoc.v:158568.7-158568.20" process $proc$libresoc.v:158568$8373 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158590.7-158590.19" process $proc$libresoc.v:158590$8374 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158611.3-158612.27" process $proc$libresoc.v:158611$8369 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158613.3-158621.6" process $proc$libresoc.v:158613$8370 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8371 $1\q_int$next[0:0]$8372 attribute \src "libresoc.v:158614.5-158614.29" switch \initial attribute \src "libresoc.v:158614.9-158614.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8372 1'0 case assign $1\q_int$next[0:0]$8372 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8371 end connect \$9 $and$libresoc.v:158603$8361_Y connect \$11 $or$libresoc.v:158604$8362_Y connect \$13 $not$libresoc.v:158605$8363_Y connect \$15 $or$libresoc.v:158606$8364_Y connect \$1 $not$libresoc.v:158607$8365_Y connect \$3 $and$libresoc.v:158608$8366_Y connect \$5 $or$libresoc.v:158609$8367_Y connect \$7 $not$libresoc.v:158610$8368_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158629.1-158687.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 attribute \src "libresoc.v:158630.7-158630.20" wire $0\initial[0:0] attribute \src "libresoc.v:158675.3-158683.6" wire $0\q_int$next[0:0]$8385 attribute \src "libresoc.v:158673.3-158674.27" wire $0\q_int[0:0] attribute \src "libresoc.v:158675.3-158683.6" wire $1\q_int$next[0:0]$8386 attribute \src "libresoc.v:158652.7-158652.19" wire $1\q_int[0:0] attribute \src "libresoc.v:158665.17-158665.96" wire $and$libresoc.v:158665$8375_Y attribute \src "libresoc.v:158670.17-158670.96" wire $and$libresoc.v:158670$8380_Y attribute \src "libresoc.v:158667.18-158667.93" wire $not$libresoc.v:158667$8377_Y attribute \src "libresoc.v:158669.17-158669.92" wire $not$libresoc.v:158669$8379_Y attribute \src "libresoc.v:158672.17-158672.92" wire $not$libresoc.v:158672$8382_Y attribute \src "libresoc.v:158666.18-158666.98" wire $or$libresoc.v:158666$8376_Y attribute \src "libresoc.v:158668.18-158668.99" wire $or$libresoc.v:158668$8378_Y attribute \src "libresoc.v:158671.17-158671.97" wire $or$libresoc.v:158671$8381_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:158630.7-158630.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:158665$8375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:158665$8375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:158670$8380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:158670$8380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:158667$8377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \Y $not$libresoc.v:158667$8377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:158669$8379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158669$8379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:158672$8382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc connect \Y $not$libresoc.v:158672$8382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:158666$8376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc connect \Y $or$libresoc.v:158666$8376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:158668$8378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int connect \Y $or$libresoc.v:158668$8378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:158671$8381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc connect \Y $or$libresoc.v:158671$8381_Y end attribute \src "libresoc.v:158630.7-158630.20" process $proc$libresoc.v:158630$8387 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:158652.7-158652.19" process $proc$libresoc.v:158652$8388 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:158673.3-158674.27" process $proc$libresoc.v:158673$8383 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:158675.3-158683.6" process $proc$libresoc.v:158675$8384 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8385 $1\q_int$next[0:0]$8386 attribute \src "libresoc.v:158676.5-158676.29" switch \initial attribute \src "libresoc.v:158676.9-158676.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$8386 1'0 case assign $1\q_int$next[0:0]$8386 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$8385 end connect \$9 $and$libresoc.v:158665$8375_Y connect \$11 $or$libresoc.v:158666$8376_Y connect \$13 $not$libresoc.v:158667$8377_Y connect \$15 $or$libresoc.v:158668$8378_Y connect \$1 $not$libresoc.v:158669$8379_Y connect \$3 $and$libresoc.v:158670$8380_Y connect \$5 $or$libresoc.v:158671$8381_Y connect \$7 $not$libresoc.v:158672$8382_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end attribute \src "libresoc.v:158691.1-159149.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output attribute \src "libresoc.v:159068.3-159079.6" wire width 4 $0\cr0[3:0] attribute \src "libresoc.v:158692.7-158692.20" wire $0\initial[0:0] attribute \src "libresoc.v:159080.3-159091.6" wire width 65 $0\o$28[64:0]$8407 attribute \src "libresoc.v:159056.3-159067.6" wire $0\so[0:0] attribute \src "libresoc.v:159112.3-159121.6" wire width 2 $0\xer_ov$24[1:0]$8414 attribute \src "libresoc.v:159122.3-159131.6" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:159092.3-159101.6" wire $0\xer_so$25[0:0]$8410 attribute \src "libresoc.v:159102.3-159111.6" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:159068.3-159079.6" wire width 4 $1\cr0[3:0] attribute \src "libresoc.v:159080.3-159091.6" wire width 65 $1\o$28[64:0]$8408 attribute \src "libresoc.v:159056.3-159067.6" wire $1\so[0:0] attribute \src "libresoc.v:159112.3-159121.6" wire width 2 $1\xer_ov$24[1:0]$8415 attribute \src "libresoc.v:159122.3-159131.6" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:159092.3-159101.6" wire $1\xer_so$25[0:0]$8411 attribute \src "libresoc.v:159102.3-159111.6" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:159043.18-159043.128" wire $and$libresoc.v:159043$8389_Y attribute \src "libresoc.v:159051.18-159051.112" wire $and$libresoc.v:159051$8399_Y attribute \src "libresoc.v:159054.18-159054.125" wire $and$libresoc.v:159054$8402_Y attribute \src "libresoc.v:159047.18-159047.123" wire $eq$libresoc.v:159047$8395_Y attribute \src "libresoc.v:159048.18-159048.123" wire $eq$libresoc.v:159048$8396_Y attribute \src "libresoc.v:159045.18-159045.103" wire width 65 $extend$libresoc.v:159045$8391_Y attribute \src "libresoc.v:159046.18-159046.101" wire width 65 $extend$libresoc.v:159046$8393_Y attribute \src "libresoc.v:159044.18-159044.100" wire width 64 $not$libresoc.v:159044$8390_Y attribute \src "libresoc.v:159050.18-159050.107" wire $not$libresoc.v:159050$8398_Y attribute \src "libresoc.v:159053.18-159053.107" wire $not$libresoc.v:159053$8401_Y attribute \src "libresoc.v:159052.18-159052.115" wire $or$libresoc.v:159052$8400_Y attribute \src "libresoc.v:159055.18-159055.112" wire $or$libresoc.v:159055$8403_Y attribute \src "libresoc.v:159045.18-159045.103" wire width 65 $pos$libresoc.v:159045$8392_Y attribute \src "libresoc.v:159046.18-159046.101" wire width 65 $pos$libresoc.v:159046$8394_Y attribute \src "libresoc.v:159049.18-159049.105" wire $reduce_or$libresoc.v:159049$8397_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 42 \alu_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 27 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 28 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \alu_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 13 \alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 38 \alu_op__input_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 43 \alu_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 26 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 41 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \alu_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \alu_op__write_cr0$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \cr_a_ok attribute \src "libresoc.v:158692.7-158692.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire \is_cmpeqb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" wire \is_negative attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire \is_nzero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 54 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 25 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 44 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" wire \oe$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 22 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 48 \xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 23 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 50 \xer_ov$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 51 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 24 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 52 \xer_so$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" cell $and $and$libresoc.v:159043$8389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok connect \Y $and$libresoc.v:159043$8389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $and $and$libresoc.v:159051$8399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 connect \Y $and$libresoc.v:159051$8399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" cell $and $and$libresoc.v:159054$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok connect \Y $and$libresoc.v:159054$8402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" cell $eq $eq$libresoc.v:159047$8395 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:159047$8395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" cell $eq $eq$libresoc.v:159048$8396 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 connect \Y $eq$libresoc.v:159048$8396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $pos $extend$libresoc.v:159045$8391 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 connect \Y $extend$libresoc.v:159045$8391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:159046$8393 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o connect \Y $extend$libresoc.v:159046$8393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $not $not$libresoc.v:159044$8390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o connect \Y $not$libresoc.v:159044$8390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $not $not$libresoc.v:159050$8398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test connect \Y $not$libresoc.v:159050$8398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $not$libresoc.v:159053$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \Y $not$libresoc.v:159053$8401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" cell $or $or$libresoc.v:159052$8400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp connect \Y $or$libresoc.v:159052$8400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" cell $or $or$libresoc.v:159055$8403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] connect \Y $or$libresoc.v:159055$8403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $pos $pos$libresoc.v:159045$8392 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:159045$8391_Y connect \Y $pos$libresoc.v:159045$8392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:159046$8394 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:159046$8393_Y connect \Y $pos$libresoc.v:159046$8394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" cell $reduce_or $reduce_or$libresoc.v:159049$8397 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target connect \Y $reduce_or$libresoc.v:159049$8397_Y end attribute \src "libresoc.v:158692.7-158692.20" process $proc$libresoc.v:158692$8417 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:159056.3-159067.6" process $proc$libresoc.v:159056$8404 assign { } { } assign $0\so[0:0] $1\so[0:0] attribute \src "libresoc.v:159057.5-159057.29" switch \initial attribute \src "libresoc.v:159057.9-159057.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" switch \oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\so[0:0] \xer_so$25 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\so[0:0] \xer_so end sync always update \so $0\so[0:0] end attribute \src "libresoc.v:159068.3-159079.6" process $proc$libresoc.v:159068$8405 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] attribute \src "libresoc.v:159069.5-159069.29" switch \initial attribute \src "libresoc.v:159069.9-159069.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cr0[3:0] \cr_a attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } end sync always update \cr0 $0\cr0[3:0] end attribute \src "libresoc.v:159080.3-159091.6" process $proc$libresoc.v:159080$8406 assign { } { } assign $0\o$28[64:0]$8407 $1\o$28[64:0]$8408 attribute \src "libresoc.v:159081.5-159081.29" switch \initial attribute \src "libresoc.v:159081.9-159081.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" switch \alu_op__invert_out attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o$28[64:0]$8408 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o$28[64:0]$8408 \$33 end sync always update \o$28 $0\o$28[64:0]$8407 end attribute \src "libresoc.v:159092.3-159101.6" process $proc$libresoc.v:159092$8409 assign { } { } assign { } { } assign $0\xer_so$25[0:0]$8410 $1\xer_so$25[0:0]$8411 attribute \src "libresoc.v:159093.5-159093.29" switch \initial attribute \src "libresoc.v:159093.9-159093.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_so$25[0:0]$8411 \$52 case assign $1\xer_so$25[0:0]$8411 1'0 end sync always update \xer_so$25 $0\xer_so$25[0:0]$8410 end attribute \src "libresoc.v:159102.3-159111.6" process $proc$libresoc.v:159102$8412 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] attribute \src "libresoc.v:159103.5-159103.29" switch \initial attribute \src "libresoc.v:159103.9-159103.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_so_ok[0:0] 1'1 case assign $1\xer_so_ok[0:0] 1'0 end sync always update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:159112.3-159121.6" process $proc$libresoc.v:159112$8413 assign { } { } assign { } { } assign $0\xer_ov$24[1:0]$8414 $1\xer_ov$24[1:0]$8415 attribute \src "libresoc.v:159113.5-159113.29" switch \initial attribute \src "libresoc.v:159113.9-159113.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_ov$24[1:0]$8415 \xer_ov case assign $1\xer_ov$24[1:0]$8415 2'00 end sync always update \xer_ov$24 $0\xer_ov$24[1:0]$8414 end attribute \src "libresoc.v:159122.3-159131.6" process $proc$libresoc.v:159122$8416 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] attribute \src "libresoc.v:159123.5-159123.29" switch \initial attribute \src "libresoc.v:159123.9-159123.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 case assign $1\xer_ov_ok[0:0] 1'0 end sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end connect \$26 $and$libresoc.v:159043$8389_Y connect \$30 $not$libresoc.v:159044$8390_Y connect \$29 $pos$libresoc.v:159045$8392_Y connect \$33 $pos$libresoc.v:159046$8394_Y connect \$35 $eq$libresoc.v:159047$8395_Y connect \$37 $eq$libresoc.v:159048$8396_Y connect \$39 $reduce_or$libresoc.v:159049$8397_Y connect \$41 $not$libresoc.v:159050$8398_Y connect \$43 $and$libresoc.v:159051$8399_Y connect \$45 $or$libresoc.v:159052$8400_Y connect \$47 $not$libresoc.v:159053$8401_Y connect \$50 $and$libresoc.v:159054$8402_Y connect \$52 $or$libresoc.v:159055$8403_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \alu_op__write_cr0 connect \cr_a$22 \cr0 connect \o_ok$21 \o_ok connect \o$20 \o$28 [63:0] connect \is_positive \$43 connect \is_negative \msb_test connect \is_nzero \$39 connect \msb_test \target [63] connect \is_cmpeqb \$37 connect \is_cmp \$35 connect \xer_ca_ok \alu_op__output_carry connect \xer_ca$23 \xer_ca connect \target \o$28 [63:0] connect \oe \$26 end attribute \src "libresoc.v:159153.1-159554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 attribute \src "libresoc.v:159486.3-159497.6" wire width 4 $0\cr0[3:0] attribute \src "libresoc.v:159154.7-159154.20" wire $0\initial[0:0] attribute \src "libresoc.v:159474.3-159485.6" wire $0\so[0:0] attribute \src "libresoc.v:159518.3-159527.6" wire width 2 $0\xer_ov$17[1:0]$8437 attribute \src "libresoc.v:159528.3-159537.6" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:159498.3-159507.6" wire $0\xer_so$18[0:0]$8433 attribute \src "libresoc.v:159508.3-159517.6" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:159486.3-159497.6" wire width 4 $1\cr0[3:0] attribute \src "libresoc.v:159474.3-159485.6" wire $1\so[0:0] attribute \src "libresoc.v:159518.3-159527.6" wire width 2 $1\xer_ov$17[1:0]$8438 attribute \src "libresoc.v:159528.3-159537.6" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:159498.3-159507.6" wire $1\xer_so$18[0:0]$8434 attribute \src "libresoc.v:159508.3-159517.6" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:159463.18-159463.128" wire $and$libresoc.v:159463$8418_Y attribute \src "libresoc.v:159469.18-159469.112" wire $and$libresoc.v:159469$8425_Y attribute \src "libresoc.v:159472.18-159472.125" wire $and$libresoc.v:159472$8428_Y attribute \src "libresoc.v:159465.18-159465.123" wire $eq$libresoc.v:159465$8421_Y attribute \src "libresoc.v:159466.18-159466.123" wire $eq$libresoc.v:159466$8422_Y attribute \src "libresoc.v:159464.18-159464.101" wire width 65 $extend$libresoc.v:159464$8419_Y attribute \src "libresoc.v:159468.18-159468.107" wire $not$libresoc.v:159468$8424_Y attribute \src "libresoc.v:159471.18-159471.107" wire $not$libresoc.v:159471$8427_Y attribute \src "libresoc.v:159470.18-159470.115" wire $or$libresoc.v:159470$8426_Y attribute \src "libresoc.v:159473.18-159473.112" wire $or$libresoc.v:159473$8429_Y attribute \src "libresoc.v:159464.18-159464.101" wire width 65 $pos$libresoc.v:159464$8420_Y attribute \src "libresoc.v:159467.18-159467.105" wire $reduce_or$libresoc.v:159467$8423_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 15 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 34 \cr_a_ok attribute \src "libresoc.v:159154.7-159154.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire \is_cmpeqb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" wire \is_negative attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire \is_nzero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 21 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 22 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 12 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 30 \mul_op__insn$13 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 19 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 24 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 23 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 39 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 18 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 13 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 31 \o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 14 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \o_ok$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" wire \oe$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 16 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 35 \xer_ov$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 36 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 17 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" cell $and $and$libresoc.v:159463$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok connect \Y $and$libresoc.v:159463$8418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $and $and$libresoc.v:159469$8425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 connect \Y $and$libresoc.v:159469$8425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" cell $and $and$libresoc.v:159472$8428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok connect \Y $and$libresoc.v:159472$8428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" cell $eq $eq$libresoc.v:159465$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:159465$8421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" cell $eq $eq$libresoc.v:159466$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 connect \Y $eq$libresoc.v:159466$8422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:159464$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o connect \Y $extend$libresoc.v:159464$8419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $not $not$libresoc.v:159468$8424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test connect \Y $not$libresoc.v:159468$8424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $not$libresoc.v:159471$8427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \Y $not$libresoc.v:159471$8427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" cell $or $or$libresoc.v:159470$8426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp connect \Y $or$libresoc.v:159470$8426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" cell $or $or$libresoc.v:159473$8429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] connect \Y $or$libresoc.v:159473$8429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:159464$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:159464$8419_Y connect \Y $pos$libresoc.v:159464$8420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" cell $reduce_or $reduce_or$libresoc.v:159467$8423 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target connect \Y $reduce_or$libresoc.v:159467$8423_Y end attribute \src "libresoc.v:159154.7-159154.20" process $proc$libresoc.v:159154$8440 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:159474.3-159485.6" process $proc$libresoc.v:159474$8430 assign { } { } assign $0\so[0:0] $1\so[0:0] attribute \src "libresoc.v:159475.5-159475.29" switch \initial attribute \src "libresoc.v:159475.9-159475.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" switch \oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\so[0:0] \xer_so$18 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\so[0:0] \xer_so end sync always update \so $0\so[0:0] end attribute \src "libresoc.v:159486.3-159497.6" process $proc$libresoc.v:159486$8431 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] attribute \src "libresoc.v:159487.5-159487.29" switch \initial attribute \src "libresoc.v:159487.9-159487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cr0[3:0] \cr_a attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cr0[3:0] { \is_negative \is_positive \$36 \so } end sync always update \cr0 $0\cr0[3:0] end attribute \src "libresoc.v:159498.3-159507.6" process $proc$libresoc.v:159498$8432 assign { } { } assign { } { } assign $0\xer_so$18[0:0]$8433 $1\xer_so$18[0:0]$8434 attribute \src "libresoc.v:159499.5-159499.29" switch \initial attribute \src "libresoc.v:159499.9-159499.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_so$18[0:0]$8434 \$41 case assign $1\xer_so$18[0:0]$8434 1'0 end sync always update \xer_so$18 $0\xer_so$18[0:0]$8433 end attribute \src "libresoc.v:159508.3-159517.6" process $proc$libresoc.v:159508$8435 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] attribute \src "libresoc.v:159509.5-159509.29" switch \initial attribute \src "libresoc.v:159509.9-159509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_so_ok[0:0] 1'1 case assign $1\xer_so_ok[0:0] 1'0 end sync always update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:159518.3-159527.6" process $proc$libresoc.v:159518$8436 assign { } { } assign { } { } assign $0\xer_ov$17[1:0]$8437 $1\xer_ov$17[1:0]$8438 attribute \src "libresoc.v:159519.5-159519.29" switch \initial attribute \src "libresoc.v:159519.9-159519.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_ov$17[1:0]$8438 \xer_ov case assign $1\xer_ov$17[1:0]$8438 2'00 end sync always update \xer_ov$17 $0\xer_ov$17[1:0]$8437 end attribute \src "libresoc.v:159528.3-159537.6" process $proc$libresoc.v:159528$8439 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] attribute \src "libresoc.v:159529.5-159529.29" switch \initial attribute \src "libresoc.v:159529.9-159529.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 case assign $1\xer_ov_ok[0:0] 1'0 end sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end connect \$19 $and$libresoc.v:159463$8418_Y connect \$22 $pos$libresoc.v:159464$8420_Y connect \$24 $eq$libresoc.v:159465$8421_Y connect \$26 $eq$libresoc.v:159466$8422_Y connect \$28 $reduce_or$libresoc.v:159467$8423_Y connect \$30 $not$libresoc.v:159468$8424_Y connect \$32 $and$libresoc.v:159469$8425_Y connect \$34 $or$libresoc.v:159470$8426_Y connect \$36 $not$libresoc.v:159471$8427_Y connect \$39 $and$libresoc.v:159472$8428_Y connect \$41 $or$libresoc.v:159473$8429_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \mul_op__write_cr0 connect \cr_a$16 \cr0 connect \o_ok$15 \o_ok connect \o$14 \o$21 [63:0] connect \is_positive \$32 connect \is_negative \msb_test connect \is_nzero \$28 connect \msb_test \target [63] connect \is_cmpeqb \$26 connect \is_cmp \$24 connect \target \o$21 [63:0] connect \o$21 \$22 connect \oe \$19 end attribute \src "libresoc.v:159558.1-159912.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 attribute \src "libresoc.v:159884.3-159895.6" wire width 4 $0\cr0[3:0] attribute \src "libresoc.v:159559.7-159559.20" wire $0\initial[0:0] attribute \src "libresoc.v:159884.3-159895.6" wire width 4 $1\cr0[3:0] attribute \src "libresoc.v:159881.18-159881.112" wire $and$libresoc.v:159881$8447_Y attribute \src "libresoc.v:159877.18-159877.122" wire $eq$libresoc.v:159877$8443_Y attribute \src "libresoc.v:159878.18-159878.122" wire $eq$libresoc.v:159878$8444_Y attribute \src "libresoc.v:159876.18-159876.101" wire width 65 $extend$libresoc.v:159876$8441_Y attribute \src "libresoc.v:159880.18-159880.107" wire $not$libresoc.v:159880$8446_Y attribute \src "libresoc.v:159883.18-159883.107" wire $not$libresoc.v:159883$8449_Y attribute \src "libresoc.v:159882.18-159882.115" wire $or$libresoc.v:159882$8448_Y attribute \src "libresoc.v:159876.18-159876.101" wire width 65 $pos$libresoc.v:159876$8442_Y attribute \src "libresoc.v:159879.18-159879.105" wire $reduce_or$libresoc.v:159879$8445_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 20 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 44 \cr_a_ok attribute \src "libresoc.v:159559.7-159559.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire \is_cmpeqb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" wire \is_negative attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire \is_nzero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 47 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 18 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 41 \o$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 19 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 42 \o_ok$20 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 26 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \sr_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 34 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 17 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 40 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 22 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 45 \xer_ca$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 46 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $and $and$libresoc.v:159881$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 connect \Y $and$libresoc.v:159881$8447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" cell $eq $eq$libresoc.v:159877$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:159877$8443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" cell $eq $eq$libresoc.v:159878$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 connect \Y $eq$libresoc.v:159878$8444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:159876$8441 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o connect \Y $extend$libresoc.v:159876$8441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $not $not$libresoc.v:159880$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test connect \Y $not$libresoc.v:159880$8446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $not$libresoc.v:159883$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \Y $not$libresoc.v:159883$8449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" cell $or $or$libresoc.v:159882$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp connect \Y $or$libresoc.v:159882$8448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:159876$8442 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:159876$8441_Y connect \Y $pos$libresoc.v:159876$8442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" cell $reduce_or $reduce_or$libresoc.v:159879$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target connect \Y $reduce_or$libresoc.v:159879$8445_Y end attribute \src "libresoc.v:159559.7-159559.20" process $proc$libresoc.v:159559$8451 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:159884.3-159895.6" process $proc$libresoc.v:159884$8450 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] attribute \src "libresoc.v:159885.5-159885.29" switch \initial attribute \src "libresoc.v:159885.9-159885.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" switch \$36 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cr0[3:0] \cr_a attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cr0[3:0] { \is_negative \is_positive \$38 \xer_so } end sync always update \cr0 $0\cr0[3:0] end connect \$24 $pos$libresoc.v:159876$8442_Y connect \$26 $eq$libresoc.v:159877$8443_Y connect \$28 $eq$libresoc.v:159878$8444_Y connect \$30 $reduce_or$libresoc.v:159879$8445_Y connect \$32 $not$libresoc.v:159880$8446_Y connect \$34 $and$libresoc.v:159881$8447_Y connect \$36 $or$libresoc.v:159882$8448_Y connect \$38 $not$libresoc.v:159883$8449_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 connect \cr_a$21 \cr0 connect \o_ok$20 \o_ok connect \o$19 \o$23 [63:0] connect \is_positive \$34 connect \is_negative \msb_test connect \is_nzero \$30 connect \msb_test \target [63] connect \is_cmpeqb \$28 connect \is_cmp \$26 connect \xer_ca_ok \sr_op__output_carry connect \xer_ca$22 \xer_ca connect \target \o$23 [63:0] connect \o$23 \$24 end attribute \src "libresoc.v:159916.1-160283.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 attribute \src "libresoc.v:160258.3-160269.6" wire width 4 $0\cr0[3:0] attribute \src "libresoc.v:159917.7-159917.20" wire $0\initial[0:0] attribute \src "libresoc.v:160246.3-160257.6" wire width 65 $0\o$23[64:0]$8465 attribute \src "libresoc.v:160258.3-160269.6" wire width 4 $1\cr0[3:0] attribute \src "libresoc.v:160246.3-160257.6" wire width 65 $1\o$23[64:0]$8466 attribute \src "libresoc.v:160243.18-160243.112" wire $and$libresoc.v:160243$8461_Y attribute \src "libresoc.v:160239.18-160239.127" wire $eq$libresoc.v:160239$8457_Y attribute \src "libresoc.v:160240.18-160240.127" wire $eq$libresoc.v:160240$8458_Y attribute \src "libresoc.v:160237.18-160237.103" wire width 65 $extend$libresoc.v:160237$8453_Y attribute \src "libresoc.v:160238.18-160238.101" wire width 65 $extend$libresoc.v:160238$8455_Y attribute \src "libresoc.v:160236.18-160236.100" wire width 64 $not$libresoc.v:160236$8452_Y attribute \src "libresoc.v:160242.18-160242.107" wire $not$libresoc.v:160242$8460_Y attribute \src "libresoc.v:160245.18-160245.107" wire $not$libresoc.v:160245$8463_Y attribute \src "libresoc.v:160244.18-160244.115" wire $or$libresoc.v:160244$8462_Y attribute \src "libresoc.v:160237.18-160237.103" wire width 65 $pos$libresoc.v:160237$8454_Y attribute \src "libresoc.v:160238.18-160238.101" wire width 65 $pos$libresoc.v:160238$8456_Y attribute \src "libresoc.v:160241.18-160241.105" wire $reduce_or$libresoc.v:160241$8459_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 45 \cr_a_ok attribute \src "libresoc.v:159917.7-159917.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire \is_cmpeqb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" wire \is_negative attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire \is_nzero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 40 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 25 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 26 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 34 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 41 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 24 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 42 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 43 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $and $and$libresoc.v:160243$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 connect \Y $and$libresoc.v:160243$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" cell $eq $eq$libresoc.v:160239$8457 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:160239$8457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" cell $eq $eq$libresoc.v:160240$8458 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 connect \Y $eq$libresoc.v:160240$8458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $pos $extend$libresoc.v:160237$8453 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 connect \Y $extend$libresoc.v:160237$8453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:160238$8455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o connect \Y $extend$libresoc.v:160238$8455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $not $not$libresoc.v:160236$8452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o connect \Y $not$libresoc.v:160236$8452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $not $not$libresoc.v:160242$8460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test connect \Y $not$libresoc.v:160242$8460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $not$libresoc.v:160245$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \Y $not$libresoc.v:160245$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" cell $or $or$libresoc.v:160244$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp connect \Y $or$libresoc.v:160244$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $pos $pos$libresoc.v:160237$8454 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:160237$8453_Y connect \Y $pos$libresoc.v:160237$8454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:160238$8456 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:160238$8455_Y connect \Y $pos$libresoc.v:160238$8456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" cell $reduce_or $reduce_or$libresoc.v:160241$8459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target connect \Y $reduce_or$libresoc.v:160241$8459_Y end attribute \src "libresoc.v:159917.7-159917.20" process $proc$libresoc.v:159917$8468 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:160246.3-160257.6" process $proc$libresoc.v:160246$8464 assign { } { } assign $0\o$23[64:0]$8465 $1\o$23[64:0]$8466 attribute \src "libresoc.v:160247.5-160247.29" switch \initial attribute \src "libresoc.v:160247.9-160247.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" switch \logical_op__invert_out attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o$23[64:0]$8466 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o$23[64:0]$8466 \$28 end sync always update \o$23 $0\o$23[64:0]$8465 end attribute \src "libresoc.v:160258.3-160269.6" process $proc$libresoc.v:160258$8467 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] attribute \src "libresoc.v:160259.5-160259.29" switch \initial attribute \src "libresoc.v:160259.9-160259.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" switch \$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cr0[3:0] \cr_a attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cr0[3:0] { \is_negative \is_positive \$42 \xer_so } end sync always update \cr0 $0\cr0[3:0] end connect \$25 $not$libresoc.v:160236$8452_Y connect \$24 $pos$libresoc.v:160237$8454_Y connect \$28 $pos$libresoc.v:160238$8456_Y connect \$30 $eq$libresoc.v:160239$8457_Y connect \$32 $eq$libresoc.v:160240$8458_Y connect \$34 $reduce_or$libresoc.v:160241$8459_Y connect \$36 $not$libresoc.v:160242$8460_Y connect \$38 $and$libresoc.v:160243$8461_Y connect \$40 $or$libresoc.v:160244$8462_Y connect \$42 $not$libresoc.v:160245$8463_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 connect \cr_a$22 \cr0 connect \o_ok$21 \o_ok connect \o$20 \o$23 [63:0] connect \is_positive \$38 connect \is_negative \msb_test connect \is_nzero \$34 connect \msb_test \target [63] connect \is_cmpeqb \$32 connect \is_cmp \$30 connect \target \o$23 [63:0] end attribute \src "libresoc.v:160287.1-160737.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 attribute \src "libresoc.v:160658.3-160669.6" wire width 4 $0\cr0[3:0] attribute \src "libresoc.v:160288.7-160288.20" wire $0\initial[0:0] attribute \src "libresoc.v:160670.3-160681.6" wire width 65 $0\o$27[64:0]$8487 attribute \src "libresoc.v:160646.3-160657.6" wire $0\so[0:0] attribute \src "libresoc.v:160702.3-160711.6" wire width 2 $0\xer_ov$23[1:0]$8494 attribute \src "libresoc.v:160712.3-160721.6" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:160682.3-160691.6" wire $0\xer_so$24[0:0]$8490 attribute \src "libresoc.v:160692.3-160701.6" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:160658.3-160669.6" wire width 4 $1\cr0[3:0] attribute \src "libresoc.v:160670.3-160681.6" wire width 65 $1\o$27[64:0]$8488 attribute \src "libresoc.v:160646.3-160657.6" wire $1\so[0:0] attribute \src "libresoc.v:160702.3-160711.6" wire width 2 $1\xer_ov$23[1:0]$8495 attribute \src "libresoc.v:160712.3-160721.6" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:160682.3-160691.6" wire $1\xer_so$24[0:0]$8491 attribute \src "libresoc.v:160692.3-160701.6" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:160633.18-160633.136" wire $and$libresoc.v:160633$8469_Y attribute \src "libresoc.v:160641.18-160641.112" wire $and$libresoc.v:160641$8479_Y attribute \src "libresoc.v:160644.18-160644.133" wire $and$libresoc.v:160644$8482_Y attribute \src "libresoc.v:160637.18-160637.127" wire $eq$libresoc.v:160637$8475_Y attribute \src "libresoc.v:160638.18-160638.127" wire $eq$libresoc.v:160638$8476_Y attribute \src "libresoc.v:160635.18-160635.103" wire width 65 $extend$libresoc.v:160635$8471_Y attribute \src "libresoc.v:160636.18-160636.101" wire width 65 $extend$libresoc.v:160636$8473_Y attribute \src "libresoc.v:160634.18-160634.100" wire width 64 $not$libresoc.v:160634$8470_Y attribute \src "libresoc.v:160640.18-160640.107" wire $not$libresoc.v:160640$8478_Y attribute \src "libresoc.v:160643.18-160643.107" wire $not$libresoc.v:160643$8481_Y attribute \src "libresoc.v:160642.18-160642.115" wire $or$libresoc.v:160642$8480_Y attribute \src "libresoc.v:160645.18-160645.112" wire $or$libresoc.v:160645$8483_Y attribute \src "libresoc.v:160635.18-160635.103" wire width 65 $pos$libresoc.v:160635$8472_Y attribute \src "libresoc.v:160636.18-160636.101" wire width 65 $pos$libresoc.v:160636$8474_Y attribute \src "libresoc.v:160639.18-160639.105" wire $reduce_or$libresoc.v:160639$8477_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 65 \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 46 \cr_a_ok attribute \src "libresoc.v:160288.7-160288.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" wire \is_cmpeqb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" wire \is_negative attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" wire \is_nzero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 41 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 26 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 27 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 35 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 42 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 25 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 24 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 19 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 43 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 20 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 44 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" wire \oe$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 22 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 47 \xer_ov$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 48 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 23 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_so$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" cell $and $and$libresoc.v:160633$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok connect \Y $and$libresoc.v:160633$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $and $and$libresoc.v:160641$8479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 connect \Y $and$libresoc.v:160641$8479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" cell $and $and$libresoc.v:160644$8482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok connect \Y $and$libresoc.v:160644$8482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" cell $eq $eq$libresoc.v:160637$8475 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 connect \Y $eq$libresoc.v:160637$8475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" cell $eq $eq$libresoc.v:160638$8476 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 connect \Y $eq$libresoc.v:160638$8476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $pos $extend$libresoc.v:160635$8471 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 connect \Y $extend$libresoc.v:160635$8471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:160636$8473 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o connect \Y $extend$libresoc.v:160636$8473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $not $not$libresoc.v:160634$8470 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o connect \Y $not$libresoc.v:160634$8470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" cell $not $not$libresoc.v:160640$8478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test connect \Y $not$libresoc.v:160640$8478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" cell $not $not$libresoc.v:160643$8481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero connect \Y $not$libresoc.v:160643$8481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" cell $or $or$libresoc.v:160642$8480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp connect \Y $or$libresoc.v:160642$8480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" cell $or $or$libresoc.v:160645$8483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] connect \Y $or$libresoc.v:160645$8483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" cell $pos $pos$libresoc.v:160635$8472 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:160635$8471_Y connect \Y $pos$libresoc.v:160635$8472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:160636$8474 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:160636$8473_Y connect \Y $pos$libresoc.v:160636$8474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" cell $reduce_or $reduce_or$libresoc.v:160639$8477 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target connect \Y $reduce_or$libresoc.v:160639$8477_Y end attribute \src "libresoc.v:160288.7-160288.20" process $proc$libresoc.v:160288$8497 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:160646.3-160657.6" process $proc$libresoc.v:160646$8484 assign { } { } assign $0\so[0:0] $1\so[0:0] attribute \src "libresoc.v:160647.5-160647.29" switch \initial attribute \src "libresoc.v:160647.9-160647.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" switch \oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\so[0:0] \xer_so$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\so[0:0] \xer_so end sync always update \so $0\so[0:0] end attribute \src "libresoc.v:160658.3-160669.6" process $proc$libresoc.v:160658$8485 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] attribute \src "libresoc.v:160659.5-160659.29" switch \initial attribute \src "libresoc.v:160659.9-160659.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cr0[3:0] \cr_a attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } end sync always update \cr0 $0\cr0[3:0] end attribute \src "libresoc.v:160670.3-160681.6" process $proc$libresoc.v:160670$8486 assign { } { } assign $0\o$27[64:0]$8487 $1\o$27[64:0]$8488 attribute \src "libresoc.v:160671.5-160671.29" switch \initial attribute \src "libresoc.v:160671.9-160671.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" switch \logical_op__invert_out attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o$27[64:0]$8488 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o$27[64:0]$8488 \$32 end sync always update \o$27 $0\o$27[64:0]$8487 end attribute \src "libresoc.v:160682.3-160691.6" process $proc$libresoc.v:160682$8489 assign { } { } assign { } { } assign $0\xer_so$24[0:0]$8490 $1\xer_so$24[0:0]$8491 attribute \src "libresoc.v:160683.5-160683.29" switch \initial attribute \src "libresoc.v:160683.9-160683.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_so$24[0:0]$8491 \$51 case assign $1\xer_so$24[0:0]$8491 1'0 end sync always update \xer_so$24 $0\xer_so$24[0:0]$8490 end attribute \src "libresoc.v:160692.3-160701.6" process $proc$libresoc.v:160692$8492 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] attribute \src "libresoc.v:160693.5-160693.29" switch \initial attribute \src "libresoc.v:160693.9-160693.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_so_ok[0:0] 1'1 case assign $1\xer_so_ok[0:0] 1'0 end sync always update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:160702.3-160711.6" process $proc$libresoc.v:160702$8493 assign { } { } assign { } { } assign $0\xer_ov$23[1:0]$8494 $1\xer_ov$23[1:0]$8495 attribute \src "libresoc.v:160703.5-160703.29" switch \initial attribute \src "libresoc.v:160703.9-160703.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_ov$23[1:0]$8495 \xer_ov case assign $1\xer_ov$23[1:0]$8495 2'00 end sync always update \xer_ov$23 $0\xer_ov$23[1:0]$8494 end attribute \src "libresoc.v:160712.3-160721.6" process $proc$libresoc.v:160712$8496 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] attribute \src "libresoc.v:160713.5-160713.29" switch \initial attribute \src "libresoc.v:160713.9-160713.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" switch \oe$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 case assign $1\xer_ov_ok[0:0] 1'0 end sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end connect \$25 $and$libresoc.v:160633$8469_Y connect \$29 $not$libresoc.v:160634$8470_Y connect \$28 $pos$libresoc.v:160635$8472_Y connect \$32 $pos$libresoc.v:160636$8474_Y connect \$34 $eq$libresoc.v:160637$8475_Y connect \$36 $eq$libresoc.v:160638$8476_Y connect \$38 $reduce_or$libresoc.v:160639$8477_Y connect \$40 $not$libresoc.v:160640$8478_Y connect \$42 $and$libresoc.v:160641$8479_Y connect \$44 $or$libresoc.v:160642$8480_Y connect \$46 $not$libresoc.v:160643$8481_Y connect \$49 $and$libresoc.v:160644$8482_Y connect \$51 $or$libresoc.v:160645$8483_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 connect \cr_a$22 \cr0 connect \o_ok$21 \o_ok connect \o$20 \o$27 [63:0] connect \is_positive \$42 connect \is_negative \msb_test connect \is_nzero \$38 connect \msb_test \target [63] connect \is_cmpeqb \$36 connect \is_cmp \$34 connect \target \o$27 [63:0] connect \oe \$25 end attribute \src "libresoc.v:160741.1-161223.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage attribute \src "libresoc.v:160742.7-160742.20" wire $0\initial[0:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $0\o[63:0] attribute \src "libresoc.v:161176.3-161209.6" wire $0\ov[0:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $1\o[63:0] attribute \src "libresoc.v:161176.3-161209.6" wire $1\ov[0:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $2\o[63:0] attribute \src "libresoc.v:161176.3-161209.6" wire $2\ov[0:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $3\o[63:0] attribute \src "libresoc.v:161176.3-161209.6" wire $3\ov[0:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $4\o[63:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $5\o[63:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $6\o[63:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $7\o[63:0] attribute \src "libresoc.v:161104.3-161175.6" wire width 64 $8\o[63:0] attribute \src "libresoc.v:161095.18-161095.122" wire $and$libresoc.v:161095$8511_Y attribute \src "libresoc.v:161087.18-161087.109" wire width 65 $extend$libresoc.v:161087$8499_Y attribute \src "libresoc.v:161088.18-161088.100" wire width 65 $extend$libresoc.v:161088$8501_Y attribute \src "libresoc.v:161090.18-161090.113" wire width 65 $extend$libresoc.v:161090$8504_Y attribute \src "libresoc.v:161091.18-161091.104" wire width 65 $extend$libresoc.v:161091$8506_Y attribute \src "libresoc.v:161099.18-161099.114" wire width 64 $extend$libresoc.v:161099$8515_Y attribute \src "libresoc.v:161100.18-161100.114" wire width 64 $extend$libresoc.v:161100$8517_Y attribute \src "libresoc.v:161101.18-161101.114" wire width 64 $extend$libresoc.v:161101$8519_Y attribute \src "libresoc.v:161102.18-161102.114" wire width 64 $extend$libresoc.v:161102$8521_Y attribute \src "libresoc.v:161103.18-161103.115" wire width 64 $extend$libresoc.v:161103$8523_Y attribute \src "libresoc.v:161096.18-161096.128" wire $ne$libresoc.v:161096$8512_Y attribute \src "libresoc.v:161087.18-161087.109" wire width 65 $neg$libresoc.v:161087$8500_Y attribute \src "libresoc.v:161090.18-161090.113" wire width 65 $neg$libresoc.v:161090$8505_Y attribute \src "libresoc.v:161093.18-161093.116" wire $not$libresoc.v:161093$8509_Y attribute \src "libresoc.v:161098.18-161098.99" wire $not$libresoc.v:161098$8514_Y attribute \src "libresoc.v:161088.18-161088.100" wire width 65 $pos$libresoc.v:161088$8502_Y attribute \src "libresoc.v:161091.18-161091.104" wire width 65 $pos$libresoc.v:161091$8507_Y attribute \src "libresoc.v:161097.18-161097.118" wire width 64 signed $pos$libresoc.v:161097$8513_Y attribute \src "libresoc.v:161099.18-161099.114" wire width 64 $pos$libresoc.v:161099$8516_Y attribute \src "libresoc.v:161100.18-161100.114" wire width 64 $pos$libresoc.v:161100$8518_Y attribute \src "libresoc.v:161101.18-161101.114" wire width 64 $pos$libresoc.v:161101$8520_Y attribute \src "libresoc.v:161102.18-161102.114" wire width 64 $pos$libresoc.v:161102$8522_Y attribute \src "libresoc.v:161103.18-161103.115" wire width 64 $pos$libresoc.v:161103$8524_Y attribute \src "libresoc.v:161089.18-161089.121" wire width 65 $ternary$libresoc.v:161089$8503_Y attribute \src "libresoc.v:161092.18-161092.122" wire width 65 $ternary$libresoc.v:161092$8508_Y attribute \src "libresoc.v:161086.18-161086.120" wire $xor$libresoc.v:161086$8498_Y attribute \src "libresoc.v:161094.18-161094.127" wire $xor$libresoc.v:161094$8510_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" wire width 65 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 65 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" wire width 65 \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" wire width 65 \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" wire width 65 \$30 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 65 \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" wire width 65 \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" wire width 64 \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" wire width 64 \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" wire width 64 \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" wire width 64 \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" wire width 64 \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" wire width 64 \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 24 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire input 22 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire input 23 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg attribute \src "libresoc.v:160742.7-160742.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 44 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 29 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 30 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 38 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 45 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 28 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 42 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 43 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 41 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 27 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 46 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 47 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" wire \ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" wire width 65 \quotient_65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" wire \quotient_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 input 25 \quotient_root attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 input 26 \remainder attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" wire width 64 \remainder_64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" wire \remainder_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" wire width 32 \remainder_s32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" wire width 64 \remainder_s32_as_s64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 48 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 19 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" cell $and $and$libresoc.v:161095$8511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 connect \Y $and$libresoc.v:161095$8511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" cell $pos $extend$libresoc.v:161087$8499 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root connect \Y $extend$libresoc.v:161087$8499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" cell $pos $extend$libresoc.v:161088$8501 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root connect \Y $extend$libresoc.v:161088$8501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" cell $pos $extend$libresoc.v:161090$8504 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] connect \Y $extend$libresoc.v:161090$8504_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $extend$libresoc.v:161091$8506 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] connect \Y $extend$libresoc.v:161091$8506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" cell $pos $extend$libresoc.v:161099$8515 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] connect \Y $extend$libresoc.v:161099$8515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" cell $pos $extend$libresoc.v:161100$8517 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] connect \Y $extend$libresoc.v:161100$8517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" cell $pos $extend$libresoc.v:161101$8519 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] connect \Y $extend$libresoc.v:161101$8519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" cell $pos $extend$libresoc.v:161102$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] connect \Y $extend$libresoc.v:161102$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" cell $pos $extend$libresoc.v:161103$8523 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] connect \Y $extend$libresoc.v:161103$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" cell $ne $ne$libresoc.v:161096$8512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] connect \Y $ne$libresoc.v:161096$8512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" cell $neg $neg$libresoc.v:161087$8500 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:161087$8499_Y connect \Y $neg$libresoc.v:161087$8500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" cell $neg $neg$libresoc.v:161090$8505 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:161090$8504_Y connect \Y $neg$libresoc.v:161090$8505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" cell $not $not$libresoc.v:161093$8509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit connect \Y $not$libresoc.v:161093$8509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" cell $not $not$libresoc.v:161098$8514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov connect \Y $not$libresoc.v:161098$8514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" cell $pos $pos$libresoc.v:161088$8502 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:161088$8501_Y connect \Y $pos$libresoc.v:161088$8502_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $pos$libresoc.v:161091$8507 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:161091$8506_Y connect \Y $pos$libresoc.v:161091$8507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" cell $pos $pos$libresoc.v:161097$8513 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } connect \Y $pos$libresoc.v:161097$8513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" cell $pos $pos$libresoc.v:161099$8516 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:161099$8515_Y connect \Y $pos$libresoc.v:161099$8516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" cell $pos $pos$libresoc.v:161100$8518 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:161100$8517_Y connect \Y $pos$libresoc.v:161100$8518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" cell $pos $pos$libresoc.v:161101$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:161101$8519_Y connect \Y $pos$libresoc.v:161101$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" cell $pos $pos$libresoc.v:161102$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:161102$8521_Y connect \Y $pos$libresoc.v:161102$8522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" cell $pos $pos$libresoc.v:161103$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:161103$8523_Y connect \Y $pos$libresoc.v:161103$8524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" cell $mux $ternary$libresoc.v:161089$8503 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg connect \Y $ternary$libresoc.v:161089$8503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" cell $mux $ternary$libresoc.v:161092$8508 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg connect \Y $ternary$libresoc.v:161092$8508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" cell $xor $xor$libresoc.v:161086$8498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg connect \Y $xor$libresoc.v:161086$8498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" cell $xor $xor$libresoc.v:161094$8510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] connect \Y $xor$libresoc.v:161094$8510_Y end attribute \src "libresoc.v:160742.7-160742.20" process $proc$libresoc.v:160742$8527 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:161104.3-161175.6" process $proc$libresoc.v:161104$8525 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] attribute \src "libresoc.v:161105.5-161105.29" switch \initial attribute \src "libresoc.v:161105.9-161105.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" switch \$46 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o[63:0] $2\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0011110 assign { } { } assign $2\o[63:0] $3\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\o[63:0] $4\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" switch \logical_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\o[63:0] \$48 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $4\o[63:0] \$50 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\o[63:0] \quotient_65 [63:0] end attribute \src "libresoc.v:0.0-0.0" case 7'0011101 assign { } { } assign $2\o[63:0] $5\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\o[63:0] $6\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" switch \logical_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\o[63:0] \$52 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $6\o[63:0] \$54 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $5\o[63:0] \quotient_65 [63:0] end attribute \src "libresoc.v:0.0-0.0" case 7'0101111 assign { } { } assign $2\o[63:0] $7\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\o[63:0] $8\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" switch \logical_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\o[63:0] \remainder_s32_as_s64 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $8\o[63:0] \$56 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $7\o[63:0] \remainder_64 end case assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \o $0\o[63:0] end attribute \src "libresoc.v:161176.3-161209.6" process $proc$libresoc.v:161176$8526 assign { } { } assign $0\ov[0:0] $1\ov[0:0] attribute \src "libresoc.v:161177.5-161177.29" switch \initial attribute \src "libresoc.v:161177.9-161177.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" switch { \logical_op__is_signed \$36 \div_by_zero } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\ov[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign { } { } assign $1\ov[0:0] $2\ov[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" switch \$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ov[0:0] 1'1 case assign $2\ov[0:0] \dive_abs_ov64 end attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign { } { } assign $1\ov[0:0] $3\ov[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ov[0:0] 1'1 case assign $3\ov[0:0] \dive_abs_ov32 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\ov[0:0] \dive_abs_ov32 end sync always update \ov $0\ov[0:0] end connect \$21 $xor$libresoc.v:161086$8498_Y connect \$23 $neg$libresoc.v:161087$8500_Y connect \$25 $pos$libresoc.v:161088$8502_Y connect \$27 $ternary$libresoc.v:161089$8503_Y connect \$30 $neg$libresoc.v:161090$8505_Y connect \$32 $pos$libresoc.v:161091$8507_Y connect \$34 $ternary$libresoc.v:161092$8508_Y connect \$36 $not$libresoc.v:161093$8509_Y connect \$38 $xor$libresoc.v:161094$8510_Y connect \$40 $and$libresoc.v:161095$8511_Y connect \$42 $ne$libresoc.v:161096$8512_Y connect \$44 $pos$libresoc.v:161097$8513_Y connect \$46 $not$libresoc.v:161098$8514_Y connect \$48 $pos$libresoc.v:161099$8516_Y connect \$50 $pos$libresoc.v:161100$8518_Y connect \$52 $pos$libresoc.v:161101$8520_Y connect \$54 $pos$libresoc.v:161102$8522_Y connect \$56 $pos$libresoc.v:161103$8524_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so connect \remainder_s32_as_s64 \$44 connect \remainder_s32 \remainder_64 [31:0] connect \o_ok 1'1 connect \xer_ov { \ov \ov } connect \xer_ov_ok 1'1 connect \remainder_64 \$34 [63:0] connect \quotient_65 \$27 connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end attribute \src "libresoc.v:161227.1-161238.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p attribute \src "libresoc.v:161236.17-161236.111" wire $and$libresoc.v:161236$8528_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161236$8528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161236$8528_Y end connect \$1 $and$libresoc.v:161236$8528_Y connect \trigger \$1 end attribute \src "libresoc.v:161242.1-161253.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 attribute \src "libresoc.v:161251.17-161251.111" wire $and$libresoc.v:161251$8529_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161251$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161251$8529_Y end connect \$1 $and$libresoc.v:161251$8529_Y connect \trigger \$1 end attribute \src "libresoc.v:161257.1-161268.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 attribute \src "libresoc.v:161266.17-161266.111" wire $and$libresoc.v:161266$8530_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161266$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161266$8530_Y end connect \$1 $and$libresoc.v:161266$8530_Y connect \trigger \$1 end attribute \src "libresoc.v:161272.1-161283.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 attribute \src "libresoc.v:161281.17-161281.111" wire $and$libresoc.v:161281$8531_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161281$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161281$8531_Y end connect \$1 $and$libresoc.v:161281$8531_Y connect \trigger \$1 end attribute \src "libresoc.v:161287.1-161298.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 attribute \src "libresoc.v:161296.17-161296.111" wire $and$libresoc.v:161296$8532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161296$8532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161296$8532_Y end connect \$1 $and$libresoc.v:161296$8532_Y connect \trigger \$1 end attribute \src "libresoc.v:161302.1-161313.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 attribute \src "libresoc.v:161311.17-161311.111" wire $and$libresoc.v:161311$8533_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161311$8533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161311$8533_Y end connect \$1 $and$libresoc.v:161311$8533_Y connect \trigger \$1 end attribute \src "libresoc.v:161317.1-161328.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 attribute \src "libresoc.v:161326.17-161326.111" wire $and$libresoc.v:161326$8534_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161326$8534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161326$8534_Y end connect \$1 $and$libresoc.v:161326$8534_Y connect \trigger \$1 end attribute \src "libresoc.v:161332.1-161343.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 attribute \src "libresoc.v:161341.17-161341.111" wire $and$libresoc.v:161341$8535_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161341$8535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161341$8535_Y end connect \$1 $and$libresoc.v:161341$8535_Y connect \trigger \$1 end attribute \src "libresoc.v:161347.1-161358.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 attribute \src "libresoc.v:161356.17-161356.111" wire $and$libresoc.v:161356$8536_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161356$8536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161356$8536_Y end connect \$1 $and$libresoc.v:161356$8536_Y connect \trigger \$1 end attribute \src "libresoc.v:161362.1-161373.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 attribute \src "libresoc.v:161371.17-161371.111" wire $and$libresoc.v:161371$8537_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161371$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161371$8537_Y end connect \$1 $and$libresoc.v:161371$8537_Y connect \trigger \$1 end attribute \src "libresoc.v:161377.1-161388.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 attribute \src "libresoc.v:161386.17-161386.111" wire $and$libresoc.v:161386$8538_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161386$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161386$8538_Y end connect \$1 $and$libresoc.v:161386$8538_Y connect \trigger \$1 end attribute \src "libresoc.v:161392.1-161403.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 attribute \src "libresoc.v:161401.17-161401.111" wire $and$libresoc.v:161401$8539_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161401$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161401$8539_Y end connect \$1 $and$libresoc.v:161401$8539_Y connect \trigger \$1 end attribute \src "libresoc.v:161407.1-161418.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 attribute \src "libresoc.v:161416.17-161416.111" wire $and$libresoc.v:161416$8540_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161416$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161416$8540_Y end connect \$1 $and$libresoc.v:161416$8540_Y connect \trigger \$1 end attribute \src "libresoc.v:161422.1-161433.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 attribute \src "libresoc.v:161431.17-161431.111" wire $and$libresoc.v:161431$8541_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161431$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161431$8541_Y end connect \$1 $and$libresoc.v:161431$8541_Y connect \trigger \$1 end attribute \src "libresoc.v:161437.1-161448.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 attribute \src "libresoc.v:161446.17-161446.111" wire $and$libresoc.v:161446$8542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161446$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161446$8542_Y end connect \$1 $and$libresoc.v:161446$8542_Y connect \trigger \$1 end attribute \src "libresoc.v:161452.1-161463.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 attribute \src "libresoc.v:161461.17-161461.111" wire $and$libresoc.v:161461$8543_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161461$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161461$8543_Y end connect \$1 $and$libresoc.v:161461$8543_Y connect \trigger \$1 end attribute \src "libresoc.v:161467.1-161478.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 attribute \src "libresoc.v:161476.17-161476.111" wire $and$libresoc.v:161476$8544_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161476$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161476$8544_Y end connect \$1 $and$libresoc.v:161476$8544_Y connect \trigger \$1 end attribute \src "libresoc.v:161482.1-161493.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 attribute \src "libresoc.v:161491.17-161491.111" wire $and$libresoc.v:161491$8545_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161491$8545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161491$8545_Y end connect \$1 $and$libresoc.v:161491$8545_Y connect \trigger \$1 end attribute \src "libresoc.v:161497.1-161508.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 attribute \src "libresoc.v:161506.17-161506.111" wire $and$libresoc.v:161506$8546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161506$8546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161506$8546_Y end connect \$1 $and$libresoc.v:161506$8546_Y connect \trigger \$1 end attribute \src "libresoc.v:161512.1-161523.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 attribute \src "libresoc.v:161521.17-161521.111" wire $and$libresoc.v:161521$8547_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161521$8547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161521$8547_Y end connect \$1 $and$libresoc.v:161521$8547_Y connect \trigger \$1 end attribute \src "libresoc.v:161527.1-161538.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 attribute \src "libresoc.v:161536.17-161536.111" wire $and$libresoc.v:161536$8548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161536$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161536$8548_Y end connect \$1 $and$libresoc.v:161536$8548_Y connect \trigger \$1 end attribute \src "libresoc.v:161542.1-161553.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 attribute \src "libresoc.v:161551.17-161551.111" wire $and$libresoc.v:161551$8549_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161551$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161551$8549_Y end connect \$1 $and$libresoc.v:161551$8549_Y connect \trigger \$1 end attribute \src "libresoc.v:161557.1-161568.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 attribute \src "libresoc.v:161566.17-161566.111" wire $and$libresoc.v:161566$8550_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161566$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161566$8550_Y end connect \$1 $and$libresoc.v:161566$8550_Y connect \trigger \$1 end attribute \src "libresoc.v:161572.1-161583.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 attribute \src "libresoc.v:161581.17-161581.111" wire $and$libresoc.v:161581$8551_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161581$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161581$8551_Y end connect \$1 $and$libresoc.v:161581$8551_Y connect \trigger \$1 end attribute \src "libresoc.v:161587.1-161598.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 attribute \src "libresoc.v:161596.17-161596.111" wire $and$libresoc.v:161596$8552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161596$8552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161596$8552_Y end connect \$1 $and$libresoc.v:161596$8552_Y connect \trigger \$1 end attribute \src "libresoc.v:161602.1-161613.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 attribute \src "libresoc.v:161611.17-161611.111" wire $and$libresoc.v:161611$8553_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire input 1 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" cell $and $and$libresoc.v:161611$8553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o connect \Y $and$libresoc.v:161611$8553_Y end connect \$1 $and$libresoc.v:161611$8553_Y connect \trigger \$1 end attribute \src "libresoc.v:161617.1-161640.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick attribute \src "libresoc.v:161618.7-161618.20" wire $0\initial[0:0] attribute \src "libresoc.v:161629.3-161638.6" wire $0\o[0:0] attribute \src "libresoc.v:161629.3-161638.6" wire $1\o[0:0] attribute \src "libresoc.v:161628.17-161628.95" wire $eq$libresoc.v:161628$8554_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i attribute \src "libresoc.v:161618.7-161618.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" cell $eq $eq$libresoc.v:161628$8554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 connect \Y $eq$libresoc.v:161628$8554_Y end attribute \src "libresoc.v:161618.7-161618.20" process $proc$libresoc.v:161618$8556 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:161629.3-161638.6" process $proc$libresoc.v:161629$8555 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] attribute \src "libresoc.v:161630.5-161630.29" switch \initial attribute \src "libresoc.v:161630.9-161630.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" switch \i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o[0:0] 1'0 case assign $1\o[0:0] 1'0 end sync always update \o $0\o[0:0] end connect \$1 $eq$libresoc.v:161628$8554_Y connect \n \$1 end attribute \src "libresoc.v:161644.1-162458.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem attribute \src "libresoc.v:162421.3-162436.6" wire $0\adrok_l_r_addr_acked[0:0] attribute \src "libresoc.v:162385.3-162420.6" wire $0\adrok_l_s_addr_acked$next[0:0]$8646 attribute \src "libresoc.v:161943.3-161944.57" wire $0\adrok_l_s_addr_acked[0:0] attribute \src "libresoc.v:162035.3-162043.6" wire $0\busy_delay$next[0:0]$8614 attribute \src "libresoc.v:161941.3-161942.37" wire $0\busy_delay[0:0] attribute \src "libresoc.v:162369.3-162384.6" wire $0\busy_l_r_busy[0:0] attribute \src "libresoc.v:162359.3-162368.6" wire $0\busy_l_s_busy[0:0] attribute \src "libresoc.v:162349.3-162358.6" wire $0\cyc_l_r_cyc[0:0] attribute \src "libresoc.v:162330.3-162339.6" wire $0\cyc_l_s_cyc[0:0] attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $0\fsm_state$next[1:0]$8632 attribute \src "libresoc.v:161933.3-161934.35" wire width 2 $0\fsm_state[1:0] attribute \src "libresoc.v:161645.7-161645.20" wire $0\initial[0:0] attribute \src "libresoc.v:162231.3-162240.6" wire $0\ld_active_r_ld_active[0:0] attribute \src "libresoc.v:161939.3-161940.35" wire $0\lds_dly[0:0] attribute \src "libresoc.v:162164.3-162194.6" wire $0\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:162221.3-162230.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] attribute \src "libresoc.v:162241.3-162250.6" wire $0\ldst_port0_ld_data_o_ok[0:0] attribute \src "libresoc.v:162070.3-162085.6" wire width 4 $0\lenexp_addr_i[3:0] attribute \src "libresoc.v:162054.3-162069.6" wire width 4 $0\lenexp_len_i[3:0] attribute \src "libresoc.v:162340.3-162348.6" wire $0\lsui_active_dly$next[0:0]$8640 attribute \src "libresoc.v:161931.3-161932.47" wire $0\lsui_active_dly[0:0] attribute \src "libresoc.v:162271.3-162290.6" wire $0\lsui_busy[0:0] attribute \src "libresoc.v:161935.3-161936.36" wire $0\reset_delay[0:0] attribute \src "libresoc.v:162211.3-162220.6" wire $0\reset_l_r_reset[0:0] attribute \src "libresoc.v:162195.3-162210.6" wire $0\reset_l_s_reset[0:0] attribute \src "libresoc.v:162044.3-162053.6" wire $0\st_active_r_st_active[0:0] attribute \src "libresoc.v:162025.3-162034.6" wire $0\st_done_r_st_done[0:0] attribute \src "libresoc.v:162010.3-162024.6" wire $0\st_done_s_st_done$next[0:0]$8609 attribute \src "libresoc.v:161945.3-161946.51" wire $0\st_done_s_st_done[0:0] attribute \src "libresoc.v:162251.3-162260.6" wire width 64 $0\stdata[63:0] attribute \src "libresoc.v:161937.3-161938.35" wire $0\sts_dly[0:0] attribute \src "libresoc.v:162086.3-162111.6" wire $0\valid_l_s_valid[0:0] attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $0\x_addr_i[47:0] attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $0\x_mask_i[7:0] attribute \src "libresoc.v:162261.3-162270.6" wire width 64 $0\x_st_data_i[63:0] attribute \src "libresoc.v:162421.3-162436.6" wire $1\adrok_l_r_addr_acked[0:0] attribute \src "libresoc.v:162385.3-162420.6" wire $1\adrok_l_s_addr_acked$next[0:0]$8647 attribute \src "libresoc.v:161739.7-161739.34" wire $1\adrok_l_s_addr_acked[0:0] attribute \src "libresoc.v:162035.3-162043.6" wire $1\busy_delay$next[0:0]$8615 attribute \src "libresoc.v:161743.7-161743.24" wire $1\busy_delay[0:0] attribute \src "libresoc.v:162369.3-162384.6" wire $1\busy_l_r_busy[0:0] attribute \src "libresoc.v:162359.3-162368.6" wire $1\busy_l_s_busy[0:0] attribute \src "libresoc.v:162349.3-162358.6" wire $1\cyc_l_r_cyc[0:0] attribute \src "libresoc.v:162330.3-162339.6" wire $1\cyc_l_s_cyc[0:0] attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $1\fsm_state$next[1:0]$8633 attribute \src "libresoc.v:161765.13-161765.29" wire width 2 $1\fsm_state[1:0] attribute \src "libresoc.v:162231.3-162240.6" wire $1\ld_active_r_ld_active[0:0] attribute \src "libresoc.v:161779.7-161779.21" wire $1\lds_dly[0:0] attribute \src "libresoc.v:162164.3-162194.6" wire $1\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:162221.3-162230.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] attribute \src "libresoc.v:162241.3-162250.6" wire $1\ldst_port0_ld_data_o_ok[0:0] attribute \src "libresoc.v:162070.3-162085.6" wire width 4 $1\lenexp_addr_i[3:0] attribute \src "libresoc.v:162054.3-162069.6" wire width 4 $1\lenexp_len_i[3:0] attribute \src "libresoc.v:162340.3-162348.6" wire $1\lsui_active_dly$next[0:0]$8641 attribute \src "libresoc.v:161822.7-161822.29" wire $1\lsui_active_dly[0:0] attribute \src "libresoc.v:162271.3-162290.6" wire $1\lsui_busy[0:0] attribute \src "libresoc.v:161834.7-161834.25" wire $1\reset_delay[0:0] attribute \src "libresoc.v:162211.3-162220.6" wire $1\reset_l_r_reset[0:0] attribute \src "libresoc.v:162195.3-162210.6" wire $1\reset_l_s_reset[0:0] attribute \src "libresoc.v:162044.3-162053.6" wire $1\st_active_r_st_active[0:0] attribute \src "libresoc.v:162025.3-162034.6" wire $1\st_done_r_st_done[0:0] attribute \src "libresoc.v:162010.3-162024.6" wire $1\st_done_s_st_done$next[0:0]$8610 attribute \src "libresoc.v:161854.7-161854.31" wire $1\st_done_s_st_done[0:0] attribute \src "libresoc.v:162251.3-162260.6" wire width 64 $1\stdata[63:0] attribute \src "libresoc.v:161862.7-161862.21" wire $1\sts_dly[0:0] attribute \src "libresoc.v:162086.3-162111.6" wire $1\valid_l_s_valid[0:0] attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $1\x_addr_i[47:0] attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $1\x_mask_i[7:0] attribute \src "libresoc.v:162261.3-162270.6" wire width 64 $1\x_st_data_i[63:0] attribute \src "libresoc.v:162421.3-162436.6" wire $2\adrok_l_r_addr_acked[0:0] attribute \src "libresoc.v:162385.3-162420.6" wire $2\adrok_l_s_addr_acked$next[0:0]$8648 attribute \src "libresoc.v:162369.3-162384.6" wire $2\busy_l_r_busy[0:0] attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $2\fsm_state$next[1:0]$8634 attribute \src "libresoc.v:162164.3-162194.6" wire $2\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:162070.3-162085.6" wire width 4 $2\lenexp_addr_i[3:0] attribute \src "libresoc.v:162054.3-162069.6" wire width 4 $2\lenexp_len_i[3:0] attribute \src "libresoc.v:162271.3-162290.6" wire $2\lsui_busy[0:0] attribute \src "libresoc.v:162195.3-162210.6" wire $2\reset_l_s_reset[0:0] attribute \src "libresoc.v:162010.3-162024.6" wire $2\st_done_s_st_done$next[0:0]$8611 attribute \src "libresoc.v:162086.3-162111.6" wire $2\valid_l_s_valid[0:0] attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $2\x_addr_i[47:0] attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $2\x_mask_i[7:0] attribute \src "libresoc.v:162385.3-162420.6" wire $3\adrok_l_s_addr_acked$next[0:0]$8649 attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $3\fsm_state$next[1:0]$8635 attribute \src "libresoc.v:162164.3-162194.6" wire $3\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:162086.3-162111.6" wire $3\valid_l_s_valid[0:0] attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $3\x_addr_i[47:0] attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $3\x_mask_i[7:0] attribute \src "libresoc.v:162385.3-162420.6" wire $4\adrok_l_s_addr_acked$next[0:0]$8650 attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $4\fsm_state$next[1:0]$8636 attribute \src "libresoc.v:162164.3-162194.6" wire $4\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:162086.3-162111.6" wire $4\valid_l_s_valid[0:0] attribute \src "libresoc.v:162138.3-162163.6" wire width 48 $4\x_addr_i[47:0] attribute \src "libresoc.v:162112.3-162137.6" wire width 8 $4\x_mask_i[7:0] attribute \src "libresoc.v:162385.3-162420.6" wire $5\adrok_l_s_addr_acked$next[0:0]$8651 attribute \src "libresoc.v:162291.3-162329.6" wire width 2 $5\fsm_state$next[1:0]$8637 attribute \src "libresoc.v:162164.3-162194.6" wire $5\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:162385.3-162420.6" wire $6\adrok_l_s_addr_acked$next[0:0]$8652 attribute \src "libresoc.v:161891.18-161891.115" wire $and$libresoc.v:161891$8558_Y attribute \src "libresoc.v:161893.18-161893.95" wire $and$libresoc.v:161893$8560_Y attribute \src "libresoc.v:161895.17-161895.138" wire $and$libresoc.v:161895$8562_Y attribute \src "libresoc.v:161896.18-161896.95" wire $and$libresoc.v:161896$8563_Y attribute \src "libresoc.v:161899.18-161899.136" wire $and$libresoc.v:161899$8568_Y attribute \src "libresoc.v:161900.18-161900.136" wire $and$libresoc.v:161900$8569_Y attribute \src "libresoc.v:161901.18-161901.136" wire $and$libresoc.v:161901$8570_Y attribute \src "libresoc.v:161902.18-161902.136" wire $and$libresoc.v:161902$8571_Y attribute \src "libresoc.v:161903.18-161903.136" wire $and$libresoc.v:161903$8572_Y attribute \src "libresoc.v:161908.18-161908.119" wire width 176 $and$libresoc.v:161908$8577_Y attribute \src "libresoc.v:161911.18-161911.136" wire $and$libresoc.v:161911$8580_Y attribute \src "libresoc.v:161912.18-161912.136" wire $and$libresoc.v:161912$8581_Y attribute \src "libresoc.v:161914.18-161914.139" wire $and$libresoc.v:161914$8583_Y attribute \src "libresoc.v:161918.18-161918.139" wire $and$libresoc.v:161918$8587_Y attribute \src "libresoc.v:161920.18-161920.114" wire $and$libresoc.v:161920$8589_Y attribute \src "libresoc.v:161922.18-161922.114" wire $and$libresoc.v:161922$8591_Y attribute \src "libresoc.v:161926.18-161926.103" wire $and$libresoc.v:161926$8595_Y attribute \src "libresoc.v:161927.17-161927.135" wire $and$libresoc.v:161927$8596_Y attribute \src "libresoc.v:161930.18-161930.103" wire $and$libresoc.v:161930$8599_Y attribute \src "libresoc.v:161897.18-161897.109" wire width 4 $extend$libresoc.v:161897$8564_Y attribute \src "libresoc.v:161898.18-161898.109" wire width 4 $extend$libresoc.v:161898$8566_Y attribute \src "libresoc.v:161909.18-161909.112" wire width 8 $mul$libresoc.v:161909$8578_Y attribute \src "libresoc.v:161915.18-161915.112" wire width 8 $mul$libresoc.v:161915$8584_Y attribute \src "libresoc.v:161890.17-161890.103" wire $not$libresoc.v:161890$8557_Y attribute \src "libresoc.v:161892.18-161892.94" wire $not$libresoc.v:161892$8559_Y attribute \src "libresoc.v:161894.18-161894.94" wire $not$libresoc.v:161894$8561_Y attribute \src "libresoc.v:161904.18-161904.102" wire $not$libresoc.v:161904$8573_Y attribute \src "libresoc.v:161907.18-161907.97" wire $not$libresoc.v:161907$8576_Y attribute \src "libresoc.v:161913.18-161913.102" wire $not$libresoc.v:161913$8582_Y attribute \src "libresoc.v:161916.17-161916.103" wire $not$libresoc.v:161916$8585_Y attribute \src "libresoc.v:161923.18-161923.101" wire $not$libresoc.v:161923$8592_Y attribute \src "libresoc.v:161924.18-161924.111" wire $not$libresoc.v:161924$8593_Y attribute \src "libresoc.v:161925.18-161925.110" wire $not$libresoc.v:161925$8594_Y attribute \src "libresoc.v:161928.18-161928.102" wire $not$libresoc.v:161928$8597_Y attribute \src "libresoc.v:161929.18-161929.102" wire $not$libresoc.v:161929$8598_Y attribute \src "libresoc.v:161905.18-161905.111" wire $or$libresoc.v:161905$8574_Y attribute \src "libresoc.v:161906.17-161906.130" wire $or$libresoc.v:161906$8575_Y attribute \src "libresoc.v:161919.18-161919.130" wire $or$libresoc.v:161919$8588_Y attribute \src "libresoc.v:161921.18-161921.130" wire $or$libresoc.v:161921$8590_Y attribute \src "libresoc.v:161897.18-161897.109" wire width 4 $pos$libresoc.v:161897$8565_Y attribute \src "libresoc.v:161898.18-161898.109" wire width 4 $pos$libresoc.v:161898$8567_Y attribute \src "libresoc.v:161917.18-161917.121" wire width 319 $sshl$libresoc.v:161917$8586_Y attribute \src "libresoc.v:161910.18-161910.106" wire width 176 $sshr$libresoc.v:161910$8579_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 4 \$21 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 4 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" wire width 176 \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" wire width 176 \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" wire width 8 \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" wire width 176 \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" wire width 319 \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" wire width 8 \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" wire width 319 \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" wire \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" wire \$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" wire \$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \adrok_l_q_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \adrok_l_qn_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \adrok_l_r_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \adrok_l_s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \adrok_l_s_addr_acked$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" wire \busy_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" wire \busy_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" wire \busy_edge attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \busy_l_q_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 23 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \cyc_l_r_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \cyc_l_s_cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next attribute \src "libresoc.v:161645.7-161645.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \ld_active_r_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \ld_active_s_ld_active attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" wire width 64 \lddata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" wire \lds attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lds_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lds_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \lds_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 48 input 6 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 7 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire output 10 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire output 4 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 input 5 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire input 18 \ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire input 2 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 3 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 12 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 13 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 15 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 14 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" wire width 4 \lenexp_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" wire width 4 \lenexp_len_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" wire width 64 \lenexp_lexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 \lenexp_rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" wire \lsui_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lsui_active_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \lsui_active_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \lsui_active_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" wire \lsui_busy attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 input 11 \m_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" wire output 21 \m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" wire \reset_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" wire \reset_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \reset_l_q_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \reset_l_r_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \st_active_q_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \st_active_r_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \st_active_s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \st_done_q_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \st_done_r_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \st_done_s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \st_done_s_st_done$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" wire width 64 \stdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" wire \sts attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \sts_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \sts_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \sts_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \valid_l_q_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \valid_l_r_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \valid_l_s_valid attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 output 9 \x_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" wire input 17 \x_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" wire output 19 \x_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" wire width 8 output 8 \x_mask_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" wire width 64 output 16 \x_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" wire output 20 \x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" cell $and $and$libresoc.v:161891$8558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 connect \Y $and$libresoc.v:161891$8558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:161893$8560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 connect \Y $and$libresoc.v:161893$8560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" cell $and $and$libresoc.v:161895$8562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok connect \Y $and$libresoc.v:161895$8562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:161896$8563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 connect \Y $and$libresoc.v:161896$8563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" cell $and $and$libresoc.v:161899$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked connect \Y $and$libresoc.v:161899$8568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" cell $and $and$libresoc.v:161900$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked connect \Y $and$libresoc.v:161900$8569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" cell $and $and$libresoc.v:161901$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked connect \Y $and$libresoc.v:161901$8570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" cell $and $and$libresoc.v:161902$8571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked connect \Y $and$libresoc.v:161902$8571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" cell $and $and$libresoc.v:161903$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked connect \Y $and$libresoc.v:161903$8572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" cell $and $and$libresoc.v:161908$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 176 parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o connect \Y $and$libresoc.v:161908$8577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" cell $and $and$libresoc.v:161911$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked connect \Y $and$libresoc.v:161911$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" cell $and $and$libresoc.v:161912$8581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked connect \Y $and$libresoc.v:161912$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" cell $and $and$libresoc.v:161914$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok connect \Y $and$libresoc.v:161914$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" cell $and $and$libresoc.v:161918$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok connect \Y $and$libresoc.v:161918$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" cell $and $and$libresoc.v:161920$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid connect \Y $and$libresoc.v:161920$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" cell $and $and$libresoc.v:161922$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid connect \Y $and$libresoc.v:161922$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" cell $and $and$libresoc.v:161926$8595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 connect \Y $and$libresoc.v:161926$8595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" cell $and $and$libresoc.v:161927$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked connect \Y $and$libresoc.v:161927$8596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:161930$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 connect \Y $and$libresoc.v:161930$8599_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $extend$libresoc.v:161897$8564 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] connect \Y $extend$libresoc.v:161897$8564_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $extend$libresoc.v:161898$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] connect \Y $extend$libresoc.v:161898$8566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" cell $mul $mul$libresoc.v:161909$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 connect \Y $mul$libresoc.v:161909$8578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" cell $mul $mul$libresoc.v:161915$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 connect \Y $mul$libresoc.v:161915$8584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" cell $not $not$libresoc.v:161890$8557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay connect \Y $not$libresoc.v:161890$8557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:161892$8559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly connect \Y $not$libresoc.v:161892$8559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:161894$8561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly connect \Y $not$libresoc.v:161894$8561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" cell $not $not$libresoc.v:161904$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy connect \Y $not$libresoc.v:161904$8573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" cell $not $not$libresoc.v:161907$8576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 connect \Y $not$libresoc.v:161907$8576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" cell $not $not$libresoc.v:161913$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy connect \Y $not$libresoc.v:161913$8582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" cell $not $not$libresoc.v:161916$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay connect \Y $not$libresoc.v:161916$8585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" cell $not $not$libresoc.v:161923$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o connect \Y $not$libresoc.v:161923$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" cell $not $not$libresoc.v:161924$8593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i connect \Y $not$libresoc.v:161924$8593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" cell $not $not$libresoc.v:161925$8594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \Y $not$libresoc.v:161925$8594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" cell $not $not$libresoc.v:161928$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o connect \Y $not$libresoc.v:161928$8597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:161929$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly connect \Y $not$libresoc.v:161929$8598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" cell $or $or$libresoc.v:161905$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy connect \Y $or$libresoc.v:161905$8574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" cell $or $or$libresoc.v:161906$8575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i connect \Y $or$libresoc.v:161906$8575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" cell $or $or$libresoc.v:161919$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i connect \Y $or$libresoc.v:161919$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" cell $or $or$libresoc.v:161921$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i connect \Y $or$libresoc.v:161921$8590_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $pos$libresoc.v:161897$8565 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A $extend$libresoc.v:161897$8564_Y connect \Y $pos$libresoc.v:161897$8565_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" cell $pos $pos$libresoc.v:161898$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A $extend$libresoc.v:161898$8566_Y connect \Y $pos$libresoc.v:161898$8567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" cell $sshl $sshl$libresoc.v:161917$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 connect \Y $sshl$libresoc.v:161917$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" cell $sshr $sshr$libresoc.v:161910$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 connect \Y $sshr$libresoc.v:161910$8579_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:161947.11-161954.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_addr_acked \adrok_l_q_addr_acked connect \qn_addr_acked \adrok_l_qn_addr_acked connect \r_addr_acked \adrok_l_r_addr_acked connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 attribute \src "libresoc.v:161955.10-161961.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_busy \busy_l_q_busy connect \r_busy \busy_l_r_busy connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 attribute \src "libresoc.v:161962.9-161968.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_cyc \cyc_l_q_cyc connect \r_cyc \cyc_l_r_cyc connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 attribute \src "libresoc.v:161969.13-161975.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_ld_active \ld_active_q_ld_active connect \r_ld_active \ld_active_r_ld_active connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 attribute \src "libresoc.v:161976.10-161981.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i connect \lexp_o \lenexp_lexp_o connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 attribute \src "libresoc.v:161982.11-161988.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_reset \reset_l_q_reset connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 attribute \src "libresoc.v:161989.13-161995.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_st_active \st_active_q_st_active connect \r_st_active \st_active_r_st_active connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 attribute \src "libresoc.v:161996.11-162002.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_st_done \st_done_q_st_done connect \r_st_done \st_done_r_st_done connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 attribute \src "libresoc.v:162003.11-162009.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_valid \valid_l_q_valid connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end attribute \src "libresoc.v:161645.7-161645.20" process $proc$libresoc.v:161645$8654 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:161739.7-161739.34" process $proc$libresoc.v:161739$8655 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end attribute \src "libresoc.v:161743.7-161743.24" process $proc$libresoc.v:161743$8656 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end attribute \src "libresoc.v:161765.13-161765.29" process $proc$libresoc.v:161765$8657 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end attribute \src "libresoc.v:161779.7-161779.21" process $proc$libresoc.v:161779$8658 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end attribute \src "libresoc.v:161822.7-161822.29" process $proc$libresoc.v:161822$8659 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end attribute \src "libresoc.v:161834.7-161834.25" process $proc$libresoc.v:161834$8660 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end attribute \src "libresoc.v:161854.7-161854.31" process $proc$libresoc.v:161854$8661 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end attribute \src "libresoc.v:161862.7-161862.21" process $proc$libresoc.v:161862$8662 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end attribute \src "libresoc.v:161931.3-161932.47" process $proc$libresoc.v:161931$8600 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end attribute \src "libresoc.v:161933.3-161934.35" process $proc$libresoc.v:161933$8601 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end attribute \src "libresoc.v:161935.3-161936.36" process $proc$libresoc.v:161935$8602 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end attribute \src "libresoc.v:161937.3-161938.35" process $proc$libresoc.v:161937$8603 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end attribute \src "libresoc.v:161939.3-161940.35" process $proc$libresoc.v:161939$8604 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end attribute \src "libresoc.v:161941.3-161942.37" process $proc$libresoc.v:161941$8605 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end attribute \src "libresoc.v:161943.3-161944.57" process $proc$libresoc.v:161943$8606 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end attribute \src "libresoc.v:161945.3-161946.51" process $proc$libresoc.v:161945$8607 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end attribute \src "libresoc.v:162010.3-162024.6" process $proc$libresoc.v:162010$8608 assign { } { } assign { } { } assign { } { } assign $0\st_done_s_st_done$next[0:0]$8609 $2\st_done_s_st_done$next[0:0]$8611 attribute \src "libresoc.v:162011.5-162011.29" switch \initial attribute \src "libresoc.v:162011.9-162011.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\st_done_s_st_done$next[0:0]$8610 1'1 case assign $1\st_done_s_st_done$next[0:0]$8610 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\st_done_s_st_done$next[0:0]$8611 1'0 case assign $2\st_done_s_st_done$next[0:0]$8611 $1\st_done_s_st_done$next[0:0]$8610 end sync always update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8609 end attribute \src "libresoc.v:162025.3-162034.6" process $proc$libresoc.v:162025$8612 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] attribute \src "libresoc.v:162026.5-162026.29" switch \initial attribute \src "libresoc.v:162026.9-162026.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\st_done_r_st_done[0:0] 1'1 case assign $1\st_done_r_st_done[0:0] 1'0 end sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end attribute \src "libresoc.v:162035.3-162043.6" process $proc$libresoc.v:162035$8613 assign { } { } assign { } { } assign $0\busy_delay$next[0:0]$8614 $1\busy_delay$next[0:0]$8615 attribute \src "libresoc.v:162036.5-162036.29" switch \initial attribute \src "libresoc.v:162036.9-162036.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\busy_delay$next[0:0]$8615 1'0 case assign $1\busy_delay$next[0:0]$8615 \ldst_port0_busy_o end sync always update \busy_delay$next $0\busy_delay$next[0:0]$8614 end attribute \src "libresoc.v:162044.3-162053.6" process $proc$libresoc.v:162044$8616 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] attribute \src "libresoc.v:162045.5-162045.29" switch \initial attribute \src "libresoc.v:162045.9-162045.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\st_active_r_st_active[0:0] 1'1 case assign $1\st_active_r_st_active[0:0] 1'0 end sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end attribute \src "libresoc.v:162054.3-162069.6" process $proc$libresoc.v:162054$8617 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] attribute \src "libresoc.v:162055.5-162055.29" switch \initial attribute \src "libresoc.v:162055.9-162055.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\lenexp_len_i[3:0] \ldst_port0_data_len case assign $1\lenexp_len_i[3:0] 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\lenexp_len_i[3:0] \ldst_port0_data_len case assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] end sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end attribute \src "libresoc.v:162070.3-162085.6" process $proc$libresoc.v:162070$8618 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] attribute \src "libresoc.v:162071.5-162071.29" switch \initial attribute \src "libresoc.v:162071.9-162071.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\lenexp_addr_i[3:0] \$21 case assign $1\lenexp_addr_i[3:0] 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\lenexp_addr_i[3:0] \$23 case assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] end sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end attribute \src "libresoc.v:162086.3-162111.6" process $proc$libresoc.v:162086$8619 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] attribute \src "libresoc.v:162087.5-162087.29" switch \initial attribute \src "libresoc.v:162087.9-162087.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\valid_l_s_valid[0:0] 1'1 case assign $2\valid_l_s_valid[0:0] 1'0 end case assign $1\valid_l_s_valid[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\valid_l_s_valid[0:0] 1'1 case assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] end case assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] end sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end attribute \src "libresoc.v:162112.3-162137.6" process $proc$libresoc.v:162112$8620 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] attribute \src "libresoc.v:162113.5-162113.29" switch \initial attribute \src "libresoc.v:162113.9-162113.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] case assign $2\x_mask_i[7:0] 8'00000000 end case assign $1\x_mask_i[7:0] 8'00000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] case assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] end case assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] end sync always update \x_mask_i $0\x_mask_i[7:0] end attribute \src "libresoc.v:162138.3-162163.6" process $proc$libresoc.v:162138$8621 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] attribute \src "libresoc.v:162139.5-162139.29" switch \initial attribute \src "libresoc.v:162139.9-162139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\x_addr_i[47:0] \ldst_port0_addr_i case assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 end case assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\x_addr_i[47:0] \ldst_port0_addr_i case assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] end case assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] end sync always update \x_addr_i $0\x_addr_i[47:0] end attribute \src "libresoc.v:162164.3-162194.6" process $proc$libresoc.v:162164$8622 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] attribute \src "libresoc.v:162165.5-162165.29" switch \initial attribute \src "libresoc.v:162165.9-162165.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ldst_port0_addr_ok_o[0:0] 1'1 case assign $2\ldst_port0_addr_ok_o[0:0] 1'0 end case assign $1\ldst_port0_addr_ok_o[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\ldst_port0_addr_ok_o[0:0] 1'1 case assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] end case assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] end case assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] end sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end attribute \src "libresoc.v:162195.3-162210.6" process $proc$libresoc.v:162195$8623 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] attribute \src "libresoc.v:162196.5-162196.29" switch \initial attribute \src "libresoc.v:162196.9-162196.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reset_l_s_reset[0:0] \$35 case assign $1\reset_l_s_reset[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" switch \st_done_q_st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reset_l_s_reset[0:0] \$37 case assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] end sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end attribute \src "libresoc.v:162211.3-162220.6" process $proc$libresoc.v:162211$8624 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] attribute \src "libresoc.v:162212.5-162212.29" switch \initial attribute \src "libresoc.v:162212.9-162212.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reset_l_r_reset[0:0] 1'1 case assign $1\reset_l_r_reset[0:0] 1'0 end sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end attribute \src "libresoc.v:162221.3-162230.6" process $proc$libresoc.v:162221$8625 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] attribute \src "libresoc.v:162222.5-162222.29" switch \initial attribute \src "libresoc.v:162222.9-162222.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_ld_data_o[63:0] \lddata case assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end attribute \src "libresoc.v:162231.3-162240.6" process $proc$libresoc.v:162231$8626 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] attribute \src "libresoc.v:162232.5-162232.29" switch \initial attribute \src "libresoc.v:162232.9-162232.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ld_active_r_ld_active[0:0] 1'1 case assign $1\ld_active_r_ld_active[0:0] 1'0 end sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end attribute \src "libresoc.v:162241.3-162250.6" process $proc$libresoc.v:162241$8627 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] attribute \src "libresoc.v:162242.5-162242.29" switch \initial attribute \src "libresoc.v:162242.9-162242.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" switch \$50 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 case assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 end sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end attribute \src "libresoc.v:162251.3-162260.6" process $proc$libresoc.v:162251$8628 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] attribute \src "libresoc.v:162252.5-162252.29" switch \initial attribute \src "libresoc.v:162252.9-162252.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" switch \$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\stdata[63:0] \$56 [63:0] case assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \stdata $0\stdata[63:0] end attribute \src "libresoc.v:162261.3-162270.6" process $proc$libresoc.v:162261$8629 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] attribute \src "libresoc.v:162262.5-162262.29" switch \initial attribute \src "libresoc.v:162262.9-162262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\x_st_data_i[63:0] \stdata case assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \x_st_data_i $0\x_st_data_i[63:0] end attribute \src "libresoc.v:162271.3-162290.6" process $proc$libresoc.v:162271$8630 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] attribute \src "libresoc.v:162272.5-162272.29" switch \initial attribute \src "libresoc.v:162272.9-162272.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$65 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\lsui_busy[0:0] 1'1 case assign $2\lsui_busy[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\lsui_busy[0:0] 1'1 case assign $1\lsui_busy[0:0] 1'0 end sync always update \lsui_busy $0\lsui_busy[0:0] end attribute \src "libresoc.v:162291.3-162329.6" process $proc$libresoc.v:162291$8631 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$next[1:0]$8632 $5\fsm_state$next[1:0]$8637 attribute \src "libresoc.v:162292.5-162292.29" switch \initial attribute \src "libresoc.v:162292.9-162292.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\fsm_state$next[1:0]$8633 $2\fsm_state$next[1:0]$8634 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fsm_state$next[1:0]$8634 2'01 case assign $2\fsm_state$next[1:0]$8634 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\fsm_state$next[1:0]$8633 $3\fsm_state$next[1:0]$8635 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\fsm_state$next[1:0]$8635 2'10 case assign $3\fsm_state$next[1:0]$8635 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\fsm_state$next[1:0]$8633 $4\fsm_state$next[1:0]$8636 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\fsm_state$next[1:0]$8636 2'00 case assign $4\fsm_state$next[1:0]$8636 \fsm_state end case assign $1\fsm_state$next[1:0]$8633 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\fsm_state$next[1:0]$8637 2'00 case assign $5\fsm_state$next[1:0]$8637 $1\fsm_state$next[1:0]$8633 end sync always update \fsm_state$next $0\fsm_state$next[1:0]$8632 end attribute \src "libresoc.v:162330.3-162339.6" process $proc$libresoc.v:162330$8638 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] attribute \src "libresoc.v:162331.5-162331.29" switch \initial attribute \src "libresoc.v:162331.9-162331.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" switch \reset_l_s_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cyc_l_s_cyc[0:0] 1'1 case assign $1\cyc_l_s_cyc[0:0] 1'0 end sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end attribute \src "libresoc.v:162340.3-162348.6" process $proc$libresoc.v:162340$8639 assign { } { } assign { } { } assign $0\lsui_active_dly$next[0:0]$8640 $1\lsui_active_dly$next[0:0]$8641 attribute \src "libresoc.v:162341.5-162341.29" switch \initial attribute \src "libresoc.v:162341.9-162341.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\lsui_active_dly$next[0:0]$8641 1'0 case assign $1\lsui_active_dly$next[0:0]$8641 \lsui_active end sync always update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8640 end attribute \src "libresoc.v:162349.3-162358.6" process $proc$libresoc.v:162349$8642 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] attribute \src "libresoc.v:162350.5-162350.29" switch \initial attribute \src "libresoc.v:162350.9-162350.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" switch \cyc_l_q_cyc attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cyc_l_r_cyc[0:0] 1'1 case assign $1\cyc_l_r_cyc[0:0] 1'0 end sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end attribute \src "libresoc.v:162359.3-162368.6" process $proc$libresoc.v:162359$8643 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] attribute \src "libresoc.v:162360.5-162360.29" switch \initial attribute \src "libresoc.v:162360.9-162360.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\busy_l_s_busy[0:0] \$5 case assign $1\busy_l_s_busy[0:0] 1'0 end sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end attribute \src "libresoc.v:162369.3-162384.6" process $proc$libresoc.v:162369$8644 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] attribute \src "libresoc.v:162370.5-162370.29" switch \initial attribute \src "libresoc.v:162370.9-162370.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" switch \ldst_port0_exc_$signal attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\busy_l_r_busy[0:0] 1'1 case assign $1\busy_l_r_busy[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" switch \cyc_l_q_cyc attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\busy_l_r_busy[0:0] 1'1 case assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] end sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end attribute \src "libresoc.v:162385.3-162420.6" process $proc$libresoc.v:162385$8645 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\adrok_l_s_addr_acked$next[0:0]$8646 $6\adrok_l_s_addr_acked$next[0:0]$8652 attribute \src "libresoc.v:162386.5-162386.29" switch \initial attribute \src "libresoc.v:162386.9-162386.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\adrok_l_s_addr_acked$next[0:0]$8647 $2\adrok_l_s_addr_acked$next[0:0]$8648 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\adrok_l_s_addr_acked$next[0:0]$8648 1'1 case assign $2\adrok_l_s_addr_acked$next[0:0]$8648 1'0 end case assign $1\adrok_l_s_addr_acked$next[0:0]$8647 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\adrok_l_s_addr_acked$next[0:0]$8649 $4\adrok_l_s_addr_acked$next[0:0]$8650 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\adrok_l_s_addr_acked$next[0:0]$8650 $5\adrok_l_s_addr_acked$next[0:0]$8651 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\adrok_l_s_addr_acked$next[0:0]$8651 1'1 case assign $5\adrok_l_s_addr_acked$next[0:0]$8651 $1\adrok_l_s_addr_acked$next[0:0]$8647 end case assign $4\adrok_l_s_addr_acked$next[0:0]$8650 $1\adrok_l_s_addr_acked$next[0:0]$8647 end case assign $3\adrok_l_s_addr_acked$next[0:0]$8649 $1\adrok_l_s_addr_acked$next[0:0]$8647 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\adrok_l_s_addr_acked$next[0:0]$8652 1'0 case assign $6\adrok_l_s_addr_acked$next[0:0]$8652 $3\adrok_l_s_addr_acked$next[0:0]$8649 end sync always update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8646 end attribute \src "libresoc.v:162421.3-162436.6" process $proc$libresoc.v:162421$8653 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] attribute \src "libresoc.v:162422.5-162422.29" switch \initial attribute \src "libresoc.v:162422.9-162422.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" switch \reset_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\adrok_l_r_addr_acked[0:0] 1'1 case assign $1\adrok_l_r_addr_acked[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\adrok_l_r_addr_acked[0:0] 1'1 case assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] end sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end connect \$9 $not$libresoc.v:161890$8557_Y connect \$11 $and$libresoc.v:161891$8558_Y connect \$13 $not$libresoc.v:161892$8559_Y connect \$15 $and$libresoc.v:161893$8560_Y connect \$17 $not$libresoc.v:161894$8561_Y connect \$1 $and$libresoc.v:161895$8562_Y connect \$19 $and$libresoc.v:161896$8563_Y connect \$21 $pos$libresoc.v:161897$8565_Y connect \$23 $pos$libresoc.v:161898$8567_Y connect \$25 $and$libresoc.v:161899$8568_Y connect \$27 $and$libresoc.v:161900$8569_Y connect \$29 $and$libresoc.v:161901$8570_Y connect \$31 $and$libresoc.v:161902$8571_Y connect \$33 $and$libresoc.v:161903$8572_Y connect \$35 $not$libresoc.v:161904$8573_Y connect \$38 $or$libresoc.v:161905$8574_Y connect \$3 $or$libresoc.v:161906$8575_Y connect \$37 $not$libresoc.v:161907$8576_Y connect \$42 $and$libresoc.v:161908$8577_Y connect \$44 $mul$libresoc.v:161909$8578_Y connect \$46 $sshr$libresoc.v:161910$8579_Y connect \$48 $and$libresoc.v:161911$8580_Y connect \$50 $and$libresoc.v:161912$8581_Y connect \$52 $not$libresoc.v:161913$8582_Y connect \$54 $and$libresoc.v:161914$8583_Y connect \$57 $mul$libresoc.v:161915$8584_Y connect \$5 $not$libresoc.v:161916$8585_Y connect \$59 $sshl$libresoc.v:161917$8586_Y connect \$61 $and$libresoc.v:161918$8587_Y connect \$63 $or$libresoc.v:161919$8588_Y connect \$65 $and$libresoc.v:161920$8589_Y connect \$67 $or$libresoc.v:161921$8590_Y connect \$69 $and$libresoc.v:161922$8591_Y connect \$71 $not$libresoc.v:161923$8592_Y connect \$73 $not$libresoc.v:161924$8593_Y connect \$75 $not$libresoc.v:161925$8594_Y connect \$77 $and$libresoc.v:161926$8595_Y connect \$7 $and$libresoc.v:161927$8596_Y connect \$79 $not$libresoc.v:161928$8597_Y connect \$81 $not$libresoc.v:161929$8598_Y connect \$83 $and$libresoc.v:161930$8599_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise connect \lsui_active_rise \$83 connect \lsui_active \$79 connect \x_valid_i \valid_l_q_valid connect \m_valid_i \valid_l_q_valid connect \x_st_i \ldst_port0_is_st_i connect \x_ld_i \ldst_port0_is_ld_i connect \ldst_port0_busy_o \busy_l_q_busy connect \reset_delay$next \reset_l_q_reset connect \lddata \$46 [63:0] connect \st_active_s_st_active \sts_rise connect \sts_rise \$19 connect \sts_dly$next \sts connect \ld_active_s_ld_active \lds_rise connect \lds_rise \$15 connect \lds_dly$next \lds connect \busy_edge \$11 connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end attribute \src "libresoc.v:162462.1-163242.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe attribute \src "libresoc.v:163205.3-163223.6" wire width 4 $0\cr_a$6$next[3:0]$8709 attribute \src "libresoc.v:163069.3-163070.31" wire width 4 $0\cr_a$6[3:0]$8665 attribute \src "libresoc.v:162476.13-162476.28" wire width 4 $0\cr_a$6[3:0]$8715 attribute \src "libresoc.v:163205.3-163223.6" wire $0\cr_a_ok$next[0:0]$8708 attribute \src "libresoc.v:163071.3-163072.31" wire $0\cr_a_ok[0:0] attribute \src "libresoc.v:163152.3-163166.6" wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8689 attribute \src "libresoc.v:163083.3-163084.51" wire width 14 $0\cr_op__fn_unit$3[13:0]$8675 attribute \src "libresoc.v:162541.14-162541.43" wire width 14 $0\cr_op__fn_unit$3[13:0]$8718 attribute \src "libresoc.v:163152.3-163166.6" wire width 32 $0\cr_op__insn$4$next[31:0]$8690 attribute \src "libresoc.v:163085.3-163086.45" wire width 32 $0\cr_op__insn$4[31:0]$8677 attribute \src "libresoc.v:162550.14-162550.37" wire width 32 $0\cr_op__insn$4[31:0]$8720 attribute \src "libresoc.v:163152.3-163166.6" wire width 7 $0\cr_op__insn_type$2$next[6:0]$8691 attribute \src "libresoc.v:163081.3-163082.55" wire width 7 $0\cr_op__insn_type$2[6:0]$8673 attribute \src "libresoc.v:162784.13-162784.41" wire width 7 $0\cr_op__insn_type$2[6:0]$8722 attribute \src "libresoc.v:163186.3-163204.6" wire width 32 $0\full_cr$5$next[31:0]$8702 attribute \src "libresoc.v:163073.3-163074.37" wire width 32 $0\full_cr$5[31:0]$8668 attribute \src "libresoc.v:162793.14-162793.33" wire width 32 $0\full_cr$5[31:0]$8724 attribute \src "libresoc.v:163186.3-163204.6" wire $0\full_cr_ok$next[0:0]$8703 attribute \src "libresoc.v:163075.3-163076.37" wire $0\full_cr_ok[0:0] attribute \src "libresoc.v:162463.7-162463.20" wire $0\initial[0:0] attribute \src "libresoc.v:163139.3-163151.6" wire width 2 $0\muxid$1$next[1:0]$8686 attribute \src "libresoc.v:163087.3-163088.33" wire width 2 $0\muxid$1[1:0]$8679 attribute \src "libresoc.v:163027.13-163027.29" wire width 2 $0\muxid$1[1:0]$8727 attribute \src "libresoc.v:163167.3-163185.6" wire width 64 $0\o$next[63:0]$8696 attribute \src "libresoc.v:163077.3-163078.19" wire width 64 $0\o[63:0] attribute \src "libresoc.v:163167.3-163185.6" wire $0\o_ok$next[0:0]$8697 attribute \src "libresoc.v:163079.3-163080.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:163121.3-163138.6" wire $0\r_busy$next[0:0]$8682 attribute \src "libresoc.v:163089.3-163090.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:163205.3-163223.6" wire width 4 $1\cr_a$6$next[3:0]$8711 attribute \src "libresoc.v:163205.3-163223.6" wire $1\cr_a_ok$next[0:0]$8710 attribute \src "libresoc.v:162481.7-162481.21" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:163152.3-163166.6" wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8692 attribute \src "libresoc.v:163152.3-163166.6" wire width 32 $1\cr_op__insn$4$next[31:0]$8693 attribute \src "libresoc.v:163152.3-163166.6" wire width 7 $1\cr_op__insn_type$2$next[6:0]$8694 attribute \src "libresoc.v:163186.3-163204.6" wire width 32 $1\full_cr$5$next[31:0]$8704 attribute \src "libresoc.v:163186.3-163204.6" wire $1\full_cr_ok$next[0:0]$8705 attribute \src "libresoc.v:162798.7-162798.24" wire $1\full_cr_ok[0:0] attribute \src "libresoc.v:163139.3-163151.6" wire width 2 $1\muxid$1$next[1:0]$8687 attribute \src "libresoc.v:163167.3-163185.6" wire width 64 $1\o$next[63:0]$8698 attribute \src "libresoc.v:163040.14-163040.38" wire width 64 $1\o[63:0] attribute \src "libresoc.v:163167.3-163185.6" wire $1\o_ok$next[0:0]$8699 attribute \src "libresoc.v:163047.7-163047.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:163121.3-163138.6" wire $1\r_busy$next[0:0]$8683 attribute \src "libresoc.v:163061.7-163061.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:163205.3-163223.6" wire $2\cr_a_ok$next[0:0]$8712 attribute \src "libresoc.v:163186.3-163204.6" wire $2\full_cr_ok$next[0:0]$8706 attribute \src "libresoc.v:163167.3-163185.6" wire $2\o_ok$next[0:0]$8700 attribute \src "libresoc.v:163121.3-163138.6" wire $2\r_busy$next[0:0]$8684 attribute \src "libresoc.v:163068.18-163068.118" wire $and$libresoc.v:163068$8663_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 26 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 24 \cr_a$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 12 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 13 \cr_c attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \cr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \cr_op__fn_unit$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 18 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \cr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 7 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \cr_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 19 \cr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \cr_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$17 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 17 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 10 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \full_cr$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 output 22 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \full_cr$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \full_cr_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \full_cr_ok$next attribute \src "libresoc.v:162463.7-162463.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \main_cr_a$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_c attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_cr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_cr_op__fn_unit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_cr_op__insn$10 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_cr_op__insn_type$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \main_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \main_full_cr$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 16 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 15 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 14 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 8 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:163068$8663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o connect \Y $and$libresoc.v:163068$8663_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:163091.12-163112.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 connect \cr_a_ok \main_cr_a_ok connect \cr_b \main_cr_b connect \cr_c \main_cr_c connect \cr_op__fn_unit \main_cr_op__fn_unit connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 connect \cr_op__insn \main_cr_op__insn connect \cr_op__insn$4 \main_cr_op__insn$10 connect \cr_op__insn_type \main_cr_op__insn_type connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 connect \full_cr \main_full_cr connect \full_cr$5 \main_full_cr$11 connect \full_cr_ok \main_full_cr_ok connect \muxid \main_muxid connect \muxid$1 \main_muxid$7 connect \o \main_o connect \o_ok \main_o_ok connect \ra \main_ra connect \rb \main_rb end attribute \module_not_derived 1 attribute \src "libresoc.v:163113.9-163116.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:163117.9-163120.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:162463.7-162463.20" process $proc$libresoc.v:162463$8713 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:162476.13-162476.28" process $proc$libresoc.v:162476$8714 assign { } { } assign $0\cr_a$6[3:0]$8715 4'0000 sync always sync init update \cr_a$6 $0\cr_a$6[3:0]$8715 end attribute \src "libresoc.v:162481.7-162481.21" process $proc$libresoc.v:162481$8716 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end attribute \src "libresoc.v:162541.14-162541.43" process $proc$libresoc.v:162541$8717 assign { } { } assign $0\cr_op__fn_unit$3[13:0]$8718 14'00000000000000 sync always sync init update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8718 end attribute \src "libresoc.v:162550.14-162550.37" process $proc$libresoc.v:162550$8719 assign { } { } assign $0\cr_op__insn$4[31:0]$8720 0 sync always sync init update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8720 end attribute \src "libresoc.v:162784.13-162784.41" process $proc$libresoc.v:162784$8721 assign { } { } assign $0\cr_op__insn_type$2[6:0]$8722 7'0000000 sync always sync init update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8722 end attribute \src "libresoc.v:162793.14-162793.33" process $proc$libresoc.v:162793$8723 assign { } { } assign $0\full_cr$5[31:0]$8724 0 sync always sync init update \full_cr$5 $0\full_cr$5[31:0]$8724 end attribute \src "libresoc.v:162798.7-162798.24" process $proc$libresoc.v:162798$8725 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end attribute \src "libresoc.v:163027.13-163027.29" process $proc$libresoc.v:163027$8726 assign { } { } assign $0\muxid$1[1:0]$8727 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8727 end attribute \src "libresoc.v:163040.14-163040.38" process $proc$libresoc.v:163040$8728 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end attribute \src "libresoc.v:163047.7-163047.18" process $proc$libresoc.v:163047$8729 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:163061.7-163061.20" process $proc$libresoc.v:163061$8730 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:163069.3-163070.31" process $proc$libresoc.v:163069$8664 assign { } { } assign $0\cr_a$6[3:0]$8665 \cr_a$6$next sync posedge \coresync_clk update \cr_a$6 $0\cr_a$6[3:0]$8665 end attribute \src "libresoc.v:163071.3-163072.31" process $proc$libresoc.v:163071$8666 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end attribute \src "libresoc.v:163073.3-163074.37" process $proc$libresoc.v:163073$8667 assign { } { } assign $0\full_cr$5[31:0]$8668 \full_cr$5$next sync posedge \coresync_clk update \full_cr$5 $0\full_cr$5[31:0]$8668 end attribute \src "libresoc.v:163075.3-163076.37" process $proc$libresoc.v:163075$8669 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end attribute \src "libresoc.v:163077.3-163078.19" process $proc$libresoc.v:163077$8670 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end attribute \src "libresoc.v:163079.3-163080.25" process $proc$libresoc.v:163079$8671 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:163081.3-163082.55" process $proc$libresoc.v:163081$8672 assign { } { } assign $0\cr_op__insn_type$2[6:0]$8673 \cr_op__insn_type$2$next sync posedge \coresync_clk update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8673 end attribute \src "libresoc.v:163083.3-163084.51" process $proc$libresoc.v:163083$8674 assign { } { } assign $0\cr_op__fn_unit$3[13:0]$8675 \cr_op__fn_unit$3$next sync posedge \coresync_clk update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8675 end attribute \src "libresoc.v:163085.3-163086.45" process $proc$libresoc.v:163085$8676 assign { } { } assign $0\cr_op__insn$4[31:0]$8677 \cr_op__insn$4$next sync posedge \coresync_clk update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8677 end attribute \src "libresoc.v:163087.3-163088.33" process $proc$libresoc.v:163087$8678 assign { } { } assign $0\muxid$1[1:0]$8679 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8679 end attribute \src "libresoc.v:163089.3-163090.29" process $proc$libresoc.v:163089$8680 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:163121.3-163138.6" process $proc$libresoc.v:163121$8681 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8682 $2\r_busy$next[0:0]$8684 attribute \src "libresoc.v:163122.5-163122.29" switch \initial attribute \src "libresoc.v:163122.9-163122.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$8683 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$8683 1'0 case assign $1\r_busy$next[0:0]$8683 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$8684 1'0 case assign $2\r_busy$next[0:0]$8684 $1\r_busy$next[0:0]$8683 end sync always update \r_busy$next $0\r_busy$next[0:0]$8682 end attribute \src "libresoc.v:163139.3-163151.6" process $proc$libresoc.v:163139$8685 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8686 $1\muxid$1$next[1:0]$8687 attribute \src "libresoc.v:163140.5-163140.29" switch \initial attribute \src "libresoc.v:163140.9-163140.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$8687 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$8687 \muxid$16 case assign $1\muxid$1$next[1:0]$8687 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$8686 end attribute \src "libresoc.v:163152.3-163166.6" process $proc$libresoc.v:163152$8688 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_op__fn_unit$3$next[13:0]$8689 $1\cr_op__fn_unit$3$next[13:0]$8692 assign $0\cr_op__insn$4$next[31:0]$8690 $1\cr_op__insn$4$next[31:0]$8693 assign $0\cr_op__insn_type$2$next[6:0]$8691 $1\cr_op__insn_type$2$next[6:0]$8694 attribute \src "libresoc.v:163153.5-163153.29" switch \initial attribute \src "libresoc.v:163153.9-163153.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { $1\cr_op__insn$4$next[31:0]$8693 $1\cr_op__fn_unit$3$next[13:0]$8692 $1\cr_op__insn_type$2$next[6:0]$8694 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { $1\cr_op__insn$4$next[31:0]$8693 $1\cr_op__fn_unit$3$next[13:0]$8692 $1\cr_op__insn_type$2$next[6:0]$8694 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case assign $1\cr_op__fn_unit$3$next[13:0]$8692 \cr_op__fn_unit$3 assign $1\cr_op__insn$4$next[31:0]$8693 \cr_op__insn$4 assign $1\cr_op__insn_type$2$next[6:0]$8694 \cr_op__insn_type$2 end sync always update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8689 update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8690 update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8691 end attribute \src "libresoc.v:163167.3-163185.6" process $proc$libresoc.v:163167$8695 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$next[63:0]$8696 $1\o$next[63:0]$8698 assign { } { } assign $0\o_ok$next[0:0]$8697 $2\o_ok$next[0:0]$8700 attribute \src "libresoc.v:163168.5-163168.29" switch \initial attribute \src "libresoc.v:163168.9-163168.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$8699 $1\o$next[63:0]$8698 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$8699 $1\o$next[63:0]$8698 } { \o_ok$21 \o$20 } case assign $1\o$next[63:0]$8698 \o assign $1\o_ok$next[0:0]$8699 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$8700 1'0 case assign $2\o_ok$next[0:0]$8700 $1\o_ok$next[0:0]$8699 end sync always update \o$next $0\o$next[63:0]$8696 update \o_ok$next $0\o_ok$next[0:0]$8697 end attribute \src "libresoc.v:163186.3-163204.6" process $proc$libresoc.v:163186$8701 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\full_cr$5$next[31:0]$8702 $1\full_cr$5$next[31:0]$8704 assign { } { } assign $0\full_cr_ok$next[0:0]$8703 $2\full_cr_ok$next[0:0]$8706 attribute \src "libresoc.v:163187.5-163187.29" switch \initial attribute \src "libresoc.v:163187.9-163187.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\full_cr_ok$next[0:0]$8705 $1\full_cr$5$next[31:0]$8704 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\full_cr_ok$next[0:0]$8705 $1\full_cr$5$next[31:0]$8704 } { \full_cr_ok$23 \full_cr$22 } case assign $1\full_cr$5$next[31:0]$8704 \full_cr$5 assign $1\full_cr_ok$next[0:0]$8705 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\full_cr_ok$next[0:0]$8706 1'0 case assign $2\full_cr_ok$next[0:0]$8706 $1\full_cr_ok$next[0:0]$8705 end sync always update \full_cr$5$next $0\full_cr$5$next[31:0]$8702 update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8703 end attribute \src "libresoc.v:163205.3-163223.6" process $proc$libresoc.v:163205$8707 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$6$next[3:0]$8709 $1\cr_a$6$next[3:0]$8711 assign $0\cr_a_ok$next[0:0]$8708 $2\cr_a_ok$next[0:0]$8712 attribute \src "libresoc.v:163206.5-163206.29" switch \initial attribute \src "libresoc.v:163206.9-163206.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$6$next[3:0]$8711 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$6$next[3:0]$8711 } { \cr_a_ok$25 \cr_a$24 } case assign $1\cr_a_ok$next[0:0]$8710 \cr_a_ok assign $1\cr_a$6$next[3:0]$8711 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$next[0:0]$8712 1'0 case assign $2\cr_a_ok$next[0:0]$8712 $1\cr_a_ok$next[0:0]$8710 end sync always update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8708 update \cr_a$6$next $0\cr_a$6$next[3:0]$8709 end connect \$14 $and$libresoc.v:163068$8663_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } connect \muxid$16 \main_muxid$7 connect \p_valid_i_p_ready_o \$14 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$13 \p_valid_i connect \main_cr_c \cr_c connect \main_cr_b \cr_b connect \main_cr_a \cr_a connect \main_full_cr \full_cr connect \main_rb \rb connect \main_ra \ra connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end attribute \src "libresoc.v:163246.1-164106.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $0\br_op__cia$2$next[63:0]$8767 attribute \src "libresoc.v:163918.3-163919.43" wire width 64 $0\br_op__cia$2[63:0]$8741 attribute \src "libresoc.v:163254.14-163254.51" wire width 64 $0\br_op__cia$2[63:0]$8805 attribute \src "libresoc.v:164006.3-164033.6" wire width 14 $0\br_op__fn_unit$4$next[13:0]$8768 attribute \src "libresoc.v:163922.3-163923.51" wire width 14 $0\br_op__fn_unit$4[13:0]$8745 attribute \src "libresoc.v:163310.14-163310.43" wire width 14 $0\br_op__fn_unit$4[13:0]$8807 attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8769 attribute \src "libresoc.v:163926.3-163927.65" wire width 64 $0\br_op__imm_data__data$6[63:0]$8749 attribute \src "libresoc.v:163319.14-163319.62" wire width 64 $0\br_op__imm_data__data$6[63:0]$8809 attribute \src "libresoc.v:164006.3-164033.6" wire $0\br_op__imm_data__ok$7$next[0:0]$8770 attribute \src "libresoc.v:163928.3-163929.61" wire $0\br_op__imm_data__ok$7[0:0]$8751 attribute \src "libresoc.v:163328.7-163328.37" wire $0\br_op__imm_data__ok$7[0:0]$8811 attribute \src "libresoc.v:164006.3-164033.6" wire width 32 $0\br_op__insn$5$next[31:0]$8771 attribute \src "libresoc.v:163924.3-163925.45" wire width 32 $0\br_op__insn$5[31:0]$8747 attribute \src "libresoc.v:163337.14-163337.37" wire width 32 $0\br_op__insn$5[31:0]$8813 attribute \src "libresoc.v:164006.3-164033.6" wire width 7 $0\br_op__insn_type$3$next[6:0]$8772 attribute \src "libresoc.v:163920.3-163921.55" wire width 7 $0\br_op__insn_type$3[6:0]$8743 attribute \src "libresoc.v:163571.13-163571.41" wire width 7 $0\br_op__insn_type$3[6:0]$8815 attribute \src "libresoc.v:164006.3-164033.6" wire $0\br_op__is_32bit$9$next[0:0]$8773 attribute \src "libresoc.v:163932.3-163933.53" wire $0\br_op__is_32bit$9[0:0]$8755 attribute \src "libresoc.v:163580.7-163580.33" wire $0\br_op__is_32bit$9[0:0]$8817 attribute \src "libresoc.v:164006.3-164033.6" wire $0\br_op__lk$8$next[0:0]$8774 attribute \src "libresoc.v:163930.3-163931.41" wire $0\br_op__lk$8[0:0]$8753 attribute \src "libresoc.v:163589.7-163589.27" wire $0\br_op__lk$8[0:0]$8819 attribute \src "libresoc.v:164034.3-164052.6" wire width 64 $0\fast1$10$next[63:0]$8786 attribute \src "libresoc.v:163914.3-163915.35" wire width 64 $0\fast1$10[63:0]$8738 attribute \src "libresoc.v:163602.14-163602.47" wire width 64 $0\fast1$10[63:0]$8821 attribute \src "libresoc.v:164034.3-164052.6" wire $0\fast1_ok$next[0:0]$8787 attribute \src "libresoc.v:163916.3-163917.33" wire $0\fast1_ok[0:0] attribute \src "libresoc.v:164053.3-164071.6" wire width 64 $0\fast2$11$next[63:0]$8792 attribute \src "libresoc.v:163910.3-163911.35" wire width 64 $0\fast2$11[63:0]$8735 attribute \src "libresoc.v:163618.14-163618.47" wire width 64 $0\fast2$11[63:0]$8824 attribute \src "libresoc.v:164053.3-164071.6" wire $0\fast2_ok$next[0:0]$8793 attribute \src "libresoc.v:163912.3-163913.33" wire $0\fast2_ok[0:0] attribute \src "libresoc.v:163247.7-163247.20" wire $0\initial[0:0] attribute \src "libresoc.v:163993.3-164005.6" wire width 2 $0\muxid$1$next[1:0]$8764 attribute \src "libresoc.v:163934.3-163935.33" wire width 2 $0\muxid$1[1:0]$8757 attribute \src "libresoc.v:163868.13-163868.29" wire width 2 $0\muxid$1[1:0]$8827 attribute \src "libresoc.v:164072.3-164090.6" wire width 64 $0\nia$next[63:0]$8798 attribute \src "libresoc.v:163906.3-163907.23" wire width 64 $0\nia[63:0] attribute \src "libresoc.v:164072.3-164090.6" wire $0\nia_ok$next[0:0]$8799 attribute \src "libresoc.v:163908.3-163909.29" wire $0\nia_ok[0:0] attribute \src "libresoc.v:163975.3-163992.6" wire $0\r_busy$next[0:0]$8760 attribute \src "libresoc.v:163936.3-163937.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $1\br_op__cia$2$next[63:0]$8775 attribute \src "libresoc.v:164006.3-164033.6" wire width 14 $1\br_op__fn_unit$4$next[13:0]$8776 attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8777 attribute \src "libresoc.v:164006.3-164033.6" wire $1\br_op__imm_data__ok$7$next[0:0]$8778 attribute \src "libresoc.v:164006.3-164033.6" wire width 32 $1\br_op__insn$5$next[31:0]$8779 attribute \src "libresoc.v:164006.3-164033.6" wire width 7 $1\br_op__insn_type$3$next[6:0]$8780 attribute \src "libresoc.v:164006.3-164033.6" wire $1\br_op__is_32bit$9$next[0:0]$8781 attribute \src "libresoc.v:164006.3-164033.6" wire $1\br_op__lk$8$next[0:0]$8782 attribute \src "libresoc.v:164034.3-164052.6" wire width 64 $1\fast1$10$next[63:0]$8788 attribute \src "libresoc.v:164034.3-164052.6" wire $1\fast1_ok$next[0:0]$8789 attribute \src "libresoc.v:163609.7-163609.22" wire $1\fast1_ok[0:0] attribute \src "libresoc.v:164053.3-164071.6" wire width 64 $1\fast2$11$next[63:0]$8794 attribute \src "libresoc.v:164053.3-164071.6" wire $1\fast2_ok$next[0:0]$8795 attribute \src "libresoc.v:163625.7-163625.22" wire $1\fast2_ok[0:0] attribute \src "libresoc.v:163993.3-164005.6" wire width 2 $1\muxid$1$next[1:0]$8765 attribute \src "libresoc.v:164072.3-164090.6" wire width 64 $1\nia$next[63:0]$8800 attribute \src "libresoc.v:163881.14-163881.40" wire width 64 $1\nia[63:0] attribute \src "libresoc.v:164072.3-164090.6" wire $1\nia_ok$next[0:0]$8801 attribute \src "libresoc.v:163888.7-163888.20" wire $1\nia_ok[0:0] attribute \src "libresoc.v:163975.3-163992.6" wire $1\r_busy$next[0:0]$8761 attribute \src "libresoc.v:163902.7-163902.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:164006.3-164033.6" wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8783 attribute \src "libresoc.v:164006.3-164033.6" wire $2\br_op__imm_data__ok$7$next[0:0]$8784 attribute \src "libresoc.v:164034.3-164052.6" wire $2\fast1_ok$next[0:0]$8790 attribute \src "libresoc.v:164053.3-164071.6" wire $2\fast2_ok$next[0:0]$8796 attribute \src "libresoc.v:164072.3-164090.6" wire $2\nia_ok$next[0:0]$8802 attribute \src "libresoc.v:163975.3-163992.6" wire $2\r_busy$next[0:0]$8762 attribute \src "libresoc.v:163905.18-163905.118" wire $and$libresoc.v:163905$8731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 19 \br_op__cia$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__cia$2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__cia$27 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 7 \br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \br_op__fn_unit$29 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 21 \br_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \br_op__fn_unit$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 9 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__imm_data__data$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 23 \br_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \br_op__imm_data__data$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__imm_data__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 24 \br_op__imm_data__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__imm_data__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 8 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \br_op__insn$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 22 \br_op__insn$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \br_op__insn$5$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 6 \br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \br_op__insn_type$28 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 20 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \br_op__insn_type$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \br_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__is_32bit$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 33 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 27 \fast1$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 29 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$next attribute \src "libresoc.v:163247.7-163247.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia$13 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_br_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__imm_data__data$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_br_op__imm_data__ok$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_br_op__insn$16 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_br_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_br_op__is_32bit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_br_op__lk$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast1$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast2$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 18 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 17 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 16 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 31 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:163905$8731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o connect \Y $and$libresoc.v:163905$8731_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:163938.13-163966.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 connect \br_op__fn_unit \main_br_op__fn_unit connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 connect \br_op__imm_data__data \main_br_op__imm_data__data connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 connect \br_op__imm_data__ok \main_br_op__imm_data__ok connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 connect \br_op__insn \main_br_op__insn connect \br_op__insn$5 \main_br_op__insn$16 connect \br_op__insn_type \main_br_op__insn_type connect \br_op__insn_type$3 \main_br_op__insn_type$14 connect \br_op__is_32bit \main_br_op__is_32bit connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 connect \br_op__lk \main_br_op__lk connect \br_op__lk$8 \main_br_op__lk$19 connect \cr_a \main_cr_a connect \fast1 \main_fast1 connect \fast1$10 \main_fast1$21 connect \fast1_ok \main_fast1_ok connect \fast2 \main_fast2 connect \fast2$11 \main_fast2$22 connect \fast2_ok \main_fast2_ok connect \muxid \main_muxid connect \muxid$1 \main_muxid$12 connect \nia \main_nia connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:163967.10-163970.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:163971.10-163974.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:163247.7-163247.20" process $proc$libresoc.v:163247$8803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:163254.14-163254.51" process $proc$libresoc.v:163254$8804 assign { } { } assign $0\br_op__cia$2[63:0]$8805 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \br_op__cia$2 $0\br_op__cia$2[63:0]$8805 end attribute \src "libresoc.v:163310.14-163310.43" process $proc$libresoc.v:163310$8806 assign { } { } assign $0\br_op__fn_unit$4[13:0]$8807 14'00000000000000 sync always sync init update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8807 end attribute \src "libresoc.v:163319.14-163319.62" process $proc$libresoc.v:163319$8808 assign { } { } assign $0\br_op__imm_data__data$6[63:0]$8809 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8809 end attribute \src "libresoc.v:163328.7-163328.37" process $proc$libresoc.v:163328$8810 assign { } { } assign $0\br_op__imm_data__ok$7[0:0]$8811 1'0 sync always sync init update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8811 end attribute \src "libresoc.v:163337.14-163337.37" process $proc$libresoc.v:163337$8812 assign { } { } assign $0\br_op__insn$5[31:0]$8813 0 sync always sync init update \br_op__insn$5 $0\br_op__insn$5[31:0]$8813 end attribute \src "libresoc.v:163571.13-163571.41" process $proc$libresoc.v:163571$8814 assign { } { } assign $0\br_op__insn_type$3[6:0]$8815 7'0000000 sync always sync init update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8815 end attribute \src "libresoc.v:163580.7-163580.33" process $proc$libresoc.v:163580$8816 assign { } { } assign $0\br_op__is_32bit$9[0:0]$8817 1'0 sync always sync init update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8817 end attribute \src "libresoc.v:163589.7-163589.27" process $proc$libresoc.v:163589$8818 assign { } { } assign $0\br_op__lk$8[0:0]$8819 1'0 sync always sync init update \br_op__lk$8 $0\br_op__lk$8[0:0]$8819 end attribute \src "libresoc.v:163602.14-163602.47" process $proc$libresoc.v:163602$8820 assign { } { } assign $0\fast1$10[63:0]$8821 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$10 $0\fast1$10[63:0]$8821 end attribute \src "libresoc.v:163609.7-163609.22" process $proc$libresoc.v:163609$8822 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end attribute \src "libresoc.v:163618.14-163618.47" process $proc$libresoc.v:163618$8823 assign { } { } assign $0\fast2$11[63:0]$8824 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2$11 $0\fast2$11[63:0]$8824 end attribute \src "libresoc.v:163625.7-163625.22" process $proc$libresoc.v:163625$8825 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end attribute \src "libresoc.v:163868.13-163868.29" process $proc$libresoc.v:163868$8826 assign { } { } assign $0\muxid$1[1:0]$8827 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8827 end attribute \src "libresoc.v:163881.14-163881.40" process $proc$libresoc.v:163881$8828 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end attribute \src "libresoc.v:163888.7-163888.20" process $proc$libresoc.v:163888$8829 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end attribute \src "libresoc.v:163902.7-163902.20" process $proc$libresoc.v:163902$8830 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:163906.3-163907.23" process $proc$libresoc.v:163906$8732 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end attribute \src "libresoc.v:163908.3-163909.29" process $proc$libresoc.v:163908$8733 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end attribute \src "libresoc.v:163910.3-163911.35" process $proc$libresoc.v:163910$8734 assign { } { } assign $0\fast2$11[63:0]$8735 \fast2$11$next sync posedge \coresync_clk update \fast2$11 $0\fast2$11[63:0]$8735 end attribute \src "libresoc.v:163912.3-163913.33" process $proc$libresoc.v:163912$8736 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end attribute \src "libresoc.v:163914.3-163915.35" process $proc$libresoc.v:163914$8737 assign { } { } assign $0\fast1$10[63:0]$8738 \fast1$10$next sync posedge \coresync_clk update \fast1$10 $0\fast1$10[63:0]$8738 end attribute \src "libresoc.v:163916.3-163917.33" process $proc$libresoc.v:163916$8739 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end attribute \src "libresoc.v:163918.3-163919.43" process $proc$libresoc.v:163918$8740 assign { } { } assign $0\br_op__cia$2[63:0]$8741 \br_op__cia$2$next sync posedge \coresync_clk update \br_op__cia$2 $0\br_op__cia$2[63:0]$8741 end attribute \src "libresoc.v:163920.3-163921.55" process $proc$libresoc.v:163920$8742 assign { } { } assign $0\br_op__insn_type$3[6:0]$8743 \br_op__insn_type$3$next sync posedge \coresync_clk update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8743 end attribute \src "libresoc.v:163922.3-163923.51" process $proc$libresoc.v:163922$8744 assign { } { } assign $0\br_op__fn_unit$4[13:0]$8745 \br_op__fn_unit$4$next sync posedge \coresync_clk update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8745 end attribute \src "libresoc.v:163924.3-163925.45" process $proc$libresoc.v:163924$8746 assign { } { } assign $0\br_op__insn$5[31:0]$8747 \br_op__insn$5$next sync posedge \coresync_clk update \br_op__insn$5 $0\br_op__insn$5[31:0]$8747 end attribute \src "libresoc.v:163926.3-163927.65" process $proc$libresoc.v:163926$8748 assign { } { } assign $0\br_op__imm_data__data$6[63:0]$8749 \br_op__imm_data__data$6$next sync posedge \coresync_clk update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8749 end attribute \src "libresoc.v:163928.3-163929.61" process $proc$libresoc.v:163928$8750 assign { } { } assign $0\br_op__imm_data__ok$7[0:0]$8751 \br_op__imm_data__ok$7$next sync posedge \coresync_clk update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8751 end attribute \src "libresoc.v:163930.3-163931.41" process $proc$libresoc.v:163930$8752 assign { } { } assign $0\br_op__lk$8[0:0]$8753 \br_op__lk$8$next sync posedge \coresync_clk update \br_op__lk$8 $0\br_op__lk$8[0:0]$8753 end attribute \src "libresoc.v:163932.3-163933.53" process $proc$libresoc.v:163932$8754 assign { } { } assign $0\br_op__is_32bit$9[0:0]$8755 \br_op__is_32bit$9$next sync posedge \coresync_clk update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8755 end attribute \src "libresoc.v:163934.3-163935.33" process $proc$libresoc.v:163934$8756 assign { } { } assign $0\muxid$1[1:0]$8757 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8757 end attribute \src "libresoc.v:163936.3-163937.29" process $proc$libresoc.v:163936$8758 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:163975.3-163992.6" process $proc$libresoc.v:163975$8759 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8760 $2\r_busy$next[0:0]$8762 attribute \src "libresoc.v:163976.5-163976.29" switch \initial attribute \src "libresoc.v:163976.9-163976.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$8761 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$8761 1'0 case assign $1\r_busy$next[0:0]$8761 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$8762 1'0 case assign $2\r_busy$next[0:0]$8762 $1\r_busy$next[0:0]$8761 end sync always update \r_busy$next $0\r_busy$next[0:0]$8760 end attribute \src "libresoc.v:163993.3-164005.6" process $proc$libresoc.v:163993$8763 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8764 $1\muxid$1$next[1:0]$8765 attribute \src "libresoc.v:163994.5-163994.29" switch \initial attribute \src "libresoc.v:163994.9-163994.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$8765 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$8765 \muxid$26 case assign $1\muxid$1$next[1:0]$8765 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$8764 end attribute \src "libresoc.v:164006.3-164033.6" process $proc$libresoc.v:164006$8766 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\br_op__cia$2$next[63:0]$8767 $1\br_op__cia$2$next[63:0]$8775 assign $0\br_op__fn_unit$4$next[13:0]$8768 $1\br_op__fn_unit$4$next[13:0]$8776 assign { } { } assign { } { } assign $0\br_op__insn$5$next[31:0]$8771 $1\br_op__insn$5$next[31:0]$8779 assign $0\br_op__insn_type$3$next[6:0]$8772 $1\br_op__insn_type$3$next[6:0]$8780 assign $0\br_op__is_32bit$9$next[0:0]$8773 $1\br_op__is_32bit$9$next[0:0]$8781 assign $0\br_op__lk$8$next[0:0]$8774 $1\br_op__lk$8$next[0:0]$8782 assign $0\br_op__imm_data__data$6$next[63:0]$8769 $2\br_op__imm_data__data$6$next[63:0]$8783 assign $0\br_op__imm_data__ok$7$next[0:0]$8770 $2\br_op__imm_data__ok$7$next[0:0]$8784 attribute \src "libresoc.v:164007.5-164007.29" switch \initial attribute \src "libresoc.v:164007.9-164007.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\br_op__is_32bit$9$next[0:0]$8781 $1\br_op__lk$8$next[0:0]$8782 $1\br_op__imm_data__ok$7$next[0:0]$8778 $1\br_op__imm_data__data$6$next[63:0]$8777 $1\br_op__insn$5$next[31:0]$8779 $1\br_op__fn_unit$4$next[13:0]$8776 $1\br_op__insn_type$3$next[6:0]$8780 $1\br_op__cia$2$next[63:0]$8775 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\br_op__is_32bit$9$next[0:0]$8781 $1\br_op__lk$8$next[0:0]$8782 $1\br_op__imm_data__ok$7$next[0:0]$8778 $1\br_op__imm_data__data$6$next[63:0]$8777 $1\br_op__insn$5$next[31:0]$8779 $1\br_op__fn_unit$4$next[13:0]$8776 $1\br_op__insn_type$3$next[6:0]$8780 $1\br_op__cia$2$next[63:0]$8775 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case assign $1\br_op__cia$2$next[63:0]$8775 \br_op__cia$2 assign $1\br_op__fn_unit$4$next[13:0]$8776 \br_op__fn_unit$4 assign $1\br_op__imm_data__data$6$next[63:0]$8777 \br_op__imm_data__data$6 assign $1\br_op__imm_data__ok$7$next[0:0]$8778 \br_op__imm_data__ok$7 assign $1\br_op__insn$5$next[31:0]$8779 \br_op__insn$5 assign $1\br_op__insn_type$3$next[6:0]$8780 \br_op__insn_type$3 assign $1\br_op__is_32bit$9$next[0:0]$8781 \br_op__is_32bit$9 assign $1\br_op__lk$8$next[0:0]$8782 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $2\br_op__imm_data__data$6$next[63:0]$8783 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\br_op__imm_data__ok$7$next[0:0]$8784 1'0 case assign $2\br_op__imm_data__data$6$next[63:0]$8783 $1\br_op__imm_data__data$6$next[63:0]$8777 assign $2\br_op__imm_data__ok$7$next[0:0]$8784 $1\br_op__imm_data__ok$7$next[0:0]$8778 end sync always update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8767 update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8768 update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8769 update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8770 update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8771 update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8772 update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8773 update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8774 end attribute \src "libresoc.v:164034.3-164052.6" process $proc$libresoc.v:164034$8785 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast1$10$next[63:0]$8786 $1\fast1$10$next[63:0]$8788 assign { } { } assign $0\fast1_ok$next[0:0]$8787 $2\fast1_ok$next[0:0]$8790 attribute \src "libresoc.v:164035.5-164035.29" switch \initial attribute \src "libresoc.v:164035.9-164035.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\fast1_ok$next[0:0]$8789 $1\fast1$10$next[63:0]$8788 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\fast1_ok$next[0:0]$8789 $1\fast1$10$next[63:0]$8788 } { \fast1_ok$36 \fast1$35 } case assign $1\fast1$10$next[63:0]$8788 \fast1$10 assign $1\fast1_ok$next[0:0]$8789 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast1_ok$next[0:0]$8790 1'0 case assign $2\fast1_ok$next[0:0]$8790 $1\fast1_ok$next[0:0]$8789 end sync always update \fast1$10$next $0\fast1$10$next[63:0]$8786 update \fast1_ok$next $0\fast1_ok$next[0:0]$8787 end attribute \src "libresoc.v:164053.3-164071.6" process $proc$libresoc.v:164053$8791 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast2$11$next[63:0]$8792 $1\fast2$11$next[63:0]$8794 assign { } { } assign $0\fast2_ok$next[0:0]$8793 $2\fast2_ok$next[0:0]$8796 attribute \src "libresoc.v:164054.5-164054.29" switch \initial attribute \src "libresoc.v:164054.9-164054.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\fast2_ok$next[0:0]$8795 $1\fast2$11$next[63:0]$8794 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\fast2_ok$next[0:0]$8795 $1\fast2$11$next[63:0]$8794 } { \fast2_ok$38 \fast2$37 } case assign $1\fast2$11$next[63:0]$8794 \fast2$11 assign $1\fast2_ok$next[0:0]$8795 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast2_ok$next[0:0]$8796 1'0 case assign $2\fast2_ok$next[0:0]$8796 $1\fast2_ok$next[0:0]$8795 end sync always update \fast2$11$next $0\fast2$11$next[63:0]$8792 update \fast2_ok$next $0\fast2_ok$next[0:0]$8793 end attribute \src "libresoc.v:164072.3-164090.6" process $proc$libresoc.v:164072$8797 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\nia$next[63:0]$8798 $1\nia$next[63:0]$8800 assign { } { } assign $0\nia_ok$next[0:0]$8799 $2\nia_ok$next[0:0]$8802 attribute \src "libresoc.v:164073.5-164073.29" switch \initial attribute \src "libresoc.v:164073.9-164073.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\nia_ok$next[0:0]$8801 $1\nia$next[63:0]$8800 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\nia_ok$next[0:0]$8801 $1\nia$next[63:0]$8800 } { \nia_ok$40 \nia$39 } case assign $1\nia$next[63:0]$8800 \nia assign $1\nia_ok$next[0:0]$8801 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\nia_ok$next[0:0]$8802 1'0 case assign $2\nia_ok$next[0:0]$8802 $1\nia_ok$next[0:0]$8801 end sync always update \nia$next $0\nia$next[63:0]$8798 update \nia_ok$next $0\nia_ok$next[0:0]$8799 end connect \$24 $and$libresoc.v:163905$8731_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } connect \muxid$26 \main_muxid$12 connect \p_valid_i_p_ready_o \$24 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$23 \p_valid_i connect \main_cr_a \cr_a connect \main_fast2 \fast2 connect \main_fast1 \fast1 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end attribute \src "libresoc.v:164110.1-165040.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 attribute \src "libresoc.v:164943.3-164961.6" wire width 64 $0\fast1$7$next[63:0]$8890 attribute \src "libresoc.v:164796.3-164797.33" wire width 64 $0\fast1$7[63:0]$8842 attribute \src "libresoc.v:164124.14-164124.46" wire width 64 $0\fast1$7[63:0]$8914 attribute \src "libresoc.v:164943.3-164961.6" wire $0\fast1_ok$next[0:0]$8889 attribute \src "libresoc.v:164798.3-164799.33" wire $0\fast1_ok[0:0] attribute \src "libresoc.v:164111.7-164111.20" wire $0\initial[0:0] attribute \src "libresoc.v:164876.3-164888.6" wire width 2 $0\muxid$1$next[1:0]$8865 attribute \src "libresoc.v:164816.3-164817.33" wire width 2 $0\muxid$1[1:0]$8858 attribute \src "libresoc.v:164138.13-164138.29" wire width 2 $0\muxid$1[1:0]$8917 attribute \src "libresoc.v:164905.3-164923.6" wire width 64 $0\o$next[63:0]$8877 attribute \src "libresoc.v:164804.3-164805.19" wire width 64 $0\o[63:0] attribute \src "libresoc.v:164905.3-164923.6" wire $0\o_ok$next[0:0]$8878 attribute \src "libresoc.v:164806.3-164807.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:164858.3-164875.6" wire $0\r_busy$next[0:0]$8861 attribute \src "libresoc.v:164818.3-164819.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:164924.3-164942.6" wire width 64 $0\spr1$6$next[63:0]$8883 attribute \src "libresoc.v:164800.3-164801.31" wire width 64 $0\spr1$6[63:0]$8845 attribute \src "libresoc.v:164183.14-164183.45" wire width 64 $0\spr1$6[63:0]$8922 attribute \src "libresoc.v:164924.3-164942.6" wire $0\spr1_ok$next[0:0]$8884 attribute \src "libresoc.v:164802.3-164803.31" wire $0\spr1_ok[0:0] attribute \src "libresoc.v:164889.3-164904.6" wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8868 attribute \src "libresoc.v:164810.3-164811.53" wire width 14 $0\spr_op__fn_unit$3[13:0]$8852 attribute \src "libresoc.v:164480.14-164480.44" wire width 14 $0\spr_op__fn_unit$3[13:0]$8925 attribute \src "libresoc.v:164889.3-164904.6" wire width 32 $0\spr_op__insn$4$next[31:0]$8869 attribute \src "libresoc.v:164812.3-164813.47" wire width 32 $0\spr_op__insn$4[31:0]$8854 attribute \src "libresoc.v:164489.14-164489.38" wire width 32 $0\spr_op__insn$4[31:0]$8927 attribute \src "libresoc.v:164889.3-164904.6" wire width 7 $0\spr_op__insn_type$2$next[6:0]$8870 attribute \src "libresoc.v:164808.3-164809.57" wire width 7 $0\spr_op__insn_type$2[6:0]$8850 attribute \src "libresoc.v:164646.13-164646.42" wire width 7 $0\spr_op__insn_type$2[6:0]$8929 attribute \src "libresoc.v:164889.3-164904.6" wire $0\spr_op__is_32bit$5$next[0:0]$8871 attribute \src "libresoc.v:164814.3-164815.55" wire $0\spr_op__is_32bit$5[0:0]$8856 attribute \src "libresoc.v:164732.7-164732.34" wire $0\spr_op__is_32bit$5[0:0]$8931 attribute \src "libresoc.v:165000.3-165018.6" wire width 2 $0\xer_ca$10$next[1:0]$8907 attribute \src "libresoc.v:164784.3-164785.37" wire width 2 $0\xer_ca$10[1:0]$8833 attribute \src "libresoc.v:164739.13-164739.31" wire width 2 $0\xer_ca$10[1:0]$8933 attribute \src "libresoc.v:165000.3-165018.6" wire $0\xer_ca_ok$next[0:0]$8908 attribute \src "libresoc.v:164786.3-164787.35" wire $0\xer_ca_ok[0:0] attribute \src "libresoc.v:164981.3-164999.6" wire width 2 $0\xer_ov$9$next[1:0]$8902 attribute \src "libresoc.v:164788.3-164789.35" wire width 2 $0\xer_ov$9[1:0]$8836 attribute \src "libresoc.v:164757.13-164757.30" wire width 2 $0\xer_ov$9[1:0]$8936 attribute \src "libresoc.v:164981.3-164999.6" wire $0\xer_ov_ok$next[0:0]$8901 attribute \src "libresoc.v:164790.3-164791.35" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:164962.3-164980.6" wire $0\xer_so$8$next[0:0]$8896 attribute \src "libresoc.v:164792.3-164793.35" wire $0\xer_so$8[0:0]$8839 attribute \src "libresoc.v:164773.7-164773.24" wire $0\xer_so$8[0:0]$8939 attribute \src "libresoc.v:164962.3-164980.6" wire $0\xer_so_ok$next[0:0]$8895 attribute \src "libresoc.v:164794.3-164795.35" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:164943.3-164961.6" wire width 64 $1\fast1$7$next[63:0]$8892 attribute \src "libresoc.v:164943.3-164961.6" wire $1\fast1_ok$next[0:0]$8891 attribute \src "libresoc.v:164129.7-164129.22" wire $1\fast1_ok[0:0] attribute \src "libresoc.v:164876.3-164888.6" wire width 2 $1\muxid$1$next[1:0]$8866 attribute \src "libresoc.v:164905.3-164923.6" wire width 64 $1\o$next[63:0]$8879 attribute \src "libresoc.v:164151.14-164151.38" wire width 64 $1\o[63:0] attribute \src "libresoc.v:164905.3-164923.6" wire $1\o_ok$next[0:0]$8880 attribute \src "libresoc.v:164158.7-164158.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:164858.3-164875.6" wire $1\r_busy$next[0:0]$8862 attribute \src "libresoc.v:164172.7-164172.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:164924.3-164942.6" wire width 64 $1\spr1$6$next[63:0]$8885 attribute \src "libresoc.v:164924.3-164942.6" wire $1\spr1_ok$next[0:0]$8886 attribute \src "libresoc.v:164188.7-164188.21" wire $1\spr1_ok[0:0] attribute \src "libresoc.v:164889.3-164904.6" wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8872 attribute \src "libresoc.v:164889.3-164904.6" wire width 32 $1\spr_op__insn$4$next[31:0]$8873 attribute \src "libresoc.v:164889.3-164904.6" wire width 7 $1\spr_op__insn_type$2$next[6:0]$8874 attribute \src "libresoc.v:164889.3-164904.6" wire $1\spr_op__is_32bit$5$next[0:0]$8875 attribute \src "libresoc.v:165000.3-165018.6" wire width 2 $1\xer_ca$10$next[1:0]$8909 attribute \src "libresoc.v:165000.3-165018.6" wire $1\xer_ca_ok$next[0:0]$8910 attribute \src "libresoc.v:164746.7-164746.23" wire $1\xer_ca_ok[0:0] attribute \src "libresoc.v:164981.3-164999.6" wire width 2 $1\xer_ov$9$next[1:0]$8904 attribute \src "libresoc.v:164981.3-164999.6" wire $1\xer_ov_ok$next[0:0]$8903 attribute \src "libresoc.v:164762.7-164762.23" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:164962.3-164980.6" wire $1\xer_so$8$next[0:0]$8898 attribute \src "libresoc.v:164962.3-164980.6" wire $1\xer_so_ok$next[0:0]$8897 attribute \src "libresoc.v:164778.7-164778.23" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:164943.3-164961.6" wire $2\fast1_ok$next[0:0]$8893 attribute \src "libresoc.v:164905.3-164923.6" wire $2\o_ok$next[0:0]$8881 attribute \src "libresoc.v:164858.3-164875.6" wire $2\r_busy$next[0:0]$8863 attribute \src "libresoc.v:164924.3-164942.6" wire $2\spr1_ok$next[0:0]$8887 attribute \src "libresoc.v:165000.3-165018.6" wire $2\xer_ca_ok$next[0:0]$8911 attribute \src "libresoc.v:164981.3-164999.6" wire $2\xer_ov_ok$next[0:0]$8905 attribute \src "libresoc.v:164962.3-164980.6" wire $2\xer_so_ok$next[0:0]$8899 attribute \src "libresoc.v:164783.18-164783.118" wire $and$libresoc.v:164783$8831_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 26 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$next attribute \src "libresoc.v:164111.7-164111.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 17 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 16 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 15 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr1$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 24 \spr1$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr1$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr1_ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr_main_fast1$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \spr_main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \spr_main_muxid$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr_main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \spr_main_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \spr_main_spr1$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \spr_main_spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \spr_main_spr_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \spr_main_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \spr_main_spr_op__insn$14 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_main_spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_main_spr_op__insn_type$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \spr_main_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \spr_main_spr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \spr_main_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \spr_main_xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \spr_main_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \spr_main_xer_ov$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \spr_main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \spr_main_xer_so_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \spr_op__fn_unit$26 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 19 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \spr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 7 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \spr_op__insn$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 20 \spr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \spr_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 18 \spr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \spr_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \spr_op__is_32bit$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 21 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \spr_op__is_32bit$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 14 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 32 \xer_ca$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 13 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 30 \xer_ov$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 12 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_so$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:164783$8831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o connect \Y $and$libresoc.v:164783$8831_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:164820.10-164823.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:164824.10-164827.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:164828.12-164857.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 connect \fast1_ok \spr_main_fast1_ok connect \muxid \spr_main_muxid connect \muxid$1 \spr_main_muxid$11 connect \o \spr_main_o connect \o_ok \spr_main_o_ok connect \ra \spr_main_ra connect \spr1 \spr_main_spr1 connect \spr1$6 \spr_main_spr1$16 connect \spr1_ok \spr_main_spr1_ok connect \spr_op__fn_unit \spr_main_spr_op__fn_unit connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 connect \spr_op__insn \spr_main_spr_op__insn connect \spr_op__insn$4 \spr_main_spr_op__insn$14 connect \spr_op__insn_type \spr_main_spr_op__insn_type connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 connect \spr_op__is_32bit \spr_main_spr_op__is_32bit connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 connect \xer_ca \spr_main_xer_ca connect \xer_ca$10 \spr_main_xer_ca$20 connect \xer_ca_ok \spr_main_xer_ca_ok connect \xer_ov \spr_main_xer_ov connect \xer_ov$9 \spr_main_xer_ov$19 connect \xer_ov_ok \spr_main_xer_ov_ok connect \xer_so \spr_main_xer_so connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end attribute \src "libresoc.v:164111.7-164111.20" process $proc$libresoc.v:164111$8912 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:164124.14-164124.46" process $proc$libresoc.v:164124$8913 assign { } { } assign $0\fast1$7[63:0]$8914 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$7 $0\fast1$7[63:0]$8914 end attribute \src "libresoc.v:164129.7-164129.22" process $proc$libresoc.v:164129$8915 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end attribute \src "libresoc.v:164138.13-164138.29" process $proc$libresoc.v:164138$8916 assign { } { } assign $0\muxid$1[1:0]$8917 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8917 end attribute \src "libresoc.v:164151.14-164151.38" process $proc$libresoc.v:164151$8918 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end attribute \src "libresoc.v:164158.7-164158.18" process $proc$libresoc.v:164158$8919 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:164172.7-164172.20" process $proc$libresoc.v:164172$8920 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:164183.14-164183.45" process $proc$libresoc.v:164183$8921 assign { } { } assign $0\spr1$6[63:0]$8922 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \spr1$6 $0\spr1$6[63:0]$8922 end attribute \src "libresoc.v:164188.7-164188.21" process $proc$libresoc.v:164188$8923 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end attribute \src "libresoc.v:164480.14-164480.44" process $proc$libresoc.v:164480$8924 assign { } { } assign $0\spr_op__fn_unit$3[13:0]$8925 14'00000000000000 sync always sync init update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8925 end attribute \src "libresoc.v:164489.14-164489.38" process $proc$libresoc.v:164489$8926 assign { } { } assign $0\spr_op__insn$4[31:0]$8927 0 sync always sync init update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8927 end attribute \src "libresoc.v:164646.13-164646.42" process $proc$libresoc.v:164646$8928 assign { } { } assign $0\spr_op__insn_type$2[6:0]$8929 7'0000000 sync always sync init update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8929 end attribute \src "libresoc.v:164732.7-164732.34" process $proc$libresoc.v:164732$8930 assign { } { } assign $0\spr_op__is_32bit$5[0:0]$8931 1'0 sync always sync init update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8931 end attribute \src "libresoc.v:164739.13-164739.31" process $proc$libresoc.v:164739$8932 assign { } { } assign $0\xer_ca$10[1:0]$8933 2'00 sync always sync init update \xer_ca$10 $0\xer_ca$10[1:0]$8933 end attribute \src "libresoc.v:164746.7-164746.23" process $proc$libresoc.v:164746$8934 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end attribute \src "libresoc.v:164757.13-164757.30" process $proc$libresoc.v:164757$8935 assign { } { } assign $0\xer_ov$9[1:0]$8936 2'00 sync always sync init update \xer_ov$9 $0\xer_ov$9[1:0]$8936 end attribute \src "libresoc.v:164762.7-164762.23" process $proc$libresoc.v:164762$8937 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end attribute \src "libresoc.v:164773.7-164773.24" process $proc$libresoc.v:164773$8938 assign { } { } assign $0\xer_so$8[0:0]$8939 1'0 sync always sync init update \xer_so$8 $0\xer_so$8[0:0]$8939 end attribute \src "libresoc.v:164778.7-164778.23" process $proc$libresoc.v:164778$8940 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end attribute \src "libresoc.v:164784.3-164785.37" process $proc$libresoc.v:164784$8832 assign { } { } assign $0\xer_ca$10[1:0]$8833 \xer_ca$10$next sync posedge \coresync_clk update \xer_ca$10 $0\xer_ca$10[1:0]$8833 end attribute \src "libresoc.v:164786.3-164787.35" process $proc$libresoc.v:164786$8834 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end attribute \src "libresoc.v:164788.3-164789.35" process $proc$libresoc.v:164788$8835 assign { } { } assign $0\xer_ov$9[1:0]$8836 \xer_ov$9$next sync posedge \coresync_clk update \xer_ov$9 $0\xer_ov$9[1:0]$8836 end attribute \src "libresoc.v:164790.3-164791.35" process $proc$libresoc.v:164790$8837 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end attribute \src "libresoc.v:164792.3-164793.35" process $proc$libresoc.v:164792$8838 assign { } { } assign $0\xer_so$8[0:0]$8839 \xer_so$8$next sync posedge \coresync_clk update \xer_so$8 $0\xer_so$8[0:0]$8839 end attribute \src "libresoc.v:164794.3-164795.35" process $proc$libresoc.v:164794$8840 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:164796.3-164797.33" process $proc$libresoc.v:164796$8841 assign { } { } assign $0\fast1$7[63:0]$8842 \fast1$7$next sync posedge \coresync_clk update \fast1$7 $0\fast1$7[63:0]$8842 end attribute \src "libresoc.v:164798.3-164799.33" process $proc$libresoc.v:164798$8843 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end attribute \src "libresoc.v:164800.3-164801.31" process $proc$libresoc.v:164800$8844 assign { } { } assign $0\spr1$6[63:0]$8845 \spr1$6$next sync posedge \coresync_clk update \spr1$6 $0\spr1$6[63:0]$8845 end attribute \src "libresoc.v:164802.3-164803.31" process $proc$libresoc.v:164802$8846 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end attribute \src "libresoc.v:164804.3-164805.19" process $proc$libresoc.v:164804$8847 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end attribute \src "libresoc.v:164806.3-164807.25" process $proc$libresoc.v:164806$8848 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:164808.3-164809.57" process $proc$libresoc.v:164808$8849 assign { } { } assign $0\spr_op__insn_type$2[6:0]$8850 \spr_op__insn_type$2$next sync posedge \coresync_clk update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8850 end attribute \src "libresoc.v:164810.3-164811.53" process $proc$libresoc.v:164810$8851 assign { } { } assign $0\spr_op__fn_unit$3[13:0]$8852 \spr_op__fn_unit$3$next sync posedge \coresync_clk update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8852 end attribute \src "libresoc.v:164812.3-164813.47" process $proc$libresoc.v:164812$8853 assign { } { } assign $0\spr_op__insn$4[31:0]$8854 \spr_op__insn$4$next sync posedge \coresync_clk update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8854 end attribute \src "libresoc.v:164814.3-164815.55" process $proc$libresoc.v:164814$8855 assign { } { } assign $0\spr_op__is_32bit$5[0:0]$8856 \spr_op__is_32bit$5$next sync posedge \coresync_clk update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8856 end attribute \src "libresoc.v:164816.3-164817.33" process $proc$libresoc.v:164816$8857 assign { } { } assign $0\muxid$1[1:0]$8858 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8858 end attribute \src "libresoc.v:164818.3-164819.29" process $proc$libresoc.v:164818$8859 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:164858.3-164875.6" process $proc$libresoc.v:164858$8860 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8861 $2\r_busy$next[0:0]$8863 attribute \src "libresoc.v:164859.5-164859.29" switch \initial attribute \src "libresoc.v:164859.9-164859.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$8862 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$8862 1'0 case assign $1\r_busy$next[0:0]$8862 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$8863 1'0 case assign $2\r_busy$next[0:0]$8863 $1\r_busy$next[0:0]$8862 end sync always update \r_busy$next $0\r_busy$next[0:0]$8861 end attribute \src "libresoc.v:164876.3-164888.6" process $proc$libresoc.v:164876$8864 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8865 $1\muxid$1$next[1:0]$8866 attribute \src "libresoc.v:164877.5-164877.29" switch \initial attribute \src "libresoc.v:164877.9-164877.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$8866 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$8866 \muxid$24 case assign $1\muxid$1$next[1:0]$8866 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$8865 end attribute \src "libresoc.v:164889.3-164904.6" process $proc$libresoc.v:164889$8867 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_op__fn_unit$3$next[13:0]$8868 $1\spr_op__fn_unit$3$next[13:0]$8872 assign $0\spr_op__insn$4$next[31:0]$8869 $1\spr_op__insn$4$next[31:0]$8873 assign $0\spr_op__insn_type$2$next[6:0]$8870 $1\spr_op__insn_type$2$next[6:0]$8874 assign $0\spr_op__is_32bit$5$next[0:0]$8871 $1\spr_op__is_32bit$5$next[0:0]$8875 attribute \src "libresoc.v:164890.5-164890.29" switch \initial attribute \src "libresoc.v:164890.9-164890.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\spr_op__is_32bit$5$next[0:0]$8875 $1\spr_op__insn$4$next[31:0]$8873 $1\spr_op__fn_unit$3$next[13:0]$8872 $1\spr_op__insn_type$2$next[6:0]$8874 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\spr_op__is_32bit$5$next[0:0]$8875 $1\spr_op__insn$4$next[31:0]$8873 $1\spr_op__fn_unit$3$next[13:0]$8872 $1\spr_op__insn_type$2$next[6:0]$8874 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case assign $1\spr_op__fn_unit$3$next[13:0]$8872 \spr_op__fn_unit$3 assign $1\spr_op__insn$4$next[31:0]$8873 \spr_op__insn$4 assign $1\spr_op__insn_type$2$next[6:0]$8874 \spr_op__insn_type$2 assign $1\spr_op__is_32bit$5$next[0:0]$8875 \spr_op__is_32bit$5 end sync always update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8868 update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8869 update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8870 update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8871 end attribute \src "libresoc.v:164905.3-164923.6" process $proc$libresoc.v:164905$8876 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$next[63:0]$8877 $1\o$next[63:0]$8879 assign { } { } assign $0\o_ok$next[0:0]$8878 $2\o_ok$next[0:0]$8881 attribute \src "libresoc.v:164906.5-164906.29" switch \initial attribute \src "libresoc.v:164906.9-164906.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$8880 $1\o$next[63:0]$8879 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$8880 $1\o$next[63:0]$8879 } { \o_ok$30 \o$29 } case assign $1\o$next[63:0]$8879 \o assign $1\o_ok$next[0:0]$8880 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$8881 1'0 case assign $2\o_ok$next[0:0]$8881 $1\o_ok$next[0:0]$8880 end sync always update \o$next $0\o$next[63:0]$8877 update \o_ok$next $0\o_ok$next[0:0]$8878 end attribute \src "libresoc.v:164924.3-164942.6" process $proc$libresoc.v:164924$8882 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr1$6$next[63:0]$8883 $1\spr1$6$next[63:0]$8885 assign { } { } assign $0\spr1_ok$next[0:0]$8884 $2\spr1_ok$next[0:0]$8887 attribute \src "libresoc.v:164925.5-164925.29" switch \initial attribute \src "libresoc.v:164925.9-164925.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\spr1_ok$next[0:0]$8886 $1\spr1$6$next[63:0]$8885 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\spr1_ok$next[0:0]$8886 $1\spr1$6$next[63:0]$8885 } { \spr1_ok$32 \spr1$31 } case assign $1\spr1$6$next[63:0]$8885 \spr1$6 assign $1\spr1_ok$next[0:0]$8886 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\spr1_ok$next[0:0]$8887 1'0 case assign $2\spr1_ok$next[0:0]$8887 $1\spr1_ok$next[0:0]$8886 end sync always update \spr1$6$next $0\spr1$6$next[63:0]$8883 update \spr1_ok$next $0\spr1_ok$next[0:0]$8884 end attribute \src "libresoc.v:164943.3-164961.6" process $proc$libresoc.v:164943$8888 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast1$7$next[63:0]$8890 $1\fast1$7$next[63:0]$8892 assign $0\fast1_ok$next[0:0]$8889 $2\fast1_ok$next[0:0]$8893 attribute \src "libresoc.v:164944.5-164944.29" switch \initial attribute \src "libresoc.v:164944.9-164944.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\fast1_ok$next[0:0]$8891 $1\fast1$7$next[63:0]$8892 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\fast1_ok$next[0:0]$8891 $1\fast1$7$next[63:0]$8892 } { \fast1_ok$34 \fast1$33 } case assign $1\fast1_ok$next[0:0]$8891 \fast1_ok assign $1\fast1$7$next[63:0]$8892 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast1_ok$next[0:0]$8893 1'0 case assign $2\fast1_ok$next[0:0]$8893 $1\fast1_ok$next[0:0]$8891 end sync always update \fast1_ok$next $0\fast1_ok$next[0:0]$8889 update \fast1$7$next $0\fast1$7$next[63:0]$8890 end attribute \src "libresoc.v:164962.3-164980.6" process $proc$libresoc.v:164962$8894 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_so$8$next[0:0]$8896 $1\xer_so$8$next[0:0]$8898 assign $0\xer_so_ok$next[0:0]$8895 $2\xer_so_ok$next[0:0]$8899 attribute \src "libresoc.v:164963.5-164963.29" switch \initial attribute \src "libresoc.v:164963.9-164963.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$8897 $1\xer_so$8$next[0:0]$8898 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$8897 $1\xer_so$8$next[0:0]$8898 } { \xer_so_ok$36 \xer_so$35 } case assign $1\xer_so_ok$next[0:0]$8897 \xer_so_ok assign $1\xer_so$8$next[0:0]$8898 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so_ok$next[0:0]$8899 1'0 case assign $2\xer_so_ok$next[0:0]$8899 $1\xer_so_ok$next[0:0]$8897 end sync always update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8895 update \xer_so$8$next $0\xer_so$8$next[0:0]$8896 end attribute \src "libresoc.v:164981.3-164999.6" process $proc$libresoc.v:164981$8900 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ov$9$next[1:0]$8902 $1\xer_ov$9$next[1:0]$8904 assign $0\xer_ov_ok$next[0:0]$8901 $2\xer_ov_ok$next[0:0]$8905 attribute \src "libresoc.v:164982.5-164982.29" switch \initial attribute \src "libresoc.v:164982.9-164982.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$8903 $1\xer_ov$9$next[1:0]$8904 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$8903 $1\xer_ov$9$next[1:0]$8904 } { \xer_ov_ok$38 \xer_ov$37 } case assign $1\xer_ov_ok$next[0:0]$8903 \xer_ov_ok assign $1\xer_ov$9$next[1:0]$8904 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ov_ok$next[0:0]$8905 1'0 case assign $2\xer_ov_ok$next[0:0]$8905 $1\xer_ov_ok$next[0:0]$8903 end sync always update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8901 update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8902 end attribute \src "libresoc.v:165000.3-165018.6" process $proc$libresoc.v:165000$8906 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ca$10$next[1:0]$8907 $1\xer_ca$10$next[1:0]$8909 assign { } { } assign $0\xer_ca_ok$next[0:0]$8908 $2\xer_ca_ok$next[0:0]$8911 attribute \src "libresoc.v:165001.5-165001.29" switch \initial attribute \src "libresoc.v:165001.9-165001.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ca_ok$next[0:0]$8910 $1\xer_ca$10$next[1:0]$8909 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ca_ok$next[0:0]$8910 $1\xer_ca$10$next[1:0]$8909 } { \xer_ca_ok$40 \xer_ca$39 } case assign $1\xer_ca$10$next[1:0]$8909 \xer_ca$10 assign $1\xer_ca_ok$next[0:0]$8910 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ca_ok$next[0:0]$8911 1'0 case assign $2\xer_ca_ok$next[0:0]$8911 $1\xer_ca_ok$next[0:0]$8910 end sync always update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8907 update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8908 end connect \$22 $and$libresoc.v:164783$8831_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } connect \muxid$24 \spr_main_muxid$11 connect \p_valid_i_p_ready_o \$22 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$21 \p_valid_i connect \spr_main_xer_ca \xer_ca connect \spr_main_xer_ov \xer_ov connect \spr_main_xer_so \xer_so connect \spr_main_fast1 \fast1 connect \spr_main_spr1 \spr1 connect \spr_main_ra \ra connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end attribute \src "libresoc.v:165044.1-166536.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 attribute \src "libresoc.v:166450.3-166491.6" wire width 4 $0\alu_op__data_len$next[3:0]$9004 attribute \src "libresoc.v:166226.3-166227.49" wire width 4 $0\alu_op__data_len[3:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 14 $0\alu_op__fn_unit$next[13:0]$9005 attribute \src "libresoc.v:166196.3-166197.47" wire width 14 $0\alu_op__fn_unit[13:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 64 $0\alu_op__imm_data__data$next[63:0]$9006 attribute \src "libresoc.v:166198.3-166199.61" wire width 64 $0\alu_op__imm_data__data[63:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__imm_data__ok$next[0:0]$9007 attribute \src "libresoc.v:166200.3-166201.57" wire $0\alu_op__imm_data__ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 2 $0\alu_op__input_carry$next[1:0]$9008 attribute \src "libresoc.v:166218.3-166219.55" wire width 2 $0\alu_op__input_carry[1:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 32 $0\alu_op__insn$next[31:0]$9009 attribute \src "libresoc.v:166228.3-166229.41" wire width 32 $0\alu_op__insn[31:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 7 $0\alu_op__insn_type$next[6:0]$9010 attribute \src "libresoc.v:166194.3-166195.51" wire width 7 $0\alu_op__insn_type[6:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__invert_in$next[0:0]$9011 attribute \src "libresoc.v:166210.3-166211.51" wire $0\alu_op__invert_in[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__invert_out$next[0:0]$9012 attribute \src "libresoc.v:166214.3-166215.53" wire $0\alu_op__invert_out[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__is_32bit$next[0:0]$9013 attribute \src "libresoc.v:166222.3-166223.49" wire $0\alu_op__is_32bit[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__is_signed$next[0:0]$9014 attribute \src "libresoc.v:166224.3-166225.51" wire $0\alu_op__is_signed[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__oe__oe$next[0:0]$9015 attribute \src "libresoc.v:166206.3-166207.45" wire $0\alu_op__oe__oe[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__oe__ok$next[0:0]$9016 attribute \src "libresoc.v:166208.3-166209.45" wire $0\alu_op__oe__ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__output_carry$next[0:0]$9017 attribute \src "libresoc.v:166220.3-166221.57" wire $0\alu_op__output_carry[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__rc__ok$next[0:0]$9018 attribute \src "libresoc.v:166204.3-166205.45" wire $0\alu_op__rc__ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__rc__rc$next[0:0]$9019 attribute \src "libresoc.v:166202.3-166203.45" wire $0\alu_op__rc__rc[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__write_cr0$next[0:0]$9020 attribute \src "libresoc.v:166216.3-166217.51" wire $0\alu_op__write_cr0[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $0\alu_op__zero_a$next[0:0]$9021 attribute \src "libresoc.v:166212.3-166213.45" wire $0\alu_op__zero_a[0:0] attribute \src "libresoc.v:166343.3-166361.6" wire width 4 $0\cr_a$next[3:0]$8973 attribute \src "libresoc.v:166186.3-166187.25" wire width 4 $0\cr_a[3:0] attribute \src "libresoc.v:166343.3-166361.6" wire $0\cr_a_ok$next[0:0]$8974 attribute \src "libresoc.v:166188.3-166189.31" wire $0\cr_a_ok[0:0] attribute \src "libresoc.v:165045.7-165045.20" wire $0\initial[0:0] attribute \src "libresoc.v:166437.3-166449.6" wire width 2 $0\muxid$next[1:0]$9001 attribute \src "libresoc.v:166230.3-166231.27" wire width 2 $0\muxid[1:0] attribute \src "libresoc.v:166492.3-166510.6" wire width 64 $0\o$next[63:0]$9047 attribute \src "libresoc.v:166190.3-166191.19" wire width 64 $0\o[63:0] attribute \src "libresoc.v:166492.3-166510.6" wire $0\o_ok$next[0:0]$9048 attribute \src "libresoc.v:166192.3-166193.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:166419.3-166436.6" wire $0\r_busy$next[0:0]$8997 attribute \src "libresoc.v:166232.3-166233.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:166362.3-166380.6" wire width 2 $0\xer_ca$next[1:0]$8980 attribute \src "libresoc.v:166182.3-166183.29" wire width 2 $0\xer_ca[1:0] attribute \src "libresoc.v:166362.3-166380.6" wire $0\xer_ca_ok$next[0:0]$8979 attribute \src "libresoc.v:166184.3-166185.35" wire $0\xer_ca_ok[0:0] attribute \src "libresoc.v:166381.3-166399.6" wire width 2 $0\xer_ov$next[1:0]$8985 attribute \src "libresoc.v:166178.3-166179.29" wire width 2 $0\xer_ov[1:0] attribute \src "libresoc.v:166381.3-166399.6" wire $0\xer_ov_ok$next[0:0]$8986 attribute \src "libresoc.v:166180.3-166181.35" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:166400.3-166418.6" wire $0\xer_so$next[0:0]$8991 attribute \src "libresoc.v:166174.3-166175.29" wire $0\xer_so[0:0] attribute \src "libresoc.v:166400.3-166418.6" wire $0\xer_so_ok$next[0:0]$8992 attribute \src "libresoc.v:166176.3-166177.35" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 4 $1\alu_op__data_len$next[3:0]$9022 attribute \src "libresoc.v:165050.13-165050.36" wire width 4 $1\alu_op__data_len[3:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 14 $1\alu_op__fn_unit$next[13:0]$9023 attribute \src "libresoc.v:165074.14-165074.40" wire width 14 $1\alu_op__fn_unit[13:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 64 $1\alu_op__imm_data__data$next[63:0]$9024 attribute \src "libresoc.v:165113.14-165113.59" wire width 64 $1\alu_op__imm_data__data[63:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__imm_data__ok$next[0:0]$9025 attribute \src "libresoc.v:165122.7-165122.34" wire $1\alu_op__imm_data__ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 2 $1\alu_op__input_carry$next[1:0]$9026 attribute \src "libresoc.v:165135.13-165135.39" wire width 2 $1\alu_op__input_carry[1:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 32 $1\alu_op__insn$next[31:0]$9027 attribute \src "libresoc.v:165152.14-165152.34" wire width 32 $1\alu_op__insn[31:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 7 $1\alu_op__insn_type$next[6:0]$9028 attribute \src "libresoc.v:165236.13-165236.38" wire width 7 $1\alu_op__insn_type[6:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__invert_in$next[0:0]$9029 attribute \src "libresoc.v:165395.7-165395.31" wire $1\alu_op__invert_in[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__invert_out$next[0:0]$9030 attribute \src "libresoc.v:165404.7-165404.32" wire $1\alu_op__invert_out[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__is_32bit$next[0:0]$9031 attribute \src "libresoc.v:165413.7-165413.30" wire $1\alu_op__is_32bit[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__is_signed$next[0:0]$9032 attribute \src "libresoc.v:165422.7-165422.31" wire $1\alu_op__is_signed[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__oe__oe$next[0:0]$9033 attribute \src "libresoc.v:165431.7-165431.28" wire $1\alu_op__oe__oe[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__oe__ok$next[0:0]$9034 attribute \src "libresoc.v:165440.7-165440.28" wire $1\alu_op__oe__ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__output_carry$next[0:0]$9035 attribute \src "libresoc.v:165449.7-165449.34" wire $1\alu_op__output_carry[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__rc__ok$next[0:0]$9036 attribute \src "libresoc.v:165458.7-165458.28" wire $1\alu_op__rc__ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__rc__rc$next[0:0]$9037 attribute \src "libresoc.v:165467.7-165467.28" wire $1\alu_op__rc__rc[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__write_cr0$next[0:0]$9038 attribute \src "libresoc.v:165476.7-165476.31" wire $1\alu_op__write_cr0[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire $1\alu_op__zero_a$next[0:0]$9039 attribute \src "libresoc.v:165485.7-165485.28" wire $1\alu_op__zero_a[0:0] attribute \src "libresoc.v:166343.3-166361.6" wire width 4 $1\cr_a$next[3:0]$8975 attribute \src "libresoc.v:165498.13-165498.24" wire width 4 $1\cr_a[3:0] attribute \src "libresoc.v:166343.3-166361.6" wire $1\cr_a_ok$next[0:0]$8976 attribute \src "libresoc.v:165505.7-165505.21" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:166437.3-166449.6" wire width 2 $1\muxid$next[1:0]$9002 attribute \src "libresoc.v:166082.13-166082.25" wire width 2 $1\muxid[1:0] attribute \src "libresoc.v:166492.3-166510.6" wire width 64 $1\o$next[63:0]$9049 attribute \src "libresoc.v:166097.14-166097.38" wire width 64 $1\o[63:0] attribute \src "libresoc.v:166492.3-166510.6" wire $1\o_ok$next[0:0]$9050 attribute \src "libresoc.v:166104.7-166104.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:166419.3-166436.6" wire $1\r_busy$next[0:0]$8998 attribute \src "libresoc.v:166118.7-166118.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:166362.3-166380.6" wire width 2 $1\xer_ca$next[1:0]$8982 attribute \src "libresoc.v:166127.13-166127.26" wire width 2 $1\xer_ca[1:0] attribute \src "libresoc.v:166362.3-166380.6" wire $1\xer_ca_ok$next[0:0]$8981 attribute \src "libresoc.v:166136.7-166136.23" wire $1\xer_ca_ok[0:0] attribute \src "libresoc.v:166381.3-166399.6" wire width 2 $1\xer_ov$next[1:0]$8987 attribute \src "libresoc.v:166143.13-166143.26" wire width 2 $1\xer_ov[1:0] attribute \src "libresoc.v:166381.3-166399.6" wire $1\xer_ov_ok$next[0:0]$8988 attribute \src "libresoc.v:166150.7-166150.23" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:166400.3-166418.6" wire $1\xer_so$next[0:0]$8993 attribute \src "libresoc.v:166157.7-166157.20" wire $1\xer_so[0:0] attribute \src "libresoc.v:166400.3-166418.6" wire $1\xer_so_ok$next[0:0]$8994 attribute \src "libresoc.v:166166.7-166166.23" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:166450.3-166491.6" wire width 64 $2\alu_op__imm_data__data$next[63:0]$9040 attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__imm_data__ok$next[0:0]$9041 attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__oe__oe$next[0:0]$9042 attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__oe__ok$next[0:0]$9043 attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__rc__ok$next[0:0]$9044 attribute \src "libresoc.v:166450.3-166491.6" wire $2\alu_op__rc__rc$next[0:0]$9045 attribute \src "libresoc.v:166343.3-166361.6" wire $2\cr_a_ok$next[0:0]$8977 attribute \src "libresoc.v:166492.3-166510.6" wire $2\o_ok$next[0:0]$9051 attribute \src "libresoc.v:166419.3-166436.6" wire $2\r_busy$next[0:0]$8999 attribute \src "libresoc.v:166362.3-166380.6" wire $2\xer_ca_ok$next[0:0]$8983 attribute \src "libresoc.v:166381.3-166399.6" wire $2\xer_ov_ok$next[0:0]$8989 attribute \src "libresoc.v:166400.3-166418.6" wire $2\xer_so_ok$next[0:0]$8995 attribute \src "libresoc.v:166173.18-166173.118" wire $and$libresoc.v:166173$8941_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 21 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 52 \alu_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 6 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 37 \alu_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_op__fn_unit$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 38 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_op__imm_data__data$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 39 \alu_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__imm_data__ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 17 \alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 48 \alu_op__input_carry$14 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_op__input_carry$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 22 \alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 53 \alu_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_op__insn$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 36 \alu_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 44 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_in$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 46 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_out$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 19 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 50 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_32bit$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 51 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_signed$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__oe$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 42 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__ok$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 43 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 49 \alu_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__output_carry$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 41 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 40 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__rc$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 47 \alu_op__write_cr0$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__write_cr0$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 45 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 58 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "libresoc.v:165045.7-165045.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len$39 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_alu_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_alu_op__imm_data__data$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__imm_data__ok$26 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_alu_op__input_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_alu_op__insn$40 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_alu_op__insn_type$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__invert_in$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__is_32bit$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__is_signed$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__oe__oe$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__oe__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__output_carry$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__rc__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__rc__rc$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_alu_op__zero_a$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \input_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \input_xer_ca$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \main_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \main_alu_op__data_len$62 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_alu_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_alu_op__imm_data__data$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__imm_data__ok$49 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \main_alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \main_alu_op__input_carry$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_alu_op__insn$63 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_alu_op__insn_type$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__invert_out$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__is_32bit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__is_signed$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__oe__oe$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__oe__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__output_carry$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__rc__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__rc__rc$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__write_cr0$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_alu_op__zero_a$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \main_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \main_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \main_xer_ca$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \main_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_so$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 35 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 23 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 34 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 33 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 54 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 55 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 27 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 57 \xer_ca$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 29 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 56 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 32 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:166173$8941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o connect \Y $and$libresoc.v:166173$8941_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:166234.11-166281.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 connect \alu_op__fn_unit \input_alu_op__fn_unit connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 connect \alu_op__imm_data__data \input_alu_op__imm_data__data connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 connect \alu_op__input_carry \input_alu_op__input_carry connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 connect \alu_op__insn \input_alu_op__insn connect \alu_op__insn$19 \input_alu_op__insn$40 connect \alu_op__insn_type \input_alu_op__insn_type connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 connect \alu_op__invert_in \input_alu_op__invert_in connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 connect \alu_op__invert_out \input_alu_op__invert_out connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 connect \alu_op__is_32bit \input_alu_op__is_32bit connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 connect \alu_op__is_signed \input_alu_op__is_signed connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 connect \alu_op__oe__oe \input_alu_op__oe__oe connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 connect \alu_op__oe__ok \input_alu_op__oe__ok connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 connect \alu_op__output_carry \input_alu_op__output_carry connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 connect \alu_op__rc__ok \input_alu_op__rc__ok connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 connect \alu_op__rc__rc \input_alu_op__rc__rc connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 connect \alu_op__write_cr0 \input_alu_op__write_cr0 connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 connect \alu_op__zero_a \input_alu_op__zero_a connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 connect \muxid \input_muxid connect \muxid$1 \input_muxid$22 connect \ra \input_ra connect \ra$20 \input_ra$41 connect \rb \input_rb connect \rb$21 \input_rb$42 connect \xer_ca \input_xer_ca connect \xer_ca$23 \input_xer_ca$44 connect \xer_so \input_xer_so connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 attribute \src "libresoc.v:166282.8-166334.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 connect \alu_op__fn_unit \main_alu_op__fn_unit connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 connect \alu_op__imm_data__data \main_alu_op__imm_data__data connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 connect \alu_op__input_carry \main_alu_op__input_carry connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 connect \alu_op__insn \main_alu_op__insn connect \alu_op__insn$19 \main_alu_op__insn$63 connect \alu_op__insn_type \main_alu_op__insn_type connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 connect \alu_op__invert_in \main_alu_op__invert_in connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 connect \alu_op__invert_out \main_alu_op__invert_out connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 connect \alu_op__is_32bit \main_alu_op__is_32bit connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 connect \alu_op__is_signed \main_alu_op__is_signed connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 connect \alu_op__oe__oe \main_alu_op__oe__oe connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 connect \alu_op__oe__ok \main_alu_op__oe__ok connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 connect \alu_op__output_carry \main_alu_op__output_carry connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 connect \alu_op__rc__ok \main_alu_op__rc__ok connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 connect \alu_op__rc__rc \main_alu_op__rc__rc connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 connect \alu_op__write_cr0 \main_alu_op__write_cr0 connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 connect \alu_op__zero_a \main_alu_op__zero_a connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 connect \cr_a \main_cr_a connect \cr_a_ok \main_cr_a_ok connect \muxid \main_muxid connect \muxid$1 \main_muxid$45 connect \o \main_o connect \o_ok \main_o_ok connect \ra \main_ra connect \rb \main_rb connect \xer_ca \main_xer_ca connect \xer_ca$20 \main_xer_ca$64 connect \xer_ca_ok \main_xer_ca_ok connect \xer_ov \main_xer_ov connect \xer_ov_ok \main_xer_ov_ok connect \xer_so \main_xer_so connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 attribute \src "libresoc.v:166335.9-166338.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:166339.9-166342.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:165045.7-165045.20" process $proc$libresoc.v:165045$9052 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:165050.13-165050.36" process $proc$libresoc.v:165050$9053 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end attribute \src "libresoc.v:165074.14-165074.40" process $proc$libresoc.v:165074$9054 assign { } { } assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end attribute \src "libresoc.v:165113.14-165113.59" process $proc$libresoc.v:165113$9055 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end attribute \src "libresoc.v:165122.7-165122.34" process $proc$libresoc.v:165122$9056 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end attribute \src "libresoc.v:165135.13-165135.39" process $proc$libresoc.v:165135$9057 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end attribute \src "libresoc.v:165152.14-165152.34" process $proc$libresoc.v:165152$9058 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end attribute \src "libresoc.v:165236.13-165236.38" process $proc$libresoc.v:165236$9059 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end attribute \src "libresoc.v:165395.7-165395.31" process $proc$libresoc.v:165395$9060 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end attribute \src "libresoc.v:165404.7-165404.32" process $proc$libresoc.v:165404$9061 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end attribute \src "libresoc.v:165413.7-165413.30" process $proc$libresoc.v:165413$9062 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end attribute \src "libresoc.v:165422.7-165422.31" process $proc$libresoc.v:165422$9063 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end attribute \src "libresoc.v:165431.7-165431.28" process $proc$libresoc.v:165431$9064 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end attribute \src "libresoc.v:165440.7-165440.28" process $proc$libresoc.v:165440$9065 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end attribute \src "libresoc.v:165449.7-165449.34" process $proc$libresoc.v:165449$9066 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end attribute \src "libresoc.v:165458.7-165458.28" process $proc$libresoc.v:165458$9067 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end attribute \src "libresoc.v:165467.7-165467.28" process $proc$libresoc.v:165467$9068 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end attribute \src "libresoc.v:165476.7-165476.31" process $proc$libresoc.v:165476$9069 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end attribute \src "libresoc.v:165485.7-165485.28" process $proc$libresoc.v:165485$9070 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end attribute \src "libresoc.v:165498.13-165498.24" process $proc$libresoc.v:165498$9071 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end attribute \src "libresoc.v:165505.7-165505.21" process $proc$libresoc.v:165505$9072 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end attribute \src "libresoc.v:166082.13-166082.25" process $proc$libresoc.v:166082$9073 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end attribute \src "libresoc.v:166097.14-166097.38" process $proc$libresoc.v:166097$9074 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end attribute \src "libresoc.v:166104.7-166104.18" process $proc$libresoc.v:166104$9075 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:166118.7-166118.20" process $proc$libresoc.v:166118$9076 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:166127.13-166127.26" process $proc$libresoc.v:166127$9077 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end attribute \src "libresoc.v:166136.7-166136.23" process $proc$libresoc.v:166136$9078 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end attribute \src "libresoc.v:166143.13-166143.26" process $proc$libresoc.v:166143$9079 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end attribute \src "libresoc.v:166150.7-166150.23" process $proc$libresoc.v:166150$9080 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end attribute \src "libresoc.v:166157.7-166157.20" process $proc$libresoc.v:166157$9081 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end attribute \src "libresoc.v:166166.7-166166.23" process $proc$libresoc.v:166166$9082 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end attribute \src "libresoc.v:166174.3-166175.29" process $proc$libresoc.v:166174$8942 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end attribute \src "libresoc.v:166176.3-166177.35" process $proc$libresoc.v:166176$8943 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:166178.3-166179.29" process $proc$libresoc.v:166178$8944 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end attribute \src "libresoc.v:166180.3-166181.35" process $proc$libresoc.v:166180$8945 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end attribute \src "libresoc.v:166182.3-166183.29" process $proc$libresoc.v:166182$8946 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end attribute \src "libresoc.v:166184.3-166185.35" process $proc$libresoc.v:166184$8947 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end attribute \src "libresoc.v:166186.3-166187.25" process $proc$libresoc.v:166186$8948 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end attribute \src "libresoc.v:166188.3-166189.31" process $proc$libresoc.v:166188$8949 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end attribute \src "libresoc.v:166190.3-166191.19" process $proc$libresoc.v:166190$8950 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end attribute \src "libresoc.v:166192.3-166193.25" process $proc$libresoc.v:166192$8951 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:166194.3-166195.51" process $proc$libresoc.v:166194$8952 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end attribute \src "libresoc.v:166196.3-166197.47" process $proc$libresoc.v:166196$8953 assign { } { } assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end attribute \src "libresoc.v:166198.3-166199.61" process $proc$libresoc.v:166198$8954 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end attribute \src "libresoc.v:166200.3-166201.57" process $proc$libresoc.v:166200$8955 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end attribute \src "libresoc.v:166202.3-166203.45" process $proc$libresoc.v:166202$8956 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end attribute \src "libresoc.v:166204.3-166205.45" process $proc$libresoc.v:166204$8957 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end attribute \src "libresoc.v:166206.3-166207.45" process $proc$libresoc.v:166206$8958 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end attribute \src "libresoc.v:166208.3-166209.45" process $proc$libresoc.v:166208$8959 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end attribute \src "libresoc.v:166210.3-166211.51" process $proc$libresoc.v:166210$8960 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end attribute \src "libresoc.v:166212.3-166213.45" process $proc$libresoc.v:166212$8961 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end attribute \src "libresoc.v:166214.3-166215.53" process $proc$libresoc.v:166214$8962 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end attribute \src "libresoc.v:166216.3-166217.51" process $proc$libresoc.v:166216$8963 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end attribute \src "libresoc.v:166218.3-166219.55" process $proc$libresoc.v:166218$8964 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end attribute \src "libresoc.v:166220.3-166221.57" process $proc$libresoc.v:166220$8965 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end attribute \src "libresoc.v:166222.3-166223.49" process $proc$libresoc.v:166222$8966 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end attribute \src "libresoc.v:166224.3-166225.51" process $proc$libresoc.v:166224$8967 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end attribute \src "libresoc.v:166226.3-166227.49" process $proc$libresoc.v:166226$8968 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end attribute \src "libresoc.v:166228.3-166229.41" process $proc$libresoc.v:166228$8969 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end attribute \src "libresoc.v:166230.3-166231.27" process $proc$libresoc.v:166230$8970 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end attribute \src "libresoc.v:166232.3-166233.29" process $proc$libresoc.v:166232$8971 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:166343.3-166361.6" process $proc$libresoc.v:166343$8972 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$next[3:0]$8973 $1\cr_a$next[3:0]$8975 assign { } { } assign $0\cr_a_ok$next[0:0]$8974 $2\cr_a_ok$next[0:0]$8977 attribute \src "libresoc.v:166344.5-166344.29" switch \initial attribute \src "libresoc.v:166344.9-166344.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$8976 $1\cr_a$next[3:0]$8975 } { \cr_a_ok$91 \cr_a$90 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$8976 $1\cr_a$next[3:0]$8975 } { \cr_a_ok$91 \cr_a$90 } case assign $1\cr_a$next[3:0]$8975 \cr_a assign $1\cr_a_ok$next[0:0]$8976 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$next[0:0]$8977 1'0 case assign $2\cr_a_ok$next[0:0]$8977 $1\cr_a_ok$next[0:0]$8976 end sync always update \cr_a$next $0\cr_a$next[3:0]$8973 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8974 end attribute \src "libresoc.v:166362.3-166380.6" process $proc$libresoc.v:166362$8978 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ca$next[1:0]$8980 $1\xer_ca$next[1:0]$8982 assign $0\xer_ca_ok$next[0:0]$8979 $2\xer_ca_ok$next[0:0]$8983 attribute \src "libresoc.v:166363.5-166363.29" switch \initial attribute \src "libresoc.v:166363.9-166363.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ca_ok$next[0:0]$8981 $1\xer_ca$next[1:0]$8982 } { \xer_ca_ok$93 \xer_ca$92 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ca_ok$next[0:0]$8981 $1\xer_ca$next[1:0]$8982 } { \xer_ca_ok$93 \xer_ca$92 } case assign $1\xer_ca_ok$next[0:0]$8981 \xer_ca_ok assign $1\xer_ca$next[1:0]$8982 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ca_ok$next[0:0]$8983 1'0 case assign $2\xer_ca_ok$next[0:0]$8983 $1\xer_ca_ok$next[0:0]$8981 end sync always update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8979 update \xer_ca$next $0\xer_ca$next[1:0]$8980 end attribute \src "libresoc.v:166381.3-166399.6" process $proc$libresoc.v:166381$8984 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ov$next[1:0]$8985 $1\xer_ov$next[1:0]$8987 assign { } { } assign $0\xer_ov_ok$next[0:0]$8986 $2\xer_ov_ok$next[0:0]$8989 attribute \src "libresoc.v:166382.5-166382.29" switch \initial attribute \src "libresoc.v:166382.9-166382.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$8988 $1\xer_ov$next[1:0]$8987 } { \xer_ov_ok$95 \xer_ov$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$8988 $1\xer_ov$next[1:0]$8987 } { \xer_ov_ok$95 \xer_ov$94 } case assign $1\xer_ov$next[1:0]$8987 \xer_ov assign $1\xer_ov_ok$next[0:0]$8988 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ov_ok$next[0:0]$8989 1'0 case assign $2\xer_ov_ok$next[0:0]$8989 $1\xer_ov_ok$next[0:0]$8988 end sync always update \xer_ov$next $0\xer_ov$next[1:0]$8985 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8986 end attribute \src "libresoc.v:166400.3-166418.6" process $proc$libresoc.v:166400$8990 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_so$next[0:0]$8991 $1\xer_so$next[0:0]$8993 assign { } { } assign $0\xer_so_ok$next[0:0]$8992 $2\xer_so_ok$next[0:0]$8995 attribute \src "libresoc.v:166401.5-166401.29" switch \initial attribute \src "libresoc.v:166401.9-166401.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$8994 $1\xer_so$next[0:0]$8993 } { \xer_so_ok$97 \xer_so$96 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$8994 $1\xer_so$next[0:0]$8993 } { \xer_so_ok$97 \xer_so$96 } case assign $1\xer_so$next[0:0]$8993 \xer_so assign $1\xer_so_ok$next[0:0]$8994 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so_ok$next[0:0]$8995 1'0 case assign $2\xer_so_ok$next[0:0]$8995 $1\xer_so_ok$next[0:0]$8994 end sync always update \xer_so$next $0\xer_so$next[0:0]$8991 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8992 end attribute \src "libresoc.v:166419.3-166436.6" process $proc$libresoc.v:166419$8996 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8997 $2\r_busy$next[0:0]$8999 attribute \src "libresoc.v:166420.5-166420.29" switch \initial attribute \src "libresoc.v:166420.9-166420.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$8998 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$8998 1'0 case assign $1\r_busy$next[0:0]$8998 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$8999 1'0 case assign $2\r_busy$next[0:0]$8999 $1\r_busy$next[0:0]$8998 end sync always update \r_busy$next $0\r_busy$next[0:0]$8997 end attribute \src "libresoc.v:166437.3-166449.6" process $proc$libresoc.v:166437$9000 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9001 $1\muxid$next[1:0]$9002 attribute \src "libresoc.v:166438.5-166438.29" switch \initial attribute \src "libresoc.v:166438.9-166438.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$next[1:0]$9002 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$next[1:0]$9002 \muxid$69 case assign $1\muxid$next[1:0]$9002 \muxid end sync always update \muxid$next $0\muxid$next[1:0]$9001 end attribute \src "libresoc.v:166450.3-166491.6" process $proc$libresoc.v:166450$9003 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_op__data_len$next[3:0]$9004 $1\alu_op__data_len$next[3:0]$9022 assign $0\alu_op__fn_unit$next[13:0]$9005 $1\alu_op__fn_unit$next[13:0]$9023 assign { } { } assign { } { } assign $0\alu_op__input_carry$next[1:0]$9008 $1\alu_op__input_carry$next[1:0]$9026 assign $0\alu_op__insn$next[31:0]$9009 $1\alu_op__insn$next[31:0]$9027 assign $0\alu_op__insn_type$next[6:0]$9010 $1\alu_op__insn_type$next[6:0]$9028 assign $0\alu_op__invert_in$next[0:0]$9011 $1\alu_op__invert_in$next[0:0]$9029 assign $0\alu_op__invert_out$next[0:0]$9012 $1\alu_op__invert_out$next[0:0]$9030 assign $0\alu_op__is_32bit$next[0:0]$9013 $1\alu_op__is_32bit$next[0:0]$9031 assign $0\alu_op__is_signed$next[0:0]$9014 $1\alu_op__is_signed$next[0:0]$9032 assign { } { } assign { } { } assign $0\alu_op__output_carry$next[0:0]$9017 $1\alu_op__output_carry$next[0:0]$9035 assign { } { } assign { } { } assign $0\alu_op__write_cr0$next[0:0]$9020 $1\alu_op__write_cr0$next[0:0]$9038 assign $0\alu_op__zero_a$next[0:0]$9021 $1\alu_op__zero_a$next[0:0]$9039 assign $0\alu_op__imm_data__data$next[63:0]$9006 $2\alu_op__imm_data__data$next[63:0]$9040 assign $0\alu_op__imm_data__ok$next[0:0]$9007 $2\alu_op__imm_data__ok$next[0:0]$9041 assign $0\alu_op__oe__oe$next[0:0]$9015 $2\alu_op__oe__oe$next[0:0]$9042 assign $0\alu_op__oe__ok$next[0:0]$9016 $2\alu_op__oe__ok$next[0:0]$9043 assign $0\alu_op__rc__ok$next[0:0]$9018 $2\alu_op__rc__ok$next[0:0]$9044 assign $0\alu_op__rc__rc$next[0:0]$9019 $2\alu_op__rc__rc$next[0:0]$9045 attribute \src "libresoc.v:166451.5-166451.29" switch \initial attribute \src "libresoc.v:166451.9-166451.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_op__insn$next[31:0]$9027 $1\alu_op__data_len$next[3:0]$9022 $1\alu_op__is_signed$next[0:0]$9032 $1\alu_op__is_32bit$next[0:0]$9031 $1\alu_op__output_carry$next[0:0]$9035 $1\alu_op__input_carry$next[1:0]$9026 $1\alu_op__write_cr0$next[0:0]$9038 $1\alu_op__invert_out$next[0:0]$9030 $1\alu_op__zero_a$next[0:0]$9039 $1\alu_op__invert_in$next[0:0]$9029 $1\alu_op__oe__ok$next[0:0]$9034 $1\alu_op__oe__oe$next[0:0]$9033 $1\alu_op__rc__ok$next[0:0]$9036 $1\alu_op__rc__rc$next[0:0]$9037 $1\alu_op__imm_data__ok$next[0:0]$9025 $1\alu_op__imm_data__data$next[63:0]$9024 $1\alu_op__fn_unit$next[13:0]$9023 $1\alu_op__insn_type$next[6:0]$9028 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_op__insn$next[31:0]$9027 $1\alu_op__data_len$next[3:0]$9022 $1\alu_op__is_signed$next[0:0]$9032 $1\alu_op__is_32bit$next[0:0]$9031 $1\alu_op__output_carry$next[0:0]$9035 $1\alu_op__input_carry$next[1:0]$9026 $1\alu_op__write_cr0$next[0:0]$9038 $1\alu_op__invert_out$next[0:0]$9030 $1\alu_op__zero_a$next[0:0]$9039 $1\alu_op__invert_in$next[0:0]$9029 $1\alu_op__oe__ok$next[0:0]$9034 $1\alu_op__oe__oe$next[0:0]$9033 $1\alu_op__rc__ok$next[0:0]$9036 $1\alu_op__rc__rc$next[0:0]$9037 $1\alu_op__imm_data__ok$next[0:0]$9025 $1\alu_op__imm_data__data$next[63:0]$9024 $1\alu_op__fn_unit$next[13:0]$9023 $1\alu_op__insn_type$next[6:0]$9028 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } case assign $1\alu_op__data_len$next[3:0]$9022 \alu_op__data_len assign $1\alu_op__fn_unit$next[13:0]$9023 \alu_op__fn_unit assign $1\alu_op__imm_data__data$next[63:0]$9024 \alu_op__imm_data__data assign $1\alu_op__imm_data__ok$next[0:0]$9025 \alu_op__imm_data__ok assign $1\alu_op__input_carry$next[1:0]$9026 \alu_op__input_carry assign $1\alu_op__insn$next[31:0]$9027 \alu_op__insn assign $1\alu_op__insn_type$next[6:0]$9028 \alu_op__insn_type assign $1\alu_op__invert_in$next[0:0]$9029 \alu_op__invert_in assign $1\alu_op__invert_out$next[0:0]$9030 \alu_op__invert_out assign $1\alu_op__is_32bit$next[0:0]$9031 \alu_op__is_32bit assign $1\alu_op__is_signed$next[0:0]$9032 \alu_op__is_signed assign $1\alu_op__oe__oe$next[0:0]$9033 \alu_op__oe__oe assign $1\alu_op__oe__ok$next[0:0]$9034 \alu_op__oe__ok assign $1\alu_op__output_carry$next[0:0]$9035 \alu_op__output_carry assign $1\alu_op__rc__ok$next[0:0]$9036 \alu_op__rc__ok assign $1\alu_op__rc__rc$next[0:0]$9037 \alu_op__rc__rc assign $1\alu_op__write_cr0$next[0:0]$9038 \alu_op__write_cr0 assign $1\alu_op__zero_a$next[0:0]$9039 \alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\alu_op__imm_data__data$next[63:0]$9040 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_op__imm_data__ok$next[0:0]$9041 1'0 assign $2\alu_op__rc__rc$next[0:0]$9045 1'0 assign $2\alu_op__rc__ok$next[0:0]$9044 1'0 assign $2\alu_op__oe__oe$next[0:0]$9042 1'0 assign $2\alu_op__oe__ok$next[0:0]$9043 1'0 case assign $2\alu_op__imm_data__data$next[63:0]$9040 $1\alu_op__imm_data__data$next[63:0]$9024 assign $2\alu_op__imm_data__ok$next[0:0]$9041 $1\alu_op__imm_data__ok$next[0:0]$9025 assign $2\alu_op__oe__oe$next[0:0]$9042 $1\alu_op__oe__oe$next[0:0]$9033 assign $2\alu_op__oe__ok$next[0:0]$9043 $1\alu_op__oe__ok$next[0:0]$9034 assign $2\alu_op__rc__ok$next[0:0]$9044 $1\alu_op__rc__ok$next[0:0]$9036 assign $2\alu_op__rc__rc$next[0:0]$9045 $1\alu_op__rc__rc$next[0:0]$9037 end sync always update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9004 update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9005 update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9006 update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9007 update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9008 update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9009 update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9010 update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9011 update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9012 update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9013 update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9014 update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9015 update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9016 update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9017 update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9018 update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9019 update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9020 update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9021 end attribute \src "libresoc.v:166492.3-166510.6" process $proc$libresoc.v:166492$9046 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$next[63:0]$9047 $1\o$next[63:0]$9049 assign { } { } assign $0\o_ok$next[0:0]$9048 $2\o_ok$next[0:0]$9051 attribute \src "libresoc.v:166493.5-166493.29" switch \initial attribute \src "libresoc.v:166493.9-166493.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9050 $1\o$next[63:0]$9049 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9050 $1\o$next[63:0]$9049 } { \o_ok$89 \o$88 } case assign $1\o$next[63:0]$9049 \o assign $1\o_ok$next[0:0]$9050 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$9051 1'0 case assign $2\o_ok$next[0:0]$9051 $1\o_ok$next[0:0]$9050 end sync always update \o$next $0\o$next[63:0]$9047 update \o_ok$next $0\o_ok$next[0:0]$9048 end connect \$67 $and$libresoc.v:166173$8941_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } connect \muxid$69 \main_muxid$45 connect \p_valid_i_p_ready_o \$67 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$66 \p_valid_i connect \main_xer_ca \input_xer_ca$44 connect \main_xer_so \input_xer_so$43 connect \main_rb \input_rb$42 connect \main_ra \input_ra$41 connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } connect \main_muxid \input_muxid$22 connect \input_xer_ca \xer_ca$21 connect \input_xer_so \xer_so$20 connect \input_rb \rb connect \input_ra \ra connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end attribute \src "libresoc.v:166540.1-167976.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 attribute \src "libresoc.v:167909.3-167927.6" wire width 4 $0\cr_a$next[3:0]$9172 attribute \src "libresoc.v:167651.3-167652.25" wire width 4 $0\cr_a[3:0] attribute \src "libresoc.v:167909.3-167927.6" wire $0\cr_a_ok$next[0:0]$9173 attribute \src "libresoc.v:167653.3-167654.31" wire $0\cr_a_ok[0:0] attribute \src "libresoc.v:166541.7-166541.20" wire $0\initial[0:0] attribute \src "libresoc.v:167836.3-167848.6" wire width 2 $0\muxid$next[1:0]$9122 attribute \src "libresoc.v:167693.3-167694.27" wire width 2 $0\muxid[1:0] attribute \src "libresoc.v:167890.3-167908.6" wire width 64 $0\o$next[63:0]$9166 attribute \src "libresoc.v:167655.3-167656.19" wire width 64 $0\o[63:0] attribute \src "libresoc.v:167890.3-167908.6" wire $0\o_ok$next[0:0]$9167 attribute \src "libresoc.v:167657.3-167658.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:167818.3-167835.6" wire $0\r_busy$next[0:0]$9118 attribute \src "libresoc.v:167695.3-167696.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 14 $0\sr_op__fn_unit$next[13:0]$9125 attribute \src "libresoc.v:167661.3-167662.45" wire width 14 $0\sr_op__fn_unit[13:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 64 $0\sr_op__imm_data__data$next[63:0]$9126 attribute \src "libresoc.v:167663.3-167664.59" wire width 64 $0\sr_op__imm_data__data[63:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__imm_data__ok$next[0:0]$9127 attribute \src "libresoc.v:167665.3-167666.55" wire $0\sr_op__imm_data__ok[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 2 $0\sr_op__input_carry$next[1:0]$9128 attribute \src "libresoc.v:167679.3-167680.53" wire width 2 $0\sr_op__input_carry[1:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__input_cr$next[0:0]$9129 attribute \src "libresoc.v:167683.3-167684.47" wire $0\sr_op__input_cr[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 32 $0\sr_op__insn$next[31:0]$9130 attribute \src "libresoc.v:167691.3-167692.39" wire width 32 $0\sr_op__insn[31:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 7 $0\sr_op__insn_type$next[6:0]$9131 attribute \src "libresoc.v:167659.3-167660.49" wire width 7 $0\sr_op__insn_type[6:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__invert_in$next[0:0]$9132 attribute \src "libresoc.v:167677.3-167678.49" wire $0\sr_op__invert_in[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__is_32bit$next[0:0]$9133 attribute \src "libresoc.v:167687.3-167688.47" wire $0\sr_op__is_32bit[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__is_signed$next[0:0]$9134 attribute \src "libresoc.v:167689.3-167690.49" wire $0\sr_op__is_signed[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__oe__oe$next[0:0]$9135 attribute \src "libresoc.v:167671.3-167672.43" wire $0\sr_op__oe__oe[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__oe__ok$next[0:0]$9136 attribute \src "libresoc.v:167673.3-167674.43" wire $0\sr_op__oe__ok[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__output_carry$next[0:0]$9137 attribute \src "libresoc.v:167681.3-167682.55" wire $0\sr_op__output_carry[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__output_cr$next[0:0]$9138 attribute \src "libresoc.v:167685.3-167686.49" wire $0\sr_op__output_cr[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__rc__ok$next[0:0]$9139 attribute \src "libresoc.v:167669.3-167670.43" wire $0\sr_op__rc__ok[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__rc__rc$next[0:0]$9140 attribute \src "libresoc.v:167667.3-167668.43" wire $0\sr_op__rc__rc[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $0\sr_op__write_cr0$next[0:0]$9141 attribute \src "libresoc.v:167675.3-167676.49" wire $0\sr_op__write_cr0[0:0] attribute \src "libresoc.v:167799.3-167817.6" wire width 2 $0\xer_ca$next[1:0]$9113 attribute \src "libresoc.v:167643.3-167644.29" wire width 2 $0\xer_ca[1:0] attribute \src "libresoc.v:167799.3-167817.6" wire $0\xer_ca_ok$next[0:0]$9112 attribute \src "libresoc.v:167645.3-167646.35" wire $0\xer_ca_ok[0:0] attribute \src "libresoc.v:167928.3-167946.6" wire $0\xer_so$next[0:0]$9178 attribute \src "libresoc.v:167647.3-167648.29" wire $0\xer_so[0:0] attribute \src "libresoc.v:167928.3-167946.6" wire $0\xer_so_ok$next[0:0]$9179 attribute \src "libresoc.v:167649.3-167650.35" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:167909.3-167927.6" wire width 4 $1\cr_a$next[3:0]$9174 attribute \src "libresoc.v:166550.13-166550.24" wire width 4 $1\cr_a[3:0] attribute \src "libresoc.v:167909.3-167927.6" wire $1\cr_a_ok$next[0:0]$9175 attribute \src "libresoc.v:166559.7-166559.21" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:167836.3-167848.6" wire width 2 $1\muxid$next[1:0]$9123 attribute \src "libresoc.v:167124.13-167124.25" wire width 2 $1\muxid[1:0] attribute \src "libresoc.v:167890.3-167908.6" wire width 64 $1\o$next[63:0]$9168 attribute \src "libresoc.v:167139.14-167139.38" wire width 64 $1\o[63:0] attribute \src "libresoc.v:167890.3-167908.6" wire $1\o_ok$next[0:0]$9169 attribute \src "libresoc.v:167146.7-167146.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:167818.3-167835.6" wire $1\r_busy$next[0:0]$9119 attribute \src "libresoc.v:167160.7-167160.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 14 $1\sr_op__fn_unit$next[13:0]$9142 attribute \src "libresoc.v:167186.14-167186.39" wire width 14 $1\sr_op__fn_unit[13:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 64 $1\sr_op__imm_data__data$next[63:0]$9143 attribute \src "libresoc.v:167225.14-167225.58" wire width 64 $1\sr_op__imm_data__data[63:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__imm_data__ok$next[0:0]$9144 attribute \src "libresoc.v:167234.7-167234.33" wire $1\sr_op__imm_data__ok[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 2 $1\sr_op__input_carry$next[1:0]$9145 attribute \src "libresoc.v:167247.13-167247.38" wire width 2 $1\sr_op__input_carry[1:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__input_cr$next[0:0]$9146 attribute \src "libresoc.v:167264.7-167264.29" wire $1\sr_op__input_cr[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 32 $1\sr_op__insn$next[31:0]$9147 attribute \src "libresoc.v:167273.14-167273.33" wire width 32 $1\sr_op__insn[31:0] attribute \src "libresoc.v:167849.3-167889.6" wire width 7 $1\sr_op__insn_type$next[6:0]$9148 attribute \src "libresoc.v:167357.13-167357.37" wire width 7 $1\sr_op__insn_type[6:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__invert_in$next[0:0]$9149 attribute \src "libresoc.v:167516.7-167516.30" wire $1\sr_op__invert_in[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__is_32bit$next[0:0]$9150 attribute \src "libresoc.v:167525.7-167525.29" wire $1\sr_op__is_32bit[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__is_signed$next[0:0]$9151 attribute \src "libresoc.v:167534.7-167534.30" wire $1\sr_op__is_signed[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__oe__oe$next[0:0]$9152 attribute \src "libresoc.v:167543.7-167543.27" wire $1\sr_op__oe__oe[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__oe__ok$next[0:0]$9153 attribute \src "libresoc.v:167552.7-167552.27" wire $1\sr_op__oe__ok[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__output_carry$next[0:0]$9154 attribute \src "libresoc.v:167561.7-167561.33" wire $1\sr_op__output_carry[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__output_cr$next[0:0]$9155 attribute \src "libresoc.v:167570.7-167570.30" wire $1\sr_op__output_cr[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__rc__ok$next[0:0]$9156 attribute \src "libresoc.v:167579.7-167579.27" wire $1\sr_op__rc__ok[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__rc__rc$next[0:0]$9157 attribute \src "libresoc.v:167588.7-167588.27" wire $1\sr_op__rc__rc[0:0] attribute \src "libresoc.v:167849.3-167889.6" wire $1\sr_op__write_cr0$next[0:0]$9158 attribute \src "libresoc.v:167597.7-167597.30" wire $1\sr_op__write_cr0[0:0] attribute \src "libresoc.v:167799.3-167817.6" wire width 2 $1\xer_ca$next[1:0]$9115 attribute \src "libresoc.v:167606.13-167606.26" wire width 2 $1\xer_ca[1:0] attribute \src "libresoc.v:167799.3-167817.6" wire $1\xer_ca_ok$next[0:0]$9114 attribute \src "libresoc.v:167617.7-167617.23" wire $1\xer_ca_ok[0:0] attribute \src "libresoc.v:167928.3-167946.6" wire $1\xer_so$next[0:0]$9180 attribute \src "libresoc.v:167626.7-167626.20" wire $1\xer_so[0:0] attribute \src "libresoc.v:167928.3-167946.6" wire $1\xer_so_ok$next[0:0]$9181 attribute \src "libresoc.v:167635.7-167635.23" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:167909.3-167927.6" wire $2\cr_a_ok$next[0:0]$9176 attribute \src "libresoc.v:167890.3-167908.6" wire $2\o_ok$next[0:0]$9170 attribute \src "libresoc.v:167818.3-167835.6" wire $2\r_busy$next[0:0]$9120 attribute \src "libresoc.v:167849.3-167889.6" wire width 64 $2\sr_op__imm_data__data$next[63:0]$9159 attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__imm_data__ok$next[0:0]$9160 attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__oe__oe$next[0:0]$9161 attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__oe__ok$next[0:0]$9162 attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__rc__ok$next[0:0]$9163 attribute \src "libresoc.v:167849.3-167889.6" wire $2\sr_op__rc__rc$next[0:0]$9164 attribute \src "libresoc.v:167799.3-167817.6" wire $2\xer_ca_ok$next[0:0]$9116 attribute \src "libresoc.v:167928.3-167946.6" wire $2\xer_so_ok$next[0:0]$9182 attribute \src "libresoc.v:167642.18-167642.118" wire $and$libresoc.v:167642$9083_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 55 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 24 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "libresoc.v:166541.7-166541.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rc$41 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_sr_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_sr_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__imm_data__ok$25 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_sr_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__input_cr$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_sr_op__insn$38 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_sr_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__invert_in$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__output_carry$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__output_cr$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_sr_op__write_cr0$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \input_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \input_xer_ca$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rc attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_sr_op__fn_unit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_sr_op__imm_data__data$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__imm_data__ok$48 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \main_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \main_sr_op__input_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__input_cr$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_sr_op__insn$61 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_sr_op__insn_type$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__is_32bit$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__is_signed$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__oe__oe$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__oe__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__output_carry$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__output_cr$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__rc__ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__rc__rc$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_sr_op__write_cr0$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \main_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_xer_so$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 32 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 31 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 30 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$64 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 50 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 51 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 52 \rc attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 6 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 34 \sr_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \sr_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 35 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \sr_op__imm_data__data$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \sr_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 36 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__imm_data__ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 15 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 43 \sr_op__input_carry$12 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \sr_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \sr_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 17 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 45 \sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__input_cr$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__input_cr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 21 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 49 \sr_op__insn$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \sr_op__insn$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \sr_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 33 \sr_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__invert_in$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 19 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 47 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 48 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 39 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 40 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 44 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_carry$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 46 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_cr$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_cr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 38 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 37 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__rc$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 41 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 28 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 54 \xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \xer_ca$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 26 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 53 \xer_so$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:167642$9083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o connect \Y $and$libresoc.v:167642$9083_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:167697.15-167744.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 connect \ra \input_ra connect \ra$19 \input_ra$39 connect \rb \input_rb connect \rb$20 \input_rb$40 connect \rc \input_rc connect \rc$21 \input_rc$41 connect \sr_op__fn_unit \input_sr_op__fn_unit connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 connect \sr_op__imm_data__data \input_sr_op__imm_data__data connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 connect \sr_op__input_carry \input_sr_op__input_carry connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 connect \sr_op__input_cr \input_sr_op__input_cr connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 connect \sr_op__insn \input_sr_op__insn connect \sr_op__insn$18 \input_sr_op__insn$38 connect \sr_op__insn_type \input_sr_op__insn_type connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 connect \sr_op__invert_in \input_sr_op__invert_in connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 connect \sr_op__is_32bit \input_sr_op__is_32bit connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 connect \sr_op__is_signed \input_sr_op__is_signed connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 connect \sr_op__oe__oe \input_sr_op__oe__oe connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 connect \sr_op__oe__ok \input_sr_op__oe__ok connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 connect \sr_op__output_carry \input_sr_op__output_carry connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 connect \sr_op__output_cr \input_sr_op__output_cr connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 connect \sr_op__rc__ok \input_sr_op__rc__ok connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 connect \sr_op__rc__rc \input_sr_op__rc__rc connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 connect \sr_op__write_cr0 \input_sr_op__write_cr0 connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 connect \xer_ca \input_xer_ca connect \xer_ca$23 \input_xer_ca$43 connect \xer_so \input_xer_so connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 attribute \src "libresoc.v:167745.14-167790.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 connect \o \main_o connect \o_ok \main_o_ok connect \ra \main_ra connect \rb \main_rb connect \rc \main_rc connect \sr_op__fn_unit \main_sr_op__fn_unit connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 connect \sr_op__imm_data__data \main_sr_op__imm_data__data connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 connect \sr_op__input_carry \main_sr_op__input_carry connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 connect \sr_op__input_cr \main_sr_op__input_cr connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 connect \sr_op__insn \main_sr_op__insn connect \sr_op__insn$18 \main_sr_op__insn$61 connect \sr_op__insn_type \main_sr_op__insn_type connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 connect \sr_op__invert_in \main_sr_op__invert_in connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 connect \sr_op__is_32bit \main_sr_op__is_32bit connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 connect \sr_op__is_signed \main_sr_op__is_signed connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 connect \sr_op__oe__oe \main_sr_op__oe__oe connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 connect \sr_op__oe__ok \main_sr_op__oe__ok connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 connect \sr_op__output_carry \main_sr_op__output_carry connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 connect \sr_op__output_cr \main_sr_op__output_cr connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 connect \sr_op__rc__ok \main_sr_op__rc__ok connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 connect \sr_op__rc__rc \main_sr_op__rc__rc connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 connect \sr_op__write_cr0 \main_sr_op__write_cr0 connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 connect \xer_ca \main_xer_ca connect \xer_so \main_xer_so connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 attribute \src "libresoc.v:167791.11-167794.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:167795.11-167798.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:166541.7-166541.20" process $proc$libresoc.v:166541$9183 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:166550.13-166550.24" process $proc$libresoc.v:166550$9184 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end attribute \src "libresoc.v:166559.7-166559.21" process $proc$libresoc.v:166559$9185 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end attribute \src "libresoc.v:167124.13-167124.25" process $proc$libresoc.v:167124$9186 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end attribute \src "libresoc.v:167139.14-167139.38" process $proc$libresoc.v:167139$9187 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end attribute \src "libresoc.v:167146.7-167146.18" process $proc$libresoc.v:167146$9188 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:167160.7-167160.20" process $proc$libresoc.v:167160$9189 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:167186.14-167186.39" process $proc$libresoc.v:167186$9190 assign { } { } assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end attribute \src "libresoc.v:167225.14-167225.58" process $proc$libresoc.v:167225$9191 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end attribute \src "libresoc.v:167234.7-167234.33" process $proc$libresoc.v:167234$9192 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end attribute \src "libresoc.v:167247.13-167247.38" process $proc$libresoc.v:167247$9193 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end attribute \src "libresoc.v:167264.7-167264.29" process $proc$libresoc.v:167264$9194 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end attribute \src "libresoc.v:167273.14-167273.33" process $proc$libresoc.v:167273$9195 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end attribute \src "libresoc.v:167357.13-167357.37" process $proc$libresoc.v:167357$9196 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end attribute \src "libresoc.v:167516.7-167516.30" process $proc$libresoc.v:167516$9197 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end attribute \src "libresoc.v:167525.7-167525.29" process $proc$libresoc.v:167525$9198 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end attribute \src "libresoc.v:167534.7-167534.30" process $proc$libresoc.v:167534$9199 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end attribute \src "libresoc.v:167543.7-167543.27" process $proc$libresoc.v:167543$9200 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end attribute \src "libresoc.v:167552.7-167552.27" process $proc$libresoc.v:167552$9201 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end attribute \src "libresoc.v:167561.7-167561.33" process $proc$libresoc.v:167561$9202 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end attribute \src "libresoc.v:167570.7-167570.30" process $proc$libresoc.v:167570$9203 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end attribute \src "libresoc.v:167579.7-167579.27" process $proc$libresoc.v:167579$9204 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end attribute \src "libresoc.v:167588.7-167588.27" process $proc$libresoc.v:167588$9205 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end attribute \src "libresoc.v:167597.7-167597.30" process $proc$libresoc.v:167597$9206 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end attribute \src "libresoc.v:167606.13-167606.26" process $proc$libresoc.v:167606$9207 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end attribute \src "libresoc.v:167617.7-167617.23" process $proc$libresoc.v:167617$9208 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end attribute \src "libresoc.v:167626.7-167626.20" process $proc$libresoc.v:167626$9209 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end attribute \src "libresoc.v:167635.7-167635.23" process $proc$libresoc.v:167635$9210 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end attribute \src "libresoc.v:167643.3-167644.29" process $proc$libresoc.v:167643$9084 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end attribute \src "libresoc.v:167645.3-167646.35" process $proc$libresoc.v:167645$9085 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end attribute \src "libresoc.v:167647.3-167648.29" process $proc$libresoc.v:167647$9086 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end attribute \src "libresoc.v:167649.3-167650.35" process $proc$libresoc.v:167649$9087 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:167651.3-167652.25" process $proc$libresoc.v:167651$9088 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end attribute \src "libresoc.v:167653.3-167654.31" process $proc$libresoc.v:167653$9089 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end attribute \src "libresoc.v:167655.3-167656.19" process $proc$libresoc.v:167655$9090 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end attribute \src "libresoc.v:167657.3-167658.25" process $proc$libresoc.v:167657$9091 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:167659.3-167660.49" process $proc$libresoc.v:167659$9092 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end attribute \src "libresoc.v:167661.3-167662.45" process $proc$libresoc.v:167661$9093 assign { } { } assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end attribute \src "libresoc.v:167663.3-167664.59" process $proc$libresoc.v:167663$9094 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end attribute \src "libresoc.v:167665.3-167666.55" process $proc$libresoc.v:167665$9095 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end attribute \src "libresoc.v:167667.3-167668.43" process $proc$libresoc.v:167667$9096 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end attribute \src "libresoc.v:167669.3-167670.43" process $proc$libresoc.v:167669$9097 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end attribute \src "libresoc.v:167671.3-167672.43" process $proc$libresoc.v:167671$9098 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end attribute \src "libresoc.v:167673.3-167674.43" process $proc$libresoc.v:167673$9099 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end attribute \src "libresoc.v:167675.3-167676.49" process $proc$libresoc.v:167675$9100 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end attribute \src "libresoc.v:167677.3-167678.49" process $proc$libresoc.v:167677$9101 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end attribute \src "libresoc.v:167679.3-167680.53" process $proc$libresoc.v:167679$9102 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end attribute \src "libresoc.v:167681.3-167682.55" process $proc$libresoc.v:167681$9103 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end attribute \src "libresoc.v:167683.3-167684.47" process $proc$libresoc.v:167683$9104 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end attribute \src "libresoc.v:167685.3-167686.49" process $proc$libresoc.v:167685$9105 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end attribute \src "libresoc.v:167687.3-167688.47" process $proc$libresoc.v:167687$9106 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end attribute \src "libresoc.v:167689.3-167690.49" process $proc$libresoc.v:167689$9107 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end attribute \src "libresoc.v:167691.3-167692.39" process $proc$libresoc.v:167691$9108 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end attribute \src "libresoc.v:167693.3-167694.27" process $proc$libresoc.v:167693$9109 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end attribute \src "libresoc.v:167695.3-167696.29" process $proc$libresoc.v:167695$9110 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:167799.3-167817.6" process $proc$libresoc.v:167799$9111 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ca$next[1:0]$9113 $1\xer_ca$next[1:0]$9115 assign $0\xer_ca_ok$next[0:0]$9112 $2\xer_ca_ok$next[0:0]$9116 attribute \src "libresoc.v:167800.5-167800.29" switch \initial attribute \src "libresoc.v:167800.9-167800.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ca_ok$next[0:0]$9114 $1\xer_ca$next[1:0]$9115 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ca_ok$next[0:0]$9114 $1\xer_ca$next[1:0]$9115 } { \xer_ca_ok$95 \xer_ca$94 } case assign $1\xer_ca_ok$next[0:0]$9114 \xer_ca_ok assign $1\xer_ca$next[1:0]$9115 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ca_ok$next[0:0]$9116 1'0 case assign $2\xer_ca_ok$next[0:0]$9116 $1\xer_ca_ok$next[0:0]$9114 end sync always update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9112 update \xer_ca$next $0\xer_ca$next[1:0]$9113 end attribute \src "libresoc.v:167818.3-167835.6" process $proc$libresoc.v:167818$9117 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9118 $2\r_busy$next[0:0]$9120 attribute \src "libresoc.v:167819.5-167819.29" switch \initial attribute \src "libresoc.v:167819.9-167819.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$9119 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$9119 1'0 case assign $1\r_busy$next[0:0]$9119 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$9120 1'0 case assign $2\r_busy$next[0:0]$9120 $1\r_busy$next[0:0]$9119 end sync always update \r_busy$next $0\r_busy$next[0:0]$9118 end attribute \src "libresoc.v:167836.3-167848.6" process $proc$libresoc.v:167836$9121 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9122 $1\muxid$next[1:0]$9123 attribute \src "libresoc.v:167837.5-167837.29" switch \initial attribute \src "libresoc.v:167837.9-167837.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$next[1:0]$9123 \muxid$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$next[1:0]$9123 \muxid$67 case assign $1\muxid$next[1:0]$9123 \muxid end sync always update \muxid$next $0\muxid$next[1:0]$9122 end attribute \src "libresoc.v:167849.3-167889.6" process $proc$libresoc.v:167849$9124 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr_op__fn_unit$next[13:0]$9125 $1\sr_op__fn_unit$next[13:0]$9142 assign { } { } assign { } { } assign $0\sr_op__input_carry$next[1:0]$9128 $1\sr_op__input_carry$next[1:0]$9145 assign $0\sr_op__input_cr$next[0:0]$9129 $1\sr_op__input_cr$next[0:0]$9146 assign $0\sr_op__insn$next[31:0]$9130 $1\sr_op__insn$next[31:0]$9147 assign $0\sr_op__insn_type$next[6:0]$9131 $1\sr_op__insn_type$next[6:0]$9148 assign $0\sr_op__invert_in$next[0:0]$9132 $1\sr_op__invert_in$next[0:0]$9149 assign $0\sr_op__is_32bit$next[0:0]$9133 $1\sr_op__is_32bit$next[0:0]$9150 assign $0\sr_op__is_signed$next[0:0]$9134 $1\sr_op__is_signed$next[0:0]$9151 assign { } { } assign { } { } assign $0\sr_op__output_carry$next[0:0]$9137 $1\sr_op__output_carry$next[0:0]$9154 assign $0\sr_op__output_cr$next[0:0]$9138 $1\sr_op__output_cr$next[0:0]$9155 assign { } { } assign { } { } assign $0\sr_op__write_cr0$next[0:0]$9141 $1\sr_op__write_cr0$next[0:0]$9158 assign $0\sr_op__imm_data__data$next[63:0]$9126 $2\sr_op__imm_data__data$next[63:0]$9159 assign $0\sr_op__imm_data__ok$next[0:0]$9127 $2\sr_op__imm_data__ok$next[0:0]$9160 assign $0\sr_op__oe__oe$next[0:0]$9135 $2\sr_op__oe__oe$next[0:0]$9161 assign $0\sr_op__oe__ok$next[0:0]$9136 $2\sr_op__oe__ok$next[0:0]$9162 assign $0\sr_op__rc__ok$next[0:0]$9139 $2\sr_op__rc__ok$next[0:0]$9163 assign $0\sr_op__rc__rc$next[0:0]$9140 $2\sr_op__rc__rc$next[0:0]$9164 attribute \src "libresoc.v:167850.5-167850.29" switch \initial attribute \src "libresoc.v:167850.9-167850.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\sr_op__insn$next[31:0]$9147 $1\sr_op__is_signed$next[0:0]$9151 $1\sr_op__is_32bit$next[0:0]$9150 $1\sr_op__output_cr$next[0:0]$9155 $1\sr_op__input_cr$next[0:0]$9146 $1\sr_op__output_carry$next[0:0]$9154 $1\sr_op__input_carry$next[1:0]$9145 $1\sr_op__invert_in$next[0:0]$9149 $1\sr_op__write_cr0$next[0:0]$9158 $1\sr_op__oe__ok$next[0:0]$9153 $1\sr_op__oe__oe$next[0:0]$9152 $1\sr_op__rc__ok$next[0:0]$9156 $1\sr_op__rc__rc$next[0:0]$9157 $1\sr_op__imm_data__ok$next[0:0]$9144 $1\sr_op__imm_data__data$next[63:0]$9143 $1\sr_op__fn_unit$next[13:0]$9142 $1\sr_op__insn_type$next[6:0]$9148 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\sr_op__insn$next[31:0]$9147 $1\sr_op__is_signed$next[0:0]$9151 $1\sr_op__is_32bit$next[0:0]$9150 $1\sr_op__output_cr$next[0:0]$9155 $1\sr_op__input_cr$next[0:0]$9146 $1\sr_op__output_carry$next[0:0]$9154 $1\sr_op__input_carry$next[1:0]$9145 $1\sr_op__invert_in$next[0:0]$9149 $1\sr_op__write_cr0$next[0:0]$9158 $1\sr_op__oe__ok$next[0:0]$9153 $1\sr_op__oe__oe$next[0:0]$9152 $1\sr_op__rc__ok$next[0:0]$9156 $1\sr_op__rc__rc$next[0:0]$9157 $1\sr_op__imm_data__ok$next[0:0]$9144 $1\sr_op__imm_data__data$next[63:0]$9143 $1\sr_op__fn_unit$next[13:0]$9142 $1\sr_op__insn_type$next[6:0]$9148 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case assign $1\sr_op__fn_unit$next[13:0]$9142 \sr_op__fn_unit assign $1\sr_op__imm_data__data$next[63:0]$9143 \sr_op__imm_data__data assign $1\sr_op__imm_data__ok$next[0:0]$9144 \sr_op__imm_data__ok assign $1\sr_op__input_carry$next[1:0]$9145 \sr_op__input_carry assign $1\sr_op__input_cr$next[0:0]$9146 \sr_op__input_cr assign $1\sr_op__insn$next[31:0]$9147 \sr_op__insn assign $1\sr_op__insn_type$next[6:0]$9148 \sr_op__insn_type assign $1\sr_op__invert_in$next[0:0]$9149 \sr_op__invert_in assign $1\sr_op__is_32bit$next[0:0]$9150 \sr_op__is_32bit assign $1\sr_op__is_signed$next[0:0]$9151 \sr_op__is_signed assign $1\sr_op__oe__oe$next[0:0]$9152 \sr_op__oe__oe assign $1\sr_op__oe__ok$next[0:0]$9153 \sr_op__oe__ok assign $1\sr_op__output_carry$next[0:0]$9154 \sr_op__output_carry assign $1\sr_op__output_cr$next[0:0]$9155 \sr_op__output_cr assign $1\sr_op__rc__ok$next[0:0]$9156 \sr_op__rc__ok assign $1\sr_op__rc__rc$next[0:0]$9157 \sr_op__rc__rc assign $1\sr_op__write_cr0$next[0:0]$9158 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\sr_op__imm_data__data$next[63:0]$9159 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\sr_op__imm_data__ok$next[0:0]$9160 1'0 assign $2\sr_op__rc__rc$next[0:0]$9164 1'0 assign $2\sr_op__rc__ok$next[0:0]$9163 1'0 assign $2\sr_op__oe__oe$next[0:0]$9161 1'0 assign $2\sr_op__oe__ok$next[0:0]$9162 1'0 case assign $2\sr_op__imm_data__data$next[63:0]$9159 $1\sr_op__imm_data__data$next[63:0]$9143 assign $2\sr_op__imm_data__ok$next[0:0]$9160 $1\sr_op__imm_data__ok$next[0:0]$9144 assign $2\sr_op__oe__oe$next[0:0]$9161 $1\sr_op__oe__oe$next[0:0]$9152 assign $2\sr_op__oe__ok$next[0:0]$9162 $1\sr_op__oe__ok$next[0:0]$9153 assign $2\sr_op__rc__ok$next[0:0]$9163 $1\sr_op__rc__ok$next[0:0]$9156 assign $2\sr_op__rc__rc$next[0:0]$9164 $1\sr_op__rc__rc$next[0:0]$9157 end sync always update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9125 update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9126 update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9127 update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9128 update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9129 update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9130 update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9131 update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9132 update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9133 update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9134 update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9135 update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9136 update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9137 update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9138 update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9139 update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9140 update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9141 end attribute \src "libresoc.v:167890.3-167908.6" process $proc$libresoc.v:167890$9165 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$next[63:0]$9166 $1\o$next[63:0]$9168 assign { } { } assign $0\o_ok$next[0:0]$9167 $2\o_ok$next[0:0]$9170 attribute \src "libresoc.v:167891.5-167891.29" switch \initial attribute \src "libresoc.v:167891.9-167891.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9169 $1\o$next[63:0]$9168 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9169 $1\o$next[63:0]$9168 } { \o_ok$86 \o$85 } case assign $1\o$next[63:0]$9168 \o assign $1\o_ok$next[0:0]$9169 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$9170 1'0 case assign $2\o_ok$next[0:0]$9170 $1\o_ok$next[0:0]$9169 end sync always update \o$next $0\o$next[63:0]$9166 update \o_ok$next $0\o_ok$next[0:0]$9167 end attribute \src "libresoc.v:167909.3-167927.6" process $proc$libresoc.v:167909$9171 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$next[3:0]$9172 $1\cr_a$next[3:0]$9174 assign { } { } assign $0\cr_a_ok$next[0:0]$9173 $2\cr_a_ok$next[0:0]$9176 attribute \src "libresoc.v:167910.5-167910.29" switch \initial attribute \src "libresoc.v:167910.9-167910.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$9175 $1\cr_a$next[3:0]$9174 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$9175 $1\cr_a$next[3:0]$9174 } { \cr_a_ok$88 \cr_a$87 } case assign $1\cr_a$next[3:0]$9174 \cr_a assign $1\cr_a_ok$next[0:0]$9175 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$next[0:0]$9176 1'0 case assign $2\cr_a_ok$next[0:0]$9176 $1\cr_a_ok$next[0:0]$9175 end sync always update \cr_a$next $0\cr_a$next[3:0]$9172 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9173 end attribute \src "libresoc.v:167928.3-167946.6" process $proc$libresoc.v:167928$9177 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_so$next[0:0]$9178 $1\xer_so$next[0:0]$9180 assign { } { } assign $0\xer_so_ok$next[0:0]$9179 $2\xer_so_ok$next[0:0]$9182 attribute \src "libresoc.v:167929.5-167929.29" switch \initial attribute \src "libresoc.v:167929.9-167929.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$next[0:0]$9180 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$next[0:0]$9180 } { \xer_so_ok$92 \xer_so$91 } case assign $1\xer_so$next[0:0]$9180 \xer_so assign $1\xer_so_ok$next[0:0]$9181 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so_ok$next[0:0]$9182 1'0 case assign $2\xer_so_ok$next[0:0]$9182 $1\xer_so_ok$next[0:0]$9181 end sync always update \xer_so$next $0\xer_so$next[0:0]$9178 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9179 end connect \$65 $and$libresoc.v:167642$9083_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 connect \xer_ca_ok$96 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } connect { \cr_a_ok$88 \cr_a$87 } 5'00000 connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } connect \muxid$67 \main_muxid$44 connect \p_valid_i_p_ready_o \$65 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$64 \p_valid_i connect \xer_ca$63 \input_xer_ca$43 connect \main_xer_so \input_xer_so$42 connect \main_rc \input_rc$41 connect \main_rb \input_rb$40 connect \main_ra \input_ra$39 connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } connect \main_muxid \input_muxid$21 connect \input_xer_ca \xer_ca$20 connect \input_xer_so \xer_so$19 connect \input_rc \rc connect \input_rb \rb connect \input_ra \ra connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end attribute \src "libresoc.v:167980.1-168828.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 attribute \src "libresoc.v:168785.3-168797.6" wire width 64 $0\fast1$next[63:0]$9260 attribute \src "libresoc.v:168641.3-168642.27" wire width 64 $0\fast1[63:0] attribute \src "libresoc.v:168798.3-168810.6" wire width 64 $0\fast2$next[63:0]$9263 attribute \src "libresoc.v:168639.3-168640.27" wire width 64 $0\fast2[63:0] attribute \src "libresoc.v:167981.7-167981.20" wire $0\initial[0:0] attribute \src "libresoc.v:168725.3-168737.6" wire width 2 $0\muxid$next[1:0]$9232 attribute \src "libresoc.v:168665.3-168666.27" wire width 2 $0\muxid[1:0] attribute \src "libresoc.v:168707.3-168724.6" wire $0\r_busy$next[0:0]$9228 attribute \src "libresoc.v:168667.3-168668.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:168759.3-168771.6" wire width 64 $0\ra$next[63:0]$9254 attribute \src "libresoc.v:168645.3-168646.21" wire width 64 $0\ra[63:0] attribute \src "libresoc.v:168772.3-168784.6" wire width 64 $0\rb$next[63:0]$9257 attribute \src "libresoc.v:168643.3-168644.21" wire width 64 $0\rb[63:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $0\trap_op__cia$next[63:0]$9235 attribute \src "libresoc.v:168655.3-168656.41" wire width 64 $0\trap_op__cia[63:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 14 $0\trap_op__fn_unit$next[13:0]$9236 attribute \src "libresoc.v:168649.3-168650.49" wire width 14 $0\trap_op__fn_unit[13:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 32 $0\trap_op__insn$next[31:0]$9237 attribute \src "libresoc.v:168651.3-168652.43" wire width 32 $0\trap_op__insn[31:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 7 $0\trap_op__insn_type$next[6:0]$9238 attribute \src "libresoc.v:168647.3-168648.53" wire width 7 $0\trap_op__insn_type[6:0] attribute \src "libresoc.v:168738.3-168758.6" wire $0\trap_op__is_32bit$next[0:0]$9239 attribute \src "libresoc.v:168657.3-168658.51" wire $0\trap_op__is_32bit[0:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $0\trap_op__ldst_exc$next[7:0]$9240 attribute \src "libresoc.v:168663.3-168664.51" wire width 8 $0\trap_op__ldst_exc[7:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $0\trap_op__msr$next[63:0]$9241 attribute \src "libresoc.v:168653.3-168654.41" wire width 64 $0\trap_op__msr[63:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 13 $0\trap_op__trapaddr$next[12:0]$9242 attribute \src "libresoc.v:168661.3-168662.51" wire width 13 $0\trap_op__trapaddr[12:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $0\trap_op__traptype$next[7:0]$9243 attribute \src "libresoc.v:168659.3-168660.51" wire width 8 $0\trap_op__traptype[7:0] attribute \src "libresoc.v:168785.3-168797.6" wire width 64 $1\fast1$next[63:0]$9261 attribute \src "libresoc.v:168226.14-168226.42" wire width 64 $1\fast1[63:0] attribute \src "libresoc.v:168798.3-168810.6" wire width 64 $1\fast2$next[63:0]$9264 attribute \src "libresoc.v:168235.14-168235.42" wire width 64 $1\fast2[63:0] attribute \src "libresoc.v:168725.3-168737.6" wire width 2 $1\muxid$next[1:0]$9233 attribute \src "libresoc.v:168244.13-168244.25" wire width 2 $1\muxid[1:0] attribute \src "libresoc.v:168707.3-168724.6" wire $1\r_busy$next[0:0]$9229 attribute \src "libresoc.v:168266.7-168266.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:168759.3-168771.6" wire width 64 $1\ra$next[63:0]$9255 attribute \src "libresoc.v:168271.14-168271.39" wire width 64 $1\ra[63:0] attribute \src "libresoc.v:168772.3-168784.6" wire width 64 $1\rb$next[63:0]$9258 attribute \src "libresoc.v:168280.14-168280.39" wire width 64 $1\rb[63:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $1\trap_op__cia$next[63:0]$9244 attribute \src "libresoc.v:168289.14-168289.49" wire width 64 $1\trap_op__cia[63:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 14 $1\trap_op__fn_unit$next[13:0]$9245 attribute \src "libresoc.v:168313.14-168313.41" wire width 14 $1\trap_op__fn_unit[13:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 32 $1\trap_op__insn$next[31:0]$9246 attribute \src "libresoc.v:168352.14-168352.35" wire width 32 $1\trap_op__insn[31:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 7 $1\trap_op__insn_type$next[6:0]$9247 attribute \src "libresoc.v:168436.13-168436.39" wire width 7 $1\trap_op__insn_type[6:0] attribute \src "libresoc.v:168738.3-168758.6" wire $1\trap_op__is_32bit$next[0:0]$9248 attribute \src "libresoc.v:168595.7-168595.31" wire $1\trap_op__is_32bit[0:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $1\trap_op__ldst_exc$next[7:0]$9249 attribute \src "libresoc.v:168604.13-168604.38" wire width 8 $1\trap_op__ldst_exc[7:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 64 $1\trap_op__msr$next[63:0]$9250 attribute \src "libresoc.v:168613.14-168613.49" wire width 64 $1\trap_op__msr[63:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 13 $1\trap_op__trapaddr$next[12:0]$9251 attribute \src "libresoc.v:168622.14-168622.42" wire width 13 $1\trap_op__trapaddr[12:0] attribute \src "libresoc.v:168738.3-168758.6" wire width 8 $1\trap_op__traptype$next[7:0]$9252 attribute \src "libresoc.v:168631.13-168631.38" wire width 8 $1\trap_op__traptype[7:0] attribute \src "libresoc.v:168707.3-168724.6" wire $2\r_busy$next[0:0]$9230 attribute \src "libresoc.v:168638.18-168638.118" wire $and$libresoc.v:168638$9211_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 34 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast2$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \dummy_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \dummy_muxid$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_ra$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_rb$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dummy_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dummy_trap_op__cia$20 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dummy_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \dummy_trap_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dummy_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \dummy_trap_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dummy_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \dummy_trap_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dummy_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \dummy_trap_op__is_32bit$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \dummy_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \dummy_trap_op__ldst_exc$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dummy_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \dummy_trap_op__msr$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \dummy_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \dummy_trap_op__trapaddr$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \dummy_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \dummy_trap_op__traptype$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 16 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 32 \fast1$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast1$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 17 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 33 \fast2$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next attribute \src "libresoc.v:167981.7-167981.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 20 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 19 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 18 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 14 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 30 \ra$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 15 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 31 \rb$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 9 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 25 \trap_op__cia$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 6 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 22 \trap_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \trap_op__fn_unit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \trap_op__insn$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 23 \trap_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \trap_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 21 \trap_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \trap_op__is_32bit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \trap_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__ldst_exc$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__ldst_exc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__msr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 output 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \trap_op__trapaddr$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \trap_op__trapaddr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 27 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:168638$9211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o connect \Y $and$libresoc.v:168638$9211_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:168669.9-168698.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 connect \fast2 \dummy_fast2 connect \fast2$14 \dummy_fast2$28 connect \muxid \dummy_muxid connect \muxid$1 \dummy_muxid$15 connect \ra \dummy_ra connect \ra$11 \dummy_ra$25 connect \rb \dummy_rb connect \rb$12 \dummy_rb$26 connect \trap_op__cia \dummy_trap_op__cia connect \trap_op__cia$6 \dummy_trap_op__cia$20 connect \trap_op__fn_unit \dummy_trap_op__fn_unit connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 connect \trap_op__insn \dummy_trap_op__insn connect \trap_op__insn$4 \dummy_trap_op__insn$18 connect \trap_op__insn_type \dummy_trap_op__insn_type connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 connect \trap_op__is_32bit \dummy_trap_op__is_32bit connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 connect \trap_op__msr \dummy_trap_op__msr connect \trap_op__msr$5 \dummy_trap_op__msr$19 connect \trap_op__trapaddr \dummy_trap_op__trapaddr connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 connect \trap_op__traptype \dummy_trap_op__traptype connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 attribute \src "libresoc.v:168699.10-168702.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:168703.10-168706.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:167981.7-167981.20" process $proc$libresoc.v:167981$9265 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:168226.14-168226.42" process $proc$libresoc.v:168226$9266 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end attribute \src "libresoc.v:168235.14-168235.42" process $proc$libresoc.v:168235$9267 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end attribute \src "libresoc.v:168244.13-168244.25" process $proc$libresoc.v:168244$9268 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end attribute \src "libresoc.v:168266.7-168266.20" process $proc$libresoc.v:168266$9269 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:168271.14-168271.39" process $proc$libresoc.v:168271$9270 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end attribute \src "libresoc.v:168280.14-168280.39" process $proc$libresoc.v:168280$9271 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end attribute \src "libresoc.v:168289.14-168289.49" process $proc$libresoc.v:168289$9272 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end attribute \src "libresoc.v:168313.14-168313.41" process $proc$libresoc.v:168313$9273 assign { } { } assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end attribute \src "libresoc.v:168352.14-168352.35" process $proc$libresoc.v:168352$9274 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end attribute \src "libresoc.v:168436.13-168436.39" process $proc$libresoc.v:168436$9275 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end attribute \src "libresoc.v:168595.7-168595.31" process $proc$libresoc.v:168595$9276 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end attribute \src "libresoc.v:168604.13-168604.38" process $proc$libresoc.v:168604$9277 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end attribute \src "libresoc.v:168613.14-168613.49" process $proc$libresoc.v:168613$9278 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end attribute \src "libresoc.v:168622.14-168622.42" process $proc$libresoc.v:168622$9279 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end attribute \src "libresoc.v:168631.13-168631.38" process $proc$libresoc.v:168631$9280 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end attribute \src "libresoc.v:168639.3-168640.27" process $proc$libresoc.v:168639$9212 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end attribute \src "libresoc.v:168641.3-168642.27" process $proc$libresoc.v:168641$9213 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end attribute \src "libresoc.v:168643.3-168644.21" process $proc$libresoc.v:168643$9214 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end attribute \src "libresoc.v:168645.3-168646.21" process $proc$libresoc.v:168645$9215 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end attribute \src "libresoc.v:168647.3-168648.53" process $proc$libresoc.v:168647$9216 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end attribute \src "libresoc.v:168649.3-168650.49" process $proc$libresoc.v:168649$9217 assign { } { } assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end attribute \src "libresoc.v:168651.3-168652.43" process $proc$libresoc.v:168651$9218 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end attribute \src "libresoc.v:168653.3-168654.41" process $proc$libresoc.v:168653$9219 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end attribute \src "libresoc.v:168655.3-168656.41" process $proc$libresoc.v:168655$9220 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end attribute \src "libresoc.v:168657.3-168658.51" process $proc$libresoc.v:168657$9221 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end attribute \src "libresoc.v:168659.3-168660.51" process $proc$libresoc.v:168659$9222 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end attribute \src "libresoc.v:168661.3-168662.51" process $proc$libresoc.v:168661$9223 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end attribute \src "libresoc.v:168663.3-168664.51" process $proc$libresoc.v:168663$9224 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end attribute \src "libresoc.v:168665.3-168666.27" process $proc$libresoc.v:168665$9225 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end attribute \src "libresoc.v:168667.3-168668.29" process $proc$libresoc.v:168667$9226 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:168707.3-168724.6" process $proc$libresoc.v:168707$9227 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9228 $2\r_busy$next[0:0]$9230 attribute \src "libresoc.v:168708.5-168708.29" switch \initial attribute \src "libresoc.v:168708.9-168708.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$9229 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$9229 1'0 case assign $1\r_busy$next[0:0]$9229 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$9230 1'0 case assign $2\r_busy$next[0:0]$9230 $1\r_busy$next[0:0]$9229 end sync always update \r_busy$next $0\r_busy$next[0:0]$9228 end attribute \src "libresoc.v:168725.3-168737.6" process $proc$libresoc.v:168725$9231 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9232 $1\muxid$next[1:0]$9233 attribute \src "libresoc.v:168726.5-168726.29" switch \initial attribute \src "libresoc.v:168726.9-168726.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$next[1:0]$9233 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$next[1:0]$9233 \muxid$32 case assign $1\muxid$next[1:0]$9233 \muxid end sync always update \muxid$next $0\muxid$next[1:0]$9232 end attribute \src "libresoc.v:168738.3-168758.6" process $proc$libresoc.v:168738$9234 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\trap_op__cia$next[63:0]$9235 $1\trap_op__cia$next[63:0]$9244 assign $0\trap_op__fn_unit$next[13:0]$9236 $1\trap_op__fn_unit$next[13:0]$9245 assign $0\trap_op__insn$next[31:0]$9237 $1\trap_op__insn$next[31:0]$9246 assign $0\trap_op__insn_type$next[6:0]$9238 $1\trap_op__insn_type$next[6:0]$9247 assign $0\trap_op__is_32bit$next[0:0]$9239 $1\trap_op__is_32bit$next[0:0]$9248 assign $0\trap_op__ldst_exc$next[7:0]$9240 $1\trap_op__ldst_exc$next[7:0]$9249 assign $0\trap_op__msr$next[63:0]$9241 $1\trap_op__msr$next[63:0]$9250 assign $0\trap_op__trapaddr$next[12:0]$9242 $1\trap_op__trapaddr$next[12:0]$9251 assign $0\trap_op__traptype$next[7:0]$9243 $1\trap_op__traptype$next[7:0]$9252 attribute \src "libresoc.v:168739.5-168739.29" switch \initial attribute \src "libresoc.v:168739.9-168739.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\trap_op__ldst_exc$next[7:0]$9249 $1\trap_op__trapaddr$next[12:0]$9251 $1\trap_op__traptype$next[7:0]$9252 $1\trap_op__is_32bit$next[0:0]$9248 $1\trap_op__cia$next[63:0]$9244 $1\trap_op__msr$next[63:0]$9250 $1\trap_op__insn$next[31:0]$9246 $1\trap_op__fn_unit$next[13:0]$9245 $1\trap_op__insn_type$next[6:0]$9247 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\trap_op__ldst_exc$next[7:0]$9249 $1\trap_op__trapaddr$next[12:0]$9251 $1\trap_op__traptype$next[7:0]$9252 $1\trap_op__is_32bit$next[0:0]$9248 $1\trap_op__cia$next[63:0]$9244 $1\trap_op__msr$next[63:0]$9250 $1\trap_op__insn$next[31:0]$9246 $1\trap_op__fn_unit$next[13:0]$9245 $1\trap_op__insn_type$next[6:0]$9247 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case assign $1\trap_op__cia$next[63:0]$9244 \trap_op__cia assign $1\trap_op__fn_unit$next[13:0]$9245 \trap_op__fn_unit assign $1\trap_op__insn$next[31:0]$9246 \trap_op__insn assign $1\trap_op__insn_type$next[6:0]$9247 \trap_op__insn_type assign $1\trap_op__is_32bit$next[0:0]$9248 \trap_op__is_32bit assign $1\trap_op__ldst_exc$next[7:0]$9249 \trap_op__ldst_exc assign $1\trap_op__msr$next[63:0]$9250 \trap_op__msr assign $1\trap_op__trapaddr$next[12:0]$9251 \trap_op__trapaddr assign $1\trap_op__traptype$next[7:0]$9252 \trap_op__traptype end sync always update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9235 update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9236 update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9237 update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9238 update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9239 update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9240 update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9241 update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9242 update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9243 end attribute \src "libresoc.v:168759.3-168771.6" process $proc$libresoc.v:168759$9253 assign { } { } assign { } { } assign $0\ra$next[63:0]$9254 $1\ra$next[63:0]$9255 attribute \src "libresoc.v:168760.5-168760.29" switch \initial attribute \src "libresoc.v:168760.9-168760.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\ra$next[63:0]$9255 \ra$42 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\ra$next[63:0]$9255 \ra$42 case assign $1\ra$next[63:0]$9255 \ra end sync always update \ra$next $0\ra$next[63:0]$9254 end attribute \src "libresoc.v:168772.3-168784.6" process $proc$libresoc.v:168772$9256 assign { } { } assign { } { } assign $0\rb$next[63:0]$9257 $1\rb$next[63:0]$9258 attribute \src "libresoc.v:168773.5-168773.29" switch \initial attribute \src "libresoc.v:168773.9-168773.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\rb$next[63:0]$9258 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\rb$next[63:0]$9258 \rb$43 case assign $1\rb$next[63:0]$9258 \rb end sync always update \rb$next $0\rb$next[63:0]$9257 end attribute \src "libresoc.v:168785.3-168797.6" process $proc$libresoc.v:168785$9259 assign { } { } assign { } { } assign $0\fast1$next[63:0]$9260 $1\fast1$next[63:0]$9261 attribute \src "libresoc.v:168786.5-168786.29" switch \initial attribute \src "libresoc.v:168786.9-168786.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\fast1$next[63:0]$9261 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\fast1$next[63:0]$9261 \fast1$44 case assign $1\fast1$next[63:0]$9261 \fast1 end sync always update \fast1$next $0\fast1$next[63:0]$9260 end attribute \src "libresoc.v:168798.3-168810.6" process $proc$libresoc.v:168798$9262 assign { } { } assign { } { } assign $0\fast2$next[63:0]$9263 $1\fast2$next[63:0]$9264 attribute \src "libresoc.v:168799.5-168799.29" switch \initial attribute \src "libresoc.v:168799.9-168799.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\fast2$next[63:0]$9264 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\fast2$next[63:0]$9264 \fast2$45 case assign $1\fast2$next[63:0]$9264 \fast2 end sync always update \fast2$next $0\fast2$next[63:0]$9263 end connect \$30 $and$libresoc.v:168638$9211_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 connect \fast1$44 \dummy_fast1$27 connect \rb$43 \dummy_rb$26 connect \ra$42 \dummy_ra$25 connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } connect \muxid$32 \dummy_muxid$15 connect \p_valid_i_p_ready_o \$30 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$29 \p_valid_i connect \dummy_fast2 \fast2$14 connect \dummy_fast1 \fast1$13 connect \dummy_rb \rb$12 connect \dummy_ra \ra$11 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end attribute \src "libresoc.v:168832.1-170017.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 attribute \src "libresoc.v:169861.3-169902.6" wire width 4 $0\alu_op__data_len$18$next[3:0]$9349 attribute \src "libresoc.v:169758.3-169759.57" wire width 4 $0\alu_op__data_len$18[3:0]$9335 attribute \src "libresoc.v:168840.13-168840.41" wire width 4 $0\alu_op__data_len$18[3:0]$9423 attribute \src "libresoc.v:169861.3-169902.6" wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9350 attribute \src "libresoc.v:169728.3-169729.53" wire width 14 $0\alu_op__fn_unit$3[13:0]$9305 attribute \src "libresoc.v:168879.14-168879.44" wire width 14 $0\alu_op__fn_unit$3[13:0]$9425 attribute \src "libresoc.v:169861.3-169902.6" wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9351 attribute \src "libresoc.v:169730.3-169731.67" wire width 64 $0\alu_op__imm_data__data$4[63:0]$9307 attribute \src "libresoc.v:168903.14-168903.63" wire width 64 $0\alu_op__imm_data__data$4[63:0]$9427 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__imm_data__ok$5$next[0:0]$9352 attribute \src "libresoc.v:169732.3-169733.63" wire $0\alu_op__imm_data__ok$5[0:0]$9309 attribute \src "libresoc.v:168912.7-168912.38" wire $0\alu_op__imm_data__ok$5[0:0]$9429 attribute \src "libresoc.v:169861.3-169902.6" wire width 2 $0\alu_op__input_carry$14$next[1:0]$9353 attribute \src "libresoc.v:169750.3-169751.63" wire width 2 $0\alu_op__input_carry$14[1:0]$9327 attribute \src "libresoc.v:168929.13-168929.44" wire width 2 $0\alu_op__input_carry$14[1:0]$9431 attribute \src "libresoc.v:169861.3-169902.6" wire width 32 $0\alu_op__insn$19$next[31:0]$9354 attribute \src "libresoc.v:169760.3-169761.49" wire width 32 $0\alu_op__insn$19[31:0]$9337 attribute \src "libresoc.v:168942.14-168942.39" wire width 32 $0\alu_op__insn$19[31:0]$9433 attribute \src "libresoc.v:169861.3-169902.6" wire width 7 $0\alu_op__insn_type$2$next[6:0]$9355 attribute \src "libresoc.v:169726.3-169727.57" wire width 7 $0\alu_op__insn_type$2[6:0]$9303 attribute \src "libresoc.v:169101.13-169101.42" wire width 7 $0\alu_op__insn_type$2[6:0]$9435 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__invert_in$10$next[0:0]$9356 attribute \src "libresoc.v:169742.3-169743.59" wire $0\alu_op__invert_in$10[0:0]$9319 attribute \src "libresoc.v:169185.7-169185.36" wire $0\alu_op__invert_in$10[0:0]$9437 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__invert_out$12$next[0:0]$9357 attribute \src "libresoc.v:169746.3-169747.61" wire $0\alu_op__invert_out$12[0:0]$9323 attribute \src "libresoc.v:169194.7-169194.37" wire $0\alu_op__invert_out$12[0:0]$9439 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__is_32bit$16$next[0:0]$9358 attribute \src "libresoc.v:169754.3-169755.57" wire $0\alu_op__is_32bit$16[0:0]$9331 attribute \src "libresoc.v:169203.7-169203.35" wire $0\alu_op__is_32bit$16[0:0]$9441 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__is_signed$17$next[0:0]$9359 attribute \src "libresoc.v:169756.3-169757.59" wire $0\alu_op__is_signed$17[0:0]$9333 attribute \src "libresoc.v:169212.7-169212.36" wire $0\alu_op__is_signed$17[0:0]$9443 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__oe__oe$8$next[0:0]$9360 attribute \src "libresoc.v:169738.3-169739.51" wire $0\alu_op__oe__oe$8[0:0]$9315 attribute \src "libresoc.v:169223.7-169223.32" wire $0\alu_op__oe__oe$8[0:0]$9445 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__oe__ok$9$next[0:0]$9361 attribute \src "libresoc.v:169740.3-169741.51" wire $0\alu_op__oe__ok$9[0:0]$9317 attribute \src "libresoc.v:169232.7-169232.32" wire $0\alu_op__oe__ok$9[0:0]$9447 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__output_carry$15$next[0:0]$9362 attribute \src "libresoc.v:169752.3-169753.65" wire $0\alu_op__output_carry$15[0:0]$9329 attribute \src "libresoc.v:169239.7-169239.39" wire $0\alu_op__output_carry$15[0:0]$9449 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__rc__ok$7$next[0:0]$9363 attribute \src "libresoc.v:169736.3-169737.51" wire $0\alu_op__rc__ok$7[0:0]$9313 attribute \src "libresoc.v:169250.7-169250.32" wire $0\alu_op__rc__ok$7[0:0]$9451 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__rc__rc$6$next[0:0]$9364 attribute \src "libresoc.v:169734.3-169735.51" wire $0\alu_op__rc__rc$6[0:0]$9311 attribute \src "libresoc.v:169257.7-169257.32" wire $0\alu_op__rc__rc$6[0:0]$9453 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__write_cr0$13$next[0:0]$9365 attribute \src "libresoc.v:169748.3-169749.59" wire $0\alu_op__write_cr0$13[0:0]$9325 attribute \src "libresoc.v:169266.7-169266.36" wire $0\alu_op__write_cr0$13[0:0]$9455 attribute \src "libresoc.v:169861.3-169902.6" wire $0\alu_op__zero_a$11$next[0:0]$9366 attribute \src "libresoc.v:169744.3-169745.53" wire $0\alu_op__zero_a$11[0:0]$9321 attribute \src "libresoc.v:169275.7-169275.33" wire $0\alu_op__zero_a$11[0:0]$9457 attribute \src "libresoc.v:169922.3-169940.6" wire width 4 $0\cr_a$22$next[3:0]$9398 attribute \src "libresoc.v:169718.3-169719.33" wire width 4 $0\cr_a$22[3:0]$9295 attribute \src "libresoc.v:169288.13-169288.29" wire width 4 $0\cr_a$22[3:0]$9459 attribute \src "libresoc.v:169922.3-169940.6" wire $0\cr_a_ok$23$next[0:0]$9399 attribute \src "libresoc.v:169720.3-169721.39" wire $0\cr_a_ok$23[0:0]$9297 attribute \src "libresoc.v:169297.7-169297.26" wire $0\cr_a_ok$23[0:0]$9461 attribute \src "libresoc.v:168833.7-168833.20" wire $0\initial[0:0] attribute \src "libresoc.v:169848.3-169860.6" wire width 2 $0\muxid$1$next[1:0]$9346 attribute \src "libresoc.v:169762.3-169763.33" wire width 2 $0\muxid$1[1:0]$9339 attribute \src "libresoc.v:169308.13-169308.29" wire width 2 $0\muxid$1[1:0]$9463 attribute \src "libresoc.v:169903.3-169921.6" wire width 64 $0\o$20$next[63:0]$9392 attribute \src "libresoc.v:169722.3-169723.27" wire width 64 $0\o$20[63:0]$9299 attribute \src "libresoc.v:169323.14-169323.43" wire width 64 $0\o$20[63:0]$9465 attribute \src "libresoc.v:169903.3-169921.6" wire $0\o_ok$21$next[0:0]$9393 attribute \src "libresoc.v:169724.3-169725.33" wire $0\o_ok$21[0:0]$9301 attribute \src "libresoc.v:169332.7-169332.23" wire $0\o_ok$21[0:0]$9467 attribute \src "libresoc.v:169830.3-169847.6" wire $0\r_busy$next[0:0]$9342 attribute \src "libresoc.v:169764.3-169765.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:169941.3-169959.6" wire width 2 $0\xer_ca$24$next[1:0]$9404 attribute \src "libresoc.v:169714.3-169715.37" wire width 2 $0\xer_ca$24[1:0]$9291 attribute \src "libresoc.v:169649.13-169649.31" wire width 2 $0\xer_ca$24[1:0]$9470 attribute \src "libresoc.v:169941.3-169959.6" wire $0\xer_ca_ok$25$next[0:0]$9405 attribute \src "libresoc.v:169716.3-169717.43" wire $0\xer_ca_ok$25[0:0]$9293 attribute \src "libresoc.v:169658.7-169658.28" wire $0\xer_ca_ok$25[0:0]$9472 attribute \src "libresoc.v:169960.3-169978.6" wire width 2 $0\xer_ov$26$next[1:0]$9410 attribute \src "libresoc.v:169710.3-169711.37" wire width 2 $0\xer_ov$26[1:0]$9287 attribute \src "libresoc.v:169669.13-169669.31" wire width 2 $0\xer_ov$26[1:0]$9474 attribute \src "libresoc.v:169960.3-169978.6" wire $0\xer_ov_ok$27$next[0:0]$9411 attribute \src "libresoc.v:169712.3-169713.43" wire $0\xer_ov_ok$27[0:0]$9289 attribute \src "libresoc.v:169678.7-169678.28" wire $0\xer_ov_ok$27[0:0]$9476 attribute \src "libresoc.v:169979.3-169997.6" wire $0\xer_so$28$next[0:0]$9416 attribute \src "libresoc.v:169706.3-169707.37" wire $0\xer_so$28[0:0]$9283 attribute \src "libresoc.v:169689.7-169689.25" wire $0\xer_so$28[0:0]$9478 attribute \src "libresoc.v:169979.3-169997.6" wire $0\xer_so_ok$29$next[0:0]$9417 attribute \src "libresoc.v:169708.3-169709.43" wire $0\xer_so_ok$29[0:0]$9285 attribute \src "libresoc.v:169698.7-169698.28" wire $0\xer_so_ok$29[0:0]$9480 attribute \src "libresoc.v:169861.3-169902.6" wire width 4 $1\alu_op__data_len$18$next[3:0]$9367 attribute \src "libresoc.v:169861.3-169902.6" wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9368 attribute \src "libresoc.v:169861.3-169902.6" wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9369 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__imm_data__ok$5$next[0:0]$9370 attribute \src "libresoc.v:169861.3-169902.6" wire width 2 $1\alu_op__input_carry$14$next[1:0]$9371 attribute \src "libresoc.v:169861.3-169902.6" wire width 32 $1\alu_op__insn$19$next[31:0]$9372 attribute \src "libresoc.v:169861.3-169902.6" wire width 7 $1\alu_op__insn_type$2$next[6:0]$9373 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__invert_in$10$next[0:0]$9374 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__invert_out$12$next[0:0]$9375 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__is_32bit$16$next[0:0]$9376 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__is_signed$17$next[0:0]$9377 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__oe__oe$8$next[0:0]$9378 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__oe__ok$9$next[0:0]$9379 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__output_carry$15$next[0:0]$9380 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__rc__ok$7$next[0:0]$9381 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__rc__rc$6$next[0:0]$9382 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__write_cr0$13$next[0:0]$9383 attribute \src "libresoc.v:169861.3-169902.6" wire $1\alu_op__zero_a$11$next[0:0]$9384 attribute \src "libresoc.v:169922.3-169940.6" wire width 4 $1\cr_a$22$next[3:0]$9400 attribute \src "libresoc.v:169922.3-169940.6" wire $1\cr_a_ok$23$next[0:0]$9401 attribute \src "libresoc.v:169848.3-169860.6" wire width 2 $1\muxid$1$next[1:0]$9347 attribute \src "libresoc.v:169903.3-169921.6" wire width 64 $1\o$20$next[63:0]$9394 attribute \src "libresoc.v:169903.3-169921.6" wire $1\o_ok$21$next[0:0]$9395 attribute \src "libresoc.v:169830.3-169847.6" wire $1\r_busy$next[0:0]$9343 attribute \src "libresoc.v:169642.7-169642.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:169941.3-169959.6" wire width 2 $1\xer_ca$24$next[1:0]$9406 attribute \src "libresoc.v:169941.3-169959.6" wire $1\xer_ca_ok$25$next[0:0]$9407 attribute \src "libresoc.v:169960.3-169978.6" wire width 2 $1\xer_ov$26$next[1:0]$9412 attribute \src "libresoc.v:169960.3-169978.6" wire $1\xer_ov_ok$27$next[0:0]$9413 attribute \src "libresoc.v:169979.3-169997.6" wire $1\xer_so$28$next[0:0]$9418 attribute \src "libresoc.v:169979.3-169997.6" wire $1\xer_so_ok$29$next[0:0]$9419 attribute \src "libresoc.v:169861.3-169902.6" wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9385 attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__imm_data__ok$5$next[0:0]$9386 attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__oe__oe$8$next[0:0]$9387 attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__oe__ok$9$next[0:0]$9388 attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__rc__ok$7$next[0:0]$9389 attribute \src "libresoc.v:169861.3-169902.6" wire $2\alu_op__rc__rc$6$next[0:0]$9390 attribute \src "libresoc.v:169922.3-169940.6" wire $2\cr_a_ok$23$next[0:0]$9402 attribute \src "libresoc.v:169903.3-169921.6" wire $2\o_ok$21$next[0:0]$9396 attribute \src "libresoc.v:169830.3-169847.6" wire $2\r_busy$next[0:0]$9344 attribute \src "libresoc.v:169941.3-169959.6" wire $2\xer_ca_ok$25$next[0:0]$9408 attribute \src "libresoc.v:169960.3-169978.6" wire $2\xer_ov_ok$27$next[0:0]$9414 attribute \src "libresoc.v:169979.3-169997.6" wire $2\xer_so_ok$29$next[0:0]$9420 attribute \src "libresoc.v:169705.18-169705.118" wire $and$libresoc.v:169705$9281_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 52 \alu_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_op__data_len$79 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 37 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_op__fn_unit$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 38 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_op__imm_data__data$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \alu_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__imm_data__ok$66 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 17 \alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 48 \alu_op__input_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_op__input_carry$14$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_op__input_carry$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 22 \alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 53 \alu_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_op__insn$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_op__insn$80 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 36 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_op__insn_type$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 44 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_in$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_in$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 46 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_out$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__invert_out$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 50 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_32bit$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 51 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__is_signed$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__oe$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 42 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__ok$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 43 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 49 \alu_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__output_carry$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__output_carry$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__ok$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 41 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__rc__rc$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 47 \alu_op__write_cr0$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__write_cr0$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__write_cr0$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 45 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 64 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 56 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$22$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 57 \cr_a_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$23$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$84 attribute \src "libresoc.v:168833.7-168833.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 35 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 34 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 33 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 23 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 54 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$20$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 24 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 55 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$21$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_alu_op__data_len$47 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_alu_op__fn_unit$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_alu_op__imm_data__data$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__imm_data__ok$34 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_alu_op__input_carry$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_alu_op__insn$48 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_alu_op__insn_type$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__invert_in$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__invert_out$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__is_32bit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__is_signed$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__oe__oe$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__oe__ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__output_carry$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__rc__ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__rc__rc$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__write_cr0$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_alu_op__zero_a$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 27 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 58 \xer_ca$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$24$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 28 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 59 \xer_ca_ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$25$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 29 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 60 \xer_ov$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$26$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 30 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 61 \xer_ov_ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$27$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 31 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 62 \xer_so$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$28$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 32 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 63 \xer_so_ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$29$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:169705$9281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o connect \Y $and$libresoc.v:169705$9281_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:169766.9-169769.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:169770.12-169825.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 connect \alu_op__fn_unit \output_alu_op__fn_unit connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 connect \alu_op__imm_data__data \output_alu_op__imm_data__data connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 connect \alu_op__input_carry \output_alu_op__input_carry connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 connect \alu_op__insn \output_alu_op__insn connect \alu_op__insn$19 \output_alu_op__insn$48 connect \alu_op__insn_type \output_alu_op__insn_type connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 connect \alu_op__invert_in \output_alu_op__invert_in connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 connect \alu_op__invert_out \output_alu_op__invert_out connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 connect \alu_op__is_32bit \output_alu_op__is_32bit connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 connect \alu_op__is_signed \output_alu_op__is_signed connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 connect \alu_op__oe__oe \output_alu_op__oe__oe connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 connect \alu_op__oe__ok \output_alu_op__oe__ok connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 connect \alu_op__output_carry \output_alu_op__output_carry connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 connect \alu_op__rc__ok \output_alu_op__rc__ok connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 connect \alu_op__rc__rc \output_alu_op__rc__rc connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 connect \alu_op__write_cr0 \output_alu_op__write_cr0 connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 connect \alu_op__zero_a \output_alu_op__zero_a connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$51 connect \cr_a_ok \output_cr_a_ok connect \muxid \output_muxid connect \muxid$1 \output_muxid$30 connect \o \output_o connect \o$20 \output_o$49 connect \o_ok \output_o_ok connect \o_ok$21 \output_o_ok$50 connect \xer_ca \output_xer_ca connect \xer_ca$23 \output_xer_ca$52 connect \xer_ca_ok \output_xer_ca_ok connect \xer_ov \output_xer_ov connect \xer_ov$24 \output_xer_ov$53 connect \xer_ov_ok \output_xer_ov_ok connect \xer_so \output_xer_so connect \xer_so$25 \output_xer_so$54 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:169826.9-169829.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:168833.7-168833.20" process $proc$libresoc.v:168833$9421 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:168840.13-168840.41" process $proc$libresoc.v:168840$9422 assign { } { } assign $0\alu_op__data_len$18[3:0]$9423 4'0000 sync always sync init update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9423 end attribute \src "libresoc.v:168879.14-168879.44" process $proc$libresoc.v:168879$9424 assign { } { } assign $0\alu_op__fn_unit$3[13:0]$9425 14'00000000000000 sync always sync init update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9425 end attribute \src "libresoc.v:168903.14-168903.63" process $proc$libresoc.v:168903$9426 assign { } { } assign $0\alu_op__imm_data__data$4[63:0]$9427 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9427 end attribute \src "libresoc.v:168912.7-168912.38" process $proc$libresoc.v:168912$9428 assign { } { } assign $0\alu_op__imm_data__ok$5[0:0]$9429 1'0 sync always sync init update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9429 end attribute \src "libresoc.v:168929.13-168929.44" process $proc$libresoc.v:168929$9430 assign { } { } assign $0\alu_op__input_carry$14[1:0]$9431 2'00 sync always sync init update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9431 end attribute \src "libresoc.v:168942.14-168942.39" process $proc$libresoc.v:168942$9432 assign { } { } assign $0\alu_op__insn$19[31:0]$9433 0 sync always sync init update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9433 end attribute \src "libresoc.v:169101.13-169101.42" process $proc$libresoc.v:169101$9434 assign { } { } assign $0\alu_op__insn_type$2[6:0]$9435 7'0000000 sync always sync init update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9435 end attribute \src "libresoc.v:169185.7-169185.36" process $proc$libresoc.v:169185$9436 assign { } { } assign $0\alu_op__invert_in$10[0:0]$9437 1'0 sync always sync init update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9437 end attribute \src "libresoc.v:169194.7-169194.37" process $proc$libresoc.v:169194$9438 assign { } { } assign $0\alu_op__invert_out$12[0:0]$9439 1'0 sync always sync init update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9439 end attribute \src "libresoc.v:169203.7-169203.35" process $proc$libresoc.v:169203$9440 assign { } { } assign $0\alu_op__is_32bit$16[0:0]$9441 1'0 sync always sync init update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9441 end attribute \src "libresoc.v:169212.7-169212.36" process $proc$libresoc.v:169212$9442 assign { } { } assign $0\alu_op__is_signed$17[0:0]$9443 1'0 sync always sync init update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9443 end attribute \src "libresoc.v:169223.7-169223.32" process $proc$libresoc.v:169223$9444 assign { } { } assign $0\alu_op__oe__oe$8[0:0]$9445 1'0 sync always sync init update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9445 end attribute \src "libresoc.v:169232.7-169232.32" process $proc$libresoc.v:169232$9446 assign { } { } assign $0\alu_op__oe__ok$9[0:0]$9447 1'0 sync always sync init update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9447 end attribute \src "libresoc.v:169239.7-169239.39" process $proc$libresoc.v:169239$9448 assign { } { } assign $0\alu_op__output_carry$15[0:0]$9449 1'0 sync always sync init update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9449 end attribute \src "libresoc.v:169250.7-169250.32" process $proc$libresoc.v:169250$9450 assign { } { } assign $0\alu_op__rc__ok$7[0:0]$9451 1'0 sync always sync init update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9451 end attribute \src "libresoc.v:169257.7-169257.32" process $proc$libresoc.v:169257$9452 assign { } { } assign $0\alu_op__rc__rc$6[0:0]$9453 1'0 sync always sync init update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9453 end attribute \src "libresoc.v:169266.7-169266.36" process $proc$libresoc.v:169266$9454 assign { } { } assign $0\alu_op__write_cr0$13[0:0]$9455 1'0 sync always sync init update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9455 end attribute \src "libresoc.v:169275.7-169275.33" process $proc$libresoc.v:169275$9456 assign { } { } assign $0\alu_op__zero_a$11[0:0]$9457 1'0 sync always sync init update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9457 end attribute \src "libresoc.v:169288.13-169288.29" process $proc$libresoc.v:169288$9458 assign { } { } assign $0\cr_a$22[3:0]$9459 4'0000 sync always sync init update \cr_a$22 $0\cr_a$22[3:0]$9459 end attribute \src "libresoc.v:169297.7-169297.26" process $proc$libresoc.v:169297$9460 assign { } { } assign $0\cr_a_ok$23[0:0]$9461 1'0 sync always sync init update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9461 end attribute \src "libresoc.v:169308.13-169308.29" process $proc$libresoc.v:169308$9462 assign { } { } assign $0\muxid$1[1:0]$9463 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9463 end attribute \src "libresoc.v:169323.14-169323.43" process $proc$libresoc.v:169323$9464 assign { } { } assign $0\o$20[63:0]$9465 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$20 $0\o$20[63:0]$9465 end attribute \src "libresoc.v:169332.7-169332.23" process $proc$libresoc.v:169332$9466 assign { } { } assign $0\o_ok$21[0:0]$9467 1'0 sync always sync init update \o_ok$21 $0\o_ok$21[0:0]$9467 end attribute \src "libresoc.v:169642.7-169642.20" process $proc$libresoc.v:169642$9468 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:169649.13-169649.31" process $proc$libresoc.v:169649$9469 assign { } { } assign $0\xer_ca$24[1:0]$9470 2'00 sync always sync init update \xer_ca$24 $0\xer_ca$24[1:0]$9470 end attribute \src "libresoc.v:169658.7-169658.28" process $proc$libresoc.v:169658$9471 assign { } { } assign $0\xer_ca_ok$25[0:0]$9472 1'0 sync always sync init update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9472 end attribute \src "libresoc.v:169669.13-169669.31" process $proc$libresoc.v:169669$9473 assign { } { } assign $0\xer_ov$26[1:0]$9474 2'00 sync always sync init update \xer_ov$26 $0\xer_ov$26[1:0]$9474 end attribute \src "libresoc.v:169678.7-169678.28" process $proc$libresoc.v:169678$9475 assign { } { } assign $0\xer_ov_ok$27[0:0]$9476 1'0 sync always sync init update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9476 end attribute \src "libresoc.v:169689.7-169689.25" process $proc$libresoc.v:169689$9477 assign { } { } assign $0\xer_so$28[0:0]$9478 1'0 sync always sync init update \xer_so$28 $0\xer_so$28[0:0]$9478 end attribute \src "libresoc.v:169698.7-169698.28" process $proc$libresoc.v:169698$9479 assign { } { } assign $0\xer_so_ok$29[0:0]$9480 1'0 sync always sync init update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9480 end attribute \src "libresoc.v:169706.3-169707.37" process $proc$libresoc.v:169706$9282 assign { } { } assign $0\xer_so$28[0:0]$9283 \xer_so$28$next sync posedge \coresync_clk update \xer_so$28 $0\xer_so$28[0:0]$9283 end attribute \src "libresoc.v:169708.3-169709.43" process $proc$libresoc.v:169708$9284 assign { } { } assign $0\xer_so_ok$29[0:0]$9285 \xer_so_ok$29$next sync posedge \coresync_clk update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9285 end attribute \src "libresoc.v:169710.3-169711.37" process $proc$libresoc.v:169710$9286 assign { } { } assign $0\xer_ov$26[1:0]$9287 \xer_ov$26$next sync posedge \coresync_clk update \xer_ov$26 $0\xer_ov$26[1:0]$9287 end attribute \src "libresoc.v:169712.3-169713.43" process $proc$libresoc.v:169712$9288 assign { } { } assign $0\xer_ov_ok$27[0:0]$9289 \xer_ov_ok$27$next sync posedge \coresync_clk update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9289 end attribute \src "libresoc.v:169714.3-169715.37" process $proc$libresoc.v:169714$9290 assign { } { } assign $0\xer_ca$24[1:0]$9291 \xer_ca$24$next sync posedge \coresync_clk update \xer_ca$24 $0\xer_ca$24[1:0]$9291 end attribute \src "libresoc.v:169716.3-169717.43" process $proc$libresoc.v:169716$9292 assign { } { } assign $0\xer_ca_ok$25[0:0]$9293 \xer_ca_ok$25$next sync posedge \coresync_clk update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9293 end attribute \src "libresoc.v:169718.3-169719.33" process $proc$libresoc.v:169718$9294 assign { } { } assign $0\cr_a$22[3:0]$9295 \cr_a$22$next sync posedge \coresync_clk update \cr_a$22 $0\cr_a$22[3:0]$9295 end attribute \src "libresoc.v:169720.3-169721.39" process $proc$libresoc.v:169720$9296 assign { } { } assign $0\cr_a_ok$23[0:0]$9297 \cr_a_ok$23$next sync posedge \coresync_clk update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9297 end attribute \src "libresoc.v:169722.3-169723.27" process $proc$libresoc.v:169722$9298 assign { } { } assign $0\o$20[63:0]$9299 \o$20$next sync posedge \coresync_clk update \o$20 $0\o$20[63:0]$9299 end attribute \src "libresoc.v:169724.3-169725.33" process $proc$libresoc.v:169724$9300 assign { } { } assign $0\o_ok$21[0:0]$9301 \o_ok$21$next sync posedge \coresync_clk update \o_ok$21 $0\o_ok$21[0:0]$9301 end attribute \src "libresoc.v:169726.3-169727.57" process $proc$libresoc.v:169726$9302 assign { } { } assign $0\alu_op__insn_type$2[6:0]$9303 \alu_op__insn_type$2$next sync posedge \coresync_clk update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9303 end attribute \src "libresoc.v:169728.3-169729.53" process $proc$libresoc.v:169728$9304 assign { } { } assign $0\alu_op__fn_unit$3[13:0]$9305 \alu_op__fn_unit$3$next sync posedge \coresync_clk update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9305 end attribute \src "libresoc.v:169730.3-169731.67" process $proc$libresoc.v:169730$9306 assign { } { } assign $0\alu_op__imm_data__data$4[63:0]$9307 \alu_op__imm_data__data$4$next sync posedge \coresync_clk update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9307 end attribute \src "libresoc.v:169732.3-169733.63" process $proc$libresoc.v:169732$9308 assign { } { } assign $0\alu_op__imm_data__ok$5[0:0]$9309 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9309 end attribute \src "libresoc.v:169734.3-169735.51" process $proc$libresoc.v:169734$9310 assign { } { } assign $0\alu_op__rc__rc$6[0:0]$9311 \alu_op__rc__rc$6$next sync posedge \coresync_clk update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9311 end attribute \src "libresoc.v:169736.3-169737.51" process $proc$libresoc.v:169736$9312 assign { } { } assign $0\alu_op__rc__ok$7[0:0]$9313 \alu_op__rc__ok$7$next sync posedge \coresync_clk update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9313 end attribute \src "libresoc.v:169738.3-169739.51" process $proc$libresoc.v:169738$9314 assign { } { } assign $0\alu_op__oe__oe$8[0:0]$9315 \alu_op__oe__oe$8$next sync posedge \coresync_clk update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9315 end attribute \src "libresoc.v:169740.3-169741.51" process $proc$libresoc.v:169740$9316 assign { } { } assign $0\alu_op__oe__ok$9[0:0]$9317 \alu_op__oe__ok$9$next sync posedge \coresync_clk update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9317 end attribute \src "libresoc.v:169742.3-169743.59" process $proc$libresoc.v:169742$9318 assign { } { } assign $0\alu_op__invert_in$10[0:0]$9319 \alu_op__invert_in$10$next sync posedge \coresync_clk update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9319 end attribute \src "libresoc.v:169744.3-169745.53" process $proc$libresoc.v:169744$9320 assign { } { } assign $0\alu_op__zero_a$11[0:0]$9321 \alu_op__zero_a$11$next sync posedge \coresync_clk update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9321 end attribute \src "libresoc.v:169746.3-169747.61" process $proc$libresoc.v:169746$9322 assign { } { } assign $0\alu_op__invert_out$12[0:0]$9323 \alu_op__invert_out$12$next sync posedge \coresync_clk update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9323 end attribute \src "libresoc.v:169748.3-169749.59" process $proc$libresoc.v:169748$9324 assign { } { } assign $0\alu_op__write_cr0$13[0:0]$9325 \alu_op__write_cr0$13$next sync posedge \coresync_clk update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9325 end attribute \src "libresoc.v:169750.3-169751.63" process $proc$libresoc.v:169750$9326 assign { } { } assign $0\alu_op__input_carry$14[1:0]$9327 \alu_op__input_carry$14$next sync posedge \coresync_clk update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9327 end attribute \src "libresoc.v:169752.3-169753.65" process $proc$libresoc.v:169752$9328 assign { } { } assign $0\alu_op__output_carry$15[0:0]$9329 \alu_op__output_carry$15$next sync posedge \coresync_clk update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9329 end attribute \src "libresoc.v:169754.3-169755.57" process $proc$libresoc.v:169754$9330 assign { } { } assign $0\alu_op__is_32bit$16[0:0]$9331 \alu_op__is_32bit$16$next sync posedge \coresync_clk update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9331 end attribute \src "libresoc.v:169756.3-169757.59" process $proc$libresoc.v:169756$9332 assign { } { } assign $0\alu_op__is_signed$17[0:0]$9333 \alu_op__is_signed$17$next sync posedge \coresync_clk update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9333 end attribute \src "libresoc.v:169758.3-169759.57" process $proc$libresoc.v:169758$9334 assign { } { } assign $0\alu_op__data_len$18[3:0]$9335 \alu_op__data_len$18$next sync posedge \coresync_clk update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9335 end attribute \src "libresoc.v:169760.3-169761.49" process $proc$libresoc.v:169760$9336 assign { } { } assign $0\alu_op__insn$19[31:0]$9337 \alu_op__insn$19$next sync posedge \coresync_clk update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9337 end attribute \src "libresoc.v:169762.3-169763.33" process $proc$libresoc.v:169762$9338 assign { } { } assign $0\muxid$1[1:0]$9339 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9339 end attribute \src "libresoc.v:169764.3-169765.29" process $proc$libresoc.v:169764$9340 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:169830.3-169847.6" process $proc$libresoc.v:169830$9341 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9342 $2\r_busy$next[0:0]$9344 attribute \src "libresoc.v:169831.5-169831.29" switch \initial attribute \src "libresoc.v:169831.9-169831.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$9343 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$9343 1'0 case assign $1\r_busy$next[0:0]$9343 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$9344 1'0 case assign $2\r_busy$next[0:0]$9344 $1\r_busy$next[0:0]$9343 end sync always update \r_busy$next $0\r_busy$next[0:0]$9342 end attribute \src "libresoc.v:169848.3-169860.6" process $proc$libresoc.v:169848$9345 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9346 $1\muxid$1$next[1:0]$9347 attribute \src "libresoc.v:169849.5-169849.29" switch \initial attribute \src "libresoc.v:169849.9-169849.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$9347 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$9347 \muxid$62 case assign $1\muxid$1$next[1:0]$9347 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$9346 end attribute \src "libresoc.v:169861.3-169902.6" process $proc$libresoc.v:169861$9348 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_op__data_len$18$next[3:0]$9349 $1\alu_op__data_len$18$next[3:0]$9367 assign $0\alu_op__fn_unit$3$next[13:0]$9350 $1\alu_op__fn_unit$3$next[13:0]$9368 assign { } { } assign { } { } assign $0\alu_op__input_carry$14$next[1:0]$9353 $1\alu_op__input_carry$14$next[1:0]$9371 assign $0\alu_op__insn$19$next[31:0]$9354 $1\alu_op__insn$19$next[31:0]$9372 assign $0\alu_op__insn_type$2$next[6:0]$9355 $1\alu_op__insn_type$2$next[6:0]$9373 assign $0\alu_op__invert_in$10$next[0:0]$9356 $1\alu_op__invert_in$10$next[0:0]$9374 assign $0\alu_op__invert_out$12$next[0:0]$9357 $1\alu_op__invert_out$12$next[0:0]$9375 assign $0\alu_op__is_32bit$16$next[0:0]$9358 $1\alu_op__is_32bit$16$next[0:0]$9376 assign $0\alu_op__is_signed$17$next[0:0]$9359 $1\alu_op__is_signed$17$next[0:0]$9377 assign { } { } assign { } { } assign $0\alu_op__output_carry$15$next[0:0]$9362 $1\alu_op__output_carry$15$next[0:0]$9380 assign { } { } assign { } { } assign $0\alu_op__write_cr0$13$next[0:0]$9365 $1\alu_op__write_cr0$13$next[0:0]$9383 assign $0\alu_op__zero_a$11$next[0:0]$9366 $1\alu_op__zero_a$11$next[0:0]$9384 assign $0\alu_op__imm_data__data$4$next[63:0]$9351 $2\alu_op__imm_data__data$4$next[63:0]$9385 assign $0\alu_op__imm_data__ok$5$next[0:0]$9352 $2\alu_op__imm_data__ok$5$next[0:0]$9386 assign $0\alu_op__oe__oe$8$next[0:0]$9360 $2\alu_op__oe__oe$8$next[0:0]$9387 assign $0\alu_op__oe__ok$9$next[0:0]$9361 $2\alu_op__oe__ok$9$next[0:0]$9388 assign $0\alu_op__rc__ok$7$next[0:0]$9363 $2\alu_op__rc__ok$7$next[0:0]$9389 assign $0\alu_op__rc__rc$6$next[0:0]$9364 $2\alu_op__rc__rc$6$next[0:0]$9390 attribute \src "libresoc.v:169862.5-169862.29" switch \initial attribute \src "libresoc.v:169862.9-169862.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_op__insn$19$next[31:0]$9372 $1\alu_op__data_len$18$next[3:0]$9367 $1\alu_op__is_signed$17$next[0:0]$9377 $1\alu_op__is_32bit$16$next[0:0]$9376 $1\alu_op__output_carry$15$next[0:0]$9380 $1\alu_op__input_carry$14$next[1:0]$9371 $1\alu_op__write_cr0$13$next[0:0]$9383 $1\alu_op__invert_out$12$next[0:0]$9375 $1\alu_op__zero_a$11$next[0:0]$9384 $1\alu_op__invert_in$10$next[0:0]$9374 $1\alu_op__oe__ok$9$next[0:0]$9379 $1\alu_op__oe__oe$8$next[0:0]$9378 $1\alu_op__rc__ok$7$next[0:0]$9381 $1\alu_op__rc__rc$6$next[0:0]$9382 $1\alu_op__imm_data__ok$5$next[0:0]$9370 $1\alu_op__imm_data__data$4$next[63:0]$9369 $1\alu_op__fn_unit$3$next[13:0]$9368 $1\alu_op__insn_type$2$next[6:0]$9373 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_op__insn$19$next[31:0]$9372 $1\alu_op__data_len$18$next[3:0]$9367 $1\alu_op__is_signed$17$next[0:0]$9377 $1\alu_op__is_32bit$16$next[0:0]$9376 $1\alu_op__output_carry$15$next[0:0]$9380 $1\alu_op__input_carry$14$next[1:0]$9371 $1\alu_op__write_cr0$13$next[0:0]$9383 $1\alu_op__invert_out$12$next[0:0]$9375 $1\alu_op__zero_a$11$next[0:0]$9384 $1\alu_op__invert_in$10$next[0:0]$9374 $1\alu_op__oe__ok$9$next[0:0]$9379 $1\alu_op__oe__oe$8$next[0:0]$9378 $1\alu_op__rc__ok$7$next[0:0]$9381 $1\alu_op__rc__rc$6$next[0:0]$9382 $1\alu_op__imm_data__ok$5$next[0:0]$9370 $1\alu_op__imm_data__data$4$next[63:0]$9369 $1\alu_op__fn_unit$3$next[13:0]$9368 $1\alu_op__insn_type$2$next[6:0]$9373 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } case assign $1\alu_op__data_len$18$next[3:0]$9367 \alu_op__data_len$18 assign $1\alu_op__fn_unit$3$next[13:0]$9368 \alu_op__fn_unit$3 assign $1\alu_op__imm_data__data$4$next[63:0]$9369 \alu_op__imm_data__data$4 assign $1\alu_op__imm_data__ok$5$next[0:0]$9370 \alu_op__imm_data__ok$5 assign $1\alu_op__input_carry$14$next[1:0]$9371 \alu_op__input_carry$14 assign $1\alu_op__insn$19$next[31:0]$9372 \alu_op__insn$19 assign $1\alu_op__insn_type$2$next[6:0]$9373 \alu_op__insn_type$2 assign $1\alu_op__invert_in$10$next[0:0]$9374 \alu_op__invert_in$10 assign $1\alu_op__invert_out$12$next[0:0]$9375 \alu_op__invert_out$12 assign $1\alu_op__is_32bit$16$next[0:0]$9376 \alu_op__is_32bit$16 assign $1\alu_op__is_signed$17$next[0:0]$9377 \alu_op__is_signed$17 assign $1\alu_op__oe__oe$8$next[0:0]$9378 \alu_op__oe__oe$8 assign $1\alu_op__oe__ok$9$next[0:0]$9379 \alu_op__oe__ok$9 assign $1\alu_op__output_carry$15$next[0:0]$9380 \alu_op__output_carry$15 assign $1\alu_op__rc__ok$7$next[0:0]$9381 \alu_op__rc__ok$7 assign $1\alu_op__rc__rc$6$next[0:0]$9382 \alu_op__rc__rc$6 assign $1\alu_op__write_cr0$13$next[0:0]$9383 \alu_op__write_cr0$13 assign $1\alu_op__zero_a$11$next[0:0]$9384 \alu_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\alu_op__imm_data__data$4$next[63:0]$9385 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_op__imm_data__ok$5$next[0:0]$9386 1'0 assign $2\alu_op__rc__rc$6$next[0:0]$9390 1'0 assign $2\alu_op__rc__ok$7$next[0:0]$9389 1'0 assign $2\alu_op__oe__oe$8$next[0:0]$9387 1'0 assign $2\alu_op__oe__ok$9$next[0:0]$9388 1'0 case assign $2\alu_op__imm_data__data$4$next[63:0]$9385 $1\alu_op__imm_data__data$4$next[63:0]$9369 assign $2\alu_op__imm_data__ok$5$next[0:0]$9386 $1\alu_op__imm_data__ok$5$next[0:0]$9370 assign $2\alu_op__oe__oe$8$next[0:0]$9387 $1\alu_op__oe__oe$8$next[0:0]$9378 assign $2\alu_op__oe__ok$9$next[0:0]$9388 $1\alu_op__oe__ok$9$next[0:0]$9379 assign $2\alu_op__rc__ok$7$next[0:0]$9389 $1\alu_op__rc__ok$7$next[0:0]$9381 assign $2\alu_op__rc__rc$6$next[0:0]$9390 $1\alu_op__rc__rc$6$next[0:0]$9382 end sync always update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9349 update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9350 update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9351 update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9352 update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9353 update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9354 update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9355 update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9356 update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9357 update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9358 update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9359 update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9360 update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9361 update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9362 update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9363 update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9364 update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9365 update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9366 end attribute \src "libresoc.v:169903.3-169921.6" process $proc$libresoc.v:169903$9391 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$20$next[63:0]$9392 $1\o$20$next[63:0]$9394 assign { } { } assign $0\o_ok$21$next[0:0]$9393 $2\o_ok$21$next[0:0]$9396 attribute \src "libresoc.v:169904.5-169904.29" switch \initial attribute \src "libresoc.v:169904.9-169904.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$21$next[0:0]$9395 $1\o$20$next[63:0]$9394 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$21$next[0:0]$9395 $1\o$20$next[63:0]$9394 } { \o_ok$82 \o$81 } case assign $1\o$20$next[63:0]$9394 \o$20 assign $1\o_ok$21$next[0:0]$9395 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$21$next[0:0]$9396 1'0 case assign $2\o_ok$21$next[0:0]$9396 $1\o_ok$21$next[0:0]$9395 end sync always update \o$20$next $0\o$20$next[63:0]$9392 update \o_ok$21$next $0\o_ok$21$next[0:0]$9393 end attribute \src "libresoc.v:169922.3-169940.6" process $proc$libresoc.v:169922$9397 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$22$next[3:0]$9398 $1\cr_a$22$next[3:0]$9400 assign { } { } assign $0\cr_a_ok$23$next[0:0]$9399 $2\cr_a_ok$23$next[0:0]$9402 attribute \src "libresoc.v:169923.5-169923.29" switch \initial attribute \src "libresoc.v:169923.9-169923.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$23$next[0:0]$9401 $1\cr_a$22$next[3:0]$9400 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$23$next[0:0]$9401 $1\cr_a$22$next[3:0]$9400 } { \cr_a_ok$84 \cr_a$83 } case assign $1\cr_a$22$next[3:0]$9400 \cr_a$22 assign $1\cr_a_ok$23$next[0:0]$9401 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$23$next[0:0]$9402 1'0 case assign $2\cr_a_ok$23$next[0:0]$9402 $1\cr_a_ok$23$next[0:0]$9401 end sync always update \cr_a$22$next $0\cr_a$22$next[3:0]$9398 update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9399 end attribute \src "libresoc.v:169941.3-169959.6" process $proc$libresoc.v:169941$9403 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ca$24$next[1:0]$9404 $1\xer_ca$24$next[1:0]$9406 assign { } { } assign $0\xer_ca_ok$25$next[0:0]$9405 $2\xer_ca_ok$25$next[0:0]$9408 attribute \src "libresoc.v:169942.5-169942.29" switch \initial attribute \src "libresoc.v:169942.9-169942.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ca_ok$25$next[0:0]$9407 $1\xer_ca$24$next[1:0]$9406 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ca_ok$25$next[0:0]$9407 $1\xer_ca$24$next[1:0]$9406 } { \xer_ca_ok$86 \xer_ca$85 } case assign $1\xer_ca$24$next[1:0]$9406 \xer_ca$24 assign $1\xer_ca_ok$25$next[0:0]$9407 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ca_ok$25$next[0:0]$9408 1'0 case assign $2\xer_ca_ok$25$next[0:0]$9408 $1\xer_ca_ok$25$next[0:0]$9407 end sync always update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9404 update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9405 end attribute \src "libresoc.v:169960.3-169978.6" process $proc$libresoc.v:169960$9409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ov$26$next[1:0]$9410 $1\xer_ov$26$next[1:0]$9412 assign { } { } assign $0\xer_ov_ok$27$next[0:0]$9411 $2\xer_ov_ok$27$next[0:0]$9414 attribute \src "libresoc.v:169961.5-169961.29" switch \initial attribute \src "libresoc.v:169961.9-169961.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ov_ok$27$next[0:0]$9413 $1\xer_ov$26$next[1:0]$9412 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ov_ok$27$next[0:0]$9413 $1\xer_ov$26$next[1:0]$9412 } { \xer_ov_ok$88 \xer_ov$87 } case assign $1\xer_ov$26$next[1:0]$9412 \xer_ov$26 assign $1\xer_ov_ok$27$next[0:0]$9413 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ov_ok$27$next[0:0]$9414 1'0 case assign $2\xer_ov_ok$27$next[0:0]$9414 $1\xer_ov_ok$27$next[0:0]$9413 end sync always update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9410 update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9411 end attribute \src "libresoc.v:169979.3-169997.6" process $proc$libresoc.v:169979$9415 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_so$28$next[0:0]$9416 $1\xer_so$28$next[0:0]$9418 assign { } { } assign $0\xer_so_ok$29$next[0:0]$9417 $2\xer_so_ok$29$next[0:0]$9420 attribute \src "libresoc.v:169980.5-169980.29" switch \initial attribute \src "libresoc.v:169980.9-169980.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_so_ok$29$next[0:0]$9419 $1\xer_so$28$next[0:0]$9418 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_so_ok$29$next[0:0]$9419 $1\xer_so$28$next[0:0]$9418 } { \xer_so_ok$90 \xer_so$89 } case assign $1\xer_so$28$next[0:0]$9418 \xer_so$28 assign $1\xer_so_ok$29$next[0:0]$9419 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so_ok$29$next[0:0]$9420 1'0 case assign $2\xer_so_ok$29$next[0:0]$9420 $1\xer_so_ok$29$next[0:0]$9419 end sync always update \xer_so$28$next $0\xer_so$28$next[0:0]$9416 update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9417 end connect \$60 $and$libresoc.v:169705$9281_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } connect \muxid$62 \output_muxid$30 connect \p_valid_i_p_ready_o \$60 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$59 \p_valid_i connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } connect { \output_o_ok \output_o } { \o_ok \o } connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end attribute \src "libresoc.v:170021.1-171090.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 attribute \src "libresoc.v:171036.3-171054.6" wire width 4 $0\cr_a$21$next[3:0]$9586 attribute \src "libresoc.v:170842.3-170843.33" wire width 4 $0\cr_a$21[3:0]$9487 attribute \src "libresoc.v:170033.13-170033.29" wire width 4 $0\cr_a$21[3:0]$9599 attribute \src "libresoc.v:171036.3-171054.6" wire $0\cr_a_ok$22$next[0:0]$9587 attribute \src "libresoc.v:170844.3-170845.39" wire $0\cr_a_ok$22[0:0]$9489 attribute \src "libresoc.v:170042.7-170042.26" wire $0\cr_a_ok$22[0:0]$9601 attribute \src "libresoc.v:170022.7-170022.20" wire $0\initial[0:0] attribute \src "libresoc.v:170963.3-170975.6" wire width 2 $0\muxid$1$next[1:0]$9536 attribute \src "libresoc.v:170884.3-170885.33" wire width 2 $0\muxid$1[1:0]$9529 attribute \src "libresoc.v:170053.13-170053.29" wire width 2 $0\muxid$1[1:0]$9603 attribute \src "libresoc.v:171017.3-171035.6" wire width 64 $0\o$19$next[63:0]$9580 attribute \src "libresoc.v:170846.3-170847.27" wire width 64 $0\o$19[63:0]$9491 attribute \src "libresoc.v:170068.14-170068.43" wire width 64 $0\o$19[63:0]$9605 attribute \src "libresoc.v:171017.3-171035.6" wire $0\o_ok$20$next[0:0]$9581 attribute \src "libresoc.v:170848.3-170849.33" wire $0\o_ok$20[0:0]$9493 attribute \src "libresoc.v:170077.7-170077.23" wire $0\o_ok$20[0:0]$9607 attribute \src "libresoc.v:170945.3-170962.6" wire $0\r_busy$next[0:0]$9532 attribute \src "libresoc.v:170886.3-170887.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:170976.3-171016.6" wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9539 attribute \src "libresoc.v:170852.3-170853.51" wire width 14 $0\sr_op__fn_unit$3[13:0]$9497 attribute \src "libresoc.v:170410.14-170410.43" wire width 14 $0\sr_op__fn_unit$3[13:0]$9610 attribute \src "libresoc.v:170976.3-171016.6" wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9540 attribute \src "libresoc.v:170854.3-170855.65" wire width 64 $0\sr_op__imm_data__data$4[63:0]$9499 attribute \src "libresoc.v:170434.14-170434.62" wire width 64 $0\sr_op__imm_data__data$4[63:0]$9612 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__imm_data__ok$5$next[0:0]$9541 attribute \src "libresoc.v:170856.3-170857.61" wire $0\sr_op__imm_data__ok$5[0:0]$9501 attribute \src "libresoc.v:170443.7-170443.37" wire $0\sr_op__imm_data__ok$5[0:0]$9614 attribute \src "libresoc.v:170976.3-171016.6" wire width 2 $0\sr_op__input_carry$12$next[1:0]$9542 attribute \src "libresoc.v:170870.3-170871.61" wire width 2 $0\sr_op__input_carry$12[1:0]$9515 attribute \src "libresoc.v:170460.13-170460.43" wire width 2 $0\sr_op__input_carry$12[1:0]$9616 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__input_cr$14$next[0:0]$9543 attribute \src "libresoc.v:170874.3-170875.55" wire $0\sr_op__input_cr$14[0:0]$9519 attribute \src "libresoc.v:170473.7-170473.34" wire $0\sr_op__input_cr$14[0:0]$9618 attribute \src "libresoc.v:170976.3-171016.6" wire width 32 $0\sr_op__insn$18$next[31:0]$9544 attribute \src "libresoc.v:170882.3-170883.47" wire width 32 $0\sr_op__insn$18[31:0]$9527 attribute \src "libresoc.v:170482.14-170482.38" wire width 32 $0\sr_op__insn$18[31:0]$9620 attribute \src "libresoc.v:170976.3-171016.6" wire width 7 $0\sr_op__insn_type$2$next[6:0]$9545 attribute \src "libresoc.v:170850.3-170851.55" wire width 7 $0\sr_op__insn_type$2[6:0]$9495 attribute \src "libresoc.v:170641.13-170641.41" wire width 7 $0\sr_op__insn_type$2[6:0]$9622 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__invert_in$11$next[0:0]$9546 attribute \src "libresoc.v:170868.3-170869.57" wire $0\sr_op__invert_in$11[0:0]$9513 attribute \src "libresoc.v:170725.7-170725.35" wire $0\sr_op__invert_in$11[0:0]$9624 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__is_32bit$16$next[0:0]$9547 attribute \src "libresoc.v:170878.3-170879.55" wire $0\sr_op__is_32bit$16[0:0]$9523 attribute \src "libresoc.v:170734.7-170734.34" wire $0\sr_op__is_32bit$16[0:0]$9626 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__is_signed$17$next[0:0]$9548 attribute \src "libresoc.v:170880.3-170881.57" wire $0\sr_op__is_signed$17[0:0]$9525 attribute \src "libresoc.v:170743.7-170743.35" wire $0\sr_op__is_signed$17[0:0]$9628 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__oe__oe$8$next[0:0]$9549 attribute \src "libresoc.v:170862.3-170863.49" wire $0\sr_op__oe__oe$8[0:0]$9507 attribute \src "libresoc.v:170754.7-170754.31" wire $0\sr_op__oe__oe$8[0:0]$9630 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__oe__ok$9$next[0:0]$9550 attribute \src "libresoc.v:170864.3-170865.49" wire $0\sr_op__oe__ok$9[0:0]$9509 attribute \src "libresoc.v:170763.7-170763.31" wire $0\sr_op__oe__ok$9[0:0]$9632 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__output_carry$13$next[0:0]$9551 attribute \src "libresoc.v:170872.3-170873.63" wire $0\sr_op__output_carry$13[0:0]$9517 attribute \src "libresoc.v:170770.7-170770.38" wire $0\sr_op__output_carry$13[0:0]$9634 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__output_cr$15$next[0:0]$9552 attribute \src "libresoc.v:170876.3-170877.57" wire $0\sr_op__output_cr$15[0:0]$9521 attribute \src "libresoc.v:170779.7-170779.35" wire $0\sr_op__output_cr$15[0:0]$9636 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__rc__ok$7$next[0:0]$9553 attribute \src "libresoc.v:170860.3-170861.49" wire $0\sr_op__rc__ok$7[0:0]$9505 attribute \src "libresoc.v:170790.7-170790.31" wire $0\sr_op__rc__ok$7[0:0]$9638 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__rc__rc$6$next[0:0]$9554 attribute \src "libresoc.v:170858.3-170859.49" wire $0\sr_op__rc__rc$6[0:0]$9503 attribute \src "libresoc.v:170799.7-170799.31" wire $0\sr_op__rc__rc$6[0:0]$9640 attribute \src "libresoc.v:170976.3-171016.6" wire $0\sr_op__write_cr0$10$next[0:0]$9555 attribute \src "libresoc.v:170866.3-170867.57" wire $0\sr_op__write_cr0$10[0:0]$9511 attribute \src "libresoc.v:170806.7-170806.35" wire $0\sr_op__write_cr0$10[0:0]$9642 attribute \src "libresoc.v:171055.3-171073.6" wire width 2 $0\xer_ca$23$next[1:0]$9592 attribute \src "libresoc.v:170838.3-170839.37" wire width 2 $0\xer_ca$23[1:0]$9483 attribute \src "libresoc.v:170815.13-170815.31" wire width 2 $0\xer_ca$23[1:0]$9644 attribute \src "libresoc.v:171055.3-171073.6" wire $0\xer_ca_ok$24$next[0:0]$9593 attribute \src "libresoc.v:170840.3-170841.43" wire $0\xer_ca_ok$24[0:0]$9485 attribute \src "libresoc.v:170824.7-170824.28" wire $0\xer_ca_ok$24[0:0]$9646 attribute \src "libresoc.v:171036.3-171054.6" wire width 4 $1\cr_a$21$next[3:0]$9588 attribute \src "libresoc.v:171036.3-171054.6" wire $1\cr_a_ok$22$next[0:0]$9589 attribute \src "libresoc.v:170963.3-170975.6" wire width 2 $1\muxid$1$next[1:0]$9537 attribute \src "libresoc.v:171017.3-171035.6" wire width 64 $1\o$19$next[63:0]$9582 attribute \src "libresoc.v:171017.3-171035.6" wire $1\o_ok$20$next[0:0]$9583 attribute \src "libresoc.v:170945.3-170962.6" wire $1\r_busy$next[0:0]$9533 attribute \src "libresoc.v:170373.7-170373.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:170976.3-171016.6" wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9556 attribute \src "libresoc.v:170976.3-171016.6" wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9557 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__imm_data__ok$5$next[0:0]$9558 attribute \src "libresoc.v:170976.3-171016.6" wire width 2 $1\sr_op__input_carry$12$next[1:0]$9559 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__input_cr$14$next[0:0]$9560 attribute \src "libresoc.v:170976.3-171016.6" wire width 32 $1\sr_op__insn$18$next[31:0]$9561 attribute \src "libresoc.v:170976.3-171016.6" wire width 7 $1\sr_op__insn_type$2$next[6:0]$9562 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__invert_in$11$next[0:0]$9563 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__is_32bit$16$next[0:0]$9564 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__is_signed$17$next[0:0]$9565 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__oe__oe$8$next[0:0]$9566 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__oe__ok$9$next[0:0]$9567 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__output_carry$13$next[0:0]$9568 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__output_cr$15$next[0:0]$9569 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__rc__ok$7$next[0:0]$9570 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__rc__rc$6$next[0:0]$9571 attribute \src "libresoc.v:170976.3-171016.6" wire $1\sr_op__write_cr0$10$next[0:0]$9572 attribute \src "libresoc.v:171055.3-171073.6" wire width 2 $1\xer_ca$23$next[1:0]$9594 attribute \src "libresoc.v:171055.3-171073.6" wire $1\xer_ca_ok$24$next[0:0]$9595 attribute \src "libresoc.v:171036.3-171054.6" wire $2\cr_a_ok$22$next[0:0]$9590 attribute \src "libresoc.v:171017.3-171035.6" wire $2\o_ok$20$next[0:0]$9584 attribute \src "libresoc.v:170945.3-170962.6" wire $2\r_busy$next[0:0]$9534 attribute \src "libresoc.v:170976.3-171016.6" wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9573 attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__imm_data__ok$5$next[0:0]$9574 attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__oe__oe$8$next[0:0]$9575 attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__oe__ok$9$next[0:0]$9576 attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__rc__ok$7$next[0:0]$9577 attribute \src "libresoc.v:170976.3-171016.6" wire $2\sr_op__rc__rc$6$next[0:0]$9578 attribute \src "libresoc.v:171055.3-171073.6" wire $2\xer_ca_ok$24$next[0:0]$9596 attribute \src "libresoc.v:170837.18-170837.118" wire $and$libresoc.v:170837$9481_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 56 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 input 24 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 52 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$21$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 53 \cr_a_ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$22$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$74 attribute \src "libresoc.v:170022.7-170022.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 32 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 31 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 30 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 50 \o$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 23 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 51 \o_ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$20$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_muxid$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$44 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \output_sr_op__fn_unit$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \output_sr_op__imm_data__data$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__imm_data__ok$29 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_sr_op__input_carry$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__input_cr$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_sr_op__insn$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_sr_op__insn_type$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__invert_in$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__is_32bit$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__is_signed$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__oe__oe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__oe__ok$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__output_carry$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__output_cr$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__rc__ok$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__rc__rc$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_sr_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ca$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 34 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \sr_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \sr_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 35 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \sr_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \sr_op__imm_data__data$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \sr_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__imm_data__ok$57 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 15 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 43 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \sr_op__input_carry$12$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \sr_op__input_carry$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 45 \sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__input_cr$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__input_cr$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 21 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 49 \sr_op__insn$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \sr_op__insn$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \sr_op__insn$70 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 33 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \sr_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__invert_in$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__invert_in$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 47 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 48 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__oe$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 44 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_carry$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_carry$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 46 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_cr$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__output_cr$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__rc$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 41 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \sr_op__write_cr0$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 input 28 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 54 \xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$23$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ca$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 29 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 55 \xer_ca_ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$24$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ca_ok$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 26 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 27 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:170837$9481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o connect \Y $and$libresoc.v:170837$9481_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:170888.11-170891.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:170892.16-170940.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 connect \cr_a_ok \output_cr_a_ok connect \muxid \output_muxid connect \muxid$1 \output_muxid$25 connect \o \output_o connect \o$19 \output_o$43 connect \o_ok \output_o_ok connect \o_ok$20 \output_o_ok$44 connect \sr_op__fn_unit \output_sr_op__fn_unit connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 connect \sr_op__imm_data__data \output_sr_op__imm_data__data connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 connect \sr_op__input_carry \output_sr_op__input_carry connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 connect \sr_op__input_cr \output_sr_op__input_cr connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 connect \sr_op__insn \output_sr_op__insn connect \sr_op__insn$18 \output_sr_op__insn$42 connect \sr_op__insn_type \output_sr_op__insn_type connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 connect \sr_op__invert_in \output_sr_op__invert_in connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 connect \sr_op__is_32bit \output_sr_op__is_32bit connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 connect \sr_op__is_signed \output_sr_op__is_signed connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 connect \sr_op__oe__oe \output_sr_op__oe__oe connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 connect \sr_op__oe__ok \output_sr_op__oe__ok connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 connect \sr_op__output_carry \output_sr_op__output_carry connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 connect \sr_op__output_cr \output_sr_op__output_cr connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 connect \sr_op__rc__ok \output_sr_op__rc__ok connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 connect \sr_op__rc__rc \output_sr_op__rc__rc connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 connect \sr_op__write_cr0 \output_sr_op__write_cr0 connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 connect \xer_ca \output_xer_ca connect \xer_ca$22 \output_xer_ca$46 connect \xer_ca_ok \output_xer_ca_ok connect \xer_so \output_xer_so end attribute \module_not_derived 1 attribute \src "libresoc.v:170941.11-170944.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:170022.7-170022.20" process $proc$libresoc.v:170022$9597 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:170033.13-170033.29" process $proc$libresoc.v:170033$9598 assign { } { } assign $0\cr_a$21[3:0]$9599 4'0000 sync always sync init update \cr_a$21 $0\cr_a$21[3:0]$9599 end attribute \src "libresoc.v:170042.7-170042.26" process $proc$libresoc.v:170042$9600 assign { } { } assign $0\cr_a_ok$22[0:0]$9601 1'0 sync always sync init update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9601 end attribute \src "libresoc.v:170053.13-170053.29" process $proc$libresoc.v:170053$9602 assign { } { } assign $0\muxid$1[1:0]$9603 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9603 end attribute \src "libresoc.v:170068.14-170068.43" process $proc$libresoc.v:170068$9604 assign { } { } assign $0\o$19[63:0]$9605 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$19 $0\o$19[63:0]$9605 end attribute \src "libresoc.v:170077.7-170077.23" process $proc$libresoc.v:170077$9606 assign { } { } assign $0\o_ok$20[0:0]$9607 1'0 sync always sync init update \o_ok$20 $0\o_ok$20[0:0]$9607 end attribute \src "libresoc.v:170373.7-170373.20" process $proc$libresoc.v:170373$9608 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:170410.14-170410.43" process $proc$libresoc.v:170410$9609 assign { } { } assign $0\sr_op__fn_unit$3[13:0]$9610 14'00000000000000 sync always sync init update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9610 end attribute \src "libresoc.v:170434.14-170434.62" process $proc$libresoc.v:170434$9611 assign { } { } assign $0\sr_op__imm_data__data$4[63:0]$9612 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9612 end attribute \src "libresoc.v:170443.7-170443.37" process $proc$libresoc.v:170443$9613 assign { } { } assign $0\sr_op__imm_data__ok$5[0:0]$9614 1'0 sync always sync init update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9614 end attribute \src "libresoc.v:170460.13-170460.43" process $proc$libresoc.v:170460$9615 assign { } { } assign $0\sr_op__input_carry$12[1:0]$9616 2'00 sync always sync init update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9616 end attribute \src "libresoc.v:170473.7-170473.34" process $proc$libresoc.v:170473$9617 assign { } { } assign $0\sr_op__input_cr$14[0:0]$9618 1'0 sync always sync init update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9618 end attribute \src "libresoc.v:170482.14-170482.38" process $proc$libresoc.v:170482$9619 assign { } { } assign $0\sr_op__insn$18[31:0]$9620 0 sync always sync init update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9620 end attribute \src "libresoc.v:170641.13-170641.41" process $proc$libresoc.v:170641$9621 assign { } { } assign $0\sr_op__insn_type$2[6:0]$9622 7'0000000 sync always sync init update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9622 end attribute \src "libresoc.v:170725.7-170725.35" process $proc$libresoc.v:170725$9623 assign { } { } assign $0\sr_op__invert_in$11[0:0]$9624 1'0 sync always sync init update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9624 end attribute \src "libresoc.v:170734.7-170734.34" process $proc$libresoc.v:170734$9625 assign { } { } assign $0\sr_op__is_32bit$16[0:0]$9626 1'0 sync always sync init update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9626 end attribute \src "libresoc.v:170743.7-170743.35" process $proc$libresoc.v:170743$9627 assign { } { } assign $0\sr_op__is_signed$17[0:0]$9628 1'0 sync always sync init update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9628 end attribute \src "libresoc.v:170754.7-170754.31" process $proc$libresoc.v:170754$9629 assign { } { } assign $0\sr_op__oe__oe$8[0:0]$9630 1'0 sync always sync init update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9630 end attribute \src "libresoc.v:170763.7-170763.31" process $proc$libresoc.v:170763$9631 assign { } { } assign $0\sr_op__oe__ok$9[0:0]$9632 1'0 sync always sync init update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9632 end attribute \src "libresoc.v:170770.7-170770.38" process $proc$libresoc.v:170770$9633 assign { } { } assign $0\sr_op__output_carry$13[0:0]$9634 1'0 sync always sync init update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9634 end attribute \src "libresoc.v:170779.7-170779.35" process $proc$libresoc.v:170779$9635 assign { } { } assign $0\sr_op__output_cr$15[0:0]$9636 1'0 sync always sync init update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9636 end attribute \src "libresoc.v:170790.7-170790.31" process $proc$libresoc.v:170790$9637 assign { } { } assign $0\sr_op__rc__ok$7[0:0]$9638 1'0 sync always sync init update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9638 end attribute \src "libresoc.v:170799.7-170799.31" process $proc$libresoc.v:170799$9639 assign { } { } assign $0\sr_op__rc__rc$6[0:0]$9640 1'0 sync always sync init update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9640 end attribute \src "libresoc.v:170806.7-170806.35" process $proc$libresoc.v:170806$9641 assign { } { } assign $0\sr_op__write_cr0$10[0:0]$9642 1'0 sync always sync init update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9642 end attribute \src "libresoc.v:170815.13-170815.31" process $proc$libresoc.v:170815$9643 assign { } { } assign $0\xer_ca$23[1:0]$9644 2'00 sync always sync init update \xer_ca$23 $0\xer_ca$23[1:0]$9644 end attribute \src "libresoc.v:170824.7-170824.28" process $proc$libresoc.v:170824$9645 assign { } { } assign $0\xer_ca_ok$24[0:0]$9646 1'0 sync always sync init update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9646 end attribute \src "libresoc.v:170838.3-170839.37" process $proc$libresoc.v:170838$9482 assign { } { } assign $0\xer_ca$23[1:0]$9483 \xer_ca$23$next sync posedge \coresync_clk update \xer_ca$23 $0\xer_ca$23[1:0]$9483 end attribute \src "libresoc.v:170840.3-170841.43" process $proc$libresoc.v:170840$9484 assign { } { } assign $0\xer_ca_ok$24[0:0]$9485 \xer_ca_ok$24$next sync posedge \coresync_clk update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9485 end attribute \src "libresoc.v:170842.3-170843.33" process $proc$libresoc.v:170842$9486 assign { } { } assign $0\cr_a$21[3:0]$9487 \cr_a$21$next sync posedge \coresync_clk update \cr_a$21 $0\cr_a$21[3:0]$9487 end attribute \src "libresoc.v:170844.3-170845.39" process $proc$libresoc.v:170844$9488 assign { } { } assign $0\cr_a_ok$22[0:0]$9489 \cr_a_ok$22$next sync posedge \coresync_clk update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9489 end attribute \src "libresoc.v:170846.3-170847.27" process $proc$libresoc.v:170846$9490 assign { } { } assign $0\o$19[63:0]$9491 \o$19$next sync posedge \coresync_clk update \o$19 $0\o$19[63:0]$9491 end attribute \src "libresoc.v:170848.3-170849.33" process $proc$libresoc.v:170848$9492 assign { } { } assign $0\o_ok$20[0:0]$9493 \o_ok$20$next sync posedge \coresync_clk update \o_ok$20 $0\o_ok$20[0:0]$9493 end attribute \src "libresoc.v:170850.3-170851.55" process $proc$libresoc.v:170850$9494 assign { } { } assign $0\sr_op__insn_type$2[6:0]$9495 \sr_op__insn_type$2$next sync posedge \coresync_clk update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9495 end attribute \src "libresoc.v:170852.3-170853.51" process $proc$libresoc.v:170852$9496 assign { } { } assign $0\sr_op__fn_unit$3[13:0]$9497 \sr_op__fn_unit$3$next sync posedge \coresync_clk update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9497 end attribute \src "libresoc.v:170854.3-170855.65" process $proc$libresoc.v:170854$9498 assign { } { } assign $0\sr_op__imm_data__data$4[63:0]$9499 \sr_op__imm_data__data$4$next sync posedge \coresync_clk update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9499 end attribute \src "libresoc.v:170856.3-170857.61" process $proc$libresoc.v:170856$9500 assign { } { } assign $0\sr_op__imm_data__ok$5[0:0]$9501 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9501 end attribute \src "libresoc.v:170858.3-170859.49" process $proc$libresoc.v:170858$9502 assign { } { } assign $0\sr_op__rc__rc$6[0:0]$9503 \sr_op__rc__rc$6$next sync posedge \coresync_clk update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9503 end attribute \src "libresoc.v:170860.3-170861.49" process $proc$libresoc.v:170860$9504 assign { } { } assign $0\sr_op__rc__ok$7[0:0]$9505 \sr_op__rc__ok$7$next sync posedge \coresync_clk update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9505 end attribute \src "libresoc.v:170862.3-170863.49" process $proc$libresoc.v:170862$9506 assign { } { } assign $0\sr_op__oe__oe$8[0:0]$9507 \sr_op__oe__oe$8$next sync posedge \coresync_clk update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9507 end attribute \src "libresoc.v:170864.3-170865.49" process $proc$libresoc.v:170864$9508 assign { } { } assign $0\sr_op__oe__ok$9[0:0]$9509 \sr_op__oe__ok$9$next sync posedge \coresync_clk update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9509 end attribute \src "libresoc.v:170866.3-170867.57" process $proc$libresoc.v:170866$9510 assign { } { } assign $0\sr_op__write_cr0$10[0:0]$9511 \sr_op__write_cr0$10$next sync posedge \coresync_clk update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9511 end attribute \src "libresoc.v:170868.3-170869.57" process $proc$libresoc.v:170868$9512 assign { } { } assign $0\sr_op__invert_in$11[0:0]$9513 \sr_op__invert_in$11$next sync posedge \coresync_clk update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9513 end attribute \src "libresoc.v:170870.3-170871.61" process $proc$libresoc.v:170870$9514 assign { } { } assign $0\sr_op__input_carry$12[1:0]$9515 \sr_op__input_carry$12$next sync posedge \coresync_clk update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9515 end attribute \src "libresoc.v:170872.3-170873.63" process $proc$libresoc.v:170872$9516 assign { } { } assign $0\sr_op__output_carry$13[0:0]$9517 \sr_op__output_carry$13$next sync posedge \coresync_clk update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9517 end attribute \src "libresoc.v:170874.3-170875.55" process $proc$libresoc.v:170874$9518 assign { } { } assign $0\sr_op__input_cr$14[0:0]$9519 \sr_op__input_cr$14$next sync posedge \coresync_clk update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9519 end attribute \src "libresoc.v:170876.3-170877.57" process $proc$libresoc.v:170876$9520 assign { } { } assign $0\sr_op__output_cr$15[0:0]$9521 \sr_op__output_cr$15$next sync posedge \coresync_clk update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9521 end attribute \src "libresoc.v:170878.3-170879.55" process $proc$libresoc.v:170878$9522 assign { } { } assign $0\sr_op__is_32bit$16[0:0]$9523 \sr_op__is_32bit$16$next sync posedge \coresync_clk update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9523 end attribute \src "libresoc.v:170880.3-170881.57" process $proc$libresoc.v:170880$9524 assign { } { } assign $0\sr_op__is_signed$17[0:0]$9525 \sr_op__is_signed$17$next sync posedge \coresync_clk update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9525 end attribute \src "libresoc.v:170882.3-170883.47" process $proc$libresoc.v:170882$9526 assign { } { } assign $0\sr_op__insn$18[31:0]$9527 \sr_op__insn$18$next sync posedge \coresync_clk update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9527 end attribute \src "libresoc.v:170884.3-170885.33" process $proc$libresoc.v:170884$9528 assign { } { } assign $0\muxid$1[1:0]$9529 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9529 end attribute \src "libresoc.v:170886.3-170887.29" process $proc$libresoc.v:170886$9530 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:170945.3-170962.6" process $proc$libresoc.v:170945$9531 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9532 $2\r_busy$next[0:0]$9534 attribute \src "libresoc.v:170946.5-170946.29" switch \initial attribute \src "libresoc.v:170946.9-170946.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$9533 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$9533 1'0 case assign $1\r_busy$next[0:0]$9533 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$9534 1'0 case assign $2\r_busy$next[0:0]$9534 $1\r_busy$next[0:0]$9533 end sync always update \r_busy$next $0\r_busy$next[0:0]$9532 end attribute \src "libresoc.v:170963.3-170975.6" process $proc$libresoc.v:170963$9535 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9536 $1\muxid$1$next[1:0]$9537 attribute \src "libresoc.v:170964.5-170964.29" switch \initial attribute \src "libresoc.v:170964.9-170964.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$9537 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$9537 \muxid$53 case assign $1\muxid$1$next[1:0]$9537 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$9536 end attribute \src "libresoc.v:170976.3-171016.6" process $proc$libresoc.v:170976$9538 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr_op__fn_unit$3$next[13:0]$9539 $1\sr_op__fn_unit$3$next[13:0]$9556 assign { } { } assign { } { } assign $0\sr_op__input_carry$12$next[1:0]$9542 $1\sr_op__input_carry$12$next[1:0]$9559 assign $0\sr_op__input_cr$14$next[0:0]$9543 $1\sr_op__input_cr$14$next[0:0]$9560 assign $0\sr_op__insn$18$next[31:0]$9544 $1\sr_op__insn$18$next[31:0]$9561 assign $0\sr_op__insn_type$2$next[6:0]$9545 $1\sr_op__insn_type$2$next[6:0]$9562 assign $0\sr_op__invert_in$11$next[0:0]$9546 $1\sr_op__invert_in$11$next[0:0]$9563 assign $0\sr_op__is_32bit$16$next[0:0]$9547 $1\sr_op__is_32bit$16$next[0:0]$9564 assign $0\sr_op__is_signed$17$next[0:0]$9548 $1\sr_op__is_signed$17$next[0:0]$9565 assign { } { } assign { } { } assign $0\sr_op__output_carry$13$next[0:0]$9551 $1\sr_op__output_carry$13$next[0:0]$9568 assign $0\sr_op__output_cr$15$next[0:0]$9552 $1\sr_op__output_cr$15$next[0:0]$9569 assign { } { } assign { } { } assign $0\sr_op__write_cr0$10$next[0:0]$9555 $1\sr_op__write_cr0$10$next[0:0]$9572 assign $0\sr_op__imm_data__data$4$next[63:0]$9540 $2\sr_op__imm_data__data$4$next[63:0]$9573 assign $0\sr_op__imm_data__ok$5$next[0:0]$9541 $2\sr_op__imm_data__ok$5$next[0:0]$9574 assign $0\sr_op__oe__oe$8$next[0:0]$9549 $2\sr_op__oe__oe$8$next[0:0]$9575 assign $0\sr_op__oe__ok$9$next[0:0]$9550 $2\sr_op__oe__ok$9$next[0:0]$9576 assign $0\sr_op__rc__ok$7$next[0:0]$9553 $2\sr_op__rc__ok$7$next[0:0]$9577 assign $0\sr_op__rc__rc$6$next[0:0]$9554 $2\sr_op__rc__rc$6$next[0:0]$9578 attribute \src "libresoc.v:170977.5-170977.29" switch \initial attribute \src "libresoc.v:170977.9-170977.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\sr_op__insn$18$next[31:0]$9561 $1\sr_op__is_signed$17$next[0:0]$9565 $1\sr_op__is_32bit$16$next[0:0]$9564 $1\sr_op__output_cr$15$next[0:0]$9569 $1\sr_op__input_cr$14$next[0:0]$9560 $1\sr_op__output_carry$13$next[0:0]$9568 $1\sr_op__input_carry$12$next[1:0]$9559 $1\sr_op__invert_in$11$next[0:0]$9563 $1\sr_op__write_cr0$10$next[0:0]$9572 $1\sr_op__oe__ok$9$next[0:0]$9567 $1\sr_op__oe__oe$8$next[0:0]$9566 $1\sr_op__rc__ok$7$next[0:0]$9570 $1\sr_op__rc__rc$6$next[0:0]$9571 $1\sr_op__imm_data__ok$5$next[0:0]$9558 $1\sr_op__imm_data__data$4$next[63:0]$9557 $1\sr_op__fn_unit$3$next[13:0]$9556 $1\sr_op__insn_type$2$next[6:0]$9562 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\sr_op__insn$18$next[31:0]$9561 $1\sr_op__is_signed$17$next[0:0]$9565 $1\sr_op__is_32bit$16$next[0:0]$9564 $1\sr_op__output_cr$15$next[0:0]$9569 $1\sr_op__input_cr$14$next[0:0]$9560 $1\sr_op__output_carry$13$next[0:0]$9568 $1\sr_op__input_carry$12$next[1:0]$9559 $1\sr_op__invert_in$11$next[0:0]$9563 $1\sr_op__write_cr0$10$next[0:0]$9572 $1\sr_op__oe__ok$9$next[0:0]$9567 $1\sr_op__oe__oe$8$next[0:0]$9566 $1\sr_op__rc__ok$7$next[0:0]$9570 $1\sr_op__rc__rc$6$next[0:0]$9571 $1\sr_op__imm_data__ok$5$next[0:0]$9558 $1\sr_op__imm_data__data$4$next[63:0]$9557 $1\sr_op__fn_unit$3$next[13:0]$9556 $1\sr_op__insn_type$2$next[6:0]$9562 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case assign $1\sr_op__fn_unit$3$next[13:0]$9556 \sr_op__fn_unit$3 assign $1\sr_op__imm_data__data$4$next[63:0]$9557 \sr_op__imm_data__data$4 assign $1\sr_op__imm_data__ok$5$next[0:0]$9558 \sr_op__imm_data__ok$5 assign $1\sr_op__input_carry$12$next[1:0]$9559 \sr_op__input_carry$12 assign $1\sr_op__input_cr$14$next[0:0]$9560 \sr_op__input_cr$14 assign $1\sr_op__insn$18$next[31:0]$9561 \sr_op__insn$18 assign $1\sr_op__insn_type$2$next[6:0]$9562 \sr_op__insn_type$2 assign $1\sr_op__invert_in$11$next[0:0]$9563 \sr_op__invert_in$11 assign $1\sr_op__is_32bit$16$next[0:0]$9564 \sr_op__is_32bit$16 assign $1\sr_op__is_signed$17$next[0:0]$9565 \sr_op__is_signed$17 assign $1\sr_op__oe__oe$8$next[0:0]$9566 \sr_op__oe__oe$8 assign $1\sr_op__oe__ok$9$next[0:0]$9567 \sr_op__oe__ok$9 assign $1\sr_op__output_carry$13$next[0:0]$9568 \sr_op__output_carry$13 assign $1\sr_op__output_cr$15$next[0:0]$9569 \sr_op__output_cr$15 assign $1\sr_op__rc__ok$7$next[0:0]$9570 \sr_op__rc__ok$7 assign $1\sr_op__rc__rc$6$next[0:0]$9571 \sr_op__rc__rc$6 assign $1\sr_op__write_cr0$10$next[0:0]$9572 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\sr_op__imm_data__data$4$next[63:0]$9573 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\sr_op__imm_data__ok$5$next[0:0]$9574 1'0 assign $2\sr_op__rc__rc$6$next[0:0]$9578 1'0 assign $2\sr_op__rc__ok$7$next[0:0]$9577 1'0 assign $2\sr_op__oe__oe$8$next[0:0]$9575 1'0 assign $2\sr_op__oe__ok$9$next[0:0]$9576 1'0 case assign $2\sr_op__imm_data__data$4$next[63:0]$9573 $1\sr_op__imm_data__data$4$next[63:0]$9557 assign $2\sr_op__imm_data__ok$5$next[0:0]$9574 $1\sr_op__imm_data__ok$5$next[0:0]$9558 assign $2\sr_op__oe__oe$8$next[0:0]$9575 $1\sr_op__oe__oe$8$next[0:0]$9566 assign $2\sr_op__oe__ok$9$next[0:0]$9576 $1\sr_op__oe__ok$9$next[0:0]$9567 assign $2\sr_op__rc__ok$7$next[0:0]$9577 $1\sr_op__rc__ok$7$next[0:0]$9570 assign $2\sr_op__rc__rc$6$next[0:0]$9578 $1\sr_op__rc__rc$6$next[0:0]$9571 end sync always update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9539 update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9540 update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9541 update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9542 update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9543 update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9544 update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9545 update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9546 update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9547 update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9548 update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9549 update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9550 update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9551 update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9552 update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9553 update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9554 update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9555 end attribute \src "libresoc.v:171017.3-171035.6" process $proc$libresoc.v:171017$9579 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$19$next[63:0]$9580 $1\o$19$next[63:0]$9582 assign { } { } assign $0\o_ok$20$next[0:0]$9581 $2\o_ok$20$next[0:0]$9584 attribute \src "libresoc.v:171018.5-171018.29" switch \initial attribute \src "libresoc.v:171018.9-171018.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$20$next[0:0]$9583 $1\o$19$next[63:0]$9582 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$20$next[0:0]$9583 $1\o$19$next[63:0]$9582 } { \o_ok$72 \o$71 } case assign $1\o$19$next[63:0]$9582 \o$19 assign $1\o_ok$20$next[0:0]$9583 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$20$next[0:0]$9584 1'0 case assign $2\o_ok$20$next[0:0]$9584 $1\o_ok$20$next[0:0]$9583 end sync always update \o$19$next $0\o$19$next[63:0]$9580 update \o_ok$20$next $0\o_ok$20$next[0:0]$9581 end attribute \src "libresoc.v:171036.3-171054.6" process $proc$libresoc.v:171036$9585 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$21$next[3:0]$9586 $1\cr_a$21$next[3:0]$9588 assign { } { } assign $0\cr_a_ok$22$next[0:0]$9587 $2\cr_a_ok$22$next[0:0]$9590 attribute \src "libresoc.v:171037.5-171037.29" switch \initial attribute \src "libresoc.v:171037.9-171037.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$22$next[0:0]$9589 $1\cr_a$21$next[3:0]$9588 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$22$next[0:0]$9589 $1\cr_a$21$next[3:0]$9588 } { \cr_a_ok$74 \cr_a$73 } case assign $1\cr_a$21$next[3:0]$9588 \cr_a$21 assign $1\cr_a_ok$22$next[0:0]$9589 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$22$next[0:0]$9590 1'0 case assign $2\cr_a_ok$22$next[0:0]$9590 $1\cr_a_ok$22$next[0:0]$9589 end sync always update \cr_a$21$next $0\cr_a$21$next[3:0]$9586 update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9587 end attribute \src "libresoc.v:171055.3-171073.6" process $proc$libresoc.v:171055$9591 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ca$23$next[1:0]$9592 $1\xer_ca$23$next[1:0]$9594 assign { } { } assign $0\xer_ca_ok$24$next[0:0]$9593 $2\xer_ca_ok$24$next[0:0]$9596 attribute \src "libresoc.v:171056.5-171056.29" switch \initial attribute \src "libresoc.v:171056.9-171056.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ca_ok$24$next[0:0]$9595 $1\xer_ca$23$next[1:0]$9594 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ca_ok$24$next[0:0]$9595 $1\xer_ca$23$next[1:0]$9594 } { \xer_ca_ok$76 \xer_ca$75 } case assign $1\xer_ca$23$next[1:0]$9594 \xer_ca$23 assign $1\xer_ca_ok$24$next[0:0]$9595 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ca_ok$24$next[0:0]$9596 1'0 case assign $2\xer_ca_ok$24$next[0:0]$9596 $1\xer_ca_ok$24$next[0:0]$9595 end sync always update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9592 update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9593 end connect \$51 $and$libresoc.v:170837$9481_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } connect \muxid$53 \output_muxid$25 connect \p_valid_i_p_ready_o \$51 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$50 \p_valid_i connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } connect { \output_o_ok \output_o } { \o_ok \o } connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end attribute \src "libresoc.v:171094.1-172058.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 attribute \src "libresoc.v:171964.3-171982.6" wire width 64 $0\fast1$11$next[63:0]$9715 attribute \src "libresoc.v:171841.3-171842.35" wire width 64 $0\fast1$11[63:0]$9677 attribute \src "libresoc.v:171106.14-171106.47" wire width 64 $0\fast1$11[63:0]$9739 attribute \src "libresoc.v:171964.3-171982.6" wire $0\fast1_ok$next[0:0]$9714 attribute \src "libresoc.v:171843.3-171844.33" wire $0\fast1_ok[0:0] attribute \src "libresoc.v:171983.3-172001.6" wire width 64 $0\fast2$12$next[63:0]$9721 attribute \src "libresoc.v:171837.3-171838.35" wire width 64 $0\fast2$12[63:0]$9674 attribute \src "libresoc.v:171122.14-171122.47" wire width 64 $0\fast2$12[63:0]$9742 attribute \src "libresoc.v:171983.3-172001.6" wire $0\fast2_ok$next[0:0]$9720 attribute \src "libresoc.v:171839.3-171840.33" wire $0\fast2_ok[0:0] attribute \src "libresoc.v:171095.7-171095.20" wire $0\initial[0:0] attribute \src "libresoc.v:172021.3-172039.6" wire width 64 $0\msr$next[63:0]$9732 attribute \src "libresoc.v:171829.3-171830.23" wire width 64 $0\msr[63:0] attribute \src "libresoc.v:172021.3-172039.6" wire $0\msr_ok$next[0:0]$9733 attribute \src "libresoc.v:171831.3-171832.29" wire $0\msr_ok[0:0] attribute \src "libresoc.v:171911.3-171923.6" wire width 2 $0\muxid$1$next[1:0]$9686 attribute \src "libresoc.v:171825.3-171826.33" wire width 2 $0\muxid$1[1:0]$9667 attribute \src "libresoc.v:171400.13-171400.29" wire width 2 $0\muxid$1[1:0]$9747 attribute \src "libresoc.v:172002.3-172020.6" wire width 64 $0\nia$next[63:0]$9726 attribute \src "libresoc.v:171833.3-171834.23" wire width 64 $0\nia[63:0] attribute \src "libresoc.v:172002.3-172020.6" wire $0\nia_ok$next[0:0]$9727 attribute \src "libresoc.v:171835.3-171836.29" wire $0\nia_ok[0:0] attribute \src "libresoc.v:171945.3-171963.6" wire width 64 $0\o$next[63:0]$9708 attribute \src "libresoc.v:171845.3-171846.19" wire width 64 $0\o[63:0] attribute \src "libresoc.v:171945.3-171963.6" wire $0\o_ok$next[0:0]$9709 attribute \src "libresoc.v:171847.3-171848.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:171893.3-171910.6" wire $0\r_busy$next[0:0]$9682 attribute \src "libresoc.v:171827.3-171828.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $0\trap_op__cia$6$next[63:0]$9689 attribute \src "libresoc.v:171815.3-171816.47" wire width 64 $0\trap_op__cia$6[63:0]$9657 attribute \src "libresoc.v:171461.14-171461.53" wire width 64 $0\trap_op__cia$6[63:0]$9754 attribute \src "libresoc.v:171924.3-171944.6" wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9690 attribute \src "libresoc.v:171809.3-171810.55" wire width 14 $0\trap_op__fn_unit$3[13:0]$9651 attribute \src "libresoc.v:171498.14-171498.45" wire width 14 $0\trap_op__fn_unit$3[13:0]$9756 attribute \src "libresoc.v:171924.3-171944.6" wire width 32 $0\trap_op__insn$4$next[31:0]$9691 attribute \src "libresoc.v:171811.3-171812.49" wire width 32 $0\trap_op__insn$4[31:0]$9653 attribute \src "libresoc.v:171524.14-171524.39" wire width 32 $0\trap_op__insn$4[31:0]$9758 attribute \src "libresoc.v:171924.3-171944.6" wire width 7 $0\trap_op__insn_type$2$next[6:0]$9692 attribute \src "libresoc.v:171807.3-171808.59" wire width 7 $0\trap_op__insn_type$2[6:0]$9649 attribute \src "libresoc.v:171681.13-171681.43" wire width 7 $0\trap_op__insn_type$2[6:0]$9760 attribute \src "libresoc.v:171924.3-171944.6" wire $0\trap_op__is_32bit$7$next[0:0]$9693 attribute \src "libresoc.v:171817.3-171818.57" wire $0\trap_op__is_32bit$7[0:0]$9659 attribute \src "libresoc.v:171767.7-171767.35" wire $0\trap_op__is_32bit$7[0:0]$9762 attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9694 attribute \src "libresoc.v:171823.3-171824.59" wire width 8 $0\trap_op__ldst_exc$10[7:0]$9665 attribute \src "libresoc.v:171774.13-171774.43" wire width 8 $0\trap_op__ldst_exc$10[7:0]$9764 attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $0\trap_op__msr$5$next[63:0]$9695 attribute \src "libresoc.v:171813.3-171814.47" wire width 64 $0\trap_op__msr$5[63:0]$9655 attribute \src "libresoc.v:171785.14-171785.53" wire width 64 $0\trap_op__msr$5[63:0]$9766 attribute \src "libresoc.v:171924.3-171944.6" wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9696 attribute \src "libresoc.v:171821.3-171822.57" wire width 13 $0\trap_op__trapaddr$9[12:0]$9663 attribute \src "libresoc.v:171794.14-171794.46" wire width 13 $0\trap_op__trapaddr$9[12:0]$9768 attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $0\trap_op__traptype$8$next[7:0]$9697 attribute \src "libresoc.v:171819.3-171820.57" wire width 8 $0\trap_op__traptype$8[7:0]$9661 attribute \src "libresoc.v:171803.13-171803.42" wire width 8 $0\trap_op__traptype$8[7:0]$9770 attribute \src "libresoc.v:171964.3-171982.6" wire width 64 $1\fast1$11$next[63:0]$9717 attribute \src "libresoc.v:171964.3-171982.6" wire $1\fast1_ok$next[0:0]$9716 attribute \src "libresoc.v:171113.7-171113.22" wire $1\fast1_ok[0:0] attribute \src "libresoc.v:171983.3-172001.6" wire width 64 $1\fast2$12$next[63:0]$9723 attribute \src "libresoc.v:171983.3-172001.6" wire $1\fast2_ok$next[0:0]$9722 attribute \src "libresoc.v:171129.7-171129.22" wire $1\fast2_ok[0:0] attribute \src "libresoc.v:172021.3-172039.6" wire width 64 $1\msr$next[63:0]$9734 attribute \src "libresoc.v:171384.14-171384.40" wire width 64 $1\msr[63:0] attribute \src "libresoc.v:172021.3-172039.6" wire $1\msr_ok$next[0:0]$9735 attribute \src "libresoc.v:171391.7-171391.20" wire $1\msr_ok[0:0] attribute \src "libresoc.v:171911.3-171923.6" wire width 2 $1\muxid$1$next[1:0]$9687 attribute \src "libresoc.v:172002.3-172020.6" wire width 64 $1\nia$next[63:0]$9728 attribute \src "libresoc.v:171413.14-171413.40" wire width 64 $1\nia[63:0] attribute \src "libresoc.v:172002.3-172020.6" wire $1\nia_ok$next[0:0]$9729 attribute \src "libresoc.v:171420.7-171420.20" wire $1\nia_ok[0:0] attribute \src "libresoc.v:171945.3-171963.6" wire width 64 $1\o$next[63:0]$9710 attribute \src "libresoc.v:171427.14-171427.38" wire width 64 $1\o[63:0] attribute \src "libresoc.v:171945.3-171963.6" wire $1\o_ok$next[0:0]$9711 attribute \src "libresoc.v:171434.7-171434.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:171893.3-171910.6" wire $1\r_busy$next[0:0]$9683 attribute \src "libresoc.v:171448.7-171448.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $1\trap_op__cia$6$next[63:0]$9698 attribute \src "libresoc.v:171924.3-171944.6" wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9699 attribute \src "libresoc.v:171924.3-171944.6" wire width 32 $1\trap_op__insn$4$next[31:0]$9700 attribute \src "libresoc.v:171924.3-171944.6" wire width 7 $1\trap_op__insn_type$2$next[6:0]$9701 attribute \src "libresoc.v:171924.3-171944.6" wire $1\trap_op__is_32bit$7$next[0:0]$9702 attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9703 attribute \src "libresoc.v:171924.3-171944.6" wire width 64 $1\trap_op__msr$5$next[63:0]$9704 attribute \src "libresoc.v:171924.3-171944.6" wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9705 attribute \src "libresoc.v:171924.3-171944.6" wire width 8 $1\trap_op__traptype$8$next[7:0]$9706 attribute \src "libresoc.v:171964.3-171982.6" wire $2\fast1_ok$next[0:0]$9718 attribute \src "libresoc.v:171983.3-172001.6" wire $2\fast2_ok$next[0:0]$9724 attribute \src "libresoc.v:172021.3-172039.6" wire $2\msr_ok$next[0:0]$9736 attribute \src "libresoc.v:172002.3-172020.6" wire $2\nia_ok$next[0:0]$9730 attribute \src "libresoc.v:171945.3-171963.6" wire $2\o_ok$next[0:0]$9712 attribute \src "libresoc.v:171893.3-171910.6" wire $2\r_busy$next[0:0]$9684 attribute \src "libresoc.v:171806.18-171806.118" wire $and$libresoc.v:171806$9647_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 40 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 16 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 32 \fast1$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast1$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 17 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 34 \fast2$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \fast2$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \fast2_ok$next attribute \src "libresoc.v:171095.7-171095.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast1$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_fast2$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_trap_op__cia$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \main_trap_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \main_trap_op__insn$16 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute 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"OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \main_trap_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \main_trap_op__is_32bit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \main_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \main_trap_op__ldst_exc$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_trap_op__msr$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \main_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \main_trap_op__trapaddr$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \main_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \main_trap_op__traptype$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 38 \msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \msr$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 39 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \msr_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \msr_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 20 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 19 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 18 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 36 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 37 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \nia_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 30 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 31 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 15 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 9 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 25 \trap_op__cia$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__cia$6$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 22 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \trap_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \trap_op__fn_unit$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \trap_op__insn$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 23 \trap_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \trap_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 21 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \trap_op__insn_type$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \trap_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \trap_op__is_32bit$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__ldst_exc$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__ldst_exc$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__msr$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \trap_op__msr$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \trap_op__trapaddr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 output 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \trap_op__trapaddr$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 output 27 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:171806$9647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o connect \Y $and$libresoc.v:171806$9647_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:171849.13-171884.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 connect \fast1_ok \main_fast1_ok connect \fast2 \main_fast2 connect \fast2$12 \main_fast2$24 connect \fast2_ok \main_fast2_ok connect \msr \main_msr connect \msr_ok \main_msr_ok connect \muxid \main_muxid connect \muxid$1 \main_muxid$13 connect \nia \main_nia connect \nia_ok \main_nia_ok connect \o \main_o connect \o_ok \main_o_ok connect \ra \main_ra connect \rb \main_rb connect \trap_op__cia \main_trap_op__cia connect \trap_op__cia$6 \main_trap_op__cia$18 connect \trap_op__fn_unit \main_trap_op__fn_unit connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 connect \trap_op__insn \main_trap_op__insn connect \trap_op__insn$4 \main_trap_op__insn$16 connect \trap_op__insn_type \main_trap_op__insn_type connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 connect \trap_op__is_32bit \main_trap_op__is_32bit connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 connect \trap_op__ldst_exc \main_trap_op__ldst_exc connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 connect \trap_op__msr \main_trap_op__msr connect \trap_op__msr$5 \main_trap_op__msr$17 connect \trap_op__trapaddr \main_trap_op__trapaddr connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 connect \trap_op__traptype \main_trap_op__traptype connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 attribute \src "libresoc.v:171885.10-171888.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:171889.10-171892.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:171095.7-171095.20" process $proc$libresoc.v:171095$9737 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:171106.14-171106.47" process $proc$libresoc.v:171106$9738 assign { } { } assign $0\fast1$11[63:0]$9739 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$11 $0\fast1$11[63:0]$9739 end attribute \src "libresoc.v:171113.7-171113.22" process $proc$libresoc.v:171113$9740 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end attribute \src "libresoc.v:171122.14-171122.47" process $proc$libresoc.v:171122$9741 assign { } { } assign $0\fast2$12[63:0]$9742 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2$12 $0\fast2$12[63:0]$9742 end attribute \src "libresoc.v:171129.7-171129.22" process $proc$libresoc.v:171129$9743 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end attribute \src "libresoc.v:171384.14-171384.40" process $proc$libresoc.v:171384$9744 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end attribute \src "libresoc.v:171391.7-171391.20" process $proc$libresoc.v:171391$9745 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end attribute \src "libresoc.v:171400.13-171400.29" process $proc$libresoc.v:171400$9746 assign { } { } assign $0\muxid$1[1:0]$9747 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9747 end attribute \src "libresoc.v:171413.14-171413.40" process $proc$libresoc.v:171413$9748 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end attribute \src "libresoc.v:171420.7-171420.20" process $proc$libresoc.v:171420$9749 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end attribute \src "libresoc.v:171427.14-171427.38" process $proc$libresoc.v:171427$9750 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end attribute \src "libresoc.v:171434.7-171434.18" process $proc$libresoc.v:171434$9751 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:171448.7-171448.20" process $proc$libresoc.v:171448$9752 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:171461.14-171461.53" process $proc$libresoc.v:171461$9753 assign { } { } assign $0\trap_op__cia$6[63:0]$9754 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9754 end attribute \src "libresoc.v:171498.14-171498.45" process $proc$libresoc.v:171498$9755 assign { } { } assign $0\trap_op__fn_unit$3[13:0]$9756 14'00000000000000 sync always sync init update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9756 end attribute \src "libresoc.v:171524.14-171524.39" process $proc$libresoc.v:171524$9757 assign { } { } assign $0\trap_op__insn$4[31:0]$9758 0 sync always sync init update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9758 end attribute \src "libresoc.v:171681.13-171681.43" process $proc$libresoc.v:171681$9759 assign { } { } assign $0\trap_op__insn_type$2[6:0]$9760 7'0000000 sync always sync init update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9760 end attribute \src "libresoc.v:171767.7-171767.35" process $proc$libresoc.v:171767$9761 assign { } { } assign $0\trap_op__is_32bit$7[0:0]$9762 1'0 sync always sync init update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9762 end attribute \src "libresoc.v:171774.13-171774.43" process $proc$libresoc.v:171774$9763 assign { } { } assign $0\trap_op__ldst_exc$10[7:0]$9764 8'00000000 sync always sync init update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9764 end attribute \src "libresoc.v:171785.14-171785.53" process $proc$libresoc.v:171785$9765 assign { } { } assign $0\trap_op__msr$5[63:0]$9766 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9766 end attribute \src "libresoc.v:171794.14-171794.46" process $proc$libresoc.v:171794$9767 assign { } { } assign $0\trap_op__trapaddr$9[12:0]$9768 13'0000000000000 sync always sync init update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9768 end attribute \src "libresoc.v:171803.13-171803.42" process $proc$libresoc.v:171803$9769 assign { } { } assign $0\trap_op__traptype$8[7:0]$9770 8'00000000 sync always sync init update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9770 end attribute \src "libresoc.v:171807.3-171808.59" process $proc$libresoc.v:171807$9648 assign { } { } assign $0\trap_op__insn_type$2[6:0]$9649 \trap_op__insn_type$2$next sync posedge \coresync_clk update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9649 end attribute \src "libresoc.v:171809.3-171810.55" process $proc$libresoc.v:171809$9650 assign { } { } assign $0\trap_op__fn_unit$3[13:0]$9651 \trap_op__fn_unit$3$next sync posedge \coresync_clk update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9651 end attribute \src "libresoc.v:171811.3-171812.49" process $proc$libresoc.v:171811$9652 assign { } { } assign $0\trap_op__insn$4[31:0]$9653 \trap_op__insn$4$next sync posedge \coresync_clk update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9653 end attribute \src "libresoc.v:171813.3-171814.47" process $proc$libresoc.v:171813$9654 assign { } { } assign $0\trap_op__msr$5[63:0]$9655 \trap_op__msr$5$next sync posedge \coresync_clk update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9655 end attribute \src "libresoc.v:171815.3-171816.47" process $proc$libresoc.v:171815$9656 assign { } { } assign $0\trap_op__cia$6[63:0]$9657 \trap_op__cia$6$next sync posedge \coresync_clk update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9657 end attribute \src "libresoc.v:171817.3-171818.57" process $proc$libresoc.v:171817$9658 assign { } { } assign $0\trap_op__is_32bit$7[0:0]$9659 \trap_op__is_32bit$7$next sync posedge \coresync_clk update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9659 end attribute \src "libresoc.v:171819.3-171820.57" process $proc$libresoc.v:171819$9660 assign { } { } assign $0\trap_op__traptype$8[7:0]$9661 \trap_op__traptype$8$next sync posedge \coresync_clk update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9661 end attribute \src "libresoc.v:171821.3-171822.57" process $proc$libresoc.v:171821$9662 assign { } { } assign $0\trap_op__trapaddr$9[12:0]$9663 \trap_op__trapaddr$9$next sync posedge \coresync_clk update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9663 end attribute \src "libresoc.v:171823.3-171824.59" process $proc$libresoc.v:171823$9664 assign { } { } assign $0\trap_op__ldst_exc$10[7:0]$9665 \trap_op__ldst_exc$10$next sync posedge \coresync_clk update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9665 end attribute \src "libresoc.v:171825.3-171826.33" process $proc$libresoc.v:171825$9666 assign { } { } assign $0\muxid$1[1:0]$9667 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9667 end attribute \src "libresoc.v:171827.3-171828.29" process $proc$libresoc.v:171827$9668 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:171829.3-171830.23" process $proc$libresoc.v:171829$9669 assign { } { } assign $0\msr[63:0] \msr$next sync posedge \coresync_clk update \msr $0\msr[63:0] end attribute \src "libresoc.v:171831.3-171832.29" process $proc$libresoc.v:171831$9670 assign { } { } assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk update \msr_ok $0\msr_ok[0:0] end attribute \src "libresoc.v:171833.3-171834.23" process $proc$libresoc.v:171833$9671 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end attribute \src "libresoc.v:171835.3-171836.29" process $proc$libresoc.v:171835$9672 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end attribute \src "libresoc.v:171837.3-171838.35" process $proc$libresoc.v:171837$9673 assign { } { } assign $0\fast2$12[63:0]$9674 \fast2$12$next sync posedge \coresync_clk update \fast2$12 $0\fast2$12[63:0]$9674 end attribute \src "libresoc.v:171839.3-171840.33" process $proc$libresoc.v:171839$9675 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end attribute \src "libresoc.v:171841.3-171842.35" process $proc$libresoc.v:171841$9676 assign { } { } assign $0\fast1$11[63:0]$9677 \fast1$11$next sync posedge \coresync_clk update \fast1$11 $0\fast1$11[63:0]$9677 end attribute \src "libresoc.v:171843.3-171844.33" process $proc$libresoc.v:171843$9678 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end attribute \src "libresoc.v:171845.3-171846.19" process $proc$libresoc.v:171845$9679 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end attribute \src "libresoc.v:171847.3-171848.25" process $proc$libresoc.v:171847$9680 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:171893.3-171910.6" process $proc$libresoc.v:171893$9681 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9682 $2\r_busy$next[0:0]$9684 attribute \src "libresoc.v:171894.5-171894.29" switch \initial attribute \src "libresoc.v:171894.9-171894.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$9683 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$9683 1'0 case assign $1\r_busy$next[0:0]$9683 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$9684 1'0 case assign $2\r_busy$next[0:0]$9684 $1\r_busy$next[0:0]$9683 end sync always update \r_busy$next $0\r_busy$next[0:0]$9682 end attribute \src "libresoc.v:171911.3-171923.6" process $proc$libresoc.v:171911$9685 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9686 $1\muxid$1$next[1:0]$9687 attribute \src "libresoc.v:171912.5-171912.29" switch \initial attribute \src "libresoc.v:171912.9-171912.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$9687 \muxid$28 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$9687 \muxid$28 case assign $1\muxid$1$next[1:0]$9687 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$9686 end attribute \src "libresoc.v:171924.3-171944.6" process $proc$libresoc.v:171924$9688 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\trap_op__cia$6$next[63:0]$9689 $1\trap_op__cia$6$next[63:0]$9698 assign $0\trap_op__fn_unit$3$next[13:0]$9690 $1\trap_op__fn_unit$3$next[13:0]$9699 assign $0\trap_op__insn$4$next[31:0]$9691 $1\trap_op__insn$4$next[31:0]$9700 assign $0\trap_op__insn_type$2$next[6:0]$9692 $1\trap_op__insn_type$2$next[6:0]$9701 assign $0\trap_op__is_32bit$7$next[0:0]$9693 $1\trap_op__is_32bit$7$next[0:0]$9702 assign $0\trap_op__ldst_exc$10$next[7:0]$9694 $1\trap_op__ldst_exc$10$next[7:0]$9703 assign $0\trap_op__msr$5$next[63:0]$9695 $1\trap_op__msr$5$next[63:0]$9704 assign $0\trap_op__trapaddr$9$next[12:0]$9696 $1\trap_op__trapaddr$9$next[12:0]$9705 assign $0\trap_op__traptype$8$next[7:0]$9697 $1\trap_op__traptype$8$next[7:0]$9706 attribute \src "libresoc.v:171925.5-171925.29" switch \initial attribute \src "libresoc.v:171925.9-171925.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\trap_op__ldst_exc$10$next[7:0]$9703 $1\trap_op__trapaddr$9$next[12:0]$9705 $1\trap_op__traptype$8$next[7:0]$9706 $1\trap_op__is_32bit$7$next[0:0]$9702 $1\trap_op__cia$6$next[63:0]$9698 $1\trap_op__msr$5$next[63:0]$9704 $1\trap_op__insn$4$next[31:0]$9700 $1\trap_op__fn_unit$3$next[13:0]$9699 $1\trap_op__insn_type$2$next[6:0]$9701 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\trap_op__ldst_exc$10$next[7:0]$9703 $1\trap_op__trapaddr$9$next[12:0]$9705 $1\trap_op__traptype$8$next[7:0]$9706 $1\trap_op__is_32bit$7$next[0:0]$9702 $1\trap_op__cia$6$next[63:0]$9698 $1\trap_op__msr$5$next[63:0]$9704 $1\trap_op__insn$4$next[31:0]$9700 $1\trap_op__fn_unit$3$next[13:0]$9699 $1\trap_op__insn_type$2$next[6:0]$9701 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case assign $1\trap_op__cia$6$next[63:0]$9698 \trap_op__cia$6 assign $1\trap_op__fn_unit$3$next[13:0]$9699 \trap_op__fn_unit$3 assign $1\trap_op__insn$4$next[31:0]$9700 \trap_op__insn$4 assign $1\trap_op__insn_type$2$next[6:0]$9701 \trap_op__insn_type$2 assign $1\trap_op__is_32bit$7$next[0:0]$9702 \trap_op__is_32bit$7 assign $1\trap_op__ldst_exc$10$next[7:0]$9703 \trap_op__ldst_exc$10 assign $1\trap_op__msr$5$next[63:0]$9704 \trap_op__msr$5 assign $1\trap_op__trapaddr$9$next[12:0]$9705 \trap_op__trapaddr$9 assign $1\trap_op__traptype$8$next[7:0]$9706 \trap_op__traptype$8 end sync always update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9689 update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9690 update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9691 update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9692 update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9693 update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9694 update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9695 update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9696 update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9697 end attribute \src "libresoc.v:171945.3-171963.6" process $proc$libresoc.v:171945$9707 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$next[63:0]$9708 $1\o$next[63:0]$9710 assign { } { } assign $0\o_ok$next[0:0]$9709 $2\o_ok$next[0:0]$9712 attribute \src "libresoc.v:171946.5-171946.29" switch \initial attribute \src "libresoc.v:171946.9-171946.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9711 $1\o$next[63:0]$9710 } { \o_ok$39 \o$38 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9711 $1\o$next[63:0]$9710 } { \o_ok$39 \o$38 } case assign $1\o$next[63:0]$9710 \o assign $1\o_ok$next[0:0]$9711 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$9712 1'0 case assign $2\o_ok$next[0:0]$9712 $1\o_ok$next[0:0]$9711 end sync always update \o$next $0\o$next[63:0]$9708 update \o_ok$next $0\o_ok$next[0:0]$9709 end attribute \src "libresoc.v:171964.3-171982.6" process $proc$libresoc.v:171964$9713 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast1$11$next[63:0]$9715 $1\fast1$11$next[63:0]$9717 assign $0\fast1_ok$next[0:0]$9714 $2\fast1_ok$next[0:0]$9718 attribute \src "libresoc.v:171965.5-171965.29" switch \initial attribute \src "libresoc.v:171965.9-171965.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\fast1_ok$next[0:0]$9716 $1\fast1$11$next[63:0]$9717 } { \fast1_ok$41 \fast1$40 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\fast1_ok$next[0:0]$9716 $1\fast1$11$next[63:0]$9717 } { \fast1_ok$41 \fast1$40 } case assign $1\fast1_ok$next[0:0]$9716 \fast1_ok assign $1\fast1$11$next[63:0]$9717 \fast1$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast1_ok$next[0:0]$9718 1'0 case assign $2\fast1_ok$next[0:0]$9718 $1\fast1_ok$next[0:0]$9716 end sync always update \fast1_ok$next $0\fast1_ok$next[0:0]$9714 update \fast1$11$next $0\fast1$11$next[63:0]$9715 end attribute \src "libresoc.v:171983.3-172001.6" process $proc$libresoc.v:171983$9719 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast2$12$next[63:0]$9721 $1\fast2$12$next[63:0]$9723 assign $0\fast2_ok$next[0:0]$9720 $2\fast2_ok$next[0:0]$9724 attribute \src "libresoc.v:171984.5-171984.29" switch \initial attribute \src "libresoc.v:171984.9-171984.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\fast2_ok$next[0:0]$9722 $1\fast2$12$next[63:0]$9723 } { \fast2_ok$43 \fast2$42 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\fast2_ok$next[0:0]$9722 $1\fast2$12$next[63:0]$9723 } { \fast2_ok$43 \fast2$42 } case assign $1\fast2_ok$next[0:0]$9722 \fast2_ok assign $1\fast2$12$next[63:0]$9723 \fast2$12 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fast2_ok$next[0:0]$9724 1'0 case assign $2\fast2_ok$next[0:0]$9724 $1\fast2_ok$next[0:0]$9722 end sync always update \fast2_ok$next $0\fast2_ok$next[0:0]$9720 update \fast2$12$next $0\fast2$12$next[63:0]$9721 end attribute \src "libresoc.v:172002.3-172020.6" process $proc$libresoc.v:172002$9725 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\nia$next[63:0]$9726 $1\nia$next[63:0]$9728 assign { } { } assign $0\nia_ok$next[0:0]$9727 $2\nia_ok$next[0:0]$9730 attribute \src "libresoc.v:172003.5-172003.29" switch \initial attribute \src "libresoc.v:172003.9-172003.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\nia_ok$next[0:0]$9729 $1\nia$next[63:0]$9728 } { \nia_ok$45 \nia$44 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\nia_ok$next[0:0]$9729 $1\nia$next[63:0]$9728 } { \nia_ok$45 \nia$44 } case assign $1\nia$next[63:0]$9728 \nia assign $1\nia_ok$next[0:0]$9729 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\nia_ok$next[0:0]$9730 1'0 case assign $2\nia_ok$next[0:0]$9730 $1\nia_ok$next[0:0]$9729 end sync always update \nia$next $0\nia$next[63:0]$9726 update \nia_ok$next $0\nia_ok$next[0:0]$9727 end attribute \src "libresoc.v:172021.3-172039.6" process $proc$libresoc.v:172021$9731 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr$next[63:0]$9732 $1\msr$next[63:0]$9734 assign { } { } assign $0\msr_ok$next[0:0]$9733 $2\msr_ok$next[0:0]$9736 attribute \src "libresoc.v:172022.5-172022.29" switch \initial attribute \src "libresoc.v:172022.9-172022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\msr_ok$next[0:0]$9735 $1\msr$next[63:0]$9734 } { \msr_ok$47 \msr$46 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\msr_ok$next[0:0]$9735 $1\msr$next[63:0]$9734 } { \msr_ok$47 \msr$46 } case assign $1\msr$next[63:0]$9734 \msr assign $1\msr_ok$next[0:0]$9735 \msr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\msr_ok$next[0:0]$9736 1'0 case assign $2\msr_ok$next[0:0]$9736 $1\msr_ok$next[0:0]$9735 end sync always update \msr$next $0\msr$next[63:0]$9732 update \msr_ok$next $0\msr_ok$next[0:0]$9733 end connect \$26 $and$libresoc.v:171806$9647_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } connect \muxid$28 \main_muxid$13 connect \p_valid_i_p_ready_o \$26 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$25 \p_valid_i connect \main_fast2 \fast2 connect \main_fast1 \fast1 connect \main_rb \rb connect \main_ra \ra connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end attribute \src "libresoc.v:172062.1-173565.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end attribute \src "libresoc.v:173403.3-173421.6" wire width 4 $0\cr_a$next[3:0]$9827 attribute \src "libresoc.v:173222.3-173223.25" wire width 4 $0\cr_a[3:0] attribute \src "libresoc.v:173403.3-173421.6" wire $0\cr_a_ok$next[0:0]$9828 attribute \src "libresoc.v:173224.3-173225.31" wire $0\cr_a_ok[0:0] attribute \src "libresoc.v:172063.7-172063.20" wire $0\initial[0:0] attribute \src "libresoc.v:173491.3-173532.6" wire width 4 $0\logical_op__data_len$18$next[3:0]$9852 attribute \src "libresoc.v:173262.3-173263.65" wire width 4 $0\logical_op__data_len$18[3:0]$9814 attribute \src "libresoc.v:172104.13-172104.45" wire width 4 $0\logical_op__data_len$18[3:0]$9898 attribute \src "libresoc.v:173491.3-173532.6" wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9853 attribute \src "libresoc.v:173232.3-173233.61" wire width 14 $0\logical_op__fn_unit$3[13:0]$9784 attribute \src "libresoc.v:172143.14-172143.48" wire width 14 $0\logical_op__fn_unit$3[13:0]$9900 attribute \src "libresoc.v:173491.3-173532.6" wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9854 attribute \src "libresoc.v:173234.3-173235.75" wire width 64 $0\logical_op__imm_data__data$4[63:0]$9786 attribute \src "libresoc.v:172167.14-172167.67" wire width 64 $0\logical_op__imm_data__data$4[63:0]$9902 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__imm_data__ok$5$next[0:0]$9855 attribute \src "libresoc.v:173236.3-173237.71" wire $0\logical_op__imm_data__ok$5[0:0]$9788 attribute \src "libresoc.v:172176.7-172176.42" wire $0\logical_op__imm_data__ok$5[0:0]$9904 attribute \src "libresoc.v:173491.3-173532.6" wire width 2 $0\logical_op__input_carry$12$next[1:0]$9856 attribute \src "libresoc.v:173250.3-173251.71" wire width 2 $0\logical_op__input_carry$12[1:0]$9802 attribute \src "libresoc.v:172193.13-172193.48" wire width 2 $0\logical_op__input_carry$12[1:0]$9906 attribute \src "libresoc.v:173491.3-173532.6" wire width 32 $0\logical_op__insn$19$next[31:0]$9857 attribute \src "libresoc.v:173264.3-173265.57" wire width 32 $0\logical_op__insn$19[31:0]$9816 attribute \src "libresoc.v:172206.14-172206.43" wire width 32 $0\logical_op__insn$19[31:0]$9908 attribute \src "libresoc.v:173491.3-173532.6" wire width 7 $0\logical_op__insn_type$2$next[6:0]$9858 attribute \src "libresoc.v:173230.3-173231.65" wire width 7 $0\logical_op__insn_type$2[6:0]$9782 attribute \src "libresoc.v:172365.13-172365.46" wire width 7 $0\logical_op__insn_type$2[6:0]$9910 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__invert_in$10$next[0:0]$9859 attribute \src "libresoc.v:173246.3-173247.67" wire $0\logical_op__invert_in$10[0:0]$9798 attribute \src "libresoc.v:172449.7-172449.40" wire $0\logical_op__invert_in$10[0:0]$9912 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__invert_out$13$next[0:0]$9860 attribute \src "libresoc.v:173252.3-173253.69" wire $0\logical_op__invert_out$13[0:0]$9804 attribute \src "libresoc.v:172458.7-172458.41" wire $0\logical_op__invert_out$13[0:0]$9914 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__is_32bit$16$next[0:0]$9861 attribute \src "libresoc.v:173258.3-173259.65" wire $0\logical_op__is_32bit$16[0:0]$9810 attribute \src "libresoc.v:172467.7-172467.39" wire $0\logical_op__is_32bit$16[0:0]$9916 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__is_signed$17$next[0:0]$9862 attribute \src "libresoc.v:173260.3-173261.67" wire $0\logical_op__is_signed$17[0:0]$9812 attribute \src "libresoc.v:172476.7-172476.40" wire $0\logical_op__is_signed$17[0:0]$9918 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__oe__oe$8$next[0:0]$9863 attribute \src "libresoc.v:173242.3-173243.59" wire $0\logical_op__oe__oe$8[0:0]$9794 attribute \src "libresoc.v:172485.7-172485.36" wire $0\logical_op__oe__oe$8[0:0]$9920 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__oe__ok$9$next[0:0]$9864 attribute \src "libresoc.v:173244.3-173245.59" wire $0\logical_op__oe__ok$9[0:0]$9796 attribute \src "libresoc.v:172496.7-172496.36" wire $0\logical_op__oe__ok$9[0:0]$9922 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__output_carry$15$next[0:0]$9865 attribute \src "libresoc.v:173256.3-173257.73" wire $0\logical_op__output_carry$15[0:0]$9808 attribute \src "libresoc.v:172503.7-172503.43" wire $0\logical_op__output_carry$15[0:0]$9924 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__rc__ok$7$next[0:0]$9866 attribute \src "libresoc.v:173240.3-173241.59" wire $0\logical_op__rc__ok$7[0:0]$9792 attribute \src "libresoc.v:172512.7-172512.36" wire $0\logical_op__rc__ok$7[0:0]$9926 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__rc__rc$6$next[0:0]$9867 attribute \src "libresoc.v:173238.3-173239.59" wire $0\logical_op__rc__rc$6[0:0]$9790 attribute \src "libresoc.v:172521.7-172521.36" wire $0\logical_op__rc__rc$6[0:0]$9928 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__write_cr0$14$next[0:0]$9868 attribute \src "libresoc.v:173254.3-173255.67" wire $0\logical_op__write_cr0$14[0:0]$9806 attribute \src "libresoc.v:172530.7-172530.40" wire $0\logical_op__write_cr0$14[0:0]$9930 attribute \src "libresoc.v:173491.3-173532.6" wire $0\logical_op__zero_a$11$next[0:0]$9869 attribute \src "libresoc.v:173248.3-173249.61" wire $0\logical_op__zero_a$11[0:0]$9800 attribute \src "libresoc.v:172539.7-172539.37" wire $0\logical_op__zero_a$11[0:0]$9932 attribute \src "libresoc.v:173478.3-173490.6" wire width 2 $0\muxid$1$next[1:0]$9849 attribute \src "libresoc.v:173266.3-173267.33" wire width 2 $0\muxid$1[1:0]$9818 attribute \src "libresoc.v:172548.13-172548.29" wire width 2 $0\muxid$1[1:0]$9934 attribute \src "libresoc.v:173384.3-173402.6" wire width 64 $0\o$next[63:0]$9821 attribute \src "libresoc.v:173226.3-173227.19" wire width 64 $0\o[63:0] attribute \src "libresoc.v:173384.3-173402.6" wire $0\o_ok$next[0:0]$9822 attribute \src "libresoc.v:173228.3-173229.25" wire $0\o_ok[0:0] attribute \src "libresoc.v:173460.3-173477.6" wire $0\r_busy$next[0:0]$9845 attribute \src "libresoc.v:173268.3-173269.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:173422.3-173440.6" wire width 2 $0\xer_ov$next[1:0]$9833 attribute \src "libresoc.v:173218.3-173219.29" wire width 2 $0\xer_ov[1:0] attribute \src "libresoc.v:173422.3-173440.6" wire $0\xer_ov_ok$next[0:0]$9834 attribute \src "libresoc.v:173220.3-173221.35" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:173441.3-173459.6" wire $0\xer_so$20$next[0:0]$9840 attribute \src "libresoc.v:173214.3-173215.37" wire $0\xer_so$20[0:0]$9773 attribute \src "libresoc.v:173199.7-173199.25" wire $0\xer_so$20[0:0]$9941 attribute \src "libresoc.v:173441.3-173459.6" wire $0\xer_so_ok$next[0:0]$9839 attribute \src "libresoc.v:173216.3-173217.35" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:173403.3-173421.6" wire width 4 $1\cr_a$next[3:0]$9829 attribute \src "libresoc.v:172072.13-172072.24" wire width 4 $1\cr_a[3:0] attribute \src "libresoc.v:173403.3-173421.6" wire $1\cr_a_ok$next[0:0]$9830 attribute \src "libresoc.v:172081.7-172081.21" wire $1\cr_a_ok[0:0] attribute \src "libresoc.v:173491.3-173532.6" wire width 4 $1\logical_op__data_len$18$next[3:0]$9870 attribute \src "libresoc.v:173491.3-173532.6" wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9871 attribute \src "libresoc.v:173491.3-173532.6" wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9872 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__imm_data__ok$5$next[0:0]$9873 attribute \src "libresoc.v:173491.3-173532.6" wire width 2 $1\logical_op__input_carry$12$next[1:0]$9874 attribute \src "libresoc.v:173491.3-173532.6" wire width 32 $1\logical_op__insn$19$next[31:0]$9875 attribute \src "libresoc.v:173491.3-173532.6" wire width 7 $1\logical_op__insn_type$2$next[6:0]$9876 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__invert_in$10$next[0:0]$9877 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__invert_out$13$next[0:0]$9878 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__is_32bit$16$next[0:0]$9879 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__is_signed$17$next[0:0]$9880 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__oe__oe$8$next[0:0]$9881 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__oe__ok$9$next[0:0]$9882 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__output_carry$15$next[0:0]$9883 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__rc__ok$7$next[0:0]$9884 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__rc__rc$6$next[0:0]$9885 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__write_cr0$14$next[0:0]$9886 attribute \src "libresoc.v:173491.3-173532.6" wire $1\logical_op__zero_a$11$next[0:0]$9887 attribute \src "libresoc.v:173478.3-173490.6" wire width 2 $1\muxid$1$next[1:0]$9850 attribute \src "libresoc.v:173384.3-173402.6" wire width 64 $1\o$next[63:0]$9823 attribute \src "libresoc.v:172561.14-172561.38" wire width 64 $1\o[63:0] attribute \src "libresoc.v:173384.3-173402.6" wire $1\o_ok$next[0:0]$9824 attribute \src "libresoc.v:172568.7-172568.18" wire $1\o_ok[0:0] attribute \src "libresoc.v:173460.3-173477.6" wire $1\r_busy$next[0:0]$9846 attribute \src "libresoc.v:173164.7-173164.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:173422.3-173440.6" wire width 2 $1\xer_ov$next[1:0]$9835 attribute \src "libresoc.v:173179.13-173179.26" wire width 2 $1\xer_ov[1:0] attribute \src "libresoc.v:173422.3-173440.6" wire $1\xer_ov_ok$next[0:0]$9836 attribute \src "libresoc.v:173186.7-173186.23" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:173441.3-173459.6" wire $1\xer_so$20$next[0:0]$9842 attribute \src "libresoc.v:173441.3-173459.6" wire $1\xer_so_ok$next[0:0]$9841 attribute \src "libresoc.v:173204.7-173204.23" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:173403.3-173421.6" wire $2\cr_a_ok$next[0:0]$9831 attribute \src "libresoc.v:173491.3-173532.6" wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9888 attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__imm_data__ok$5$next[0:0]$9889 attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__oe__oe$8$next[0:0]$9890 attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__oe__ok$9$next[0:0]$9891 attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__rc__ok$7$next[0:0]$9892 attribute \src "libresoc.v:173491.3-173532.6" wire $2\logical_op__rc__rc$6$next[0:0]$9893 attribute \src "libresoc.v:173384.3-173402.6" wire $2\o_ok$next[0:0]$9825 attribute \src "libresoc.v:173460.3-173477.6" wire $2\r_busy$next[0:0]$9847 attribute \src "libresoc.v:173422.3-173440.6" wire $2\xer_ov_ok$next[0:0]$9837 attribute \src "libresoc.v:173441.3-173459.6" wire $2\xer_so_ok$next[0:0]$9843 attribute \src "libresoc.v:173213.18-173213.118" wire $and$libresoc.v:173213$9771_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 62 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 output 56 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 57 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire input 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire input 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg attribute \src "libresoc.v:172063.7-172063.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 52 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$93 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 37 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 38 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 39 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$80 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 15 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 46 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$12$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 53 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$94 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 36 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 44 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 47 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 50 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 51 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 42 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 43 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 49 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 41 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 48 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 45 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 35 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 34 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 33 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 54 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 55 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \output_cr_a$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len$58 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \output_logical_op__input_carry$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \output_logical_op__insn$59 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute 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attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 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attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_logical_op__insn_type$42 attribute \src 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wire \output_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__oe__oe$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__oe__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__output_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__rc__ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_logical_op__rc__rc attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_o_ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \output_stage_div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \output_stage_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \output_stage_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \output_stage_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \output_stage_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_stage_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 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attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_stage_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \output_stage_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \output_stage_logical_op__zero_a$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_stage_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \output_stage_muxid$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \output_stage_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_stage_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \output_stage_quotient_root attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 \output_stage_remainder attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_stage_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_stage_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \output_stage_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_stage_xer_so$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \output_xer_ov$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 input 31 \quotient_root attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 input 32 \remainder attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 58 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \xer_ov$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 59 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 25 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 60 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so$20$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 61 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:173213$9771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o connect \Y $and$libresoc.v:173213$9771_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:173270.10-173273.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:173274.15-173326.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 connect \cr_a_ok \output_cr_a_ok connect \logical_op__data_len \output_logical_op__data_len connect \logical_op__data_len$18 \output_logical_op__data_len$58 connect \logical_op__fn_unit \output_logical_op__fn_unit connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 connect \logical_op__imm_data__data \output_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 connect \logical_op__input_carry \output_logical_op__input_carry connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 connect \logical_op__insn \output_logical_op__insn connect \logical_op__insn$19 \output_logical_op__insn$59 connect \logical_op__insn_type \output_logical_op__insn_type connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 connect \logical_op__invert_in \output_logical_op__invert_in connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 connect \logical_op__invert_out \output_logical_op__invert_out connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 connect \logical_op__is_32bit \output_logical_op__is_32bit connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 connect \logical_op__is_signed \output_logical_op__is_signed connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 connect \logical_op__oe__oe \output_logical_op__oe__oe connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 connect \logical_op__oe__ok \output_logical_op__oe__ok connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 connect \logical_op__output_carry \output_logical_op__output_carry connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 connect \logical_op__rc__ok \output_logical_op__rc__ok connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 connect \logical_op__rc__rc \output_logical_op__rc__rc connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 connect \logical_op__write_cr0 \output_logical_op__write_cr0 connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 connect \logical_op__zero_a \output_logical_op__zero_a connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 connect \muxid \output_muxid connect \muxid$1 \output_muxid$41 connect \o \output_o connect \o$20 \output_o$60 connect \o_ok \output_o_ok connect \o_ok$21 \output_o_ok$61 connect \xer_ov \output_xer_ov connect \xer_ov$23 \output_xer_ov$63 connect \xer_ov_ok \output_xer_ov_ok connect \xer_so \output_xer_so connect \xer_so$24 \output_xer_so$64 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:173327.16-173379.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 connect \dive_abs_ov64 \output_stage_dive_abs_ov64 connect \dividend_neg \output_stage_dividend_neg connect \divisor_neg \output_stage_divisor_neg connect \logical_op__data_len \output_stage_logical_op__data_len connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 connect \logical_op__fn_unit \output_stage_logical_op__fn_unit connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 connect \logical_op__input_carry \output_stage_logical_op__input_carry connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 connect \logical_op__insn \output_stage_logical_op__insn connect \logical_op__insn$19 \output_stage_logical_op__insn$39 connect \logical_op__insn_type \output_stage_logical_op__insn_type connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 connect \logical_op__invert_in \output_stage_logical_op__invert_in connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 connect \logical_op__invert_out \output_stage_logical_op__invert_out connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 connect \logical_op__is_32bit \output_stage_logical_op__is_32bit connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 connect \logical_op__is_signed \output_stage_logical_op__is_signed connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 connect \logical_op__oe__oe \output_stage_logical_op__oe__oe connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 connect \logical_op__oe__ok \output_stage_logical_op__oe__ok connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 connect \logical_op__output_carry \output_stage_logical_op__output_carry connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 connect \logical_op__rc__ok \output_stage_logical_op__rc__ok connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 connect \logical_op__rc__rc \output_stage_logical_op__rc__rc connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 connect \logical_op__zero_a \output_stage_logical_op__zero_a connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 connect \muxid \output_stage_muxid connect \muxid$1 \output_stage_muxid$21 connect \o \output_stage_o connect \o_ok \output_stage_o_ok connect \quotient_root \output_stage_quotient_root connect \remainder \output_stage_remainder connect \xer_ov \output_stage_xer_ov connect \xer_ov_ok \output_stage_xer_ov_ok connect \xer_so \output_stage_xer_so connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 attribute \src "libresoc.v:173380.10-173383.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:172063.7-172063.20" process $proc$libresoc.v:172063$9894 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:172072.13-172072.24" process $proc$libresoc.v:172072$9895 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end attribute \src "libresoc.v:172081.7-172081.21" process $proc$libresoc.v:172081$9896 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end attribute \src "libresoc.v:172104.13-172104.45" process $proc$libresoc.v:172104$9897 assign { } { } assign $0\logical_op__data_len$18[3:0]$9898 4'0000 sync always sync init update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9898 end attribute \src "libresoc.v:172143.14-172143.48" process $proc$libresoc.v:172143$9899 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$9900 14'00000000000000 sync always sync init update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9900 end attribute \src "libresoc.v:172167.14-172167.67" process $proc$libresoc.v:172167$9901 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$9902 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9902 end attribute \src "libresoc.v:172176.7-172176.42" process $proc$libresoc.v:172176$9903 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$9904 1'0 sync always sync init update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9904 end attribute \src "libresoc.v:172193.13-172193.48" process $proc$libresoc.v:172193$9905 assign { } { } assign $0\logical_op__input_carry$12[1:0]$9906 2'00 sync always sync init update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9906 end attribute \src "libresoc.v:172206.14-172206.43" process $proc$libresoc.v:172206$9907 assign { } { } assign $0\logical_op__insn$19[31:0]$9908 0 sync always sync init update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9908 end attribute \src "libresoc.v:172365.13-172365.46" process $proc$libresoc.v:172365$9909 assign { } { } assign $0\logical_op__insn_type$2[6:0]$9910 7'0000000 sync always sync init update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9910 end attribute \src "libresoc.v:172449.7-172449.40" process $proc$libresoc.v:172449$9911 assign { } { } assign $0\logical_op__invert_in$10[0:0]$9912 1'0 sync always sync init update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9912 end attribute \src "libresoc.v:172458.7-172458.41" process $proc$libresoc.v:172458$9913 assign { } { } assign $0\logical_op__invert_out$13[0:0]$9914 1'0 sync always sync init update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9914 end attribute \src "libresoc.v:172467.7-172467.39" process $proc$libresoc.v:172467$9915 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$9916 1'0 sync always sync init update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9916 end attribute \src "libresoc.v:172476.7-172476.40" process $proc$libresoc.v:172476$9917 assign { } { } assign $0\logical_op__is_signed$17[0:0]$9918 1'0 sync always sync init update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9918 end attribute \src "libresoc.v:172485.7-172485.36" process $proc$libresoc.v:172485$9919 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$9920 1'0 sync always sync init update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9920 end attribute \src "libresoc.v:172496.7-172496.36" process $proc$libresoc.v:172496$9921 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$9922 1'0 sync always sync init update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9922 end attribute \src "libresoc.v:172503.7-172503.43" process $proc$libresoc.v:172503$9923 assign { } { } assign $0\logical_op__output_carry$15[0:0]$9924 1'0 sync always sync init update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9924 end attribute \src "libresoc.v:172512.7-172512.36" process $proc$libresoc.v:172512$9925 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$9926 1'0 sync always sync init update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9926 end attribute \src "libresoc.v:172521.7-172521.36" process $proc$libresoc.v:172521$9927 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$9928 1'0 sync always sync init update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9928 end attribute \src "libresoc.v:172530.7-172530.40" process $proc$libresoc.v:172530$9929 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$9930 1'0 sync always sync init update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9930 end attribute \src "libresoc.v:172539.7-172539.37" process $proc$libresoc.v:172539$9931 assign { } { } assign $0\logical_op__zero_a$11[0:0]$9932 1'0 sync always sync init update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9932 end attribute \src "libresoc.v:172548.13-172548.29" process $proc$libresoc.v:172548$9933 assign { } { } assign $0\muxid$1[1:0]$9934 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9934 end attribute \src "libresoc.v:172561.14-172561.38" process $proc$libresoc.v:172561$9935 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end attribute \src "libresoc.v:172568.7-172568.18" process $proc$libresoc.v:172568$9936 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end attribute \src "libresoc.v:173164.7-173164.20" process $proc$libresoc.v:173164$9937 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:173179.13-173179.26" process $proc$libresoc.v:173179$9938 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end attribute \src "libresoc.v:173186.7-173186.23" process $proc$libresoc.v:173186$9939 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end attribute \src "libresoc.v:173199.7-173199.25" process $proc$libresoc.v:173199$9940 assign { } { } assign $0\xer_so$20[0:0]$9941 1'0 sync always sync init update \xer_so$20 $0\xer_so$20[0:0]$9941 end attribute \src "libresoc.v:173204.7-173204.23" process $proc$libresoc.v:173204$9942 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end attribute \src "libresoc.v:173214.3-173215.37" process $proc$libresoc.v:173214$9772 assign { } { } assign $0\xer_so$20[0:0]$9773 \xer_so$20$next sync posedge \coresync_clk update \xer_so$20 $0\xer_so$20[0:0]$9773 end attribute \src "libresoc.v:173216.3-173217.35" process $proc$libresoc.v:173216$9774 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:173218.3-173219.29" process $proc$libresoc.v:173218$9775 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end attribute \src "libresoc.v:173220.3-173221.35" process $proc$libresoc.v:173220$9776 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end attribute \src "libresoc.v:173222.3-173223.25" process $proc$libresoc.v:173222$9777 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end attribute \src "libresoc.v:173224.3-173225.31" process $proc$libresoc.v:173224$9778 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end attribute \src "libresoc.v:173226.3-173227.19" process $proc$libresoc.v:173226$9779 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end attribute \src "libresoc.v:173228.3-173229.25" process $proc$libresoc.v:173228$9780 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end attribute \src "libresoc.v:173230.3-173231.65" process $proc$libresoc.v:173230$9781 assign { } { } assign $0\logical_op__insn_type$2[6:0]$9782 \logical_op__insn_type$2$next sync posedge \coresync_clk update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9782 end attribute \src "libresoc.v:173232.3-173233.61" process $proc$libresoc.v:173232$9783 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$9784 \logical_op__fn_unit$3$next sync posedge \coresync_clk update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9784 end attribute \src "libresoc.v:173234.3-173235.75" process $proc$libresoc.v:173234$9785 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$9786 \logical_op__imm_data__data$4$next sync posedge \coresync_clk update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9786 end attribute \src "libresoc.v:173236.3-173237.71" process $proc$libresoc.v:173236$9787 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$9788 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9788 end attribute \src "libresoc.v:173238.3-173239.59" process $proc$libresoc.v:173238$9789 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$9790 \logical_op__rc__rc$6$next sync posedge \coresync_clk update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9790 end attribute \src "libresoc.v:173240.3-173241.59" process $proc$libresoc.v:173240$9791 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$9792 \logical_op__rc__ok$7$next sync posedge \coresync_clk update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9792 end attribute \src "libresoc.v:173242.3-173243.59" process $proc$libresoc.v:173242$9793 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$9794 \logical_op__oe__oe$8$next sync posedge \coresync_clk update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9794 end attribute \src "libresoc.v:173244.3-173245.59" process $proc$libresoc.v:173244$9795 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$9796 \logical_op__oe__ok$9$next sync posedge \coresync_clk update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9796 end attribute \src "libresoc.v:173246.3-173247.67" process $proc$libresoc.v:173246$9797 assign { } { } assign $0\logical_op__invert_in$10[0:0]$9798 \logical_op__invert_in$10$next sync posedge \coresync_clk update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9798 end attribute \src "libresoc.v:173248.3-173249.61" process $proc$libresoc.v:173248$9799 assign { } { } assign $0\logical_op__zero_a$11[0:0]$9800 \logical_op__zero_a$11$next sync posedge \coresync_clk update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9800 end attribute \src "libresoc.v:173250.3-173251.71" process $proc$libresoc.v:173250$9801 assign { } { } assign $0\logical_op__input_carry$12[1:0]$9802 \logical_op__input_carry$12$next sync posedge \coresync_clk update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9802 end attribute \src "libresoc.v:173252.3-173253.69" process $proc$libresoc.v:173252$9803 assign { } { } assign $0\logical_op__invert_out$13[0:0]$9804 \logical_op__invert_out$13$next sync posedge \coresync_clk update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9804 end attribute \src "libresoc.v:173254.3-173255.67" process $proc$libresoc.v:173254$9805 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$9806 \logical_op__write_cr0$14$next sync posedge \coresync_clk update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9806 end attribute \src "libresoc.v:173256.3-173257.73" process $proc$libresoc.v:173256$9807 assign { } { } assign $0\logical_op__output_carry$15[0:0]$9808 \logical_op__output_carry$15$next sync posedge \coresync_clk update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9808 end attribute \src "libresoc.v:173258.3-173259.65" process $proc$libresoc.v:173258$9809 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$9810 \logical_op__is_32bit$16$next sync posedge \coresync_clk update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9810 end attribute \src "libresoc.v:173260.3-173261.67" process $proc$libresoc.v:173260$9811 assign { } { } assign $0\logical_op__is_signed$17[0:0]$9812 \logical_op__is_signed$17$next sync posedge \coresync_clk update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9812 end attribute \src "libresoc.v:173262.3-173263.65" process $proc$libresoc.v:173262$9813 assign { } { } assign $0\logical_op__data_len$18[3:0]$9814 \logical_op__data_len$18$next sync posedge \coresync_clk update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9814 end attribute \src "libresoc.v:173264.3-173265.57" process $proc$libresoc.v:173264$9815 assign { } { } assign $0\logical_op__insn$19[31:0]$9816 \logical_op__insn$19$next sync posedge \coresync_clk update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9816 end attribute \src "libresoc.v:173266.3-173267.33" process $proc$libresoc.v:173266$9817 assign { } { } assign $0\muxid$1[1:0]$9818 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9818 end attribute \src "libresoc.v:173268.3-173269.29" process $proc$libresoc.v:173268$9819 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:173384.3-173402.6" process $proc$libresoc.v:173384$9820 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o$next[63:0]$9821 $1\o$next[63:0]$9823 assign { } { } assign $0\o_ok$next[0:0]$9822 $2\o_ok$next[0:0]$9825 attribute \src "libresoc.v:173385.5-173385.29" switch \initial attribute \src "libresoc.v:173385.9-173385.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9824 $1\o$next[63:0]$9823 } { \o_ok$96 \o$95 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\o_ok$next[0:0]$9824 $1\o$next[63:0]$9823 } { \o_ok$96 \o$95 } case assign $1\o$next[63:0]$9823 \o assign $1\o_ok$next[0:0]$9824 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\o_ok$next[0:0]$9825 1'0 case assign $2\o_ok$next[0:0]$9825 $1\o_ok$next[0:0]$9824 end sync always update \o$next $0\o$next[63:0]$9821 update \o_ok$next $0\o_ok$next[0:0]$9822 end attribute \src "libresoc.v:173403.3-173421.6" process $proc$libresoc.v:173403$9826 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a$next[3:0]$9827 $1\cr_a$next[3:0]$9829 assign { } { } assign $0\cr_a_ok$next[0:0]$9828 $2\cr_a_ok$next[0:0]$9831 attribute \src "libresoc.v:173404.5-173404.29" switch \initial attribute \src "libresoc.v:173404.9-173404.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$9830 $1\cr_a$next[3:0]$9829 } { \cr_a_ok$98 \cr_a$97 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\cr_a_ok$next[0:0]$9830 $1\cr_a$next[3:0]$9829 } { \cr_a_ok$98 \cr_a$97 } case assign $1\cr_a$next[3:0]$9829 \cr_a assign $1\cr_a_ok$next[0:0]$9830 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_a_ok$next[0:0]$9831 1'0 case assign $2\cr_a_ok$next[0:0]$9831 $1\cr_a_ok$next[0:0]$9830 end sync always update \cr_a$next $0\cr_a$next[3:0]$9827 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9828 end attribute \src "libresoc.v:173422.3-173440.6" process $proc$libresoc.v:173422$9832 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_ov$next[1:0]$9833 $1\xer_ov$next[1:0]$9835 assign { } { } assign $0\xer_ov_ok$next[0:0]$9834 $2\xer_ov_ok$next[0:0]$9837 attribute \src "libresoc.v:173423.5-173423.29" switch \initial attribute \src "libresoc.v:173423.9-173423.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$9836 $1\xer_ov$next[1:0]$9835 } { \xer_ov_ok$100 \xer_ov$99 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_ov_ok$next[0:0]$9836 $1\xer_ov$next[1:0]$9835 } { \xer_ov_ok$100 \xer_ov$99 } case assign $1\xer_ov$next[1:0]$9835 \xer_ov assign $1\xer_ov_ok$next[0:0]$9836 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_ov_ok$next[0:0]$9837 1'0 case assign $2\xer_ov_ok$next[0:0]$9837 $1\xer_ov_ok$next[0:0]$9836 end sync always update \xer_ov$next $0\xer_ov$next[1:0]$9833 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9834 end attribute \src "libresoc.v:173441.3-173459.6" process $proc$libresoc.v:173441$9838 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xer_so$20$next[0:0]$9840 $1\xer_so$20$next[0:0]$9842 assign $0\xer_so_ok$next[0:0]$9839 $2\xer_so_ok$next[0:0]$9843 attribute \src "libresoc.v:173442.5-173442.29" switch \initial attribute \src "libresoc.v:173442.9-173442.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$9841 $1\xer_so$20$next[0:0]$9842 } { \xer_so_ok$102 \xer_so$101 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { $1\xer_so_ok$next[0:0]$9841 $1\xer_so$20$next[0:0]$9842 } { \xer_so_ok$102 \xer_so$101 } case assign $1\xer_so_ok$next[0:0]$9841 \xer_so_ok assign $1\xer_so$20$next[0:0]$9842 \xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so_ok$next[0:0]$9843 1'0 case assign $2\xer_so_ok$next[0:0]$9843 $1\xer_so_ok$next[0:0]$9841 end sync always update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9839 update \xer_so$20$next $0\xer_so$20$next[0:0]$9840 end attribute \src "libresoc.v:173460.3-173477.6" process $proc$libresoc.v:173460$9844 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9845 $2\r_busy$next[0:0]$9847 attribute \src "libresoc.v:173461.5-173461.29" switch \initial attribute \src "libresoc.v:173461.9-173461.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$9846 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$9846 1'0 case assign $1\r_busy$next[0:0]$9846 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$9847 1'0 case assign $2\r_busy$next[0:0]$9847 $1\r_busy$next[0:0]$9846 end sync always update \r_busy$next $0\r_busy$next[0:0]$9845 end attribute \src "libresoc.v:173478.3-173490.6" process $proc$libresoc.v:173478$9848 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9849 $1\muxid$1$next[1:0]$9850 attribute \src "libresoc.v:173479.5-173479.29" switch \initial attribute \src "libresoc.v:173479.9-173479.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$1$next[1:0]$9850 \muxid$76 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$1$next[1:0]$9850 \muxid$76 case assign $1\muxid$1$next[1:0]$9850 \muxid$1 end sync always update \muxid$1$next $0\muxid$1$next[1:0]$9849 end attribute \src "libresoc.v:173491.3-173532.6" process $proc$libresoc.v:173491$9851 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\logical_op__data_len$18$next[3:0]$9852 $1\logical_op__data_len$18$next[3:0]$9870 assign $0\logical_op__fn_unit$3$next[13:0]$9853 $1\logical_op__fn_unit$3$next[13:0]$9871 assign { } { } assign { } { } assign $0\logical_op__input_carry$12$next[1:0]$9856 $1\logical_op__input_carry$12$next[1:0]$9874 assign $0\logical_op__insn$19$next[31:0]$9857 $1\logical_op__insn$19$next[31:0]$9875 assign $0\logical_op__insn_type$2$next[6:0]$9858 $1\logical_op__insn_type$2$next[6:0]$9876 assign $0\logical_op__invert_in$10$next[0:0]$9859 $1\logical_op__invert_in$10$next[0:0]$9877 assign $0\logical_op__invert_out$13$next[0:0]$9860 $1\logical_op__invert_out$13$next[0:0]$9878 assign $0\logical_op__is_32bit$16$next[0:0]$9861 $1\logical_op__is_32bit$16$next[0:0]$9879 assign $0\logical_op__is_signed$17$next[0:0]$9862 $1\logical_op__is_signed$17$next[0:0]$9880 assign { } { } assign { } { } assign $0\logical_op__output_carry$15$next[0:0]$9865 $1\logical_op__output_carry$15$next[0:0]$9883 assign { } { } assign { } { } assign $0\logical_op__write_cr0$14$next[0:0]$9868 $1\logical_op__write_cr0$14$next[0:0]$9886 assign $0\logical_op__zero_a$11$next[0:0]$9869 $1\logical_op__zero_a$11$next[0:0]$9887 assign $0\logical_op__imm_data__data$4$next[63:0]$9854 $2\logical_op__imm_data__data$4$next[63:0]$9888 assign $0\logical_op__imm_data__ok$5$next[0:0]$9855 $2\logical_op__imm_data__ok$5$next[0:0]$9889 assign $0\logical_op__oe__oe$8$next[0:0]$9863 $2\logical_op__oe__oe$8$next[0:0]$9890 assign $0\logical_op__oe__ok$9$next[0:0]$9864 $2\logical_op__oe__ok$9$next[0:0]$9891 assign $0\logical_op__rc__ok$7$next[0:0]$9866 $2\logical_op__rc__ok$7$next[0:0]$9892 assign $0\logical_op__rc__rc$6$next[0:0]$9867 $2\logical_op__rc__rc$6$next[0:0]$9893 attribute \src "libresoc.v:173492.5-173492.29" switch \initial attribute \src "libresoc.v:173492.9-173492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$19$next[31:0]$9875 $1\logical_op__data_len$18$next[3:0]$9870 $1\logical_op__is_signed$17$next[0:0]$9880 $1\logical_op__is_32bit$16$next[0:0]$9879 $1\logical_op__output_carry$15$next[0:0]$9883 $1\logical_op__write_cr0$14$next[0:0]$9886 $1\logical_op__invert_out$13$next[0:0]$9878 $1\logical_op__input_carry$12$next[1:0]$9874 $1\logical_op__zero_a$11$next[0:0]$9887 $1\logical_op__invert_in$10$next[0:0]$9877 $1\logical_op__oe__ok$9$next[0:0]$9882 $1\logical_op__oe__oe$8$next[0:0]$9881 $1\logical_op__rc__ok$7$next[0:0]$9884 $1\logical_op__rc__rc$6$next[0:0]$9885 $1\logical_op__imm_data__ok$5$next[0:0]$9873 $1\logical_op__imm_data__data$4$next[63:0]$9872 $1\logical_op__fn_unit$3$next[13:0]$9871 $1\logical_op__insn_type$2$next[6:0]$9876 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$19$next[31:0]$9875 $1\logical_op__data_len$18$next[3:0]$9870 $1\logical_op__is_signed$17$next[0:0]$9880 $1\logical_op__is_32bit$16$next[0:0]$9879 $1\logical_op__output_carry$15$next[0:0]$9883 $1\logical_op__write_cr0$14$next[0:0]$9886 $1\logical_op__invert_out$13$next[0:0]$9878 $1\logical_op__input_carry$12$next[1:0]$9874 $1\logical_op__zero_a$11$next[0:0]$9887 $1\logical_op__invert_in$10$next[0:0]$9877 $1\logical_op__oe__ok$9$next[0:0]$9882 $1\logical_op__oe__oe$8$next[0:0]$9881 $1\logical_op__rc__ok$7$next[0:0]$9884 $1\logical_op__rc__rc$6$next[0:0]$9885 $1\logical_op__imm_data__ok$5$next[0:0]$9873 $1\logical_op__imm_data__data$4$next[63:0]$9872 $1\logical_op__fn_unit$3$next[13:0]$9871 $1\logical_op__insn_type$2$next[6:0]$9876 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } case assign $1\logical_op__data_len$18$next[3:0]$9870 \logical_op__data_len$18 assign $1\logical_op__fn_unit$3$next[13:0]$9871 \logical_op__fn_unit$3 assign $1\logical_op__imm_data__data$4$next[63:0]$9872 \logical_op__imm_data__data$4 assign $1\logical_op__imm_data__ok$5$next[0:0]$9873 \logical_op__imm_data__ok$5 assign $1\logical_op__input_carry$12$next[1:0]$9874 \logical_op__input_carry$12 assign $1\logical_op__insn$19$next[31:0]$9875 \logical_op__insn$19 assign $1\logical_op__insn_type$2$next[6:0]$9876 \logical_op__insn_type$2 assign $1\logical_op__invert_in$10$next[0:0]$9877 \logical_op__invert_in$10 assign $1\logical_op__invert_out$13$next[0:0]$9878 \logical_op__invert_out$13 assign $1\logical_op__is_32bit$16$next[0:0]$9879 \logical_op__is_32bit$16 assign $1\logical_op__is_signed$17$next[0:0]$9880 \logical_op__is_signed$17 assign $1\logical_op__oe__oe$8$next[0:0]$9881 \logical_op__oe__oe$8 assign $1\logical_op__oe__ok$9$next[0:0]$9882 \logical_op__oe__ok$9 assign $1\logical_op__output_carry$15$next[0:0]$9883 \logical_op__output_carry$15 assign $1\logical_op__rc__ok$7$next[0:0]$9884 \logical_op__rc__ok$7 assign $1\logical_op__rc__rc$6$next[0:0]$9885 \logical_op__rc__rc$6 assign $1\logical_op__write_cr0$14$next[0:0]$9886 \logical_op__write_cr0$14 assign $1\logical_op__zero_a$11$next[0:0]$9887 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\logical_op__imm_data__data$4$next[63:0]$9888 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\logical_op__imm_data__ok$5$next[0:0]$9889 1'0 assign $2\logical_op__rc__rc$6$next[0:0]$9893 1'0 assign $2\logical_op__rc__ok$7$next[0:0]$9892 1'0 assign $2\logical_op__oe__oe$8$next[0:0]$9890 1'0 assign $2\logical_op__oe__ok$9$next[0:0]$9891 1'0 case assign $2\logical_op__imm_data__data$4$next[63:0]$9888 $1\logical_op__imm_data__data$4$next[63:0]$9872 assign $2\logical_op__imm_data__ok$5$next[0:0]$9889 $1\logical_op__imm_data__ok$5$next[0:0]$9873 assign $2\logical_op__oe__oe$8$next[0:0]$9890 $1\logical_op__oe__oe$8$next[0:0]$9881 assign $2\logical_op__oe__ok$9$next[0:0]$9891 $1\logical_op__oe__ok$9$next[0:0]$9882 assign $2\logical_op__rc__ok$7$next[0:0]$9892 $1\logical_op__rc__ok$7$next[0:0]$9884 assign $2\logical_op__rc__rc$6$next[0:0]$9893 $1\logical_op__rc__rc$6$next[0:0]$9885 end sync always update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9852 update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9853 update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9854 update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9855 update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9856 update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9857 update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9858 update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9859 update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9860 update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9861 update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9862 update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9863 update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9864 update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9865 update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9866 update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9867 update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9868 update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9869 end connect \$74 $and$libresoc.v:173213$9771_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } connect \muxid$76 \output_muxid$41 connect \p_valid_i_p_ready_o \$74 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$73 \p_valid_i connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } connect { \cr_a_ok$67 \output_cr_a } 5'00000 connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } connect \output_muxid \output_stage_muxid$21 connect \output_stage_remainder \remainder connect \output_stage_quotient_root \quotient_root connect \output_stage_div_by_zero \div_by_zero connect \output_stage_dive_abs_ov64 \dive_abs_ov64 connect \output_stage_dive_abs_ov32 \dive_abs_ov32 connect \output_stage_dividend_neg \dividend_neg connect \output_stage_divisor_neg \divisor_neg connect \output_stage_xer_so \xer_so connect \rb$66 \rb connect \ra$65 \ra connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end attribute \src "libresoc.v:173569.1-174556.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 attribute \src "libresoc.v:174481.3-174495.6" wire $0\div_by_zero$54$next[0:0]$10122 attribute \src "libresoc.v:173592.7-173592.30" wire $0\div_by_zero$54[0:0]$10139 attribute \src "libresoc.v:174155.3-174156.47" wire $0\div_by_zero$54[0:0]$9957 attribute \src "libresoc.v:174277.3-174288.6" wire width 64 $0\div_state_next_divisor[63:0] attribute \src "libresoc.v:174265.3-174276.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] attribute \src "libresoc.v:174253.3-174264.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] attribute \src "libresoc.v:174451.3-174465.6" wire $0\dive_abs_ov32$52$next[0:0]$10114 attribute \src "libresoc.v:173616.7-173616.32" wire $0\dive_abs_ov32$52[0:0]$10141 attribute \src "libresoc.v:174159.3-174160.51" wire $0\dive_abs_ov32$52[0:0]$9961 attribute \src "libresoc.v:174466.3-174480.6" wire $0\dive_abs_ov64$53$next[0:0]$10118 attribute \src "libresoc.v:173624.7-173624.32" wire $0\dive_abs_ov64$53[0:0]$10143 attribute \src "libresoc.v:174157.3-174158.51" wire $0\dive_abs_ov64$53[0:0]$9959 attribute \src "libresoc.v:174496.3-174510.6" wire width 128 $0\dividend$68$next[127:0]$10126 attribute \src "libresoc.v:173630.15-173630.68" wire width 128 $0\dividend$68[127:0]$10145 attribute \src "libresoc.v:174153.3-174154.41" wire width 128 $0\dividend$68[127:0]$9955 attribute \src "libresoc.v:174436.3-174450.6" wire $0\dividend_neg$51$next[0:0]$10110 attribute \src "libresoc.v:173638.7-173638.31" wire $0\dividend_neg$51[0:0]$10147 attribute \src "libresoc.v:174161.3-174162.49" wire $0\dividend_neg$51[0:0]$9963 attribute \src "libresoc.v:174421.3-174435.6" wire $0\divisor_neg$50$next[0:0]$10106 attribute \src "libresoc.v:173646.7-173646.30" wire $0\divisor_neg$50[0:0]$10149 attribute \src "libresoc.v:174163.3-174164.47" wire $0\divisor_neg$50[0:0]$9965 attribute \src "libresoc.v:174511.3-174525.6" wire width 64 $0\divisor_radicand$65$next[63:0]$10130 attribute \src "libresoc.v:173652.14-173652.58" wire width 64 $0\divisor_radicand$65[63:0]$10151 attribute \src "libresoc.v:174151.3-174152.57" wire width 64 $0\divisor_radicand$65[63:0]$9953 attribute \src "libresoc.v:174289.3-174316.6" wire $0\empty$next[0:0]$10023 attribute \src "libresoc.v:174209.3-174210.27" wire $0\empty[0:0] attribute \src "libresoc.v:173570.7-173570.20" wire $0\initial[0:0] attribute \src "libresoc.v:174332.3-174375.6" wire width 4 $0\logical_op__data_len$45$next[3:0]$10033 attribute \src "libresoc.v:174203.3-174204.65" wire width 4 $0\logical_op__data_len$45[3:0]$10005 attribute \src "libresoc.v:173664.13-173664.45" wire width 4 $0\logical_op__data_len$45[3:0]$10154 attribute \src "libresoc.v:174332.3-174375.6" wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10034 attribute \src "libresoc.v:173717.14-173717.49" wire width 14 $0\logical_op__fn_unit$30[13:0]$10156 attribute \src "libresoc.v:174173.3-174174.63" wire width 14 $0\logical_op__fn_unit$30[13:0]$9975 attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10035 attribute \src "libresoc.v:173723.14-173723.68" wire width 64 $0\logical_op__imm_data__data$31[63:0]$10158 attribute \src "libresoc.v:174175.3-174176.77" wire width 64 $0\logical_op__imm_data__data$31[63:0]$9977 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__imm_data__ok$32$next[0:0]$10036 attribute \src "libresoc.v:173731.7-173731.43" wire $0\logical_op__imm_data__ok$32[0:0]$10160 attribute \src "libresoc.v:174177.3-174178.73" wire $0\logical_op__imm_data__ok$32[0:0]$9979 attribute \src "libresoc.v:174332.3-174375.6" wire width 2 $0\logical_op__input_carry$39$next[1:0]$10037 attribute \src "libresoc.v:173753.13-173753.48" wire width 2 $0\logical_op__input_carry$39[1:0]$10162 attribute \src "libresoc.v:174191.3-174192.71" wire width 2 $0\logical_op__input_carry$39[1:0]$9993 attribute \src "libresoc.v:174332.3-174375.6" wire width 32 $0\logical_op__insn$46$next[31:0]$10038 attribute \src "libresoc.v:174205.3-174206.57" wire width 32 $0\logical_op__insn$46[31:0]$10007 attribute \src "libresoc.v:173761.14-173761.43" wire width 32 $0\logical_op__insn$46[31:0]$10164 attribute \src "libresoc.v:174332.3-174375.6" wire width 7 $0\logical_op__insn_type$29$next[6:0]$10039 attribute \src "libresoc.v:173994.13-173994.47" wire width 7 $0\logical_op__insn_type$29[6:0]$10166 attribute \src "libresoc.v:174171.3-174172.67" wire width 7 $0\logical_op__insn_type$29[6:0]$9973 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__invert_in$37$next[0:0]$10040 attribute \src "libresoc.v:174002.7-174002.40" wire $0\logical_op__invert_in$37[0:0]$10168 attribute \src "libresoc.v:174187.3-174188.67" wire $0\logical_op__invert_in$37[0:0]$9989 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__invert_out$40$next[0:0]$10041 attribute \src "libresoc.v:174010.7-174010.41" wire $0\logical_op__invert_out$40[0:0]$10170 attribute \src "libresoc.v:174193.3-174194.69" wire $0\logical_op__invert_out$40[0:0]$9995 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__is_32bit$43$next[0:0]$10042 attribute \src "libresoc.v:174199.3-174200.65" wire $0\logical_op__is_32bit$43[0:0]$10001 attribute \src "libresoc.v:174018.7-174018.39" wire $0\logical_op__is_32bit$43[0:0]$10172 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__is_signed$44$next[0:0]$10043 attribute \src "libresoc.v:174201.3-174202.67" wire $0\logical_op__is_signed$44[0:0]$10003 attribute \src "libresoc.v:174026.7-174026.40" wire $0\logical_op__is_signed$44[0:0]$10174 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__oe__oe$35$next[0:0]$10044 attribute \src "libresoc.v:174032.7-174032.37" wire $0\logical_op__oe__oe$35[0:0]$10176 attribute \src "libresoc.v:174183.3-174184.61" wire $0\logical_op__oe__oe$35[0:0]$9985 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__oe__ok$36$next[0:0]$10045 attribute \src "libresoc.v:174040.7-174040.37" wire $0\logical_op__oe__ok$36[0:0]$10178 attribute \src "libresoc.v:174185.3-174186.61" wire $0\logical_op__oe__ok$36[0:0]$9987 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__output_carry$42$next[0:0]$10046 attribute \src "libresoc.v:174050.7-174050.43" wire $0\logical_op__output_carry$42[0:0]$10180 attribute \src "libresoc.v:174197.3-174198.73" wire $0\logical_op__output_carry$42[0:0]$9999 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__rc__ok$34$next[0:0]$10047 attribute \src "libresoc.v:174056.7-174056.37" wire $0\logical_op__rc__ok$34[0:0]$10182 attribute \src "libresoc.v:174181.3-174182.61" wire $0\logical_op__rc__ok$34[0:0]$9983 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__rc__rc$33$next[0:0]$10048 attribute \src "libresoc.v:174064.7-174064.37" wire $0\logical_op__rc__rc$33[0:0]$10184 attribute \src "libresoc.v:174179.3-174180.61" wire $0\logical_op__rc__rc$33[0:0]$9981 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__write_cr0$41$next[0:0]$10049 attribute \src "libresoc.v:174074.7-174074.40" wire $0\logical_op__write_cr0$41[0:0]$10186 attribute \src "libresoc.v:174195.3-174196.67" wire $0\logical_op__write_cr0$41[0:0]$9997 attribute \src "libresoc.v:174332.3-174375.6" wire $0\logical_op__zero_a$38$next[0:0]$10050 attribute \src "libresoc.v:174082.7-174082.37" wire $0\logical_op__zero_a$38[0:0]$10188 attribute \src "libresoc.v:174189.3-174190.61" wire $0\logical_op__zero_a$38[0:0]$9991 attribute \src "libresoc.v:174317.3-174331.6" wire width 2 $0\muxid$28$next[1:0]$10029 attribute \src "libresoc.v:174207.3-174208.35" wire width 2 $0\muxid$28[1:0]$10009 attribute \src "libresoc.v:174090.13-174090.30" wire width 2 $0\muxid$28[1:0]$10190 attribute \src "libresoc.v:174526.3-174540.6" wire width 2 $0\operation$69$next[1:0]$10134 attribute \src "libresoc.v:174100.13-174100.34" wire width 2 $0\operation$69[1:0]$10192 attribute \src "libresoc.v:174149.3-174150.43" wire width 2 $0\operation$69[1:0]$9951 attribute \src "libresoc.v:174376.3-174390.6" wire width 64 $0\ra$47$next[63:0]$10094 attribute \src "libresoc.v:174114.14-174114.44" wire width 64 $0\ra$47[63:0]$10194 attribute \src "libresoc.v:174169.3-174170.29" wire width 64 $0\ra$47[63:0]$9971 attribute \src "libresoc.v:174391.3-174405.6" wire width 64 $0\rb$48$next[63:0]$10098 attribute \src "libresoc.v:174122.14-174122.44" wire width 64 $0\rb$48[63:0]$10196 attribute \src "libresoc.v:174167.3-174168.29" wire width 64 $0\rb$48[63:0]$9969 attribute \src "libresoc.v:174244.3-174252.6" wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10017 attribute \src "libresoc.v:174211.3-174212.75" wire width 128 $0\saved_state_dividend_quotient[127:0] attribute \src "libresoc.v:174235.3-174243.6" wire width 7 $0\saved_state_q_bits_known$next[6:0]$10014 attribute \src "libresoc.v:174213.3-174214.65" wire width 7 $0\saved_state_q_bits_known[6:0] attribute \src "libresoc.v:174406.3-174420.6" wire $0\xer_so$49$next[0:0]$10102 attribute \src "libresoc.v:174140.7-174140.25" wire $0\xer_so$49[0:0]$10200 attribute \src "libresoc.v:174165.3-174166.37" wire $0\xer_so$49[0:0]$9967 attribute \src "libresoc.v:174481.3-174495.6" wire $1\div_by_zero$54$next[0:0]$10123 attribute \src "libresoc.v:174277.3-174288.6" wire width 64 $1\div_state_next_divisor[63:0] attribute \src "libresoc.v:174265.3-174276.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] attribute \src "libresoc.v:174253.3-174264.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] attribute \src "libresoc.v:174451.3-174465.6" wire $1\dive_abs_ov32$52$next[0:0]$10115 attribute \src "libresoc.v:174466.3-174480.6" wire $1\dive_abs_ov64$53$next[0:0]$10119 attribute \src "libresoc.v:174496.3-174510.6" wire width 128 $1\dividend$68$next[127:0]$10127 attribute \src "libresoc.v:174436.3-174450.6" wire $1\dividend_neg$51$next[0:0]$10111 attribute \src "libresoc.v:174421.3-174435.6" wire $1\divisor_neg$50$next[0:0]$10107 attribute \src "libresoc.v:174511.3-174525.6" wire width 64 $1\divisor_radicand$65$next[63:0]$10131 attribute \src "libresoc.v:174289.3-174316.6" wire $1\empty$next[0:0]$10024 attribute \src "libresoc.v:173656.7-173656.19" wire $1\empty[0:0] attribute \src "libresoc.v:174332.3-174375.6" wire width 4 $1\logical_op__data_len$45$next[3:0]$10051 attribute \src "libresoc.v:174332.3-174375.6" wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10052 attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10053 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__imm_data__ok$32$next[0:0]$10054 attribute \src "libresoc.v:174332.3-174375.6" wire width 2 $1\logical_op__input_carry$39$next[1:0]$10055 attribute \src "libresoc.v:174332.3-174375.6" wire width 32 $1\logical_op__insn$46$next[31:0]$10056 attribute \src "libresoc.v:174332.3-174375.6" wire width 7 $1\logical_op__insn_type$29$next[6:0]$10057 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__invert_in$37$next[0:0]$10058 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__invert_out$40$next[0:0]$10059 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__is_32bit$43$next[0:0]$10060 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__is_signed$44$next[0:0]$10061 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__oe__oe$35$next[0:0]$10062 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__oe__ok$36$next[0:0]$10063 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__output_carry$42$next[0:0]$10064 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__rc__ok$34$next[0:0]$10065 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__rc__rc$33$next[0:0]$10066 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__write_cr0$41$next[0:0]$10067 attribute \src "libresoc.v:174332.3-174375.6" wire $1\logical_op__zero_a$38$next[0:0]$10068 attribute \src "libresoc.v:174317.3-174331.6" wire width 2 $1\muxid$28$next[1:0]$10030 attribute \src "libresoc.v:174526.3-174540.6" wire width 2 $1\operation$69$next[1:0]$10135 attribute \src "libresoc.v:174376.3-174390.6" wire width 64 $1\ra$47$next[63:0]$10095 attribute \src "libresoc.v:174391.3-174405.6" wire width 64 $1\rb$48$next[63:0]$10099 attribute \src "libresoc.v:174244.3-174252.6" wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10018 attribute \src "libresoc.v:174128.15-174128.84" wire width 128 $1\saved_state_dividend_quotient[127:0] attribute \src "libresoc.v:174235.3-174243.6" wire width 7 $1\saved_state_q_bits_known$next[6:0]$10015 attribute \src "libresoc.v:174132.13-174132.45" wire width 7 $1\saved_state_q_bits_known[6:0] attribute \src "libresoc.v:174406.3-174420.6" wire $1\xer_so$49$next[0:0]$10103 attribute \src "libresoc.v:174481.3-174495.6" wire $2\div_by_zero$54$next[0:0]$10124 attribute \src "libresoc.v:174451.3-174465.6" wire $2\dive_abs_ov32$52$next[0:0]$10116 attribute \src "libresoc.v:174466.3-174480.6" wire $2\dive_abs_ov64$53$next[0:0]$10120 attribute \src "libresoc.v:174496.3-174510.6" wire width 128 $2\dividend$68$next[127:0]$10128 attribute \src "libresoc.v:174436.3-174450.6" wire $2\dividend_neg$51$next[0:0]$10112 attribute \src "libresoc.v:174421.3-174435.6" wire $2\divisor_neg$50$next[0:0]$10108 attribute \src "libresoc.v:174511.3-174525.6" wire width 64 $2\divisor_radicand$65$next[63:0]$10132 attribute \src "libresoc.v:174289.3-174316.6" wire $2\empty$next[0:0]$10025 attribute \src "libresoc.v:174332.3-174375.6" wire width 4 $2\logical_op__data_len$45$next[3:0]$10069 attribute \src "libresoc.v:174332.3-174375.6" wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10070 attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10071 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__imm_data__ok$32$next[0:0]$10072 attribute \src "libresoc.v:174332.3-174375.6" wire width 2 $2\logical_op__input_carry$39$next[1:0]$10073 attribute \src "libresoc.v:174332.3-174375.6" wire width 32 $2\logical_op__insn$46$next[31:0]$10074 attribute \src "libresoc.v:174332.3-174375.6" wire width 7 $2\logical_op__insn_type$29$next[6:0]$10075 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__invert_in$37$next[0:0]$10076 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__invert_out$40$next[0:0]$10077 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__is_32bit$43$next[0:0]$10078 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__is_signed$44$next[0:0]$10079 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__oe__oe$35$next[0:0]$10080 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__oe__ok$36$next[0:0]$10081 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__output_carry$42$next[0:0]$10082 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__rc__ok$34$next[0:0]$10083 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__rc__rc$33$next[0:0]$10084 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__write_cr0$41$next[0:0]$10085 attribute \src "libresoc.v:174332.3-174375.6" wire $2\logical_op__zero_a$38$next[0:0]$10086 attribute \src "libresoc.v:174317.3-174331.6" wire width 2 $2\muxid$28$next[1:0]$10031 attribute \src "libresoc.v:174526.3-174540.6" wire width 2 $2\operation$69$next[1:0]$10136 attribute \src "libresoc.v:174376.3-174390.6" wire width 64 $2\ra$47$next[63:0]$10096 attribute \src "libresoc.v:174391.3-174405.6" wire width 64 $2\rb$48$next[63:0]$10100 attribute \src "libresoc.v:174406.3-174420.6" wire $2\xer_so$49$next[0:0]$10104 attribute \src "libresoc.v:174289.3-174316.6" wire $3\empty$next[0:0]$10026 attribute \src "libresoc.v:174332.3-174375.6" wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10087 attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__imm_data__ok$32$next[0:0]$10088 attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__oe__oe$35$next[0:0]$10089 attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__oe__ok$36$next[0:0]$10090 attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__rc__ok$34$next[0:0]$10091 attribute \src "libresoc.v:174332.3-174375.6" wire $3\logical_op__rc__rc$33$next[0:0]$10092 attribute \src "libresoc.v:174289.3-174316.6" wire $4\empty$next[0:0]$10027 attribute \src "libresoc.v:174147.18-174147.98" wire $and$libresoc.v:174147$9948_Y attribute \src "libresoc.v:174148.18-174148.107" wire $and$libresoc.v:174148$9949_Y attribute \src "libresoc.v:174144.18-174144.92" wire width 192 $extend$libresoc.v:174144$9944_Y attribute \src "libresoc.v:174146.18-174146.119" wire $ge$libresoc.v:174146$9947_Y attribute \src "libresoc.v:174145.18-174145.93" wire $not$libresoc.v:174145$9946_Y attribute \src "libresoc.v:174144.18-174144.92" wire width 192 $pos$libresoc.v:174144$9945_Y attribute \src "libresoc.v:174143.18-174143.138" wire width 191 $sshl$libresoc.v:174143$9943_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 191 \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 65 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 62 \div_by_zero$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \div_by_zero$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \div_by_zero$54$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" wire width 128 \div_state_init_dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 \div_state_init_o_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 \div_state_init_o_q_bits_known attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" wire width 64 \div_state_next_divisor attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 \div_state_next_i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 \div_state_next_i_q_bits_known attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 \div_state_next_o_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 \div_state_next_o_q_bits_known attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire input 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire output 60 \dive_abs_ov32$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \dive_abs_ov32$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \dive_abs_ov32$52$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire input 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire output 61 \dive_abs_ov64$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \dive_abs_ov64$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \dive_abs_ov64$53$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 input 31 \dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \dividend$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \dividend$68$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire output 59 \dividend_neg$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \dividend_neg$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \dividend_neg$51$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire output 58 \divisor_neg$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \divisor_neg$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \divisor_neg$50$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 input 32 \divisor_radicand attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$65$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next attribute \src "libresoc.v:173570.7-173570.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 53 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$45$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 38 \logical_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$30$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$31$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 39 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$32$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 40 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 15 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 47 \logical_op__input_carry$12 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$39$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 54 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$46$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 37 \logical_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$29$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 45 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$37$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 48 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$40$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 51 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$43$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 52 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$44$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$35$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 43 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$36$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 44 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 50 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$42$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$34$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 42 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$33$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 41 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 49 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$41$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 46 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$38$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 36 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$28$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 35 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 34 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 input 33 \operation attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \operation$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \operation$69$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 output 63 \quotient_root attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 55 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$47$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 56 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$48$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 output 64 \remainder attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 \saved_state_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" wire width 128 \saved_state_dividend_quotient$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 \saved_state_q_bits_known attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 \saved_state_q_bits_known$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 25 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 57 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" cell $and $and$libresoc.v:174147$9948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 connect \Y $and$libresoc.v:174147$9948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" cell $and $and$libresoc.v:174148$9949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o connect \Y $and$libresoc.v:174148$9949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" cell $pos $extend$libresoc.v:174144$9944 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 connect \Y $extend$libresoc.v:174144$9944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" cell $ge $ge$libresoc.v:174146$9947 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 connect \Y $ge$libresoc.v:174146$9947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" cell $not $not$libresoc.v:174145$9946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty connect \Y $not$libresoc.v:174145$9946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" cell $pos $pos$libresoc.v:174144$9945 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 connect \A $extend$libresoc.v:174144$9944_Y connect \Y $pos$libresoc.v:174144$9945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" cell $sshl $sshl$libresoc.v:174143$9943 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 connect \Y $sshl$libresoc.v:174143$9943_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:174215.18-174219.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 attribute \src "libresoc.v:174220.18-174226.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient connect \i_q_bits_known \div_state_next_i_q_bits_known connect \o_dividend_quotient \div_state_next_o_dividend_quotient connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 attribute \src "libresoc.v:174227.10-174230.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:174231.10-174234.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \src "libresoc.v:173570.7-173570.20" process $proc$libresoc.v:173570$10137 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:173592.7-173592.30" process $proc$libresoc.v:173592$10138 assign { } { } assign $0\div_by_zero$54[0:0]$10139 1'0 sync always sync init update \div_by_zero$54 $0\div_by_zero$54[0:0]$10139 end attribute \src "libresoc.v:173616.7-173616.32" process $proc$libresoc.v:173616$10140 assign { } { } assign $0\dive_abs_ov32$52[0:0]$10141 1'0 sync always sync init update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10141 end attribute \src "libresoc.v:173624.7-173624.32" process $proc$libresoc.v:173624$10142 assign { } { } assign $0\dive_abs_ov64$53[0:0]$10143 1'0 sync always sync init update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10143 end attribute \src "libresoc.v:173630.15-173630.68" process $proc$libresoc.v:173630$10144 assign { } { } assign $0\dividend$68[127:0]$10145 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend$68 $0\dividend$68[127:0]$10145 end attribute \src "libresoc.v:173638.7-173638.31" process $proc$libresoc.v:173638$10146 assign { } { } assign $0\dividend_neg$51[0:0]$10147 1'0 sync always sync init update \dividend_neg$51 $0\dividend_neg$51[0:0]$10147 end attribute \src "libresoc.v:173646.7-173646.30" process $proc$libresoc.v:173646$10148 assign { } { } assign $0\divisor_neg$50[0:0]$10149 1'0 sync always sync init update \divisor_neg$50 $0\divisor_neg$50[0:0]$10149 end attribute \src "libresoc.v:173652.14-173652.58" process $proc$libresoc.v:173652$10150 assign { } { } assign $0\divisor_radicand$65[63:0]$10151 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10151 end attribute \src "libresoc.v:173656.7-173656.19" process $proc$libresoc.v:173656$10152 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end attribute \src "libresoc.v:173664.13-173664.45" process $proc$libresoc.v:173664$10153 assign { } { } assign $0\logical_op__data_len$45[3:0]$10154 4'0000 sync always sync init update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10154 end attribute \src "libresoc.v:173717.14-173717.49" process $proc$libresoc.v:173717$10155 assign { } { } assign $0\logical_op__fn_unit$30[13:0]$10156 14'00000000000000 sync always sync init update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10156 end attribute \src "libresoc.v:173723.14-173723.68" process $proc$libresoc.v:173723$10157 assign { } { } assign $0\logical_op__imm_data__data$31[63:0]$10158 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10158 end attribute \src "libresoc.v:173731.7-173731.43" process $proc$libresoc.v:173731$10159 assign { } { } assign $0\logical_op__imm_data__ok$32[0:0]$10160 1'0 sync always sync init update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10160 end attribute \src "libresoc.v:173753.13-173753.48" process $proc$libresoc.v:173753$10161 assign { } { } assign $0\logical_op__input_carry$39[1:0]$10162 2'00 sync always sync init update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10162 end attribute \src "libresoc.v:173761.14-173761.43" process $proc$libresoc.v:173761$10163 assign { } { } assign $0\logical_op__insn$46[31:0]$10164 0 sync always sync init update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10164 end attribute \src "libresoc.v:173994.13-173994.47" process $proc$libresoc.v:173994$10165 assign { } { } assign $0\logical_op__insn_type$29[6:0]$10166 7'0000000 sync always sync init update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10166 end attribute \src "libresoc.v:174002.7-174002.40" process $proc$libresoc.v:174002$10167 assign { } { } assign $0\logical_op__invert_in$37[0:0]$10168 1'0 sync always sync init update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10168 end attribute \src "libresoc.v:174010.7-174010.41" process $proc$libresoc.v:174010$10169 assign { } { } assign $0\logical_op__invert_out$40[0:0]$10170 1'0 sync always sync init update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10170 end attribute \src "libresoc.v:174018.7-174018.39" process $proc$libresoc.v:174018$10171 assign { } { } assign $0\logical_op__is_32bit$43[0:0]$10172 1'0 sync always sync init update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10172 end attribute \src "libresoc.v:174026.7-174026.40" process $proc$libresoc.v:174026$10173 assign { } { } assign $0\logical_op__is_signed$44[0:0]$10174 1'0 sync always sync init update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10174 end attribute \src "libresoc.v:174032.7-174032.37" process $proc$libresoc.v:174032$10175 assign { } { } assign $0\logical_op__oe__oe$35[0:0]$10176 1'0 sync always sync init update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10176 end attribute \src "libresoc.v:174040.7-174040.37" process $proc$libresoc.v:174040$10177 assign { } { } assign $0\logical_op__oe__ok$36[0:0]$10178 1'0 sync always sync init update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10178 end attribute \src "libresoc.v:174050.7-174050.43" process $proc$libresoc.v:174050$10179 assign { } { } assign $0\logical_op__output_carry$42[0:0]$10180 1'0 sync always sync init update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10180 end attribute \src "libresoc.v:174056.7-174056.37" process $proc$libresoc.v:174056$10181 assign { } { } assign $0\logical_op__rc__ok$34[0:0]$10182 1'0 sync always sync init update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10182 end attribute \src "libresoc.v:174064.7-174064.37" process $proc$libresoc.v:174064$10183 assign { } { } assign $0\logical_op__rc__rc$33[0:0]$10184 1'0 sync always sync init update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10184 end attribute \src "libresoc.v:174074.7-174074.40" process $proc$libresoc.v:174074$10185 assign { } { } assign $0\logical_op__write_cr0$41[0:0]$10186 1'0 sync always sync init update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10186 end attribute \src "libresoc.v:174082.7-174082.37" process $proc$libresoc.v:174082$10187 assign { } { } assign $0\logical_op__zero_a$38[0:0]$10188 1'0 sync always sync init update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10188 end attribute \src "libresoc.v:174090.13-174090.30" process $proc$libresoc.v:174090$10189 assign { } { } assign $0\muxid$28[1:0]$10190 2'00 sync always sync init update \muxid$28 $0\muxid$28[1:0]$10190 end attribute \src "libresoc.v:174100.13-174100.34" process $proc$libresoc.v:174100$10191 assign { } { } assign $0\operation$69[1:0]$10192 2'00 sync always sync init update \operation$69 $0\operation$69[1:0]$10192 end attribute \src "libresoc.v:174114.14-174114.44" process $proc$libresoc.v:174114$10193 assign { } { } assign $0\ra$47[63:0]$10194 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra$47 $0\ra$47[63:0]$10194 end attribute \src "libresoc.v:174122.14-174122.44" process $proc$libresoc.v:174122$10195 assign { } { } assign $0\rb$48[63:0]$10196 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb$48 $0\rb$48[63:0]$10196 end attribute \src "libresoc.v:174128.15-174128.84" process $proc$libresoc.v:174128$10197 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end attribute \src "libresoc.v:174132.13-174132.45" process $proc$libresoc.v:174132$10198 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end attribute \src "libresoc.v:174140.7-174140.25" process $proc$libresoc.v:174140$10199 assign { } { } assign $0\xer_so$49[0:0]$10200 1'0 sync always sync init update \xer_so$49 $0\xer_so$49[0:0]$10200 end attribute \src "libresoc.v:174149.3-174150.43" process $proc$libresoc.v:174149$9950 assign { } { } assign $0\operation$69[1:0]$9951 \operation$69$next sync posedge \coresync_clk update \operation$69 $0\operation$69[1:0]$9951 end attribute \src "libresoc.v:174151.3-174152.57" process $proc$libresoc.v:174151$9952 assign { } { } assign $0\divisor_radicand$65[63:0]$9953 \divisor_radicand$65$next sync posedge \coresync_clk update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9953 end attribute \src "libresoc.v:174153.3-174154.41" process $proc$libresoc.v:174153$9954 assign { } { } assign $0\dividend$68[127:0]$9955 \dividend$68$next sync posedge \coresync_clk update \dividend$68 $0\dividend$68[127:0]$9955 end attribute \src "libresoc.v:174155.3-174156.47" process $proc$libresoc.v:174155$9956 assign { } { } assign $0\div_by_zero$54[0:0]$9957 \div_by_zero$54$next sync posedge \coresync_clk update \div_by_zero$54 $0\div_by_zero$54[0:0]$9957 end attribute \src "libresoc.v:174157.3-174158.51" process $proc$libresoc.v:174157$9958 assign { } { } assign $0\dive_abs_ov64$53[0:0]$9959 \dive_abs_ov64$53$next sync posedge \coresync_clk update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9959 end attribute \src "libresoc.v:174159.3-174160.51" process $proc$libresoc.v:174159$9960 assign { } { } assign $0\dive_abs_ov32$52[0:0]$9961 \dive_abs_ov32$52$next sync posedge \coresync_clk update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9961 end attribute \src "libresoc.v:174161.3-174162.49" process $proc$libresoc.v:174161$9962 assign { } { } assign $0\dividend_neg$51[0:0]$9963 \dividend_neg$51$next sync posedge \coresync_clk update \dividend_neg$51 $0\dividend_neg$51[0:0]$9963 end attribute \src "libresoc.v:174163.3-174164.47" process $proc$libresoc.v:174163$9964 assign { } { } assign $0\divisor_neg$50[0:0]$9965 \divisor_neg$50$next sync posedge \coresync_clk update \divisor_neg$50 $0\divisor_neg$50[0:0]$9965 end attribute \src "libresoc.v:174165.3-174166.37" process $proc$libresoc.v:174165$9966 assign { } { } assign $0\xer_so$49[0:0]$9967 \xer_so$49$next sync posedge \coresync_clk update \xer_so$49 $0\xer_so$49[0:0]$9967 end attribute \src "libresoc.v:174167.3-174168.29" process $proc$libresoc.v:174167$9968 assign { } { } assign $0\rb$48[63:0]$9969 \rb$48$next sync posedge \coresync_clk update \rb$48 $0\rb$48[63:0]$9969 end attribute \src "libresoc.v:174169.3-174170.29" process $proc$libresoc.v:174169$9970 assign { } { } assign $0\ra$47[63:0]$9971 \ra$47$next sync posedge \coresync_clk update \ra$47 $0\ra$47[63:0]$9971 end attribute \src "libresoc.v:174171.3-174172.67" process $proc$libresoc.v:174171$9972 assign { } { } assign $0\logical_op__insn_type$29[6:0]$9973 \logical_op__insn_type$29$next sync posedge \coresync_clk update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9973 end attribute \src "libresoc.v:174173.3-174174.63" process $proc$libresoc.v:174173$9974 assign { } { } assign $0\logical_op__fn_unit$30[13:0]$9975 \logical_op__fn_unit$30$next sync posedge \coresync_clk update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$9975 end attribute \src "libresoc.v:174175.3-174176.77" process $proc$libresoc.v:174175$9976 assign { } { } assign $0\logical_op__imm_data__data$31[63:0]$9977 \logical_op__imm_data__data$31$next sync posedge \coresync_clk update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9977 end attribute \src "libresoc.v:174177.3-174178.73" process $proc$libresoc.v:174177$9978 assign { } { } assign $0\logical_op__imm_data__ok$32[0:0]$9979 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9979 end attribute \src "libresoc.v:174179.3-174180.61" process $proc$libresoc.v:174179$9980 assign { } { } assign $0\logical_op__rc__rc$33[0:0]$9981 \logical_op__rc__rc$33$next sync posedge \coresync_clk update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9981 end attribute \src "libresoc.v:174181.3-174182.61" process $proc$libresoc.v:174181$9982 assign { } { } assign $0\logical_op__rc__ok$34[0:0]$9983 \logical_op__rc__ok$34$next sync posedge \coresync_clk update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9983 end attribute \src "libresoc.v:174183.3-174184.61" process $proc$libresoc.v:174183$9984 assign { } { } assign $0\logical_op__oe__oe$35[0:0]$9985 \logical_op__oe__oe$35$next sync posedge \coresync_clk update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9985 end attribute \src "libresoc.v:174185.3-174186.61" process $proc$libresoc.v:174185$9986 assign { } { } assign $0\logical_op__oe__ok$36[0:0]$9987 \logical_op__oe__ok$36$next sync posedge \coresync_clk update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9987 end attribute \src "libresoc.v:174187.3-174188.67" process $proc$libresoc.v:174187$9988 assign { } { } assign $0\logical_op__invert_in$37[0:0]$9989 \logical_op__invert_in$37$next sync posedge \coresync_clk update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9989 end attribute \src "libresoc.v:174189.3-174190.61" process $proc$libresoc.v:174189$9990 assign { } { } assign $0\logical_op__zero_a$38[0:0]$9991 \logical_op__zero_a$38$next sync posedge \coresync_clk update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9991 end attribute \src "libresoc.v:174191.3-174192.71" process $proc$libresoc.v:174191$9992 assign { } { } assign $0\logical_op__input_carry$39[1:0]$9993 \logical_op__input_carry$39$next sync posedge \coresync_clk update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9993 end attribute \src "libresoc.v:174193.3-174194.69" process $proc$libresoc.v:174193$9994 assign { } { } assign $0\logical_op__invert_out$40[0:0]$9995 \logical_op__invert_out$40$next sync posedge \coresync_clk update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9995 end attribute \src "libresoc.v:174195.3-174196.67" process $proc$libresoc.v:174195$9996 assign { } { } assign $0\logical_op__write_cr0$41[0:0]$9997 \logical_op__write_cr0$41$next sync posedge \coresync_clk update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9997 end attribute \src "libresoc.v:174197.3-174198.73" process $proc$libresoc.v:174197$9998 assign { } { } assign $0\logical_op__output_carry$42[0:0]$9999 \logical_op__output_carry$42$next sync posedge \coresync_clk update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9999 end attribute \src "libresoc.v:174199.3-174200.65" process $proc$libresoc.v:174199$10000 assign { } { } assign $0\logical_op__is_32bit$43[0:0]$10001 \logical_op__is_32bit$43$next sync posedge \coresync_clk update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10001 end attribute \src "libresoc.v:174201.3-174202.67" process $proc$libresoc.v:174201$10002 assign { } { } assign $0\logical_op__is_signed$44[0:0]$10003 \logical_op__is_signed$44$next sync posedge \coresync_clk update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10003 end attribute \src "libresoc.v:174203.3-174204.65" process $proc$libresoc.v:174203$10004 assign { } { } assign $0\logical_op__data_len$45[3:0]$10005 \logical_op__data_len$45$next sync posedge \coresync_clk update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10005 end attribute \src "libresoc.v:174205.3-174206.57" process $proc$libresoc.v:174205$10006 assign { } { } assign $0\logical_op__insn$46[31:0]$10007 \logical_op__insn$46$next sync posedge \coresync_clk update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10007 end attribute \src "libresoc.v:174207.3-174208.35" process $proc$libresoc.v:174207$10008 assign { } { } assign $0\muxid$28[1:0]$10009 \muxid$28$next sync posedge \coresync_clk update \muxid$28 $0\muxid$28[1:0]$10009 end attribute \src "libresoc.v:174209.3-174210.27" process $proc$libresoc.v:174209$10010 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end attribute \src "libresoc.v:174211.3-174212.75" process $proc$libresoc.v:174211$10011 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end attribute \src "libresoc.v:174213.3-174214.65" process $proc$libresoc.v:174213$10012 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end attribute \src "libresoc.v:174235.3-174243.6" process $proc$libresoc.v:174235$10013 assign { } { } assign { } { } assign $0\saved_state_q_bits_known$next[6:0]$10014 $1\saved_state_q_bits_known$next[6:0]$10015 attribute \src "libresoc.v:174236.5-174236.29" switch \initial attribute \src "libresoc.v:174236.9-174236.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\saved_state_q_bits_known$next[6:0]$10015 7'0000000 case assign $1\saved_state_q_bits_known$next[6:0]$10015 \div_state_next_o_q_bits_known end sync always update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10014 end attribute \src "libresoc.v:174244.3-174252.6" process $proc$libresoc.v:174244$10016 assign { } { } assign { } { } assign $0\saved_state_dividend_quotient$next[127:0]$10017 $1\saved_state_dividend_quotient$next[127:0]$10018 attribute \src "libresoc.v:174245.5-174245.29" switch \initial attribute \src "libresoc.v:174245.9-174245.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\saved_state_dividend_quotient$next[127:0]$10018 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case assign $1\saved_state_dividend_quotient$next[127:0]$10018 \div_state_next_o_dividend_quotient end sync always update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10017 end attribute \src "libresoc.v:174253.3-174264.6" process $proc$libresoc.v:174253$10019 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] attribute \src "libresoc.v:174254.5-174254.29" switch \initial attribute \src "libresoc.v:174254.9-174254.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known end sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end attribute \src "libresoc.v:174265.3-174276.6" process $proc$libresoc.v:174265$10020 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] attribute \src "libresoc.v:174266.5-174266.29" switch \initial attribute \src "libresoc.v:174266.9-174266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient end sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end attribute \src "libresoc.v:174277.3-174288.6" process $proc$libresoc.v:174277$10021 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] attribute \src "libresoc.v:174278.5-174278.29" switch \initial attribute \src "libresoc.v:174278.9-174278.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\div_state_next_divisor[63:0] \divisor_radicand attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 end sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end attribute \src "libresoc.v:174289.3-174316.6" process $proc$libresoc.v:174289$10022 assign { } { } assign { } { } assign { } { } assign $0\empty$next[0:0]$10023 $4\empty$next[0:0]$10027 attribute \src "libresoc.v:174290.5-174290.29" switch \initial attribute \src "libresoc.v:174290.9-174290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\empty$next[0:0]$10024 $2\empty$next[0:0]$10025 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\empty$next[0:0]$10025 1'0 case assign $2\empty$next[0:0]$10025 \empty end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\empty$next[0:0]$10024 $3\empty$next[0:0]$10026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch \$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\empty$next[0:0]$10026 1'1 case assign $3\empty$next[0:0]$10026 \empty end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\empty$next[0:0]$10027 1'1 case assign $4\empty$next[0:0]$10027 $1\empty$next[0:0]$10024 end sync always update \empty$next $0\empty$next[0:0]$10023 end attribute \src "libresoc.v:174317.3-174331.6" process $proc$libresoc.v:174317$10028 assign { } { } assign { } { } assign $0\muxid$28$next[1:0]$10029 $1\muxid$28$next[1:0]$10030 attribute \src "libresoc.v:174318.5-174318.29" switch \initial attribute \src "libresoc.v:174318.9-174318.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\muxid$28$next[1:0]$10030 $2\muxid$28$next[1:0]$10031 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\muxid$28$next[1:0]$10031 \muxid case assign $2\muxid$28$next[1:0]$10031 \muxid$28 end case assign $1\muxid$28$next[1:0]$10030 \muxid$28 end sync always update \muxid$28$next $0\muxid$28$next[1:0]$10029 end attribute \src "libresoc.v:174332.3-174375.6" process $proc$libresoc.v:174332$10032 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\logical_op__data_len$45$next[3:0]$10033 $1\logical_op__data_len$45$next[3:0]$10051 assign $0\logical_op__fn_unit$30$next[13:0]$10034 $1\logical_op__fn_unit$30$next[13:0]$10052 assign { } { } assign { } { } assign $0\logical_op__input_carry$39$next[1:0]$10037 $1\logical_op__input_carry$39$next[1:0]$10055 assign $0\logical_op__insn$46$next[31:0]$10038 $1\logical_op__insn$46$next[31:0]$10056 assign $0\logical_op__insn_type$29$next[6:0]$10039 $1\logical_op__insn_type$29$next[6:0]$10057 assign $0\logical_op__invert_in$37$next[0:0]$10040 $1\logical_op__invert_in$37$next[0:0]$10058 assign $0\logical_op__invert_out$40$next[0:0]$10041 $1\logical_op__invert_out$40$next[0:0]$10059 assign $0\logical_op__is_32bit$43$next[0:0]$10042 $1\logical_op__is_32bit$43$next[0:0]$10060 assign $0\logical_op__is_signed$44$next[0:0]$10043 $1\logical_op__is_signed$44$next[0:0]$10061 assign { } { } assign { } { } assign $0\logical_op__output_carry$42$next[0:0]$10046 $1\logical_op__output_carry$42$next[0:0]$10064 assign { } { } assign { } { } assign $0\logical_op__write_cr0$41$next[0:0]$10049 $1\logical_op__write_cr0$41$next[0:0]$10067 assign $0\logical_op__zero_a$38$next[0:0]$10050 $1\logical_op__zero_a$38$next[0:0]$10068 assign $0\logical_op__imm_data__data$31$next[63:0]$10035 $3\logical_op__imm_data__data$31$next[63:0]$10087 assign $0\logical_op__imm_data__ok$32$next[0:0]$10036 $3\logical_op__imm_data__ok$32$next[0:0]$10088 assign $0\logical_op__oe__oe$35$next[0:0]$10044 $3\logical_op__oe__oe$35$next[0:0]$10089 assign $0\logical_op__oe__ok$36$next[0:0]$10045 $3\logical_op__oe__ok$36$next[0:0]$10090 assign $0\logical_op__rc__ok$34$next[0:0]$10047 $3\logical_op__rc__ok$34$next[0:0]$10091 assign $0\logical_op__rc__rc$33$next[0:0]$10048 $3\logical_op__rc__rc$33$next[0:0]$10092 attribute \src "libresoc.v:174333.5-174333.29" switch \initial attribute \src "libresoc.v:174333.9-174333.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\logical_op__data_len$45$next[3:0]$10051 $2\logical_op__data_len$45$next[3:0]$10069 assign $1\logical_op__fn_unit$30$next[13:0]$10052 $2\logical_op__fn_unit$30$next[13:0]$10070 assign $1\logical_op__imm_data__data$31$next[63:0]$10053 $2\logical_op__imm_data__data$31$next[63:0]$10071 assign $1\logical_op__imm_data__ok$32$next[0:0]$10054 $2\logical_op__imm_data__ok$32$next[0:0]$10072 assign $1\logical_op__input_carry$39$next[1:0]$10055 $2\logical_op__input_carry$39$next[1:0]$10073 assign $1\logical_op__insn$46$next[31:0]$10056 $2\logical_op__insn$46$next[31:0]$10074 assign $1\logical_op__insn_type$29$next[6:0]$10057 $2\logical_op__insn_type$29$next[6:0]$10075 assign $1\logical_op__invert_in$37$next[0:0]$10058 $2\logical_op__invert_in$37$next[0:0]$10076 assign $1\logical_op__invert_out$40$next[0:0]$10059 $2\logical_op__invert_out$40$next[0:0]$10077 assign $1\logical_op__is_32bit$43$next[0:0]$10060 $2\logical_op__is_32bit$43$next[0:0]$10078 assign $1\logical_op__is_signed$44$next[0:0]$10061 $2\logical_op__is_signed$44$next[0:0]$10079 assign $1\logical_op__oe__oe$35$next[0:0]$10062 $2\logical_op__oe__oe$35$next[0:0]$10080 assign $1\logical_op__oe__ok$36$next[0:0]$10063 $2\logical_op__oe__ok$36$next[0:0]$10081 assign $1\logical_op__output_carry$42$next[0:0]$10064 $2\logical_op__output_carry$42$next[0:0]$10082 assign $1\logical_op__rc__ok$34$next[0:0]$10065 $2\logical_op__rc__ok$34$next[0:0]$10083 assign $1\logical_op__rc__rc$33$next[0:0]$10066 $2\logical_op__rc__rc$33$next[0:0]$10084 assign $1\logical_op__write_cr0$41$next[0:0]$10067 $2\logical_op__write_cr0$41$next[0:0]$10085 assign $1\logical_op__zero_a$38$next[0:0]$10068 $2\logical_op__zero_a$38$next[0:0]$10086 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $2\logical_op__insn$46$next[31:0]$10074 $2\logical_op__data_len$45$next[3:0]$10069 $2\logical_op__is_signed$44$next[0:0]$10079 $2\logical_op__is_32bit$43$next[0:0]$10078 $2\logical_op__output_carry$42$next[0:0]$10082 $2\logical_op__write_cr0$41$next[0:0]$10085 $2\logical_op__invert_out$40$next[0:0]$10077 $2\logical_op__input_carry$39$next[1:0]$10073 $2\logical_op__zero_a$38$next[0:0]$10086 $2\logical_op__invert_in$37$next[0:0]$10076 $2\logical_op__oe__ok$36$next[0:0]$10081 $2\logical_op__oe__oe$35$next[0:0]$10080 $2\logical_op__rc__ok$34$next[0:0]$10083 $2\logical_op__rc__rc$33$next[0:0]$10084 $2\logical_op__imm_data__ok$32$next[0:0]$10072 $2\logical_op__imm_data__data$31$next[63:0]$10071 $2\logical_op__fn_unit$30$next[13:0]$10070 $2\logical_op__insn_type$29$next[6:0]$10075 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } case assign $2\logical_op__data_len$45$next[3:0]$10069 \logical_op__data_len$45 assign $2\logical_op__fn_unit$30$next[13:0]$10070 \logical_op__fn_unit$30 assign $2\logical_op__imm_data__data$31$next[63:0]$10071 \logical_op__imm_data__data$31 assign $2\logical_op__imm_data__ok$32$next[0:0]$10072 \logical_op__imm_data__ok$32 assign $2\logical_op__input_carry$39$next[1:0]$10073 \logical_op__input_carry$39 assign $2\logical_op__insn$46$next[31:0]$10074 \logical_op__insn$46 assign $2\logical_op__insn_type$29$next[6:0]$10075 \logical_op__insn_type$29 assign $2\logical_op__invert_in$37$next[0:0]$10076 \logical_op__invert_in$37 assign $2\logical_op__invert_out$40$next[0:0]$10077 \logical_op__invert_out$40 assign $2\logical_op__is_32bit$43$next[0:0]$10078 \logical_op__is_32bit$43 assign $2\logical_op__is_signed$44$next[0:0]$10079 \logical_op__is_signed$44 assign $2\logical_op__oe__oe$35$next[0:0]$10080 \logical_op__oe__oe$35 assign $2\logical_op__oe__ok$36$next[0:0]$10081 \logical_op__oe__ok$36 assign $2\logical_op__output_carry$42$next[0:0]$10082 \logical_op__output_carry$42 assign $2\logical_op__rc__ok$34$next[0:0]$10083 \logical_op__rc__ok$34 assign $2\logical_op__rc__rc$33$next[0:0]$10084 \logical_op__rc__rc$33 assign $2\logical_op__write_cr0$41$next[0:0]$10085 \logical_op__write_cr0$41 assign $2\logical_op__zero_a$38$next[0:0]$10086 \logical_op__zero_a$38 end case assign $1\logical_op__data_len$45$next[3:0]$10051 \logical_op__data_len$45 assign $1\logical_op__fn_unit$30$next[13:0]$10052 \logical_op__fn_unit$30 assign $1\logical_op__imm_data__data$31$next[63:0]$10053 \logical_op__imm_data__data$31 assign $1\logical_op__imm_data__ok$32$next[0:0]$10054 \logical_op__imm_data__ok$32 assign $1\logical_op__input_carry$39$next[1:0]$10055 \logical_op__input_carry$39 assign $1\logical_op__insn$46$next[31:0]$10056 \logical_op__insn$46 assign $1\logical_op__insn_type$29$next[6:0]$10057 \logical_op__insn_type$29 assign $1\logical_op__invert_in$37$next[0:0]$10058 \logical_op__invert_in$37 assign $1\logical_op__invert_out$40$next[0:0]$10059 \logical_op__invert_out$40 assign $1\logical_op__is_32bit$43$next[0:0]$10060 \logical_op__is_32bit$43 assign $1\logical_op__is_signed$44$next[0:0]$10061 \logical_op__is_signed$44 assign $1\logical_op__oe__oe$35$next[0:0]$10062 \logical_op__oe__oe$35 assign $1\logical_op__oe__ok$36$next[0:0]$10063 \logical_op__oe__ok$36 assign $1\logical_op__output_carry$42$next[0:0]$10064 \logical_op__output_carry$42 assign $1\logical_op__rc__ok$34$next[0:0]$10065 \logical_op__rc__ok$34 assign $1\logical_op__rc__rc$33$next[0:0]$10066 \logical_op__rc__rc$33 assign $1\logical_op__write_cr0$41$next[0:0]$10067 \logical_op__write_cr0$41 assign $1\logical_op__zero_a$38$next[0:0]$10068 \logical_op__zero_a$38 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $3\logical_op__imm_data__data$31$next[63:0]$10087 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\logical_op__imm_data__ok$32$next[0:0]$10088 1'0 assign $3\logical_op__rc__rc$33$next[0:0]$10092 1'0 assign $3\logical_op__rc__ok$34$next[0:0]$10091 1'0 assign $3\logical_op__oe__oe$35$next[0:0]$10089 1'0 assign $3\logical_op__oe__ok$36$next[0:0]$10090 1'0 case assign $3\logical_op__imm_data__data$31$next[63:0]$10087 $1\logical_op__imm_data__data$31$next[63:0]$10053 assign $3\logical_op__imm_data__ok$32$next[0:0]$10088 $1\logical_op__imm_data__ok$32$next[0:0]$10054 assign $3\logical_op__oe__oe$35$next[0:0]$10089 $1\logical_op__oe__oe$35$next[0:0]$10062 assign $3\logical_op__oe__ok$36$next[0:0]$10090 $1\logical_op__oe__ok$36$next[0:0]$10063 assign $3\logical_op__rc__ok$34$next[0:0]$10091 $1\logical_op__rc__ok$34$next[0:0]$10065 assign $3\logical_op__rc__rc$33$next[0:0]$10092 $1\logical_op__rc__rc$33$next[0:0]$10066 end sync always update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10033 update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10034 update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10035 update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10036 update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10037 update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10038 update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10039 update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10040 update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10041 update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10042 update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10043 update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10044 update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10045 update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10046 update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10047 update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10048 update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10049 update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10050 end attribute \src "libresoc.v:174376.3-174390.6" process $proc$libresoc.v:174376$10093 assign { } { } assign { } { } assign $0\ra$47$next[63:0]$10094 $1\ra$47$next[63:0]$10095 attribute \src "libresoc.v:174377.5-174377.29" switch \initial attribute \src "libresoc.v:174377.9-174377.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ra$47$next[63:0]$10095 $2\ra$47$next[63:0]$10096 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ra$47$next[63:0]$10096 \ra case assign $2\ra$47$next[63:0]$10096 \ra$47 end case assign $1\ra$47$next[63:0]$10095 \ra$47 end sync always update \ra$47$next $0\ra$47$next[63:0]$10094 end attribute \src "libresoc.v:174391.3-174405.6" process $proc$libresoc.v:174391$10097 assign { } { } assign { } { } assign $0\rb$48$next[63:0]$10098 $1\rb$48$next[63:0]$10099 attribute \src "libresoc.v:174392.5-174392.29" switch \initial attribute \src "libresoc.v:174392.9-174392.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rb$48$next[63:0]$10099 $2\rb$48$next[63:0]$10100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\rb$48$next[63:0]$10100 \rb case assign $2\rb$48$next[63:0]$10100 \rb$48 end case assign $1\rb$48$next[63:0]$10099 \rb$48 end sync always update \rb$48$next $0\rb$48$next[63:0]$10098 end attribute \src "libresoc.v:174406.3-174420.6" process $proc$libresoc.v:174406$10101 assign { } { } assign { } { } assign $0\xer_so$49$next[0:0]$10102 $1\xer_so$49$next[0:0]$10103 attribute \src "libresoc.v:174407.5-174407.29" switch \initial attribute \src "libresoc.v:174407.9-174407.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xer_so$49$next[0:0]$10103 $2\xer_so$49$next[0:0]$10104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xer_so$49$next[0:0]$10104 \xer_so case assign $2\xer_so$49$next[0:0]$10104 \xer_so$49 end case assign $1\xer_so$49$next[0:0]$10103 \xer_so$49 end sync always update \xer_so$49$next $0\xer_so$49$next[0:0]$10102 end attribute \src "libresoc.v:174421.3-174435.6" process $proc$libresoc.v:174421$10105 assign { } { } assign { } { } assign $0\divisor_neg$50$next[0:0]$10106 $1\divisor_neg$50$next[0:0]$10107 attribute \src "libresoc.v:174422.5-174422.29" switch \initial attribute \src "libresoc.v:174422.9-174422.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\divisor_neg$50$next[0:0]$10107 $2\divisor_neg$50$next[0:0]$10108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\divisor_neg$50$next[0:0]$10108 \divisor_neg case assign $2\divisor_neg$50$next[0:0]$10108 \divisor_neg$50 end case assign $1\divisor_neg$50$next[0:0]$10107 \divisor_neg$50 end sync always update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10106 end attribute \src "libresoc.v:174436.3-174450.6" process $proc$libresoc.v:174436$10109 assign { } { } assign { } { } assign $0\dividend_neg$51$next[0:0]$10110 $1\dividend_neg$51$next[0:0]$10111 attribute \src "libresoc.v:174437.5-174437.29" switch \initial attribute \src "libresoc.v:174437.9-174437.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dividend_neg$51$next[0:0]$10111 $2\dividend_neg$51$next[0:0]$10112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dividend_neg$51$next[0:0]$10112 \dividend_neg case assign $2\dividend_neg$51$next[0:0]$10112 \dividend_neg$51 end case assign $1\dividend_neg$51$next[0:0]$10111 \dividend_neg$51 end sync always update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10110 end attribute \src "libresoc.v:174451.3-174465.6" process $proc$libresoc.v:174451$10113 assign { } { } assign { } { } assign $0\dive_abs_ov32$52$next[0:0]$10114 $1\dive_abs_ov32$52$next[0:0]$10115 attribute \src "libresoc.v:174452.5-174452.29" switch \initial attribute \src "libresoc.v:174452.9-174452.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dive_abs_ov32$52$next[0:0]$10115 $2\dive_abs_ov32$52$next[0:0]$10116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dive_abs_ov32$52$next[0:0]$10116 \dive_abs_ov32 case assign $2\dive_abs_ov32$52$next[0:0]$10116 \dive_abs_ov32$52 end case assign $1\dive_abs_ov32$52$next[0:0]$10115 \dive_abs_ov32$52 end sync always update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10114 end attribute \src "libresoc.v:174466.3-174480.6" process $proc$libresoc.v:174466$10117 assign { } { } assign { } { } assign $0\dive_abs_ov64$53$next[0:0]$10118 $1\dive_abs_ov64$53$next[0:0]$10119 attribute \src "libresoc.v:174467.5-174467.29" switch \initial attribute \src "libresoc.v:174467.9-174467.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dive_abs_ov64$53$next[0:0]$10119 $2\dive_abs_ov64$53$next[0:0]$10120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dive_abs_ov64$53$next[0:0]$10120 \dive_abs_ov64 case assign $2\dive_abs_ov64$53$next[0:0]$10120 \dive_abs_ov64$53 end case assign $1\dive_abs_ov64$53$next[0:0]$10119 \dive_abs_ov64$53 end sync always update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10118 end attribute \src "libresoc.v:174481.3-174495.6" process $proc$libresoc.v:174481$10121 assign { } { } assign { } { } assign $0\div_by_zero$54$next[0:0]$10122 $1\div_by_zero$54$next[0:0]$10123 attribute \src "libresoc.v:174482.5-174482.29" switch \initial attribute \src "libresoc.v:174482.9-174482.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\div_by_zero$54$next[0:0]$10123 $2\div_by_zero$54$next[0:0]$10124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\div_by_zero$54$next[0:0]$10124 \div_by_zero case assign $2\div_by_zero$54$next[0:0]$10124 \div_by_zero$54 end case assign $1\div_by_zero$54$next[0:0]$10123 \div_by_zero$54 end sync always update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10122 end attribute \src "libresoc.v:174496.3-174510.6" process $proc$libresoc.v:174496$10125 assign { } { } assign { } { } assign $0\dividend$68$next[127:0]$10126 $1\dividend$68$next[127:0]$10127 attribute \src "libresoc.v:174497.5-174497.29" switch \initial attribute \src "libresoc.v:174497.9-174497.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dividend$68$next[127:0]$10127 $2\dividend$68$next[127:0]$10128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dividend$68$next[127:0]$10128 \dividend case assign $2\dividend$68$next[127:0]$10128 \dividend$68 end case assign $1\dividend$68$next[127:0]$10127 \dividend$68 end sync always update \dividend$68$next $0\dividend$68$next[127:0]$10126 end attribute \src "libresoc.v:174511.3-174525.6" process $proc$libresoc.v:174511$10129 assign { } { } assign { } { } assign $0\divisor_radicand$65$next[63:0]$10130 $1\divisor_radicand$65$next[63:0]$10131 attribute \src "libresoc.v:174512.5-174512.29" switch \initial attribute \src "libresoc.v:174512.9-174512.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\divisor_radicand$65$next[63:0]$10131 $2\divisor_radicand$65$next[63:0]$10132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\divisor_radicand$65$next[63:0]$10132 \divisor_radicand case assign $2\divisor_radicand$65$next[63:0]$10132 \divisor_radicand$65 end case assign $1\divisor_radicand$65$next[63:0]$10131 \divisor_radicand$65 end sync always update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10130 end attribute \src "libresoc.v:174526.3-174540.6" process $proc$libresoc.v:174526$10133 assign { } { } assign { } { } assign $0\operation$69$next[1:0]$10134 $1\operation$69$next[1:0]$10135 attribute \src "libresoc.v:174527.5-174527.29" switch \initial attribute \src "libresoc.v:174527.9-174527.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\operation$69$next[1:0]$10135 $2\operation$69$next[1:0]$10136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\operation$69$next[1:0]$10136 \operation case assign $2\operation$69$next[1:0]$10136 \operation$69 end case assign $1\operation$69$next[1:0]$10135 \operation$69 end sync always update \operation$69$next $0\operation$69$next[1:0]$10134 end connect \$56 $sshl$libresoc.v:174143$9943_Y connect \$55 $pos$libresoc.v:174144$9945_Y connect \$59 $not$libresoc.v:174145$9946_Y connect \$61 $ge$libresoc.v:174146$9947_Y connect \$63 $and$libresoc.v:174147$9948_Y connect \$66 $and$libresoc.v:174148$9949_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 connect \quotient_root \div_state_next_o_dividend_quotient [63:0] connect \div_by_zero$27 \div_by_zero$54 connect \dive_abs_ov64$26 \dive_abs_ov64$53 connect \dive_abs_ov32$25 \dive_abs_ov32$52 connect \dividend_neg$24 \dividend_neg$51 connect \divisor_neg$23 \divisor_neg$50 connect \xer_so$22 \xer_so$49 connect \rb$21 \rb$48 connect \ra$20 \ra$47 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end attribute \src "libresoc.v:174560.1-176105.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start attribute \src "libresoc.v:175911.3-175923.6" wire $0\div_by_zero$next[0:0]$10246 attribute \src "libresoc.v:175697.3-175698.39" wire $0\div_by_zero[0:0] attribute \src "libresoc.v:175885.3-175897.6" wire $0\dive_abs_ov32$next[0:0]$10240 attribute \src "libresoc.v:175701.3-175702.43" wire $0\dive_abs_ov32[0:0] attribute \src "libresoc.v:175898.3-175910.6" wire $0\dive_abs_ov64$next[0:0]$10243 attribute \src "libresoc.v:175699.3-175700.43" wire $0\dive_abs_ov64[0:0] attribute \src "libresoc.v:175924.3-175936.6" wire width 128 $0\dividend$next[127:0]$10249 attribute \src "libresoc.v:175695.3-175696.33" wire width 128 $0\dividend[127:0] attribute \src "libresoc.v:175872.3-175884.6" wire $0\dividend_neg$next[0:0]$10237 attribute \src "libresoc.v:175703.3-175704.41" wire $0\dividend_neg[0:0] attribute \src "libresoc.v:175859.3-175871.6" wire $0\divisor_neg$next[0:0]$10234 attribute \src "libresoc.v:175705.3-175706.39" wire $0\divisor_neg[0:0] attribute \src "libresoc.v:175937.3-175949.6" wire width 64 $0\divisor_radicand$next[63:0]$10252 attribute \src "libresoc.v:175693.3-175694.49" wire width 64 $0\divisor_radicand[63:0] attribute \src "libresoc.v:174561.7-174561.20" wire $0\initial[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 4 $0\logical_op__data_len$next[3:0]$10265 attribute \src "libresoc.v:175745.3-175746.57" wire width 4 $0\logical_op__data_len[3:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 14 $0\logical_op__fn_unit$next[13:0]$10266 attribute \src "libresoc.v:175715.3-175716.55" wire width 14 $0\logical_op__fn_unit[13:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 64 $0\logical_op__imm_data__data$next[63:0]$10267 attribute \src "libresoc.v:175717.3-175718.69" wire width 64 $0\logical_op__imm_data__data[63:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__imm_data__ok$next[0:0]$10268 attribute \src "libresoc.v:175719.3-175720.65" wire $0\logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 2 $0\logical_op__input_carry$next[1:0]$10269 attribute \src "libresoc.v:175733.3-175734.63" wire width 2 $0\logical_op__input_carry[1:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 32 $0\logical_op__insn$next[31:0]$10270 attribute \src "libresoc.v:175747.3-175748.49" wire width 32 $0\logical_op__insn[31:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 7 $0\logical_op__insn_type$next[6:0]$10271 attribute \src "libresoc.v:175713.3-175714.59" wire width 7 $0\logical_op__insn_type[6:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__invert_in$next[0:0]$10272 attribute \src "libresoc.v:175729.3-175730.59" wire $0\logical_op__invert_in[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__invert_out$next[0:0]$10273 attribute \src "libresoc.v:175735.3-175736.61" wire $0\logical_op__invert_out[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__is_32bit$next[0:0]$10274 attribute \src "libresoc.v:175741.3-175742.57" wire $0\logical_op__is_32bit[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__is_signed$next[0:0]$10275 attribute \src "libresoc.v:175743.3-175744.59" wire $0\logical_op__is_signed[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__oe__oe$next[0:0]$10276 attribute \src "libresoc.v:175725.3-175726.53" wire $0\logical_op__oe__oe[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__oe__ok$next[0:0]$10277 attribute \src "libresoc.v:175727.3-175728.53" wire $0\logical_op__oe__ok[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__output_carry$next[0:0]$10278 attribute \src "libresoc.v:175739.3-175740.65" wire $0\logical_op__output_carry[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__rc__ok$next[0:0]$10279 attribute \src "libresoc.v:175723.3-175724.53" wire $0\logical_op__rc__ok[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__rc__rc$next[0:0]$10280 attribute \src "libresoc.v:175721.3-175722.53" wire $0\logical_op__rc__rc[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__write_cr0$next[0:0]$10281 attribute \src "libresoc.v:175737.3-175738.59" wire $0\logical_op__write_cr0[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $0\logical_op__zero_a$next[0:0]$10282 attribute \src "libresoc.v:175731.3-175732.53" wire $0\logical_op__zero_a[0:0] attribute \src "libresoc.v:175981.3-175993.6" wire width 2 $0\muxid$next[1:0]$10262 attribute \src "libresoc.v:175749.3-175750.27" wire width 2 $0\muxid[1:0] attribute \src "libresoc.v:175950.3-175962.6" wire width 2 $0\operation$next[1:0]$10255 attribute \src "libresoc.v:175691.3-175692.35" wire width 2 $0\operation[1:0] attribute \src "libresoc.v:175963.3-175980.6" wire $0\r_busy$next[0:0]$10258 attribute \src "libresoc.v:175751.3-175752.29" wire $0\r_busy[0:0] attribute \src "libresoc.v:176036.3-176048.6" wire width 64 $0\ra$next[63:0]$10308 attribute \src "libresoc.v:175711.3-175712.21" wire width 64 $0\ra[63:0] attribute \src "libresoc.v:176049.3-176061.6" wire width 64 $0\rb$next[63:0]$10311 attribute \src "libresoc.v:175709.3-175710.21" wire width 64 $0\rb[63:0] attribute \src "libresoc.v:176062.3-176074.6" wire $0\xer_so$next[0:0]$10314 attribute \src "libresoc.v:175707.3-175708.29" wire $0\xer_so[0:0] attribute \src "libresoc.v:175911.3-175923.6" wire $1\div_by_zero$next[0:0]$10247 attribute \src "libresoc.v:174570.7-174570.25" wire $1\div_by_zero[0:0] attribute \src "libresoc.v:175885.3-175897.6" wire $1\dive_abs_ov32$next[0:0]$10241 attribute \src "libresoc.v:174577.7-174577.27" wire $1\dive_abs_ov32[0:0] attribute \src "libresoc.v:175898.3-175910.6" wire $1\dive_abs_ov64$next[0:0]$10244 attribute \src "libresoc.v:174584.7-174584.27" wire $1\dive_abs_ov64[0:0] attribute \src "libresoc.v:175924.3-175936.6" wire width 128 $1\dividend$next[127:0]$10250 attribute \src "libresoc.v:174591.15-174591.63" wire width 128 $1\dividend[127:0] attribute \src "libresoc.v:175872.3-175884.6" wire $1\dividend_neg$next[0:0]$10238 attribute \src "libresoc.v:174598.7-174598.26" wire $1\dividend_neg[0:0] attribute \src "libresoc.v:175859.3-175871.6" wire $1\divisor_neg$next[0:0]$10235 attribute \src "libresoc.v:174605.7-174605.25" wire $1\divisor_neg[0:0] attribute \src "libresoc.v:175937.3-175949.6" wire width 64 $1\divisor_radicand$next[63:0]$10253 attribute \src "libresoc.v:174612.14-174612.53" wire width 64 $1\divisor_radicand[63:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 4 $1\logical_op__data_len$next[3:0]$10283 attribute \src "libresoc.v:174895.13-174895.40" wire width 4 $1\logical_op__data_len[3:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 14 $1\logical_op__fn_unit$next[13:0]$10284 attribute \src "libresoc.v:174919.14-174919.44" wire width 14 $1\logical_op__fn_unit[13:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 64 $1\logical_op__imm_data__data$next[63:0]$10285 attribute \src "libresoc.v:174958.14-174958.63" wire width 64 $1\logical_op__imm_data__data[63:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__imm_data__ok$next[0:0]$10286 attribute \src "libresoc.v:174967.7-174967.38" wire $1\logical_op__imm_data__ok[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 2 $1\logical_op__input_carry$next[1:0]$10287 attribute \src "libresoc.v:174980.13-174980.43" wire width 2 $1\logical_op__input_carry[1:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 32 $1\logical_op__insn$next[31:0]$10288 attribute \src "libresoc.v:174997.14-174997.38" wire width 32 $1\logical_op__insn[31:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 7 $1\logical_op__insn_type$next[6:0]$10289 attribute \src "libresoc.v:175081.13-175081.42" wire width 7 $1\logical_op__insn_type[6:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__invert_in$next[0:0]$10290 attribute \src "libresoc.v:175240.7-175240.35" wire $1\logical_op__invert_in[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__invert_out$next[0:0]$10291 attribute \src "libresoc.v:175249.7-175249.36" wire $1\logical_op__invert_out[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__is_32bit$next[0:0]$10292 attribute \src "libresoc.v:175258.7-175258.34" wire $1\logical_op__is_32bit[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__is_signed$next[0:0]$10293 attribute \src "libresoc.v:175267.7-175267.35" wire $1\logical_op__is_signed[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__oe__oe$next[0:0]$10294 attribute \src "libresoc.v:175276.7-175276.32" wire $1\logical_op__oe__oe[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__oe__ok$next[0:0]$10295 attribute \src "libresoc.v:175285.7-175285.32" wire $1\logical_op__oe__ok[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__output_carry$next[0:0]$10296 attribute \src "libresoc.v:175294.7-175294.38" wire $1\logical_op__output_carry[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__rc__ok$next[0:0]$10297 attribute \src "libresoc.v:175303.7-175303.32" wire $1\logical_op__rc__ok[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__rc__rc$next[0:0]$10298 attribute \src "libresoc.v:175312.7-175312.32" wire $1\logical_op__rc__rc[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__write_cr0$next[0:0]$10299 attribute \src "libresoc.v:175321.7-175321.35" wire $1\logical_op__write_cr0[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire $1\logical_op__zero_a$next[0:0]$10300 attribute \src "libresoc.v:175330.7-175330.32" wire $1\logical_op__zero_a[0:0] attribute \src "libresoc.v:175981.3-175993.6" wire width 2 $1\muxid$next[1:0]$10263 attribute \src "libresoc.v:175339.13-175339.25" wire width 2 $1\muxid[1:0] attribute \src "libresoc.v:175950.3-175962.6" wire width 2 $1\operation$next[1:0]$10256 attribute \src "libresoc.v:175354.13-175354.29" wire width 2 $1\operation[1:0] attribute \src "libresoc.v:175963.3-175980.6" wire $1\r_busy$next[0:0]$10259 attribute \src "libresoc.v:175368.7-175368.20" wire $1\r_busy[0:0] attribute \src "libresoc.v:176036.3-176048.6" wire width 64 $1\ra$next[63:0]$10309 attribute \src "libresoc.v:175373.14-175373.39" wire width 64 $1\ra[63:0] attribute \src "libresoc.v:176049.3-176061.6" wire width 64 $1\rb$next[63:0]$10312 attribute \src "libresoc.v:175384.14-175384.39" wire width 64 $1\rb[63:0] attribute \src "libresoc.v:176062.3-176074.6" wire $1\xer_so$next[0:0]$10315 attribute \src "libresoc.v:175683.7-175683.20" wire $1\xer_so[0:0] attribute \src "libresoc.v:175994.3-176035.6" wire width 64 $2\logical_op__imm_data__data$next[63:0]$10301 attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__imm_data__ok$next[0:0]$10302 attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__oe__oe$next[0:0]$10303 attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__oe__ok$next[0:0]$10304 attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__rc__ok$next[0:0]$10305 attribute \src "libresoc.v:175994.3-176035.6" wire $2\logical_op__rc__rc$next[0:0]$10306 attribute \src "libresoc.v:175963.3-175980.6" wire $2\r_busy$next[0:0]$10260 attribute \src "libresoc.v:175690.18-175690.118" wire $and$libresoc.v:175690$10201_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 58 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \div_by_zero$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \div_by_zero$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire output 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \dive_abs_ov32$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \dive_abs_ov32$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire output 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \dive_abs_ov64$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \dive_abs_ov64$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 output 31 \dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \dividend$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \dividend$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire output 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \dividend_neg$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \dividend_neg$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire output 26 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \divisor_neg$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \divisor_neg$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 32 \divisor_radicand attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next attribute \src "libresoc.v:174561.7-174561.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len$40 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \input_logical_op__fn_unit$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \input_logical_op__imm_data__data$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__imm_data__ok$27 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \input_logical_op__input_carry$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \input_logical_op__insn$41 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \input_logical_op__insn_type$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_in$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__invert_out$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_32bit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__is_signed$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__oe$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__oe__ok$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__output_carry$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__rc__rc$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__write_cr0$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \input_logical_op__zero_a$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_ra$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \input_rb$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \input_xer_so$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 53 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 6 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 38 \logical_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 39 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \logical_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 8 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 40 \logical_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 15 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 47 \logical_op__input_carry$12 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \logical_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 54 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \logical_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 37 \logical_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \logical_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 45 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 48 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 51 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 52 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 43 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 12 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 44 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 50 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 10 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 42 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 41 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 49 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 46 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 36 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 output 33 \operation attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \operation$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \operation$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire output 35 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire input 34 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" wire \p_valid_i$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 55 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \ra$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 output 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 56 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \rb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \setup_stage_div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire \setup_stage_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire \setup_stage_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 \setup_stage_dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire \setup_stage_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire \setup_stage_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \setup_stage_divisor_radicand attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \setup_stage_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \setup_stage_logical_op__data_len$62 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \setup_stage_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \setup_stage_logical_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \setup_stage_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \setup_stage_logical_op__imm_data__data$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__imm_data__ok$49 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \setup_stage_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \setup_stage_logical_op__input_carry$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \setup_stage_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \setup_stage_logical_op__insn$63 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \setup_stage_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \setup_stage_logical_op__insn_type$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__invert_out$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__is_32bit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__is_signed$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__oe__oe$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__oe__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__output_carry$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__rc__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__rc__rc$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__write_cr0$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \setup_stage_logical_op__zero_a$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \setup_stage_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \setup_stage_muxid$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 \setup_stage_operation attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \setup_stage_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \setup_stage_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \setup_stage_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \setup_stage_xer_so$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 25 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 57 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" cell $and $and$libresoc.v:175690$10201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o connect \Y $and$libresoc.v:175690$10201_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:175753.14-175798.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 connect \logical_op__fn_unit \input_logical_op__fn_unit connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 connect \logical_op__imm_data__data \input_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 connect \logical_op__input_carry \input_logical_op__input_carry connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 connect \logical_op__insn \input_logical_op__insn connect \logical_op__insn$19 \input_logical_op__insn$41 connect \logical_op__insn_type \input_logical_op__insn_type connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 connect \logical_op__invert_in \input_logical_op__invert_in connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 connect \logical_op__invert_out \input_logical_op__invert_out connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 connect \logical_op__is_32bit \input_logical_op__is_32bit connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 connect \logical_op__is_signed \input_logical_op__is_signed connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 connect \logical_op__oe__oe \input_logical_op__oe__oe connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 connect \logical_op__oe__ok \input_logical_op__oe__ok connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 connect \logical_op__output_carry \input_logical_op__output_carry connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 connect \logical_op__rc__ok \input_logical_op__rc__ok connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 connect \logical_op__rc__rc \input_logical_op__rc__rc connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 connect \logical_op__write_cr0 \input_logical_op__write_cr0 connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 connect \logical_op__zero_a \input_logical_op__zero_a connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 connect \muxid \input_muxid connect \muxid$1 \input_muxid$23 connect \ra \input_ra connect \ra$20 \input_ra$42 connect \rb \input_rb connect \rb$21 \input_rb$43 connect \xer_so \input_xer_so connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 attribute \src "libresoc.v:175799.10-175802.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 attribute \src "libresoc.v:175803.10-175806.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 attribute \src "libresoc.v:175807.15-175858.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 connect \dividend \setup_stage_dividend connect \dividend_neg \setup_stage_dividend_neg connect \divisor_neg \setup_stage_divisor_neg connect \divisor_radicand \setup_stage_divisor_radicand connect \logical_op__data_len \setup_stage_logical_op__data_len connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 connect \logical_op__input_carry \setup_stage_logical_op__input_carry connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 connect \logical_op__insn \setup_stage_logical_op__insn connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 connect \logical_op__insn_type \setup_stage_logical_op__insn_type connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 connect \logical_op__invert_in \setup_stage_logical_op__invert_in connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 connect \logical_op__invert_out \setup_stage_logical_op__invert_out connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 connect \logical_op__is_signed \setup_stage_logical_op__is_signed connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 connect \logical_op__output_carry \setup_stage_logical_op__output_carry connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 connect \logical_op__zero_a \setup_stage_logical_op__zero_a connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 connect \muxid \setup_stage_muxid connect \muxid$1 \setup_stage_muxid$45 connect \operation \setup_stage_operation connect \ra \setup_stage_ra connect \rb \setup_stage_rb connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end attribute \src "libresoc.v:174561.7-174561.20" process $proc$libresoc.v:174561$10316 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:174570.7-174570.25" process $proc$libresoc.v:174570$10317 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end attribute \src "libresoc.v:174577.7-174577.27" process $proc$libresoc.v:174577$10318 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end attribute \src "libresoc.v:174584.7-174584.27" process $proc$libresoc.v:174584$10319 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end attribute \src "libresoc.v:174591.15-174591.63" process $proc$libresoc.v:174591$10320 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end attribute \src "libresoc.v:174598.7-174598.26" process $proc$libresoc.v:174598$10321 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end attribute \src "libresoc.v:174605.7-174605.25" process $proc$libresoc.v:174605$10322 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end attribute \src "libresoc.v:174612.14-174612.53" process $proc$libresoc.v:174612$10323 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end attribute \src "libresoc.v:174895.13-174895.40" process $proc$libresoc.v:174895$10324 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end attribute \src "libresoc.v:174919.14-174919.44" process $proc$libresoc.v:174919$10325 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end attribute \src "libresoc.v:174958.14-174958.63" process $proc$libresoc.v:174958$10326 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:174967.7-174967.38" process $proc$libresoc.v:174967$10327 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:174980.13-174980.43" process $proc$libresoc.v:174980$10328 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end attribute \src "libresoc.v:174997.14-174997.38" process $proc$libresoc.v:174997$10329 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end attribute \src "libresoc.v:175081.13-175081.42" process $proc$libresoc.v:175081$10330 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end attribute \src "libresoc.v:175240.7-175240.35" process $proc$libresoc.v:175240$10331 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end attribute \src "libresoc.v:175249.7-175249.36" process $proc$libresoc.v:175249$10332 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end attribute \src "libresoc.v:175258.7-175258.34" process $proc$libresoc.v:175258$10333 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end attribute \src "libresoc.v:175267.7-175267.35" process $proc$libresoc.v:175267$10334 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end attribute \src "libresoc.v:175276.7-175276.32" process $proc$libresoc.v:175276$10335 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end attribute \src "libresoc.v:175285.7-175285.32" process $proc$libresoc.v:175285$10336 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end attribute \src "libresoc.v:175294.7-175294.38" process $proc$libresoc.v:175294$10337 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end attribute \src "libresoc.v:175303.7-175303.32" process $proc$libresoc.v:175303$10338 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end attribute \src "libresoc.v:175312.7-175312.32" process $proc$libresoc.v:175312$10339 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end attribute \src "libresoc.v:175321.7-175321.35" process $proc$libresoc.v:175321$10340 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end attribute \src "libresoc.v:175330.7-175330.32" process $proc$libresoc.v:175330$10341 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end attribute \src "libresoc.v:175339.13-175339.25" process $proc$libresoc.v:175339$10342 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end attribute \src "libresoc.v:175354.13-175354.29" process $proc$libresoc.v:175354$10343 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end attribute \src "libresoc.v:175368.7-175368.20" process $proc$libresoc.v:175368$10344 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end attribute \src "libresoc.v:175373.14-175373.39" process $proc$libresoc.v:175373$10345 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end attribute \src "libresoc.v:175384.14-175384.39" process $proc$libresoc.v:175384$10346 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end attribute \src "libresoc.v:175683.7-175683.20" process $proc$libresoc.v:175683$10347 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end attribute \src "libresoc.v:175691.3-175692.35" process $proc$libresoc.v:175691$10202 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end attribute \src "libresoc.v:175693.3-175694.49" process $proc$libresoc.v:175693$10203 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end attribute \src "libresoc.v:175695.3-175696.33" process $proc$libresoc.v:175695$10204 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end attribute \src "libresoc.v:175697.3-175698.39" process $proc$libresoc.v:175697$10205 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end attribute \src "libresoc.v:175699.3-175700.43" process $proc$libresoc.v:175699$10206 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end attribute \src "libresoc.v:175701.3-175702.43" process $proc$libresoc.v:175701$10207 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end attribute \src "libresoc.v:175703.3-175704.41" process $proc$libresoc.v:175703$10208 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end attribute \src "libresoc.v:175705.3-175706.39" process $proc$libresoc.v:175705$10209 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end attribute \src "libresoc.v:175707.3-175708.29" process $proc$libresoc.v:175707$10210 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end attribute \src "libresoc.v:175709.3-175710.21" process $proc$libresoc.v:175709$10211 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end attribute \src "libresoc.v:175711.3-175712.21" process $proc$libresoc.v:175711$10212 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end attribute \src "libresoc.v:175713.3-175714.59" process $proc$libresoc.v:175713$10213 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end attribute \src "libresoc.v:175715.3-175716.55" process $proc$libresoc.v:175715$10214 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end attribute \src "libresoc.v:175717.3-175718.69" process $proc$libresoc.v:175717$10215 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end attribute \src "libresoc.v:175719.3-175720.65" process $proc$libresoc.v:175719$10216 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end attribute \src "libresoc.v:175721.3-175722.53" process $proc$libresoc.v:175721$10217 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end attribute \src "libresoc.v:175723.3-175724.53" process $proc$libresoc.v:175723$10218 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end attribute \src "libresoc.v:175725.3-175726.53" process $proc$libresoc.v:175725$10219 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end attribute \src "libresoc.v:175727.3-175728.53" process $proc$libresoc.v:175727$10220 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end attribute \src "libresoc.v:175729.3-175730.59" process $proc$libresoc.v:175729$10221 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end attribute \src "libresoc.v:175731.3-175732.53" process $proc$libresoc.v:175731$10222 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end attribute \src "libresoc.v:175733.3-175734.63" process $proc$libresoc.v:175733$10223 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end attribute \src "libresoc.v:175735.3-175736.61" process $proc$libresoc.v:175735$10224 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end attribute \src "libresoc.v:175737.3-175738.59" process $proc$libresoc.v:175737$10225 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end attribute \src "libresoc.v:175739.3-175740.65" process $proc$libresoc.v:175739$10226 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end attribute \src "libresoc.v:175741.3-175742.57" process $proc$libresoc.v:175741$10227 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end attribute \src "libresoc.v:175743.3-175744.59" process $proc$libresoc.v:175743$10228 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end attribute \src "libresoc.v:175745.3-175746.57" process $proc$libresoc.v:175745$10229 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end attribute \src "libresoc.v:175747.3-175748.49" process $proc$libresoc.v:175747$10230 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end attribute \src "libresoc.v:175749.3-175750.27" process $proc$libresoc.v:175749$10231 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end attribute \src "libresoc.v:175751.3-175752.29" process $proc$libresoc.v:175751$10232 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end attribute \src "libresoc.v:175859.3-175871.6" process $proc$libresoc.v:175859$10233 assign { } { } assign { } { } assign $0\divisor_neg$next[0:0]$10234 $1\divisor_neg$next[0:0]$10235 attribute \src "libresoc.v:175860.5-175860.29" switch \initial attribute \src "libresoc.v:175860.9-175860.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\divisor_neg$next[0:0]$10235 \divisor_neg$92 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\divisor_neg$next[0:0]$10235 \divisor_neg$92 case assign $1\divisor_neg$next[0:0]$10235 \divisor_neg end sync always update \divisor_neg$next $0\divisor_neg$next[0:0]$10234 end attribute \src "libresoc.v:175872.3-175884.6" process $proc$libresoc.v:175872$10236 assign { } { } assign { } { } assign $0\dividend_neg$next[0:0]$10237 $1\dividend_neg$next[0:0]$10238 attribute \src "libresoc.v:175873.5-175873.29" switch \initial attribute \src "libresoc.v:175873.9-175873.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\dividend_neg$next[0:0]$10238 \dividend_neg$93 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\dividend_neg$next[0:0]$10238 \dividend_neg$93 case assign $1\dividend_neg$next[0:0]$10238 \dividend_neg end sync always update \dividend_neg$next $0\dividend_neg$next[0:0]$10237 end attribute \src "libresoc.v:175885.3-175897.6" process $proc$libresoc.v:175885$10239 assign { } { } assign { } { } assign $0\dive_abs_ov32$next[0:0]$10240 $1\dive_abs_ov32$next[0:0]$10241 attribute \src "libresoc.v:175886.5-175886.29" switch \initial attribute \src "libresoc.v:175886.9-175886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32$94 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32$94 case assign $1\dive_abs_ov32$next[0:0]$10241 \dive_abs_ov32 end sync always update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10240 end attribute \src "libresoc.v:175898.3-175910.6" process $proc$libresoc.v:175898$10242 assign { } { } assign { } { } assign $0\dive_abs_ov64$next[0:0]$10243 $1\dive_abs_ov64$next[0:0]$10244 attribute \src "libresoc.v:175899.5-175899.29" switch \initial attribute \src "libresoc.v:175899.9-175899.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64$95 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64$95 case assign $1\dive_abs_ov64$next[0:0]$10244 \dive_abs_ov64 end sync always update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10243 end attribute \src "libresoc.v:175911.3-175923.6" process $proc$libresoc.v:175911$10245 assign { } { } assign { } { } assign $0\div_by_zero$next[0:0]$10246 $1\div_by_zero$next[0:0]$10247 attribute \src "libresoc.v:175912.5-175912.29" switch \initial attribute \src "libresoc.v:175912.9-175912.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\div_by_zero$next[0:0]$10247 \div_by_zero$96 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\div_by_zero$next[0:0]$10247 \div_by_zero$96 case assign $1\div_by_zero$next[0:0]$10247 \div_by_zero end sync always update \div_by_zero$next $0\div_by_zero$next[0:0]$10246 end attribute \src "libresoc.v:175924.3-175936.6" process $proc$libresoc.v:175924$10248 assign { } { } assign { } { } assign $0\dividend$next[127:0]$10249 $1\dividend$next[127:0]$10250 attribute \src "libresoc.v:175925.5-175925.29" switch \initial attribute \src "libresoc.v:175925.9-175925.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\dividend$next[127:0]$10250 \dividend$97 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\dividend$next[127:0]$10250 \dividend$97 case assign $1\dividend$next[127:0]$10250 \dividend end sync always update \dividend$next $0\dividend$next[127:0]$10249 end attribute \src "libresoc.v:175937.3-175949.6" process $proc$libresoc.v:175937$10251 assign { } { } assign { } { } assign $0\divisor_radicand$next[63:0]$10252 $1\divisor_radicand$next[63:0]$10253 attribute \src "libresoc.v:175938.5-175938.29" switch \initial attribute \src "libresoc.v:175938.9-175938.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand$98 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand$98 case assign $1\divisor_radicand$next[63:0]$10253 \divisor_radicand end sync always update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10252 end attribute \src "libresoc.v:175950.3-175962.6" process $proc$libresoc.v:175950$10254 assign { } { } assign { } { } assign $0\operation$next[1:0]$10255 $1\operation$next[1:0]$10256 attribute \src "libresoc.v:175951.5-175951.29" switch \initial attribute \src "libresoc.v:175951.9-175951.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\operation$next[1:0]$10256 \operation$99 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\operation$next[1:0]$10256 \operation$99 case assign $1\operation$next[1:0]$10256 \operation end sync always update \operation$next $0\operation$next[1:0]$10255 end attribute \src "libresoc.v:175963.3-175980.6" process $proc$libresoc.v:175963$10257 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$10258 $2\r_busy$next[0:0]$10260 attribute \src "libresoc.v:175964.5-175964.29" switch \initial attribute \src "libresoc.v:175964.9-175964.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\r_busy$next[0:0]$10259 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\r_busy$next[0:0]$10259 1'0 case assign $1\r_busy$next[0:0]$10259 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r_busy$next[0:0]$10260 1'0 case assign $2\r_busy$next[0:0]$10260 $1\r_busy$next[0:0]$10259 end sync always update \r_busy$next $0\r_busy$next[0:0]$10258 end attribute \src "libresoc.v:175981.3-175993.6" process $proc$libresoc.v:175981$10261 assign { } { } assign { } { } assign $0\muxid$next[1:0]$10262 $1\muxid$next[1:0]$10263 attribute \src "libresoc.v:175982.5-175982.29" switch \initial attribute \src "libresoc.v:175982.9-175982.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\muxid$next[1:0]$10263 \muxid$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\muxid$next[1:0]$10263 \muxid$68 case assign $1\muxid$next[1:0]$10263 \muxid end sync always update \muxid$next $0\muxid$next[1:0]$10262 end attribute \src "libresoc.v:175994.3-176035.6" process $proc$libresoc.v:175994$10264 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\logical_op__data_len$next[3:0]$10265 $1\logical_op__data_len$next[3:0]$10283 assign $0\logical_op__fn_unit$next[13:0]$10266 $1\logical_op__fn_unit$next[13:0]$10284 assign { } { } assign { } { } assign $0\logical_op__input_carry$next[1:0]$10269 $1\logical_op__input_carry$next[1:0]$10287 assign $0\logical_op__insn$next[31:0]$10270 $1\logical_op__insn$next[31:0]$10288 assign $0\logical_op__insn_type$next[6:0]$10271 $1\logical_op__insn_type$next[6:0]$10289 assign $0\logical_op__invert_in$next[0:0]$10272 $1\logical_op__invert_in$next[0:0]$10290 assign $0\logical_op__invert_out$next[0:0]$10273 $1\logical_op__invert_out$next[0:0]$10291 assign $0\logical_op__is_32bit$next[0:0]$10274 $1\logical_op__is_32bit$next[0:0]$10292 assign $0\logical_op__is_signed$next[0:0]$10275 $1\logical_op__is_signed$next[0:0]$10293 assign { } { } assign { } { } assign $0\logical_op__output_carry$next[0:0]$10278 $1\logical_op__output_carry$next[0:0]$10296 assign { } { } assign { } { } assign $0\logical_op__write_cr0$next[0:0]$10281 $1\logical_op__write_cr0$next[0:0]$10299 assign $0\logical_op__zero_a$next[0:0]$10282 $1\logical_op__zero_a$next[0:0]$10300 assign $0\logical_op__imm_data__data$next[63:0]$10267 $2\logical_op__imm_data__data$next[63:0]$10301 assign $0\logical_op__imm_data__ok$next[0:0]$10268 $2\logical_op__imm_data__ok$next[0:0]$10302 assign $0\logical_op__oe__oe$next[0:0]$10276 $2\logical_op__oe__oe$next[0:0]$10303 assign $0\logical_op__oe__ok$next[0:0]$10277 $2\logical_op__oe__ok$next[0:0]$10304 assign $0\logical_op__rc__ok$next[0:0]$10279 $2\logical_op__rc__ok$next[0:0]$10305 assign $0\logical_op__rc__rc$next[0:0]$10280 $2\logical_op__rc__rc$next[0:0]$10306 attribute \src "libresoc.v:175995.5-175995.29" switch \initial attribute \src "libresoc.v:175995.9-175995.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$next[31:0]$10288 $1\logical_op__data_len$next[3:0]$10283 $1\logical_op__is_signed$next[0:0]$10293 $1\logical_op__is_32bit$next[0:0]$10292 $1\logical_op__output_carry$next[0:0]$10296 $1\logical_op__write_cr0$next[0:0]$10299 $1\logical_op__invert_out$next[0:0]$10291 $1\logical_op__input_carry$next[1:0]$10287 $1\logical_op__zero_a$next[0:0]$10300 $1\logical_op__invert_in$next[0:0]$10290 $1\logical_op__oe__ok$next[0:0]$10295 $1\logical_op__oe__oe$next[0:0]$10294 $1\logical_op__rc__ok$next[0:0]$10297 $1\logical_op__rc__rc$next[0:0]$10298 $1\logical_op__imm_data__ok$next[0:0]$10286 $1\logical_op__imm_data__data$next[63:0]$10285 $1\logical_op__fn_unit$next[13:0]$10284 $1\logical_op__insn_type$next[6:0]$10289 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\logical_op__insn$next[31:0]$10288 $1\logical_op__data_len$next[3:0]$10283 $1\logical_op__is_signed$next[0:0]$10293 $1\logical_op__is_32bit$next[0:0]$10292 $1\logical_op__output_carry$next[0:0]$10296 $1\logical_op__write_cr0$next[0:0]$10299 $1\logical_op__invert_out$next[0:0]$10291 $1\logical_op__input_carry$next[1:0]$10287 $1\logical_op__zero_a$next[0:0]$10300 $1\logical_op__invert_in$next[0:0]$10290 $1\logical_op__oe__ok$next[0:0]$10295 $1\logical_op__oe__oe$next[0:0]$10294 $1\logical_op__rc__ok$next[0:0]$10297 $1\logical_op__rc__rc$next[0:0]$10298 $1\logical_op__imm_data__ok$next[0:0]$10286 $1\logical_op__imm_data__data$next[63:0]$10285 $1\logical_op__fn_unit$next[13:0]$10284 $1\logical_op__insn_type$next[6:0]$10289 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } case assign $1\logical_op__data_len$next[3:0]$10283 \logical_op__data_len assign $1\logical_op__fn_unit$next[13:0]$10284 \logical_op__fn_unit assign $1\logical_op__imm_data__data$next[63:0]$10285 \logical_op__imm_data__data assign $1\logical_op__imm_data__ok$next[0:0]$10286 \logical_op__imm_data__ok assign $1\logical_op__input_carry$next[1:0]$10287 \logical_op__input_carry assign $1\logical_op__insn$next[31:0]$10288 \logical_op__insn assign $1\logical_op__insn_type$next[6:0]$10289 \logical_op__insn_type assign $1\logical_op__invert_in$next[0:0]$10290 \logical_op__invert_in assign $1\logical_op__invert_out$next[0:0]$10291 \logical_op__invert_out assign $1\logical_op__is_32bit$next[0:0]$10292 \logical_op__is_32bit assign $1\logical_op__is_signed$next[0:0]$10293 \logical_op__is_signed assign $1\logical_op__oe__oe$next[0:0]$10294 \logical_op__oe__oe assign $1\logical_op__oe__ok$next[0:0]$10295 \logical_op__oe__ok assign $1\logical_op__output_carry$next[0:0]$10296 \logical_op__output_carry assign $1\logical_op__rc__ok$next[0:0]$10297 \logical_op__rc__ok assign $1\logical_op__rc__rc$next[0:0]$10298 \logical_op__rc__rc assign $1\logical_op__write_cr0$next[0:0]$10299 \logical_op__write_cr0 assign $1\logical_op__zero_a$next[0:0]$10300 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\logical_op__imm_data__data$next[63:0]$10301 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\logical_op__imm_data__ok$next[0:0]$10302 1'0 assign $2\logical_op__rc__rc$next[0:0]$10306 1'0 assign $2\logical_op__rc__ok$next[0:0]$10305 1'0 assign $2\logical_op__oe__oe$next[0:0]$10303 1'0 assign $2\logical_op__oe__ok$next[0:0]$10304 1'0 case assign $2\logical_op__imm_data__data$next[63:0]$10301 $1\logical_op__imm_data__data$next[63:0]$10285 assign $2\logical_op__imm_data__ok$next[0:0]$10302 $1\logical_op__imm_data__ok$next[0:0]$10286 assign $2\logical_op__oe__oe$next[0:0]$10303 $1\logical_op__oe__oe$next[0:0]$10294 assign $2\logical_op__oe__ok$next[0:0]$10304 $1\logical_op__oe__ok$next[0:0]$10295 assign $2\logical_op__rc__ok$next[0:0]$10305 $1\logical_op__rc__ok$next[0:0]$10297 assign $2\logical_op__rc__rc$next[0:0]$10306 $1\logical_op__rc__rc$next[0:0]$10298 end sync always update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10265 update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10266 update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10267 update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10268 update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10269 update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10270 update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10271 update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10272 update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10273 update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10274 update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10275 update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10276 update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10277 update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10278 update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10279 update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10280 update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10281 update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10282 end attribute \src "libresoc.v:176036.3-176048.6" process $proc$libresoc.v:176036$10307 assign { } { } assign { } { } assign $0\ra$next[63:0]$10308 $1\ra$next[63:0]$10309 attribute \src "libresoc.v:176037.5-176037.29" switch \initial attribute \src "libresoc.v:176037.9-176037.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\ra$next[63:0]$10309 \ra$87 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\ra$next[63:0]$10309 \ra$87 case assign $1\ra$next[63:0]$10309 \ra end sync always update \ra$next $0\ra$next[63:0]$10308 end attribute \src "libresoc.v:176049.3-176061.6" process $proc$libresoc.v:176049$10310 assign { } { } assign { } { } assign $0\rb$next[63:0]$10311 $1\rb$next[63:0]$10312 attribute \src "libresoc.v:176050.5-176050.29" switch \initial attribute \src "libresoc.v:176050.9-176050.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\rb$next[63:0]$10312 \rb$89 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\rb$next[63:0]$10312 \rb$89 case assign $1\rb$next[63:0]$10312 \rb end sync always update \rb$next $0\rb$next[63:0]$10311 end attribute \src "libresoc.v:176062.3-176074.6" process $proc$libresoc.v:176062$10313 assign { } { } assign { } { } assign $0\xer_so$next[0:0]$10314 $1\xer_so$next[0:0]$10315 attribute \src "libresoc.v:176063.5-176063.29" switch \initial attribute \src "libresoc.v:176063.9-176063.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\xer_so$next[0:0]$10315 \xer_so$91 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\xer_so$next[0:0]$10315 \xer_so$91 case assign $1\xer_so$next[0:0]$10315 \xer_so end sync always update \xer_so$next $0\xer_so$next[0:0]$10314 end connect \$66 $and$libresoc.v:175690$10201_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \operation$99 \setup_stage_operation connect \divisor_radicand$98 \setup_stage_divisor_radicand connect \dividend$97 \setup_stage_dividend connect \div_by_zero$96 \setup_stage_div_by_zero connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 connect \dividend_neg$93 \setup_stage_dividend_neg connect \divisor_neg$92 \setup_stage_divisor_neg connect \xer_so$91 \setup_stage_xer_so$64 connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } connect \muxid$68 \setup_stage_muxid$45 connect \p_valid_i_p_ready_o \$66 connect \n_i_rdy_data \n_ready_i connect \p_valid_i$65 \p_valid_i connect \setup_stage_xer_so \input_xer_so$44 connect \setup_stage_rb \input_rb$43 connect \setup_stage_ra \input_ra$42 connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } connect \setup_stage_muxid \input_muxid$23 connect \input_xer_so \xer_so$22 connect \input_rb \rb$21 connect \input_ra \ra$20 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end attribute \src "libresoc.v:176109.1-176751.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount attribute \src "libresoc.v:176110.7-176110.20" wire $0\initial[0:0] attribute \src "libresoc.v:176598.3-176624.6" wire width 64 $0\o[63:0] attribute \src "libresoc.v:176598.3-176624.6" wire width 64 $1\o[63:0] attribute \src "libresoc.v:176522.19-176522.132" wire width 4 $add$libresoc.v:176522$10348_Y attribute \src "libresoc.v:176523.19-176523.132" wire width 4 $add$libresoc.v:176523$10349_Y attribute \src "libresoc.v:176524.19-176524.132" wire width 4 $add$libresoc.v:176524$10350_Y attribute \src "libresoc.v:176525.19-176525.132" wire width 4 $add$libresoc.v:176525$10351_Y attribute \src "libresoc.v:176526.19-176526.134" wire width 4 $add$libresoc.v:176526$10352_Y attribute \src "libresoc.v:176527.19-176527.134" wire width 4 $add$libresoc.v:176527$10353_Y attribute \src "libresoc.v:176528.18-176528.125" wire width 3 $add$libresoc.v:176528$10354_Y attribute \src "libresoc.v:176529.19-176529.134" wire width 4 $add$libresoc.v:176529$10355_Y attribute \src "libresoc.v:176530.19-176530.134" wire width 4 $add$libresoc.v:176530$10356_Y attribute \src "libresoc.v:176531.19-176531.134" wire width 4 $add$libresoc.v:176531$10357_Y attribute \src "libresoc.v:176532.19-176532.134" wire width 4 $add$libresoc.v:176532$10358_Y attribute \src "libresoc.v:176533.19-176533.134" wire width 4 $add$libresoc.v:176533$10359_Y attribute \src "libresoc.v:176534.19-176534.134" wire width 4 $add$libresoc.v:176534$10360_Y attribute \src "libresoc.v:176535.19-176535.134" wire width 4 $add$libresoc.v:176535$10361_Y attribute \src "libresoc.v:176536.19-176536.134" wire width 4 $add$libresoc.v:176536$10362_Y attribute \src "libresoc.v:176537.19-176537.134" wire width 4 $add$libresoc.v:176537$10363_Y attribute \src "libresoc.v:176538.19-176538.132" wire width 5 $add$libresoc.v:176538$10364_Y attribute \src "libresoc.v:176539.18-176539.125" wire width 3 $add$libresoc.v:176539$10365_Y attribute \src "libresoc.v:176540.19-176540.132" wire width 5 $add$libresoc.v:176540$10366_Y attribute \src "libresoc.v:176541.19-176541.132" wire width 5 $add$libresoc.v:176541$10367_Y attribute \src "libresoc.v:176542.19-176542.132" wire width 5 $add$libresoc.v:176542$10368_Y attribute \src "libresoc.v:176543.19-176543.132" wire width 5 $add$libresoc.v:176543$10369_Y attribute \src "libresoc.v:176544.19-176544.134" wire width 5 $add$libresoc.v:176544$10370_Y attribute \src "libresoc.v:176545.19-176545.134" wire width 5 $add$libresoc.v:176545$10371_Y attribute \src "libresoc.v:176546.19-176546.134" wire width 5 $add$libresoc.v:176546$10372_Y attribute \src "libresoc.v:176547.19-176547.132" wire width 6 $add$libresoc.v:176547$10373_Y attribute \src "libresoc.v:176548.19-176548.132" wire width 6 $add$libresoc.v:176548$10374_Y attribute \src "libresoc.v:176549.19-176549.132" wire width 6 $add$libresoc.v:176549$10375_Y attribute \src "libresoc.v:176550.18-176550.127" wire width 3 $add$libresoc.v:176550$10376_Y attribute \src "libresoc.v:176551.19-176551.132" wire width 6 $add$libresoc.v:176551$10377_Y attribute \src "libresoc.v:176552.19-176552.132" wire width 7 $add$libresoc.v:176552$10378_Y attribute \src "libresoc.v:176553.19-176553.132" wire width 7 $add$libresoc.v:176553$10379_Y attribute \src "libresoc.v:176554.19-176554.132" wire width 8 $add$libresoc.v:176554$10380_Y attribute \src "libresoc.v:176565.18-176565.127" wire width 3 $add$libresoc.v:176565$10399_Y attribute \src "libresoc.v:176569.18-176569.127" wire width 3 $add$libresoc.v:176569$10406_Y attribute \src "libresoc.v:176570.18-176570.127" wire width 3 $add$libresoc.v:176570$10407_Y attribute \src "libresoc.v:176571.17-176571.124" wire width 3 $add$libresoc.v:176571$10408_Y attribute \src "libresoc.v:176572.18-176572.127" wire width 3 $add$libresoc.v:176572$10409_Y attribute \src "libresoc.v:176573.18-176573.127" wire width 3 $add$libresoc.v:176573$10410_Y attribute \src "libresoc.v:176574.18-176574.127" wire width 3 $add$libresoc.v:176574$10411_Y attribute \src "libresoc.v:176575.18-176575.127" wire width 3 $add$libresoc.v:176575$10412_Y attribute \src "libresoc.v:176576.18-176576.127" wire width 3 $add$libresoc.v:176576$10413_Y attribute \src "libresoc.v:176577.18-176577.127" wire width 3 $add$libresoc.v:176577$10414_Y attribute \src "libresoc.v:176578.18-176578.127" wire width 3 $add$libresoc.v:176578$10415_Y attribute \src "libresoc.v:176579.18-176579.127" wire width 3 $add$libresoc.v:176579$10416_Y attribute \src "libresoc.v:176580.18-176580.127" wire width 3 $add$libresoc.v:176580$10417_Y attribute \src "libresoc.v:176581.18-176581.127" wire width 3 $add$libresoc.v:176581$10418_Y attribute \src "libresoc.v:176582.17-176582.124" wire width 3 $add$libresoc.v:176582$10419_Y attribute \src "libresoc.v:176583.18-176583.127" wire width 3 $add$libresoc.v:176583$10420_Y attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 4 \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 4 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len attribute \src "libresoc.v:176110.7-176110.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 2 \pop_2_9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 3 \pop_3_9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 4 \pop_4_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 5 \pop_5_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 5 \pop_5_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 5 \pop_5_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 5 \pop_5_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 6 \pop_6_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 6 \pop_6_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176522$10348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } connect \Y $add$libresoc.v:176522$10348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176523$10349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } connect \Y $add$libresoc.v:176523$10349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176524$10350 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } connect \Y $add$libresoc.v:176524$10350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176525$10351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } connect \Y $add$libresoc.v:176525$10351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176526$10352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } connect \Y $add$libresoc.v:176526$10352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176527$10353 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } connect \Y $add$libresoc.v:176527$10353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176528$10354 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } connect \Y $add$libresoc.v:176528$10354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176529$10355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } connect \Y $add$libresoc.v:176529$10355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176530$10356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } connect \Y $add$libresoc.v:176530$10356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176531$10357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } connect \Y $add$libresoc.v:176531$10357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176532$10358 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } connect \Y $add$libresoc.v:176532$10358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176533$10359 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } connect \Y $add$libresoc.v:176533$10359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176534$10360 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } connect \Y $add$libresoc.v:176534$10360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176535$10361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } connect \Y $add$libresoc.v:176535$10361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176536$10362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } connect \Y $add$libresoc.v:176536$10362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176537$10363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } connect \Y $add$libresoc.v:176537$10363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176538$10364 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } connect \Y $add$libresoc.v:176538$10364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176539$10365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } connect \Y $add$libresoc.v:176539$10365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176540$10366 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } connect \Y $add$libresoc.v:176540$10366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176541$10367 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } connect \Y $add$libresoc.v:176541$10367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176542$10368 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } connect \Y $add$libresoc.v:176542$10368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176543$10369 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } connect \Y $add$libresoc.v:176543$10369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176544$10370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } connect \Y $add$libresoc.v:176544$10370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176545$10371 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } connect \Y $add$libresoc.v:176545$10371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176546$10372 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } connect \Y $add$libresoc.v:176546$10372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176547$10373 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } connect \Y $add$libresoc.v:176547$10373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176548$10374 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } connect \Y $add$libresoc.v:176548$10374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176549$10375 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } connect \Y $add$libresoc.v:176549$10375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176550$10376 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } connect \Y $add$libresoc.v:176550$10376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176551$10377 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } connect \Y $add$libresoc.v:176551$10377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176552$10378 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } connect \Y $add$libresoc.v:176552$10378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176553$10379 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } connect \Y $add$libresoc.v:176553$10379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176554$10380 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } connect \Y $add$libresoc.v:176554$10380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176565$10399 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } connect \Y $add$libresoc.v:176565$10399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176569$10406 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } connect \Y $add$libresoc.v:176569$10406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176570$10407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } connect \Y $add$libresoc.v:176570$10407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176571$10408 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } connect \Y $add$libresoc.v:176571$10408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176572$10409 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } connect \Y $add$libresoc.v:176572$10409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176573$10410 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } connect \Y $add$libresoc.v:176573$10410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176574$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } connect \Y $add$libresoc.v:176574$10411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176575$10412 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } connect \Y $add$libresoc.v:176575$10412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176576$10413 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } connect \Y $add$libresoc.v:176576$10413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176577$10414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } connect \Y $add$libresoc.v:176577$10414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176578$10415 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } connect \Y $add$libresoc.v:176578$10415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176579$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } connect \Y $add$libresoc.v:176579$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176580$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } connect \Y $add$libresoc.v:176580$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176581$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } connect \Y $add$libresoc.v:176581$10418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176582$10419 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } connect \Y $add$libresoc.v:176582$10419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176583$10420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } connect \Y $add$libresoc.v:176583$10420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176584$10421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } connect \Y $add$libresoc.v:176584$10421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176585$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } connect \Y $add$libresoc.v:176585$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176586$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } connect \Y $add$libresoc.v:176586$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176587$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } connect \Y $add$libresoc.v:176587$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176588$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } connect \Y $add$libresoc.v:176588$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176589$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } connect \Y $add$libresoc.v:176589$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176590$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } connect \Y $add$libresoc.v:176590$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176591$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } connect \Y $add$libresoc.v:176591$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176592$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } connect \Y $add$libresoc.v:176592$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176593$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } connect \Y $add$libresoc.v:176593$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176594$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } connect \Y $add$libresoc.v:176594$10431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176595$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } connect \Y $add$libresoc.v:176595$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176596$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } connect \Y $add$libresoc.v:176596$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" cell $add $add$libresoc.v:176597$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } connect \Y $add$libresoc.v:176597$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" cell $eq $eq$libresoc.v:176555$10381 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 connect \Y $eq$libresoc.v:176555$10381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" cell $eq $eq$libresoc.v:176556$10382 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 connect \Y $eq$libresoc.v:176556$10382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176557$10383 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 connect \Y $extend$libresoc.v:176557$10383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176558$10385 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 connect \Y $extend$libresoc.v:176558$10385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176559$10387 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 connect \Y $extend$libresoc.v:176559$10387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176560$10389 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 connect \Y $extend$libresoc.v:176560$10389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176561$10391 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 connect \Y $extend$libresoc.v:176561$10391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176562$10393 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 connect \Y $extend$libresoc.v:176562$10393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176563$10395 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 connect \Y $extend$libresoc.v:176563$10395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176564$10397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 connect \Y $extend$libresoc.v:176564$10397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176566$10400 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 connect \Y $extend$libresoc.v:176566$10400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176567$10402 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 connect \Y $extend$libresoc.v:176567$10402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $extend$libresoc.v:176568$10404 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 connect \Y $extend$libresoc.v:176568$10404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176557$10384 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176557$10383_Y connect \Y $pos$libresoc.v:176557$10384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176558$10386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176558$10385_Y connect \Y $pos$libresoc.v:176558$10386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176559$10388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176559$10387_Y connect \Y $pos$libresoc.v:176559$10388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176560$10390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176560$10389_Y connect \Y $pos$libresoc.v:176560$10390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176561$10392 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176561$10391_Y connect \Y $pos$libresoc.v:176561$10392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176562$10394 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176562$10393_Y connect \Y $pos$libresoc.v:176562$10394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176563$10396 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176563$10395_Y connect \Y $pos$libresoc.v:176563$10396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176564$10398 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A $extend$libresoc.v:176564$10397_Y connect \Y $pos$libresoc.v:176564$10398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176566$10401 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 connect \A $extend$libresoc.v:176566$10400_Y connect \Y $pos$libresoc.v:176566$10401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176567$10403 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 connect \A $extend$libresoc.v:176567$10402_Y connect \Y $pos$libresoc.v:176567$10403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" cell $pos $pos$libresoc.v:176568$10405 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:176568$10404_Y connect \Y $pos$libresoc.v:176568$10405_Y end attribute \src "libresoc.v:176110.7-176110.20" process $proc$libresoc.v:176110$10436 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:176598.3-176624.6" process $proc$libresoc.v:176598$10435 assign { } { } assign $0\o[63:0] $1\o[63:0] attribute \src "libresoc.v:176599.5-176599.29" switch \initial attribute \src "libresoc.v:176599.9-176599.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" switch { \$192 \$190 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\o[63:0] [7:0] \$194 assign $1\o[63:0] [15:8] \$196 assign $1\o[63:0] [23:16] \$198 assign $1\o[63:0] [31:24] \$200 assign $1\o[63:0] [39:32] \$202 assign $1\o[63:0] [47:40] \$204 assign $1\o[63:0] [55:48] \$206 assign $1\o[63:0] [63:56] \$208 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\o[63:0] [31:0] \$210 assign $1\o[63:0] [63:32] \$212 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\o[63:0] \$214 end sync always update \o $0\o[63:0] end connect \$101 $add$libresoc.v:176522$10348_Y connect \$104 $add$libresoc.v:176523$10349_Y connect \$107 $add$libresoc.v:176524$10350_Y connect \$110 $add$libresoc.v:176525$10351_Y connect \$113 $add$libresoc.v:176526$10352_Y connect \$116 $add$libresoc.v:176527$10353_Y connect \$11 $add$libresoc.v:176528$10354_Y connect \$119 $add$libresoc.v:176529$10355_Y connect \$122 $add$libresoc.v:176530$10356_Y connect \$125 $add$libresoc.v:176531$10357_Y connect \$128 $add$libresoc.v:176532$10358_Y connect \$131 $add$libresoc.v:176533$10359_Y connect \$134 $add$libresoc.v:176534$10360_Y connect \$137 $add$libresoc.v:176535$10361_Y connect \$140 $add$libresoc.v:176536$10362_Y connect \$143 $add$libresoc.v:176537$10363_Y connect \$146 $add$libresoc.v:176538$10364_Y connect \$14 $add$libresoc.v:176539$10365_Y connect \$149 $add$libresoc.v:176540$10366_Y connect \$152 $add$libresoc.v:176541$10367_Y connect \$155 $add$libresoc.v:176542$10368_Y connect \$158 $add$libresoc.v:176543$10369_Y connect \$161 $add$libresoc.v:176544$10370_Y connect \$164 $add$libresoc.v:176545$10371_Y connect \$167 $add$libresoc.v:176546$10372_Y connect \$170 $add$libresoc.v:176547$10373_Y connect \$173 $add$libresoc.v:176548$10374_Y connect \$176 $add$libresoc.v:176549$10375_Y connect \$17 $add$libresoc.v:176550$10376_Y connect \$179 $add$libresoc.v:176551$10377_Y connect \$182 $add$libresoc.v:176552$10378_Y connect \$185 $add$libresoc.v:176553$10379_Y connect \$188 $add$libresoc.v:176554$10380_Y connect \$190 $eq$libresoc.v:176555$10381_Y connect \$192 $eq$libresoc.v:176556$10382_Y connect \$194 $pos$libresoc.v:176557$10384_Y connect \$196 $pos$libresoc.v:176558$10386_Y connect \$198 $pos$libresoc.v:176559$10388_Y connect \$200 $pos$libresoc.v:176560$10390_Y connect \$202 $pos$libresoc.v:176561$10392_Y connect \$204 $pos$libresoc.v:176562$10394_Y connect \$206 $pos$libresoc.v:176563$10396_Y connect \$208 $pos$libresoc.v:176564$10398_Y connect \$20 $add$libresoc.v:176565$10399_Y connect \$210 $pos$libresoc.v:176566$10401_Y connect \$212 $pos$libresoc.v:176567$10403_Y connect \$214 $pos$libresoc.v:176568$10405_Y connect \$23 $add$libresoc.v:176569$10406_Y connect \$26 $add$libresoc.v:176570$10407_Y connect \$2 $add$libresoc.v:176571$10408_Y connect \$29 $add$libresoc.v:176572$10409_Y connect \$32 $add$libresoc.v:176573$10410_Y connect \$35 $add$libresoc.v:176574$10411_Y connect \$38 $add$libresoc.v:176575$10412_Y connect \$41 $add$libresoc.v:176576$10413_Y connect \$44 $add$libresoc.v:176577$10414_Y connect \$47 $add$libresoc.v:176578$10415_Y connect \$50 $add$libresoc.v:176579$10416_Y connect \$53 $add$libresoc.v:176580$10417_Y connect \$56 $add$libresoc.v:176581$10418_Y connect \$5 $add$libresoc.v:176582$10419_Y connect \$59 $add$libresoc.v:176583$10420_Y connect \$62 $add$libresoc.v:176584$10421_Y connect \$65 $add$libresoc.v:176585$10422_Y connect \$68 $add$libresoc.v:176586$10423_Y connect \$71 $add$libresoc.v:176587$10424_Y connect \$74 $add$libresoc.v:176588$10425_Y connect \$77 $add$libresoc.v:176589$10426_Y connect \$80 $add$libresoc.v:176590$10427_Y connect \$83 $add$libresoc.v:176591$10428_Y connect \$86 $add$libresoc.v:176592$10429_Y connect \$8 $add$libresoc.v:176593$10430_Y connect \$89 $add$libresoc.v:176594$10431_Y connect \$92 $add$libresoc.v:176595$10432_Y connect \$95 $add$libresoc.v:176596$10433_Y connect \$98 $add$libresoc.v:176597$10434_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 connect \$10 \$11 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 connect \$25 \$26 connect \$28 \$29 connect \$31 \$32 connect \$34 \$35 connect \$37 \$38 connect \$40 \$41 connect \$43 \$44 connect \$46 \$47 connect \$49 \$50 connect \$52 \$53 connect \$55 \$56 connect \$58 \$59 connect \$61 \$62 connect \$64 \$65 connect \$67 \$68 connect \$70 \$71 connect \$73 \$74 connect \$76 \$77 connect \$79 \$80 connect \$82 \$83 connect \$85 \$86 connect \$88 \$89 connect \$91 \$92 connect \$94 \$95 connect \$97 \$98 connect \$100 \$101 connect \$103 \$104 connect \$106 \$107 connect \$109 \$110 connect \$112 \$113 connect \$115 \$116 connect \$118 \$119 connect \$121 \$122 connect \$124 \$125 connect \$127 \$128 connect \$130 \$131 connect \$133 \$134 connect \$136 \$137 connect \$139 \$140 connect \$142 \$143 connect \$145 \$146 connect \$148 \$149 connect \$151 \$152 connect \$154 \$155 connect \$157 \$158 connect \$160 \$161 connect \$163 \$164 connect \$166 \$167 connect \$169 \$170 connect \$172 \$173 connect \$175 \$176 connect \$178 \$179 connect \$181 \$182 connect \$184 \$185 connect \$187 \$188 connect \pop_7_0 \$188 [6:0] connect \pop_6_1 \$185 [5:0] connect \pop_6_0 \$182 [5:0] connect \pop_5_3 \$179 [4:0] connect \pop_5_2 \$176 [4:0] connect \pop_5_1 \$173 [4:0] connect \pop_5_0 \$170 [4:0] connect \pop_4_7 \$167 [3:0] connect \pop_4_6 \$164 [3:0] connect \pop_4_5 \$161 [3:0] connect \pop_4_4 \$158 [3:0] connect \pop_4_3 \$155 [3:0] connect \pop_4_2 \$152 [3:0] connect \pop_4_1 \$149 [3:0] connect \pop_4_0 \$146 [3:0] connect \pop_3_15 \$143 [2:0] connect \pop_3_14 \$140 [2:0] connect \pop_3_13 \$137 [2:0] connect \pop_3_12 \$134 [2:0] connect \pop_3_11 \$131 [2:0] connect \pop_3_10 \$128 [2:0] connect \pop_3_9 \$125 [2:0] connect \pop_3_8 \$122 [2:0] connect \pop_3_7 \$119 [2:0] connect \pop_3_6 \$116 [2:0] connect \pop_3_5 \$113 [2:0] connect \pop_3_4 \$110 [2:0] connect \pop_3_3 \$107 [2:0] connect \pop_3_2 \$104 [2:0] connect \pop_3_1 \$101 [2:0] connect \pop_3_0 \$98 [2:0] connect \pop_2_31 \$95 [1:0] connect \pop_2_30 \$92 [1:0] connect \pop_2_29 \$89 [1:0] connect \pop_2_28 \$86 [1:0] connect \pop_2_27 \$83 [1:0] connect \pop_2_26 \$80 [1:0] connect \pop_2_25 \$77 [1:0] connect \pop_2_24 \$74 [1:0] connect \pop_2_23 \$71 [1:0] connect \pop_2_22 \$68 [1:0] connect \pop_2_21 \$65 [1:0] connect \pop_2_20 \$62 [1:0] connect \pop_2_19 \$59 [1:0] connect \pop_2_18 \$56 [1:0] connect \pop_2_17 \$53 [1:0] connect \pop_2_16 \$50 [1:0] connect \pop_2_15 \$47 [1:0] connect \pop_2_14 \$44 [1:0] connect \pop_2_13 \$41 [1:0] connect \pop_2_12 \$38 [1:0] connect \pop_2_11 \$35 [1:0] connect \pop_2_10 \$32 [1:0] connect \pop_2_9 \$29 [1:0] connect \pop_2_8 \$26 [1:0] connect \pop_2_7 \$23 [1:0] connect \pop_2_6 \$20 [1:0] connect \pop_2_5 \$17 [1:0] connect \pop_2_4 \$14 [1:0] connect \pop_2_3 \$11 [1:0] connect \pop_2_2 \$8 [1:0] connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end attribute \src "libresoc.v:176755.1-176839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick attribute \src "libresoc.v:176812.17-176812.91" wire $not$libresoc.v:176812$10437_Y attribute \src "libresoc.v:176814.18-176814.93" wire $not$libresoc.v:176814$10439_Y attribute \src "libresoc.v:176816.18-176816.93" wire $not$libresoc.v:176816$10441_Y attribute \src "libresoc.v:176817.17-176817.138" wire width 8 $not$libresoc.v:176817$10442_Y attribute \src "libresoc.v:176819.18-176819.93" wire $not$libresoc.v:176819$10444_Y attribute \src "libresoc.v:176821.18-176821.93" wire $not$libresoc.v:176821$10446_Y attribute \src "libresoc.v:176823.18-176823.93" wire $not$libresoc.v:176823$10448_Y attribute \src "libresoc.v:176826.17-176826.91" wire $not$libresoc.v:176826$10451_Y attribute \src "libresoc.v:176813.18-176813.116" wire $reduce_or$libresoc.v:176813$10438_Y attribute \src "libresoc.v:176815.18-176815.122" wire $reduce_or$libresoc.v:176815$10440_Y attribute \src "libresoc.v:176818.18-176818.128" wire $reduce_or$libresoc.v:176818$10443_Y attribute \src "libresoc.v:176820.18-176820.134" wire $reduce_or$libresoc.v:176820$10445_Y attribute \src "libresoc.v:176822.18-176822.140" wire $reduce_or$libresoc.v:176822$10447_Y attribute \src "libresoc.v:176824.18-176824.90" wire $reduce_or$libresoc.v:176824$10449_Y attribute \src "libresoc.v:176825.17-176825.103" wire $reduce_or$libresoc.v:176825$10450_Y attribute \src "libresoc.v:176827.17-176827.109" wire $reduce_or$libresoc.v:176827$10452_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 input 2 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 8 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176812$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:176812$10437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176814$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:176814$10439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176816$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:176816$10441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:176817$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } connect \Y $not$libresoc.v:176817$10442_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176819$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 connect \Y $not$libresoc.v:176819$10444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176821$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:176821$10446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176823$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 connect \Y $not$libresoc.v:176823$10448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176826$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:176826$10451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176813$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } connect \Y $reduce_or$libresoc.v:176813$10438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176815$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } connect \Y $reduce_or$libresoc.v:176815$10440_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176818$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } connect \Y $reduce_or$libresoc.v:176818$10443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176820$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } connect \Y $reduce_or$libresoc.v:176820$10445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176822$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } connect \Y $reduce_or$libresoc.v:176822$10447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:176824$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:176824$10449_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176825$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } connect \Y $reduce_or$libresoc.v:176825$10450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176827$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } connect \Y $reduce_or$libresoc.v:176827$10452_Y end connect \$7 $not$libresoc.v:176812$10437_Y connect \$12 $reduce_or$libresoc.v:176813$10438_Y connect \$11 $not$libresoc.v:176814$10439_Y connect \$16 $reduce_or$libresoc.v:176815$10440_Y connect \$15 $not$libresoc.v:176816$10441_Y connect \$1 $not$libresoc.v:176817$10442_Y connect \$20 $reduce_or$libresoc.v:176818$10443_Y connect \$19 $not$libresoc.v:176819$10444_Y connect \$24 $reduce_or$libresoc.v:176820$10445_Y connect \$23 $not$libresoc.v:176821$10446_Y connect \$28 $reduce_or$libresoc.v:176822$10447_Y connect \$27 $not$libresoc.v:176823$10448_Y connect \$31 $reduce_or$libresoc.v:176824$10449_Y connect \$4 $reduce_or$libresoc.v:176825$10450_Y connect \$3 $not$libresoc.v:176826$10451_Y connect \$8 $reduce_or$libresoc.v:176827$10452_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 connect \t6 \$23 connect \t5 \$19 connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [7] connect \ni \$1 end attribute \src "libresoc.v:176843.1-176927.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 attribute \src "libresoc.v:176900.17-176900.91" wire $not$libresoc.v:176900$10453_Y attribute \src "libresoc.v:176902.18-176902.93" wire $not$libresoc.v:176902$10455_Y attribute \src "libresoc.v:176904.18-176904.93" wire $not$libresoc.v:176904$10457_Y attribute \src "libresoc.v:176905.17-176905.138" wire width 8 $not$libresoc.v:176905$10458_Y attribute \src "libresoc.v:176907.18-176907.93" wire $not$libresoc.v:176907$10460_Y attribute \src "libresoc.v:176909.18-176909.93" wire $not$libresoc.v:176909$10462_Y attribute \src "libresoc.v:176911.18-176911.93" wire $not$libresoc.v:176911$10464_Y attribute \src "libresoc.v:176914.17-176914.91" wire $not$libresoc.v:176914$10467_Y attribute \src "libresoc.v:176901.18-176901.116" wire $reduce_or$libresoc.v:176901$10454_Y attribute \src "libresoc.v:176903.18-176903.122" wire $reduce_or$libresoc.v:176903$10456_Y attribute \src "libresoc.v:176906.18-176906.128" wire $reduce_or$libresoc.v:176906$10459_Y attribute \src "libresoc.v:176908.18-176908.134" wire $reduce_or$libresoc.v:176908$10461_Y attribute \src "libresoc.v:176910.18-176910.140" wire $reduce_or$libresoc.v:176910$10463_Y attribute \src "libresoc.v:176912.18-176912.90" wire $reduce_or$libresoc.v:176912$10465_Y attribute \src "libresoc.v:176913.17-176913.103" wire $reduce_or$libresoc.v:176913$10466_Y attribute \src "libresoc.v:176915.17-176915.109" wire $reduce_or$libresoc.v:176915$10468_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 1 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 8 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176900$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:176900$10453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176902$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:176902$10455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176904$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:176904$10457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:176905$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } connect \Y $not$libresoc.v:176905$10458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176907$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 connect \Y $not$libresoc.v:176907$10460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176909$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:176909$10462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176911$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 connect \Y $not$libresoc.v:176911$10464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176914$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:176914$10467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176901$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } connect \Y $reduce_or$libresoc.v:176901$10454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176903$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } connect \Y $reduce_or$libresoc.v:176903$10456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176906$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } connect \Y $reduce_or$libresoc.v:176906$10459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176908$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } connect \Y $reduce_or$libresoc.v:176908$10461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176910$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } connect \Y $reduce_or$libresoc.v:176910$10463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:176912$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:176912$10465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176913$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } connect \Y $reduce_or$libresoc.v:176913$10466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176915$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } connect \Y $reduce_or$libresoc.v:176915$10468_Y end connect \$7 $not$libresoc.v:176900$10453_Y connect \$12 $reduce_or$libresoc.v:176901$10454_Y connect \$11 $not$libresoc.v:176902$10455_Y connect \$16 $reduce_or$libresoc.v:176903$10456_Y connect \$15 $not$libresoc.v:176904$10457_Y connect \$1 $not$libresoc.v:176905$10458_Y connect \$20 $reduce_or$libresoc.v:176906$10459_Y connect \$19 $not$libresoc.v:176907$10460_Y connect \$24 $reduce_or$libresoc.v:176908$10461_Y connect \$23 $not$libresoc.v:176909$10462_Y connect \$28 $reduce_or$libresoc.v:176910$10463_Y connect \$27 $not$libresoc.v:176911$10464_Y connect \$31 $reduce_or$libresoc.v:176912$10465_Y connect \$4 $reduce_or$libresoc.v:176913$10466_Y connect \$3 $not$libresoc.v:176914$10467_Y connect \$8 $reduce_or$libresoc.v:176915$10468_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 connect \t6 \$23 connect \t5 \$19 connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [7] connect \ni \$1 end attribute \src "libresoc.v:176931.1-176961.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a attribute \src "libresoc.v:176952.17-176952.89" wire width 2 $not$libresoc.v:176952$10469_Y attribute \src "libresoc.v:176954.17-176954.91" wire $not$libresoc.v:176954$10471_Y attribute \src "libresoc.v:176953.17-176953.103" wire $reduce_or$libresoc.v:176953$10470_Y attribute \src "libresoc.v:176955.17-176955.89" wire $reduce_or$libresoc.v:176955$10472_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 2 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:176952$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i connect \Y $not$libresoc.v:176952$10469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:176954$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:176954$10471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:176953$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:176953$10470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:176955$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:176955$10472_Y end connect \$1 $not$libresoc.v:176952$10469_Y connect \$4 $reduce_or$libresoc.v:176953$10470_Y connect \$3 $not$libresoc.v:176954$10471_Y connect \$7 $reduce_or$libresoc.v:176955$10472_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:176965.1-176986.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b attribute \src "libresoc.v:176980.17-176980.89" wire $not$libresoc.v:176980$10473_Y attribute \src "libresoc.v:176981.17-176981.89" wire $reduce_or$libresoc.v:176981$10474_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:176980$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:176980$10473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:176981$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:176981$10474_Y end connect \$1 $not$libresoc.v:176980$10473_Y connect \$3 $reduce_or$libresoc.v:176981$10474_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:176990.1-177011.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c attribute \src "libresoc.v:177005.17-177005.89" wire $not$libresoc.v:177005$10475_Y attribute \src "libresoc.v:177006.17-177006.89" wire $reduce_or$libresoc.v:177006$10476_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177005$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:177005$10475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177006$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177006$10476_Y end connect \$1 $not$libresoc.v:177005$10475_Y connect \$3 $reduce_or$libresoc.v:177006$10476_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:177015.1-177036.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr attribute \src "libresoc.v:177030.17-177030.89" wire $not$libresoc.v:177030$10477_Y attribute \src "libresoc.v:177031.17-177031.89" wire $reduce_or$libresoc.v:177031$10478_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177030$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:177030$10477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177031$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177031$10478_Y end connect \$1 $not$libresoc.v:177030$10477_Y connect \$3 $reduce_or$libresoc.v:177031$10478_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:177040.1-177097.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 attribute \src "libresoc.v:177079.17-177079.91" wire $not$libresoc.v:177079$10479_Y attribute \src "libresoc.v:177081.18-177081.93" wire $not$libresoc.v:177081$10481_Y attribute \src "libresoc.v:177083.18-177083.93" wire $not$libresoc.v:177083$10483_Y attribute \src "libresoc.v:177084.17-177084.89" wire width 5 $not$libresoc.v:177084$10484_Y attribute \src "libresoc.v:177087.17-177087.91" wire $not$libresoc.v:177087$10487_Y attribute \src "libresoc.v:177080.18-177080.106" wire $reduce_or$libresoc.v:177080$10480_Y attribute \src "libresoc.v:177082.18-177082.106" wire $reduce_or$libresoc.v:177082$10482_Y attribute \src "libresoc.v:177085.18-177085.90" wire $reduce_or$libresoc.v:177085$10485_Y attribute \src "libresoc.v:177086.17-177086.103" wire $reduce_or$libresoc.v:177086$10486_Y attribute \src "libresoc.v:177088.17-177088.105" wire $reduce_or$libresoc.v:177088$10488_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 5 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 5 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 5 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177079$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:177079$10479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177081$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:177081$10481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177083$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:177083$10483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177084$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i connect \Y $not$libresoc.v:177084$10484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177087$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:177087$10487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177080$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:177080$10480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177082$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } connect \Y $reduce_or$libresoc.v:177082$10482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177085$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177085$10485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177086$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:177086$10486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177088$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:177088$10488_Y end connect \$7 $not$libresoc.v:177079$10479_Y connect \$12 $reduce_or$libresoc.v:177080$10480_Y connect \$11 $not$libresoc.v:177081$10481_Y connect \$16 $reduce_or$libresoc.v:177082$10482_Y connect \$15 $not$libresoc.v:177083$10483_Y connect \$1 $not$libresoc.v:177084$10484_Y connect \$19 $reduce_or$libresoc.v:177085$10485_Y connect \$4 $reduce_or$libresoc.v:177086$10486_Y connect \$3 $not$libresoc.v:177087$10487_Y connect \$8 $reduce_or$libresoc.v:177088$10488_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:177101.1-177284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rabc" attribute \generator "nMigen" module \rdpick_INT_rabc attribute \src "libresoc.v:177224.17-177224.91" wire $not$libresoc.v:177224$10489_Y attribute \src "libresoc.v:177226.18-177226.93" wire $not$libresoc.v:177226$10491_Y attribute \src "libresoc.v:177228.18-177228.93" wire $not$libresoc.v:177228$10493_Y attribute \src "libresoc.v:177229.17-177229.89" wire width 19 $not$libresoc.v:177229$10494_Y attribute \src "libresoc.v:177231.18-177231.93" wire $not$libresoc.v:177231$10496_Y attribute \src "libresoc.v:177233.18-177233.93" wire $not$libresoc.v:177233$10498_Y attribute \src "libresoc.v:177235.18-177235.93" wire $not$libresoc.v:177235$10500_Y attribute \src "libresoc.v:177237.18-177237.93" wire $not$libresoc.v:177237$10502_Y attribute \src "libresoc.v:177239.18-177239.93" wire $not$libresoc.v:177239$10504_Y attribute \src "libresoc.v:177241.18-177241.93" wire $not$libresoc.v:177241$10506_Y attribute \src "libresoc.v:177243.18-177243.93" wire $not$libresoc.v:177243$10508_Y attribute \src "libresoc.v:177246.18-177246.93" wire $not$libresoc.v:177246$10511_Y attribute \src "libresoc.v:177248.18-177248.93" wire $not$libresoc.v:177248$10513_Y attribute \src "libresoc.v:177250.18-177250.93" wire $not$libresoc.v:177250$10515_Y attribute \src "libresoc.v:177251.17-177251.91" wire $not$libresoc.v:177251$10516_Y attribute \src "libresoc.v:177253.18-177253.93" wire $not$libresoc.v:177253$10518_Y attribute \src "libresoc.v:177255.18-177255.93" wire $not$libresoc.v:177255$10520_Y attribute \src "libresoc.v:177257.18-177257.93" wire $not$libresoc.v:177257$10522_Y attribute \src "libresoc.v:177259.18-177259.93" wire $not$libresoc.v:177259$10524_Y attribute \src "libresoc.v:177225.18-177225.106" wire $reduce_or$libresoc.v:177225$10490_Y attribute \src "libresoc.v:177227.18-177227.106" wire $reduce_or$libresoc.v:177227$10492_Y attribute \src "libresoc.v:177230.18-177230.106" wire $reduce_or$libresoc.v:177230$10495_Y attribute \src "libresoc.v:177232.18-177232.106" wire $reduce_or$libresoc.v:177232$10497_Y attribute \src "libresoc.v:177234.18-177234.106" wire $reduce_or$libresoc.v:177234$10499_Y attribute \src "libresoc.v:177236.18-177236.106" wire $reduce_or$libresoc.v:177236$10501_Y attribute \src "libresoc.v:177238.18-177238.106" wire $reduce_or$libresoc.v:177238$10503_Y attribute \src "libresoc.v:177240.18-177240.107" wire $reduce_or$libresoc.v:177240$10505_Y attribute \src "libresoc.v:177242.18-177242.108" wire $reduce_or$libresoc.v:177242$10507_Y attribute \src "libresoc.v:177244.18-177244.108" wire $reduce_or$libresoc.v:177244$10509_Y attribute \src "libresoc.v:177245.17-177245.103" wire $reduce_or$libresoc.v:177245$10510_Y attribute \src "libresoc.v:177247.18-177247.108" wire $reduce_or$libresoc.v:177247$10512_Y attribute \src "libresoc.v:177249.18-177249.108" wire $reduce_or$libresoc.v:177249$10514_Y attribute \src "libresoc.v:177252.18-177252.108" wire $reduce_or$libresoc.v:177252$10517_Y attribute \src "libresoc.v:177254.18-177254.108" wire $reduce_or$libresoc.v:177254$10519_Y attribute \src "libresoc.v:177256.18-177256.108" wire $reduce_or$libresoc.v:177256$10521_Y attribute \src "libresoc.v:177258.18-177258.108" wire $reduce_or$libresoc.v:177258$10523_Y attribute \src "libresoc.v:177260.18-177260.90" wire $reduce_or$libresoc.v:177260$10525_Y attribute \src "libresoc.v:177261.17-177261.105" wire $reduce_or$libresoc.v:177261$10526_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 19 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$35 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$64 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$72 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 19 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 19 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 19 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177224$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:177224$10489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177226$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:177226$10491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177228$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:177228$10493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177229$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 19 connect \A \i connect \Y $not$libresoc.v:177229$10494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177231$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 connect \Y $not$libresoc.v:177231$10496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177233$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:177233$10498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177235$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 connect \Y $not$libresoc.v:177235$10500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177237$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 connect \Y $not$libresoc.v:177237$10502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177239$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 connect \Y $not$libresoc.v:177239$10504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177241$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$40 connect \Y $not$libresoc.v:177241$10506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177243$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \Y $not$libresoc.v:177243$10508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177246$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$48 connect \Y $not$libresoc.v:177246$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177248$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$52 connect \Y $not$libresoc.v:177248$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177250$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$56 connect \Y $not$libresoc.v:177250$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177251$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:177251$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177253$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$60 connect \Y $not$libresoc.v:177253$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177255$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 connect \Y $not$libresoc.v:177255$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177257$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$68 connect \Y $not$libresoc.v:177257$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177259$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$72 connect \Y $not$libresoc.v:177259$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177225$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:177225$10490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177227$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } connect \Y $reduce_or$libresoc.v:177227$10492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177230$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } connect \Y $reduce_or$libresoc.v:177230$10495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177232$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } connect \Y $reduce_or$libresoc.v:177232$10497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177234$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } connect \Y $reduce_or$libresoc.v:177234$10499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177236$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } connect \Y $reduce_or$libresoc.v:177236$10501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177238$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } connect \Y $reduce_or$libresoc.v:177238$10503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177240$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 11 parameter \Y_WIDTH 1 connect \A { \i [9:0] \ni [10] } connect \Y $reduce_or$libresoc.v:177240$10505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177242$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 connect \A { \i [10:0] \ni [11] } connect \Y $reduce_or$libresoc.v:177242$10507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177244$10509 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A { \i [11:0] \ni [12] } connect \Y $reduce_or$libresoc.v:177244$10509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177245$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:177245$10510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177247$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A { \i [12:0] \ni [13] } connect \Y $reduce_or$libresoc.v:177247$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177249$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \Y_WIDTH 1 connect \A { \i [13:0] \ni [14] } connect \Y $reduce_or$libresoc.v:177249$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177252$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 1 connect \A { \i [14:0] \ni [15] } connect \Y $reduce_or$libresoc.v:177252$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177254$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \Y_WIDTH 1 connect \A { \i [15:0] \ni [16] } connect \Y $reduce_or$libresoc.v:177254$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177256$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 18 parameter \Y_WIDTH 1 connect \A { \i [16:0] \ni [17] } connect \Y $reduce_or$libresoc.v:177256$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177258$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 1 connect \A { \i [17:0] \ni [18] } connect \Y $reduce_or$libresoc.v:177258$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177260$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 19 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177260$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177261$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:177261$10526_Y end connect \$7 $not$libresoc.v:177224$10489_Y connect \$12 $reduce_or$libresoc.v:177225$10490_Y connect \$11 $not$libresoc.v:177226$10491_Y connect \$16 $reduce_or$libresoc.v:177227$10492_Y connect \$15 $not$libresoc.v:177228$10493_Y connect \$1 $not$libresoc.v:177229$10494_Y connect \$20 $reduce_or$libresoc.v:177230$10495_Y connect \$19 $not$libresoc.v:177231$10496_Y connect \$24 $reduce_or$libresoc.v:177232$10497_Y connect \$23 $not$libresoc.v:177233$10498_Y connect \$28 $reduce_or$libresoc.v:177234$10499_Y connect \$27 $not$libresoc.v:177235$10500_Y connect \$32 $reduce_or$libresoc.v:177236$10501_Y connect \$31 $not$libresoc.v:177237$10502_Y connect \$36 $reduce_or$libresoc.v:177238$10503_Y connect \$35 $not$libresoc.v:177239$10504_Y connect \$40 $reduce_or$libresoc.v:177240$10505_Y connect \$39 $not$libresoc.v:177241$10506_Y connect \$44 $reduce_or$libresoc.v:177242$10507_Y connect \$43 $not$libresoc.v:177243$10508_Y connect \$48 $reduce_or$libresoc.v:177244$10509_Y connect \$4 $reduce_or$libresoc.v:177245$10510_Y connect \$47 $not$libresoc.v:177246$10511_Y connect \$52 $reduce_or$libresoc.v:177247$10512_Y connect \$51 $not$libresoc.v:177248$10513_Y connect \$56 $reduce_or$libresoc.v:177249$10514_Y connect \$55 $not$libresoc.v:177250$10515_Y connect \$3 $not$libresoc.v:177251$10516_Y connect \$60 $reduce_or$libresoc.v:177252$10517_Y connect \$59 $not$libresoc.v:177253$10518_Y connect \$64 $reduce_or$libresoc.v:177254$10519_Y connect \$63 $not$libresoc.v:177255$10520_Y connect \$68 $reduce_or$libresoc.v:177256$10521_Y connect \$67 $not$libresoc.v:177257$10522_Y connect \$72 $reduce_or$libresoc.v:177258$10523_Y connect \$71 $not$libresoc.v:177259$10524_Y connect \$75 $reduce_or$libresoc.v:177260$10525_Y connect \$8 $reduce_or$libresoc.v:177261$10526_Y connect \en_o \$75 connect \o { \t18 \t17 \t16 \t15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t18 \$71 connect \t17 \$67 connect \t16 \$63 connect \t15 \$59 connect \t14 \$55 connect \t13 \$51 connect \t12 \$47 connect \t11 \$43 connect \t10 \$39 connect \t9 \$35 connect \t8 \$31 connect \t7 \$27 connect \t6 \$23 connect \t5 \$19 connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:177288.1-177309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 attribute \src "libresoc.v:177303.17-177303.89" wire $not$libresoc.v:177303$10527_Y attribute \src "libresoc.v:177304.17-177304.89" wire $reduce_or$libresoc.v:177304$10528_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177303$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:177303$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177304$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177304$10528_Y end connect \$1 $not$libresoc.v:177303$10527_Y connect \$3 $reduce_or$libresoc.v:177304$10528_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:177313.1-177352.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca attribute \src "libresoc.v:177340.17-177340.91" wire $not$libresoc.v:177340$10529_Y attribute \src "libresoc.v:177342.17-177342.89" wire width 3 $not$libresoc.v:177342$10531_Y attribute \src "libresoc.v:177344.17-177344.91" wire $not$libresoc.v:177344$10533_Y attribute \src "libresoc.v:177341.18-177341.90" wire $reduce_or$libresoc.v:177341$10530_Y attribute \src "libresoc.v:177343.17-177343.103" wire $reduce_or$libresoc.v:177343$10532_Y attribute \src "libresoc.v:177345.17-177345.105" wire $reduce_or$libresoc.v:177345$10534_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 3 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177340$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:177340$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177342$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i connect \Y $not$libresoc.v:177342$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177344$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:177344$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177341$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177341$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177343$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:177343$10532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177345$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:177345$10534_Y end connect \$7 $not$libresoc.v:177340$10529_Y connect \$11 $reduce_or$libresoc.v:177341$10530_Y connect \$1 $not$libresoc.v:177342$10531_Y connect \$4 $reduce_or$libresoc.v:177343$10532_Y connect \$3 $not$libresoc.v:177344$10533_Y connect \$8 $reduce_or$libresoc.v:177345$10534_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:177356.1-177377.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov attribute \src "libresoc.v:177371.17-177371.89" wire $not$libresoc.v:177371$10535_Y attribute \src "libresoc.v:177372.17-177372.89" wire $reduce_or$libresoc.v:177372$10536_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177371$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:177371$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177372$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177372$10536_Y end connect \$1 $not$libresoc.v:177371$10535_Y connect \$3 $reduce_or$libresoc.v:177372$10536_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:177381.1-177447.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so attribute \src "libresoc.v:177426.17-177426.91" wire $not$libresoc.v:177426$10537_Y attribute \src "libresoc.v:177428.18-177428.93" wire $not$libresoc.v:177428$10539_Y attribute \src "libresoc.v:177430.18-177430.93" wire $not$libresoc.v:177430$10541_Y attribute \src "libresoc.v:177431.17-177431.89" wire width 6 $not$libresoc.v:177431$10542_Y attribute \src "libresoc.v:177433.18-177433.93" wire $not$libresoc.v:177433$10544_Y attribute \src "libresoc.v:177436.17-177436.91" wire $not$libresoc.v:177436$10547_Y attribute \src "libresoc.v:177427.18-177427.106" wire $reduce_or$libresoc.v:177427$10538_Y attribute \src "libresoc.v:177429.18-177429.106" wire $reduce_or$libresoc.v:177429$10540_Y attribute \src "libresoc.v:177432.18-177432.106" wire $reduce_or$libresoc.v:177432$10543_Y attribute \src "libresoc.v:177434.18-177434.90" wire $reduce_or$libresoc.v:177434$10545_Y attribute \src "libresoc.v:177435.17-177435.103" wire $reduce_or$libresoc.v:177435$10546_Y attribute \src "libresoc.v:177437.17-177437.105" wire $reduce_or$libresoc.v:177437$10548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 6 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177426$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:177426$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177428$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:177428$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177430$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:177430$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:177431$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i connect \Y $not$libresoc.v:177431$10542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177433$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 connect \Y $not$libresoc.v:177433$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:177436$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:177436$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177427$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:177427$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177429$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } connect \Y $reduce_or$libresoc.v:177429$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177432$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } connect \Y $reduce_or$libresoc.v:177432$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:177434$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:177434$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177435$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:177435$10546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:177437$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:177437$10548_Y end connect \$7 $not$libresoc.v:177426$10537_Y connect \$12 $reduce_or$libresoc.v:177427$10538_Y connect \$11 $not$libresoc.v:177428$10539_Y connect \$16 $reduce_or$libresoc.v:177429$10540_Y connect \$15 $not$libresoc.v:177430$10541_Y connect \$1 $not$libresoc.v:177431$10542_Y connect \$20 $reduce_or$libresoc.v:177432$10543_Y connect \$19 $not$libresoc.v:177433$10544_Y connect \$23 $reduce_or$libresoc.v:177434$10545_Y connect \$4 $reduce_or$libresoc.v:177435$10546_Y connect \$3 $not$libresoc.v:177436$10547_Y connect \$8 $reduce_or$libresoc.v:177437$10548_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:177451.1-177922.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 attribute \src "libresoc.v:177452.7-177452.20" wire $0\initial[0:0] attribute \src "libresoc.v:177782.3-177821.6" wire width 4 $0\r0__data_o$next[3:0]$10604 attribute \src "libresoc.v:177537.3-177538.37" wire width 4 $0\r0__data_o[3:0] attribute \src "libresoc.v:177852.3-177891.6" wire width 4 $0\r20__data_o$next[3:0]$10618 attribute \src "libresoc.v:177535.3-177536.39" wire width 4 $0\r20__data_o[3:0] attribute \src "libresoc.v:177615.3-177641.6" wire width 4 $0\reg$next[3:0]$10570 attribute \src "libresoc.v:177533.3-177534.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:177545.3-177584.6" wire width 4 $0\src10__data_o$next[3:0]$10561 attribute \src "libresoc.v:177543.3-177544.43" wire width 4 $0\src10__data_o[3:0] attribute \src "libresoc.v:177642.3-177681.6" wire width 4 $0\src20__data_o$next[3:0]$10576 attribute \src "libresoc.v:177541.3-177542.43" wire width 4 $0\src20__data_o[3:0] attribute \src "libresoc.v:177712.3-177751.6" wire width 4 $0\src30__data_o$next[3:0]$10590 attribute \src "libresoc.v:177539.3-177540.43" wire width 4 $0\src30__data_o[3:0] attribute \src "libresoc.v:177822.3-177851.6" wire $0\wr_detect$10[0:0]$10612 attribute \src "libresoc.v:177892.3-177921.6" wire $0\wr_detect$13[0:0]$10626 attribute \src "libresoc.v:177682.3-177711.6" wire $0\wr_detect$4[0:0]$10584 attribute \src "libresoc.v:177752.3-177781.6" wire $0\wr_detect$7[0:0]$10598 attribute \src "libresoc.v:177585.3-177614.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:177782.3-177821.6" wire width 4 $1\r0__data_o$next[3:0]$10605 attribute \src "libresoc.v:177477.13-177477.30" wire width 4 $1\r0__data_o[3:0] attribute \src "libresoc.v:177852.3-177891.6" wire width 4 $1\r20__data_o$next[3:0]$10619 attribute \src "libresoc.v:177484.13-177484.31" wire width 4 $1\r20__data_o[3:0] attribute \src "libresoc.v:177615.3-177641.6" wire width 4 $1\reg$next[3:0]$10571 attribute \src "libresoc.v:177490.13-177490.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:177545.3-177584.6" wire width 4 $1\src10__data_o$next[3:0]$10562 attribute \src "libresoc.v:177495.13-177495.33" wire width 4 $1\src10__data_o[3:0] attribute \src "libresoc.v:177642.3-177681.6" wire width 4 $1\src20__data_o$next[3:0]$10577 attribute \src "libresoc.v:177502.13-177502.33" wire width 4 $1\src20__data_o[3:0] attribute \src "libresoc.v:177712.3-177751.6" wire width 4 $1\src30__data_o$next[3:0]$10591 attribute \src "libresoc.v:177509.13-177509.33" wire width 4 $1\src30__data_o[3:0] attribute \src "libresoc.v:177822.3-177851.6" wire $1\wr_detect$10[0:0]$10613 attribute \src "libresoc.v:177892.3-177921.6" wire $1\wr_detect$13[0:0]$10627 attribute \src "libresoc.v:177682.3-177711.6" wire $1\wr_detect$4[0:0]$10585 attribute \src "libresoc.v:177752.3-177781.6" wire $1\wr_detect$7[0:0]$10599 attribute \src "libresoc.v:177585.3-177614.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:177782.3-177821.6" wire width 4 $2\r0__data_o$next[3:0]$10606 attribute \src "libresoc.v:177852.3-177891.6" wire width 4 $2\r20__data_o$next[3:0]$10620 attribute \src "libresoc.v:177615.3-177641.6" wire width 4 $2\reg$next[3:0]$10572 attribute \src "libresoc.v:177545.3-177584.6" wire width 4 $2\src10__data_o$next[3:0]$10563 attribute \src "libresoc.v:177642.3-177681.6" wire width 4 $2\src20__data_o$next[3:0]$10578 attribute \src "libresoc.v:177712.3-177751.6" wire width 4 $2\src30__data_o$next[3:0]$10592 attribute \src "libresoc.v:177822.3-177851.6" wire $2\wr_detect$10[0:0]$10614 attribute \src "libresoc.v:177892.3-177921.6" wire $2\wr_detect$13[0:0]$10628 attribute \src "libresoc.v:177682.3-177711.6" wire $2\wr_detect$4[0:0]$10586 attribute \src "libresoc.v:177752.3-177781.6" wire $2\wr_detect$7[0:0]$10600 attribute \src "libresoc.v:177585.3-177614.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:177782.3-177821.6" wire width 4 $3\r0__data_o$next[3:0]$10607 attribute \src "libresoc.v:177852.3-177891.6" wire width 4 $3\r20__data_o$next[3:0]$10621 attribute \src "libresoc.v:177615.3-177641.6" wire width 4 $3\reg$next[3:0]$10573 attribute \src "libresoc.v:177545.3-177584.6" wire width 4 $3\src10__data_o$next[3:0]$10564 attribute \src "libresoc.v:177642.3-177681.6" wire width 4 $3\src20__data_o$next[3:0]$10579 attribute \src "libresoc.v:177712.3-177751.6" wire width 4 $3\src30__data_o$next[3:0]$10593 attribute \src "libresoc.v:177822.3-177851.6" wire $3\wr_detect$10[0:0]$10615 attribute \src "libresoc.v:177892.3-177921.6" wire $3\wr_detect$13[0:0]$10629 attribute \src "libresoc.v:177682.3-177711.6" wire $3\wr_detect$4[0:0]$10587 attribute \src "libresoc.v:177752.3-177781.6" wire $3\wr_detect$7[0:0]$10601 attribute \src "libresoc.v:177585.3-177614.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:177782.3-177821.6" wire width 4 $4\r0__data_o$next[3:0]$10608 attribute \src "libresoc.v:177852.3-177891.6" wire width 4 $4\r20__data_o$next[3:0]$10622 attribute \src "libresoc.v:177615.3-177641.6" wire width 4 $4\reg$next[3:0]$10574 attribute \src "libresoc.v:177545.3-177584.6" wire width 4 $4\src10__data_o$next[3:0]$10565 attribute \src "libresoc.v:177642.3-177681.6" wire width 4 $4\src20__data_o$next[3:0]$10580 attribute \src "libresoc.v:177712.3-177751.6" wire width 4 $4\src30__data_o$next[3:0]$10594 attribute \src "libresoc.v:177822.3-177851.6" wire $4\wr_detect$10[0:0]$10616 attribute \src "libresoc.v:177892.3-177921.6" wire $4\wr_detect$13[0:0]$10630 attribute \src "libresoc.v:177682.3-177711.6" wire $4\wr_detect$4[0:0]$10588 attribute \src "libresoc.v:177752.3-177781.6" wire $4\wr_detect$7[0:0]$10602 attribute \src "libresoc.v:177585.3-177614.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:177782.3-177821.6" wire width 4 $5\r0__data_o$next[3:0]$10609 attribute \src "libresoc.v:177852.3-177891.6" wire width 4 $5\r20__data_o$next[3:0]$10623 attribute \src "libresoc.v:177545.3-177584.6" wire width 4 $5\src10__data_o$next[3:0]$10566 attribute \src "libresoc.v:177642.3-177681.6" wire width 4 $5\src20__data_o$next[3:0]$10581 attribute \src "libresoc.v:177712.3-177751.6" wire width 4 $5\src30__data_o$next[3:0]$10595 attribute \src "libresoc.v:177782.3-177821.6" wire width 4 $6\r0__data_o$next[3:0]$10610 attribute \src "libresoc.v:177852.3-177891.6" wire width 4 $6\r20__data_o$next[3:0]$10624 attribute \src "libresoc.v:177545.3-177584.6" wire width 4 $6\src10__data_o$next[3:0]$10567 attribute \src "libresoc.v:177642.3-177681.6" wire width 4 $6\src20__data_o$next[3:0]$10582 attribute \src "libresoc.v:177712.3-177751.6" wire width 4 $6\src30__data_o$next[3:0]$10596 attribute \src "libresoc.v:177528.17-177528.104" wire $not$libresoc.v:177528$10549_Y attribute \src "libresoc.v:177529.18-177529.105" wire $not$libresoc.v:177529$10550_Y attribute \src "libresoc.v:177530.17-177530.100" wire $not$libresoc.v:177530$10551_Y attribute \src "libresoc.v:177531.17-177531.103" wire $not$libresoc.v:177531$10552_Y attribute \src "libresoc.v:177532.17-177532.103" wire $not$libresoc.v:177532$10553_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest20__wen attribute \src "libresoc.v:177452.7-177452.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r20__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src10__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src10__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src30__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src30__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src30__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177528$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:177528$10549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177529$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:177529$10550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177530$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:177530$10551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177531$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:177531$10552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177532$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:177532$10553_Y end attribute \src "libresoc.v:177452.7-177452.20" process $proc$libresoc.v:177452$10631 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:177477.13-177477.30" process $proc$libresoc.v:177477$10632 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end attribute \src "libresoc.v:177484.13-177484.31" process $proc$libresoc.v:177484$10633 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end attribute \src "libresoc.v:177490.13-177490.25" process $proc$libresoc.v:177490$10634 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:177495.13-177495.33" process $proc$libresoc.v:177495$10635 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end attribute \src "libresoc.v:177502.13-177502.33" process $proc$libresoc.v:177502$10636 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end attribute \src "libresoc.v:177509.13-177509.33" process $proc$libresoc.v:177509$10637 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end attribute \src "libresoc.v:177533.3-177534.25" process $proc$libresoc.v:177533$10554 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:177535.3-177536.39" process $proc$libresoc.v:177535$10555 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end attribute \src "libresoc.v:177537.3-177538.37" process $proc$libresoc.v:177537$10556 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end attribute \src "libresoc.v:177539.3-177540.43" process $proc$libresoc.v:177539$10557 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end attribute \src "libresoc.v:177541.3-177542.43" process $proc$libresoc.v:177541$10558 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end attribute \src "libresoc.v:177543.3-177544.43" process $proc$libresoc.v:177543$10559 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end attribute \src "libresoc.v:177545.3-177584.6" process $proc$libresoc.v:177545$10560 assign { } { } assign { } { } assign { } { } assign $0\src10__data_o$next[3:0]$10561 $6\src10__data_o$next[3:0]$10567 attribute \src "libresoc.v:177546.5-177546.29" switch \initial attribute \src "libresoc.v:177546.9-177546.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src10__data_o$next[3:0]$10562 $5\src10__data_o$next[3:0]$10566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src10__data_o$next[3:0]$10563 \dest10__data_i case assign $2\src10__data_o$next[3:0]$10563 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src10__data_o$next[3:0]$10564 \dest20__data_i case assign $3\src10__data_o$next[3:0]$10564 $2\src10__data_o$next[3:0]$10563 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src10__data_o$next[3:0]$10565 \w0__data_i case assign $4\src10__data_o$next[3:0]$10565 $3\src10__data_o$next[3:0]$10564 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src10__data_o$next[3:0]$10566 \reg case assign $5\src10__data_o$next[3:0]$10566 $4\src10__data_o$next[3:0]$10565 end case assign $1\src10__data_o$next[3:0]$10562 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src10__data_o$next[3:0]$10567 4'0000 case assign $6\src10__data_o$next[3:0]$10567 $1\src10__data_o$next[3:0]$10562 end sync always update \src10__data_o$next $0\src10__data_o$next[3:0]$10561 end attribute \src "libresoc.v:177585.3-177614.6" process $proc$libresoc.v:177585$10568 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:177586.5-177586.29" switch \initial attribute \src "libresoc.v:177586.9-177586.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:177615.3-177641.6" process $proc$libresoc.v:177615$10569 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$10570 $4\reg$next[3:0]$10574 attribute \src "libresoc.v:177616.5-177616.29" switch \initial attribute \src "libresoc.v:177616.9-177616.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$10571 \dest10__data_i case assign $1\reg$next[3:0]$10571 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$10572 \dest20__data_i case assign $2\reg$next[3:0]$10572 $1\reg$next[3:0]$10571 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$10573 \w0__data_i case assign $3\reg$next[3:0]$10573 $2\reg$next[3:0]$10572 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$10574 4'0000 case assign $4\reg$next[3:0]$10574 $3\reg$next[3:0]$10573 end sync always update \reg$next $0\reg$next[3:0]$10570 end attribute \src "libresoc.v:177642.3-177681.6" process $proc$libresoc.v:177642$10575 assign { } { } assign { } { } assign { } { } assign $0\src20__data_o$next[3:0]$10576 $6\src20__data_o$next[3:0]$10582 attribute \src "libresoc.v:177643.5-177643.29" switch \initial attribute \src "libresoc.v:177643.9-177643.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src20__data_o$next[3:0]$10577 $5\src20__data_o$next[3:0]$10581 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src20__data_o$next[3:0]$10578 \dest10__data_i case assign $2\src20__data_o$next[3:0]$10578 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src20__data_o$next[3:0]$10579 \dest20__data_i case assign $3\src20__data_o$next[3:0]$10579 $2\src20__data_o$next[3:0]$10578 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src20__data_o$next[3:0]$10580 \w0__data_i case assign $4\src20__data_o$next[3:0]$10580 $3\src20__data_o$next[3:0]$10579 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src20__data_o$next[3:0]$10581 \reg case assign $5\src20__data_o$next[3:0]$10581 $4\src20__data_o$next[3:0]$10580 end case assign $1\src20__data_o$next[3:0]$10577 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src20__data_o$next[3:0]$10582 4'0000 case assign $6\src20__data_o$next[3:0]$10582 $1\src20__data_o$next[3:0]$10577 end sync always update \src20__data_o$next $0\src20__data_o$next[3:0]$10576 end attribute \src "libresoc.v:177682.3-177711.6" process $proc$libresoc.v:177682$10583 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10584 $1\wr_detect$4[0:0]$10585 attribute \src "libresoc.v:177683.5-177683.29" switch \initial attribute \src "libresoc.v:177683.9-177683.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$10585 $4\wr_detect$4[0:0]$10588 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$10586 1'1 case assign $2\wr_detect$4[0:0]$10586 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$10587 1'1 case assign $3\wr_detect$4[0:0]$10587 $2\wr_detect$4[0:0]$10586 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$10588 1'1 case assign $4\wr_detect$4[0:0]$10588 $3\wr_detect$4[0:0]$10587 end case assign $1\wr_detect$4[0:0]$10585 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10584 end attribute \src "libresoc.v:177712.3-177751.6" process $proc$libresoc.v:177712$10589 assign { } { } assign { } { } assign { } { } assign $0\src30__data_o$next[3:0]$10590 $6\src30__data_o$next[3:0]$10596 attribute \src "libresoc.v:177713.5-177713.29" switch \initial attribute \src "libresoc.v:177713.9-177713.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src30__data_o$next[3:0]$10591 $5\src30__data_o$next[3:0]$10595 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src30__data_o$next[3:0]$10592 \dest10__data_i case assign $2\src30__data_o$next[3:0]$10592 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src30__data_o$next[3:0]$10593 \dest20__data_i case assign $3\src30__data_o$next[3:0]$10593 $2\src30__data_o$next[3:0]$10592 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src30__data_o$next[3:0]$10594 \w0__data_i case assign $4\src30__data_o$next[3:0]$10594 $3\src30__data_o$next[3:0]$10593 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src30__data_o$next[3:0]$10595 \reg case assign $5\src30__data_o$next[3:0]$10595 $4\src30__data_o$next[3:0]$10594 end case assign $1\src30__data_o$next[3:0]$10591 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src30__data_o$next[3:0]$10596 4'0000 case assign $6\src30__data_o$next[3:0]$10596 $1\src30__data_o$next[3:0]$10591 end sync always update \src30__data_o$next $0\src30__data_o$next[3:0]$10590 end attribute \src "libresoc.v:177752.3-177781.6" process $proc$libresoc.v:177752$10597 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10598 $1\wr_detect$7[0:0]$10599 attribute \src "libresoc.v:177753.5-177753.29" switch \initial attribute \src "libresoc.v:177753.9-177753.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$10599 $4\wr_detect$7[0:0]$10602 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$10600 1'1 case assign $2\wr_detect$7[0:0]$10600 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$10601 1'1 case assign $3\wr_detect$7[0:0]$10601 $2\wr_detect$7[0:0]$10600 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$10602 1'1 case assign $4\wr_detect$7[0:0]$10602 $3\wr_detect$7[0:0]$10601 end case assign $1\wr_detect$7[0:0]$10599 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10598 end attribute \src "libresoc.v:177782.3-177821.6" process $proc$libresoc.v:177782$10603 assign { } { } assign { } { } assign { } { } assign $0\r0__data_o$next[3:0]$10604 $6\r0__data_o$next[3:0]$10610 attribute \src "libresoc.v:177783.5-177783.29" switch \initial attribute \src "libresoc.v:177783.9-177783.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r0__data_o$next[3:0]$10605 $5\r0__data_o$next[3:0]$10609 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r0__data_o$next[3:0]$10606 \dest10__data_i case assign $2\r0__data_o$next[3:0]$10606 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r0__data_o$next[3:0]$10607 \dest20__data_i case assign $3\r0__data_o$next[3:0]$10607 $2\r0__data_o$next[3:0]$10606 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r0__data_o$next[3:0]$10608 \w0__data_i case assign $4\r0__data_o$next[3:0]$10608 $3\r0__data_o$next[3:0]$10607 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r0__data_o$next[3:0]$10609 \reg case assign $5\r0__data_o$next[3:0]$10609 $4\r0__data_o$next[3:0]$10608 end case assign $1\r0__data_o$next[3:0]$10605 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r0__data_o$next[3:0]$10610 4'0000 case assign $6\r0__data_o$next[3:0]$10610 $1\r0__data_o$next[3:0]$10605 end sync always update \r0__data_o$next $0\r0__data_o$next[3:0]$10604 end attribute \src "libresoc.v:177822.3-177851.6" process $proc$libresoc.v:177822$10611 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$10612 $1\wr_detect$10[0:0]$10613 attribute \src "libresoc.v:177823.5-177823.29" switch \initial attribute \src "libresoc.v:177823.9-177823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$10613 $4\wr_detect$10[0:0]$10616 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$10614 1'1 case assign $2\wr_detect$10[0:0]$10614 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$10615 1'1 case assign $3\wr_detect$10[0:0]$10615 $2\wr_detect$10[0:0]$10614 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$10616 1'1 case assign $4\wr_detect$10[0:0]$10616 $3\wr_detect$10[0:0]$10615 end case assign $1\wr_detect$10[0:0]$10613 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$10612 end attribute \src "libresoc.v:177852.3-177891.6" process $proc$libresoc.v:177852$10617 assign { } { } assign { } { } assign { } { } assign $0\r20__data_o$next[3:0]$10618 $6\r20__data_o$next[3:0]$10624 attribute \src "libresoc.v:177853.5-177853.29" switch \initial attribute \src "libresoc.v:177853.9-177853.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r20__data_o$next[3:0]$10619 $5\r20__data_o$next[3:0]$10623 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r20__data_o$next[3:0]$10620 \dest10__data_i case assign $2\r20__data_o$next[3:0]$10620 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r20__data_o$next[3:0]$10621 \dest20__data_i case assign $3\r20__data_o$next[3:0]$10621 $2\r20__data_o$next[3:0]$10620 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r20__data_o$next[3:0]$10622 \w0__data_i case assign $4\r20__data_o$next[3:0]$10622 $3\r20__data_o$next[3:0]$10621 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r20__data_o$next[3:0]$10623 \reg case assign $5\r20__data_o$next[3:0]$10623 $4\r20__data_o$next[3:0]$10622 end case assign $1\r20__data_o$next[3:0]$10619 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r20__data_o$next[3:0]$10624 4'0000 case assign $6\r20__data_o$next[3:0]$10624 $1\r20__data_o$next[3:0]$10619 end sync always update \r20__data_o$next $0\r20__data_o$next[3:0]$10618 end attribute \src "libresoc.v:177892.3-177921.6" process $proc$libresoc.v:177892$10625 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$10626 $1\wr_detect$13[0:0]$10627 attribute \src "libresoc.v:177893.5-177893.29" switch \initial attribute \src "libresoc.v:177893.9-177893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$10627 $4\wr_detect$13[0:0]$10630 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$10628 1'1 case assign $2\wr_detect$13[0:0]$10628 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$10629 1'1 case assign $3\wr_detect$13[0:0]$10629 $2\wr_detect$13[0:0]$10628 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$10630 1'1 case assign $4\wr_detect$13[0:0]$10630 $3\wr_detect$13[0:0]$10629 end case assign $1\wr_detect$13[0:0]$10627 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$10626 end connect \$9 $not$libresoc.v:177528$10549_Y connect \$12 $not$libresoc.v:177529$10550_Y connect \$1 $not$libresoc.v:177530$10551_Y connect \$3 $not$libresoc.v:177531$10552_Y connect \$6 $not$libresoc.v:177532$10553_Y end attribute \src "libresoc.v:177926.1-178371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 attribute \src "libresoc.v:177927.7-177927.20" wire $0\initial[0:0] attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $0\r0__data_o$next[1:0]$10690 attribute \src "libresoc.v:178002.3-178003.37" wire width 2 $0\r0__data_o[1:0] attribute \src "libresoc.v:178338.3-178370.6" wire width 2 $0\reg$next[1:0]$10706 attribute \src "libresoc.v:178000.3-178001.25" wire width 2 $0\reg[1:0] attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $0\src10__data_o$next[1:0]$10648 attribute \src "libresoc.v:178008.3-178009.43" wire width 2 $0\src10__data_o[1:0] attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $0\src20__data_o$next[1:0]$10658 attribute \src "libresoc.v:178006.3-178007.43" wire width 2 $0\src20__data_o[1:0] attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $0\src30__data_o$next[1:0]$10674 attribute \src "libresoc.v:178004.3-178005.43" wire width 2 $0\src30__data_o[1:0] attribute \src "libresoc.v:178302.3-178337.6" wire $0\wr_detect$10[0:0]$10699 attribute \src "libresoc.v:178138.3-178173.6" wire $0\wr_detect$4[0:0]$10667 attribute \src "libresoc.v:178220.3-178255.6" wire $0\wr_detect$7[0:0]$10683 attribute \src "libresoc.v:178056.3-178091.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $1\r0__data_o$next[1:0]$10691 attribute \src "libresoc.v:177954.13-177954.30" wire width 2 $1\r0__data_o[1:0] attribute \src "libresoc.v:178338.3-178370.6" wire width 2 $1\reg$next[1:0]$10707 attribute \src "libresoc.v:177960.13-177960.25" wire width 2 $1\reg[1:0] attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $1\src10__data_o$next[1:0]$10649 attribute \src "libresoc.v:177965.13-177965.33" wire width 2 $1\src10__data_o[1:0] attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $1\src20__data_o$next[1:0]$10659 attribute \src "libresoc.v:177972.13-177972.33" wire width 2 $1\src20__data_o[1:0] attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $1\src30__data_o$next[1:0]$10675 attribute \src "libresoc.v:177979.13-177979.33" wire width 2 $1\src30__data_o[1:0] attribute \src "libresoc.v:178302.3-178337.6" wire $1\wr_detect$10[0:0]$10700 attribute \src "libresoc.v:178138.3-178173.6" wire $1\wr_detect$4[0:0]$10668 attribute \src "libresoc.v:178220.3-178255.6" wire $1\wr_detect$7[0:0]$10684 attribute \src "libresoc.v:178056.3-178091.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $2\r0__data_o$next[1:0]$10692 attribute \src "libresoc.v:178338.3-178370.6" wire width 2 $2\reg$next[1:0]$10708 attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $2\src10__data_o$next[1:0]$10650 attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $2\src20__data_o$next[1:0]$10660 attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $2\src30__data_o$next[1:0]$10676 attribute \src "libresoc.v:178302.3-178337.6" wire $2\wr_detect$10[0:0]$10701 attribute \src "libresoc.v:178138.3-178173.6" wire $2\wr_detect$4[0:0]$10669 attribute \src "libresoc.v:178220.3-178255.6" wire $2\wr_detect$7[0:0]$10685 attribute \src "libresoc.v:178056.3-178091.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $3\r0__data_o$next[1:0]$10693 attribute \src "libresoc.v:178338.3-178370.6" wire width 2 $3\reg$next[1:0]$10709 attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $3\src10__data_o$next[1:0]$10651 attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $3\src20__data_o$next[1:0]$10661 attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $3\src30__data_o$next[1:0]$10677 attribute \src "libresoc.v:178302.3-178337.6" wire $3\wr_detect$10[0:0]$10702 attribute \src "libresoc.v:178138.3-178173.6" wire $3\wr_detect$4[0:0]$10670 attribute \src "libresoc.v:178220.3-178255.6" wire $3\wr_detect$7[0:0]$10686 attribute \src "libresoc.v:178056.3-178091.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $4\r0__data_o$next[1:0]$10694 attribute \src "libresoc.v:178338.3-178370.6" wire width 2 $4\reg$next[1:0]$10710 attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $4\src10__data_o$next[1:0]$10652 attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $4\src20__data_o$next[1:0]$10662 attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $4\src30__data_o$next[1:0]$10678 attribute \src "libresoc.v:178302.3-178337.6" wire $4\wr_detect$10[0:0]$10703 attribute \src "libresoc.v:178138.3-178173.6" wire $4\wr_detect$4[0:0]$10671 attribute \src "libresoc.v:178220.3-178255.6" wire $4\wr_detect$7[0:0]$10687 attribute \src "libresoc.v:178056.3-178091.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $5\r0__data_o$next[1:0]$10695 attribute \src "libresoc.v:178338.3-178370.6" wire width 2 $5\reg$next[1:0]$10711 attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $5\src10__data_o$next[1:0]$10653 attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $5\src20__data_o$next[1:0]$10663 attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $5\src30__data_o$next[1:0]$10679 attribute \src "libresoc.v:178302.3-178337.6" wire $5\wr_detect$10[0:0]$10704 attribute \src "libresoc.v:178138.3-178173.6" wire $5\wr_detect$4[0:0]$10672 attribute \src "libresoc.v:178220.3-178255.6" wire $5\wr_detect$7[0:0]$10688 attribute \src "libresoc.v:178056.3-178091.6" wire $5\wr_detect[0:0] attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $6\r0__data_o$next[1:0]$10696 attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $6\src10__data_o$next[1:0]$10654 attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $6\src20__data_o$next[1:0]$10664 attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $6\src30__data_o$next[1:0]$10680 attribute \src "libresoc.v:178256.3-178301.6" wire width 2 $7\r0__data_o$next[1:0]$10697 attribute \src "libresoc.v:178010.3-178055.6" wire width 2 $7\src10__data_o$next[1:0]$10655 attribute \src "libresoc.v:178092.3-178137.6" wire width 2 $7\src20__data_o$next[1:0]$10665 attribute \src "libresoc.v:178174.3-178219.6" wire width 2 $7\src30__data_o$next[1:0]$10681 attribute \src "libresoc.v:177996.17-177996.104" wire $not$libresoc.v:177996$10638_Y attribute \src "libresoc.v:177997.17-177997.100" wire $not$libresoc.v:177997$10639_Y attribute \src "libresoc.v:177998.17-177998.103" wire $not$libresoc.v:177998$10640_Y attribute \src "libresoc.v:177999.17-177999.103" wire $not$libresoc.v:177999$10641_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 11 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest20__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen attribute \src "libresoc.v:177927.7-177927.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \r0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r0__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 3 \src10__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src10__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 5 \src20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src20__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 7 \src30__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src30__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src30__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 16 \w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177996$10638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:177996$10638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177997$10639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:177997$10639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177998$10640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:177998$10640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:177999$10641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:177999$10641_Y end attribute \src "libresoc.v:177927.7-177927.20" process $proc$libresoc.v:177927$10712 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:177954.13-177954.30" process $proc$libresoc.v:177954$10713 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end attribute \src "libresoc.v:177960.13-177960.25" process $proc$libresoc.v:177960$10714 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end attribute \src "libresoc.v:177965.13-177965.33" process $proc$libresoc.v:177965$10715 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end attribute \src "libresoc.v:177972.13-177972.33" process $proc$libresoc.v:177972$10716 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end attribute \src "libresoc.v:177979.13-177979.33" process $proc$libresoc.v:177979$10717 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end attribute \src "libresoc.v:178000.3-178001.25" process $proc$libresoc.v:178000$10642 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end attribute \src "libresoc.v:178002.3-178003.37" process $proc$libresoc.v:178002$10643 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end attribute \src "libresoc.v:178004.3-178005.43" process $proc$libresoc.v:178004$10644 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end attribute \src "libresoc.v:178006.3-178007.43" process $proc$libresoc.v:178006$10645 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end attribute \src "libresoc.v:178008.3-178009.43" process $proc$libresoc.v:178008$10646 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end attribute \src "libresoc.v:178010.3-178055.6" process $proc$libresoc.v:178010$10647 assign { } { } assign { } { } assign { } { } assign $0\src10__data_o$next[1:0]$10648 $7\src10__data_o$next[1:0]$10655 attribute \src "libresoc.v:178011.5-178011.29" switch \initial attribute \src "libresoc.v:178011.9-178011.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src10__data_o$next[1:0]$10649 $6\src10__data_o$next[1:0]$10654 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src10__data_o$next[1:0]$10650 \dest10__data_i case assign $2\src10__data_o$next[1:0]$10650 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src10__data_o$next[1:0]$10651 \dest20__data_i case assign $3\src10__data_o$next[1:0]$10651 $2\src10__data_o$next[1:0]$10650 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src10__data_o$next[1:0]$10652 \dest30__data_i case assign $4\src10__data_o$next[1:0]$10652 $3\src10__data_o$next[1:0]$10651 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src10__data_o$next[1:0]$10653 \w0__data_i case assign $5\src10__data_o$next[1:0]$10653 $4\src10__data_o$next[1:0]$10652 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src10__data_o$next[1:0]$10654 \reg case assign $6\src10__data_o$next[1:0]$10654 $5\src10__data_o$next[1:0]$10653 end case assign $1\src10__data_o$next[1:0]$10649 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src10__data_o$next[1:0]$10655 2'00 case assign $7\src10__data_o$next[1:0]$10655 $1\src10__data_o$next[1:0]$10649 end sync always update \src10__data_o$next $0\src10__data_o$next[1:0]$10648 end attribute \src "libresoc.v:178056.3-178091.6" process $proc$libresoc.v:178056$10656 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:178057.5-178057.29" switch \initial attribute \src "libresoc.v:178057.9-178057.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src10__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect[0:0] 1'1 case assign $5\wr_detect[0:0] $4\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:178092.3-178137.6" process $proc$libresoc.v:178092$10657 assign { } { } assign { } { } assign { } { } assign $0\src20__data_o$next[1:0]$10658 $7\src20__data_o$next[1:0]$10665 attribute \src "libresoc.v:178093.5-178093.29" switch \initial attribute \src "libresoc.v:178093.9-178093.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src20__data_o$next[1:0]$10659 $6\src20__data_o$next[1:0]$10664 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src20__data_o$next[1:0]$10660 \dest10__data_i case assign $2\src20__data_o$next[1:0]$10660 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src20__data_o$next[1:0]$10661 \dest20__data_i case assign $3\src20__data_o$next[1:0]$10661 $2\src20__data_o$next[1:0]$10660 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src20__data_o$next[1:0]$10662 \dest30__data_i case assign $4\src20__data_o$next[1:0]$10662 $3\src20__data_o$next[1:0]$10661 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src20__data_o$next[1:0]$10663 \w0__data_i case assign $5\src20__data_o$next[1:0]$10663 $4\src20__data_o$next[1:0]$10662 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src20__data_o$next[1:0]$10664 \reg case assign $6\src20__data_o$next[1:0]$10664 $5\src20__data_o$next[1:0]$10663 end case assign $1\src20__data_o$next[1:0]$10659 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src20__data_o$next[1:0]$10665 2'00 case assign $7\src20__data_o$next[1:0]$10665 $1\src20__data_o$next[1:0]$10659 end sync always update \src20__data_o$next $0\src20__data_o$next[1:0]$10658 end attribute \src "libresoc.v:178138.3-178173.6" process $proc$libresoc.v:178138$10666 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10667 $1\wr_detect$4[0:0]$10668 attribute \src "libresoc.v:178139.5-178139.29" switch \initial attribute \src "libresoc.v:178139.9-178139.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src20__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$10668 $5\wr_detect$4[0:0]$10672 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$10669 1'1 case assign $2\wr_detect$4[0:0]$10669 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$10670 1'1 case assign $3\wr_detect$4[0:0]$10670 $2\wr_detect$4[0:0]$10669 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$10671 1'1 case assign $4\wr_detect$4[0:0]$10671 $3\wr_detect$4[0:0]$10670 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$4[0:0]$10672 1'1 case assign $5\wr_detect$4[0:0]$10672 $4\wr_detect$4[0:0]$10671 end case assign $1\wr_detect$4[0:0]$10668 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10667 end attribute \src "libresoc.v:178174.3-178219.6" process $proc$libresoc.v:178174$10673 assign { } { } assign { } { } assign { } { } assign $0\src30__data_o$next[1:0]$10674 $7\src30__data_o$next[1:0]$10681 attribute \src "libresoc.v:178175.5-178175.29" switch \initial attribute \src "libresoc.v:178175.9-178175.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src30__data_o$next[1:0]$10675 $6\src30__data_o$next[1:0]$10680 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src30__data_o$next[1:0]$10676 \dest10__data_i case assign $2\src30__data_o$next[1:0]$10676 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src30__data_o$next[1:0]$10677 \dest20__data_i case assign $3\src30__data_o$next[1:0]$10677 $2\src30__data_o$next[1:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src30__data_o$next[1:0]$10678 \dest30__data_i case assign $4\src30__data_o$next[1:0]$10678 $3\src30__data_o$next[1:0]$10677 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src30__data_o$next[1:0]$10679 \w0__data_i case assign $5\src30__data_o$next[1:0]$10679 $4\src30__data_o$next[1:0]$10678 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src30__data_o$next[1:0]$10680 \reg case assign $6\src30__data_o$next[1:0]$10680 $5\src30__data_o$next[1:0]$10679 end case assign $1\src30__data_o$next[1:0]$10675 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src30__data_o$next[1:0]$10681 2'00 case assign $7\src30__data_o$next[1:0]$10681 $1\src30__data_o$next[1:0]$10675 end sync always update \src30__data_o$next $0\src30__data_o$next[1:0]$10674 end attribute \src "libresoc.v:178220.3-178255.6" process $proc$libresoc.v:178220$10682 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10683 $1\wr_detect$7[0:0]$10684 attribute \src "libresoc.v:178221.5-178221.29" switch \initial attribute \src "libresoc.v:178221.9-178221.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src30__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$10684 $5\wr_detect$7[0:0]$10688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$10685 1'1 case assign $2\wr_detect$7[0:0]$10685 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$10686 1'1 case assign $3\wr_detect$7[0:0]$10686 $2\wr_detect$7[0:0]$10685 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$10687 1'1 case assign $4\wr_detect$7[0:0]$10687 $3\wr_detect$7[0:0]$10686 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$7[0:0]$10688 1'1 case assign $5\wr_detect$7[0:0]$10688 $4\wr_detect$7[0:0]$10687 end case assign $1\wr_detect$7[0:0]$10684 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10683 end attribute \src "libresoc.v:178256.3-178301.6" process $proc$libresoc.v:178256$10689 assign { } { } assign { } { } assign { } { } assign $0\r0__data_o$next[1:0]$10690 $7\r0__data_o$next[1:0]$10697 attribute \src "libresoc.v:178257.5-178257.29" switch \initial attribute \src "libresoc.v:178257.9-178257.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r0__data_o$next[1:0]$10691 $6\r0__data_o$next[1:0]$10696 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r0__data_o$next[1:0]$10692 \dest10__data_i case assign $2\r0__data_o$next[1:0]$10692 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r0__data_o$next[1:0]$10693 \dest20__data_i case assign $3\r0__data_o$next[1:0]$10693 $2\r0__data_o$next[1:0]$10692 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r0__data_o$next[1:0]$10694 \dest30__data_i case assign $4\r0__data_o$next[1:0]$10694 $3\r0__data_o$next[1:0]$10693 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r0__data_o$next[1:0]$10695 \w0__data_i case assign $5\r0__data_o$next[1:0]$10695 $4\r0__data_o$next[1:0]$10694 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r0__data_o$next[1:0]$10696 \reg case assign $6\r0__data_o$next[1:0]$10696 $5\r0__data_o$next[1:0]$10695 end case assign $1\r0__data_o$next[1:0]$10691 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\r0__data_o$next[1:0]$10697 2'00 case assign $7\r0__data_o$next[1:0]$10697 $1\r0__data_o$next[1:0]$10691 end sync always update \r0__data_o$next $0\r0__data_o$next[1:0]$10690 end attribute \src "libresoc.v:178302.3-178337.6" process $proc$libresoc.v:178302$10698 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$10699 $1\wr_detect$10[0:0]$10700 attribute \src "libresoc.v:178303.5-178303.29" switch \initial attribute \src "libresoc.v:178303.9-178303.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$10700 $5\wr_detect$10[0:0]$10704 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$10701 1'1 case assign $2\wr_detect$10[0:0]$10701 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$10702 1'1 case assign $3\wr_detect$10[0:0]$10702 $2\wr_detect$10[0:0]$10701 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$10703 1'1 case assign $4\wr_detect$10[0:0]$10703 $3\wr_detect$10[0:0]$10702 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$10[0:0]$10704 1'1 case assign $5\wr_detect$10[0:0]$10704 $4\wr_detect$10[0:0]$10703 end case assign $1\wr_detect$10[0:0]$10700 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$10699 end attribute \src "libresoc.v:178338.3-178370.6" process $proc$libresoc.v:178338$10705 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[1:0]$10706 $5\reg$next[1:0]$10711 attribute \src "libresoc.v:178339.5-178339.29" switch \initial attribute \src "libresoc.v:178339.9-178339.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[1:0]$10707 \dest10__data_i case assign $1\reg$next[1:0]$10707 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[1:0]$10708 \dest20__data_i case assign $2\reg$next[1:0]$10708 $1\reg$next[1:0]$10707 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[1:0]$10709 \dest30__data_i case assign $3\reg$next[1:0]$10709 $2\reg$next[1:0]$10708 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[1:0]$10710 \w0__data_i case assign $4\reg$next[1:0]$10710 $3\reg$next[1:0]$10709 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\reg$next[1:0]$10711 2'00 case assign $5\reg$next[1:0]$10711 $4\reg$next[1:0]$10710 end sync always update \reg$next $0\reg$next[1:0]$10706 end connect \$9 $not$libresoc.v:177996$10638_Y connect \$1 $not$libresoc.v:177997$10639_Y connect \$3 $not$libresoc.v:177998$10640_Y connect \$6 $not$libresoc.v:177999$10641_Y end attribute \src "libresoc.v:178375.1-178724.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $0\cia0__data_o$next[63:0]$10726 attribute \src "libresoc.v:178443.3-178444.41" wire width 64 $0\cia0__data_o[63:0] attribute \src "libresoc.v:178376.7-178376.20" wire $0\initial[0:0] attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $0\msr0__data_o$next[63:0]$10736 attribute \src "libresoc.v:178441.3-178442.41" wire width 64 $0\msr0__data_o[63:0] attribute \src "libresoc.v:178691.3-178723.6" wire width 64 $0\reg$next[63:0]$10768 attribute \src "libresoc.v:178437.3-178438.25" wire width 64 $0\reg[63:0] attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $0\sv0__data_o$next[63:0]$10752 attribute \src "libresoc.v:178439.3-178440.39" wire width 64 $0\sv0__data_o[63:0] attribute \src "libresoc.v:178573.3-178608.6" wire $0\wr_detect$4[0:0]$10745 attribute \src "libresoc.v:178655.3-178690.6" wire $0\wr_detect$7[0:0]$10761 attribute \src "libresoc.v:178491.3-178526.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $1\cia0__data_o$next[63:0]$10727 attribute \src "libresoc.v:178385.14-178385.49" wire width 64 $1\cia0__data_o[63:0] attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $1\msr0__data_o$next[63:0]$10737 attribute \src "libresoc.v:178402.14-178402.49" wire width 64 $1\msr0__data_o[63:0] attribute \src "libresoc.v:178691.3-178723.6" wire width 64 $1\reg$next[63:0]$10769 attribute \src "libresoc.v:178414.14-178414.42" wire width 64 $1\reg[63:0] attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $1\sv0__data_o$next[63:0]$10753 attribute \src "libresoc.v:178421.14-178421.48" wire width 64 $1\sv0__data_o[63:0] attribute \src "libresoc.v:178573.3-178608.6" wire $1\wr_detect$4[0:0]$10746 attribute \src "libresoc.v:178655.3-178690.6" wire $1\wr_detect$7[0:0]$10762 attribute \src "libresoc.v:178491.3-178526.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $2\cia0__data_o$next[63:0]$10728 attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $2\msr0__data_o$next[63:0]$10738 attribute \src "libresoc.v:178691.3-178723.6" wire width 64 $2\reg$next[63:0]$10770 attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $2\sv0__data_o$next[63:0]$10754 attribute \src "libresoc.v:178573.3-178608.6" wire $2\wr_detect$4[0:0]$10747 attribute \src "libresoc.v:178655.3-178690.6" wire $2\wr_detect$7[0:0]$10763 attribute \src "libresoc.v:178491.3-178526.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $3\cia0__data_o$next[63:0]$10729 attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $3\msr0__data_o$next[63:0]$10739 attribute \src "libresoc.v:178691.3-178723.6" wire width 64 $3\reg$next[63:0]$10771 attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $3\sv0__data_o$next[63:0]$10755 attribute \src "libresoc.v:178573.3-178608.6" wire $3\wr_detect$4[0:0]$10748 attribute \src "libresoc.v:178655.3-178690.6" wire $3\wr_detect$7[0:0]$10764 attribute \src "libresoc.v:178491.3-178526.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $4\cia0__data_o$next[63:0]$10730 attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $4\msr0__data_o$next[63:0]$10740 attribute \src "libresoc.v:178691.3-178723.6" wire width 64 $4\reg$next[63:0]$10772 attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $4\sv0__data_o$next[63:0]$10756 attribute \src "libresoc.v:178573.3-178608.6" wire $4\wr_detect$4[0:0]$10749 attribute \src "libresoc.v:178655.3-178690.6" wire $4\wr_detect$7[0:0]$10765 attribute \src "libresoc.v:178491.3-178526.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $5\cia0__data_o$next[63:0]$10731 attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $5\msr0__data_o$next[63:0]$10741 attribute \src "libresoc.v:178691.3-178723.6" wire width 64 $5\reg$next[63:0]$10773 attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $5\sv0__data_o$next[63:0]$10757 attribute \src "libresoc.v:178573.3-178608.6" wire $5\wr_detect$4[0:0]$10750 attribute \src "libresoc.v:178655.3-178690.6" wire $5\wr_detect$7[0:0]$10766 attribute \src "libresoc.v:178491.3-178526.6" wire $5\wr_detect[0:0] attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $6\cia0__data_o$next[63:0]$10732 attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $6\msr0__data_o$next[63:0]$10742 attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $6\sv0__data_o$next[63:0]$10758 attribute \src "libresoc.v:178445.3-178490.6" wire width 64 $7\cia0__data_o$next[63:0]$10733 attribute \src "libresoc.v:178527.3-178572.6" wire width 64 $7\msr0__data_o$next[63:0]$10743 attribute \src "libresoc.v:178609.3-178654.6" wire width 64 $7\sv0__data_o$next[63:0]$10759 attribute \src "libresoc.v:178434.17-178434.100" wire $not$libresoc.v:178434$10718_Y attribute \src "libresoc.v:178435.17-178435.103" wire $not$libresoc.v:178435$10719_Y attribute \src "libresoc.v:178436.17-178436.103" wire $not$libresoc.v:178436$10720_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 3 \cia0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen attribute \src "libresoc.v:178376.7-178376.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \msr0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \msr0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \msr0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \msr0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 9 \nia0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \nia0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 13 \sv0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 7 \sv0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \sv0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \sv0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \sv0__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178434$10718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:178434$10718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178435$10719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:178435$10719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178436$10720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:178436$10720_Y end attribute \src "libresoc.v:178376.7-178376.20" process $proc$libresoc.v:178376$10774 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:178385.14-178385.49" process $proc$libresoc.v:178385$10775 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end attribute \src "libresoc.v:178402.14-178402.49" process $proc$libresoc.v:178402$10776 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end attribute \src "libresoc.v:178414.14-178414.42" process $proc$libresoc.v:178414$10777 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end attribute \src "libresoc.v:178421.14-178421.48" process $proc$libresoc.v:178421$10778 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end attribute \src "libresoc.v:178437.3-178438.25" process $proc$libresoc.v:178437$10721 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end attribute \src "libresoc.v:178439.3-178440.39" process $proc$libresoc.v:178439$10722 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end attribute \src "libresoc.v:178441.3-178442.41" process $proc$libresoc.v:178441$10723 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end attribute \src "libresoc.v:178443.3-178444.41" process $proc$libresoc.v:178443$10724 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end attribute \src "libresoc.v:178445.3-178490.6" process $proc$libresoc.v:178445$10725 assign { } { } assign { } { } assign { } { } assign $0\cia0__data_o$next[63:0]$10726 $7\cia0__data_o$next[63:0]$10733 attribute \src "libresoc.v:178446.5-178446.29" switch \initial attribute \src "libresoc.v:178446.9-178446.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \cia0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\cia0__data_o$next[63:0]$10727 $6\cia0__data_o$next[63:0]$10732 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cia0__data_o$next[63:0]$10728 \nia0__data_i case assign $2\cia0__data_o$next[63:0]$10728 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cia0__data_o$next[63:0]$10729 \msr0__data_i case assign $3\cia0__data_o$next[63:0]$10729 $2\cia0__data_o$next[63:0]$10728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\cia0__data_o$next[63:0]$10730 \sv0__data_i case assign $4\cia0__data_o$next[63:0]$10730 $3\cia0__data_o$next[63:0]$10729 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\cia0__data_o$next[63:0]$10731 \d_wr10__data_i case assign $5\cia0__data_o$next[63:0]$10731 $4\cia0__data_o$next[63:0]$10730 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\cia0__data_o$next[63:0]$10732 \reg case assign $6\cia0__data_o$next[63:0]$10732 $5\cia0__data_o$next[63:0]$10731 end case assign $1\cia0__data_o$next[63:0]$10727 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\cia0__data_o$next[63:0]$10733 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\cia0__data_o$next[63:0]$10733 $1\cia0__data_o$next[63:0]$10727 end sync always update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10726 end attribute \src "libresoc.v:178491.3-178526.6" process $proc$libresoc.v:178491$10734 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:178492.5-178492.29" switch \initial attribute \src "libresoc.v:178492.9-178492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \cia0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect[0:0] 1'1 case assign $5\wr_detect[0:0] $4\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:178527.3-178572.6" process $proc$libresoc.v:178527$10735 assign { } { } assign { } { } assign { } { } assign $0\msr0__data_o$next[63:0]$10736 $7\msr0__data_o$next[63:0]$10743 attribute \src "libresoc.v:178528.5-178528.29" switch \initial attribute \src "libresoc.v:178528.9-178528.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \msr0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\msr0__data_o$next[63:0]$10737 $6\msr0__data_o$next[63:0]$10742 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\msr0__data_o$next[63:0]$10738 \nia0__data_i case assign $2\msr0__data_o$next[63:0]$10738 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\msr0__data_o$next[63:0]$10739 \msr0__data_i case assign $3\msr0__data_o$next[63:0]$10739 $2\msr0__data_o$next[63:0]$10738 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\msr0__data_o$next[63:0]$10740 \sv0__data_i case assign $4\msr0__data_o$next[63:0]$10740 $3\msr0__data_o$next[63:0]$10739 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\msr0__data_o$next[63:0]$10741 \d_wr10__data_i case assign $5\msr0__data_o$next[63:0]$10741 $4\msr0__data_o$next[63:0]$10740 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\msr0__data_o$next[63:0]$10742 \reg case assign $6\msr0__data_o$next[63:0]$10742 $5\msr0__data_o$next[63:0]$10741 end case assign $1\msr0__data_o$next[63:0]$10737 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\msr0__data_o$next[63:0]$10743 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\msr0__data_o$next[63:0]$10743 $1\msr0__data_o$next[63:0]$10737 end sync always update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10736 end attribute \src "libresoc.v:178573.3-178608.6" process $proc$libresoc.v:178573$10744 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10745 $1\wr_detect$4[0:0]$10746 attribute \src "libresoc.v:178574.5-178574.29" switch \initial attribute \src "libresoc.v:178574.9-178574.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \msr0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$10746 $5\wr_detect$4[0:0]$10750 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$10747 1'1 case assign $2\wr_detect$4[0:0]$10747 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$10748 1'1 case assign $3\wr_detect$4[0:0]$10748 $2\wr_detect$4[0:0]$10747 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$10749 1'1 case assign $4\wr_detect$4[0:0]$10749 $3\wr_detect$4[0:0]$10748 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$4[0:0]$10750 1'1 case assign $5\wr_detect$4[0:0]$10750 $4\wr_detect$4[0:0]$10749 end case assign $1\wr_detect$4[0:0]$10746 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10745 end attribute \src "libresoc.v:178609.3-178654.6" process $proc$libresoc.v:178609$10751 assign { } { } assign { } { } assign { } { } assign $0\sv0__data_o$next[63:0]$10752 $7\sv0__data_o$next[63:0]$10759 attribute \src "libresoc.v:178610.5-178610.29" switch \initial attribute \src "libresoc.v:178610.9-178610.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \sv0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\sv0__data_o$next[63:0]$10753 $6\sv0__data_o$next[63:0]$10758 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sv0__data_o$next[63:0]$10754 \nia0__data_i case assign $2\sv0__data_o$next[63:0]$10754 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\sv0__data_o$next[63:0]$10755 \msr0__data_i case assign $3\sv0__data_o$next[63:0]$10755 $2\sv0__data_o$next[63:0]$10754 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\sv0__data_o$next[63:0]$10756 \sv0__data_i case assign $4\sv0__data_o$next[63:0]$10756 $3\sv0__data_o$next[63:0]$10755 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\sv0__data_o$next[63:0]$10757 \d_wr10__data_i case assign $5\sv0__data_o$next[63:0]$10757 $4\sv0__data_o$next[63:0]$10756 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\sv0__data_o$next[63:0]$10758 \reg case assign $6\sv0__data_o$next[63:0]$10758 $5\sv0__data_o$next[63:0]$10757 end case assign $1\sv0__data_o$next[63:0]$10753 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\sv0__data_o$next[63:0]$10759 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\sv0__data_o$next[63:0]$10759 $1\sv0__data_o$next[63:0]$10753 end sync always update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10752 end attribute \src "libresoc.v:178655.3-178690.6" process $proc$libresoc.v:178655$10760 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10761 $1\wr_detect$7[0:0]$10762 attribute \src "libresoc.v:178656.5-178656.29" switch \initial attribute \src "libresoc.v:178656.9-178656.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \sv0__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$10762 $5\wr_detect$7[0:0]$10766 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$10763 1'1 case assign $2\wr_detect$7[0:0]$10763 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$10764 1'1 case assign $3\wr_detect$7[0:0]$10764 $2\wr_detect$7[0:0]$10763 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$10765 1'1 case assign $4\wr_detect$7[0:0]$10765 $3\wr_detect$7[0:0]$10764 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$7[0:0]$10766 1'1 case assign $5\wr_detect$7[0:0]$10766 $4\wr_detect$7[0:0]$10765 end case assign $1\wr_detect$7[0:0]$10762 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10761 end attribute \src "libresoc.v:178691.3-178723.6" process $proc$libresoc.v:178691$10767 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[63:0]$10768 $5\reg$next[63:0]$10773 attribute \src "libresoc.v:178692.5-178692.29" switch \initial attribute \src "libresoc.v:178692.9-178692.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[63:0]$10769 \nia0__data_i case assign $1\reg$next[63:0]$10769 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[63:0]$10770 \msr0__data_i case assign $2\reg$next[63:0]$10770 $1\reg$next[63:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[63:0]$10771 \sv0__data_i case assign $3\reg$next[63:0]$10771 $2\reg$next[63:0]$10770 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[63:0]$10772 \d_wr10__data_i case assign $4\reg$next[63:0]$10772 $3\reg$next[63:0]$10771 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\reg$next[63:0]$10773 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $5\reg$next[63:0]$10773 $4\reg$next[63:0]$10772 end sync always update \reg$next $0\reg$next[63:0]$10768 end connect \$1 $not$libresoc.v:178434$10718_Y connect \$3 $not$libresoc.v:178435$10719_Y connect \$6 $not$libresoc.v:178436$10720_Y end attribute \src "libresoc.v:178728.1-179199.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 attribute \src "libresoc.v:178729.7-178729.20" wire $0\initial[0:0] attribute \src "libresoc.v:179059.3-179098.6" wire width 4 $0\r1__data_o$next[3:0]$10834 attribute \src "libresoc.v:178814.3-178815.37" wire width 4 $0\r1__data_o[3:0] attribute \src "libresoc.v:179129.3-179168.6" wire width 4 $0\r21__data_o$next[3:0]$10848 attribute \src "libresoc.v:178812.3-178813.39" wire width 4 $0\r21__data_o[3:0] attribute \src "libresoc.v:178892.3-178918.6" wire width 4 $0\reg$next[3:0]$10800 attribute \src "libresoc.v:178810.3-178811.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:178822.3-178861.6" wire width 4 $0\src11__data_o$next[3:0]$10791 attribute \src "libresoc.v:178820.3-178821.43" wire width 4 $0\src11__data_o[3:0] attribute \src "libresoc.v:178919.3-178958.6" wire width 4 $0\src21__data_o$next[3:0]$10806 attribute \src "libresoc.v:178818.3-178819.43" wire width 4 $0\src21__data_o[3:0] attribute \src "libresoc.v:178989.3-179028.6" wire width 4 $0\src31__data_o$next[3:0]$10820 attribute \src "libresoc.v:178816.3-178817.43" wire width 4 $0\src31__data_o[3:0] attribute \src "libresoc.v:179099.3-179128.6" wire $0\wr_detect$10[0:0]$10842 attribute \src "libresoc.v:179169.3-179198.6" wire $0\wr_detect$13[0:0]$10856 attribute \src "libresoc.v:178959.3-178988.6" wire $0\wr_detect$4[0:0]$10814 attribute \src "libresoc.v:179029.3-179058.6" wire $0\wr_detect$7[0:0]$10828 attribute \src "libresoc.v:178862.3-178891.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:179059.3-179098.6" wire width 4 $1\r1__data_o$next[3:0]$10835 attribute \src "libresoc.v:178754.13-178754.30" wire width 4 $1\r1__data_o[3:0] attribute \src "libresoc.v:179129.3-179168.6" wire width 4 $1\r21__data_o$next[3:0]$10849 attribute \src "libresoc.v:178761.13-178761.31" wire width 4 $1\r21__data_o[3:0] attribute \src "libresoc.v:178892.3-178918.6" wire width 4 $1\reg$next[3:0]$10801 attribute \src "libresoc.v:178767.13-178767.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:178822.3-178861.6" wire width 4 $1\src11__data_o$next[3:0]$10792 attribute \src "libresoc.v:178772.13-178772.33" wire width 4 $1\src11__data_o[3:0] attribute \src "libresoc.v:178919.3-178958.6" wire width 4 $1\src21__data_o$next[3:0]$10807 attribute \src "libresoc.v:178779.13-178779.33" wire width 4 $1\src21__data_o[3:0] attribute \src "libresoc.v:178989.3-179028.6" wire width 4 $1\src31__data_o$next[3:0]$10821 attribute \src "libresoc.v:178786.13-178786.33" wire width 4 $1\src31__data_o[3:0] attribute \src "libresoc.v:179099.3-179128.6" wire $1\wr_detect$10[0:0]$10843 attribute \src "libresoc.v:179169.3-179198.6" wire $1\wr_detect$13[0:0]$10857 attribute \src "libresoc.v:178959.3-178988.6" wire $1\wr_detect$4[0:0]$10815 attribute \src "libresoc.v:179029.3-179058.6" wire $1\wr_detect$7[0:0]$10829 attribute \src "libresoc.v:178862.3-178891.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:179059.3-179098.6" wire width 4 $2\r1__data_o$next[3:0]$10836 attribute \src "libresoc.v:179129.3-179168.6" wire width 4 $2\r21__data_o$next[3:0]$10850 attribute \src "libresoc.v:178892.3-178918.6" wire width 4 $2\reg$next[3:0]$10802 attribute \src "libresoc.v:178822.3-178861.6" wire width 4 $2\src11__data_o$next[3:0]$10793 attribute \src "libresoc.v:178919.3-178958.6" wire width 4 $2\src21__data_o$next[3:0]$10808 attribute \src "libresoc.v:178989.3-179028.6" wire width 4 $2\src31__data_o$next[3:0]$10822 attribute \src "libresoc.v:179099.3-179128.6" wire $2\wr_detect$10[0:0]$10844 attribute \src "libresoc.v:179169.3-179198.6" wire $2\wr_detect$13[0:0]$10858 attribute \src "libresoc.v:178959.3-178988.6" wire $2\wr_detect$4[0:0]$10816 attribute \src "libresoc.v:179029.3-179058.6" wire $2\wr_detect$7[0:0]$10830 attribute \src "libresoc.v:178862.3-178891.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:179059.3-179098.6" wire width 4 $3\r1__data_o$next[3:0]$10837 attribute \src "libresoc.v:179129.3-179168.6" wire width 4 $3\r21__data_o$next[3:0]$10851 attribute \src "libresoc.v:178892.3-178918.6" wire width 4 $3\reg$next[3:0]$10803 attribute \src "libresoc.v:178822.3-178861.6" wire width 4 $3\src11__data_o$next[3:0]$10794 attribute \src "libresoc.v:178919.3-178958.6" wire width 4 $3\src21__data_o$next[3:0]$10809 attribute \src "libresoc.v:178989.3-179028.6" wire width 4 $3\src31__data_o$next[3:0]$10823 attribute \src "libresoc.v:179099.3-179128.6" wire $3\wr_detect$10[0:0]$10845 attribute \src "libresoc.v:179169.3-179198.6" wire $3\wr_detect$13[0:0]$10859 attribute \src "libresoc.v:178959.3-178988.6" wire $3\wr_detect$4[0:0]$10817 attribute \src "libresoc.v:179029.3-179058.6" wire $3\wr_detect$7[0:0]$10831 attribute \src "libresoc.v:178862.3-178891.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:179059.3-179098.6" wire width 4 $4\r1__data_o$next[3:0]$10838 attribute \src "libresoc.v:179129.3-179168.6" wire width 4 $4\r21__data_o$next[3:0]$10852 attribute \src "libresoc.v:178892.3-178918.6" wire width 4 $4\reg$next[3:0]$10804 attribute \src "libresoc.v:178822.3-178861.6" wire width 4 $4\src11__data_o$next[3:0]$10795 attribute \src "libresoc.v:178919.3-178958.6" wire width 4 $4\src21__data_o$next[3:0]$10810 attribute \src "libresoc.v:178989.3-179028.6" wire width 4 $4\src31__data_o$next[3:0]$10824 attribute \src "libresoc.v:179099.3-179128.6" wire $4\wr_detect$10[0:0]$10846 attribute \src "libresoc.v:179169.3-179198.6" wire $4\wr_detect$13[0:0]$10860 attribute \src "libresoc.v:178959.3-178988.6" wire $4\wr_detect$4[0:0]$10818 attribute \src "libresoc.v:179029.3-179058.6" wire $4\wr_detect$7[0:0]$10832 attribute \src "libresoc.v:178862.3-178891.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:179059.3-179098.6" wire width 4 $5\r1__data_o$next[3:0]$10839 attribute \src "libresoc.v:179129.3-179168.6" wire width 4 $5\r21__data_o$next[3:0]$10853 attribute \src "libresoc.v:178822.3-178861.6" wire width 4 $5\src11__data_o$next[3:0]$10796 attribute \src "libresoc.v:178919.3-178958.6" wire width 4 $5\src21__data_o$next[3:0]$10811 attribute \src "libresoc.v:178989.3-179028.6" wire width 4 $5\src31__data_o$next[3:0]$10825 attribute \src "libresoc.v:179059.3-179098.6" wire width 4 $6\r1__data_o$next[3:0]$10840 attribute \src "libresoc.v:179129.3-179168.6" wire width 4 $6\r21__data_o$next[3:0]$10854 attribute \src "libresoc.v:178822.3-178861.6" wire width 4 $6\src11__data_o$next[3:0]$10797 attribute \src "libresoc.v:178919.3-178958.6" wire width 4 $6\src21__data_o$next[3:0]$10812 attribute \src "libresoc.v:178989.3-179028.6" wire width 4 $6\src31__data_o$next[3:0]$10826 attribute \src "libresoc.v:178805.17-178805.104" wire $not$libresoc.v:178805$10779_Y attribute \src "libresoc.v:178806.18-178806.105" wire $not$libresoc.v:178806$10780_Y attribute \src "libresoc.v:178807.17-178807.100" wire $not$libresoc.v:178807$10781_Y attribute \src "libresoc.v:178808.17-178808.103" wire $not$libresoc.v:178808$10782_Y attribute \src "libresoc.v:178809.17-178809.103" wire $not$libresoc.v:178809$10783_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest21__wen attribute \src "libresoc.v:178729.7-178729.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r21__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src11__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src11__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src11__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src31__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src31__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src31__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178805$10779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:178805$10779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178806$10780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:178806$10780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178807$10781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:178807$10781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178808$10782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:178808$10782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:178809$10783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:178809$10783_Y end attribute \src "libresoc.v:178729.7-178729.20" process $proc$libresoc.v:178729$10861 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:178754.13-178754.30" process $proc$libresoc.v:178754$10862 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end attribute \src "libresoc.v:178761.13-178761.31" process $proc$libresoc.v:178761$10863 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end attribute \src "libresoc.v:178767.13-178767.25" process $proc$libresoc.v:178767$10864 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:178772.13-178772.33" process $proc$libresoc.v:178772$10865 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end attribute \src "libresoc.v:178779.13-178779.33" process $proc$libresoc.v:178779$10866 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end attribute \src "libresoc.v:178786.13-178786.33" process $proc$libresoc.v:178786$10867 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end attribute \src "libresoc.v:178810.3-178811.25" process $proc$libresoc.v:178810$10784 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:178812.3-178813.39" process $proc$libresoc.v:178812$10785 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end attribute \src "libresoc.v:178814.3-178815.37" process $proc$libresoc.v:178814$10786 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end attribute \src "libresoc.v:178816.3-178817.43" process $proc$libresoc.v:178816$10787 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end attribute \src "libresoc.v:178818.3-178819.43" process $proc$libresoc.v:178818$10788 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end attribute \src "libresoc.v:178820.3-178821.43" process $proc$libresoc.v:178820$10789 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end attribute \src "libresoc.v:178822.3-178861.6" process $proc$libresoc.v:178822$10790 assign { } { } assign { } { } assign { } { } assign $0\src11__data_o$next[3:0]$10791 $6\src11__data_o$next[3:0]$10797 attribute \src "libresoc.v:178823.5-178823.29" switch \initial attribute \src "libresoc.v:178823.9-178823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src11__data_o$next[3:0]$10792 $5\src11__data_o$next[3:0]$10796 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src11__data_o$next[3:0]$10793 \dest11__data_i case assign $2\src11__data_o$next[3:0]$10793 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src11__data_o$next[3:0]$10794 \dest21__data_i case assign $3\src11__data_o$next[3:0]$10794 $2\src11__data_o$next[3:0]$10793 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src11__data_o$next[3:0]$10795 \w1__data_i case assign $4\src11__data_o$next[3:0]$10795 $3\src11__data_o$next[3:0]$10794 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src11__data_o$next[3:0]$10796 \reg case assign $5\src11__data_o$next[3:0]$10796 $4\src11__data_o$next[3:0]$10795 end case assign $1\src11__data_o$next[3:0]$10792 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src11__data_o$next[3:0]$10797 4'0000 case assign $6\src11__data_o$next[3:0]$10797 $1\src11__data_o$next[3:0]$10792 end sync always update \src11__data_o$next $0\src11__data_o$next[3:0]$10791 end attribute \src "libresoc.v:178862.3-178891.6" process $proc$libresoc.v:178862$10798 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:178863.5-178863.29" switch \initial attribute \src "libresoc.v:178863.9-178863.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:178892.3-178918.6" process $proc$libresoc.v:178892$10799 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$10800 $4\reg$next[3:0]$10804 attribute \src "libresoc.v:178893.5-178893.29" switch \initial attribute \src "libresoc.v:178893.9-178893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$10801 \dest11__data_i case assign $1\reg$next[3:0]$10801 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$10802 \dest21__data_i case assign $2\reg$next[3:0]$10802 $1\reg$next[3:0]$10801 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$10803 \w1__data_i case assign $3\reg$next[3:0]$10803 $2\reg$next[3:0]$10802 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$10804 4'0000 case assign $4\reg$next[3:0]$10804 $3\reg$next[3:0]$10803 end sync always update \reg$next $0\reg$next[3:0]$10800 end attribute \src "libresoc.v:178919.3-178958.6" process $proc$libresoc.v:178919$10805 assign { } { } assign { } { } assign { } { } assign $0\src21__data_o$next[3:0]$10806 $6\src21__data_o$next[3:0]$10812 attribute \src "libresoc.v:178920.5-178920.29" switch \initial attribute \src "libresoc.v:178920.9-178920.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src21__data_o$next[3:0]$10807 $5\src21__data_o$next[3:0]$10811 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src21__data_o$next[3:0]$10808 \dest11__data_i case assign $2\src21__data_o$next[3:0]$10808 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src21__data_o$next[3:0]$10809 \dest21__data_i case assign $3\src21__data_o$next[3:0]$10809 $2\src21__data_o$next[3:0]$10808 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src21__data_o$next[3:0]$10810 \w1__data_i case assign $4\src21__data_o$next[3:0]$10810 $3\src21__data_o$next[3:0]$10809 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src21__data_o$next[3:0]$10811 \reg case assign $5\src21__data_o$next[3:0]$10811 $4\src21__data_o$next[3:0]$10810 end case assign $1\src21__data_o$next[3:0]$10807 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src21__data_o$next[3:0]$10812 4'0000 case assign $6\src21__data_o$next[3:0]$10812 $1\src21__data_o$next[3:0]$10807 end sync always update \src21__data_o$next $0\src21__data_o$next[3:0]$10806 end attribute \src "libresoc.v:178959.3-178988.6" process $proc$libresoc.v:178959$10813 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10814 $1\wr_detect$4[0:0]$10815 attribute \src "libresoc.v:178960.5-178960.29" switch \initial attribute \src "libresoc.v:178960.9-178960.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$10815 $4\wr_detect$4[0:0]$10818 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$10816 1'1 case assign $2\wr_detect$4[0:0]$10816 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$10817 1'1 case assign $3\wr_detect$4[0:0]$10817 $2\wr_detect$4[0:0]$10816 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$10818 1'1 case assign $4\wr_detect$4[0:0]$10818 $3\wr_detect$4[0:0]$10817 end case assign $1\wr_detect$4[0:0]$10815 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10814 end attribute \src "libresoc.v:178989.3-179028.6" process $proc$libresoc.v:178989$10819 assign { } { } assign { } { } assign { } { } assign $0\src31__data_o$next[3:0]$10820 $6\src31__data_o$next[3:0]$10826 attribute \src "libresoc.v:178990.5-178990.29" switch \initial attribute \src "libresoc.v:178990.9-178990.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src31__data_o$next[3:0]$10821 $5\src31__data_o$next[3:0]$10825 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src31__data_o$next[3:0]$10822 \dest11__data_i case assign $2\src31__data_o$next[3:0]$10822 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src31__data_o$next[3:0]$10823 \dest21__data_i case assign $3\src31__data_o$next[3:0]$10823 $2\src31__data_o$next[3:0]$10822 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src31__data_o$next[3:0]$10824 \w1__data_i case assign $4\src31__data_o$next[3:0]$10824 $3\src31__data_o$next[3:0]$10823 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src31__data_o$next[3:0]$10825 \reg case assign $5\src31__data_o$next[3:0]$10825 $4\src31__data_o$next[3:0]$10824 end case assign $1\src31__data_o$next[3:0]$10821 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src31__data_o$next[3:0]$10826 4'0000 case assign $6\src31__data_o$next[3:0]$10826 $1\src31__data_o$next[3:0]$10821 end sync always update \src31__data_o$next $0\src31__data_o$next[3:0]$10820 end attribute \src "libresoc.v:179029.3-179058.6" process $proc$libresoc.v:179029$10827 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10828 $1\wr_detect$7[0:0]$10829 attribute \src "libresoc.v:179030.5-179030.29" switch \initial attribute \src "libresoc.v:179030.9-179030.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$10829 $4\wr_detect$7[0:0]$10832 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$10830 1'1 case assign $2\wr_detect$7[0:0]$10830 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$10831 1'1 case assign $3\wr_detect$7[0:0]$10831 $2\wr_detect$7[0:0]$10830 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$10832 1'1 case assign $4\wr_detect$7[0:0]$10832 $3\wr_detect$7[0:0]$10831 end case assign $1\wr_detect$7[0:0]$10829 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10828 end attribute \src "libresoc.v:179059.3-179098.6" process $proc$libresoc.v:179059$10833 assign { } { } assign { } { } assign { } { } assign $0\r1__data_o$next[3:0]$10834 $6\r1__data_o$next[3:0]$10840 attribute \src "libresoc.v:179060.5-179060.29" switch \initial attribute \src "libresoc.v:179060.9-179060.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r1__data_o$next[3:0]$10835 $5\r1__data_o$next[3:0]$10839 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r1__data_o$next[3:0]$10836 \dest11__data_i case assign $2\r1__data_o$next[3:0]$10836 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r1__data_o$next[3:0]$10837 \dest21__data_i case assign $3\r1__data_o$next[3:0]$10837 $2\r1__data_o$next[3:0]$10836 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r1__data_o$next[3:0]$10838 \w1__data_i case assign $4\r1__data_o$next[3:0]$10838 $3\r1__data_o$next[3:0]$10837 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r1__data_o$next[3:0]$10839 \reg case assign $5\r1__data_o$next[3:0]$10839 $4\r1__data_o$next[3:0]$10838 end case assign $1\r1__data_o$next[3:0]$10835 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r1__data_o$next[3:0]$10840 4'0000 case assign $6\r1__data_o$next[3:0]$10840 $1\r1__data_o$next[3:0]$10835 end sync always update \r1__data_o$next $0\r1__data_o$next[3:0]$10834 end attribute \src "libresoc.v:179099.3-179128.6" process $proc$libresoc.v:179099$10841 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$10842 $1\wr_detect$10[0:0]$10843 attribute \src "libresoc.v:179100.5-179100.29" switch \initial attribute \src "libresoc.v:179100.9-179100.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$10843 $4\wr_detect$10[0:0]$10846 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$10844 1'1 case assign $2\wr_detect$10[0:0]$10844 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$10845 1'1 case assign $3\wr_detect$10[0:0]$10845 $2\wr_detect$10[0:0]$10844 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$10846 1'1 case assign $4\wr_detect$10[0:0]$10846 $3\wr_detect$10[0:0]$10845 end case assign $1\wr_detect$10[0:0]$10843 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$10842 end attribute \src "libresoc.v:179129.3-179168.6" process $proc$libresoc.v:179129$10847 assign { } { } assign { } { } assign { } { } assign $0\r21__data_o$next[3:0]$10848 $6\r21__data_o$next[3:0]$10854 attribute \src "libresoc.v:179130.5-179130.29" switch \initial attribute \src "libresoc.v:179130.9-179130.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r21__data_o$next[3:0]$10849 $5\r21__data_o$next[3:0]$10853 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r21__data_o$next[3:0]$10850 \dest11__data_i case assign $2\r21__data_o$next[3:0]$10850 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r21__data_o$next[3:0]$10851 \dest21__data_i case assign $3\r21__data_o$next[3:0]$10851 $2\r21__data_o$next[3:0]$10850 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r21__data_o$next[3:0]$10852 \w1__data_i case assign $4\r21__data_o$next[3:0]$10852 $3\r21__data_o$next[3:0]$10851 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r21__data_o$next[3:0]$10853 \reg case assign $5\r21__data_o$next[3:0]$10853 $4\r21__data_o$next[3:0]$10852 end case assign $1\r21__data_o$next[3:0]$10849 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r21__data_o$next[3:0]$10854 4'0000 case assign $6\r21__data_o$next[3:0]$10854 $1\r21__data_o$next[3:0]$10849 end sync always update \r21__data_o$next $0\r21__data_o$next[3:0]$10848 end attribute \src "libresoc.v:179169.3-179198.6" process $proc$libresoc.v:179169$10855 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$10856 $1\wr_detect$13[0:0]$10857 attribute \src "libresoc.v:179170.5-179170.29" switch \initial attribute \src "libresoc.v:179170.9-179170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$10857 $4\wr_detect$13[0:0]$10860 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$10858 1'1 case assign $2\wr_detect$13[0:0]$10858 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$10859 1'1 case assign $3\wr_detect$13[0:0]$10859 $2\wr_detect$13[0:0]$10858 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$10860 1'1 case assign $4\wr_detect$13[0:0]$10860 $3\wr_detect$13[0:0]$10859 end case assign $1\wr_detect$13[0:0]$10857 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$10856 end connect \$9 $not$libresoc.v:178805$10779_Y connect \$12 $not$libresoc.v:178806$10780_Y connect \$1 $not$libresoc.v:178807$10781_Y connect \$3 $not$libresoc.v:178808$10782_Y connect \$6 $not$libresoc.v:178809$10783_Y end attribute \src "libresoc.v:179203.1-179648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 attribute \src "libresoc.v:179204.7-179204.20" wire $0\initial[0:0] attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $0\r1__data_o$next[1:0]$10920 attribute \src "libresoc.v:179279.3-179280.37" wire width 2 $0\r1__data_o[1:0] attribute \src "libresoc.v:179615.3-179647.6" wire width 2 $0\reg$next[1:0]$10936 attribute \src "libresoc.v:179277.3-179278.25" wire width 2 $0\reg[1:0] attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $0\src11__data_o$next[1:0]$10878 attribute \src "libresoc.v:179285.3-179286.43" wire width 2 $0\src11__data_o[1:0] attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $0\src21__data_o$next[1:0]$10888 attribute \src "libresoc.v:179283.3-179284.43" wire width 2 $0\src21__data_o[1:0] attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $0\src31__data_o$next[1:0]$10904 attribute \src "libresoc.v:179281.3-179282.43" wire width 2 $0\src31__data_o[1:0] attribute \src "libresoc.v:179579.3-179614.6" wire $0\wr_detect$10[0:0]$10929 attribute \src "libresoc.v:179415.3-179450.6" wire $0\wr_detect$4[0:0]$10897 attribute \src "libresoc.v:179497.3-179532.6" wire $0\wr_detect$7[0:0]$10913 attribute \src "libresoc.v:179333.3-179368.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $1\r1__data_o$next[1:0]$10921 attribute \src "libresoc.v:179231.13-179231.30" wire width 2 $1\r1__data_o[1:0] attribute \src "libresoc.v:179615.3-179647.6" wire width 2 $1\reg$next[1:0]$10937 attribute \src "libresoc.v:179237.13-179237.25" wire width 2 $1\reg[1:0] attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $1\src11__data_o$next[1:0]$10879 attribute \src "libresoc.v:179242.13-179242.33" wire width 2 $1\src11__data_o[1:0] attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $1\src21__data_o$next[1:0]$10889 attribute \src "libresoc.v:179249.13-179249.33" wire width 2 $1\src21__data_o[1:0] attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $1\src31__data_o$next[1:0]$10905 attribute \src "libresoc.v:179256.13-179256.33" wire width 2 $1\src31__data_o[1:0] attribute \src "libresoc.v:179579.3-179614.6" wire $1\wr_detect$10[0:0]$10930 attribute \src "libresoc.v:179415.3-179450.6" wire $1\wr_detect$4[0:0]$10898 attribute \src "libresoc.v:179497.3-179532.6" wire $1\wr_detect$7[0:0]$10914 attribute \src "libresoc.v:179333.3-179368.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $2\r1__data_o$next[1:0]$10922 attribute \src "libresoc.v:179615.3-179647.6" wire width 2 $2\reg$next[1:0]$10938 attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $2\src11__data_o$next[1:0]$10880 attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $2\src21__data_o$next[1:0]$10890 attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $2\src31__data_o$next[1:0]$10906 attribute \src "libresoc.v:179579.3-179614.6" wire $2\wr_detect$10[0:0]$10931 attribute \src "libresoc.v:179415.3-179450.6" wire $2\wr_detect$4[0:0]$10899 attribute \src "libresoc.v:179497.3-179532.6" wire $2\wr_detect$7[0:0]$10915 attribute \src "libresoc.v:179333.3-179368.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $3\r1__data_o$next[1:0]$10923 attribute \src "libresoc.v:179615.3-179647.6" wire width 2 $3\reg$next[1:0]$10939 attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $3\src11__data_o$next[1:0]$10881 attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $3\src21__data_o$next[1:0]$10891 attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $3\src31__data_o$next[1:0]$10907 attribute \src "libresoc.v:179579.3-179614.6" wire $3\wr_detect$10[0:0]$10932 attribute \src "libresoc.v:179415.3-179450.6" wire $3\wr_detect$4[0:0]$10900 attribute \src "libresoc.v:179497.3-179532.6" wire $3\wr_detect$7[0:0]$10916 attribute \src "libresoc.v:179333.3-179368.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $4\r1__data_o$next[1:0]$10924 attribute \src "libresoc.v:179615.3-179647.6" wire width 2 $4\reg$next[1:0]$10940 attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $4\src11__data_o$next[1:0]$10882 attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $4\src21__data_o$next[1:0]$10892 attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $4\src31__data_o$next[1:0]$10908 attribute \src "libresoc.v:179579.3-179614.6" wire $4\wr_detect$10[0:0]$10933 attribute \src "libresoc.v:179415.3-179450.6" wire $4\wr_detect$4[0:0]$10901 attribute \src "libresoc.v:179497.3-179532.6" wire $4\wr_detect$7[0:0]$10917 attribute \src "libresoc.v:179333.3-179368.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $5\r1__data_o$next[1:0]$10925 attribute \src "libresoc.v:179615.3-179647.6" wire width 2 $5\reg$next[1:0]$10941 attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $5\src11__data_o$next[1:0]$10883 attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $5\src21__data_o$next[1:0]$10893 attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $5\src31__data_o$next[1:0]$10909 attribute \src "libresoc.v:179579.3-179614.6" wire $5\wr_detect$10[0:0]$10934 attribute \src "libresoc.v:179415.3-179450.6" wire $5\wr_detect$4[0:0]$10902 attribute \src "libresoc.v:179497.3-179532.6" wire $5\wr_detect$7[0:0]$10918 attribute \src "libresoc.v:179333.3-179368.6" wire $5\wr_detect[0:0] attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $6\r1__data_o$next[1:0]$10926 attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $6\src11__data_o$next[1:0]$10884 attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $6\src21__data_o$next[1:0]$10894 attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $6\src31__data_o$next[1:0]$10910 attribute \src "libresoc.v:179533.3-179578.6" wire width 2 $7\r1__data_o$next[1:0]$10927 attribute \src "libresoc.v:179287.3-179332.6" wire width 2 $7\src11__data_o$next[1:0]$10885 attribute \src "libresoc.v:179369.3-179414.6" wire width 2 $7\src21__data_o$next[1:0]$10895 attribute \src "libresoc.v:179451.3-179496.6" wire width 2 $7\src31__data_o$next[1:0]$10911 attribute \src "libresoc.v:179273.17-179273.104" wire $not$libresoc.v:179273$10868_Y attribute \src "libresoc.v:179274.17-179274.100" wire $not$libresoc.v:179274$10869_Y attribute \src "libresoc.v:179275.17-179275.103" wire $not$libresoc.v:179275$10870_Y attribute \src "libresoc.v:179276.17-179276.103" wire $not$libresoc.v:179276$10871_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 11 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest21__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen attribute \src "libresoc.v:179204.7-179204.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \r1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r1__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 3 \src11__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src11__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src11__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 5 \src21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src21__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 7 \src31__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src31__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src31__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 16 \w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:179273$10868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:179273$10868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:179274$10869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:179274$10869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:179275$10870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:179275$10870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:179276$10871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:179276$10871_Y end attribute \src "libresoc.v:179204.7-179204.20" process $proc$libresoc.v:179204$10942 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:179231.13-179231.30" process $proc$libresoc.v:179231$10943 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end attribute \src "libresoc.v:179237.13-179237.25" process $proc$libresoc.v:179237$10944 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end attribute \src "libresoc.v:179242.13-179242.33" process $proc$libresoc.v:179242$10945 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end attribute \src "libresoc.v:179249.13-179249.33" process $proc$libresoc.v:179249$10946 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end attribute \src "libresoc.v:179256.13-179256.33" process $proc$libresoc.v:179256$10947 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end attribute \src "libresoc.v:179277.3-179278.25" process $proc$libresoc.v:179277$10872 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end attribute \src "libresoc.v:179279.3-179280.37" process $proc$libresoc.v:179279$10873 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end attribute \src "libresoc.v:179281.3-179282.43" process $proc$libresoc.v:179281$10874 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end attribute \src "libresoc.v:179283.3-179284.43" process $proc$libresoc.v:179283$10875 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end attribute \src "libresoc.v:179285.3-179286.43" process $proc$libresoc.v:179285$10876 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end attribute \src "libresoc.v:179287.3-179332.6" process $proc$libresoc.v:179287$10877 assign { } { } assign { } { } assign { } { } assign $0\src11__data_o$next[1:0]$10878 $7\src11__data_o$next[1:0]$10885 attribute \src "libresoc.v:179288.5-179288.29" switch \initial attribute \src "libresoc.v:179288.9-179288.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src11__data_o$next[1:0]$10879 $6\src11__data_o$next[1:0]$10884 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src11__data_o$next[1:0]$10880 \dest11__data_i case assign $2\src11__data_o$next[1:0]$10880 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src11__data_o$next[1:0]$10881 \dest21__data_i case assign $3\src11__data_o$next[1:0]$10881 $2\src11__data_o$next[1:0]$10880 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src11__data_o$next[1:0]$10882 \dest31__data_i case assign $4\src11__data_o$next[1:0]$10882 $3\src11__data_o$next[1:0]$10881 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src11__data_o$next[1:0]$10883 \w1__data_i case assign $5\src11__data_o$next[1:0]$10883 $4\src11__data_o$next[1:0]$10882 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src11__data_o$next[1:0]$10884 \reg case assign $6\src11__data_o$next[1:0]$10884 $5\src11__data_o$next[1:0]$10883 end case assign $1\src11__data_o$next[1:0]$10879 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src11__data_o$next[1:0]$10885 2'00 case assign $7\src11__data_o$next[1:0]$10885 $1\src11__data_o$next[1:0]$10879 end sync always update \src11__data_o$next $0\src11__data_o$next[1:0]$10878 end attribute \src "libresoc.v:179333.3-179368.6" process $proc$libresoc.v:179333$10886 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:179334.5-179334.29" switch \initial attribute \src "libresoc.v:179334.9-179334.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src11__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect[0:0] 1'1 case assign $5\wr_detect[0:0] $4\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:179369.3-179414.6" process $proc$libresoc.v:179369$10887 assign { } { } assign { } { } assign { } { } assign $0\src21__data_o$next[1:0]$10888 $7\src21__data_o$next[1:0]$10895 attribute \src "libresoc.v:179370.5-179370.29" switch \initial attribute \src "libresoc.v:179370.9-179370.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src21__data_o$next[1:0]$10889 $6\src21__data_o$next[1:0]$10894 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src21__data_o$next[1:0]$10890 \dest11__data_i case assign $2\src21__data_o$next[1:0]$10890 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src21__data_o$next[1:0]$10891 \dest21__data_i case assign $3\src21__data_o$next[1:0]$10891 $2\src21__data_o$next[1:0]$10890 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src21__data_o$next[1:0]$10892 \dest31__data_i case assign $4\src21__data_o$next[1:0]$10892 $3\src21__data_o$next[1:0]$10891 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src21__data_o$next[1:0]$10893 \w1__data_i case assign $5\src21__data_o$next[1:0]$10893 $4\src21__data_o$next[1:0]$10892 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src21__data_o$next[1:0]$10894 \reg case assign $6\src21__data_o$next[1:0]$10894 $5\src21__data_o$next[1:0]$10893 end case assign $1\src21__data_o$next[1:0]$10889 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src21__data_o$next[1:0]$10895 2'00 case assign $7\src21__data_o$next[1:0]$10895 $1\src21__data_o$next[1:0]$10889 end sync always update \src21__data_o$next $0\src21__data_o$next[1:0]$10888 end attribute \src "libresoc.v:179415.3-179450.6" process $proc$libresoc.v:179415$10896 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10897 $1\wr_detect$4[0:0]$10898 attribute \src "libresoc.v:179416.5-179416.29" switch \initial attribute \src "libresoc.v:179416.9-179416.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src21__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$10898 $5\wr_detect$4[0:0]$10902 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$10899 1'1 case assign $2\wr_detect$4[0:0]$10899 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$10900 1'1 case assign $3\wr_detect$4[0:0]$10900 $2\wr_detect$4[0:0]$10899 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$10901 1'1 case assign $4\wr_detect$4[0:0]$10901 $3\wr_detect$4[0:0]$10900 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$4[0:0]$10902 1'1 case assign $5\wr_detect$4[0:0]$10902 $4\wr_detect$4[0:0]$10901 end case assign $1\wr_detect$4[0:0]$10898 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10897 end attribute \src "libresoc.v:179451.3-179496.6" process $proc$libresoc.v:179451$10903 assign { } { } assign { } { } assign { } { } assign $0\src31__data_o$next[1:0]$10904 $7\src31__data_o$next[1:0]$10911 attribute \src "libresoc.v:179452.5-179452.29" switch \initial attribute \src "libresoc.v:179452.9-179452.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src31__data_o$next[1:0]$10905 $6\src31__data_o$next[1:0]$10910 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src31__data_o$next[1:0]$10906 \dest11__data_i case assign $2\src31__data_o$next[1:0]$10906 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src31__data_o$next[1:0]$10907 \dest21__data_i case assign $3\src31__data_o$next[1:0]$10907 $2\src31__data_o$next[1:0]$10906 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src31__data_o$next[1:0]$10908 \dest31__data_i case assign $4\src31__data_o$next[1:0]$10908 $3\src31__data_o$next[1:0]$10907 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src31__data_o$next[1:0]$10909 \w1__data_i case assign $5\src31__data_o$next[1:0]$10909 $4\src31__data_o$next[1:0]$10908 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src31__data_o$next[1:0]$10910 \reg case assign $6\src31__data_o$next[1:0]$10910 $5\src31__data_o$next[1:0]$10909 end case assign $1\src31__data_o$next[1:0]$10905 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src31__data_o$next[1:0]$10911 2'00 case assign $7\src31__data_o$next[1:0]$10911 $1\src31__data_o$next[1:0]$10905 end sync always update \src31__data_o$next $0\src31__data_o$next[1:0]$10904 end attribute \src "libresoc.v:179497.3-179532.6" process $proc$libresoc.v:179497$10912 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10913 $1\wr_detect$7[0:0]$10914 attribute \src "libresoc.v:179498.5-179498.29" switch \initial attribute \src "libresoc.v:179498.9-179498.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src31__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$10914 $5\wr_detect$7[0:0]$10918 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$10915 1'1 case assign $2\wr_detect$7[0:0]$10915 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$10916 1'1 case assign $3\wr_detect$7[0:0]$10916 $2\wr_detect$7[0:0]$10915 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$10917 1'1 case assign $4\wr_detect$7[0:0]$10917 $3\wr_detect$7[0:0]$10916 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$7[0:0]$10918 1'1 case assign $5\wr_detect$7[0:0]$10918 $4\wr_detect$7[0:0]$10917 end case assign $1\wr_detect$7[0:0]$10914 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10913 end attribute \src "libresoc.v:179533.3-179578.6" process $proc$libresoc.v:179533$10919 assign { } { } assign { } { } assign { } { } assign $0\r1__data_o$next[1:0]$10920 $7\r1__data_o$next[1:0]$10927 attribute \src "libresoc.v:179534.5-179534.29" switch \initial attribute \src "libresoc.v:179534.9-179534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r1__data_o$next[1:0]$10921 $6\r1__data_o$next[1:0]$10926 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r1__data_o$next[1:0]$10922 \dest11__data_i case assign $2\r1__data_o$next[1:0]$10922 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r1__data_o$next[1:0]$10923 \dest21__data_i case assign $3\r1__data_o$next[1:0]$10923 $2\r1__data_o$next[1:0]$10922 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r1__data_o$next[1:0]$10924 \dest31__data_i case assign $4\r1__data_o$next[1:0]$10924 $3\r1__data_o$next[1:0]$10923 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r1__data_o$next[1:0]$10925 \w1__data_i case assign $5\r1__data_o$next[1:0]$10925 $4\r1__data_o$next[1:0]$10924 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r1__data_o$next[1:0]$10926 \reg case assign $6\r1__data_o$next[1:0]$10926 $5\r1__data_o$next[1:0]$10925 end case assign $1\r1__data_o$next[1:0]$10921 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\r1__data_o$next[1:0]$10927 2'00 case assign $7\r1__data_o$next[1:0]$10927 $1\r1__data_o$next[1:0]$10921 end sync always update \r1__data_o$next $0\r1__data_o$next[1:0]$10920 end attribute \src "libresoc.v:179579.3-179614.6" process $proc$libresoc.v:179579$10928 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$10929 $1\wr_detect$10[0:0]$10930 attribute \src "libresoc.v:179580.5-179580.29" switch \initial attribute \src "libresoc.v:179580.9-179580.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$10930 $5\wr_detect$10[0:0]$10934 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$10931 1'1 case assign $2\wr_detect$10[0:0]$10931 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$10932 1'1 case assign $3\wr_detect$10[0:0]$10932 $2\wr_detect$10[0:0]$10931 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$10933 1'1 case assign $4\wr_detect$10[0:0]$10933 $3\wr_detect$10[0:0]$10932 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$10[0:0]$10934 1'1 case assign $5\wr_detect$10[0:0]$10934 $4\wr_detect$10[0:0]$10933 end case assign $1\wr_detect$10[0:0]$10930 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$10929 end attribute \src "libresoc.v:179615.3-179647.6" process $proc$libresoc.v:179615$10935 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[1:0]$10936 $5\reg$next[1:0]$10941 attribute \src "libresoc.v:179616.5-179616.29" switch \initial attribute \src "libresoc.v:179616.9-179616.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[1:0]$10937 \dest11__data_i case assign $1\reg$next[1:0]$10937 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[1:0]$10938 \dest21__data_i case assign $2\reg$next[1:0]$10938 $1\reg$next[1:0]$10937 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[1:0]$10939 \dest31__data_i case assign $3\reg$next[1:0]$10939 $2\reg$next[1:0]$10938 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[1:0]$10940 \w1__data_i case assign $4\reg$next[1:0]$10940 $3\reg$next[1:0]$10939 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\reg$next[1:0]$10941 2'00 case assign $5\reg$next[1:0]$10941 $4\reg$next[1:0]$10940 end sync always update \reg$next $0\reg$next[1:0]$10936 end connect \$9 $not$libresoc.v:179273$10868_Y connect \$1 $not$libresoc.v:179274$10869_Y connect \$3 $not$libresoc.v:179275$10870_Y connect \$6 $not$libresoc.v:179276$10871_Y end attribute \src "libresoc.v:179652.1-180001.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $0\cia1__data_o$next[63:0]$10956 attribute \src "libresoc.v:179720.3-179721.41" wire width 64 $0\cia1__data_o[63:0] attribute \src "libresoc.v:179653.7-179653.20" wire $0\initial[0:0] attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $0\msr1__data_o$next[63:0]$10966 attribute \src "libresoc.v:179718.3-179719.41" wire width 64 $0\msr1__data_o[63:0] attribute \src "libresoc.v:179968.3-180000.6" wire width 64 $0\reg$next[63:0]$10998 attribute \src "libresoc.v:179714.3-179715.25" wire width 64 $0\reg[63:0] attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $0\sv1__data_o$next[63:0]$10982 attribute \src "libresoc.v:179716.3-179717.39" wire width 64 $0\sv1__data_o[63:0] attribute \src "libresoc.v:179850.3-179885.6" wire $0\wr_detect$4[0:0]$10975 attribute \src "libresoc.v:179932.3-179967.6" wire $0\wr_detect$7[0:0]$10991 attribute \src "libresoc.v:179768.3-179803.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $1\cia1__data_o$next[63:0]$10957 attribute \src "libresoc.v:179662.14-179662.49" wire width 64 $1\cia1__data_o[63:0] attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $1\msr1__data_o$next[63:0]$10967 attribute \src "libresoc.v:179679.14-179679.49" wire width 64 $1\msr1__data_o[63:0] attribute \src "libresoc.v:179968.3-180000.6" wire width 64 $1\reg$next[63:0]$10999 attribute \src "libresoc.v:179691.14-179691.42" wire width 64 $1\reg[63:0] attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $1\sv1__data_o$next[63:0]$10983 attribute \src "libresoc.v:179698.14-179698.48" wire width 64 $1\sv1__data_o[63:0] attribute \src "libresoc.v:179850.3-179885.6" wire $1\wr_detect$4[0:0]$10976 attribute \src "libresoc.v:179932.3-179967.6" wire $1\wr_detect$7[0:0]$10992 attribute \src "libresoc.v:179768.3-179803.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $2\cia1__data_o$next[63:0]$10958 attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $2\msr1__data_o$next[63:0]$10968 attribute \src "libresoc.v:179968.3-180000.6" wire width 64 $2\reg$next[63:0]$11000 attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $2\sv1__data_o$next[63:0]$10984 attribute \src "libresoc.v:179850.3-179885.6" wire $2\wr_detect$4[0:0]$10977 attribute \src "libresoc.v:179932.3-179967.6" wire $2\wr_detect$7[0:0]$10993 attribute \src "libresoc.v:179768.3-179803.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $3\cia1__data_o$next[63:0]$10959 attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $3\msr1__data_o$next[63:0]$10969 attribute \src "libresoc.v:179968.3-180000.6" wire width 64 $3\reg$next[63:0]$11001 attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $3\sv1__data_o$next[63:0]$10985 attribute \src "libresoc.v:179850.3-179885.6" wire $3\wr_detect$4[0:0]$10978 attribute \src "libresoc.v:179932.3-179967.6" wire $3\wr_detect$7[0:0]$10994 attribute \src "libresoc.v:179768.3-179803.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $4\cia1__data_o$next[63:0]$10960 attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $4\msr1__data_o$next[63:0]$10970 attribute \src "libresoc.v:179968.3-180000.6" wire width 64 $4\reg$next[63:0]$11002 attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $4\sv1__data_o$next[63:0]$10986 attribute \src "libresoc.v:179850.3-179885.6" wire $4\wr_detect$4[0:0]$10979 attribute \src "libresoc.v:179932.3-179967.6" wire $4\wr_detect$7[0:0]$10995 attribute \src "libresoc.v:179768.3-179803.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $5\cia1__data_o$next[63:0]$10961 attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $5\msr1__data_o$next[63:0]$10971 attribute \src "libresoc.v:179968.3-180000.6" wire width 64 $5\reg$next[63:0]$11003 attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $5\sv1__data_o$next[63:0]$10987 attribute \src "libresoc.v:179850.3-179885.6" wire $5\wr_detect$4[0:0]$10980 attribute \src "libresoc.v:179932.3-179967.6" wire $5\wr_detect$7[0:0]$10996 attribute \src "libresoc.v:179768.3-179803.6" wire $5\wr_detect[0:0] attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $6\cia1__data_o$next[63:0]$10962 attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $6\msr1__data_o$next[63:0]$10972 attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $6\sv1__data_o$next[63:0]$10988 attribute \src "libresoc.v:179722.3-179767.6" wire width 64 $7\cia1__data_o$next[63:0]$10963 attribute \src "libresoc.v:179804.3-179849.6" wire width 64 $7\msr1__data_o$next[63:0]$10973 attribute \src "libresoc.v:179886.3-179931.6" wire width 64 $7\sv1__data_o$next[63:0]$10989 attribute \src "libresoc.v:179711.17-179711.100" wire $not$libresoc.v:179711$10948_Y attribute \src "libresoc.v:179712.17-179712.103" wire $not$libresoc.v:179712$10949_Y attribute \src "libresoc.v:179713.17-179713.103" wire $not$libresoc.v:179713$10950_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 3 \cia1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen attribute \src "libresoc.v:179653.7-179653.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \msr1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \msr1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \msr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \msr1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 9 \nia1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \nia1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 13 \sv1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 7 \sv1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \sv1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \sv1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \sv1__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:179711$10948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:179711$10948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:179712$10949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:179712$10949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:179713$10950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:179713$10950_Y end attribute \src "libresoc.v:179653.7-179653.20" process $proc$libresoc.v:179653$11004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:179662.14-179662.49" process $proc$libresoc.v:179662$11005 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end attribute \src "libresoc.v:179679.14-179679.49" process $proc$libresoc.v:179679$11006 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end attribute \src "libresoc.v:179691.14-179691.42" process $proc$libresoc.v:179691$11007 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end attribute \src "libresoc.v:179698.14-179698.48" process $proc$libresoc.v:179698$11008 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end attribute \src "libresoc.v:179714.3-179715.25" process $proc$libresoc.v:179714$10951 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end attribute \src "libresoc.v:179716.3-179717.39" process $proc$libresoc.v:179716$10952 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end attribute \src "libresoc.v:179718.3-179719.41" process $proc$libresoc.v:179718$10953 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end attribute \src "libresoc.v:179720.3-179721.41" process $proc$libresoc.v:179720$10954 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end attribute \src "libresoc.v:179722.3-179767.6" process $proc$libresoc.v:179722$10955 assign { } { } assign { } { } assign { } { } assign $0\cia1__data_o$next[63:0]$10956 $7\cia1__data_o$next[63:0]$10963 attribute \src "libresoc.v:179723.5-179723.29" switch \initial attribute \src "libresoc.v:179723.9-179723.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \cia1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\cia1__data_o$next[63:0]$10957 $6\cia1__data_o$next[63:0]$10962 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cia1__data_o$next[63:0]$10958 \nia1__data_i case assign $2\cia1__data_o$next[63:0]$10958 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cia1__data_o$next[63:0]$10959 \msr1__data_i case assign $3\cia1__data_o$next[63:0]$10959 $2\cia1__data_o$next[63:0]$10958 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\cia1__data_o$next[63:0]$10960 \sv1__data_i case assign $4\cia1__data_o$next[63:0]$10960 $3\cia1__data_o$next[63:0]$10959 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\cia1__data_o$next[63:0]$10961 \d_wr11__data_i case assign $5\cia1__data_o$next[63:0]$10961 $4\cia1__data_o$next[63:0]$10960 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\cia1__data_o$next[63:0]$10962 \reg case assign $6\cia1__data_o$next[63:0]$10962 $5\cia1__data_o$next[63:0]$10961 end case assign $1\cia1__data_o$next[63:0]$10957 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\cia1__data_o$next[63:0]$10963 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\cia1__data_o$next[63:0]$10963 $1\cia1__data_o$next[63:0]$10957 end sync always update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10956 end attribute \src "libresoc.v:179768.3-179803.6" process $proc$libresoc.v:179768$10964 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:179769.5-179769.29" switch \initial attribute \src "libresoc.v:179769.9-179769.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \cia1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect[0:0] 1'1 case assign $5\wr_detect[0:0] $4\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:179804.3-179849.6" process $proc$libresoc.v:179804$10965 assign { } { } assign { } { } assign { } { } assign $0\msr1__data_o$next[63:0]$10966 $7\msr1__data_o$next[63:0]$10973 attribute \src "libresoc.v:179805.5-179805.29" switch \initial attribute \src "libresoc.v:179805.9-179805.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \msr1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\msr1__data_o$next[63:0]$10967 $6\msr1__data_o$next[63:0]$10972 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\msr1__data_o$next[63:0]$10968 \nia1__data_i case assign $2\msr1__data_o$next[63:0]$10968 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\msr1__data_o$next[63:0]$10969 \msr1__data_i case assign $3\msr1__data_o$next[63:0]$10969 $2\msr1__data_o$next[63:0]$10968 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\msr1__data_o$next[63:0]$10970 \sv1__data_i case assign $4\msr1__data_o$next[63:0]$10970 $3\msr1__data_o$next[63:0]$10969 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\msr1__data_o$next[63:0]$10971 \d_wr11__data_i case assign $5\msr1__data_o$next[63:0]$10971 $4\msr1__data_o$next[63:0]$10970 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\msr1__data_o$next[63:0]$10972 \reg case assign $6\msr1__data_o$next[63:0]$10972 $5\msr1__data_o$next[63:0]$10971 end case assign $1\msr1__data_o$next[63:0]$10967 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\msr1__data_o$next[63:0]$10973 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\msr1__data_o$next[63:0]$10973 $1\msr1__data_o$next[63:0]$10967 end sync always update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10966 end attribute \src "libresoc.v:179850.3-179885.6" process $proc$libresoc.v:179850$10974 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10975 $1\wr_detect$4[0:0]$10976 attribute \src "libresoc.v:179851.5-179851.29" switch \initial attribute \src "libresoc.v:179851.9-179851.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \msr1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$10976 $5\wr_detect$4[0:0]$10980 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$10977 1'1 case assign $2\wr_detect$4[0:0]$10977 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$10978 1'1 case assign $3\wr_detect$4[0:0]$10978 $2\wr_detect$4[0:0]$10977 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$10979 1'1 case assign $4\wr_detect$4[0:0]$10979 $3\wr_detect$4[0:0]$10978 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$4[0:0]$10980 1'1 case assign $5\wr_detect$4[0:0]$10980 $4\wr_detect$4[0:0]$10979 end case assign $1\wr_detect$4[0:0]$10976 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10975 end attribute \src "libresoc.v:179886.3-179931.6" process $proc$libresoc.v:179886$10981 assign { } { } assign { } { } assign { } { } assign $0\sv1__data_o$next[63:0]$10982 $7\sv1__data_o$next[63:0]$10989 attribute \src "libresoc.v:179887.5-179887.29" switch \initial attribute \src "libresoc.v:179887.9-179887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \sv1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\sv1__data_o$next[63:0]$10983 $6\sv1__data_o$next[63:0]$10988 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sv1__data_o$next[63:0]$10984 \nia1__data_i case assign $2\sv1__data_o$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\sv1__data_o$next[63:0]$10985 \msr1__data_i case assign $3\sv1__data_o$next[63:0]$10985 $2\sv1__data_o$next[63:0]$10984 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\sv1__data_o$next[63:0]$10986 \sv1__data_i case assign $4\sv1__data_o$next[63:0]$10986 $3\sv1__data_o$next[63:0]$10985 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\sv1__data_o$next[63:0]$10987 \d_wr11__data_i case assign $5\sv1__data_o$next[63:0]$10987 $4\sv1__data_o$next[63:0]$10986 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\sv1__data_o$next[63:0]$10988 \reg case assign $6\sv1__data_o$next[63:0]$10988 $5\sv1__data_o$next[63:0]$10987 end case assign $1\sv1__data_o$next[63:0]$10983 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\sv1__data_o$next[63:0]$10989 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\sv1__data_o$next[63:0]$10989 $1\sv1__data_o$next[63:0]$10983 end sync always update \sv1__data_o$next $0\sv1__data_o$next[63:0]$10982 end attribute \src "libresoc.v:179932.3-179967.6" process $proc$libresoc.v:179932$10990 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10991 $1\wr_detect$7[0:0]$10992 attribute \src "libresoc.v:179933.5-179933.29" switch \initial attribute \src "libresoc.v:179933.9-179933.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \sv1__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$10992 $5\wr_detect$7[0:0]$10996 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$10993 1'1 case assign $2\wr_detect$7[0:0]$10993 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$10994 1'1 case assign $3\wr_detect$7[0:0]$10994 $2\wr_detect$7[0:0]$10993 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$10995 1'1 case assign $4\wr_detect$7[0:0]$10995 $3\wr_detect$7[0:0]$10994 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$7[0:0]$10996 1'1 case assign $5\wr_detect$7[0:0]$10996 $4\wr_detect$7[0:0]$10995 end case assign $1\wr_detect$7[0:0]$10992 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10991 end attribute \src "libresoc.v:179968.3-180000.6" process $proc$libresoc.v:179968$10997 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[63:0]$10998 $5\reg$next[63:0]$11003 attribute \src "libresoc.v:179969.5-179969.29" switch \initial attribute \src "libresoc.v:179969.9-179969.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[63:0]$10999 \nia1__data_i case assign $1\reg$next[63:0]$10999 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[63:0]$11000 \msr1__data_i case assign $2\reg$next[63:0]$11000 $1\reg$next[63:0]$10999 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[63:0]$11001 \sv1__data_i case assign $3\reg$next[63:0]$11001 $2\reg$next[63:0]$11000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[63:0]$11002 \d_wr11__data_i case assign $4\reg$next[63:0]$11002 $3\reg$next[63:0]$11001 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\reg$next[63:0]$11003 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $5\reg$next[63:0]$11003 $4\reg$next[63:0]$11002 end sync always update \reg$next $0\reg$next[63:0]$10998 end connect \$1 $not$libresoc.v:179711$10948_Y connect \$3 $not$libresoc.v:179712$10949_Y connect \$6 $not$libresoc.v:179713$10950_Y end attribute \src "libresoc.v:180005.1-180476.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 attribute \src "libresoc.v:180006.7-180006.20" wire $0\initial[0:0] attribute \src "libresoc.v:180406.3-180445.6" wire width 4 $0\r22__data_o$next[3:0]$11078 attribute \src "libresoc.v:180089.3-180090.39" wire width 4 $0\r22__data_o[3:0] attribute \src "libresoc.v:180336.3-180375.6" wire width 4 $0\r2__data_o$next[3:0]$11064 attribute \src "libresoc.v:180091.3-180092.37" wire width 4 $0\r2__data_o[3:0] attribute \src "libresoc.v:180169.3-180195.6" wire width 4 $0\reg$next[3:0]$11030 attribute \src "libresoc.v:180087.3-180088.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:180099.3-180138.6" wire width 4 $0\src12__data_o$next[3:0]$11021 attribute \src "libresoc.v:180097.3-180098.43" wire width 4 $0\src12__data_o[3:0] attribute \src "libresoc.v:180196.3-180235.6" wire width 4 $0\src22__data_o$next[3:0]$11036 attribute \src "libresoc.v:180095.3-180096.43" wire width 4 $0\src22__data_o[3:0] attribute \src "libresoc.v:180266.3-180305.6" wire width 4 $0\src32__data_o$next[3:0]$11050 attribute \src "libresoc.v:180093.3-180094.43" wire width 4 $0\src32__data_o[3:0] attribute \src "libresoc.v:180376.3-180405.6" wire $0\wr_detect$10[0:0]$11072 attribute \src "libresoc.v:180446.3-180475.6" wire $0\wr_detect$13[0:0]$11086 attribute \src "libresoc.v:180236.3-180265.6" wire $0\wr_detect$4[0:0]$11044 attribute \src "libresoc.v:180306.3-180335.6" wire $0\wr_detect$7[0:0]$11058 attribute \src "libresoc.v:180139.3-180168.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:180406.3-180445.6" wire width 4 $1\r22__data_o$next[3:0]$11079 attribute \src "libresoc.v:180031.13-180031.31" wire width 4 $1\r22__data_o[3:0] attribute \src "libresoc.v:180336.3-180375.6" wire width 4 $1\r2__data_o$next[3:0]$11065 attribute \src "libresoc.v:180038.13-180038.30" wire width 4 $1\r2__data_o[3:0] attribute \src "libresoc.v:180169.3-180195.6" wire width 4 $1\reg$next[3:0]$11031 attribute \src "libresoc.v:180044.13-180044.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:180099.3-180138.6" wire width 4 $1\src12__data_o$next[3:0]$11022 attribute \src "libresoc.v:180049.13-180049.33" wire width 4 $1\src12__data_o[3:0] attribute \src "libresoc.v:180196.3-180235.6" wire width 4 $1\src22__data_o$next[3:0]$11037 attribute \src "libresoc.v:180056.13-180056.33" wire width 4 $1\src22__data_o[3:0] attribute \src "libresoc.v:180266.3-180305.6" wire width 4 $1\src32__data_o$next[3:0]$11051 attribute \src "libresoc.v:180063.13-180063.33" wire width 4 $1\src32__data_o[3:0] attribute \src "libresoc.v:180376.3-180405.6" wire $1\wr_detect$10[0:0]$11073 attribute \src "libresoc.v:180446.3-180475.6" wire $1\wr_detect$13[0:0]$11087 attribute \src "libresoc.v:180236.3-180265.6" wire $1\wr_detect$4[0:0]$11045 attribute \src "libresoc.v:180306.3-180335.6" wire $1\wr_detect$7[0:0]$11059 attribute \src "libresoc.v:180139.3-180168.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:180406.3-180445.6" wire width 4 $2\r22__data_o$next[3:0]$11080 attribute \src "libresoc.v:180336.3-180375.6" wire width 4 $2\r2__data_o$next[3:0]$11066 attribute \src "libresoc.v:180169.3-180195.6" wire width 4 $2\reg$next[3:0]$11032 attribute \src "libresoc.v:180099.3-180138.6" wire width 4 $2\src12__data_o$next[3:0]$11023 attribute \src "libresoc.v:180196.3-180235.6" wire width 4 $2\src22__data_o$next[3:0]$11038 attribute \src "libresoc.v:180266.3-180305.6" wire width 4 $2\src32__data_o$next[3:0]$11052 attribute \src "libresoc.v:180376.3-180405.6" wire $2\wr_detect$10[0:0]$11074 attribute \src "libresoc.v:180446.3-180475.6" wire $2\wr_detect$13[0:0]$11088 attribute \src "libresoc.v:180236.3-180265.6" wire $2\wr_detect$4[0:0]$11046 attribute \src "libresoc.v:180306.3-180335.6" wire $2\wr_detect$7[0:0]$11060 attribute \src "libresoc.v:180139.3-180168.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:180406.3-180445.6" wire width 4 $3\r22__data_o$next[3:0]$11081 attribute \src "libresoc.v:180336.3-180375.6" wire width 4 $3\r2__data_o$next[3:0]$11067 attribute \src "libresoc.v:180169.3-180195.6" wire width 4 $3\reg$next[3:0]$11033 attribute \src "libresoc.v:180099.3-180138.6" wire width 4 $3\src12__data_o$next[3:0]$11024 attribute \src "libresoc.v:180196.3-180235.6" wire width 4 $3\src22__data_o$next[3:0]$11039 attribute \src "libresoc.v:180266.3-180305.6" wire width 4 $3\src32__data_o$next[3:0]$11053 attribute \src "libresoc.v:180376.3-180405.6" wire $3\wr_detect$10[0:0]$11075 attribute \src "libresoc.v:180446.3-180475.6" wire $3\wr_detect$13[0:0]$11089 attribute \src "libresoc.v:180236.3-180265.6" wire $3\wr_detect$4[0:0]$11047 attribute \src "libresoc.v:180306.3-180335.6" wire $3\wr_detect$7[0:0]$11061 attribute \src "libresoc.v:180139.3-180168.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:180406.3-180445.6" wire width 4 $4\r22__data_o$next[3:0]$11082 attribute \src "libresoc.v:180336.3-180375.6" wire width 4 $4\r2__data_o$next[3:0]$11068 attribute \src "libresoc.v:180169.3-180195.6" wire width 4 $4\reg$next[3:0]$11034 attribute \src "libresoc.v:180099.3-180138.6" wire width 4 $4\src12__data_o$next[3:0]$11025 attribute \src "libresoc.v:180196.3-180235.6" wire width 4 $4\src22__data_o$next[3:0]$11040 attribute \src "libresoc.v:180266.3-180305.6" wire width 4 $4\src32__data_o$next[3:0]$11054 attribute \src "libresoc.v:180376.3-180405.6" wire $4\wr_detect$10[0:0]$11076 attribute \src "libresoc.v:180446.3-180475.6" wire $4\wr_detect$13[0:0]$11090 attribute \src "libresoc.v:180236.3-180265.6" wire $4\wr_detect$4[0:0]$11048 attribute \src "libresoc.v:180306.3-180335.6" wire $4\wr_detect$7[0:0]$11062 attribute \src "libresoc.v:180139.3-180168.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:180406.3-180445.6" wire width 4 $5\r22__data_o$next[3:0]$11083 attribute \src "libresoc.v:180336.3-180375.6" wire width 4 $5\r2__data_o$next[3:0]$11069 attribute \src "libresoc.v:180099.3-180138.6" wire width 4 $5\src12__data_o$next[3:0]$11026 attribute \src "libresoc.v:180196.3-180235.6" wire width 4 $5\src22__data_o$next[3:0]$11041 attribute \src "libresoc.v:180266.3-180305.6" wire width 4 $5\src32__data_o$next[3:0]$11055 attribute \src "libresoc.v:180406.3-180445.6" wire width 4 $6\r22__data_o$next[3:0]$11084 attribute \src "libresoc.v:180336.3-180375.6" wire width 4 $6\r2__data_o$next[3:0]$11070 attribute \src "libresoc.v:180099.3-180138.6" wire width 4 $6\src12__data_o$next[3:0]$11027 attribute \src "libresoc.v:180196.3-180235.6" wire width 4 $6\src22__data_o$next[3:0]$11042 attribute \src "libresoc.v:180266.3-180305.6" wire width 4 $6\src32__data_o$next[3:0]$11056 attribute \src "libresoc.v:180082.17-180082.104" wire $not$libresoc.v:180082$11009_Y attribute \src "libresoc.v:180083.18-180083.105" wire $not$libresoc.v:180083$11010_Y attribute \src "libresoc.v:180084.17-180084.100" wire $not$libresoc.v:180084$11011_Y attribute \src "libresoc.v:180085.17-180085.103" wire $not$libresoc.v:180085$11012_Y attribute \src "libresoc.v:180086.17-180086.103" wire $not$libresoc.v:180086$11013_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest22__wen attribute \src "libresoc.v:180006.7-180006.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src12__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src12__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src12__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src32__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src32__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src32__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180082$11009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:180082$11009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180083$11010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:180083$11010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180084$11011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:180084$11011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180085$11012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:180085$11012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180086$11013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:180086$11013_Y end attribute \src "libresoc.v:180006.7-180006.20" process $proc$libresoc.v:180006$11091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:180031.13-180031.31" process $proc$libresoc.v:180031$11092 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end attribute \src "libresoc.v:180038.13-180038.30" process $proc$libresoc.v:180038$11093 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end attribute \src "libresoc.v:180044.13-180044.25" process $proc$libresoc.v:180044$11094 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:180049.13-180049.33" process $proc$libresoc.v:180049$11095 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end attribute \src "libresoc.v:180056.13-180056.33" process $proc$libresoc.v:180056$11096 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end attribute \src "libresoc.v:180063.13-180063.33" process $proc$libresoc.v:180063$11097 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end attribute \src "libresoc.v:180087.3-180088.25" process $proc$libresoc.v:180087$11014 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:180089.3-180090.39" process $proc$libresoc.v:180089$11015 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end attribute \src "libresoc.v:180091.3-180092.37" process $proc$libresoc.v:180091$11016 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end attribute \src "libresoc.v:180093.3-180094.43" process $proc$libresoc.v:180093$11017 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end attribute \src "libresoc.v:180095.3-180096.43" process $proc$libresoc.v:180095$11018 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end attribute \src "libresoc.v:180097.3-180098.43" process $proc$libresoc.v:180097$11019 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end attribute \src "libresoc.v:180099.3-180138.6" process $proc$libresoc.v:180099$11020 assign { } { } assign { } { } assign { } { } assign $0\src12__data_o$next[3:0]$11021 $6\src12__data_o$next[3:0]$11027 attribute \src "libresoc.v:180100.5-180100.29" switch \initial attribute \src "libresoc.v:180100.9-180100.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src12__data_o$next[3:0]$11022 $5\src12__data_o$next[3:0]$11026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src12__data_o$next[3:0]$11023 \dest12__data_i case assign $2\src12__data_o$next[3:0]$11023 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src12__data_o$next[3:0]$11024 \dest22__data_i case assign $3\src12__data_o$next[3:0]$11024 $2\src12__data_o$next[3:0]$11023 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src12__data_o$next[3:0]$11025 \w2__data_i case assign $4\src12__data_o$next[3:0]$11025 $3\src12__data_o$next[3:0]$11024 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src12__data_o$next[3:0]$11026 \reg case assign $5\src12__data_o$next[3:0]$11026 $4\src12__data_o$next[3:0]$11025 end case assign $1\src12__data_o$next[3:0]$11022 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src12__data_o$next[3:0]$11027 4'0000 case assign $6\src12__data_o$next[3:0]$11027 $1\src12__data_o$next[3:0]$11022 end sync always update \src12__data_o$next $0\src12__data_o$next[3:0]$11021 end attribute \src "libresoc.v:180139.3-180168.6" process $proc$libresoc.v:180139$11028 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:180140.5-180140.29" switch \initial attribute \src "libresoc.v:180140.9-180140.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:180169.3-180195.6" process $proc$libresoc.v:180169$11029 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11030 $4\reg$next[3:0]$11034 attribute \src "libresoc.v:180170.5-180170.29" switch \initial attribute \src "libresoc.v:180170.9-180170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$11031 \dest12__data_i case assign $1\reg$next[3:0]$11031 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$11032 \dest22__data_i case assign $2\reg$next[3:0]$11032 $1\reg$next[3:0]$11031 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$11033 \w2__data_i case assign $3\reg$next[3:0]$11033 $2\reg$next[3:0]$11032 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$11034 4'0000 case assign $4\reg$next[3:0]$11034 $3\reg$next[3:0]$11033 end sync always update \reg$next $0\reg$next[3:0]$11030 end attribute \src "libresoc.v:180196.3-180235.6" process $proc$libresoc.v:180196$11035 assign { } { } assign { } { } assign { } { } assign $0\src22__data_o$next[3:0]$11036 $6\src22__data_o$next[3:0]$11042 attribute \src "libresoc.v:180197.5-180197.29" switch \initial attribute \src "libresoc.v:180197.9-180197.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src22__data_o$next[3:0]$11037 $5\src22__data_o$next[3:0]$11041 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src22__data_o$next[3:0]$11038 \dest12__data_i case assign $2\src22__data_o$next[3:0]$11038 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src22__data_o$next[3:0]$11039 \dest22__data_i case assign $3\src22__data_o$next[3:0]$11039 $2\src22__data_o$next[3:0]$11038 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src22__data_o$next[3:0]$11040 \w2__data_i case assign $4\src22__data_o$next[3:0]$11040 $3\src22__data_o$next[3:0]$11039 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src22__data_o$next[3:0]$11041 \reg case assign $5\src22__data_o$next[3:0]$11041 $4\src22__data_o$next[3:0]$11040 end case assign $1\src22__data_o$next[3:0]$11037 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src22__data_o$next[3:0]$11042 4'0000 case assign $6\src22__data_o$next[3:0]$11042 $1\src22__data_o$next[3:0]$11037 end sync always update \src22__data_o$next $0\src22__data_o$next[3:0]$11036 end attribute \src "libresoc.v:180236.3-180265.6" process $proc$libresoc.v:180236$11043 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11044 $1\wr_detect$4[0:0]$11045 attribute \src "libresoc.v:180237.5-180237.29" switch \initial attribute \src "libresoc.v:180237.9-180237.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11045 $4\wr_detect$4[0:0]$11048 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11046 1'1 case assign $2\wr_detect$4[0:0]$11046 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11047 1'1 case assign $3\wr_detect$4[0:0]$11047 $2\wr_detect$4[0:0]$11046 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11048 1'1 case assign $4\wr_detect$4[0:0]$11048 $3\wr_detect$4[0:0]$11047 end case assign $1\wr_detect$4[0:0]$11045 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11044 end attribute \src "libresoc.v:180266.3-180305.6" process $proc$libresoc.v:180266$11049 assign { } { } assign { } { } assign { } { } assign $0\src32__data_o$next[3:0]$11050 $6\src32__data_o$next[3:0]$11056 attribute \src "libresoc.v:180267.5-180267.29" switch \initial attribute \src "libresoc.v:180267.9-180267.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src32__data_o$next[3:0]$11051 $5\src32__data_o$next[3:0]$11055 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src32__data_o$next[3:0]$11052 \dest12__data_i case assign $2\src32__data_o$next[3:0]$11052 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src32__data_o$next[3:0]$11053 \dest22__data_i case assign $3\src32__data_o$next[3:0]$11053 $2\src32__data_o$next[3:0]$11052 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src32__data_o$next[3:0]$11054 \w2__data_i case assign $4\src32__data_o$next[3:0]$11054 $3\src32__data_o$next[3:0]$11053 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src32__data_o$next[3:0]$11055 \reg case assign $5\src32__data_o$next[3:0]$11055 $4\src32__data_o$next[3:0]$11054 end case assign $1\src32__data_o$next[3:0]$11051 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src32__data_o$next[3:0]$11056 4'0000 case assign $6\src32__data_o$next[3:0]$11056 $1\src32__data_o$next[3:0]$11051 end sync always update \src32__data_o$next $0\src32__data_o$next[3:0]$11050 end attribute \src "libresoc.v:180306.3-180335.6" process $proc$libresoc.v:180306$11057 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11058 $1\wr_detect$7[0:0]$11059 attribute \src "libresoc.v:180307.5-180307.29" switch \initial attribute \src "libresoc.v:180307.9-180307.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11059 $4\wr_detect$7[0:0]$11062 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11060 1'1 case assign $2\wr_detect$7[0:0]$11060 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11061 1'1 case assign $3\wr_detect$7[0:0]$11061 $2\wr_detect$7[0:0]$11060 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11062 1'1 case assign $4\wr_detect$7[0:0]$11062 $3\wr_detect$7[0:0]$11061 end case assign $1\wr_detect$7[0:0]$11059 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11058 end attribute \src "libresoc.v:180336.3-180375.6" process $proc$libresoc.v:180336$11063 assign { } { } assign { } { } assign { } { } assign $0\r2__data_o$next[3:0]$11064 $6\r2__data_o$next[3:0]$11070 attribute \src "libresoc.v:180337.5-180337.29" switch \initial attribute \src "libresoc.v:180337.9-180337.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r2__data_o$next[3:0]$11065 $5\r2__data_o$next[3:0]$11069 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r2__data_o$next[3:0]$11066 \dest12__data_i case assign $2\r2__data_o$next[3:0]$11066 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r2__data_o$next[3:0]$11067 \dest22__data_i case assign $3\r2__data_o$next[3:0]$11067 $2\r2__data_o$next[3:0]$11066 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r2__data_o$next[3:0]$11068 \w2__data_i case assign $4\r2__data_o$next[3:0]$11068 $3\r2__data_o$next[3:0]$11067 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r2__data_o$next[3:0]$11069 \reg case assign $5\r2__data_o$next[3:0]$11069 $4\r2__data_o$next[3:0]$11068 end case assign $1\r2__data_o$next[3:0]$11065 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r2__data_o$next[3:0]$11070 4'0000 case assign $6\r2__data_o$next[3:0]$11070 $1\r2__data_o$next[3:0]$11065 end sync always update \r2__data_o$next $0\r2__data_o$next[3:0]$11064 end attribute \src "libresoc.v:180376.3-180405.6" process $proc$libresoc.v:180376$11071 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11072 $1\wr_detect$10[0:0]$11073 attribute \src "libresoc.v:180377.5-180377.29" switch \initial attribute \src "libresoc.v:180377.9-180377.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$11073 $4\wr_detect$10[0:0]$11076 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$11074 1'1 case assign $2\wr_detect$10[0:0]$11074 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$11075 1'1 case assign $3\wr_detect$10[0:0]$11075 $2\wr_detect$10[0:0]$11074 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$11076 1'1 case assign $4\wr_detect$10[0:0]$11076 $3\wr_detect$10[0:0]$11075 end case assign $1\wr_detect$10[0:0]$11073 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11072 end attribute \src "libresoc.v:180406.3-180445.6" process $proc$libresoc.v:180406$11077 assign { } { } assign { } { } assign { } { } assign $0\r22__data_o$next[3:0]$11078 $6\r22__data_o$next[3:0]$11084 attribute \src "libresoc.v:180407.5-180407.29" switch \initial attribute \src "libresoc.v:180407.9-180407.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r22__data_o$next[3:0]$11079 $5\r22__data_o$next[3:0]$11083 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r22__data_o$next[3:0]$11080 \dest12__data_i case assign $2\r22__data_o$next[3:0]$11080 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r22__data_o$next[3:0]$11081 \dest22__data_i case assign $3\r22__data_o$next[3:0]$11081 $2\r22__data_o$next[3:0]$11080 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r22__data_o$next[3:0]$11082 \w2__data_i case assign $4\r22__data_o$next[3:0]$11082 $3\r22__data_o$next[3:0]$11081 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r22__data_o$next[3:0]$11083 \reg case assign $5\r22__data_o$next[3:0]$11083 $4\r22__data_o$next[3:0]$11082 end case assign $1\r22__data_o$next[3:0]$11079 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r22__data_o$next[3:0]$11084 4'0000 case assign $6\r22__data_o$next[3:0]$11084 $1\r22__data_o$next[3:0]$11079 end sync always update \r22__data_o$next $0\r22__data_o$next[3:0]$11078 end attribute \src "libresoc.v:180446.3-180475.6" process $proc$libresoc.v:180446$11085 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11086 $1\wr_detect$13[0:0]$11087 attribute \src "libresoc.v:180447.5-180447.29" switch \initial attribute \src "libresoc.v:180447.9-180447.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$11087 $4\wr_detect$13[0:0]$11090 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$11088 1'1 case assign $2\wr_detect$13[0:0]$11088 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$11089 1'1 case assign $3\wr_detect$13[0:0]$11089 $2\wr_detect$13[0:0]$11088 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$11090 1'1 case assign $4\wr_detect$13[0:0]$11090 $3\wr_detect$13[0:0]$11089 end case assign $1\wr_detect$13[0:0]$11087 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11086 end connect \$9 $not$libresoc.v:180082$11009_Y connect \$12 $not$libresoc.v:180083$11010_Y connect \$1 $not$libresoc.v:180084$11011_Y connect \$3 $not$libresoc.v:180085$11012_Y connect \$6 $not$libresoc.v:180086$11013_Y end attribute \src "libresoc.v:180480.1-180925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 attribute \src "libresoc.v:180481.7-180481.20" wire $0\initial[0:0] attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $0\r2__data_o$next[1:0]$11150 attribute \src "libresoc.v:180556.3-180557.37" wire width 2 $0\r2__data_o[1:0] attribute \src "libresoc.v:180892.3-180924.6" wire width 2 $0\reg$next[1:0]$11166 attribute \src "libresoc.v:180554.3-180555.25" wire width 2 $0\reg[1:0] attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $0\src12__data_o$next[1:0]$11108 attribute \src "libresoc.v:180562.3-180563.43" wire width 2 $0\src12__data_o[1:0] attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $0\src22__data_o$next[1:0]$11118 attribute \src "libresoc.v:180560.3-180561.43" wire width 2 $0\src22__data_o[1:0] attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $0\src32__data_o$next[1:0]$11134 attribute \src "libresoc.v:180558.3-180559.43" wire width 2 $0\src32__data_o[1:0] attribute \src "libresoc.v:180856.3-180891.6" wire $0\wr_detect$10[0:0]$11159 attribute \src "libresoc.v:180692.3-180727.6" wire $0\wr_detect$4[0:0]$11127 attribute \src "libresoc.v:180774.3-180809.6" wire $0\wr_detect$7[0:0]$11143 attribute \src "libresoc.v:180610.3-180645.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $1\r2__data_o$next[1:0]$11151 attribute \src "libresoc.v:180508.13-180508.30" wire width 2 $1\r2__data_o[1:0] attribute \src "libresoc.v:180892.3-180924.6" wire width 2 $1\reg$next[1:0]$11167 attribute \src "libresoc.v:180514.13-180514.25" wire width 2 $1\reg[1:0] attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $1\src12__data_o$next[1:0]$11109 attribute \src "libresoc.v:180519.13-180519.33" wire width 2 $1\src12__data_o[1:0] attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $1\src22__data_o$next[1:0]$11119 attribute \src "libresoc.v:180526.13-180526.33" wire width 2 $1\src22__data_o[1:0] attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $1\src32__data_o$next[1:0]$11135 attribute \src "libresoc.v:180533.13-180533.33" wire width 2 $1\src32__data_o[1:0] attribute \src "libresoc.v:180856.3-180891.6" wire $1\wr_detect$10[0:0]$11160 attribute \src "libresoc.v:180692.3-180727.6" wire $1\wr_detect$4[0:0]$11128 attribute \src "libresoc.v:180774.3-180809.6" wire $1\wr_detect$7[0:0]$11144 attribute \src "libresoc.v:180610.3-180645.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $2\r2__data_o$next[1:0]$11152 attribute \src "libresoc.v:180892.3-180924.6" wire width 2 $2\reg$next[1:0]$11168 attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $2\src12__data_o$next[1:0]$11110 attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $2\src22__data_o$next[1:0]$11120 attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $2\src32__data_o$next[1:0]$11136 attribute \src "libresoc.v:180856.3-180891.6" wire $2\wr_detect$10[0:0]$11161 attribute \src "libresoc.v:180692.3-180727.6" wire $2\wr_detect$4[0:0]$11129 attribute \src "libresoc.v:180774.3-180809.6" wire $2\wr_detect$7[0:0]$11145 attribute \src "libresoc.v:180610.3-180645.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $3\r2__data_o$next[1:0]$11153 attribute \src "libresoc.v:180892.3-180924.6" wire width 2 $3\reg$next[1:0]$11169 attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $3\src12__data_o$next[1:0]$11111 attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $3\src22__data_o$next[1:0]$11121 attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $3\src32__data_o$next[1:0]$11137 attribute \src "libresoc.v:180856.3-180891.6" wire $3\wr_detect$10[0:0]$11162 attribute \src "libresoc.v:180692.3-180727.6" wire $3\wr_detect$4[0:0]$11130 attribute \src "libresoc.v:180774.3-180809.6" wire $3\wr_detect$7[0:0]$11146 attribute \src "libresoc.v:180610.3-180645.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $4\r2__data_o$next[1:0]$11154 attribute \src "libresoc.v:180892.3-180924.6" wire width 2 $4\reg$next[1:0]$11170 attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $4\src12__data_o$next[1:0]$11112 attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $4\src22__data_o$next[1:0]$11122 attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $4\src32__data_o$next[1:0]$11138 attribute \src "libresoc.v:180856.3-180891.6" wire $4\wr_detect$10[0:0]$11163 attribute \src "libresoc.v:180692.3-180727.6" wire $4\wr_detect$4[0:0]$11131 attribute \src "libresoc.v:180774.3-180809.6" wire $4\wr_detect$7[0:0]$11147 attribute \src "libresoc.v:180610.3-180645.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $5\r2__data_o$next[1:0]$11155 attribute \src "libresoc.v:180892.3-180924.6" wire width 2 $5\reg$next[1:0]$11171 attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $5\src12__data_o$next[1:0]$11113 attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $5\src22__data_o$next[1:0]$11123 attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $5\src32__data_o$next[1:0]$11139 attribute \src "libresoc.v:180856.3-180891.6" wire $5\wr_detect$10[0:0]$11164 attribute \src "libresoc.v:180692.3-180727.6" wire $5\wr_detect$4[0:0]$11132 attribute \src "libresoc.v:180774.3-180809.6" wire $5\wr_detect$7[0:0]$11148 attribute \src "libresoc.v:180610.3-180645.6" wire $5\wr_detect[0:0] attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $6\r2__data_o$next[1:0]$11156 attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $6\src12__data_o$next[1:0]$11114 attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $6\src22__data_o$next[1:0]$11124 attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $6\src32__data_o$next[1:0]$11140 attribute \src "libresoc.v:180810.3-180855.6" wire width 2 $7\r2__data_o$next[1:0]$11157 attribute \src "libresoc.v:180564.3-180609.6" wire width 2 $7\src12__data_o$next[1:0]$11115 attribute \src "libresoc.v:180646.3-180691.6" wire width 2 $7\src22__data_o$next[1:0]$11125 attribute \src "libresoc.v:180728.3-180773.6" wire width 2 $7\src32__data_o$next[1:0]$11141 attribute \src "libresoc.v:180550.17-180550.104" wire $not$libresoc.v:180550$11098_Y attribute \src "libresoc.v:180551.17-180551.100" wire $not$libresoc.v:180551$11099_Y attribute \src "libresoc.v:180552.17-180552.103" wire $not$libresoc.v:180552$11100_Y attribute \src "libresoc.v:180553.17-180553.103" wire $not$libresoc.v:180553$11101_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 11 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest22__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen attribute \src "libresoc.v:180481.7-180481.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \r2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 2 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 3 \src12__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src12__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src12__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 5 \src22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src22__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 7 \src32__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \src32__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src32__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 16 \w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180550$11098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:180550$11098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180551$11099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:180551$11099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180552$11100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:180552$11100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180553$11101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:180553$11101_Y end attribute \src "libresoc.v:180481.7-180481.20" process $proc$libresoc.v:180481$11172 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:180508.13-180508.30" process $proc$libresoc.v:180508$11173 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end attribute \src "libresoc.v:180514.13-180514.25" process $proc$libresoc.v:180514$11174 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end attribute \src "libresoc.v:180519.13-180519.33" process $proc$libresoc.v:180519$11175 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end attribute \src "libresoc.v:180526.13-180526.33" process $proc$libresoc.v:180526$11176 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end attribute \src "libresoc.v:180533.13-180533.33" process $proc$libresoc.v:180533$11177 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end attribute \src "libresoc.v:180554.3-180555.25" process $proc$libresoc.v:180554$11102 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end attribute \src "libresoc.v:180556.3-180557.37" process $proc$libresoc.v:180556$11103 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end attribute \src "libresoc.v:180558.3-180559.43" process $proc$libresoc.v:180558$11104 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end attribute \src "libresoc.v:180560.3-180561.43" process $proc$libresoc.v:180560$11105 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end attribute \src "libresoc.v:180562.3-180563.43" process $proc$libresoc.v:180562$11106 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end attribute \src "libresoc.v:180564.3-180609.6" process $proc$libresoc.v:180564$11107 assign { } { } assign { } { } assign { } { } assign $0\src12__data_o$next[1:0]$11108 $7\src12__data_o$next[1:0]$11115 attribute \src "libresoc.v:180565.5-180565.29" switch \initial attribute \src "libresoc.v:180565.9-180565.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src12__data_o$next[1:0]$11109 $6\src12__data_o$next[1:0]$11114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src12__data_o$next[1:0]$11110 \dest12__data_i case assign $2\src12__data_o$next[1:0]$11110 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src12__data_o$next[1:0]$11111 \dest22__data_i case assign $3\src12__data_o$next[1:0]$11111 $2\src12__data_o$next[1:0]$11110 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src12__data_o$next[1:0]$11112 \dest32__data_i case assign $4\src12__data_o$next[1:0]$11112 $3\src12__data_o$next[1:0]$11111 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src12__data_o$next[1:0]$11113 \w2__data_i case assign $5\src12__data_o$next[1:0]$11113 $4\src12__data_o$next[1:0]$11112 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src12__data_o$next[1:0]$11114 \reg case assign $6\src12__data_o$next[1:0]$11114 $5\src12__data_o$next[1:0]$11113 end case assign $1\src12__data_o$next[1:0]$11109 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src12__data_o$next[1:0]$11115 2'00 case assign $7\src12__data_o$next[1:0]$11115 $1\src12__data_o$next[1:0]$11109 end sync always update \src12__data_o$next $0\src12__data_o$next[1:0]$11108 end attribute \src "libresoc.v:180610.3-180645.6" process $proc$libresoc.v:180610$11116 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:180611.5-180611.29" switch \initial attribute \src "libresoc.v:180611.9-180611.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src12__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect[0:0] 1'1 case assign $5\wr_detect[0:0] $4\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:180646.3-180691.6" process $proc$libresoc.v:180646$11117 assign { } { } assign { } { } assign { } { } assign $0\src22__data_o$next[1:0]$11118 $7\src22__data_o$next[1:0]$11125 attribute \src "libresoc.v:180647.5-180647.29" switch \initial attribute \src "libresoc.v:180647.9-180647.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src22__data_o$next[1:0]$11119 $6\src22__data_o$next[1:0]$11124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src22__data_o$next[1:0]$11120 \dest12__data_i case assign $2\src22__data_o$next[1:0]$11120 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src22__data_o$next[1:0]$11121 \dest22__data_i case assign $3\src22__data_o$next[1:0]$11121 $2\src22__data_o$next[1:0]$11120 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src22__data_o$next[1:0]$11122 \dest32__data_i case assign $4\src22__data_o$next[1:0]$11122 $3\src22__data_o$next[1:0]$11121 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src22__data_o$next[1:0]$11123 \w2__data_i case assign $5\src22__data_o$next[1:0]$11123 $4\src22__data_o$next[1:0]$11122 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src22__data_o$next[1:0]$11124 \reg case assign $6\src22__data_o$next[1:0]$11124 $5\src22__data_o$next[1:0]$11123 end case assign $1\src22__data_o$next[1:0]$11119 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src22__data_o$next[1:0]$11125 2'00 case assign $7\src22__data_o$next[1:0]$11125 $1\src22__data_o$next[1:0]$11119 end sync always update \src22__data_o$next $0\src22__data_o$next[1:0]$11118 end attribute \src "libresoc.v:180692.3-180727.6" process $proc$libresoc.v:180692$11126 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11127 $1\wr_detect$4[0:0]$11128 attribute \src "libresoc.v:180693.5-180693.29" switch \initial attribute \src "libresoc.v:180693.9-180693.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src22__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11128 $5\wr_detect$4[0:0]$11132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11129 1'1 case assign $2\wr_detect$4[0:0]$11129 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11130 1'1 case assign $3\wr_detect$4[0:0]$11130 $2\wr_detect$4[0:0]$11129 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11131 1'1 case assign $4\wr_detect$4[0:0]$11131 $3\wr_detect$4[0:0]$11130 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$4[0:0]$11132 1'1 case assign $5\wr_detect$4[0:0]$11132 $4\wr_detect$4[0:0]$11131 end case assign $1\wr_detect$4[0:0]$11128 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11127 end attribute \src "libresoc.v:180728.3-180773.6" process $proc$libresoc.v:180728$11133 assign { } { } assign { } { } assign { } { } assign $0\src32__data_o$next[1:0]$11134 $7\src32__data_o$next[1:0]$11141 attribute \src "libresoc.v:180729.5-180729.29" switch \initial attribute \src "libresoc.v:180729.9-180729.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src32__data_o$next[1:0]$11135 $6\src32__data_o$next[1:0]$11140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src32__data_o$next[1:0]$11136 \dest12__data_i case assign $2\src32__data_o$next[1:0]$11136 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src32__data_o$next[1:0]$11137 \dest22__data_i case assign $3\src32__data_o$next[1:0]$11137 $2\src32__data_o$next[1:0]$11136 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src32__data_o$next[1:0]$11138 \dest32__data_i case assign $4\src32__data_o$next[1:0]$11138 $3\src32__data_o$next[1:0]$11137 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src32__data_o$next[1:0]$11139 \w2__data_i case assign $5\src32__data_o$next[1:0]$11139 $4\src32__data_o$next[1:0]$11138 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src32__data_o$next[1:0]$11140 \reg case assign $6\src32__data_o$next[1:0]$11140 $5\src32__data_o$next[1:0]$11139 end case assign $1\src32__data_o$next[1:0]$11135 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\src32__data_o$next[1:0]$11141 2'00 case assign $7\src32__data_o$next[1:0]$11141 $1\src32__data_o$next[1:0]$11135 end sync always update \src32__data_o$next $0\src32__data_o$next[1:0]$11134 end attribute \src "libresoc.v:180774.3-180809.6" process $proc$libresoc.v:180774$11142 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11143 $1\wr_detect$7[0:0]$11144 attribute \src "libresoc.v:180775.5-180775.29" switch \initial attribute \src "libresoc.v:180775.9-180775.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src32__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11144 $5\wr_detect$7[0:0]$11148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11145 1'1 case assign $2\wr_detect$7[0:0]$11145 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11146 1'1 case assign $3\wr_detect$7[0:0]$11146 $2\wr_detect$7[0:0]$11145 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11147 1'1 case assign $4\wr_detect$7[0:0]$11147 $3\wr_detect$7[0:0]$11146 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$7[0:0]$11148 1'1 case assign $5\wr_detect$7[0:0]$11148 $4\wr_detect$7[0:0]$11147 end case assign $1\wr_detect$7[0:0]$11144 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11143 end attribute \src "libresoc.v:180810.3-180855.6" process $proc$libresoc.v:180810$11149 assign { } { } assign { } { } assign { } { } assign $0\r2__data_o$next[1:0]$11150 $7\r2__data_o$next[1:0]$11157 attribute \src "libresoc.v:180811.5-180811.29" switch \initial attribute \src "libresoc.v:180811.9-180811.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r2__data_o$next[1:0]$11151 $6\r2__data_o$next[1:0]$11156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r2__data_o$next[1:0]$11152 \dest12__data_i case assign $2\r2__data_o$next[1:0]$11152 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r2__data_o$next[1:0]$11153 \dest22__data_i case assign $3\r2__data_o$next[1:0]$11153 $2\r2__data_o$next[1:0]$11152 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r2__data_o$next[1:0]$11154 \dest32__data_i case assign $4\r2__data_o$next[1:0]$11154 $3\r2__data_o$next[1:0]$11153 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r2__data_o$next[1:0]$11155 \w2__data_i case assign $5\r2__data_o$next[1:0]$11155 $4\r2__data_o$next[1:0]$11154 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r2__data_o$next[1:0]$11156 \reg case assign $6\r2__data_o$next[1:0]$11156 $5\r2__data_o$next[1:0]$11155 end case assign $1\r2__data_o$next[1:0]$11151 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\r2__data_o$next[1:0]$11157 2'00 case assign $7\r2__data_o$next[1:0]$11157 $1\r2__data_o$next[1:0]$11151 end sync always update \r2__data_o$next $0\r2__data_o$next[1:0]$11150 end attribute \src "libresoc.v:180856.3-180891.6" process $proc$libresoc.v:180856$11158 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11159 $1\wr_detect$10[0:0]$11160 attribute \src "libresoc.v:180857.5-180857.29" switch \initial attribute \src "libresoc.v:180857.9-180857.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$11160 $5\wr_detect$10[0:0]$11164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$11161 1'1 case assign $2\wr_detect$10[0:0]$11161 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$11162 1'1 case assign $3\wr_detect$10[0:0]$11162 $2\wr_detect$10[0:0]$11161 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$11163 1'1 case assign $4\wr_detect$10[0:0]$11163 $3\wr_detect$10[0:0]$11162 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$10[0:0]$11164 1'1 case assign $5\wr_detect$10[0:0]$11164 $4\wr_detect$10[0:0]$11163 end case assign $1\wr_detect$10[0:0]$11160 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11159 end attribute \src "libresoc.v:180892.3-180924.6" process $proc$libresoc.v:180892$11165 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[1:0]$11166 $5\reg$next[1:0]$11171 attribute \src "libresoc.v:180893.5-180893.29" switch \initial attribute \src "libresoc.v:180893.9-180893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[1:0]$11167 \dest12__data_i case assign $1\reg$next[1:0]$11167 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[1:0]$11168 \dest22__data_i case assign $2\reg$next[1:0]$11168 $1\reg$next[1:0]$11167 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[1:0]$11169 \dest32__data_i case assign $3\reg$next[1:0]$11169 $2\reg$next[1:0]$11168 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[1:0]$11170 \w2__data_i case assign $4\reg$next[1:0]$11170 $3\reg$next[1:0]$11169 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\reg$next[1:0]$11171 2'00 case assign $5\reg$next[1:0]$11171 $4\reg$next[1:0]$11170 end sync always update \reg$next $0\reg$next[1:0]$11166 end connect \$9 $not$libresoc.v:180550$11098_Y connect \$1 $not$libresoc.v:180551$11099_Y connect \$3 $not$libresoc.v:180552$11100_Y connect \$6 $not$libresoc.v:180553$11101_Y end attribute \src "libresoc.v:180929.1-181278.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $0\cia2__data_o$next[63:0]$11186 attribute \src "libresoc.v:180997.3-180998.41" wire width 64 $0\cia2__data_o[63:0] attribute \src "libresoc.v:180930.7-180930.20" wire $0\initial[0:0] attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $0\msr2__data_o$next[63:0]$11196 attribute \src "libresoc.v:180995.3-180996.41" wire width 64 $0\msr2__data_o[63:0] attribute \src "libresoc.v:181245.3-181277.6" wire width 64 $0\reg$next[63:0]$11228 attribute \src "libresoc.v:180991.3-180992.25" wire width 64 $0\reg[63:0] attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $0\sv2__data_o$next[63:0]$11212 attribute \src "libresoc.v:180993.3-180994.39" wire width 64 $0\sv2__data_o[63:0] attribute \src "libresoc.v:181127.3-181162.6" wire $0\wr_detect$4[0:0]$11205 attribute \src "libresoc.v:181209.3-181244.6" wire $0\wr_detect$7[0:0]$11221 attribute \src "libresoc.v:181045.3-181080.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $1\cia2__data_o$next[63:0]$11187 attribute \src "libresoc.v:180939.14-180939.49" wire width 64 $1\cia2__data_o[63:0] attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $1\msr2__data_o$next[63:0]$11197 attribute \src "libresoc.v:180956.14-180956.49" wire width 64 $1\msr2__data_o[63:0] attribute \src "libresoc.v:181245.3-181277.6" wire width 64 $1\reg$next[63:0]$11229 attribute \src "libresoc.v:180968.14-180968.42" wire width 64 $1\reg[63:0] attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $1\sv2__data_o$next[63:0]$11213 attribute \src "libresoc.v:180975.14-180975.48" wire width 64 $1\sv2__data_o[63:0] attribute \src "libresoc.v:181127.3-181162.6" wire $1\wr_detect$4[0:0]$11206 attribute \src "libresoc.v:181209.3-181244.6" wire $1\wr_detect$7[0:0]$11222 attribute \src "libresoc.v:181045.3-181080.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $2\cia2__data_o$next[63:0]$11188 attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $2\msr2__data_o$next[63:0]$11198 attribute \src "libresoc.v:181245.3-181277.6" wire width 64 $2\reg$next[63:0]$11230 attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $2\sv2__data_o$next[63:0]$11214 attribute \src "libresoc.v:181127.3-181162.6" wire $2\wr_detect$4[0:0]$11207 attribute \src "libresoc.v:181209.3-181244.6" wire $2\wr_detect$7[0:0]$11223 attribute \src "libresoc.v:181045.3-181080.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $3\cia2__data_o$next[63:0]$11189 attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $3\msr2__data_o$next[63:0]$11199 attribute \src "libresoc.v:181245.3-181277.6" wire width 64 $3\reg$next[63:0]$11231 attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $3\sv2__data_o$next[63:0]$11215 attribute \src "libresoc.v:181127.3-181162.6" wire $3\wr_detect$4[0:0]$11208 attribute \src "libresoc.v:181209.3-181244.6" wire $3\wr_detect$7[0:0]$11224 attribute \src "libresoc.v:181045.3-181080.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $4\cia2__data_o$next[63:0]$11190 attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $4\msr2__data_o$next[63:0]$11200 attribute \src "libresoc.v:181245.3-181277.6" wire width 64 $4\reg$next[63:0]$11232 attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $4\sv2__data_o$next[63:0]$11216 attribute \src "libresoc.v:181127.3-181162.6" wire $4\wr_detect$4[0:0]$11209 attribute \src "libresoc.v:181209.3-181244.6" wire $4\wr_detect$7[0:0]$11225 attribute \src "libresoc.v:181045.3-181080.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $5\cia2__data_o$next[63:0]$11191 attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $5\msr2__data_o$next[63:0]$11201 attribute \src "libresoc.v:181245.3-181277.6" wire width 64 $5\reg$next[63:0]$11233 attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $5\sv2__data_o$next[63:0]$11217 attribute \src "libresoc.v:181127.3-181162.6" wire $5\wr_detect$4[0:0]$11210 attribute \src "libresoc.v:181209.3-181244.6" wire $5\wr_detect$7[0:0]$11226 attribute \src "libresoc.v:181045.3-181080.6" wire $5\wr_detect[0:0] attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $6\cia2__data_o$next[63:0]$11192 attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $6\msr2__data_o$next[63:0]$11202 attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $6\sv2__data_o$next[63:0]$11218 attribute \src "libresoc.v:180999.3-181044.6" wire width 64 $7\cia2__data_o$next[63:0]$11193 attribute \src "libresoc.v:181081.3-181126.6" wire width 64 $7\msr2__data_o$next[63:0]$11203 attribute \src "libresoc.v:181163.3-181208.6" wire width 64 $7\sv2__data_o$next[63:0]$11219 attribute \src "libresoc.v:180988.17-180988.100" wire $not$libresoc.v:180988$11178_Y attribute \src "libresoc.v:180989.17-180989.103" wire $not$libresoc.v:180989$11179_Y attribute \src "libresoc.v:180990.17-180990.103" wire $not$libresoc.v:180990$11180_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 3 \cia2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen attribute \src "libresoc.v:180930.7-180930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \msr2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \msr2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \msr2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \msr2__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 9 \nia2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \nia2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 64 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 13 \sv2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 7 \sv2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \sv2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \sv2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \sv2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180988$11178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:180988$11178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180989$11179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:180989$11179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:180990$11180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:180990$11180_Y end attribute \src "libresoc.v:180930.7-180930.20" process $proc$libresoc.v:180930$11234 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:180939.14-180939.49" process $proc$libresoc.v:180939$11235 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end attribute \src "libresoc.v:180956.14-180956.49" process $proc$libresoc.v:180956$11236 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end attribute \src "libresoc.v:180968.14-180968.42" process $proc$libresoc.v:180968$11237 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end attribute \src "libresoc.v:180975.14-180975.48" process $proc$libresoc.v:180975$11238 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end attribute \src "libresoc.v:180991.3-180992.25" process $proc$libresoc.v:180991$11181 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end attribute \src "libresoc.v:180993.3-180994.39" process $proc$libresoc.v:180993$11182 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end attribute \src "libresoc.v:180995.3-180996.41" process $proc$libresoc.v:180995$11183 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end attribute \src "libresoc.v:180997.3-180998.41" process $proc$libresoc.v:180997$11184 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end attribute \src "libresoc.v:180999.3-181044.6" process $proc$libresoc.v:180999$11185 assign { } { } assign { } { } assign { } { } assign $0\cia2__data_o$next[63:0]$11186 $7\cia2__data_o$next[63:0]$11193 attribute \src "libresoc.v:181000.5-181000.29" switch \initial attribute \src "libresoc.v:181000.9-181000.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \cia2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\cia2__data_o$next[63:0]$11187 $6\cia2__data_o$next[63:0]$11192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cia2__data_o$next[63:0]$11188 \nia2__data_i case assign $2\cia2__data_o$next[63:0]$11188 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cia2__data_o$next[63:0]$11189 \msr2__data_i case assign $3\cia2__data_o$next[63:0]$11189 $2\cia2__data_o$next[63:0]$11188 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\cia2__data_o$next[63:0]$11190 \sv2__data_i case assign $4\cia2__data_o$next[63:0]$11190 $3\cia2__data_o$next[63:0]$11189 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\cia2__data_o$next[63:0]$11191 \d_wr12__data_i case assign $5\cia2__data_o$next[63:0]$11191 $4\cia2__data_o$next[63:0]$11190 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\cia2__data_o$next[63:0]$11192 \reg case assign $6\cia2__data_o$next[63:0]$11192 $5\cia2__data_o$next[63:0]$11191 end case assign $1\cia2__data_o$next[63:0]$11187 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\cia2__data_o$next[63:0]$11193 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\cia2__data_o$next[63:0]$11193 $1\cia2__data_o$next[63:0]$11187 end sync always update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11186 end attribute \src "libresoc.v:181045.3-181080.6" process $proc$libresoc.v:181045$11194 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:181046.5-181046.29" switch \initial attribute \src "libresoc.v:181046.9-181046.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \cia2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $5\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect[0:0] 1'1 case assign $5\wr_detect[0:0] $4\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:181081.3-181126.6" process $proc$libresoc.v:181081$11195 assign { } { } assign { } { } assign { } { } assign $0\msr2__data_o$next[63:0]$11196 $7\msr2__data_o$next[63:0]$11203 attribute \src "libresoc.v:181082.5-181082.29" switch \initial attribute \src "libresoc.v:181082.9-181082.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \msr2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\msr2__data_o$next[63:0]$11197 $6\msr2__data_o$next[63:0]$11202 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\msr2__data_o$next[63:0]$11198 \nia2__data_i case assign $2\msr2__data_o$next[63:0]$11198 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\msr2__data_o$next[63:0]$11199 \msr2__data_i case assign $3\msr2__data_o$next[63:0]$11199 $2\msr2__data_o$next[63:0]$11198 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\msr2__data_o$next[63:0]$11200 \sv2__data_i case assign $4\msr2__data_o$next[63:0]$11200 $3\msr2__data_o$next[63:0]$11199 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\msr2__data_o$next[63:0]$11201 \d_wr12__data_i case assign $5\msr2__data_o$next[63:0]$11201 $4\msr2__data_o$next[63:0]$11200 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\msr2__data_o$next[63:0]$11202 \reg case assign $6\msr2__data_o$next[63:0]$11202 $5\msr2__data_o$next[63:0]$11201 end case assign $1\msr2__data_o$next[63:0]$11197 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\msr2__data_o$next[63:0]$11203 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\msr2__data_o$next[63:0]$11203 $1\msr2__data_o$next[63:0]$11197 end sync always update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11196 end attribute \src "libresoc.v:181127.3-181162.6" process $proc$libresoc.v:181127$11204 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11205 $1\wr_detect$4[0:0]$11206 attribute \src "libresoc.v:181128.5-181128.29" switch \initial attribute \src "libresoc.v:181128.9-181128.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \msr2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11206 $5\wr_detect$4[0:0]$11210 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11207 1'1 case assign $2\wr_detect$4[0:0]$11207 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11208 1'1 case assign $3\wr_detect$4[0:0]$11208 $2\wr_detect$4[0:0]$11207 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11209 1'1 case assign $4\wr_detect$4[0:0]$11209 $3\wr_detect$4[0:0]$11208 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$4[0:0]$11210 1'1 case assign $5\wr_detect$4[0:0]$11210 $4\wr_detect$4[0:0]$11209 end case assign $1\wr_detect$4[0:0]$11206 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11205 end attribute \src "libresoc.v:181163.3-181208.6" process $proc$libresoc.v:181163$11211 assign { } { } assign { } { } assign { } { } assign $0\sv2__data_o$next[63:0]$11212 $7\sv2__data_o$next[63:0]$11219 attribute \src "libresoc.v:181164.5-181164.29" switch \initial attribute \src "libresoc.v:181164.9-181164.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \sv2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\sv2__data_o$next[63:0]$11213 $6\sv2__data_o$next[63:0]$11218 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\sv2__data_o$next[63:0]$11214 \nia2__data_i case assign $2\sv2__data_o$next[63:0]$11214 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\sv2__data_o$next[63:0]$11215 \msr2__data_i case assign $3\sv2__data_o$next[63:0]$11215 $2\sv2__data_o$next[63:0]$11214 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\sv2__data_o$next[63:0]$11216 \sv2__data_i case assign $4\sv2__data_o$next[63:0]$11216 $3\sv2__data_o$next[63:0]$11215 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\sv2__data_o$next[63:0]$11217 \d_wr12__data_i case assign $5\sv2__data_o$next[63:0]$11217 $4\sv2__data_o$next[63:0]$11216 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\sv2__data_o$next[63:0]$11218 \reg case assign $6\sv2__data_o$next[63:0]$11218 $5\sv2__data_o$next[63:0]$11217 end case assign $1\sv2__data_o$next[63:0]$11213 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\sv2__data_o$next[63:0]$11219 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $7\sv2__data_o$next[63:0]$11219 $1\sv2__data_o$next[63:0]$11213 end sync always update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11212 end attribute \src "libresoc.v:181209.3-181244.6" process $proc$libresoc.v:181209$11220 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11221 $1\wr_detect$7[0:0]$11222 attribute \src "libresoc.v:181210.5-181210.29" switch \initial attribute \src "libresoc.v:181210.9-181210.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \sv2__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11222 $5\wr_detect$7[0:0]$11226 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11223 1'1 case assign $2\wr_detect$7[0:0]$11223 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11224 1'1 case assign $3\wr_detect$7[0:0]$11224 $2\wr_detect$7[0:0]$11223 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11225 1'1 case assign $4\wr_detect$7[0:0]$11225 $3\wr_detect$7[0:0]$11224 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\wr_detect$7[0:0]$11226 1'1 case assign $5\wr_detect$7[0:0]$11226 $4\wr_detect$7[0:0]$11225 end case assign $1\wr_detect$7[0:0]$11222 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11221 end attribute \src "libresoc.v:181245.3-181277.6" process $proc$libresoc.v:181245$11227 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[63:0]$11228 $5\reg$next[63:0]$11233 attribute \src "libresoc.v:181246.5-181246.29" switch \initial attribute \src "libresoc.v:181246.9-181246.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[63:0]$11229 \nia2__data_i case assign $1\reg$next[63:0]$11229 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[63:0]$11230 \msr2__data_i case assign $2\reg$next[63:0]$11230 $1\reg$next[63:0]$11229 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[63:0]$11231 \sv2__data_i case assign $3\reg$next[63:0]$11231 $2\reg$next[63:0]$11230 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[63:0]$11232 \d_wr12__data_i case assign $4\reg$next[63:0]$11232 $3\reg$next[63:0]$11231 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\reg$next[63:0]$11233 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $5\reg$next[63:0]$11233 $4\reg$next[63:0]$11232 end sync always update \reg$next $0\reg$next[63:0]$11228 end connect \$1 $not$libresoc.v:180988$11178_Y connect \$3 $not$libresoc.v:180989$11179_Y connect \$6 $not$libresoc.v:180990$11180_Y end attribute \src "libresoc.v:181282.1-181753.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 attribute \src "libresoc.v:181283.7-181283.20" wire $0\initial[0:0] attribute \src "libresoc.v:181683.3-181722.6" wire width 4 $0\r23__data_o$next[3:0]$11308 attribute \src "libresoc.v:181366.3-181367.39" wire width 4 $0\r23__data_o[3:0] attribute \src "libresoc.v:181613.3-181652.6" wire width 4 $0\r3__data_o$next[3:0]$11294 attribute \src "libresoc.v:181368.3-181369.37" wire width 4 $0\r3__data_o[3:0] attribute \src "libresoc.v:181446.3-181472.6" wire width 4 $0\reg$next[3:0]$11260 attribute \src "libresoc.v:181364.3-181365.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:181376.3-181415.6" wire width 4 $0\src13__data_o$next[3:0]$11251 attribute \src "libresoc.v:181374.3-181375.43" wire width 4 $0\src13__data_o[3:0] attribute \src "libresoc.v:181473.3-181512.6" wire width 4 $0\src23__data_o$next[3:0]$11266 attribute \src "libresoc.v:181372.3-181373.43" wire width 4 $0\src23__data_o[3:0] attribute \src "libresoc.v:181543.3-181582.6" wire width 4 $0\src33__data_o$next[3:0]$11280 attribute \src "libresoc.v:181370.3-181371.43" wire width 4 $0\src33__data_o[3:0] attribute \src "libresoc.v:181653.3-181682.6" wire $0\wr_detect$10[0:0]$11302 attribute \src "libresoc.v:181723.3-181752.6" wire $0\wr_detect$13[0:0]$11316 attribute \src "libresoc.v:181513.3-181542.6" wire $0\wr_detect$4[0:0]$11274 attribute \src "libresoc.v:181583.3-181612.6" wire $0\wr_detect$7[0:0]$11288 attribute \src "libresoc.v:181416.3-181445.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:181683.3-181722.6" wire width 4 $1\r23__data_o$next[3:0]$11309 attribute \src "libresoc.v:181308.13-181308.31" wire width 4 $1\r23__data_o[3:0] attribute \src "libresoc.v:181613.3-181652.6" wire width 4 $1\r3__data_o$next[3:0]$11295 attribute \src "libresoc.v:181315.13-181315.30" wire width 4 $1\r3__data_o[3:0] attribute \src "libresoc.v:181446.3-181472.6" wire width 4 $1\reg$next[3:0]$11261 attribute \src "libresoc.v:181321.13-181321.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:181376.3-181415.6" wire width 4 $1\src13__data_o$next[3:0]$11252 attribute \src "libresoc.v:181326.13-181326.33" wire width 4 $1\src13__data_o[3:0] attribute \src "libresoc.v:181473.3-181512.6" wire width 4 $1\src23__data_o$next[3:0]$11267 attribute \src "libresoc.v:181333.13-181333.33" wire width 4 $1\src23__data_o[3:0] attribute \src "libresoc.v:181543.3-181582.6" wire width 4 $1\src33__data_o$next[3:0]$11281 attribute \src "libresoc.v:181340.13-181340.33" wire width 4 $1\src33__data_o[3:0] attribute \src "libresoc.v:181653.3-181682.6" wire $1\wr_detect$10[0:0]$11303 attribute \src "libresoc.v:181723.3-181752.6" wire $1\wr_detect$13[0:0]$11317 attribute \src "libresoc.v:181513.3-181542.6" wire $1\wr_detect$4[0:0]$11275 attribute \src "libresoc.v:181583.3-181612.6" wire $1\wr_detect$7[0:0]$11289 attribute \src "libresoc.v:181416.3-181445.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:181683.3-181722.6" wire width 4 $2\r23__data_o$next[3:0]$11310 attribute \src "libresoc.v:181613.3-181652.6" wire width 4 $2\r3__data_o$next[3:0]$11296 attribute \src "libresoc.v:181446.3-181472.6" wire width 4 $2\reg$next[3:0]$11262 attribute \src "libresoc.v:181376.3-181415.6" wire width 4 $2\src13__data_o$next[3:0]$11253 attribute \src "libresoc.v:181473.3-181512.6" wire width 4 $2\src23__data_o$next[3:0]$11268 attribute \src "libresoc.v:181543.3-181582.6" wire width 4 $2\src33__data_o$next[3:0]$11282 attribute \src "libresoc.v:181653.3-181682.6" wire $2\wr_detect$10[0:0]$11304 attribute \src "libresoc.v:181723.3-181752.6" wire $2\wr_detect$13[0:0]$11318 attribute \src "libresoc.v:181513.3-181542.6" wire $2\wr_detect$4[0:0]$11276 attribute \src "libresoc.v:181583.3-181612.6" wire $2\wr_detect$7[0:0]$11290 attribute \src "libresoc.v:181416.3-181445.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:181683.3-181722.6" wire width 4 $3\r23__data_o$next[3:0]$11311 attribute \src "libresoc.v:181613.3-181652.6" wire width 4 $3\r3__data_o$next[3:0]$11297 attribute \src "libresoc.v:181446.3-181472.6" wire width 4 $3\reg$next[3:0]$11263 attribute \src "libresoc.v:181376.3-181415.6" wire width 4 $3\src13__data_o$next[3:0]$11254 attribute \src "libresoc.v:181473.3-181512.6" wire width 4 $3\src23__data_o$next[3:0]$11269 attribute \src "libresoc.v:181543.3-181582.6" wire width 4 $3\src33__data_o$next[3:0]$11283 attribute \src "libresoc.v:181653.3-181682.6" wire $3\wr_detect$10[0:0]$11305 attribute \src "libresoc.v:181723.3-181752.6" wire $3\wr_detect$13[0:0]$11319 attribute \src "libresoc.v:181513.3-181542.6" wire $3\wr_detect$4[0:0]$11277 attribute \src "libresoc.v:181583.3-181612.6" wire $3\wr_detect$7[0:0]$11291 attribute \src "libresoc.v:181416.3-181445.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:181683.3-181722.6" wire width 4 $4\r23__data_o$next[3:0]$11312 attribute \src "libresoc.v:181613.3-181652.6" wire width 4 $4\r3__data_o$next[3:0]$11298 attribute \src "libresoc.v:181446.3-181472.6" wire width 4 $4\reg$next[3:0]$11264 attribute \src "libresoc.v:181376.3-181415.6" wire width 4 $4\src13__data_o$next[3:0]$11255 attribute \src "libresoc.v:181473.3-181512.6" wire width 4 $4\src23__data_o$next[3:0]$11270 attribute \src "libresoc.v:181543.3-181582.6" wire width 4 $4\src33__data_o$next[3:0]$11284 attribute \src "libresoc.v:181653.3-181682.6" wire $4\wr_detect$10[0:0]$11306 attribute \src "libresoc.v:181723.3-181752.6" wire $4\wr_detect$13[0:0]$11320 attribute \src "libresoc.v:181513.3-181542.6" wire $4\wr_detect$4[0:0]$11278 attribute \src "libresoc.v:181583.3-181612.6" wire $4\wr_detect$7[0:0]$11292 attribute \src "libresoc.v:181416.3-181445.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:181683.3-181722.6" wire width 4 $5\r23__data_o$next[3:0]$11313 attribute \src "libresoc.v:181613.3-181652.6" wire width 4 $5\r3__data_o$next[3:0]$11299 attribute \src "libresoc.v:181376.3-181415.6" wire width 4 $5\src13__data_o$next[3:0]$11256 attribute \src "libresoc.v:181473.3-181512.6" wire width 4 $5\src23__data_o$next[3:0]$11271 attribute \src "libresoc.v:181543.3-181582.6" wire width 4 $5\src33__data_o$next[3:0]$11285 attribute \src "libresoc.v:181683.3-181722.6" wire width 4 $6\r23__data_o$next[3:0]$11314 attribute \src "libresoc.v:181613.3-181652.6" wire width 4 $6\r3__data_o$next[3:0]$11300 attribute \src "libresoc.v:181376.3-181415.6" wire width 4 $6\src13__data_o$next[3:0]$11257 attribute \src "libresoc.v:181473.3-181512.6" wire width 4 $6\src23__data_o$next[3:0]$11272 attribute \src "libresoc.v:181543.3-181582.6" wire width 4 $6\src33__data_o$next[3:0]$11286 attribute \src "libresoc.v:181359.17-181359.104" wire $not$libresoc.v:181359$11239_Y attribute \src "libresoc.v:181360.18-181360.105" wire $not$libresoc.v:181360$11240_Y attribute \src "libresoc.v:181361.17-181361.100" wire $not$libresoc.v:181361$11241_Y attribute \src "libresoc.v:181362.17-181362.103" wire $not$libresoc.v:181362$11242_Y attribute \src "libresoc.v:181363.17-181363.103" wire $not$libresoc.v:181363$11243_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest23__wen attribute \src "libresoc.v:181283.7-181283.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r3__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r3__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src13__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src13__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src13__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src23__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src23__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src23__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src33__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src33__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src33__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w3__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181359$11239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:181359$11239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181360$11240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:181360$11240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181361$11241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:181361$11241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181362$11242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:181362$11242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181363$11243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:181363$11243_Y end attribute \src "libresoc.v:181283.7-181283.20" process $proc$libresoc.v:181283$11321 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:181308.13-181308.31" process $proc$libresoc.v:181308$11322 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end attribute \src "libresoc.v:181315.13-181315.30" process $proc$libresoc.v:181315$11323 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end attribute \src "libresoc.v:181321.13-181321.25" process $proc$libresoc.v:181321$11324 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:181326.13-181326.33" process $proc$libresoc.v:181326$11325 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end attribute \src "libresoc.v:181333.13-181333.33" process $proc$libresoc.v:181333$11326 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end attribute \src "libresoc.v:181340.13-181340.33" process $proc$libresoc.v:181340$11327 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end attribute \src "libresoc.v:181364.3-181365.25" process $proc$libresoc.v:181364$11244 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:181366.3-181367.39" process $proc$libresoc.v:181366$11245 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end attribute \src "libresoc.v:181368.3-181369.37" process $proc$libresoc.v:181368$11246 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end attribute \src "libresoc.v:181370.3-181371.43" process $proc$libresoc.v:181370$11247 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end attribute \src "libresoc.v:181372.3-181373.43" process $proc$libresoc.v:181372$11248 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end attribute \src "libresoc.v:181374.3-181375.43" process $proc$libresoc.v:181374$11249 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end attribute \src "libresoc.v:181376.3-181415.6" process $proc$libresoc.v:181376$11250 assign { } { } assign { } { } assign { } { } assign $0\src13__data_o$next[3:0]$11251 $6\src13__data_o$next[3:0]$11257 attribute \src "libresoc.v:181377.5-181377.29" switch \initial attribute \src "libresoc.v:181377.9-181377.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src13__data_o$next[3:0]$11252 $5\src13__data_o$next[3:0]$11256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src13__data_o$next[3:0]$11253 \dest13__data_i case assign $2\src13__data_o$next[3:0]$11253 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src13__data_o$next[3:0]$11254 \dest23__data_i case assign $3\src13__data_o$next[3:0]$11254 $2\src13__data_o$next[3:0]$11253 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src13__data_o$next[3:0]$11255 \w3__data_i case assign $4\src13__data_o$next[3:0]$11255 $3\src13__data_o$next[3:0]$11254 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src13__data_o$next[3:0]$11256 \reg case assign $5\src13__data_o$next[3:0]$11256 $4\src13__data_o$next[3:0]$11255 end case assign $1\src13__data_o$next[3:0]$11252 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src13__data_o$next[3:0]$11257 4'0000 case assign $6\src13__data_o$next[3:0]$11257 $1\src13__data_o$next[3:0]$11252 end sync always update \src13__data_o$next $0\src13__data_o$next[3:0]$11251 end attribute \src "libresoc.v:181416.3-181445.6" process $proc$libresoc.v:181416$11258 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:181417.5-181417.29" switch \initial attribute \src "libresoc.v:181417.9-181417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src13__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:181446.3-181472.6" process $proc$libresoc.v:181446$11259 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11260 $4\reg$next[3:0]$11264 attribute \src "libresoc.v:181447.5-181447.29" switch \initial attribute \src "libresoc.v:181447.9-181447.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$11261 \dest13__data_i case assign $1\reg$next[3:0]$11261 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$11262 \dest23__data_i case assign $2\reg$next[3:0]$11262 $1\reg$next[3:0]$11261 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$11263 \w3__data_i case assign $3\reg$next[3:0]$11263 $2\reg$next[3:0]$11262 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$11264 4'0000 case assign $4\reg$next[3:0]$11264 $3\reg$next[3:0]$11263 end sync always update \reg$next $0\reg$next[3:0]$11260 end attribute \src "libresoc.v:181473.3-181512.6" process $proc$libresoc.v:181473$11265 assign { } { } assign { } { } assign { } { } assign $0\src23__data_o$next[3:0]$11266 $6\src23__data_o$next[3:0]$11272 attribute \src "libresoc.v:181474.5-181474.29" switch \initial attribute \src "libresoc.v:181474.9-181474.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src23__data_o$next[3:0]$11267 $5\src23__data_o$next[3:0]$11271 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src23__data_o$next[3:0]$11268 \dest13__data_i case assign $2\src23__data_o$next[3:0]$11268 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src23__data_o$next[3:0]$11269 \dest23__data_i case assign $3\src23__data_o$next[3:0]$11269 $2\src23__data_o$next[3:0]$11268 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src23__data_o$next[3:0]$11270 \w3__data_i case assign $4\src23__data_o$next[3:0]$11270 $3\src23__data_o$next[3:0]$11269 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src23__data_o$next[3:0]$11271 \reg case assign $5\src23__data_o$next[3:0]$11271 $4\src23__data_o$next[3:0]$11270 end case assign $1\src23__data_o$next[3:0]$11267 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src23__data_o$next[3:0]$11272 4'0000 case assign $6\src23__data_o$next[3:0]$11272 $1\src23__data_o$next[3:0]$11267 end sync always update \src23__data_o$next $0\src23__data_o$next[3:0]$11266 end attribute \src "libresoc.v:181513.3-181542.6" process $proc$libresoc.v:181513$11273 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11274 $1\wr_detect$4[0:0]$11275 attribute \src "libresoc.v:181514.5-181514.29" switch \initial attribute \src "libresoc.v:181514.9-181514.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11275 $4\wr_detect$4[0:0]$11278 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11276 1'1 case assign $2\wr_detect$4[0:0]$11276 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11277 1'1 case assign $3\wr_detect$4[0:0]$11277 $2\wr_detect$4[0:0]$11276 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11278 1'1 case assign $4\wr_detect$4[0:0]$11278 $3\wr_detect$4[0:0]$11277 end case assign $1\wr_detect$4[0:0]$11275 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11274 end attribute \src "libresoc.v:181543.3-181582.6" process $proc$libresoc.v:181543$11279 assign { } { } assign { } { } assign { } { } assign $0\src33__data_o$next[3:0]$11280 $6\src33__data_o$next[3:0]$11286 attribute \src "libresoc.v:181544.5-181544.29" switch \initial attribute \src "libresoc.v:181544.9-181544.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src33__data_o$next[3:0]$11281 $5\src33__data_o$next[3:0]$11285 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src33__data_o$next[3:0]$11282 \dest13__data_i case assign $2\src33__data_o$next[3:0]$11282 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src33__data_o$next[3:0]$11283 \dest23__data_i case assign $3\src33__data_o$next[3:0]$11283 $2\src33__data_o$next[3:0]$11282 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src33__data_o$next[3:0]$11284 \w3__data_i case assign $4\src33__data_o$next[3:0]$11284 $3\src33__data_o$next[3:0]$11283 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src33__data_o$next[3:0]$11285 \reg case assign $5\src33__data_o$next[3:0]$11285 $4\src33__data_o$next[3:0]$11284 end case assign $1\src33__data_o$next[3:0]$11281 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src33__data_o$next[3:0]$11286 4'0000 case assign $6\src33__data_o$next[3:0]$11286 $1\src33__data_o$next[3:0]$11281 end sync always update \src33__data_o$next $0\src33__data_o$next[3:0]$11280 end attribute \src "libresoc.v:181583.3-181612.6" process $proc$libresoc.v:181583$11287 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11288 $1\wr_detect$7[0:0]$11289 attribute \src "libresoc.v:181584.5-181584.29" switch \initial attribute \src "libresoc.v:181584.9-181584.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src33__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11289 $4\wr_detect$7[0:0]$11292 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11290 1'1 case assign $2\wr_detect$7[0:0]$11290 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11291 1'1 case assign $3\wr_detect$7[0:0]$11291 $2\wr_detect$7[0:0]$11290 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11292 1'1 case assign $4\wr_detect$7[0:0]$11292 $3\wr_detect$7[0:0]$11291 end case assign $1\wr_detect$7[0:0]$11289 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11288 end attribute \src "libresoc.v:181613.3-181652.6" process $proc$libresoc.v:181613$11293 assign { } { } assign { } { } assign { } { } assign $0\r3__data_o$next[3:0]$11294 $6\r3__data_o$next[3:0]$11300 attribute \src "libresoc.v:181614.5-181614.29" switch \initial attribute \src "libresoc.v:181614.9-181614.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r3__data_o$next[3:0]$11295 $5\r3__data_o$next[3:0]$11299 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r3__data_o$next[3:0]$11296 \dest13__data_i case assign $2\r3__data_o$next[3:0]$11296 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r3__data_o$next[3:0]$11297 \dest23__data_i case assign $3\r3__data_o$next[3:0]$11297 $2\r3__data_o$next[3:0]$11296 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r3__data_o$next[3:0]$11298 \w3__data_i case assign $4\r3__data_o$next[3:0]$11298 $3\r3__data_o$next[3:0]$11297 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r3__data_o$next[3:0]$11299 \reg case assign $5\r3__data_o$next[3:0]$11299 $4\r3__data_o$next[3:0]$11298 end case assign $1\r3__data_o$next[3:0]$11295 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r3__data_o$next[3:0]$11300 4'0000 case assign $6\r3__data_o$next[3:0]$11300 $1\r3__data_o$next[3:0]$11295 end sync always update \r3__data_o$next $0\r3__data_o$next[3:0]$11294 end attribute \src "libresoc.v:181653.3-181682.6" process $proc$libresoc.v:181653$11301 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11302 $1\wr_detect$10[0:0]$11303 attribute \src "libresoc.v:181654.5-181654.29" switch \initial attribute \src "libresoc.v:181654.9-181654.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r3__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$11303 $4\wr_detect$10[0:0]$11306 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$11304 1'1 case assign $2\wr_detect$10[0:0]$11304 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$11305 1'1 case assign $3\wr_detect$10[0:0]$11305 $2\wr_detect$10[0:0]$11304 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$11306 1'1 case assign $4\wr_detect$10[0:0]$11306 $3\wr_detect$10[0:0]$11305 end case assign $1\wr_detect$10[0:0]$11303 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11302 end attribute \src "libresoc.v:181683.3-181722.6" process $proc$libresoc.v:181683$11307 assign { } { } assign { } { } assign { } { } assign $0\r23__data_o$next[3:0]$11308 $6\r23__data_o$next[3:0]$11314 attribute \src "libresoc.v:181684.5-181684.29" switch \initial attribute \src "libresoc.v:181684.9-181684.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r23__data_o$next[3:0]$11309 $5\r23__data_o$next[3:0]$11313 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r23__data_o$next[3:0]$11310 \dest13__data_i case assign $2\r23__data_o$next[3:0]$11310 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r23__data_o$next[3:0]$11311 \dest23__data_i case assign $3\r23__data_o$next[3:0]$11311 $2\r23__data_o$next[3:0]$11310 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r23__data_o$next[3:0]$11312 \w3__data_i case assign $4\r23__data_o$next[3:0]$11312 $3\r23__data_o$next[3:0]$11311 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r23__data_o$next[3:0]$11313 \reg case assign $5\r23__data_o$next[3:0]$11313 $4\r23__data_o$next[3:0]$11312 end case assign $1\r23__data_o$next[3:0]$11309 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r23__data_o$next[3:0]$11314 4'0000 case assign $6\r23__data_o$next[3:0]$11314 $1\r23__data_o$next[3:0]$11309 end sync always update \r23__data_o$next $0\r23__data_o$next[3:0]$11308 end attribute \src "libresoc.v:181723.3-181752.6" process $proc$libresoc.v:181723$11315 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11316 $1\wr_detect$13[0:0]$11317 attribute \src "libresoc.v:181724.5-181724.29" switch \initial attribute \src "libresoc.v:181724.9-181724.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r23__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$11317 $4\wr_detect$13[0:0]$11320 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$11318 1'1 case assign $2\wr_detect$13[0:0]$11318 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$11319 1'1 case assign $3\wr_detect$13[0:0]$11319 $2\wr_detect$13[0:0]$11318 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$11320 1'1 case assign $4\wr_detect$13[0:0]$11320 $3\wr_detect$13[0:0]$11319 end case assign $1\wr_detect$13[0:0]$11317 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11316 end connect \$9 $not$libresoc.v:181359$11239_Y connect \$12 $not$libresoc.v:181360$11240_Y connect \$1 $not$libresoc.v:181361$11241_Y connect \$3 $not$libresoc.v:181362$11242_Y connect \$6 $not$libresoc.v:181363$11243_Y end attribute \src "libresoc.v:181757.1-182228.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 attribute \src "libresoc.v:181758.7-181758.20" wire $0\initial[0:0] attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $0\r24__data_o$next[3:0]$11397 attribute \src "libresoc.v:181841.3-181842.39" wire width 4 $0\r24__data_o[3:0] attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $0\r4__data_o$next[3:0]$11383 attribute \src "libresoc.v:181843.3-181844.37" wire width 4 $0\r4__data_o[3:0] attribute \src "libresoc.v:181921.3-181947.6" wire width 4 $0\reg$next[3:0]$11349 attribute \src "libresoc.v:181839.3-181840.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:181851.3-181890.6" wire width 4 $0\src14__data_o$next[3:0]$11340 attribute \src "libresoc.v:181849.3-181850.43" wire width 4 $0\src14__data_o[3:0] attribute \src "libresoc.v:181948.3-181987.6" wire width 4 $0\src24__data_o$next[3:0]$11355 attribute \src "libresoc.v:181847.3-181848.43" wire width 4 $0\src24__data_o[3:0] attribute \src "libresoc.v:182018.3-182057.6" wire width 4 $0\src34__data_o$next[3:0]$11369 attribute \src "libresoc.v:181845.3-181846.43" wire width 4 $0\src34__data_o[3:0] attribute \src "libresoc.v:182128.3-182157.6" wire $0\wr_detect$10[0:0]$11391 attribute \src "libresoc.v:182198.3-182227.6" wire $0\wr_detect$13[0:0]$11405 attribute \src "libresoc.v:181988.3-182017.6" wire $0\wr_detect$4[0:0]$11363 attribute \src "libresoc.v:182058.3-182087.6" wire $0\wr_detect$7[0:0]$11377 attribute \src "libresoc.v:181891.3-181920.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $1\r24__data_o$next[3:0]$11398 attribute \src "libresoc.v:181783.13-181783.31" wire width 4 $1\r24__data_o[3:0] attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $1\r4__data_o$next[3:0]$11384 attribute \src "libresoc.v:181790.13-181790.30" wire width 4 $1\r4__data_o[3:0] attribute \src "libresoc.v:181921.3-181947.6" wire width 4 $1\reg$next[3:0]$11350 attribute \src "libresoc.v:181796.13-181796.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:181851.3-181890.6" wire width 4 $1\src14__data_o$next[3:0]$11341 attribute \src "libresoc.v:181801.13-181801.33" wire width 4 $1\src14__data_o[3:0] attribute \src "libresoc.v:181948.3-181987.6" wire width 4 $1\src24__data_o$next[3:0]$11356 attribute \src "libresoc.v:181808.13-181808.33" wire width 4 $1\src24__data_o[3:0] attribute \src "libresoc.v:182018.3-182057.6" wire width 4 $1\src34__data_o$next[3:0]$11370 attribute \src "libresoc.v:181815.13-181815.33" wire width 4 $1\src34__data_o[3:0] attribute \src "libresoc.v:182128.3-182157.6" wire $1\wr_detect$10[0:0]$11392 attribute \src "libresoc.v:182198.3-182227.6" wire $1\wr_detect$13[0:0]$11406 attribute \src "libresoc.v:181988.3-182017.6" wire $1\wr_detect$4[0:0]$11364 attribute \src "libresoc.v:182058.3-182087.6" wire $1\wr_detect$7[0:0]$11378 attribute \src "libresoc.v:181891.3-181920.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $2\r24__data_o$next[3:0]$11399 attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $2\r4__data_o$next[3:0]$11385 attribute \src "libresoc.v:181921.3-181947.6" wire width 4 $2\reg$next[3:0]$11351 attribute \src "libresoc.v:181851.3-181890.6" wire width 4 $2\src14__data_o$next[3:0]$11342 attribute \src "libresoc.v:181948.3-181987.6" wire width 4 $2\src24__data_o$next[3:0]$11357 attribute \src "libresoc.v:182018.3-182057.6" wire width 4 $2\src34__data_o$next[3:0]$11371 attribute \src "libresoc.v:182128.3-182157.6" wire $2\wr_detect$10[0:0]$11393 attribute \src "libresoc.v:182198.3-182227.6" wire $2\wr_detect$13[0:0]$11407 attribute \src "libresoc.v:181988.3-182017.6" wire $2\wr_detect$4[0:0]$11365 attribute \src "libresoc.v:182058.3-182087.6" wire $2\wr_detect$7[0:0]$11379 attribute \src "libresoc.v:181891.3-181920.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $3\r24__data_o$next[3:0]$11400 attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $3\r4__data_o$next[3:0]$11386 attribute \src "libresoc.v:181921.3-181947.6" wire width 4 $3\reg$next[3:0]$11352 attribute \src "libresoc.v:181851.3-181890.6" wire width 4 $3\src14__data_o$next[3:0]$11343 attribute \src "libresoc.v:181948.3-181987.6" wire width 4 $3\src24__data_o$next[3:0]$11358 attribute \src "libresoc.v:182018.3-182057.6" wire width 4 $3\src34__data_o$next[3:0]$11372 attribute \src "libresoc.v:182128.3-182157.6" wire $3\wr_detect$10[0:0]$11394 attribute \src "libresoc.v:182198.3-182227.6" wire $3\wr_detect$13[0:0]$11408 attribute \src "libresoc.v:181988.3-182017.6" wire $3\wr_detect$4[0:0]$11366 attribute \src "libresoc.v:182058.3-182087.6" wire $3\wr_detect$7[0:0]$11380 attribute \src "libresoc.v:181891.3-181920.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $4\r24__data_o$next[3:0]$11401 attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $4\r4__data_o$next[3:0]$11387 attribute \src "libresoc.v:181921.3-181947.6" wire width 4 $4\reg$next[3:0]$11353 attribute \src "libresoc.v:181851.3-181890.6" wire width 4 $4\src14__data_o$next[3:0]$11344 attribute \src "libresoc.v:181948.3-181987.6" wire width 4 $4\src24__data_o$next[3:0]$11359 attribute \src "libresoc.v:182018.3-182057.6" wire width 4 $4\src34__data_o$next[3:0]$11373 attribute \src "libresoc.v:182128.3-182157.6" wire $4\wr_detect$10[0:0]$11395 attribute \src "libresoc.v:182198.3-182227.6" wire $4\wr_detect$13[0:0]$11409 attribute \src "libresoc.v:181988.3-182017.6" wire $4\wr_detect$4[0:0]$11367 attribute \src "libresoc.v:182058.3-182087.6" wire $4\wr_detect$7[0:0]$11381 attribute \src "libresoc.v:181891.3-181920.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $5\r24__data_o$next[3:0]$11402 attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $5\r4__data_o$next[3:0]$11388 attribute \src "libresoc.v:181851.3-181890.6" wire width 4 $5\src14__data_o$next[3:0]$11345 attribute \src "libresoc.v:181948.3-181987.6" wire width 4 $5\src24__data_o$next[3:0]$11360 attribute \src "libresoc.v:182018.3-182057.6" wire width 4 $5\src34__data_o$next[3:0]$11374 attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $6\r24__data_o$next[3:0]$11403 attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $6\r4__data_o$next[3:0]$11389 attribute \src "libresoc.v:181851.3-181890.6" wire width 4 $6\src14__data_o$next[3:0]$11346 attribute \src "libresoc.v:181948.3-181987.6" wire width 4 $6\src24__data_o$next[3:0]$11361 attribute \src "libresoc.v:182018.3-182057.6" wire width 4 $6\src34__data_o$next[3:0]$11375 attribute \src "libresoc.v:181834.17-181834.104" wire $not$libresoc.v:181834$11328_Y attribute \src "libresoc.v:181835.18-181835.105" wire $not$libresoc.v:181835$11329_Y attribute \src "libresoc.v:181836.17-181836.100" wire $not$libresoc.v:181836$11330_Y attribute \src "libresoc.v:181837.17-181837.103" wire $not$libresoc.v:181837$11331_Y attribute \src "libresoc.v:181838.17-181838.103" wire $not$libresoc.v:181838$11332_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest14__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest24__wen attribute \src "libresoc.v:181758.7-181758.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r4__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r4__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r4__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src14__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src14__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src14__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src24__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src24__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src24__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src34__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src34__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src34__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w4__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181834$11328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:181834$11328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181835$11329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:181835$11329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181836$11330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:181836$11330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181837$11331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:181837$11331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:181838$11332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:181838$11332_Y end attribute \src "libresoc.v:181758.7-181758.20" process $proc$libresoc.v:181758$11410 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:181783.13-181783.31" process $proc$libresoc.v:181783$11411 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end attribute \src "libresoc.v:181790.13-181790.30" process $proc$libresoc.v:181790$11412 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end attribute \src "libresoc.v:181796.13-181796.25" process $proc$libresoc.v:181796$11413 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:181801.13-181801.33" process $proc$libresoc.v:181801$11414 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end attribute \src "libresoc.v:181808.13-181808.33" process $proc$libresoc.v:181808$11415 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end attribute \src "libresoc.v:181815.13-181815.33" process $proc$libresoc.v:181815$11416 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end attribute \src "libresoc.v:181839.3-181840.25" process $proc$libresoc.v:181839$11333 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:181841.3-181842.39" process $proc$libresoc.v:181841$11334 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end attribute \src "libresoc.v:181843.3-181844.37" process $proc$libresoc.v:181843$11335 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end attribute \src "libresoc.v:181845.3-181846.43" process $proc$libresoc.v:181845$11336 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end attribute \src "libresoc.v:181847.3-181848.43" process $proc$libresoc.v:181847$11337 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end attribute \src "libresoc.v:181849.3-181850.43" process $proc$libresoc.v:181849$11338 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end attribute \src "libresoc.v:181851.3-181890.6" process $proc$libresoc.v:181851$11339 assign { } { } assign { } { } assign { } { } assign $0\src14__data_o$next[3:0]$11340 $6\src14__data_o$next[3:0]$11346 attribute \src "libresoc.v:181852.5-181852.29" switch \initial attribute \src "libresoc.v:181852.9-181852.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src14__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src14__data_o$next[3:0]$11341 $5\src14__data_o$next[3:0]$11345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src14__data_o$next[3:0]$11342 \dest14__data_i case assign $2\src14__data_o$next[3:0]$11342 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src14__data_o$next[3:0]$11343 \dest24__data_i case assign $3\src14__data_o$next[3:0]$11343 $2\src14__data_o$next[3:0]$11342 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src14__data_o$next[3:0]$11344 \w4__data_i case assign $4\src14__data_o$next[3:0]$11344 $3\src14__data_o$next[3:0]$11343 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src14__data_o$next[3:0]$11345 \reg case assign $5\src14__data_o$next[3:0]$11345 $4\src14__data_o$next[3:0]$11344 end case assign $1\src14__data_o$next[3:0]$11341 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src14__data_o$next[3:0]$11346 4'0000 case assign $6\src14__data_o$next[3:0]$11346 $1\src14__data_o$next[3:0]$11341 end sync always update \src14__data_o$next $0\src14__data_o$next[3:0]$11340 end attribute \src "libresoc.v:181891.3-181920.6" process $proc$libresoc.v:181891$11347 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:181892.5-181892.29" switch \initial attribute \src "libresoc.v:181892.9-181892.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src14__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:181921.3-181947.6" process $proc$libresoc.v:181921$11348 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11349 $4\reg$next[3:0]$11353 attribute \src "libresoc.v:181922.5-181922.29" switch \initial attribute \src "libresoc.v:181922.9-181922.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$11350 \dest14__data_i case assign $1\reg$next[3:0]$11350 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$11351 \dest24__data_i case assign $2\reg$next[3:0]$11351 $1\reg$next[3:0]$11350 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$11352 \w4__data_i case assign $3\reg$next[3:0]$11352 $2\reg$next[3:0]$11351 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$11353 4'0000 case assign $4\reg$next[3:0]$11353 $3\reg$next[3:0]$11352 end sync always update \reg$next $0\reg$next[3:0]$11349 end attribute \src "libresoc.v:181948.3-181987.6" process $proc$libresoc.v:181948$11354 assign { } { } assign { } { } assign { } { } assign $0\src24__data_o$next[3:0]$11355 $6\src24__data_o$next[3:0]$11361 attribute \src "libresoc.v:181949.5-181949.29" switch \initial attribute \src "libresoc.v:181949.9-181949.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src24__data_o$next[3:0]$11356 $5\src24__data_o$next[3:0]$11360 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src24__data_o$next[3:0]$11357 \dest14__data_i case assign $2\src24__data_o$next[3:0]$11357 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src24__data_o$next[3:0]$11358 \dest24__data_i case assign $3\src24__data_o$next[3:0]$11358 $2\src24__data_o$next[3:0]$11357 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src24__data_o$next[3:0]$11359 \w4__data_i case assign $4\src24__data_o$next[3:0]$11359 $3\src24__data_o$next[3:0]$11358 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src24__data_o$next[3:0]$11360 \reg case assign $5\src24__data_o$next[3:0]$11360 $4\src24__data_o$next[3:0]$11359 end case assign $1\src24__data_o$next[3:0]$11356 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src24__data_o$next[3:0]$11361 4'0000 case assign $6\src24__data_o$next[3:0]$11361 $1\src24__data_o$next[3:0]$11356 end sync always update \src24__data_o$next $0\src24__data_o$next[3:0]$11355 end attribute \src "libresoc.v:181988.3-182017.6" process $proc$libresoc.v:181988$11362 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11363 $1\wr_detect$4[0:0]$11364 attribute \src "libresoc.v:181989.5-181989.29" switch \initial attribute \src "libresoc.v:181989.9-181989.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11364 $4\wr_detect$4[0:0]$11367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11365 1'1 case assign $2\wr_detect$4[0:0]$11365 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11366 1'1 case assign $3\wr_detect$4[0:0]$11366 $2\wr_detect$4[0:0]$11365 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11367 1'1 case assign $4\wr_detect$4[0:0]$11367 $3\wr_detect$4[0:0]$11366 end case assign $1\wr_detect$4[0:0]$11364 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11363 end attribute \src "libresoc.v:182018.3-182057.6" process $proc$libresoc.v:182018$11368 assign { } { } assign { } { } assign { } { } assign $0\src34__data_o$next[3:0]$11369 $6\src34__data_o$next[3:0]$11375 attribute \src "libresoc.v:182019.5-182019.29" switch \initial attribute \src "libresoc.v:182019.9-182019.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src34__data_o$next[3:0]$11370 $5\src34__data_o$next[3:0]$11374 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src34__data_o$next[3:0]$11371 \dest14__data_i case assign $2\src34__data_o$next[3:0]$11371 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src34__data_o$next[3:0]$11372 \dest24__data_i case assign $3\src34__data_o$next[3:0]$11372 $2\src34__data_o$next[3:0]$11371 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src34__data_o$next[3:0]$11373 \w4__data_i case assign $4\src34__data_o$next[3:0]$11373 $3\src34__data_o$next[3:0]$11372 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src34__data_o$next[3:0]$11374 \reg case assign $5\src34__data_o$next[3:0]$11374 $4\src34__data_o$next[3:0]$11373 end case assign $1\src34__data_o$next[3:0]$11370 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src34__data_o$next[3:0]$11375 4'0000 case assign $6\src34__data_o$next[3:0]$11375 $1\src34__data_o$next[3:0]$11370 end sync always update \src34__data_o$next $0\src34__data_o$next[3:0]$11369 end attribute \src "libresoc.v:182058.3-182087.6" process $proc$libresoc.v:182058$11376 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11377 $1\wr_detect$7[0:0]$11378 attribute \src "libresoc.v:182059.5-182059.29" switch \initial attribute \src "libresoc.v:182059.9-182059.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src34__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11378 $4\wr_detect$7[0:0]$11381 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11379 1'1 case assign $2\wr_detect$7[0:0]$11379 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11380 1'1 case assign $3\wr_detect$7[0:0]$11380 $2\wr_detect$7[0:0]$11379 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11381 1'1 case assign $4\wr_detect$7[0:0]$11381 $3\wr_detect$7[0:0]$11380 end case assign $1\wr_detect$7[0:0]$11378 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11377 end attribute \src "libresoc.v:182088.3-182127.6" process $proc$libresoc.v:182088$11382 assign { } { } assign { } { } assign { } { } assign $0\r4__data_o$next[3:0]$11383 $6\r4__data_o$next[3:0]$11389 attribute \src "libresoc.v:182089.5-182089.29" switch \initial attribute \src "libresoc.v:182089.9-182089.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r4__data_o$next[3:0]$11384 $5\r4__data_o$next[3:0]$11388 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r4__data_o$next[3:0]$11385 \dest14__data_i case assign $2\r4__data_o$next[3:0]$11385 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r4__data_o$next[3:0]$11386 \dest24__data_i case assign $3\r4__data_o$next[3:0]$11386 $2\r4__data_o$next[3:0]$11385 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r4__data_o$next[3:0]$11387 \w4__data_i case assign $4\r4__data_o$next[3:0]$11387 $3\r4__data_o$next[3:0]$11386 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r4__data_o$next[3:0]$11388 \reg case assign $5\r4__data_o$next[3:0]$11388 $4\r4__data_o$next[3:0]$11387 end case assign $1\r4__data_o$next[3:0]$11384 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r4__data_o$next[3:0]$11389 4'0000 case assign $6\r4__data_o$next[3:0]$11389 $1\r4__data_o$next[3:0]$11384 end sync always update \r4__data_o$next $0\r4__data_o$next[3:0]$11383 end attribute \src "libresoc.v:182128.3-182157.6" process $proc$libresoc.v:182128$11390 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11391 $1\wr_detect$10[0:0]$11392 attribute \src "libresoc.v:182129.5-182129.29" switch \initial attribute \src "libresoc.v:182129.9-182129.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r4__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$11392 $4\wr_detect$10[0:0]$11395 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$11393 1'1 case assign $2\wr_detect$10[0:0]$11393 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$11394 1'1 case assign $3\wr_detect$10[0:0]$11394 $2\wr_detect$10[0:0]$11393 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$11395 1'1 case assign $4\wr_detect$10[0:0]$11395 $3\wr_detect$10[0:0]$11394 end case assign $1\wr_detect$10[0:0]$11392 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11391 end attribute \src "libresoc.v:182158.3-182197.6" process $proc$libresoc.v:182158$11396 assign { } { } assign { } { } assign { } { } assign $0\r24__data_o$next[3:0]$11397 $6\r24__data_o$next[3:0]$11403 attribute \src "libresoc.v:182159.5-182159.29" switch \initial attribute \src "libresoc.v:182159.9-182159.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r24__data_o$next[3:0]$11398 $5\r24__data_o$next[3:0]$11402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r24__data_o$next[3:0]$11399 \dest14__data_i case assign $2\r24__data_o$next[3:0]$11399 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r24__data_o$next[3:0]$11400 \dest24__data_i case assign $3\r24__data_o$next[3:0]$11400 $2\r24__data_o$next[3:0]$11399 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r24__data_o$next[3:0]$11401 \w4__data_i case assign $4\r24__data_o$next[3:0]$11401 $3\r24__data_o$next[3:0]$11400 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r24__data_o$next[3:0]$11402 \reg case assign $5\r24__data_o$next[3:0]$11402 $4\r24__data_o$next[3:0]$11401 end case assign $1\r24__data_o$next[3:0]$11398 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r24__data_o$next[3:0]$11403 4'0000 case assign $6\r24__data_o$next[3:0]$11403 $1\r24__data_o$next[3:0]$11398 end sync always update \r24__data_o$next $0\r24__data_o$next[3:0]$11397 end attribute \src "libresoc.v:182198.3-182227.6" process $proc$libresoc.v:182198$11404 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11405 $1\wr_detect$13[0:0]$11406 attribute \src "libresoc.v:182199.5-182199.29" switch \initial attribute \src "libresoc.v:182199.9-182199.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r24__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$11406 $4\wr_detect$13[0:0]$11409 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$11407 1'1 case assign $2\wr_detect$13[0:0]$11407 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$11408 1'1 case assign $3\wr_detect$13[0:0]$11408 $2\wr_detect$13[0:0]$11407 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$11409 1'1 case assign $4\wr_detect$13[0:0]$11409 $3\wr_detect$13[0:0]$11408 end case assign $1\wr_detect$13[0:0]$11406 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11405 end connect \$9 $not$libresoc.v:181834$11328_Y connect \$12 $not$libresoc.v:181835$11329_Y connect \$1 $not$libresoc.v:181836$11330_Y connect \$3 $not$libresoc.v:181837$11331_Y connect \$6 $not$libresoc.v:181838$11332_Y end attribute \src "libresoc.v:182232.1-182703.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 attribute \src "libresoc.v:182233.7-182233.20" wire $0\initial[0:0] attribute \src "libresoc.v:182633.3-182672.6" wire width 4 $0\r25__data_o$next[3:0]$11486 attribute \src "libresoc.v:182316.3-182317.39" wire width 4 $0\r25__data_o[3:0] attribute \src "libresoc.v:182563.3-182602.6" wire width 4 $0\r5__data_o$next[3:0]$11472 attribute \src "libresoc.v:182318.3-182319.37" wire width 4 $0\r5__data_o[3:0] attribute \src "libresoc.v:182396.3-182422.6" wire width 4 $0\reg$next[3:0]$11438 attribute \src "libresoc.v:182314.3-182315.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:182326.3-182365.6" wire width 4 $0\src15__data_o$next[3:0]$11429 attribute \src "libresoc.v:182324.3-182325.43" wire width 4 $0\src15__data_o[3:0] attribute \src "libresoc.v:182423.3-182462.6" wire width 4 $0\src25__data_o$next[3:0]$11444 attribute \src "libresoc.v:182322.3-182323.43" wire width 4 $0\src25__data_o[3:0] attribute \src "libresoc.v:182493.3-182532.6" wire width 4 $0\src35__data_o$next[3:0]$11458 attribute \src "libresoc.v:182320.3-182321.43" wire width 4 $0\src35__data_o[3:0] attribute \src "libresoc.v:182603.3-182632.6" wire $0\wr_detect$10[0:0]$11480 attribute \src "libresoc.v:182673.3-182702.6" wire $0\wr_detect$13[0:0]$11494 attribute \src "libresoc.v:182463.3-182492.6" wire $0\wr_detect$4[0:0]$11452 attribute \src "libresoc.v:182533.3-182562.6" wire $0\wr_detect$7[0:0]$11466 attribute \src "libresoc.v:182366.3-182395.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:182633.3-182672.6" wire width 4 $1\r25__data_o$next[3:0]$11487 attribute \src "libresoc.v:182258.13-182258.31" wire width 4 $1\r25__data_o[3:0] attribute \src "libresoc.v:182563.3-182602.6" wire width 4 $1\r5__data_o$next[3:0]$11473 attribute \src "libresoc.v:182265.13-182265.30" wire width 4 $1\r5__data_o[3:0] attribute \src "libresoc.v:182396.3-182422.6" wire width 4 $1\reg$next[3:0]$11439 attribute \src "libresoc.v:182271.13-182271.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:182326.3-182365.6" wire width 4 $1\src15__data_o$next[3:0]$11430 attribute \src "libresoc.v:182276.13-182276.33" wire width 4 $1\src15__data_o[3:0] attribute \src "libresoc.v:182423.3-182462.6" wire width 4 $1\src25__data_o$next[3:0]$11445 attribute \src "libresoc.v:182283.13-182283.33" wire width 4 $1\src25__data_o[3:0] attribute \src "libresoc.v:182493.3-182532.6" wire width 4 $1\src35__data_o$next[3:0]$11459 attribute \src "libresoc.v:182290.13-182290.33" wire width 4 $1\src35__data_o[3:0] attribute \src "libresoc.v:182603.3-182632.6" wire $1\wr_detect$10[0:0]$11481 attribute \src "libresoc.v:182673.3-182702.6" wire $1\wr_detect$13[0:0]$11495 attribute \src "libresoc.v:182463.3-182492.6" wire $1\wr_detect$4[0:0]$11453 attribute \src "libresoc.v:182533.3-182562.6" wire $1\wr_detect$7[0:0]$11467 attribute \src "libresoc.v:182366.3-182395.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:182633.3-182672.6" wire width 4 $2\r25__data_o$next[3:0]$11488 attribute \src "libresoc.v:182563.3-182602.6" wire width 4 $2\r5__data_o$next[3:0]$11474 attribute \src "libresoc.v:182396.3-182422.6" wire width 4 $2\reg$next[3:0]$11440 attribute \src "libresoc.v:182326.3-182365.6" wire width 4 $2\src15__data_o$next[3:0]$11431 attribute \src "libresoc.v:182423.3-182462.6" wire width 4 $2\src25__data_o$next[3:0]$11446 attribute \src "libresoc.v:182493.3-182532.6" wire width 4 $2\src35__data_o$next[3:0]$11460 attribute \src "libresoc.v:182603.3-182632.6" wire $2\wr_detect$10[0:0]$11482 attribute \src "libresoc.v:182673.3-182702.6" wire $2\wr_detect$13[0:0]$11496 attribute \src "libresoc.v:182463.3-182492.6" wire $2\wr_detect$4[0:0]$11454 attribute \src "libresoc.v:182533.3-182562.6" wire $2\wr_detect$7[0:0]$11468 attribute \src "libresoc.v:182366.3-182395.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:182633.3-182672.6" wire width 4 $3\r25__data_o$next[3:0]$11489 attribute \src "libresoc.v:182563.3-182602.6" wire width 4 $3\r5__data_o$next[3:0]$11475 attribute \src "libresoc.v:182396.3-182422.6" wire width 4 $3\reg$next[3:0]$11441 attribute \src "libresoc.v:182326.3-182365.6" wire width 4 $3\src15__data_o$next[3:0]$11432 attribute \src "libresoc.v:182423.3-182462.6" wire width 4 $3\src25__data_o$next[3:0]$11447 attribute \src "libresoc.v:182493.3-182532.6" wire width 4 $3\src35__data_o$next[3:0]$11461 attribute \src "libresoc.v:182603.3-182632.6" wire $3\wr_detect$10[0:0]$11483 attribute \src "libresoc.v:182673.3-182702.6" wire $3\wr_detect$13[0:0]$11497 attribute \src "libresoc.v:182463.3-182492.6" wire $3\wr_detect$4[0:0]$11455 attribute \src "libresoc.v:182533.3-182562.6" wire $3\wr_detect$7[0:0]$11469 attribute \src "libresoc.v:182366.3-182395.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:182633.3-182672.6" wire width 4 $4\r25__data_o$next[3:0]$11490 attribute \src "libresoc.v:182563.3-182602.6" wire width 4 $4\r5__data_o$next[3:0]$11476 attribute \src "libresoc.v:182396.3-182422.6" wire width 4 $4\reg$next[3:0]$11442 attribute \src "libresoc.v:182326.3-182365.6" wire width 4 $4\src15__data_o$next[3:0]$11433 attribute \src "libresoc.v:182423.3-182462.6" wire width 4 $4\src25__data_o$next[3:0]$11448 attribute \src "libresoc.v:182493.3-182532.6" wire width 4 $4\src35__data_o$next[3:0]$11462 attribute \src "libresoc.v:182603.3-182632.6" wire $4\wr_detect$10[0:0]$11484 attribute \src "libresoc.v:182673.3-182702.6" wire $4\wr_detect$13[0:0]$11498 attribute \src "libresoc.v:182463.3-182492.6" wire $4\wr_detect$4[0:0]$11456 attribute \src "libresoc.v:182533.3-182562.6" wire $4\wr_detect$7[0:0]$11470 attribute \src "libresoc.v:182366.3-182395.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:182633.3-182672.6" wire width 4 $5\r25__data_o$next[3:0]$11491 attribute \src "libresoc.v:182563.3-182602.6" wire width 4 $5\r5__data_o$next[3:0]$11477 attribute \src "libresoc.v:182326.3-182365.6" wire width 4 $5\src15__data_o$next[3:0]$11434 attribute \src "libresoc.v:182423.3-182462.6" wire width 4 $5\src25__data_o$next[3:0]$11449 attribute \src "libresoc.v:182493.3-182532.6" wire width 4 $5\src35__data_o$next[3:0]$11463 attribute \src "libresoc.v:182633.3-182672.6" wire width 4 $6\r25__data_o$next[3:0]$11492 attribute \src "libresoc.v:182563.3-182602.6" wire width 4 $6\r5__data_o$next[3:0]$11478 attribute \src "libresoc.v:182326.3-182365.6" wire width 4 $6\src15__data_o$next[3:0]$11435 attribute \src "libresoc.v:182423.3-182462.6" wire width 4 $6\src25__data_o$next[3:0]$11450 attribute \src "libresoc.v:182493.3-182532.6" wire width 4 $6\src35__data_o$next[3:0]$11464 attribute \src "libresoc.v:182309.17-182309.104" wire $not$libresoc.v:182309$11417_Y attribute \src "libresoc.v:182310.18-182310.105" wire $not$libresoc.v:182310$11418_Y attribute \src "libresoc.v:182311.17-182311.100" wire $not$libresoc.v:182311$11419_Y attribute \src "libresoc.v:182312.17-182312.103" wire $not$libresoc.v:182312$11420_Y attribute \src "libresoc.v:182313.17-182313.103" wire $not$libresoc.v:182313$11421_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest15__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest25__wen attribute \src "libresoc.v:182233.7-182233.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r5__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r5__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r5__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src15__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src15__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src15__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src25__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src25__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src25__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src35__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src35__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src35__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w5__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182309$11417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:182309$11417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182310$11418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:182310$11418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182311$11419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:182311$11419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182312$11420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:182312$11420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182313$11421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:182313$11421_Y end attribute \src "libresoc.v:182233.7-182233.20" process $proc$libresoc.v:182233$11499 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:182258.13-182258.31" process $proc$libresoc.v:182258$11500 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end attribute \src "libresoc.v:182265.13-182265.30" process $proc$libresoc.v:182265$11501 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end attribute \src "libresoc.v:182271.13-182271.25" process $proc$libresoc.v:182271$11502 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:182276.13-182276.33" process $proc$libresoc.v:182276$11503 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end attribute \src "libresoc.v:182283.13-182283.33" process $proc$libresoc.v:182283$11504 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end attribute \src "libresoc.v:182290.13-182290.33" process $proc$libresoc.v:182290$11505 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end attribute \src "libresoc.v:182314.3-182315.25" process $proc$libresoc.v:182314$11422 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:182316.3-182317.39" process $proc$libresoc.v:182316$11423 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end attribute \src "libresoc.v:182318.3-182319.37" process $proc$libresoc.v:182318$11424 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end attribute \src "libresoc.v:182320.3-182321.43" process $proc$libresoc.v:182320$11425 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end attribute \src "libresoc.v:182322.3-182323.43" process $proc$libresoc.v:182322$11426 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end attribute \src "libresoc.v:182324.3-182325.43" process $proc$libresoc.v:182324$11427 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end attribute \src "libresoc.v:182326.3-182365.6" process $proc$libresoc.v:182326$11428 assign { } { } assign { } { } assign { } { } assign $0\src15__data_o$next[3:0]$11429 $6\src15__data_o$next[3:0]$11435 attribute \src "libresoc.v:182327.5-182327.29" switch \initial attribute \src "libresoc.v:182327.9-182327.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src15__data_o$next[3:0]$11430 $5\src15__data_o$next[3:0]$11434 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src15__data_o$next[3:0]$11431 \dest15__data_i case assign $2\src15__data_o$next[3:0]$11431 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src15__data_o$next[3:0]$11432 \dest25__data_i case assign $3\src15__data_o$next[3:0]$11432 $2\src15__data_o$next[3:0]$11431 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src15__data_o$next[3:0]$11433 \w5__data_i case assign $4\src15__data_o$next[3:0]$11433 $3\src15__data_o$next[3:0]$11432 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src15__data_o$next[3:0]$11434 \reg case assign $5\src15__data_o$next[3:0]$11434 $4\src15__data_o$next[3:0]$11433 end case assign $1\src15__data_o$next[3:0]$11430 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src15__data_o$next[3:0]$11435 4'0000 case assign $6\src15__data_o$next[3:0]$11435 $1\src15__data_o$next[3:0]$11430 end sync always update \src15__data_o$next $0\src15__data_o$next[3:0]$11429 end attribute \src "libresoc.v:182366.3-182395.6" process $proc$libresoc.v:182366$11436 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:182367.5-182367.29" switch \initial attribute \src "libresoc.v:182367.9-182367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src15__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:182396.3-182422.6" process $proc$libresoc.v:182396$11437 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11438 $4\reg$next[3:0]$11442 attribute \src "libresoc.v:182397.5-182397.29" switch \initial attribute \src "libresoc.v:182397.9-182397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$11439 \dest15__data_i case assign $1\reg$next[3:0]$11439 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$11440 \dest25__data_i case assign $2\reg$next[3:0]$11440 $1\reg$next[3:0]$11439 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$11441 \w5__data_i case assign $3\reg$next[3:0]$11441 $2\reg$next[3:0]$11440 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$11442 4'0000 case assign $4\reg$next[3:0]$11442 $3\reg$next[3:0]$11441 end sync always update \reg$next $0\reg$next[3:0]$11438 end attribute \src "libresoc.v:182423.3-182462.6" process $proc$libresoc.v:182423$11443 assign { } { } assign { } { } assign { } { } assign $0\src25__data_o$next[3:0]$11444 $6\src25__data_o$next[3:0]$11450 attribute \src "libresoc.v:182424.5-182424.29" switch \initial attribute \src "libresoc.v:182424.9-182424.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src25__data_o$next[3:0]$11445 $5\src25__data_o$next[3:0]$11449 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src25__data_o$next[3:0]$11446 \dest15__data_i case assign $2\src25__data_o$next[3:0]$11446 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src25__data_o$next[3:0]$11447 \dest25__data_i case assign $3\src25__data_o$next[3:0]$11447 $2\src25__data_o$next[3:0]$11446 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src25__data_o$next[3:0]$11448 \w5__data_i case assign $4\src25__data_o$next[3:0]$11448 $3\src25__data_o$next[3:0]$11447 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src25__data_o$next[3:0]$11449 \reg case assign $5\src25__data_o$next[3:0]$11449 $4\src25__data_o$next[3:0]$11448 end case assign $1\src25__data_o$next[3:0]$11445 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src25__data_o$next[3:0]$11450 4'0000 case assign $6\src25__data_o$next[3:0]$11450 $1\src25__data_o$next[3:0]$11445 end sync always update \src25__data_o$next $0\src25__data_o$next[3:0]$11444 end attribute \src "libresoc.v:182463.3-182492.6" process $proc$libresoc.v:182463$11451 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11452 $1\wr_detect$4[0:0]$11453 attribute \src "libresoc.v:182464.5-182464.29" switch \initial attribute \src "libresoc.v:182464.9-182464.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11453 $4\wr_detect$4[0:0]$11456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11454 1'1 case assign $2\wr_detect$4[0:0]$11454 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11455 1'1 case assign $3\wr_detect$4[0:0]$11455 $2\wr_detect$4[0:0]$11454 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11456 1'1 case assign $4\wr_detect$4[0:0]$11456 $3\wr_detect$4[0:0]$11455 end case assign $1\wr_detect$4[0:0]$11453 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11452 end attribute \src "libresoc.v:182493.3-182532.6" process $proc$libresoc.v:182493$11457 assign { } { } assign { } { } assign { } { } assign $0\src35__data_o$next[3:0]$11458 $6\src35__data_o$next[3:0]$11464 attribute \src "libresoc.v:182494.5-182494.29" switch \initial attribute \src "libresoc.v:182494.9-182494.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src35__data_o$next[3:0]$11459 $5\src35__data_o$next[3:0]$11463 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src35__data_o$next[3:0]$11460 \dest15__data_i case assign $2\src35__data_o$next[3:0]$11460 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src35__data_o$next[3:0]$11461 \dest25__data_i case assign $3\src35__data_o$next[3:0]$11461 $2\src35__data_o$next[3:0]$11460 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src35__data_o$next[3:0]$11462 \w5__data_i case assign $4\src35__data_o$next[3:0]$11462 $3\src35__data_o$next[3:0]$11461 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src35__data_o$next[3:0]$11463 \reg case assign $5\src35__data_o$next[3:0]$11463 $4\src35__data_o$next[3:0]$11462 end case assign $1\src35__data_o$next[3:0]$11459 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src35__data_o$next[3:0]$11464 4'0000 case assign $6\src35__data_o$next[3:0]$11464 $1\src35__data_o$next[3:0]$11459 end sync always update \src35__data_o$next $0\src35__data_o$next[3:0]$11458 end attribute \src "libresoc.v:182533.3-182562.6" process $proc$libresoc.v:182533$11465 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11466 $1\wr_detect$7[0:0]$11467 attribute \src "libresoc.v:182534.5-182534.29" switch \initial attribute \src "libresoc.v:182534.9-182534.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src35__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11467 $4\wr_detect$7[0:0]$11470 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11468 1'1 case assign $2\wr_detect$7[0:0]$11468 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11469 1'1 case assign $3\wr_detect$7[0:0]$11469 $2\wr_detect$7[0:0]$11468 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11470 1'1 case assign $4\wr_detect$7[0:0]$11470 $3\wr_detect$7[0:0]$11469 end case assign $1\wr_detect$7[0:0]$11467 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11466 end attribute \src "libresoc.v:182563.3-182602.6" process $proc$libresoc.v:182563$11471 assign { } { } assign { } { } assign { } { } assign $0\r5__data_o$next[3:0]$11472 $6\r5__data_o$next[3:0]$11478 attribute \src "libresoc.v:182564.5-182564.29" switch \initial attribute \src "libresoc.v:182564.9-182564.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r5__data_o$next[3:0]$11473 $5\r5__data_o$next[3:0]$11477 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r5__data_o$next[3:0]$11474 \dest15__data_i case assign $2\r5__data_o$next[3:0]$11474 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r5__data_o$next[3:0]$11475 \dest25__data_i case assign $3\r5__data_o$next[3:0]$11475 $2\r5__data_o$next[3:0]$11474 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r5__data_o$next[3:0]$11476 \w5__data_i case assign $4\r5__data_o$next[3:0]$11476 $3\r5__data_o$next[3:0]$11475 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r5__data_o$next[3:0]$11477 \reg case assign $5\r5__data_o$next[3:0]$11477 $4\r5__data_o$next[3:0]$11476 end case assign $1\r5__data_o$next[3:0]$11473 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r5__data_o$next[3:0]$11478 4'0000 case assign $6\r5__data_o$next[3:0]$11478 $1\r5__data_o$next[3:0]$11473 end sync always update \r5__data_o$next $0\r5__data_o$next[3:0]$11472 end attribute \src "libresoc.v:182603.3-182632.6" process $proc$libresoc.v:182603$11479 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11480 $1\wr_detect$10[0:0]$11481 attribute \src "libresoc.v:182604.5-182604.29" switch \initial attribute \src "libresoc.v:182604.9-182604.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r5__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$11481 $4\wr_detect$10[0:0]$11484 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$11482 1'1 case assign $2\wr_detect$10[0:0]$11482 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$11483 1'1 case assign $3\wr_detect$10[0:0]$11483 $2\wr_detect$10[0:0]$11482 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$11484 1'1 case assign $4\wr_detect$10[0:0]$11484 $3\wr_detect$10[0:0]$11483 end case assign $1\wr_detect$10[0:0]$11481 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11480 end attribute \src "libresoc.v:182633.3-182672.6" process $proc$libresoc.v:182633$11485 assign { } { } assign { } { } assign { } { } assign $0\r25__data_o$next[3:0]$11486 $6\r25__data_o$next[3:0]$11492 attribute \src "libresoc.v:182634.5-182634.29" switch \initial attribute \src "libresoc.v:182634.9-182634.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r25__data_o$next[3:0]$11487 $5\r25__data_o$next[3:0]$11491 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r25__data_o$next[3:0]$11488 \dest15__data_i case assign $2\r25__data_o$next[3:0]$11488 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r25__data_o$next[3:0]$11489 \dest25__data_i case assign $3\r25__data_o$next[3:0]$11489 $2\r25__data_o$next[3:0]$11488 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r25__data_o$next[3:0]$11490 \w5__data_i case assign $4\r25__data_o$next[3:0]$11490 $3\r25__data_o$next[3:0]$11489 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r25__data_o$next[3:0]$11491 \reg case assign $5\r25__data_o$next[3:0]$11491 $4\r25__data_o$next[3:0]$11490 end case assign $1\r25__data_o$next[3:0]$11487 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r25__data_o$next[3:0]$11492 4'0000 case assign $6\r25__data_o$next[3:0]$11492 $1\r25__data_o$next[3:0]$11487 end sync always update \r25__data_o$next $0\r25__data_o$next[3:0]$11486 end attribute \src "libresoc.v:182673.3-182702.6" process $proc$libresoc.v:182673$11493 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11494 $1\wr_detect$13[0:0]$11495 attribute \src "libresoc.v:182674.5-182674.29" switch \initial attribute \src "libresoc.v:182674.9-182674.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r25__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$11495 $4\wr_detect$13[0:0]$11498 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$11496 1'1 case assign $2\wr_detect$13[0:0]$11496 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$11497 1'1 case assign $3\wr_detect$13[0:0]$11497 $2\wr_detect$13[0:0]$11496 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$11498 1'1 case assign $4\wr_detect$13[0:0]$11498 $3\wr_detect$13[0:0]$11497 end case assign $1\wr_detect$13[0:0]$11495 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11494 end connect \$9 $not$libresoc.v:182309$11417_Y connect \$12 $not$libresoc.v:182310$11418_Y connect \$1 $not$libresoc.v:182311$11419_Y connect \$3 $not$libresoc.v:182312$11420_Y connect \$6 $not$libresoc.v:182313$11421_Y end attribute \src "libresoc.v:182707.1-183178.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 attribute \src "libresoc.v:182708.7-182708.20" wire $0\initial[0:0] attribute \src "libresoc.v:183108.3-183147.6" wire width 4 $0\r26__data_o$next[3:0]$11575 attribute \src "libresoc.v:182791.3-182792.39" wire width 4 $0\r26__data_o[3:0] attribute \src "libresoc.v:183038.3-183077.6" wire width 4 $0\r6__data_o$next[3:0]$11561 attribute \src "libresoc.v:182793.3-182794.37" wire width 4 $0\r6__data_o[3:0] attribute \src "libresoc.v:182871.3-182897.6" wire width 4 $0\reg$next[3:0]$11527 attribute \src "libresoc.v:182789.3-182790.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:182801.3-182840.6" wire width 4 $0\src16__data_o$next[3:0]$11518 attribute \src "libresoc.v:182799.3-182800.43" wire width 4 $0\src16__data_o[3:0] attribute \src "libresoc.v:182898.3-182937.6" wire width 4 $0\src26__data_o$next[3:0]$11533 attribute \src "libresoc.v:182797.3-182798.43" wire width 4 $0\src26__data_o[3:0] attribute \src "libresoc.v:182968.3-183007.6" wire width 4 $0\src36__data_o$next[3:0]$11547 attribute \src "libresoc.v:182795.3-182796.43" wire width 4 $0\src36__data_o[3:0] attribute \src "libresoc.v:183078.3-183107.6" wire $0\wr_detect$10[0:0]$11569 attribute \src "libresoc.v:183148.3-183177.6" wire $0\wr_detect$13[0:0]$11583 attribute \src "libresoc.v:182938.3-182967.6" wire $0\wr_detect$4[0:0]$11541 attribute \src "libresoc.v:183008.3-183037.6" wire $0\wr_detect$7[0:0]$11555 attribute \src "libresoc.v:182841.3-182870.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:183108.3-183147.6" wire width 4 $1\r26__data_o$next[3:0]$11576 attribute \src "libresoc.v:182733.13-182733.31" wire width 4 $1\r26__data_o[3:0] attribute \src "libresoc.v:183038.3-183077.6" wire width 4 $1\r6__data_o$next[3:0]$11562 attribute \src "libresoc.v:182740.13-182740.30" wire width 4 $1\r6__data_o[3:0] attribute \src "libresoc.v:182871.3-182897.6" wire width 4 $1\reg$next[3:0]$11528 attribute \src "libresoc.v:182746.13-182746.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:182801.3-182840.6" wire width 4 $1\src16__data_o$next[3:0]$11519 attribute \src "libresoc.v:182751.13-182751.33" wire width 4 $1\src16__data_o[3:0] attribute \src "libresoc.v:182898.3-182937.6" wire width 4 $1\src26__data_o$next[3:0]$11534 attribute \src "libresoc.v:182758.13-182758.33" wire width 4 $1\src26__data_o[3:0] attribute \src "libresoc.v:182968.3-183007.6" wire width 4 $1\src36__data_o$next[3:0]$11548 attribute \src "libresoc.v:182765.13-182765.33" wire width 4 $1\src36__data_o[3:0] attribute \src "libresoc.v:183078.3-183107.6" wire $1\wr_detect$10[0:0]$11570 attribute \src "libresoc.v:183148.3-183177.6" wire $1\wr_detect$13[0:0]$11584 attribute \src "libresoc.v:182938.3-182967.6" wire $1\wr_detect$4[0:0]$11542 attribute \src "libresoc.v:183008.3-183037.6" wire $1\wr_detect$7[0:0]$11556 attribute \src "libresoc.v:182841.3-182870.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:183108.3-183147.6" wire width 4 $2\r26__data_o$next[3:0]$11577 attribute \src "libresoc.v:183038.3-183077.6" wire width 4 $2\r6__data_o$next[3:0]$11563 attribute \src "libresoc.v:182871.3-182897.6" wire width 4 $2\reg$next[3:0]$11529 attribute \src "libresoc.v:182801.3-182840.6" wire width 4 $2\src16__data_o$next[3:0]$11520 attribute \src "libresoc.v:182898.3-182937.6" wire width 4 $2\src26__data_o$next[3:0]$11535 attribute \src "libresoc.v:182968.3-183007.6" wire width 4 $2\src36__data_o$next[3:0]$11549 attribute \src "libresoc.v:183078.3-183107.6" wire $2\wr_detect$10[0:0]$11571 attribute \src "libresoc.v:183148.3-183177.6" wire $2\wr_detect$13[0:0]$11585 attribute \src "libresoc.v:182938.3-182967.6" wire $2\wr_detect$4[0:0]$11543 attribute \src "libresoc.v:183008.3-183037.6" wire $2\wr_detect$7[0:0]$11557 attribute \src "libresoc.v:182841.3-182870.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:183108.3-183147.6" wire width 4 $3\r26__data_o$next[3:0]$11578 attribute \src "libresoc.v:183038.3-183077.6" wire width 4 $3\r6__data_o$next[3:0]$11564 attribute \src "libresoc.v:182871.3-182897.6" wire width 4 $3\reg$next[3:0]$11530 attribute \src "libresoc.v:182801.3-182840.6" wire width 4 $3\src16__data_o$next[3:0]$11521 attribute \src "libresoc.v:182898.3-182937.6" wire width 4 $3\src26__data_o$next[3:0]$11536 attribute \src "libresoc.v:182968.3-183007.6" wire width 4 $3\src36__data_o$next[3:0]$11550 attribute \src "libresoc.v:183078.3-183107.6" wire $3\wr_detect$10[0:0]$11572 attribute \src "libresoc.v:183148.3-183177.6" wire $3\wr_detect$13[0:0]$11586 attribute \src "libresoc.v:182938.3-182967.6" wire $3\wr_detect$4[0:0]$11544 attribute \src "libresoc.v:183008.3-183037.6" wire $3\wr_detect$7[0:0]$11558 attribute \src "libresoc.v:182841.3-182870.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:183108.3-183147.6" wire width 4 $4\r26__data_o$next[3:0]$11579 attribute \src "libresoc.v:183038.3-183077.6" wire width 4 $4\r6__data_o$next[3:0]$11565 attribute \src "libresoc.v:182871.3-182897.6" wire width 4 $4\reg$next[3:0]$11531 attribute \src "libresoc.v:182801.3-182840.6" wire width 4 $4\src16__data_o$next[3:0]$11522 attribute \src "libresoc.v:182898.3-182937.6" wire width 4 $4\src26__data_o$next[3:0]$11537 attribute \src "libresoc.v:182968.3-183007.6" wire width 4 $4\src36__data_o$next[3:0]$11551 attribute \src "libresoc.v:183078.3-183107.6" wire $4\wr_detect$10[0:0]$11573 attribute \src "libresoc.v:183148.3-183177.6" wire $4\wr_detect$13[0:0]$11587 attribute \src "libresoc.v:182938.3-182967.6" wire $4\wr_detect$4[0:0]$11545 attribute \src "libresoc.v:183008.3-183037.6" wire $4\wr_detect$7[0:0]$11559 attribute \src "libresoc.v:182841.3-182870.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:183108.3-183147.6" wire width 4 $5\r26__data_o$next[3:0]$11580 attribute \src "libresoc.v:183038.3-183077.6" wire width 4 $5\r6__data_o$next[3:0]$11566 attribute \src "libresoc.v:182801.3-182840.6" wire width 4 $5\src16__data_o$next[3:0]$11523 attribute \src "libresoc.v:182898.3-182937.6" wire width 4 $5\src26__data_o$next[3:0]$11538 attribute \src "libresoc.v:182968.3-183007.6" wire width 4 $5\src36__data_o$next[3:0]$11552 attribute \src "libresoc.v:183108.3-183147.6" wire width 4 $6\r26__data_o$next[3:0]$11581 attribute \src "libresoc.v:183038.3-183077.6" wire width 4 $6\r6__data_o$next[3:0]$11567 attribute \src "libresoc.v:182801.3-182840.6" wire width 4 $6\src16__data_o$next[3:0]$11524 attribute \src "libresoc.v:182898.3-182937.6" wire width 4 $6\src26__data_o$next[3:0]$11539 attribute \src "libresoc.v:182968.3-183007.6" wire width 4 $6\src36__data_o$next[3:0]$11553 attribute \src "libresoc.v:182784.17-182784.104" wire $not$libresoc.v:182784$11506_Y attribute \src "libresoc.v:182785.18-182785.105" wire $not$libresoc.v:182785$11507_Y attribute \src "libresoc.v:182786.17-182786.100" wire $not$libresoc.v:182786$11508_Y attribute \src "libresoc.v:182787.17-182787.103" wire $not$libresoc.v:182787$11509_Y attribute \src "libresoc.v:182788.17-182788.103" wire $not$libresoc.v:182788$11510_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest16__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest16__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest26__wen attribute \src "libresoc.v:182708.7-182708.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r6__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r6__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r6__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src16__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src16__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src16__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src26__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src26__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src26__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src36__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src36__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src36__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w6__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182784$11506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:182784$11506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182785$11507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:182785$11507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182786$11508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:182786$11508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182787$11509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:182787$11509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:182788$11510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:182788$11510_Y end attribute \src "libresoc.v:182708.7-182708.20" process $proc$libresoc.v:182708$11588 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:182733.13-182733.31" process $proc$libresoc.v:182733$11589 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end attribute \src "libresoc.v:182740.13-182740.30" process $proc$libresoc.v:182740$11590 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end attribute \src "libresoc.v:182746.13-182746.25" process $proc$libresoc.v:182746$11591 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:182751.13-182751.33" process $proc$libresoc.v:182751$11592 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end attribute \src "libresoc.v:182758.13-182758.33" process $proc$libresoc.v:182758$11593 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end attribute \src "libresoc.v:182765.13-182765.33" process $proc$libresoc.v:182765$11594 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end attribute \src "libresoc.v:182789.3-182790.25" process $proc$libresoc.v:182789$11511 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:182791.3-182792.39" process $proc$libresoc.v:182791$11512 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end attribute \src "libresoc.v:182793.3-182794.37" process $proc$libresoc.v:182793$11513 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end attribute \src "libresoc.v:182795.3-182796.43" process $proc$libresoc.v:182795$11514 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end attribute \src "libresoc.v:182797.3-182798.43" process $proc$libresoc.v:182797$11515 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end attribute \src "libresoc.v:182799.3-182800.43" process $proc$libresoc.v:182799$11516 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end attribute \src "libresoc.v:182801.3-182840.6" process $proc$libresoc.v:182801$11517 assign { } { } assign { } { } assign { } { } assign $0\src16__data_o$next[3:0]$11518 $6\src16__data_o$next[3:0]$11524 attribute \src "libresoc.v:182802.5-182802.29" switch \initial attribute \src "libresoc.v:182802.9-182802.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src16__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src16__data_o$next[3:0]$11519 $5\src16__data_o$next[3:0]$11523 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src16__data_o$next[3:0]$11520 \dest16__data_i case assign $2\src16__data_o$next[3:0]$11520 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src16__data_o$next[3:0]$11521 \dest26__data_i case assign $3\src16__data_o$next[3:0]$11521 $2\src16__data_o$next[3:0]$11520 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src16__data_o$next[3:0]$11522 \w6__data_i case assign $4\src16__data_o$next[3:0]$11522 $3\src16__data_o$next[3:0]$11521 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src16__data_o$next[3:0]$11523 \reg case assign $5\src16__data_o$next[3:0]$11523 $4\src16__data_o$next[3:0]$11522 end case assign $1\src16__data_o$next[3:0]$11519 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src16__data_o$next[3:0]$11524 4'0000 case assign $6\src16__data_o$next[3:0]$11524 $1\src16__data_o$next[3:0]$11519 end sync always update \src16__data_o$next $0\src16__data_o$next[3:0]$11518 end attribute \src "libresoc.v:182841.3-182870.6" process $proc$libresoc.v:182841$11525 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:182842.5-182842.29" switch \initial attribute \src "libresoc.v:182842.9-182842.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src16__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:182871.3-182897.6" process $proc$libresoc.v:182871$11526 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11527 $4\reg$next[3:0]$11531 attribute \src "libresoc.v:182872.5-182872.29" switch \initial attribute \src "libresoc.v:182872.9-182872.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$11528 \dest16__data_i case assign $1\reg$next[3:0]$11528 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$11529 \dest26__data_i case assign $2\reg$next[3:0]$11529 $1\reg$next[3:0]$11528 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$11530 \w6__data_i case assign $3\reg$next[3:0]$11530 $2\reg$next[3:0]$11529 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$11531 4'0000 case assign $4\reg$next[3:0]$11531 $3\reg$next[3:0]$11530 end sync always update \reg$next $0\reg$next[3:0]$11527 end attribute \src "libresoc.v:182898.3-182937.6" process $proc$libresoc.v:182898$11532 assign { } { } assign { } { } assign { } { } assign $0\src26__data_o$next[3:0]$11533 $6\src26__data_o$next[3:0]$11539 attribute \src "libresoc.v:182899.5-182899.29" switch \initial attribute \src "libresoc.v:182899.9-182899.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src26__data_o$next[3:0]$11534 $5\src26__data_o$next[3:0]$11538 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src26__data_o$next[3:0]$11535 \dest16__data_i case assign $2\src26__data_o$next[3:0]$11535 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src26__data_o$next[3:0]$11536 \dest26__data_i case assign $3\src26__data_o$next[3:0]$11536 $2\src26__data_o$next[3:0]$11535 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src26__data_o$next[3:0]$11537 \w6__data_i case assign $4\src26__data_o$next[3:0]$11537 $3\src26__data_o$next[3:0]$11536 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src26__data_o$next[3:0]$11538 \reg case assign $5\src26__data_o$next[3:0]$11538 $4\src26__data_o$next[3:0]$11537 end case assign $1\src26__data_o$next[3:0]$11534 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src26__data_o$next[3:0]$11539 4'0000 case assign $6\src26__data_o$next[3:0]$11539 $1\src26__data_o$next[3:0]$11534 end sync always update \src26__data_o$next $0\src26__data_o$next[3:0]$11533 end attribute \src "libresoc.v:182938.3-182967.6" process $proc$libresoc.v:182938$11540 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11541 $1\wr_detect$4[0:0]$11542 attribute \src "libresoc.v:182939.5-182939.29" switch \initial attribute \src "libresoc.v:182939.9-182939.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11542 $4\wr_detect$4[0:0]$11545 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11543 1'1 case assign $2\wr_detect$4[0:0]$11543 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11544 1'1 case assign $3\wr_detect$4[0:0]$11544 $2\wr_detect$4[0:0]$11543 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11545 1'1 case assign $4\wr_detect$4[0:0]$11545 $3\wr_detect$4[0:0]$11544 end case assign $1\wr_detect$4[0:0]$11542 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11541 end attribute \src "libresoc.v:182968.3-183007.6" process $proc$libresoc.v:182968$11546 assign { } { } assign { } { } assign { } { } assign $0\src36__data_o$next[3:0]$11547 $6\src36__data_o$next[3:0]$11553 attribute \src "libresoc.v:182969.5-182969.29" switch \initial attribute \src "libresoc.v:182969.9-182969.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src36__data_o$next[3:0]$11548 $5\src36__data_o$next[3:0]$11552 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src36__data_o$next[3:0]$11549 \dest16__data_i case assign $2\src36__data_o$next[3:0]$11549 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src36__data_o$next[3:0]$11550 \dest26__data_i case assign $3\src36__data_o$next[3:0]$11550 $2\src36__data_o$next[3:0]$11549 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src36__data_o$next[3:0]$11551 \w6__data_i case assign $4\src36__data_o$next[3:0]$11551 $3\src36__data_o$next[3:0]$11550 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src36__data_o$next[3:0]$11552 \reg case assign $5\src36__data_o$next[3:0]$11552 $4\src36__data_o$next[3:0]$11551 end case assign $1\src36__data_o$next[3:0]$11548 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src36__data_o$next[3:0]$11553 4'0000 case assign $6\src36__data_o$next[3:0]$11553 $1\src36__data_o$next[3:0]$11548 end sync always update \src36__data_o$next $0\src36__data_o$next[3:0]$11547 end attribute \src "libresoc.v:183008.3-183037.6" process $proc$libresoc.v:183008$11554 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11555 $1\wr_detect$7[0:0]$11556 attribute \src "libresoc.v:183009.5-183009.29" switch \initial attribute \src "libresoc.v:183009.9-183009.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src36__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11556 $4\wr_detect$7[0:0]$11559 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11557 1'1 case assign $2\wr_detect$7[0:0]$11557 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11558 1'1 case assign $3\wr_detect$7[0:0]$11558 $2\wr_detect$7[0:0]$11557 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11559 1'1 case assign $4\wr_detect$7[0:0]$11559 $3\wr_detect$7[0:0]$11558 end case assign $1\wr_detect$7[0:0]$11556 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11555 end attribute \src "libresoc.v:183038.3-183077.6" process $proc$libresoc.v:183038$11560 assign { } { } assign { } { } assign { } { } assign $0\r6__data_o$next[3:0]$11561 $6\r6__data_o$next[3:0]$11567 attribute \src "libresoc.v:183039.5-183039.29" switch \initial attribute \src "libresoc.v:183039.9-183039.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r6__data_o$next[3:0]$11562 $5\r6__data_o$next[3:0]$11566 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r6__data_o$next[3:0]$11563 \dest16__data_i case assign $2\r6__data_o$next[3:0]$11563 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r6__data_o$next[3:0]$11564 \dest26__data_i case assign $3\r6__data_o$next[3:0]$11564 $2\r6__data_o$next[3:0]$11563 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r6__data_o$next[3:0]$11565 \w6__data_i case assign $4\r6__data_o$next[3:0]$11565 $3\r6__data_o$next[3:0]$11564 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r6__data_o$next[3:0]$11566 \reg case assign $5\r6__data_o$next[3:0]$11566 $4\r6__data_o$next[3:0]$11565 end case assign $1\r6__data_o$next[3:0]$11562 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r6__data_o$next[3:0]$11567 4'0000 case assign $6\r6__data_o$next[3:0]$11567 $1\r6__data_o$next[3:0]$11562 end sync always update \r6__data_o$next $0\r6__data_o$next[3:0]$11561 end attribute \src "libresoc.v:183078.3-183107.6" process $proc$libresoc.v:183078$11568 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11569 $1\wr_detect$10[0:0]$11570 attribute \src "libresoc.v:183079.5-183079.29" switch \initial attribute \src "libresoc.v:183079.9-183079.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r6__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$11570 $4\wr_detect$10[0:0]$11573 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$11571 1'1 case assign $2\wr_detect$10[0:0]$11571 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$11572 1'1 case assign $3\wr_detect$10[0:0]$11572 $2\wr_detect$10[0:0]$11571 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$11573 1'1 case assign $4\wr_detect$10[0:0]$11573 $3\wr_detect$10[0:0]$11572 end case assign $1\wr_detect$10[0:0]$11570 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11569 end attribute \src "libresoc.v:183108.3-183147.6" process $proc$libresoc.v:183108$11574 assign { } { } assign { } { } assign { } { } assign $0\r26__data_o$next[3:0]$11575 $6\r26__data_o$next[3:0]$11581 attribute \src "libresoc.v:183109.5-183109.29" switch \initial attribute \src "libresoc.v:183109.9-183109.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r26__data_o$next[3:0]$11576 $5\r26__data_o$next[3:0]$11580 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r26__data_o$next[3:0]$11577 \dest16__data_i case assign $2\r26__data_o$next[3:0]$11577 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r26__data_o$next[3:0]$11578 \dest26__data_i case assign $3\r26__data_o$next[3:0]$11578 $2\r26__data_o$next[3:0]$11577 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r26__data_o$next[3:0]$11579 \w6__data_i case assign $4\r26__data_o$next[3:0]$11579 $3\r26__data_o$next[3:0]$11578 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r26__data_o$next[3:0]$11580 \reg case assign $5\r26__data_o$next[3:0]$11580 $4\r26__data_o$next[3:0]$11579 end case assign $1\r26__data_o$next[3:0]$11576 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r26__data_o$next[3:0]$11581 4'0000 case assign $6\r26__data_o$next[3:0]$11581 $1\r26__data_o$next[3:0]$11576 end sync always update \r26__data_o$next $0\r26__data_o$next[3:0]$11575 end attribute \src "libresoc.v:183148.3-183177.6" process $proc$libresoc.v:183148$11582 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11583 $1\wr_detect$13[0:0]$11584 attribute \src "libresoc.v:183149.5-183149.29" switch \initial attribute \src "libresoc.v:183149.9-183149.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r26__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$11584 $4\wr_detect$13[0:0]$11587 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$11585 1'1 case assign $2\wr_detect$13[0:0]$11585 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$11586 1'1 case assign $3\wr_detect$13[0:0]$11586 $2\wr_detect$13[0:0]$11585 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$11587 1'1 case assign $4\wr_detect$13[0:0]$11587 $3\wr_detect$13[0:0]$11586 end case assign $1\wr_detect$13[0:0]$11584 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11583 end connect \$9 $not$libresoc.v:182784$11506_Y connect \$12 $not$libresoc.v:182785$11507_Y connect \$1 $not$libresoc.v:182786$11508_Y connect \$3 $not$libresoc.v:182787$11509_Y connect \$6 $not$libresoc.v:182788$11510_Y end attribute \src "libresoc.v:183182.1-183653.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 attribute \src "libresoc.v:183183.7-183183.20" wire $0\initial[0:0] attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $0\r27__data_o$next[3:0]$11664 attribute \src "libresoc.v:183266.3-183267.39" wire width 4 $0\r27__data_o[3:0] attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $0\r7__data_o$next[3:0]$11650 attribute \src "libresoc.v:183268.3-183269.37" wire width 4 $0\r7__data_o[3:0] attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $0\reg$next[3:0]$11616 attribute \src "libresoc.v:183264.3-183265.25" wire width 4 $0\reg[3:0] attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $0\src17__data_o$next[3:0]$11607 attribute \src "libresoc.v:183274.3-183275.43" wire width 4 $0\src17__data_o[3:0] attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $0\src27__data_o$next[3:0]$11622 attribute \src "libresoc.v:183272.3-183273.43" wire width 4 $0\src27__data_o[3:0] attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $0\src37__data_o$next[3:0]$11636 attribute \src "libresoc.v:183270.3-183271.43" wire width 4 $0\src37__data_o[3:0] attribute \src "libresoc.v:183553.3-183582.6" wire $0\wr_detect$10[0:0]$11658 attribute \src "libresoc.v:183623.3-183652.6" wire $0\wr_detect$13[0:0]$11672 attribute \src "libresoc.v:183413.3-183442.6" wire $0\wr_detect$4[0:0]$11630 attribute \src "libresoc.v:183483.3-183512.6" wire $0\wr_detect$7[0:0]$11644 attribute \src "libresoc.v:183316.3-183345.6" wire $0\wr_detect[0:0] attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $1\r27__data_o$next[3:0]$11665 attribute \src "libresoc.v:183208.13-183208.31" wire width 4 $1\r27__data_o[3:0] attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $1\r7__data_o$next[3:0]$11651 attribute \src "libresoc.v:183215.13-183215.30" wire width 4 $1\r7__data_o[3:0] attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $1\reg$next[3:0]$11617 attribute \src "libresoc.v:183221.13-183221.25" wire width 4 $1\reg[3:0] attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $1\src17__data_o$next[3:0]$11608 attribute \src "libresoc.v:183226.13-183226.33" wire width 4 $1\src17__data_o[3:0] attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $1\src27__data_o$next[3:0]$11623 attribute \src "libresoc.v:183233.13-183233.33" wire width 4 $1\src27__data_o[3:0] attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $1\src37__data_o$next[3:0]$11637 attribute \src "libresoc.v:183240.13-183240.33" wire width 4 $1\src37__data_o[3:0] attribute \src "libresoc.v:183553.3-183582.6" wire $1\wr_detect$10[0:0]$11659 attribute \src "libresoc.v:183623.3-183652.6" wire $1\wr_detect$13[0:0]$11673 attribute \src "libresoc.v:183413.3-183442.6" wire $1\wr_detect$4[0:0]$11631 attribute \src "libresoc.v:183483.3-183512.6" wire $1\wr_detect$7[0:0]$11645 attribute \src "libresoc.v:183316.3-183345.6" wire $1\wr_detect[0:0] attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $2\r27__data_o$next[3:0]$11666 attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $2\r7__data_o$next[3:0]$11652 attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $2\reg$next[3:0]$11618 attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $2\src17__data_o$next[3:0]$11609 attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $2\src27__data_o$next[3:0]$11624 attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $2\src37__data_o$next[3:0]$11638 attribute \src "libresoc.v:183553.3-183582.6" wire $2\wr_detect$10[0:0]$11660 attribute \src "libresoc.v:183623.3-183652.6" wire $2\wr_detect$13[0:0]$11674 attribute \src "libresoc.v:183413.3-183442.6" wire $2\wr_detect$4[0:0]$11632 attribute \src "libresoc.v:183483.3-183512.6" wire $2\wr_detect$7[0:0]$11646 attribute \src "libresoc.v:183316.3-183345.6" wire $2\wr_detect[0:0] attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $3\r27__data_o$next[3:0]$11667 attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $3\r7__data_o$next[3:0]$11653 attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $3\reg$next[3:0]$11619 attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $3\src17__data_o$next[3:0]$11610 attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $3\src27__data_o$next[3:0]$11625 attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $3\src37__data_o$next[3:0]$11639 attribute \src "libresoc.v:183553.3-183582.6" wire $3\wr_detect$10[0:0]$11661 attribute \src "libresoc.v:183623.3-183652.6" wire $3\wr_detect$13[0:0]$11675 attribute \src "libresoc.v:183413.3-183442.6" wire $3\wr_detect$4[0:0]$11633 attribute \src "libresoc.v:183483.3-183512.6" wire $3\wr_detect$7[0:0]$11647 attribute \src "libresoc.v:183316.3-183345.6" wire $3\wr_detect[0:0] attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $4\r27__data_o$next[3:0]$11668 attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $4\r7__data_o$next[3:0]$11654 attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $4\reg$next[3:0]$11620 attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $4\src17__data_o$next[3:0]$11611 attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $4\src27__data_o$next[3:0]$11626 attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $4\src37__data_o$next[3:0]$11640 attribute \src "libresoc.v:183553.3-183582.6" wire $4\wr_detect$10[0:0]$11662 attribute \src "libresoc.v:183623.3-183652.6" wire $4\wr_detect$13[0:0]$11676 attribute \src "libresoc.v:183413.3-183442.6" wire $4\wr_detect$4[0:0]$11634 attribute \src "libresoc.v:183483.3-183512.6" wire $4\wr_detect$7[0:0]$11648 attribute \src "libresoc.v:183316.3-183345.6" wire $4\wr_detect[0:0] attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $5\r27__data_o$next[3:0]$11669 attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $5\r7__data_o$next[3:0]$11655 attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $5\src17__data_o$next[3:0]$11612 attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $5\src27__data_o$next[3:0]$11627 attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $5\src37__data_o$next[3:0]$11641 attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $6\r27__data_o$next[3:0]$11670 attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $6\r7__data_o$next[3:0]$11656 attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $6\src17__data_o$next[3:0]$11613 attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $6\src27__data_o$next[3:0]$11628 attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $6\src37__data_o$next[3:0]$11642 attribute \src "libresoc.v:183259.17-183259.104" wire $not$libresoc.v:183259$11595_Y attribute \src "libresoc.v:183260.18-183260.105" wire $not$libresoc.v:183260$11596_Y attribute \src "libresoc.v:183261.17-183261.100" wire $not$libresoc.v:183261$11597_Y attribute \src "libresoc.v:183262.17-183262.103" wire $not$libresoc.v:183262$11598_Y attribute \src "libresoc.v:183263.17-183263.103" wire $not$libresoc.v:183263$11599_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 18 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest17__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 8 \dest17__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 11 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest27__wen attribute \src "libresoc.v:183183.7-183183.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 15 \r27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r7__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \r7__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \r7__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" wire width 4 \reg$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \src17__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src17__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \src17__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 5 \src27__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src27__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \src27__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 7 \src37__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \src37__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 6 \src37__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 16 \w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 17 \w7__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:183259$11595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 connect \Y $not$libresoc.v:183259$11595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:183260$11596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 connect \Y $not$libresoc.v:183260$11596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:183261$11597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect connect \Y $not$libresoc.v:183261$11597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:183262$11598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 connect \Y $not$libresoc.v:183262$11598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" cell $not $not$libresoc.v:183263$11599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 connect \Y $not$libresoc.v:183263$11599_Y end attribute \src "libresoc.v:183183.7-183183.20" process $proc$libresoc.v:183183$11677 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:183208.13-183208.31" process $proc$libresoc.v:183208$11678 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end attribute \src "libresoc.v:183215.13-183215.30" process $proc$libresoc.v:183215$11679 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end attribute \src "libresoc.v:183221.13-183221.25" process $proc$libresoc.v:183221$11680 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end attribute \src "libresoc.v:183226.13-183226.33" process $proc$libresoc.v:183226$11681 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end attribute \src "libresoc.v:183233.13-183233.33" process $proc$libresoc.v:183233$11682 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end attribute \src "libresoc.v:183240.13-183240.33" process $proc$libresoc.v:183240$11683 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end attribute \src "libresoc.v:183264.3-183265.25" process $proc$libresoc.v:183264$11600 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end attribute \src "libresoc.v:183266.3-183267.39" process $proc$libresoc.v:183266$11601 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end attribute \src "libresoc.v:183268.3-183269.37" process $proc$libresoc.v:183268$11602 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end attribute \src "libresoc.v:183270.3-183271.43" process $proc$libresoc.v:183270$11603 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end attribute \src "libresoc.v:183272.3-183273.43" process $proc$libresoc.v:183272$11604 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end attribute \src "libresoc.v:183274.3-183275.43" process $proc$libresoc.v:183274$11605 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end attribute \src "libresoc.v:183276.3-183315.6" process $proc$libresoc.v:183276$11606 assign { } { } assign { } { } assign { } { } assign $0\src17__data_o$next[3:0]$11607 $6\src17__data_o$next[3:0]$11613 attribute \src "libresoc.v:183277.5-183277.29" switch \initial attribute \src "libresoc.v:183277.9-183277.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src17__data_o$next[3:0]$11608 $5\src17__data_o$next[3:0]$11612 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src17__data_o$next[3:0]$11609 \dest17__data_i case assign $2\src17__data_o$next[3:0]$11609 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src17__data_o$next[3:0]$11610 \dest27__data_i case assign $3\src17__data_o$next[3:0]$11610 $2\src17__data_o$next[3:0]$11609 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src17__data_o$next[3:0]$11611 \w7__data_i case assign $4\src17__data_o$next[3:0]$11611 $3\src17__data_o$next[3:0]$11610 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src17__data_o$next[3:0]$11612 \reg case assign $5\src17__data_o$next[3:0]$11612 $4\src17__data_o$next[3:0]$11611 end case assign $1\src17__data_o$next[3:0]$11608 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src17__data_o$next[3:0]$11613 4'0000 case assign $6\src17__data_o$next[3:0]$11613 $1\src17__data_o$next[3:0]$11608 end sync always update \src17__data_o$next $0\src17__data_o$next[3:0]$11607 end attribute \src "libresoc.v:183316.3-183345.6" process $proc$libresoc.v:183316$11614 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] attribute \src "libresoc.v:183317.5-183317.29" switch \initial attribute \src "libresoc.v:183317.9-183317.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src17__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect[0:0] $4\wr_detect[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect[0:0] 1'1 case assign $2\wr_detect[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect[0:0] 1'1 case assign $3\wr_detect[0:0] $2\wr_detect[0:0] end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect[0:0] 1'1 case assign $4\wr_detect[0:0] $3\wr_detect[0:0] end case assign $1\wr_detect[0:0] 1'0 end sync always update \wr_detect $0\wr_detect[0:0] end attribute \src "libresoc.v:183346.3-183372.6" process $proc$libresoc.v:183346$11615 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11616 $4\reg$next[3:0]$11620 attribute \src "libresoc.v:183347.5-183347.29" switch \initial attribute \src "libresoc.v:183347.9-183347.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\reg$next[3:0]$11617 \dest17__data_i case assign $1\reg$next[3:0]$11617 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\reg$next[3:0]$11618 \dest27__data_i case assign $2\reg$next[3:0]$11618 $1\reg$next[3:0]$11617 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\reg$next[3:0]$11619 \w7__data_i case assign $3\reg$next[3:0]$11619 $2\reg$next[3:0]$11618 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\reg$next[3:0]$11620 4'0000 case assign $4\reg$next[3:0]$11620 $3\reg$next[3:0]$11619 end sync always update \reg$next $0\reg$next[3:0]$11616 end attribute \src "libresoc.v:183373.3-183412.6" process $proc$libresoc.v:183373$11621 assign { } { } assign { } { } assign { } { } assign $0\src27__data_o$next[3:0]$11622 $6\src27__data_o$next[3:0]$11628 attribute \src "libresoc.v:183374.5-183374.29" switch \initial attribute \src "libresoc.v:183374.9-183374.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src27__data_o$next[3:0]$11623 $5\src27__data_o$next[3:0]$11627 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src27__data_o$next[3:0]$11624 \dest17__data_i case assign $2\src27__data_o$next[3:0]$11624 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src27__data_o$next[3:0]$11625 \dest27__data_i case assign $3\src27__data_o$next[3:0]$11625 $2\src27__data_o$next[3:0]$11624 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src27__data_o$next[3:0]$11626 \w7__data_i case assign $4\src27__data_o$next[3:0]$11626 $3\src27__data_o$next[3:0]$11625 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src27__data_o$next[3:0]$11627 \reg case assign $5\src27__data_o$next[3:0]$11627 $4\src27__data_o$next[3:0]$11626 end case assign $1\src27__data_o$next[3:0]$11623 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src27__data_o$next[3:0]$11628 4'0000 case assign $6\src27__data_o$next[3:0]$11628 $1\src27__data_o$next[3:0]$11623 end sync always update \src27__data_o$next $0\src27__data_o$next[3:0]$11622 end attribute \src "libresoc.v:183413.3-183442.6" process $proc$libresoc.v:183413$11629 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11630 $1\wr_detect$4[0:0]$11631 attribute \src "libresoc.v:183414.5-183414.29" switch \initial attribute \src "libresoc.v:183414.9-183414.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$4[0:0]$11631 $4\wr_detect$4[0:0]$11634 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$4[0:0]$11632 1'1 case assign $2\wr_detect$4[0:0]$11632 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$4[0:0]$11633 1'1 case assign $3\wr_detect$4[0:0]$11633 $2\wr_detect$4[0:0]$11632 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$4[0:0]$11634 1'1 case assign $4\wr_detect$4[0:0]$11634 $3\wr_detect$4[0:0]$11633 end case assign $1\wr_detect$4[0:0]$11631 1'0 end sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11630 end attribute \src "libresoc.v:183443.3-183482.6" process $proc$libresoc.v:183443$11635 assign { } { } assign { } { } assign { } { } assign $0\src37__data_o$next[3:0]$11636 $6\src37__data_o$next[3:0]$11642 attribute \src "libresoc.v:183444.5-183444.29" switch \initial attribute \src "libresoc.v:183444.9-183444.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\src37__data_o$next[3:0]$11637 $5\src37__data_o$next[3:0]$11641 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\src37__data_o$next[3:0]$11638 \dest17__data_i case assign $2\src37__data_o$next[3:0]$11638 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\src37__data_o$next[3:0]$11639 \dest27__data_i case assign $3\src37__data_o$next[3:0]$11639 $2\src37__data_o$next[3:0]$11638 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\src37__data_o$next[3:0]$11640 \w7__data_i case assign $4\src37__data_o$next[3:0]$11640 $3\src37__data_o$next[3:0]$11639 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\src37__data_o$next[3:0]$11641 \reg case assign $5\src37__data_o$next[3:0]$11641 $4\src37__data_o$next[3:0]$11640 end case assign $1\src37__data_o$next[3:0]$11637 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\src37__data_o$next[3:0]$11642 4'0000 case assign $6\src37__data_o$next[3:0]$11642 $1\src37__data_o$next[3:0]$11637 end sync always update \src37__data_o$next $0\src37__data_o$next[3:0]$11636 end attribute \src "libresoc.v:183483.3-183512.6" process $proc$libresoc.v:183483$11643 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11644 $1\wr_detect$7[0:0]$11645 attribute \src "libresoc.v:183484.5-183484.29" switch \initial attribute \src "libresoc.v:183484.9-183484.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \src37__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$7[0:0]$11645 $4\wr_detect$7[0:0]$11648 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$7[0:0]$11646 1'1 case assign $2\wr_detect$7[0:0]$11646 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$7[0:0]$11647 1'1 case assign $3\wr_detect$7[0:0]$11647 $2\wr_detect$7[0:0]$11646 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$7[0:0]$11648 1'1 case assign $4\wr_detect$7[0:0]$11648 $3\wr_detect$7[0:0]$11647 end case assign $1\wr_detect$7[0:0]$11645 1'0 end sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11644 end attribute \src "libresoc.v:183513.3-183552.6" process $proc$libresoc.v:183513$11649 assign { } { } assign { } { } assign { } { } assign $0\r7__data_o$next[3:0]$11650 $6\r7__data_o$next[3:0]$11656 attribute \src "libresoc.v:183514.5-183514.29" switch \initial attribute \src "libresoc.v:183514.9-183514.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r7__data_o$next[3:0]$11651 $5\r7__data_o$next[3:0]$11655 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r7__data_o$next[3:0]$11652 \dest17__data_i case assign $2\r7__data_o$next[3:0]$11652 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r7__data_o$next[3:0]$11653 \dest27__data_i case assign $3\r7__data_o$next[3:0]$11653 $2\r7__data_o$next[3:0]$11652 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r7__data_o$next[3:0]$11654 \w7__data_i case assign $4\r7__data_o$next[3:0]$11654 $3\r7__data_o$next[3:0]$11653 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r7__data_o$next[3:0]$11655 \reg case assign $5\r7__data_o$next[3:0]$11655 $4\r7__data_o$next[3:0]$11654 end case assign $1\r7__data_o$next[3:0]$11651 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r7__data_o$next[3:0]$11656 4'0000 case assign $6\r7__data_o$next[3:0]$11656 $1\r7__data_o$next[3:0]$11651 end sync always update \r7__data_o$next $0\r7__data_o$next[3:0]$11650 end attribute \src "libresoc.v:183553.3-183582.6" process $proc$libresoc.v:183553$11657 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11658 $1\wr_detect$10[0:0]$11659 attribute \src "libresoc.v:183554.5-183554.29" switch \initial attribute \src "libresoc.v:183554.9-183554.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r7__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$10[0:0]$11659 $4\wr_detect$10[0:0]$11662 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$10[0:0]$11660 1'1 case assign $2\wr_detect$10[0:0]$11660 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$10[0:0]$11661 1'1 case assign $3\wr_detect$10[0:0]$11661 $2\wr_detect$10[0:0]$11660 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$10[0:0]$11662 1'1 case assign $4\wr_detect$10[0:0]$11662 $3\wr_detect$10[0:0]$11661 end case assign $1\wr_detect$10[0:0]$11659 1'0 end sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11658 end attribute \src "libresoc.v:183583.3-183622.6" process $proc$libresoc.v:183583$11663 assign { } { } assign { } { } assign { } { } assign $0\r27__data_o$next[3:0]$11664 $6\r27__data_o$next[3:0]$11670 attribute \src "libresoc.v:183584.5-183584.29" switch \initial attribute \src "libresoc.v:183584.9-183584.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\r27__data_o$next[3:0]$11665 $5\r27__data_o$next[3:0]$11669 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\r27__data_o$next[3:0]$11666 \dest17__data_i case assign $2\r27__data_o$next[3:0]$11666 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\r27__data_o$next[3:0]$11667 \dest27__data_i case assign $3\r27__data_o$next[3:0]$11667 $2\r27__data_o$next[3:0]$11666 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\r27__data_o$next[3:0]$11668 \w7__data_i case assign $4\r27__data_o$next[3:0]$11668 $3\r27__data_o$next[3:0]$11667 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\r27__data_o$next[3:0]$11669 \reg case assign $5\r27__data_o$next[3:0]$11669 $4\r27__data_o$next[3:0]$11668 end case assign $1\r27__data_o$next[3:0]$11665 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\r27__data_o$next[3:0]$11670 4'0000 case assign $6\r27__data_o$next[3:0]$11670 $1\r27__data_o$next[3:0]$11665 end sync always update \r27__data_o$next $0\r27__data_o$next[3:0]$11664 end attribute \src "libresoc.v:183623.3-183652.6" process $proc$libresoc.v:183623$11671 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11672 $1\wr_detect$13[0:0]$11673 attribute \src "libresoc.v:183624.5-183624.29" switch \initial attribute \src "libresoc.v:183624.9-183624.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" switch \r27__ren attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign $1\wr_detect$13[0:0]$11673 $4\wr_detect$13[0:0]$11676 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\wr_detect$13[0:0]$11674 1'1 case assign $2\wr_detect$13[0:0]$11674 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\wr_detect$13[0:0]$11675 1'1 case assign $3\wr_detect$13[0:0]$11675 $2\wr_detect$13[0:0]$11674 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\wr_detect$13[0:0]$11676 1'1 case assign $4\wr_detect$13[0:0]$11676 $3\wr_detect$13[0:0]$11675 end case assign $1\wr_detect$13[0:0]$11673 1'0 end sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11672 end connect \$9 $not$libresoc.v:183259$11595_Y connect \$12 $not$libresoc.v:183260$11596_Y connect \$1 $not$libresoc.v:183261$11597_Y connect \$3 $not$libresoc.v:183262$11598_Y connect \$6 $not$libresoc.v:183263$11599_Y end attribute \src "libresoc.v:183657.1-183715.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l attribute \src "libresoc.v:183658.7-183658.20" wire $0\initial[0:0] attribute \src "libresoc.v:183703.3-183711.6" wire width 5 $0\q_int$next[4:0]$11694 attribute \src "libresoc.v:183701.3-183702.27" wire width 5 $0\q_int[4:0] attribute \src "libresoc.v:183703.3-183711.6" wire width 5 $1\q_int$next[4:0]$11695 attribute \src "libresoc.v:183680.13-183680.26" wire width 5 $1\q_int[4:0] attribute \src "libresoc.v:183693.17-183693.96" wire width 5 $and$libresoc.v:183693$11684_Y attribute \src "libresoc.v:183698.17-183698.96" wire width 5 $and$libresoc.v:183698$11689_Y attribute \src "libresoc.v:183695.18-183695.93" wire width 5 $not$libresoc.v:183695$11686_Y attribute \src "libresoc.v:183697.17-183697.92" wire width 5 $not$libresoc.v:183697$11688_Y attribute \src "libresoc.v:183700.17-183700.92" wire width 5 $not$libresoc.v:183700$11691_Y attribute \src "libresoc.v:183694.18-183694.98" wire width 5 $or$libresoc.v:183694$11685_Y attribute \src "libresoc.v:183696.18-183696.99" wire width 5 $or$libresoc.v:183696$11687_Y attribute \src "libresoc.v:183699.17-183699.97" wire width 5 $or$libresoc.v:183699$11690_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 5 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 5 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:183658.7-183658.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 5 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:183693$11684 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:183693$11684_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:183698$11689 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:183698$11689_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:183695$11686 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req connect \Y $not$libresoc.v:183695$11686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:183697$11688 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req connect \Y $not$libresoc.v:183697$11688_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:183700$11691 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req connect \Y $not$libresoc.v:183700$11691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:183694$11685 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:183694$11685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:183696$11687 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:183696$11687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:183699$11690 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:183699$11690_Y end attribute \src "libresoc.v:183658.7-183658.20" process $proc$libresoc.v:183658$11696 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:183680.13-183680.26" process $proc$libresoc.v:183680$11697 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end attribute \src "libresoc.v:183701.3-183702.27" process $proc$libresoc.v:183701$11692 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end attribute \src "libresoc.v:183703.3-183711.6" process $proc$libresoc.v:183703$11693 assign { } { } assign { } { } assign $0\q_int$next[4:0]$11694 $1\q_int$next[4:0]$11695 attribute \src "libresoc.v:183704.5-183704.29" switch \initial attribute \src "libresoc.v:183704.9-183704.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[4:0]$11695 5'00000 case assign $1\q_int$next[4:0]$11695 \$5 end sync always update \q_int$next $0\q_int$next[4:0]$11694 end connect \$9 $and$libresoc.v:183693$11684_Y connect \$11 $or$libresoc.v:183694$11685_Y connect \$13 $not$libresoc.v:183695$11686_Y connect \$15 $or$libresoc.v:183696$11687_Y connect \$1 $not$libresoc.v:183697$11688_Y connect \$3 $and$libresoc.v:183698$11689_Y connect \$5 $or$libresoc.v:183699$11690_Y connect \$7 $not$libresoc.v:183700$11691_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:183719.1-183777.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 attribute \src "libresoc.v:183720.7-183720.20" wire $0\initial[0:0] attribute \src "libresoc.v:183765.3-183773.6" wire width 4 $0\q_int$next[3:0]$11708 attribute \src "libresoc.v:183763.3-183764.27" wire width 4 $0\q_int[3:0] attribute \src "libresoc.v:183765.3-183773.6" wire width 4 $1\q_int$next[3:0]$11709 attribute \src "libresoc.v:183742.13-183742.25" wire width 4 $1\q_int[3:0] attribute \src "libresoc.v:183755.17-183755.96" wire width 4 $and$libresoc.v:183755$11698_Y attribute \src "libresoc.v:183760.17-183760.96" wire width 4 $and$libresoc.v:183760$11703_Y attribute \src "libresoc.v:183757.18-183757.93" wire width 4 $not$libresoc.v:183757$11700_Y attribute \src "libresoc.v:183759.17-183759.92" wire width 4 $not$libresoc.v:183759$11702_Y attribute \src "libresoc.v:183762.17-183762.92" wire width 4 $not$libresoc.v:183762$11705_Y attribute \src "libresoc.v:183756.18-183756.98" wire width 4 $or$libresoc.v:183756$11699_Y attribute \src "libresoc.v:183758.18-183758.99" wire width 4 $or$libresoc.v:183758$11701_Y attribute \src "libresoc.v:183761.17-183761.97" wire width 4 $or$libresoc.v:183761$11704_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:183720.7-183720.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:183755$11698 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:183755$11698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:183760$11703 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:183760$11703_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:183757$11700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req connect \Y $not$libresoc.v:183757$11700_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:183759$11702 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req connect \Y $not$libresoc.v:183759$11702_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:183762$11705 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req connect \Y $not$libresoc.v:183762$11705_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:183756$11699 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:183756$11699_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:183758$11701 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:183758$11701_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:183761$11704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:183761$11704_Y end attribute \src "libresoc.v:183720.7-183720.20" process $proc$libresoc.v:183720$11710 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:183742.13-183742.25" process $proc$libresoc.v:183742$11711 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end attribute \src "libresoc.v:183763.3-183764.27" process $proc$libresoc.v:183763$11706 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end attribute \src "libresoc.v:183765.3-183773.6" process $proc$libresoc.v:183765$11707 assign { } { } assign { } { } assign $0\q_int$next[3:0]$11708 $1\q_int$next[3:0]$11709 attribute \src "libresoc.v:183766.5-183766.29" switch \initial attribute \src "libresoc.v:183766.9-183766.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[3:0]$11709 4'0000 case assign $1\q_int$next[3:0]$11709 \$5 end sync always update \q_int$next $0\q_int$next[3:0]$11708 end connect \$9 $and$libresoc.v:183755$11698_Y connect \$11 $or$libresoc.v:183756$11699_Y connect \$13 $not$libresoc.v:183757$11700_Y connect \$15 $or$libresoc.v:183758$11701_Y connect \$1 $not$libresoc.v:183759$11702_Y connect \$3 $and$libresoc.v:183760$11703_Y connect \$5 $or$libresoc.v:183761$11704_Y connect \$7 $not$libresoc.v:183762$11705_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:183781.1-183839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 attribute \src "libresoc.v:183782.7-183782.20" wire $0\initial[0:0] attribute \src "libresoc.v:183827.3-183835.6" wire width 3 $0\q_int$next[2:0]$11722 attribute \src "libresoc.v:183825.3-183826.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:183827.3-183835.6" wire width 3 $1\q_int$next[2:0]$11723 attribute \src "libresoc.v:183804.13-183804.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:183817.17-183817.96" wire width 3 $and$libresoc.v:183817$11712_Y attribute \src "libresoc.v:183822.17-183822.96" wire width 3 $and$libresoc.v:183822$11717_Y attribute \src "libresoc.v:183819.18-183819.93" wire width 3 $not$libresoc.v:183819$11714_Y attribute \src "libresoc.v:183821.17-183821.92" wire width 3 $not$libresoc.v:183821$11716_Y attribute \src "libresoc.v:183824.17-183824.92" wire width 3 $not$libresoc.v:183824$11719_Y attribute \src "libresoc.v:183818.18-183818.98" wire width 3 $or$libresoc.v:183818$11713_Y attribute \src "libresoc.v:183820.18-183820.99" wire width 3 $or$libresoc.v:183820$11715_Y attribute \src "libresoc.v:183823.17-183823.97" wire width 3 $or$libresoc.v:183823$11718_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:183782.7-183782.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:183817$11712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:183817$11712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:183822$11717 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:183822$11717_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:183819$11714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req connect \Y $not$libresoc.v:183819$11714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:183821$11716 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req connect \Y $not$libresoc.v:183821$11716_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:183824$11719 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req connect \Y $not$libresoc.v:183824$11719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:183818$11713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:183818$11713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:183820$11715 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:183820$11715_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:183823$11718 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:183823$11718_Y end attribute \src "libresoc.v:183782.7-183782.20" process $proc$libresoc.v:183782$11724 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:183804.13-183804.25" process $proc$libresoc.v:183804$11725 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:183825.3-183826.27" process $proc$libresoc.v:183825$11720 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:183827.3-183835.6" process $proc$libresoc.v:183827$11721 assign { } { } assign { } { } assign $0\q_int$next[2:0]$11722 $1\q_int$next[2:0]$11723 attribute \src "libresoc.v:183828.5-183828.29" switch \initial attribute \src "libresoc.v:183828.9-183828.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$11723 3'000 case assign $1\q_int$next[2:0]$11723 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$11722 end connect \$9 $and$libresoc.v:183817$11712_Y connect \$11 $or$libresoc.v:183818$11713_Y connect \$13 $not$libresoc.v:183819$11714_Y connect \$15 $or$libresoc.v:183820$11715_Y connect \$1 $not$libresoc.v:183821$11716_Y connect \$3 $and$libresoc.v:183822$11717_Y connect \$5 $or$libresoc.v:183823$11718_Y connect \$7 $not$libresoc.v:183824$11719_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:183843.1-183901.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 attribute \src "libresoc.v:183844.7-183844.20" wire $0\initial[0:0] attribute \src "libresoc.v:183889.3-183897.6" wire width 3 $0\q_int$next[2:0]$11736 attribute \src "libresoc.v:183887.3-183888.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:183889.3-183897.6" wire width 3 $1\q_int$next[2:0]$11737 attribute \src "libresoc.v:183866.13-183866.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:183879.17-183879.96" wire width 3 $and$libresoc.v:183879$11726_Y attribute \src "libresoc.v:183884.17-183884.96" wire width 3 $and$libresoc.v:183884$11731_Y attribute \src "libresoc.v:183881.18-183881.93" wire width 3 $not$libresoc.v:183881$11728_Y attribute \src "libresoc.v:183883.17-183883.92" wire width 3 $not$libresoc.v:183883$11730_Y attribute \src "libresoc.v:183886.17-183886.92" wire width 3 $not$libresoc.v:183886$11733_Y attribute \src "libresoc.v:183880.18-183880.98" wire width 3 $or$libresoc.v:183880$11727_Y attribute \src "libresoc.v:183882.18-183882.99" wire width 3 $or$libresoc.v:183882$11729_Y attribute \src "libresoc.v:183885.17-183885.97" wire width 3 $or$libresoc.v:183885$11732_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:183844.7-183844.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:183879$11726 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:183879$11726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:183884$11731 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:183884$11731_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:183881$11728 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req connect \Y $not$libresoc.v:183881$11728_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:183883$11730 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req connect \Y $not$libresoc.v:183883$11730_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:183886$11733 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req connect \Y $not$libresoc.v:183886$11733_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:183880$11727 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:183880$11727_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:183882$11729 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:183882$11729_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:183885$11732 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:183885$11732_Y end attribute \src "libresoc.v:183844.7-183844.20" process $proc$libresoc.v:183844$11738 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:183866.13-183866.25" process $proc$libresoc.v:183866$11739 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:183887.3-183888.27" process $proc$libresoc.v:183887$11734 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:183889.3-183897.6" process $proc$libresoc.v:183889$11735 assign { } { } assign { } { } assign $0\q_int$next[2:0]$11736 $1\q_int$next[2:0]$11737 attribute \src "libresoc.v:183890.5-183890.29" switch \initial attribute \src "libresoc.v:183890.9-183890.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$11737 3'000 case assign $1\q_int$next[2:0]$11737 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$11736 end connect \$9 $and$libresoc.v:183879$11726_Y connect \$11 $or$libresoc.v:183880$11727_Y connect \$13 $not$libresoc.v:183881$11728_Y connect \$15 $or$libresoc.v:183882$11729_Y connect \$1 $not$libresoc.v:183883$11730_Y connect \$3 $and$libresoc.v:183884$11731_Y connect \$5 $or$libresoc.v:183885$11732_Y connect \$7 $not$libresoc.v:183886$11733_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:183905.1-183963.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 attribute \src "libresoc.v:183906.7-183906.20" wire $0\initial[0:0] attribute \src "libresoc.v:183951.3-183959.6" wire width 3 $0\q_int$next[2:0]$11750 attribute \src "libresoc.v:183949.3-183950.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:183951.3-183959.6" wire width 3 $1\q_int$next[2:0]$11751 attribute \src "libresoc.v:183928.13-183928.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:183941.17-183941.96" wire width 3 $and$libresoc.v:183941$11740_Y attribute \src "libresoc.v:183946.17-183946.96" wire width 3 $and$libresoc.v:183946$11745_Y attribute \src "libresoc.v:183943.18-183943.93" wire width 3 $not$libresoc.v:183943$11742_Y attribute \src "libresoc.v:183945.17-183945.92" wire width 3 $not$libresoc.v:183945$11744_Y attribute \src "libresoc.v:183948.17-183948.92" wire width 3 $not$libresoc.v:183948$11747_Y attribute \src "libresoc.v:183942.18-183942.98" wire width 3 $or$libresoc.v:183942$11741_Y attribute \src "libresoc.v:183944.18-183944.99" wire width 3 $or$libresoc.v:183944$11743_Y attribute \src "libresoc.v:183947.17-183947.97" wire width 3 $or$libresoc.v:183947$11746_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:183906.7-183906.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:183941$11740 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:183941$11740_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:183946$11745 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:183946$11745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:183943$11742 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req connect \Y $not$libresoc.v:183943$11742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:183945$11744 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req connect \Y $not$libresoc.v:183945$11744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:183948$11747 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req connect \Y $not$libresoc.v:183948$11747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:183942$11741 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:183942$11741_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:183944$11743 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:183944$11743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:183947$11746 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:183947$11746_Y end attribute \src "libresoc.v:183906.7-183906.20" process $proc$libresoc.v:183906$11752 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:183928.13-183928.25" process $proc$libresoc.v:183928$11753 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:183949.3-183950.27" process $proc$libresoc.v:183949$11748 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:183951.3-183959.6" process $proc$libresoc.v:183951$11749 assign { } { } assign { } { } assign $0\q_int$next[2:0]$11750 $1\q_int$next[2:0]$11751 attribute \src "libresoc.v:183952.5-183952.29" switch \initial attribute \src "libresoc.v:183952.9-183952.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$11751 3'000 case assign $1\q_int$next[2:0]$11751 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$11750 end connect \$9 $and$libresoc.v:183941$11740_Y connect \$11 $or$libresoc.v:183942$11741_Y connect \$13 $not$libresoc.v:183943$11742_Y connect \$15 $or$libresoc.v:183944$11743_Y connect \$1 $not$libresoc.v:183945$11744_Y connect \$3 $and$libresoc.v:183946$11745_Y connect \$5 $or$libresoc.v:183947$11746_Y connect \$7 $not$libresoc.v:183948$11747_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:183967.1-184025.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 attribute \src "libresoc.v:183968.7-183968.20" wire $0\initial[0:0] attribute \src "libresoc.v:184013.3-184021.6" wire width 5 $0\q_int$next[4:0]$11764 attribute \src "libresoc.v:184011.3-184012.27" wire width 5 $0\q_int[4:0] attribute \src "libresoc.v:184013.3-184021.6" wire width 5 $1\q_int$next[4:0]$11765 attribute \src "libresoc.v:183990.13-183990.26" wire width 5 $1\q_int[4:0] attribute \src "libresoc.v:184003.17-184003.96" wire width 5 $and$libresoc.v:184003$11754_Y attribute \src "libresoc.v:184008.17-184008.96" wire width 5 $and$libresoc.v:184008$11759_Y attribute \src "libresoc.v:184005.18-184005.93" wire width 5 $not$libresoc.v:184005$11756_Y attribute \src "libresoc.v:184007.17-184007.92" wire width 5 $not$libresoc.v:184007$11758_Y attribute \src "libresoc.v:184010.17-184010.92" wire width 5 $not$libresoc.v:184010$11761_Y attribute \src "libresoc.v:184004.18-184004.98" wire width 5 $or$libresoc.v:184004$11755_Y attribute \src "libresoc.v:184006.18-184006.99" wire width 5 $or$libresoc.v:184006$11757_Y attribute \src "libresoc.v:184009.17-184009.97" wire width 5 $or$libresoc.v:184009$11760_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 5 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 5 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:183968.7-183968.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 5 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:184003$11754 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:184003$11754_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:184008$11759 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:184008$11759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:184005$11756 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req connect \Y $not$libresoc.v:184005$11756_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:184007$11758 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req connect \Y $not$libresoc.v:184007$11758_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:184010$11761 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req connect \Y $not$libresoc.v:184010$11761_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:184004$11755 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:184004$11755_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:184006$11757 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:184006$11757_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:184009$11760 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:184009$11760_Y end attribute \src "libresoc.v:183968.7-183968.20" process $proc$libresoc.v:183968$11766 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:183990.13-183990.26" process $proc$libresoc.v:183990$11767 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end attribute \src "libresoc.v:184011.3-184012.27" process $proc$libresoc.v:184011$11762 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end attribute \src "libresoc.v:184013.3-184021.6" process $proc$libresoc.v:184013$11763 assign { } { } assign { } { } assign $0\q_int$next[4:0]$11764 $1\q_int$next[4:0]$11765 attribute \src "libresoc.v:184014.5-184014.29" switch \initial attribute \src "libresoc.v:184014.9-184014.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[4:0]$11765 5'00000 case assign $1\q_int$next[4:0]$11765 \$5 end sync always update \q_int$next $0\q_int$next[4:0]$11764 end connect \$9 $and$libresoc.v:184003$11754_Y connect \$11 $or$libresoc.v:184004$11755_Y connect \$13 $not$libresoc.v:184005$11756_Y connect \$15 $or$libresoc.v:184006$11757_Y connect \$1 $not$libresoc.v:184007$11758_Y connect \$3 $and$libresoc.v:184008$11759_Y connect \$5 $or$libresoc.v:184009$11760_Y connect \$7 $not$libresoc.v:184010$11761_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:184029.1-184087.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 attribute \src "libresoc.v:184030.7-184030.20" wire $0\initial[0:0] attribute \src "libresoc.v:184075.3-184083.6" wire width 2 $0\q_int$next[1:0]$11778 attribute \src "libresoc.v:184073.3-184074.27" wire width 2 $0\q_int[1:0] attribute \src "libresoc.v:184075.3-184083.6" wire width 2 $1\q_int$next[1:0]$11779 attribute \src "libresoc.v:184052.13-184052.25" wire width 2 $1\q_int[1:0] attribute \src "libresoc.v:184065.17-184065.96" wire width 2 $and$libresoc.v:184065$11768_Y attribute \src "libresoc.v:184070.17-184070.96" wire width 2 $and$libresoc.v:184070$11773_Y attribute \src "libresoc.v:184067.18-184067.93" wire width 2 $not$libresoc.v:184067$11770_Y attribute \src "libresoc.v:184069.17-184069.92" wire width 2 $not$libresoc.v:184069$11772_Y attribute \src "libresoc.v:184072.17-184072.92" wire width 2 $not$libresoc.v:184072$11775_Y attribute \src "libresoc.v:184066.18-184066.98" wire width 2 $or$libresoc.v:184066$11769_Y attribute \src "libresoc.v:184068.18-184068.99" wire width 2 $or$libresoc.v:184068$11771_Y attribute \src "libresoc.v:184071.17-184071.97" wire width 2 $or$libresoc.v:184071$11774_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 2 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 2 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:184030.7-184030.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 2 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 2 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 2 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:184065$11768 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:184065$11768_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:184070$11773 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:184070$11773_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:184067$11770 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req connect \Y $not$libresoc.v:184067$11770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:184069$11772 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req connect \Y $not$libresoc.v:184069$11772_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:184072$11775 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req connect \Y $not$libresoc.v:184072$11775_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:184066$11769 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:184066$11769_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:184068$11771 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:184068$11771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:184071$11774 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:184071$11774_Y end attribute \src "libresoc.v:184030.7-184030.20" process $proc$libresoc.v:184030$11780 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184052.13-184052.25" process $proc$libresoc.v:184052$11781 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end attribute \src "libresoc.v:184073.3-184074.27" process $proc$libresoc.v:184073$11776 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end attribute \src "libresoc.v:184075.3-184083.6" process $proc$libresoc.v:184075$11777 assign { } { } assign { } { } assign $0\q_int$next[1:0]$11778 $1\q_int$next[1:0]$11779 attribute \src "libresoc.v:184076.5-184076.29" switch \initial attribute \src "libresoc.v:184076.9-184076.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[1:0]$11779 2'00 case assign $1\q_int$next[1:0]$11779 \$5 end sync always update \q_int$next $0\q_int$next[1:0]$11778 end connect \$9 $and$libresoc.v:184065$11768_Y connect \$11 $or$libresoc.v:184066$11769_Y connect \$13 $not$libresoc.v:184067$11770_Y connect \$15 $or$libresoc.v:184068$11771_Y connect \$1 $not$libresoc.v:184069$11772_Y connect \$3 $and$libresoc.v:184070$11773_Y connect \$5 $or$libresoc.v:184071$11774_Y connect \$7 $not$libresoc.v:184072$11775_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:184091.1-184149.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 attribute \src "libresoc.v:184092.7-184092.20" wire $0\initial[0:0] attribute \src "libresoc.v:184137.3-184145.6" wire width 6 $0\q_int$next[5:0]$11792 attribute \src "libresoc.v:184135.3-184136.27" wire width 6 $0\q_int[5:0] attribute \src "libresoc.v:184137.3-184145.6" wire width 6 $1\q_int$next[5:0]$11793 attribute \src "libresoc.v:184114.13-184114.26" wire width 6 $1\q_int[5:0] attribute \src "libresoc.v:184127.17-184127.96" wire width 6 $and$libresoc.v:184127$11782_Y attribute \src "libresoc.v:184132.17-184132.96" wire width 6 $and$libresoc.v:184132$11787_Y attribute \src "libresoc.v:184129.18-184129.93" wire width 6 $not$libresoc.v:184129$11784_Y attribute \src "libresoc.v:184131.17-184131.92" wire width 6 $not$libresoc.v:184131$11786_Y attribute \src "libresoc.v:184134.17-184134.92" wire width 6 $not$libresoc.v:184134$11789_Y attribute \src "libresoc.v:184128.18-184128.98" wire width 6 $or$libresoc.v:184128$11783_Y attribute \src "libresoc.v:184130.18-184130.99" wire width 6 $or$libresoc.v:184130$11785_Y attribute \src "libresoc.v:184133.17-184133.97" wire width 6 $or$libresoc.v:184133$11788_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 6 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 6 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:184092.7-184092.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 6 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:184127$11782 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:184127$11782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:184132$11787 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:184132$11787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:184129$11784 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req connect \Y $not$libresoc.v:184129$11784_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:184131$11786 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req connect \Y $not$libresoc.v:184131$11786_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:184134$11789 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req connect \Y $not$libresoc.v:184134$11789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:184128$11783 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:184128$11783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:184130$11785 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:184130$11785_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:184133$11788 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:184133$11788_Y end attribute \src "libresoc.v:184092.7-184092.20" process $proc$libresoc.v:184092$11794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184114.13-184114.26" process $proc$libresoc.v:184114$11795 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end attribute \src "libresoc.v:184135.3-184136.27" process $proc$libresoc.v:184135$11790 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end attribute \src "libresoc.v:184137.3-184145.6" process $proc$libresoc.v:184137$11791 assign { } { } assign { } { } assign $0\q_int$next[5:0]$11792 $1\q_int$next[5:0]$11793 attribute \src "libresoc.v:184138.5-184138.29" switch \initial attribute \src "libresoc.v:184138.9-184138.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[5:0]$11793 6'000000 case assign $1\q_int$next[5:0]$11793 \$5 end sync always update \q_int$next $0\q_int$next[5:0]$11792 end connect \$9 $and$libresoc.v:184127$11782_Y connect \$11 $or$libresoc.v:184128$11783_Y connect \$13 $not$libresoc.v:184129$11784_Y connect \$15 $or$libresoc.v:184130$11785_Y connect \$1 $not$libresoc.v:184131$11786_Y connect \$3 $and$libresoc.v:184132$11787_Y connect \$5 $or$libresoc.v:184133$11788_Y connect \$7 $not$libresoc.v:184134$11789_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:184153.1-184211.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 attribute \src "libresoc.v:184154.7-184154.20" wire $0\initial[0:0] attribute \src "libresoc.v:184199.3-184207.6" wire width 4 $0\q_int$next[3:0]$11806 attribute \src "libresoc.v:184197.3-184198.27" wire width 4 $0\q_int[3:0] attribute \src "libresoc.v:184199.3-184207.6" wire width 4 $1\q_int$next[3:0]$11807 attribute \src "libresoc.v:184176.13-184176.25" wire width 4 $1\q_int[3:0] attribute \src "libresoc.v:184189.17-184189.96" wire width 4 $and$libresoc.v:184189$11796_Y attribute \src "libresoc.v:184194.17-184194.96" wire width 4 $and$libresoc.v:184194$11801_Y attribute \src "libresoc.v:184191.18-184191.93" wire width 4 $not$libresoc.v:184191$11798_Y attribute \src "libresoc.v:184193.17-184193.92" wire width 4 $not$libresoc.v:184193$11800_Y attribute \src "libresoc.v:184196.17-184196.92" wire width 4 $not$libresoc.v:184196$11803_Y attribute \src "libresoc.v:184190.18-184190.98" wire width 4 $or$libresoc.v:184190$11797_Y attribute \src "libresoc.v:184192.18-184192.99" wire width 4 $or$libresoc.v:184192$11799_Y attribute \src "libresoc.v:184195.17-184195.97" wire width 4 $or$libresoc.v:184195$11802_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:184154.7-184154.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:184189$11796 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:184189$11796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:184194$11801 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:184194$11801_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:184191$11798 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req connect \Y $not$libresoc.v:184191$11798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:184193$11800 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req connect \Y $not$libresoc.v:184193$11800_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:184196$11803 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req connect \Y $not$libresoc.v:184196$11803_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:184190$11797 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req connect \Y $or$libresoc.v:184190$11797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:184192$11799 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int connect \Y $or$libresoc.v:184192$11799_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:184195$11802 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req connect \Y $or$libresoc.v:184195$11802_Y end attribute \src "libresoc.v:184154.7-184154.20" process $proc$libresoc.v:184154$11808 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184176.13-184176.25" process $proc$libresoc.v:184176$11809 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end attribute \src "libresoc.v:184197.3-184198.27" process $proc$libresoc.v:184197$11804 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end attribute \src "libresoc.v:184199.3-184207.6" process $proc$libresoc.v:184199$11805 assign { } { } assign { } { } assign $0\q_int$next[3:0]$11806 $1\q_int$next[3:0]$11807 attribute \src "libresoc.v:184200.5-184200.29" switch \initial attribute \src "libresoc.v:184200.9-184200.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[3:0]$11807 4'0000 case assign $1\q_int$next[3:0]$11807 \$5 end sync always update \q_int$next $0\q_int$next[3:0]$11806 end connect \$9 $and$libresoc.v:184189$11796_Y connect \$11 $or$libresoc.v:184190$11797_Y connect \$13 $not$libresoc.v:184191$11798_Y connect \$15 $or$libresoc.v:184192$11799_Y connect \$1 $not$libresoc.v:184193$11800_Y connect \$3 $and$libresoc.v:184194$11801_Y connect \$5 $or$libresoc.v:184195$11802_Y connect \$7 $not$libresoc.v:184196$11803_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end attribute \src "libresoc.v:184215.1-184264.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l attribute \src "libresoc.v:184216.7-184216.20" wire $0\initial[0:0] attribute \src "libresoc.v:184252.3-184260.6" wire $0\q_int$next[0:0]$11817 attribute \src "libresoc.v:184250.3-184251.27" wire $0\q_int[0:0] attribute \src "libresoc.v:184252.3-184260.6" wire $1\q_int$next[0:0]$11818 attribute \src "libresoc.v:184232.7-184232.19" wire $1\q_int[0:0] attribute \src "libresoc.v:184247.17-184247.96" wire $and$libresoc.v:184247$11812_Y attribute \src "libresoc.v:184246.17-184246.94" wire $not$libresoc.v:184246$11811_Y attribute \src "libresoc.v:184249.17-184249.94" wire $not$libresoc.v:184249$11814_Y attribute \src "libresoc.v:184245.17-184245.100" wire $or$libresoc.v:184245$11810_Y attribute \src "libresoc.v:184248.17-184248.99" wire $or$libresoc.v:184248$11813_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:184216.7-184216.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:184247$11812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:184247$11812_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:184246$11811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset connect \Y $not$libresoc.v:184246$11811_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:184249$11814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset connect \Y $not$libresoc.v:184249$11814_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:184245$11810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int connect \Y $or$libresoc.v:184245$11810_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:184248$11813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset connect \Y $or$libresoc.v:184248$11813_Y end attribute \src "libresoc.v:184216.7-184216.20" process $proc$libresoc.v:184216$11819 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184232.7-184232.19" process $proc$libresoc.v:184232$11820 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:184250.3-184251.27" process $proc$libresoc.v:184250$11815 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:184252.3-184260.6" process $proc$libresoc.v:184252$11816 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11817 $1\q_int$next[0:0]$11818 attribute \src "libresoc.v:184253.5-184253.29" switch \initial attribute \src "libresoc.v:184253.9-184253.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11818 1'0 case assign $1\q_int$next[0:0]$11818 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11817 end connect \$9 $or$libresoc.v:184245$11810_Y connect \$1 $not$libresoc.v:184246$11811_Y connect \$3 $and$libresoc.v:184247$11812_Y connect \$5 $or$libresoc.v:184248$11813_Y connect \$7 $not$libresoc.v:184249$11814_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end attribute \src "libresoc.v:184268.1-184317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 attribute \src "libresoc.v:184269.7-184269.20" wire $0\initial[0:0] attribute \src "libresoc.v:184305.3-184313.6" wire $0\q_int$next[0:0]$11828 attribute \src "libresoc.v:184303.3-184304.27" wire $0\q_int[0:0] attribute \src "libresoc.v:184305.3-184313.6" wire $1\q_int$next[0:0]$11829 attribute \src "libresoc.v:184285.7-184285.19" wire $1\q_int[0:0] attribute \src "libresoc.v:184300.17-184300.96" wire $and$libresoc.v:184300$11823_Y attribute \src "libresoc.v:184299.17-184299.94" wire $not$libresoc.v:184299$11822_Y attribute \src "libresoc.v:184302.17-184302.94" wire $not$libresoc.v:184302$11825_Y attribute \src "libresoc.v:184298.17-184298.100" wire $or$libresoc.v:184298$11821_Y attribute \src "libresoc.v:184301.17-184301.99" wire $or$libresoc.v:184301$11824_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:184269.7-184269.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:184300$11823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:184300$11823_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:184299$11822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset connect \Y $not$libresoc.v:184299$11822_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:184302$11825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset connect \Y $not$libresoc.v:184302$11825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:184298$11821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int connect \Y $or$libresoc.v:184298$11821_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:184301$11824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset connect \Y $or$libresoc.v:184301$11824_Y end attribute \src "libresoc.v:184269.7-184269.20" process $proc$libresoc.v:184269$11830 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184285.7-184285.19" process $proc$libresoc.v:184285$11831 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:184303.3-184304.27" process $proc$libresoc.v:184303$11826 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:184305.3-184313.6" process $proc$libresoc.v:184305$11827 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11828 $1\q_int$next[0:0]$11829 attribute \src "libresoc.v:184306.5-184306.29" switch \initial attribute \src "libresoc.v:184306.9-184306.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11829 1'0 case assign $1\q_int$next[0:0]$11829 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11828 end connect \$9 $or$libresoc.v:184298$11821_Y connect \$1 $not$libresoc.v:184299$11822_Y connect \$3 $and$libresoc.v:184300$11823_Y connect \$5 $or$libresoc.v:184301$11824_Y connect \$7 $not$libresoc.v:184302$11825_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end attribute \src "libresoc.v:184321.1-184908.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask attribute \src "libresoc.v:184322.7-184322.20" wire $0\initial[0:0] attribute \src "libresoc.v:184520.3-184907.6" wire width 64 $0\mask[63:0] attribute \src "libresoc.v:184520.3-184907.6" wire $10\mask[9:9] attribute \src "libresoc.v:184520.3-184907.6" wire $11\mask[10:10] attribute \src "libresoc.v:184520.3-184907.6" wire $12\mask[11:11] attribute \src "libresoc.v:184520.3-184907.6" wire $13\mask[12:12] attribute \src "libresoc.v:184520.3-184907.6" wire $14\mask[13:13] attribute \src "libresoc.v:184520.3-184907.6" wire $15\mask[14:14] attribute \src "libresoc.v:184520.3-184907.6" wire $16\mask[15:15] attribute \src "libresoc.v:184520.3-184907.6" wire $17\mask[16:16] attribute \src "libresoc.v:184520.3-184907.6" wire $18\mask[17:17] attribute \src "libresoc.v:184520.3-184907.6" wire $19\mask[18:18] attribute \src "libresoc.v:184520.3-184907.6" wire $1\mask[0:0] attribute \src "libresoc.v:184520.3-184907.6" wire $20\mask[19:19] attribute \src "libresoc.v:184520.3-184907.6" wire $21\mask[20:20] attribute \src "libresoc.v:184520.3-184907.6" wire $22\mask[21:21] attribute \src "libresoc.v:184520.3-184907.6" wire $23\mask[22:22] attribute \src "libresoc.v:184520.3-184907.6" wire $24\mask[23:23] attribute \src "libresoc.v:184520.3-184907.6" wire $25\mask[24:24] attribute \src "libresoc.v:184520.3-184907.6" wire $26\mask[25:25] attribute \src "libresoc.v:184520.3-184907.6" wire $27\mask[26:26] attribute \src "libresoc.v:184520.3-184907.6" wire $28\mask[27:27] attribute \src "libresoc.v:184520.3-184907.6" wire $29\mask[28:28] attribute \src "libresoc.v:184520.3-184907.6" wire $2\mask[1:1] attribute \src "libresoc.v:184520.3-184907.6" wire $30\mask[29:29] attribute \src "libresoc.v:184520.3-184907.6" wire $31\mask[30:30] attribute \src "libresoc.v:184520.3-184907.6" wire $32\mask[31:31] attribute \src "libresoc.v:184520.3-184907.6" wire $33\mask[32:32] attribute \src "libresoc.v:184520.3-184907.6" wire $34\mask[33:33] attribute \src "libresoc.v:184520.3-184907.6" wire $35\mask[34:34] attribute \src "libresoc.v:184520.3-184907.6" wire $36\mask[35:35] attribute \src "libresoc.v:184520.3-184907.6" wire $37\mask[36:36] attribute \src "libresoc.v:184520.3-184907.6" wire $38\mask[37:37] attribute \src "libresoc.v:184520.3-184907.6" wire $39\mask[38:38] attribute \src "libresoc.v:184520.3-184907.6" wire $3\mask[2:2] attribute \src "libresoc.v:184520.3-184907.6" wire $40\mask[39:39] attribute \src "libresoc.v:184520.3-184907.6" wire $41\mask[40:40] attribute \src "libresoc.v:184520.3-184907.6" wire $42\mask[41:41] attribute \src "libresoc.v:184520.3-184907.6" wire $43\mask[42:42] attribute \src "libresoc.v:184520.3-184907.6" wire $44\mask[43:43] attribute \src "libresoc.v:184520.3-184907.6" wire $45\mask[44:44] attribute \src "libresoc.v:184520.3-184907.6" wire $46\mask[45:45] attribute \src "libresoc.v:184520.3-184907.6" wire $47\mask[46:46] attribute \src "libresoc.v:184520.3-184907.6" wire $48\mask[47:47] attribute \src "libresoc.v:184520.3-184907.6" wire $49\mask[48:48] attribute \src "libresoc.v:184520.3-184907.6" wire $4\mask[3:3] attribute \src "libresoc.v:184520.3-184907.6" wire $50\mask[49:49] attribute \src "libresoc.v:184520.3-184907.6" wire $51\mask[50:50] attribute \src "libresoc.v:184520.3-184907.6" wire $52\mask[51:51] attribute \src "libresoc.v:184520.3-184907.6" wire $53\mask[52:52] attribute \src "libresoc.v:184520.3-184907.6" wire $54\mask[53:53] attribute \src "libresoc.v:184520.3-184907.6" wire $55\mask[54:54] attribute \src "libresoc.v:184520.3-184907.6" wire $56\mask[55:55] attribute \src "libresoc.v:184520.3-184907.6" wire $57\mask[56:56] attribute \src "libresoc.v:184520.3-184907.6" wire $58\mask[57:57] attribute \src "libresoc.v:184520.3-184907.6" wire $59\mask[58:58] attribute \src "libresoc.v:184520.3-184907.6" wire $5\mask[4:4] attribute \src "libresoc.v:184520.3-184907.6" wire $60\mask[59:59] attribute \src "libresoc.v:184520.3-184907.6" wire $61\mask[60:60] attribute \src "libresoc.v:184520.3-184907.6" wire $62\mask[61:61] attribute \src "libresoc.v:184520.3-184907.6" wire $63\mask[62:62] attribute \src "libresoc.v:184520.3-184907.6" wire $64\mask[63:63] attribute \src "libresoc.v:184520.3-184907.6" wire $6\mask[5:5] attribute \src "libresoc.v:184520.3-184907.6" wire $7\mask[6:6] attribute \src "libresoc.v:184520.3-184907.6" wire $8\mask[7:7] attribute \src "libresoc.v:184520.3-184907.6" wire $9\mask[8:8] attribute \src "libresoc.v:184456.17-184456.96" wire $gt$libresoc.v:184456$11832_Y attribute \src "libresoc.v:184457.18-184457.98" wire $gt$libresoc.v:184457$11833_Y attribute \src "libresoc.v:184458.19-184458.99" wire $gt$libresoc.v:184458$11834_Y attribute \src "libresoc.v:184459.19-184459.99" wire $gt$libresoc.v:184459$11835_Y attribute \src "libresoc.v:184460.19-184460.99" wire $gt$libresoc.v:184460$11836_Y attribute \src "libresoc.v:184461.19-184461.99" wire $gt$libresoc.v:184461$11837_Y attribute \src "libresoc.v:184462.19-184462.99" wire $gt$libresoc.v:184462$11838_Y attribute \src "libresoc.v:184463.19-184463.99" wire $gt$libresoc.v:184463$11839_Y attribute \src "libresoc.v:184464.19-184464.99" wire $gt$libresoc.v:184464$11840_Y attribute \src "libresoc.v:184465.19-184465.99" wire $gt$libresoc.v:184465$11841_Y attribute \src "libresoc.v:184466.19-184466.99" wire $gt$libresoc.v:184466$11842_Y attribute \src "libresoc.v:184467.18-184467.97" wire $gt$libresoc.v:184467$11843_Y attribute \src "libresoc.v:184468.19-184468.99" wire $gt$libresoc.v:184468$11844_Y attribute \src "libresoc.v:184469.19-184469.99" wire $gt$libresoc.v:184469$11845_Y attribute \src "libresoc.v:184470.19-184470.99" wire $gt$libresoc.v:184470$11846_Y attribute \src "libresoc.v:184471.19-184471.99" wire $gt$libresoc.v:184471$11847_Y attribute \src "libresoc.v:184472.19-184472.99" wire $gt$libresoc.v:184472$11848_Y attribute \src "libresoc.v:184473.18-184473.97" wire $gt$libresoc.v:184473$11849_Y attribute \src "libresoc.v:184474.18-184474.97" wire $gt$libresoc.v:184474$11850_Y attribute \src "libresoc.v:184475.18-184475.97" wire $gt$libresoc.v:184475$11851_Y attribute \src "libresoc.v:184476.17-184476.96" wire $gt$libresoc.v:184476$11852_Y attribute \src "libresoc.v:184477.18-184477.97" wire $gt$libresoc.v:184477$11853_Y attribute \src "libresoc.v:184478.18-184478.97" wire $gt$libresoc.v:184478$11854_Y attribute \src "libresoc.v:184479.18-184479.97" wire $gt$libresoc.v:184479$11855_Y attribute \src "libresoc.v:184480.18-184480.97" wire $gt$libresoc.v:184480$11856_Y attribute \src "libresoc.v:184481.18-184481.97" wire $gt$libresoc.v:184481$11857_Y attribute \src "libresoc.v:184482.18-184482.97" wire $gt$libresoc.v:184482$11858_Y attribute \src "libresoc.v:184483.18-184483.97" wire $gt$libresoc.v:184483$11859_Y attribute \src "libresoc.v:184484.18-184484.98" wire $gt$libresoc.v:184484$11860_Y attribute \src "libresoc.v:184485.18-184485.98" wire $gt$libresoc.v:184485$11861_Y attribute \src "libresoc.v:184486.18-184486.98" wire $gt$libresoc.v:184486$11862_Y attribute \src "libresoc.v:184487.17-184487.96" wire $gt$libresoc.v:184487$11863_Y attribute \src "libresoc.v:184488.18-184488.98" wire $gt$libresoc.v:184488$11864_Y attribute \src "libresoc.v:184489.18-184489.98" wire $gt$libresoc.v:184489$11865_Y attribute \src "libresoc.v:184490.18-184490.98" wire $gt$libresoc.v:184490$11866_Y attribute \src "libresoc.v:184491.18-184491.98" wire $gt$libresoc.v:184491$11867_Y attribute \src "libresoc.v:184492.18-184492.98" wire $gt$libresoc.v:184492$11868_Y attribute \src "libresoc.v:184493.18-184493.98" wire $gt$libresoc.v:184493$11869_Y attribute \src "libresoc.v:184494.18-184494.98" wire $gt$libresoc.v:184494$11870_Y attribute \src "libresoc.v:184495.18-184495.98" wire $gt$libresoc.v:184495$11871_Y attribute \src "libresoc.v:184496.18-184496.98" wire $gt$libresoc.v:184496$11872_Y attribute \src "libresoc.v:184497.18-184497.98" wire $gt$libresoc.v:184497$11873_Y attribute \src "libresoc.v:184498.17-184498.96" wire $gt$libresoc.v:184498$11874_Y attribute \src "libresoc.v:184499.18-184499.98" wire $gt$libresoc.v:184499$11875_Y attribute \src "libresoc.v:184500.18-184500.98" wire $gt$libresoc.v:184500$11876_Y attribute \src "libresoc.v:184501.18-184501.98" wire $gt$libresoc.v:184501$11877_Y attribute \src "libresoc.v:184502.18-184502.98" wire $gt$libresoc.v:184502$11878_Y attribute \src "libresoc.v:184503.18-184503.98" wire $gt$libresoc.v:184503$11879_Y attribute \src "libresoc.v:184504.18-184504.98" wire $gt$libresoc.v:184504$11880_Y attribute \src "libresoc.v:184505.18-184505.98" wire $gt$libresoc.v:184505$11881_Y attribute \src "libresoc.v:184506.18-184506.98" wire $gt$libresoc.v:184506$11882_Y attribute \src "libresoc.v:184507.18-184507.98" wire $gt$libresoc.v:184507$11883_Y attribute \src "libresoc.v:184508.18-184508.98" wire $gt$libresoc.v:184508$11884_Y attribute \src "libresoc.v:184509.17-184509.96" wire $gt$libresoc.v:184509$11885_Y attribute \src "libresoc.v:184510.18-184510.98" wire $gt$libresoc.v:184510$11886_Y attribute \src "libresoc.v:184511.18-184511.98" wire $gt$libresoc.v:184511$11887_Y attribute \src "libresoc.v:184512.18-184512.98" wire $gt$libresoc.v:184512$11888_Y attribute \src "libresoc.v:184513.18-184513.98" wire $gt$libresoc.v:184513$11889_Y attribute \src "libresoc.v:184514.18-184514.98" wire $gt$libresoc.v:184514$11890_Y attribute \src "libresoc.v:184515.18-184515.98" wire $gt$libresoc.v:184515$11891_Y attribute \src "libresoc.v:184516.18-184516.98" wire $gt$libresoc.v:184516$11892_Y attribute \src "libresoc.v:184517.18-184517.98" wire $gt$libresoc.v:184517$11893_Y attribute \src "libresoc.v:184518.18-184518.98" wire $gt$libresoc.v:184518$11894_Y attribute \src "libresoc.v:184519.18-184519.98" wire $gt$libresoc.v:184519$11895_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$113 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$115 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$35 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$95 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 attribute \src "libresoc.v:184322.7-184322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184456$11832 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 connect \Y $gt$libresoc.v:184456$11832_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184457$11833 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 connect \Y $gt$libresoc.v:184457$11833_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184458$11834 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 connect \Y $gt$libresoc.v:184458$11834_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184459$11835 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 connect \Y $gt$libresoc.v:184459$11835_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184460$11836 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 connect \Y $gt$libresoc.v:184460$11836_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184461$11837 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 connect \Y $gt$libresoc.v:184461$11837_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184462$11838 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 connect \Y $gt$libresoc.v:184462$11838_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184463$11839 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 connect \Y $gt$libresoc.v:184463$11839_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184464$11840 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 connect \Y $gt$libresoc.v:184464$11840_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184465$11841 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 connect \Y $gt$libresoc.v:184465$11841_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184466$11842 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 connect \Y $gt$libresoc.v:184466$11842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184467$11843 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 connect \Y $gt$libresoc.v:184467$11843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184468$11844 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 connect \Y $gt$libresoc.v:184468$11844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184469$11845 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 connect \Y $gt$libresoc.v:184469$11845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184470$11846 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 connect \Y $gt$libresoc.v:184470$11846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184471$11847 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 connect \Y $gt$libresoc.v:184471$11847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184472$11848 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 connect \Y $gt$libresoc.v:184472$11848_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184473$11849 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 connect \Y $gt$libresoc.v:184473$11849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184474$11850 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 connect \Y $gt$libresoc.v:184474$11850_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184475$11851 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 connect \Y $gt$libresoc.v:184475$11851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184476$11852 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 connect \Y $gt$libresoc.v:184476$11852_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184477$11853 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 connect \Y $gt$libresoc.v:184477$11853_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184478$11854 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 connect \Y $gt$libresoc.v:184478$11854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184479$11855 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 connect \Y $gt$libresoc.v:184479$11855_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184480$11856 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 connect \Y $gt$libresoc.v:184480$11856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184481$11857 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 connect \Y $gt$libresoc.v:184481$11857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184482$11858 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 connect \Y $gt$libresoc.v:184482$11858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184483$11859 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 connect \Y $gt$libresoc.v:184483$11859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184484$11860 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 connect \Y $gt$libresoc.v:184484$11860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184485$11861 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 connect \Y $gt$libresoc.v:184485$11861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184486$11862 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 connect \Y $gt$libresoc.v:184486$11862_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184487$11863 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 connect \Y $gt$libresoc.v:184487$11863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184488$11864 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 connect \Y $gt$libresoc.v:184488$11864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184489$11865 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 connect \Y $gt$libresoc.v:184489$11865_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184490$11866 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 connect \Y $gt$libresoc.v:184490$11866_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184491$11867 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 connect \Y $gt$libresoc.v:184491$11867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184492$11868 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 connect \Y $gt$libresoc.v:184492$11868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184493$11869 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 connect \Y $gt$libresoc.v:184493$11869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184494$11870 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 connect \Y $gt$libresoc.v:184494$11870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184495$11871 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 connect \Y $gt$libresoc.v:184495$11871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184496$11872 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 connect \Y $gt$libresoc.v:184496$11872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184497$11873 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 connect \Y $gt$libresoc.v:184497$11873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184498$11874 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 connect \Y $gt$libresoc.v:184498$11874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184499$11875 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 connect \Y $gt$libresoc.v:184499$11875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184500$11876 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 connect \Y $gt$libresoc.v:184500$11876_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184501$11877 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 connect \Y $gt$libresoc.v:184501$11877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184502$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 connect \Y $gt$libresoc.v:184502$11878_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184503$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 connect \Y $gt$libresoc.v:184503$11879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184504$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 connect \Y $gt$libresoc.v:184504$11880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184505$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 connect \Y $gt$libresoc.v:184505$11881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184506$11882 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 connect \Y $gt$libresoc.v:184506$11882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184507$11883 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 connect \Y $gt$libresoc.v:184507$11883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184508$11884 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 connect \Y $gt$libresoc.v:184508$11884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184509$11885 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 connect \Y $gt$libresoc.v:184509$11885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184510$11886 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 connect \Y $gt$libresoc.v:184510$11886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184511$11887 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 connect \Y $gt$libresoc.v:184511$11887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184512$11888 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 connect \Y $gt$libresoc.v:184512$11888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184513$11889 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 connect \Y $gt$libresoc.v:184513$11889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184514$11890 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 connect \Y $gt$libresoc.v:184514$11890_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184515$11891 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 connect \Y $gt$libresoc.v:184515$11891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184516$11892 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 connect \Y $gt$libresoc.v:184516$11892_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184517$11893 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 connect \Y $gt$libresoc.v:184517$11893_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184518$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 connect \Y $gt$libresoc.v:184518$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" cell $gt $gt$libresoc.v:184519$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 connect \Y $gt$libresoc.v:184519$11895_Y end attribute \src "libresoc.v:184322.7-184322.20" process $proc$libresoc.v:184322$11897 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184520.3-184907.6" process $proc$libresoc.v:184520$11896 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] assign $0\mask[63:0] [1] $2\mask[1:1] assign $0\mask[63:0] [2] $3\mask[2:2] assign $0\mask[63:0] [3] $4\mask[3:3] assign $0\mask[63:0] [4] $5\mask[4:4] assign $0\mask[63:0] [5] $6\mask[5:5] assign $0\mask[63:0] [6] $7\mask[6:6] assign $0\mask[63:0] [7] $8\mask[7:7] assign $0\mask[63:0] [8] $9\mask[8:8] assign $0\mask[63:0] [9] $10\mask[9:9] assign $0\mask[63:0] [10] $11\mask[10:10] assign $0\mask[63:0] [11] $12\mask[11:11] assign $0\mask[63:0] [12] $13\mask[12:12] assign $0\mask[63:0] [13] $14\mask[13:13] assign $0\mask[63:0] [14] $15\mask[14:14] assign $0\mask[63:0] [15] $16\mask[15:15] assign $0\mask[63:0] [16] $17\mask[16:16] assign $0\mask[63:0] [17] $18\mask[17:17] assign $0\mask[63:0] [18] $19\mask[18:18] assign $0\mask[63:0] [19] $20\mask[19:19] assign $0\mask[63:0] [20] $21\mask[20:20] assign $0\mask[63:0] [21] $22\mask[21:21] assign $0\mask[63:0] [22] $23\mask[22:22] assign $0\mask[63:0] [23] $24\mask[23:23] assign $0\mask[63:0] [24] $25\mask[24:24] assign $0\mask[63:0] [25] $26\mask[25:25] assign $0\mask[63:0] [26] $27\mask[26:26] assign $0\mask[63:0] [27] $28\mask[27:27] assign $0\mask[63:0] [28] $29\mask[28:28] assign $0\mask[63:0] [29] $30\mask[29:29] assign $0\mask[63:0] [30] $31\mask[30:30] assign $0\mask[63:0] [31] $32\mask[31:31] assign $0\mask[63:0] [32] $33\mask[32:32] assign $0\mask[63:0] [33] $34\mask[33:33] assign $0\mask[63:0] [34] $35\mask[34:34] assign $0\mask[63:0] [35] $36\mask[35:35] assign $0\mask[63:0] [36] $37\mask[36:36] assign $0\mask[63:0] [37] $38\mask[37:37] assign $0\mask[63:0] [38] $39\mask[38:38] assign $0\mask[63:0] [39] $40\mask[39:39] assign $0\mask[63:0] [40] $41\mask[40:40] assign $0\mask[63:0] [41] $42\mask[41:41] assign $0\mask[63:0] [42] $43\mask[42:42] assign $0\mask[63:0] [43] $44\mask[43:43] assign $0\mask[63:0] [44] $45\mask[44:44] assign $0\mask[63:0] [45] $46\mask[45:45] assign $0\mask[63:0] [46] $47\mask[46:46] assign $0\mask[63:0] [47] $48\mask[47:47] assign $0\mask[63:0] [48] $49\mask[48:48] assign $0\mask[63:0] [49] $50\mask[49:49] assign $0\mask[63:0] [50] $51\mask[50:50] assign $0\mask[63:0] [51] $52\mask[51:51] assign $0\mask[63:0] [52] $53\mask[52:52] assign $0\mask[63:0] [53] $54\mask[53:53] assign $0\mask[63:0] [54] $55\mask[54:54] assign $0\mask[63:0] [55] $56\mask[55:55] assign $0\mask[63:0] [56] $57\mask[56:56] assign $0\mask[63:0] [57] $58\mask[57:57] assign $0\mask[63:0] [58] $59\mask[58:58] assign $0\mask[63:0] [59] $60\mask[59:59] assign $0\mask[63:0] [60] $61\mask[60:60] assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] attribute \src "libresoc.v:184521.5-184521.29" switch \initial attribute \src "libresoc.v:184521.9-184521.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\mask[0:0] 1'1 case assign $1\mask[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\mask[1:1] 1'1 case assign $2\mask[1:1] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\mask[2:2] 1'1 case assign $3\mask[2:2] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\mask[3:3] 1'1 case assign $4\mask[3:3] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\mask[4:4] 1'1 case assign $5\mask[4:4] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\mask[5:5] 1'1 case assign $6\mask[5:5] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\mask[6:6] 1'1 case assign $7\mask[6:6] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\mask[7:7] 1'1 case assign $8\mask[7:7] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\mask[8:8] 1'1 case assign $9\mask[8:8] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $10\mask[9:9] 1'1 case assign $10\mask[9:9] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $11\mask[10:10] 1'1 case assign $11\mask[10:10] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $12\mask[11:11] 1'1 case assign $12\mask[11:11] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $13\mask[12:12] 1'1 case assign $13\mask[12:12] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $14\mask[13:13] 1'1 case assign $14\mask[13:13] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $15\mask[14:14] 1'1 case assign $15\mask[14:14] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $16\mask[15:15] 1'1 case assign $16\mask[15:15] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $17\mask[16:16] 1'1 case assign $17\mask[16:16] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$35 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $18\mask[17:17] 1'1 case assign $18\mask[17:17] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $19\mask[18:18] 1'1 case assign $19\mask[18:18] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $20\mask[19:19] 1'1 case assign $20\mask[19:19] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $21\mask[20:20] 1'1 case assign $21\mask[20:20] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $22\mask[21:21] 1'1 case assign $22\mask[21:21] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $23\mask[22:22] 1'1 case assign $23\mask[22:22] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$47 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $24\mask[23:23] 1'1 case assign $24\mask[23:23] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $25\mask[24:24] 1'1 case assign $25\mask[24:24] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$51 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $26\mask[25:25] 1'1 case assign $26\mask[25:25] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $27\mask[26:26] 1'1 case assign $27\mask[26:26] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $28\mask[27:27] 1'1 case assign $28\mask[27:27] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $29\mask[28:28] 1'1 case assign $29\mask[28:28] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $30\mask[29:29] 1'1 case assign $30\mask[29:29] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $31\mask[30:30] 1'1 case assign $31\mask[30:30] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $32\mask[31:31] 1'1 case assign $32\mask[31:31] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$65 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $33\mask[32:32] 1'1 case assign $33\mask[32:32] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $34\mask[33:33] 1'1 case assign $34\mask[33:33] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $35\mask[34:34] 1'1 case assign $35\mask[34:34] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $36\mask[35:35] 1'1 case assign $36\mask[35:35] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $37\mask[36:36] 1'1 case assign $37\mask[36:36] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$75 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $38\mask[37:37] 1'1 case assign $38\mask[37:37] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $39\mask[38:38] 1'1 case assign $39\mask[38:38] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$79 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $40\mask[39:39] 1'1 case assign $40\mask[39:39] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $41\mask[40:40] 1'1 case assign $41\mask[40:40] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $42\mask[41:41] 1'1 case assign $42\mask[41:41] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $43\mask[42:42] 1'1 case assign $43\mask[42:42] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $44\mask[43:43] 1'1 case assign $44\mask[43:43] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$89 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $45\mask[44:44] 1'1 case assign $45\mask[44:44] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$91 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $46\mask[45:45] 1'1 case assign $46\mask[45:45] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $47\mask[46:46] 1'1 case assign $47\mask[46:46] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $48\mask[47:47] 1'1 case assign $48\mask[47:47] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$97 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $49\mask[48:48] 1'1 case assign $49\mask[48:48] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$99 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $50\mask[49:49] 1'1 case assign $50\mask[49:49] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $51\mask[50:50] 1'1 case assign $51\mask[50:50] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $52\mask[51:51] 1'1 case assign $52\mask[51:51] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $53\mask[52:52] 1'1 case assign $53\mask[52:52] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$107 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $54\mask[53:53] 1'1 case assign $54\mask[53:53] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $55\mask[54:54] 1'1 case assign $55\mask[54:54] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$111 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $56\mask[55:55] 1'1 case assign $56\mask[55:55] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $57\mask[56:56] 1'1 case assign $57\mask[56:56] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $58\mask[57:57] 1'1 case assign $58\mask[57:57] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $59\mask[58:58] 1'1 case assign $59\mask[58:58] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $60\mask[59:59] 1'1 case assign $60\mask[59:59] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $61\mask[60:60] 1'1 case assign $61\mask[60:60] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $62\mask[61:61] 1'1 case assign $62\mask[61:61] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$125 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $63\mask[62:62] 1'1 case assign $63\mask[62:62] 1'0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" switch \$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $64\mask[63:63] 1'1 case assign $64\mask[63:63] 1'0 end sync always update \mask $0\mask[63:0] end connect \$9 $gt$libresoc.v:184456$11832_Y connect \$99 $gt$libresoc.v:184457$11833_Y connect \$101 $gt$libresoc.v:184458$11834_Y connect \$103 $gt$libresoc.v:184459$11835_Y connect \$105 $gt$libresoc.v:184460$11836_Y connect \$107 $gt$libresoc.v:184461$11837_Y connect \$109 $gt$libresoc.v:184462$11838_Y connect \$111 $gt$libresoc.v:184463$11839_Y connect \$113 $gt$libresoc.v:184464$11840_Y connect \$115 $gt$libresoc.v:184465$11841_Y connect \$117 $gt$libresoc.v:184466$11842_Y connect \$11 $gt$libresoc.v:184467$11843_Y connect \$119 $gt$libresoc.v:184468$11844_Y connect \$121 $gt$libresoc.v:184469$11845_Y connect \$123 $gt$libresoc.v:184470$11846_Y connect \$125 $gt$libresoc.v:184471$11847_Y connect \$127 $gt$libresoc.v:184472$11848_Y connect \$13 $gt$libresoc.v:184473$11849_Y connect \$15 $gt$libresoc.v:184474$11850_Y connect \$17 $gt$libresoc.v:184475$11851_Y connect \$1 $gt$libresoc.v:184476$11852_Y connect \$19 $gt$libresoc.v:184477$11853_Y connect \$21 $gt$libresoc.v:184478$11854_Y connect \$23 $gt$libresoc.v:184479$11855_Y connect \$25 $gt$libresoc.v:184480$11856_Y connect \$27 $gt$libresoc.v:184481$11857_Y connect \$29 $gt$libresoc.v:184482$11858_Y connect \$31 $gt$libresoc.v:184483$11859_Y connect \$33 $gt$libresoc.v:184484$11860_Y connect \$35 $gt$libresoc.v:184485$11861_Y connect \$37 $gt$libresoc.v:184486$11862_Y connect \$3 $gt$libresoc.v:184487$11863_Y connect \$39 $gt$libresoc.v:184488$11864_Y connect \$41 $gt$libresoc.v:184489$11865_Y connect \$43 $gt$libresoc.v:184490$11866_Y connect \$45 $gt$libresoc.v:184491$11867_Y connect \$47 $gt$libresoc.v:184492$11868_Y connect \$49 $gt$libresoc.v:184493$11869_Y connect \$51 $gt$libresoc.v:184494$11870_Y connect \$53 $gt$libresoc.v:184495$11871_Y connect \$55 $gt$libresoc.v:184496$11872_Y connect \$57 $gt$libresoc.v:184497$11873_Y connect \$5 $gt$libresoc.v:184498$11874_Y connect \$59 $gt$libresoc.v:184499$11875_Y connect \$61 $gt$libresoc.v:184500$11876_Y connect \$63 $gt$libresoc.v:184501$11877_Y connect \$65 $gt$libresoc.v:184502$11878_Y connect \$67 $gt$libresoc.v:184503$11879_Y connect \$69 $gt$libresoc.v:184504$11880_Y connect \$71 $gt$libresoc.v:184505$11881_Y connect \$73 $gt$libresoc.v:184506$11882_Y connect \$75 $gt$libresoc.v:184507$11883_Y connect \$77 $gt$libresoc.v:184508$11884_Y connect \$7 $gt$libresoc.v:184509$11885_Y connect \$79 $gt$libresoc.v:184510$11886_Y connect \$81 $gt$libresoc.v:184511$11887_Y connect \$83 $gt$libresoc.v:184512$11888_Y connect \$85 $gt$libresoc.v:184513$11889_Y connect \$87 $gt$libresoc.v:184514$11890_Y connect \$89 $gt$libresoc.v:184515$11891_Y connect \$91 $gt$libresoc.v:184516$11892_Y connect \$93 $gt$libresoc.v:184517$11893_Y connect \$95 $gt$libresoc.v:184518$11894_Y connect \$97 $gt$libresoc.v:184519$11895_Y end attribute \src "libresoc.v:184912.1-184970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l attribute \src "libresoc.v:184913.7-184913.20" wire $0\initial[0:0] attribute \src "libresoc.v:184958.3-184966.6" wire $0\q_int$next[0:0]$11908 attribute \src "libresoc.v:184956.3-184957.27" wire $0\q_int[0:0] attribute \src "libresoc.v:184958.3-184966.6" wire $1\q_int$next[0:0]$11909 attribute \src "libresoc.v:184935.7-184935.19" wire $1\q_int[0:0] attribute \src "libresoc.v:184948.17-184948.96" wire $and$libresoc.v:184948$11898_Y attribute \src "libresoc.v:184953.17-184953.96" wire $and$libresoc.v:184953$11903_Y attribute \src "libresoc.v:184950.18-184950.94" wire $not$libresoc.v:184950$11900_Y attribute \src "libresoc.v:184952.17-184952.93" wire $not$libresoc.v:184952$11902_Y attribute \src "libresoc.v:184955.17-184955.93" wire $not$libresoc.v:184955$11905_Y attribute \src "libresoc.v:184949.18-184949.99" wire $or$libresoc.v:184949$11899_Y attribute \src "libresoc.v:184951.18-184951.100" wire $or$libresoc.v:184951$11901_Y attribute \src "libresoc.v:184954.17-184954.98" wire $or$libresoc.v:184954$11904_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:184913.7-184913.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:184948$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:184948$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:184953$11903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:184953$11903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:184950$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:184950$11900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:184952$11902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:184952$11902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:184955$11905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:184955$11905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:184949$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:184949$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:184951$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:184951$11901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:184954$11904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:184954$11904_Y end attribute \src "libresoc.v:184913.7-184913.20" process $proc$libresoc.v:184913$11910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184935.7-184935.19" process $proc$libresoc.v:184935$11911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:184956.3-184957.27" process $proc$libresoc.v:184956$11906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:184958.3-184966.6" process $proc$libresoc.v:184958$11907 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11908 $1\q_int$next[0:0]$11909 attribute \src "libresoc.v:184959.5-184959.29" switch \initial attribute \src "libresoc.v:184959.9-184959.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11909 1'0 case assign $1\q_int$next[0:0]$11909 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11908 end connect \$9 $and$libresoc.v:184948$11898_Y connect \$11 $or$libresoc.v:184949$11899_Y connect \$13 $not$libresoc.v:184950$11900_Y connect \$15 $or$libresoc.v:184951$11901_Y connect \$1 $not$libresoc.v:184952$11902_Y connect \$3 $and$libresoc.v:184953$11903_Y connect \$5 $or$libresoc.v:184954$11904_Y connect \$7 $not$libresoc.v:184955$11905_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:184974.1-185032.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 attribute \src "libresoc.v:184975.7-184975.20" wire $0\initial[0:0] attribute \src "libresoc.v:185020.3-185028.6" wire $0\q_int$next[0:0]$11922 attribute \src "libresoc.v:185018.3-185019.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185020.3-185028.6" wire $1\q_int$next[0:0]$11923 attribute \src "libresoc.v:184997.7-184997.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185010.17-185010.96" wire $and$libresoc.v:185010$11912_Y attribute \src "libresoc.v:185015.17-185015.96" wire $and$libresoc.v:185015$11917_Y attribute \src "libresoc.v:185012.18-185012.94" wire $not$libresoc.v:185012$11914_Y attribute \src "libresoc.v:185014.17-185014.93" wire $not$libresoc.v:185014$11916_Y attribute \src "libresoc.v:185017.17-185017.93" wire $not$libresoc.v:185017$11919_Y attribute \src "libresoc.v:185011.18-185011.99" wire $or$libresoc.v:185011$11913_Y attribute \src "libresoc.v:185013.18-185013.100" wire $or$libresoc.v:185013$11915_Y attribute \src "libresoc.v:185016.17-185016.98" wire $or$libresoc.v:185016$11918_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:184975.7-184975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185010$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185010$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185015$11917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185015$11917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185012$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185012$11914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185014$11916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185014$11916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185017$11919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185017$11919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185011$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185011$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185013$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185013$11915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185016$11918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185016$11918_Y end attribute \src "libresoc.v:184975.7-184975.20" process $proc$libresoc.v:184975$11924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:184997.7-184997.19" process $proc$libresoc.v:184997$11925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185018.3-185019.27" process $proc$libresoc.v:185018$11920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185020.3-185028.6" process $proc$libresoc.v:185020$11921 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11922 $1\q_int$next[0:0]$11923 attribute \src "libresoc.v:185021.5-185021.29" switch \initial attribute \src "libresoc.v:185021.9-185021.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11923 1'0 case assign $1\q_int$next[0:0]$11923 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11922 end connect \$9 $and$libresoc.v:185010$11912_Y connect \$11 $or$libresoc.v:185011$11913_Y connect \$13 $not$libresoc.v:185012$11914_Y connect \$15 $or$libresoc.v:185013$11915_Y connect \$1 $not$libresoc.v:185014$11916_Y connect \$3 $and$libresoc.v:185015$11917_Y connect \$5 $or$libresoc.v:185016$11918_Y connect \$7 $not$libresoc.v:185017$11919_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185036.1-185094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 attribute \src "libresoc.v:185037.7-185037.20" wire $0\initial[0:0] attribute \src "libresoc.v:185082.3-185090.6" wire $0\q_int$next[0:0]$11936 attribute \src "libresoc.v:185080.3-185081.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185082.3-185090.6" wire $1\q_int$next[0:0]$11937 attribute \src "libresoc.v:185059.7-185059.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185072.17-185072.96" wire $and$libresoc.v:185072$11926_Y attribute \src "libresoc.v:185077.17-185077.96" wire $and$libresoc.v:185077$11931_Y attribute \src "libresoc.v:185074.18-185074.94" wire $not$libresoc.v:185074$11928_Y attribute \src "libresoc.v:185076.17-185076.93" wire $not$libresoc.v:185076$11930_Y attribute \src "libresoc.v:185079.17-185079.93" wire $not$libresoc.v:185079$11933_Y attribute \src "libresoc.v:185073.18-185073.99" wire $or$libresoc.v:185073$11927_Y attribute \src "libresoc.v:185075.18-185075.100" wire $or$libresoc.v:185075$11929_Y attribute \src "libresoc.v:185078.17-185078.98" wire $or$libresoc.v:185078$11932_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185037.7-185037.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185072$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185072$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185077$11931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185077$11931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185074$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185074$11928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185076$11930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185076$11930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185079$11933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185079$11933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185073$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185073$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185075$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185075$11929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185078$11932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185078$11932_Y end attribute \src "libresoc.v:185037.7-185037.20" process $proc$libresoc.v:185037$11938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185059.7-185059.19" process $proc$libresoc.v:185059$11939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185080.3-185081.27" process $proc$libresoc.v:185080$11934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185082.3-185090.6" process $proc$libresoc.v:185082$11935 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11936 $1\q_int$next[0:0]$11937 attribute \src "libresoc.v:185083.5-185083.29" switch \initial attribute \src "libresoc.v:185083.9-185083.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11937 1'0 case assign $1\q_int$next[0:0]$11937 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11936 end connect \$9 $and$libresoc.v:185072$11926_Y connect \$11 $or$libresoc.v:185073$11927_Y connect \$13 $not$libresoc.v:185074$11928_Y connect \$15 $or$libresoc.v:185075$11929_Y connect \$1 $not$libresoc.v:185076$11930_Y connect \$3 $and$libresoc.v:185077$11931_Y connect \$5 $or$libresoc.v:185078$11932_Y connect \$7 $not$libresoc.v:185079$11933_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185098.1-185156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 attribute \src "libresoc.v:185099.7-185099.20" wire $0\initial[0:0] attribute \src "libresoc.v:185144.3-185152.6" wire $0\q_int$next[0:0]$11950 attribute \src "libresoc.v:185142.3-185143.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185144.3-185152.6" wire $1\q_int$next[0:0]$11951 attribute \src "libresoc.v:185121.7-185121.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185134.17-185134.96" wire $and$libresoc.v:185134$11940_Y attribute \src "libresoc.v:185139.17-185139.96" wire $and$libresoc.v:185139$11945_Y attribute \src "libresoc.v:185136.18-185136.94" wire $not$libresoc.v:185136$11942_Y attribute \src "libresoc.v:185138.17-185138.93" wire $not$libresoc.v:185138$11944_Y attribute \src "libresoc.v:185141.17-185141.93" wire $not$libresoc.v:185141$11947_Y attribute \src "libresoc.v:185135.18-185135.99" wire $or$libresoc.v:185135$11941_Y attribute \src "libresoc.v:185137.18-185137.100" wire $or$libresoc.v:185137$11943_Y attribute \src "libresoc.v:185140.17-185140.98" wire $or$libresoc.v:185140$11946_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185099.7-185099.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185134$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185134$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185139$11945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185139$11945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185136$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185136$11942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185138$11944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185138$11944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185141$11947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185141$11947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185135$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185135$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185137$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185137$11943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185140$11946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185140$11946_Y end attribute \src "libresoc.v:185099.7-185099.20" process $proc$libresoc.v:185099$11952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185121.7-185121.19" process $proc$libresoc.v:185121$11953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185142.3-185143.27" process $proc$libresoc.v:185142$11948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185144.3-185152.6" process $proc$libresoc.v:185144$11949 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11950 $1\q_int$next[0:0]$11951 attribute \src "libresoc.v:185145.5-185145.29" switch \initial attribute \src "libresoc.v:185145.9-185145.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11951 1'0 case assign $1\q_int$next[0:0]$11951 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11950 end connect \$9 $and$libresoc.v:185134$11940_Y connect \$11 $or$libresoc.v:185135$11941_Y connect \$13 $not$libresoc.v:185136$11942_Y connect \$15 $or$libresoc.v:185137$11943_Y connect \$1 $not$libresoc.v:185138$11944_Y connect \$3 $and$libresoc.v:185139$11945_Y connect \$5 $or$libresoc.v:185140$11946_Y connect \$7 $not$libresoc.v:185141$11947_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185160.1-185218.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 attribute \src "libresoc.v:185161.7-185161.20" wire $0\initial[0:0] attribute \src "libresoc.v:185206.3-185214.6" wire $0\q_int$next[0:0]$11964 attribute \src "libresoc.v:185204.3-185205.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185206.3-185214.6" wire $1\q_int$next[0:0]$11965 attribute \src "libresoc.v:185183.7-185183.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185196.17-185196.96" wire $and$libresoc.v:185196$11954_Y attribute \src "libresoc.v:185201.17-185201.96" wire $and$libresoc.v:185201$11959_Y attribute \src "libresoc.v:185198.18-185198.94" wire $not$libresoc.v:185198$11956_Y attribute \src "libresoc.v:185200.17-185200.93" wire $not$libresoc.v:185200$11958_Y attribute \src "libresoc.v:185203.17-185203.93" wire $not$libresoc.v:185203$11961_Y attribute \src "libresoc.v:185197.18-185197.99" wire $or$libresoc.v:185197$11955_Y attribute \src "libresoc.v:185199.18-185199.100" wire $or$libresoc.v:185199$11957_Y attribute \src "libresoc.v:185202.17-185202.98" wire $or$libresoc.v:185202$11960_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185161.7-185161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185196$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185196$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185201$11959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185201$11959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185198$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185198$11956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185200$11958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185200$11958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185203$11961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185203$11961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185197$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185197$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185199$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185199$11957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185202$11960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185202$11960_Y end attribute \src "libresoc.v:185161.7-185161.20" process $proc$libresoc.v:185161$11966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185183.7-185183.19" process $proc$libresoc.v:185183$11967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185204.3-185205.27" process $proc$libresoc.v:185204$11962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185206.3-185214.6" process $proc$libresoc.v:185206$11963 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11964 $1\q_int$next[0:0]$11965 attribute \src "libresoc.v:185207.5-185207.29" switch \initial attribute \src "libresoc.v:185207.9-185207.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11965 1'0 case assign $1\q_int$next[0:0]$11965 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11964 end connect \$9 $and$libresoc.v:185196$11954_Y connect \$11 $or$libresoc.v:185197$11955_Y connect \$13 $not$libresoc.v:185198$11956_Y connect \$15 $or$libresoc.v:185199$11957_Y connect \$1 $not$libresoc.v:185200$11958_Y connect \$3 $and$libresoc.v:185201$11959_Y connect \$5 $or$libresoc.v:185202$11960_Y connect \$7 $not$libresoc.v:185203$11961_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185222.1-185280.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 attribute \src "libresoc.v:185223.7-185223.20" wire $0\initial[0:0] attribute \src "libresoc.v:185268.3-185276.6" wire $0\q_int$next[0:0]$11978 attribute \src "libresoc.v:185266.3-185267.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185268.3-185276.6" wire $1\q_int$next[0:0]$11979 attribute \src "libresoc.v:185245.7-185245.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185258.17-185258.96" wire $and$libresoc.v:185258$11968_Y attribute \src "libresoc.v:185263.17-185263.96" wire $and$libresoc.v:185263$11973_Y attribute \src "libresoc.v:185260.18-185260.94" wire $not$libresoc.v:185260$11970_Y attribute \src "libresoc.v:185262.17-185262.93" wire $not$libresoc.v:185262$11972_Y attribute \src "libresoc.v:185265.17-185265.93" wire $not$libresoc.v:185265$11975_Y attribute \src "libresoc.v:185259.18-185259.99" wire $or$libresoc.v:185259$11969_Y attribute \src "libresoc.v:185261.18-185261.100" wire $or$libresoc.v:185261$11971_Y attribute \src "libresoc.v:185264.17-185264.98" wire $or$libresoc.v:185264$11974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185223.7-185223.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185258$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185258$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185263$11973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185263$11973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185260$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185260$11970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185262$11972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185262$11972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185265$11975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185265$11975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185259$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185259$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185261$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185261$11971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185264$11974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185264$11974_Y end attribute \src "libresoc.v:185223.7-185223.20" process $proc$libresoc.v:185223$11980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185245.7-185245.19" process $proc$libresoc.v:185245$11981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185266.3-185267.27" process $proc$libresoc.v:185266$11976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185268.3-185276.6" process $proc$libresoc.v:185268$11977 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11978 $1\q_int$next[0:0]$11979 attribute \src "libresoc.v:185269.5-185269.29" switch \initial attribute \src "libresoc.v:185269.9-185269.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11979 1'0 case assign $1\q_int$next[0:0]$11979 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11978 end connect \$9 $and$libresoc.v:185258$11968_Y connect \$11 $or$libresoc.v:185259$11969_Y connect \$13 $not$libresoc.v:185260$11970_Y connect \$15 $or$libresoc.v:185261$11971_Y connect \$1 $not$libresoc.v:185262$11972_Y connect \$3 $and$libresoc.v:185263$11973_Y connect \$5 $or$libresoc.v:185264$11974_Y connect \$7 $not$libresoc.v:185265$11975_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185284.1-185342.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 attribute \src "libresoc.v:185285.7-185285.20" wire $0\initial[0:0] attribute \src "libresoc.v:185330.3-185338.6" wire $0\q_int$next[0:0]$11992 attribute \src "libresoc.v:185328.3-185329.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185330.3-185338.6" wire $1\q_int$next[0:0]$11993 attribute \src "libresoc.v:185307.7-185307.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185320.17-185320.96" wire $and$libresoc.v:185320$11982_Y attribute \src "libresoc.v:185325.17-185325.96" wire $and$libresoc.v:185325$11987_Y attribute \src "libresoc.v:185322.18-185322.94" wire $not$libresoc.v:185322$11984_Y attribute \src "libresoc.v:185324.17-185324.93" wire $not$libresoc.v:185324$11986_Y attribute \src "libresoc.v:185327.17-185327.93" wire $not$libresoc.v:185327$11989_Y attribute \src "libresoc.v:185321.18-185321.99" wire $or$libresoc.v:185321$11983_Y attribute \src "libresoc.v:185323.18-185323.100" wire $or$libresoc.v:185323$11985_Y attribute \src "libresoc.v:185326.17-185326.98" wire $or$libresoc.v:185326$11988_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185285.7-185285.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185320$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185320$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185325$11987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185325$11987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185322$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185322$11984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185324$11986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185324$11986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185327$11989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185327$11989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185321$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185321$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185323$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185323$11985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185326$11988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185326$11988_Y end attribute \src "libresoc.v:185285.7-185285.20" process $proc$libresoc.v:185285$11994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185307.7-185307.19" process $proc$libresoc.v:185307$11995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185328.3-185329.27" process $proc$libresoc.v:185328$11990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185330.3-185338.6" process $proc$libresoc.v:185330$11991 assign { } { } assign { } { } assign $0\q_int$next[0:0]$11992 $1\q_int$next[0:0]$11993 attribute \src "libresoc.v:185331.5-185331.29" switch \initial attribute \src "libresoc.v:185331.9-185331.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$11993 1'0 case assign $1\q_int$next[0:0]$11993 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$11992 end connect \$9 $and$libresoc.v:185320$11982_Y connect \$11 $or$libresoc.v:185321$11983_Y connect \$13 $not$libresoc.v:185322$11984_Y connect \$15 $or$libresoc.v:185323$11985_Y connect \$1 $not$libresoc.v:185324$11986_Y connect \$3 $and$libresoc.v:185325$11987_Y connect \$5 $or$libresoc.v:185326$11988_Y connect \$7 $not$libresoc.v:185327$11989_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185346.1-185404.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 attribute \src "libresoc.v:185347.7-185347.20" wire $0\initial[0:0] attribute \src "libresoc.v:185392.3-185400.6" wire $0\q_int$next[0:0]$12006 attribute \src "libresoc.v:185390.3-185391.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185392.3-185400.6" wire $1\q_int$next[0:0]$12007 attribute \src "libresoc.v:185369.7-185369.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185382.17-185382.96" wire $and$libresoc.v:185382$11996_Y attribute \src "libresoc.v:185387.17-185387.96" wire $and$libresoc.v:185387$12001_Y attribute \src "libresoc.v:185384.18-185384.94" wire $not$libresoc.v:185384$11998_Y attribute \src "libresoc.v:185386.17-185386.93" wire $not$libresoc.v:185386$12000_Y attribute \src "libresoc.v:185389.17-185389.93" wire $not$libresoc.v:185389$12003_Y attribute \src "libresoc.v:185383.18-185383.99" wire $or$libresoc.v:185383$11997_Y attribute \src "libresoc.v:185385.18-185385.100" wire $or$libresoc.v:185385$11999_Y attribute \src "libresoc.v:185388.17-185388.98" wire $or$libresoc.v:185388$12002_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185347.7-185347.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185382$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185382$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185387$12001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185387$12001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185384$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185384$11998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185386$12000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185386$12000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185389$12003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185389$12003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185383$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185383$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185385$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185385$11999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185388$12002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185388$12002_Y end attribute \src "libresoc.v:185347.7-185347.20" process $proc$libresoc.v:185347$12008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185369.7-185369.19" process $proc$libresoc.v:185369$12009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185390.3-185391.27" process $proc$libresoc.v:185390$12004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185392.3-185400.6" process $proc$libresoc.v:185392$12005 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12006 $1\q_int$next[0:0]$12007 attribute \src "libresoc.v:185393.5-185393.29" switch \initial attribute \src "libresoc.v:185393.9-185393.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12007 1'0 case assign $1\q_int$next[0:0]$12007 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12006 end connect \$9 $and$libresoc.v:185382$11996_Y connect \$11 $or$libresoc.v:185383$11997_Y connect \$13 $not$libresoc.v:185384$11998_Y connect \$15 $or$libresoc.v:185385$11999_Y connect \$1 $not$libresoc.v:185386$12000_Y connect \$3 $and$libresoc.v:185387$12001_Y connect \$5 $or$libresoc.v:185388$12002_Y connect \$7 $not$libresoc.v:185389$12003_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185408.1-185466.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 attribute \src "libresoc.v:185409.7-185409.20" wire $0\initial[0:0] attribute \src "libresoc.v:185454.3-185462.6" wire $0\q_int$next[0:0]$12020 attribute \src "libresoc.v:185452.3-185453.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185454.3-185462.6" wire $1\q_int$next[0:0]$12021 attribute \src "libresoc.v:185431.7-185431.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185444.17-185444.96" wire $and$libresoc.v:185444$12010_Y attribute \src "libresoc.v:185449.17-185449.96" wire $and$libresoc.v:185449$12015_Y attribute \src "libresoc.v:185446.18-185446.94" wire $not$libresoc.v:185446$12012_Y attribute \src "libresoc.v:185448.17-185448.93" wire $not$libresoc.v:185448$12014_Y attribute \src "libresoc.v:185451.17-185451.93" wire $not$libresoc.v:185451$12017_Y attribute \src "libresoc.v:185445.18-185445.99" wire $or$libresoc.v:185445$12011_Y attribute \src "libresoc.v:185447.18-185447.100" wire $or$libresoc.v:185447$12013_Y attribute \src "libresoc.v:185450.17-185450.98" wire $or$libresoc.v:185450$12016_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185409.7-185409.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185444$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185444$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185449$12015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185449$12015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185446$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \Y $not$libresoc.v:185446$12012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185448$12014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185448$12014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185451$12017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok connect \Y $not$libresoc.v:185451$12017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185445$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok connect \Y $or$libresoc.v:185445$12011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185447$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int connect \Y $or$libresoc.v:185447$12013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185450$12016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok connect \Y $or$libresoc.v:185450$12016_Y end attribute \src "libresoc.v:185409.7-185409.20" process $proc$libresoc.v:185409$12022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185431.7-185431.19" process $proc$libresoc.v:185431$12023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185452.3-185453.27" process $proc$libresoc.v:185452$12018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185454.3-185462.6" process $proc$libresoc.v:185454$12019 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12020 $1\q_int$next[0:0]$12021 attribute \src "libresoc.v:185455.5-185455.29" switch \initial attribute \src "libresoc.v:185455.9-185455.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12021 1'0 case assign $1\q_int$next[0:0]$12021 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12020 end connect \$9 $and$libresoc.v:185444$12010_Y connect \$11 $or$libresoc.v:185445$12011_Y connect \$13 $not$libresoc.v:185446$12012_Y connect \$15 $or$libresoc.v:185447$12013_Y connect \$1 $not$libresoc.v:185448$12014_Y connect \$3 $and$libresoc.v:185449$12015_Y connect \$5 $or$libresoc.v:185450$12016_Y connect \$7 $not$libresoc.v:185451$12017_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end attribute \src "libresoc.v:185470.1-185830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator attribute \src "libresoc.v:185739.3-185757.6" wire $0\carry_out_o[0:0] attribute \src "libresoc.v:185671.3-185685.6" wire width 32 $0\hi32[31:0] attribute \src "libresoc.v:185471.7-185471.20" wire $0\initial[0:0] attribute \src "libresoc.v:185770.3-185803.6" wire width 7 $0\mb$8[6:0]$12071 attribute \src "libresoc.v:185804.3-185818.6" wire width 7 $0\me$13[6:0]$12076 attribute \src "libresoc.v:185696.3-185707.6" wire width 64 $0\mr[63:0] attribute \src "libresoc.v:185708.3-185719.6" wire width 2 $0\output_mode[1:0] attribute \src "libresoc.v:185720.3-185738.6" wire width 64 $0\result_o[63:0] attribute \src "libresoc.v:185686.3-185695.6" wire width 7 $0\right_mask_shift[6:0] attribute \src "libresoc.v:185758.3-185769.6" wire width 6 $0\rot_count[5:0] attribute \src "libresoc.v:185739.3-185757.6" wire $1\carry_out_o[0:0] attribute \src "libresoc.v:185671.3-185685.6" wire width 32 $1\hi32[31:0] attribute \src "libresoc.v:185770.3-185803.6" wire width 7 $1\mb$8[6:0]$12072 attribute \src "libresoc.v:185804.3-185818.6" wire width 7 $1\me$13[6:0]$12077 attribute \src "libresoc.v:185696.3-185707.6" wire width 64 $1\mr[63:0] attribute \src "libresoc.v:185708.3-185719.6" wire width 2 $1\output_mode[1:0] attribute \src "libresoc.v:185720.3-185738.6" wire width 64 $1\result_o[63:0] attribute \src "libresoc.v:185686.3-185695.6" wire width 7 $1\right_mask_shift[6:0] attribute \src "libresoc.v:185758.3-185769.6" wire width 6 $1\rot_count[5:0] attribute \src "libresoc.v:185770.3-185803.6" wire width 2 $2\mb$8[6:5]$12073 attribute \src "libresoc.v:185770.3-185803.6" wire width 2 $3\mb$8[6:5]$12074 attribute \src "libresoc.v:185622.18-185622.118" wire $and$libresoc.v:185622$12027_Y attribute \src "libresoc.v:185624.18-185624.114" wire $and$libresoc.v:185624$12029_Y attribute \src "libresoc.v:185633.18-185633.113" wire $and$libresoc.v:185633$12038_Y attribute \src "libresoc.v:185635.18-185635.114" wire $and$libresoc.v:185635$12040_Y attribute \src "libresoc.v:185637.18-185637.114" wire $and$libresoc.v:185637$12042_Y attribute \src "libresoc.v:185638.18-185638.103" wire width 64 $and$libresoc.v:185638$12043_Y attribute \src "libresoc.v:185639.18-185639.106" wire width 64 $and$libresoc.v:185639$12044_Y attribute \src "libresoc.v:185641.18-185641.103" wire width 64 $and$libresoc.v:185641$12046_Y attribute \src "libresoc.v:185643.18-185643.105" wire width 64 $and$libresoc.v:185643$12048_Y attribute \src "libresoc.v:185646.18-185646.106" wire width 64 $and$libresoc.v:185646$12051_Y attribute \src "libresoc.v:185649.18-185649.105" wire width 64 $and$libresoc.v:185649$12054_Y attribute \src "libresoc.v:185651.17-185651.109" wire $and$libresoc.v:185651$12056_Y attribute \src "libresoc.v:185652.18-185652.104" wire width 64 $and$libresoc.v:185652$12057_Y attribute \src "libresoc.v:185656.18-185656.105" wire width 64 $and$libresoc.v:185656$12061_Y attribute \src "libresoc.v:185620.17-185620.98" wire width 7 $extend$libresoc.v:185620$12024_Y attribute \src "libresoc.v:185636.18-185636.122" wire $gt$libresoc.v:185636$12041_Y attribute \src "libresoc.v:185626.18-185626.111" wire $le$libresoc.v:185626$12031_Y attribute \src "libresoc.v:185628.18-185628.111" wire $le$libresoc.v:185628$12033_Y attribute \src "libresoc.v:185629.17-185629.117" wire width 7 signed $neg$libresoc.v:185629$12034_Y attribute \src "libresoc.v:185621.18-185621.103" wire $not$libresoc.v:185621$12026_Y attribute \src "libresoc.v:185623.18-185623.108" wire $not$libresoc.v:185623$12028_Y attribute \src "libresoc.v:185625.18-185625.105" wire width 6 $not$libresoc.v:185625$12030_Y attribute \src "libresoc.v:185631.18-185631.112" wire width 64 $not$libresoc.v:185631$12036_Y attribute \src "libresoc.v:185632.18-185632.109" wire $not$libresoc.v:185632$12037_Y attribute \src "libresoc.v:185640.17-185640.105" wire $not$libresoc.v:185640$12045_Y attribute \src "libresoc.v:185642.18-185642.102" wire width 64 $not$libresoc.v:185642$12047_Y attribute \src "libresoc.v:185648.18-185648.102" wire width 64 $not$libresoc.v:185648$12053_Y attribute \src "libresoc.v:185653.18-185653.100" wire width 64 $not$libresoc.v:185653$12058_Y attribute \src "libresoc.v:185655.18-185655.100" wire width 64 $not$libresoc.v:185655$12060_Y attribute \src "libresoc.v:185634.18-185634.115" wire $or$libresoc.v:185634$12039_Y attribute \src "libresoc.v:185644.18-185644.108" wire width 64 $or$libresoc.v:185644$12049_Y attribute \src "libresoc.v:185645.18-185645.103" wire width 64 $or$libresoc.v:185645$12050_Y attribute \src "libresoc.v:185647.18-185647.103" wire width 64 $or$libresoc.v:185647$12052_Y attribute \src "libresoc.v:185650.18-185650.108" wire width 64 $or$libresoc.v:185650$12055_Y attribute \src "libresoc.v:185654.18-185654.106" wire width 64 $or$libresoc.v:185654$12059_Y attribute \src "libresoc.v:185620.17-185620.98" wire width 7 $pos$libresoc.v:185620$12025_Y attribute \src "libresoc.v:185657.18-185657.102" wire $reduce_or$libresoc.v:185657$12062_Y attribute \src "libresoc.v:185627.18-185627.109" wire width 8 $sub$libresoc.v:185627$12032_Y attribute \src "libresoc.v:185630.18-185630.110" wire width 8 $sub$libresoc.v:185630$12035_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" wire width 6 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" wire width 8 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" wire width 8 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" wire width 8 \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" wire width 8 \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" wire width 64 \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" wire width 64 \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" wire width 64 \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" wire width 64 \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" wire width 64 \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" wire width 64 \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" wire width 64 \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" wire width 64 \$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" wire width 64 \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" wire width 64 \$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" wire width 64 \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" wire width 64 \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" wire width 64 \$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" wire width 64 \$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" wire width 64 \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" wire width 64 \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" wire \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" wire width 64 \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" wire width 64 \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" wire width 7 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" wire input 7 \arith attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" wire output 13 \carry_out_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" wire input 9 \clear_left attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 attribute \src "libresoc.v:185471.7-185471.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 \left_mask_mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 \left_mask_shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" wire width 5 input 1 \mb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76" wire width 7 \mb$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" wire input 2 \mb_extra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" wire width 5 input 14 \me attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77" wire width 7 \me$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79" wire width 64 \ml attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78" wire width 64 \mr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:80" wire width 2 \output_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" wire width 64 input 4 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" wire width 64 \repl32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" wire width 64 output 12 \result_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 \right_mask_mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 \right_mask_shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" wire input 8 \right_shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74" wire width 64 \rot attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73" wire width 6 \rot_count attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" wire width 64 \rotl_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" wire width 6 \rotl_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 \rotl_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" wire width 64 input 3 \rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75" wire width 7 \sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" wire width 7 input 5 \shift attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94" wire width 6 \shift_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" cell $and $and$libresoc.v:185622$12027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit connect \Y $and$libresoc.v:185622$12027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" cell $and $and$libresoc.v:185624$12029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 connect \Y $and$libresoc.v:185624$12029_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" cell $and $and$libresoc.v:185633$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 connect \Y $and$libresoc.v:185633$12038_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" cell $and $and$libresoc.v:185635$12040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] connect \Y $and$libresoc.v:185635$12040_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" cell $and $and$libresoc.v:185637$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 connect \Y $and$libresoc.v:185637$12042_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" cell $and $and$libresoc.v:185638$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr connect \B \ml connect \Y $and$libresoc.v:185638$12043_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" cell $and $and$libresoc.v:185639$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 connect \Y $and$libresoc.v:185639$12044_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" cell $and $and$libresoc.v:185641$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr connect \B \ml connect \Y $and$libresoc.v:185641$12046_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" cell $and $and$libresoc.v:185643$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 connect \Y $and$libresoc.v:185643$12048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" cell $and $and$libresoc.v:185646$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 connect \Y $and$libresoc.v:185646$12051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" cell $and $and$libresoc.v:185649$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 connect \Y $and$libresoc.v:185649$12054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" cell $and $and$libresoc.v:185651$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 connect \Y $and$libresoc.v:185651$12056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" cell $and $and$libresoc.v:185652$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rot connect \B \mr connect \Y $and$libresoc.v:185652$12057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" cell $and $and$libresoc.v:185656$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 connect \Y $and$libresoc.v:185656$12061_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" cell $pos $extend$libresoc.v:185620$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb connect \Y $extend$libresoc.v:185620$12024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" cell $gt $gt$libresoc.v:185636$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] connect \Y $gt$libresoc.v:185636$12041_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" cell $le $le$libresoc.v:185626$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 connect \Y $le$libresoc.v:185626$12031_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" cell $le $le$libresoc.v:185628$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 connect \Y $le$libresoc.v:185628$12033_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" cell $neg $neg$libresoc.v:185629$12034 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } connect \Y $neg$libresoc.v:185629$12034_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" cell $not $not$libresoc.v:185621$12026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] connect \Y $not$libresoc.v:185621$12026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" cell $not $not$libresoc.v:185623$12028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left connect \Y $not$libresoc.v:185623$12028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" cell $not $not$libresoc.v:185625$12030 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] connect \Y $not$libresoc.v:185625$12030_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" cell $not $not$libresoc.v:185631$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask connect \Y $not$libresoc.v:185631$12036_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" cell $not $not$libresoc.v:185632$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right connect \Y $not$libresoc.v:185632$12037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" cell $not $not$libresoc.v:185640$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit connect \Y $not$libresoc.v:185640$12045_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" cell $not $not$libresoc.v:185642$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 connect \Y $not$libresoc.v:185642$12047_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" cell $not $not$libresoc.v:185648$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 connect \Y $not$libresoc.v:185648$12053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" cell $not $not$libresoc.v:185653$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr connect \Y $not$libresoc.v:185653$12058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" cell $not $not$libresoc.v:185655$12060 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml connect \Y $not$libresoc.v:185655$12060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" cell $or $or$libresoc.v:185634$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift connect \Y $or$libresoc.v:185634$12039_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" cell $or $or$libresoc.v:185644$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 connect \Y $or$libresoc.v:185644$12049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" cell $or $or$libresoc.v:185645$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr connect \B \ml connect \Y $or$libresoc.v:185645$12050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" cell $or $or$libresoc.v:185647$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr connect \B \ml connect \Y $or$libresoc.v:185647$12052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" cell $or $or$libresoc.v:185650$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 connect \Y $or$libresoc.v:185650$12055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" cell $or $or$libresoc.v:185654$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 connect \Y $or$libresoc.v:185654$12059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" cell $pos $pos$libresoc.v:185620$12025 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A $extend$libresoc.v:185620$12024_Y connect \Y $pos$libresoc.v:185620$12025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" cell $reduce_or $reduce_or$libresoc.v:185657$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 connect \Y $reduce_or$libresoc.v:185657$12062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" cell $sub $sub$libresoc.v:185627$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 connect \Y $sub$libresoc.v:185627$12032_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" cell $sub $sub$libresoc.v:185630$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 connect \Y $sub$libresoc.v:185630$12035_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:185658.13-185661.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 attribute \src "libresoc.v:185662.14-185665.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 attribute \src "libresoc.v:185666.8-185670.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end attribute \src "libresoc.v:185471.7-185471.20" process $proc$libresoc.v:185471$12078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185671.3-185685.6" process $proc$libresoc.v:185671$12063 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] attribute \src "libresoc.v:185672.5-185672.29" switch \initial attribute \src "libresoc.v:185672.9-185672.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" switch { \sign_ext_rs \is_32bit } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\hi32[31:0] \rs [31:0] attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\hi32[31:0] { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\hi32[31:0] \rs [63:32] end sync always update \hi32 $0\hi32[31:0] end attribute \src "libresoc.v:185686.3-185695.6" process $proc$libresoc.v:185686$12064 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] attribute \src "libresoc.v:185687.5-185687.29" switch \initial attribute \src "libresoc.v:185687.9-185687.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" switch \$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\right_mask_shift[6:0] \$24 [6:0] case assign $1\right_mask_shift[6:0] 7'0000000 end sync always update \right_mask_shift $0\right_mask_shift[6:0] end attribute \src "libresoc.v:185696.3-185707.6" process $proc$libresoc.v:185696$12065 assign { } { } assign $0\mr[63:0] $1\mr[63:0] attribute \src "libresoc.v:185697.5-185697.29" switch \initial attribute \src "libresoc.v:185697.9-185697.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\mr[63:0] \right_mask_mask attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\mr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \mr $0\mr[63:0] end attribute \src "libresoc.v:185708.3-185719.6" process $proc$libresoc.v:185708$12066 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] attribute \src "libresoc.v:185709.5-185709.29" switch \initial attribute \src "libresoc.v:185709.9-185709.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" switch \$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\output_mode[1:0] { 1'1 \$40 } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\output_mode[1:0] { 1'0 \$44 } end sync always update \output_mode $0\output_mode[1:0] end attribute \src "libresoc.v:185720.3-185738.6" process $proc$libresoc.v:185720$12067 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] attribute \src "libresoc.v:185721.5-185721.29" switch \initial attribute \src "libresoc.v:185721.9-185721.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" switch \output_mode attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\result_o[63:0] \$56 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\result_o[63:0] \$68 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\result_o[63:0] \$70 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\result_o[63:0] \$74 case assign $1\result_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \result_o $0\result_o[63:0] end attribute \src "libresoc.v:185739.3-185757.6" process $proc$libresoc.v:185739$12068 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] attribute \src "libresoc.v:185740.5-185740.29" switch \initial attribute \src "libresoc.v:185740.9-185740.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" switch \output_mode attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\carry_out_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\carry_out_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign $1\carry_out_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\carry_out_o[0:0] \$76 case assign $1\carry_out_o[0:0] 1'0 end sync always update \carry_out_o $0\carry_out_o[0:0] end attribute \src "libresoc.v:185758.3-185769.6" process $proc$libresoc.v:185758$12069 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] attribute \src "libresoc.v:185759.5-185759.29" switch \initial attribute \src "libresoc.v:185759.9-185759.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" switch \right_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rot_count[5:0] \$1 [5:0] attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\rot_count[5:0] \shift [5:0] end sync always update \rot_count $0\rot_count[5:0] end attribute \src "libresoc.v:185770.3-185803.6" process $proc$libresoc.v:185770$12070 assign { } { } assign $0\mb$8[6:0]$12071 $1\mb$8[6:0]$12072 attribute \src "libresoc.v:185771.5-185771.29" switch \initial attribute \src "libresoc.v:185771.9-185771.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" switch { \right_shift \clear_left } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\mb$8[6:0]$12072 [4:0] \$9 [4:0] assign $1\mb$8[6:0]$12072 [6:5] $2\mb$8[6:5]$12073 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\mb$8[6:5]$12073 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\mb$8[6:5]$12073 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\mb$8[6:0]$12072 [4:0] \sh [4:0] assign $1\mb$8[6:0]$12072 [6:5] $3\mb$8[6:5]$12074 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\mb$8[6:5]$12074 { \sh [5] \$11 } case assign $3\mb$8[6:5]$12074 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\mb$8[6:0]$12072 { 1'0 \is_32bit 5'00000 } end sync always update \mb$8 $0\mb$8[6:0]$12071 end attribute \src "libresoc.v:185804.3-185818.6" process $proc$libresoc.v:185804$12075 assign { } { } assign $0\me$13[6:0]$12076 $1\me$13[6:0]$12077 attribute \src "libresoc.v:185805.5-185805.29" switch \initial attribute \src "libresoc.v:185805.9-185805.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" switch { \$18 \$14 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\me$13[6:0]$12077 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $1\me$13[6:0]$12077 { 1'0 \mb_extra \mb } attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\me$13[6:0]$12077 { \sh [6] \$20 } end sync always update \me$13 $0\me$13[6:0]$12076 end connect \$9 $pos$libresoc.v:185620$12025_Y connect \$11 $not$libresoc.v:185621$12026_Y connect \$14 $and$libresoc.v:185622$12027_Y connect \$16 $not$libresoc.v:185623$12028_Y connect \$18 $and$libresoc.v:185624$12029_Y connect \$20 $not$libresoc.v:185625$12030_Y connect \$22 $le$libresoc.v:185626$12031_Y connect \$25 $sub$libresoc.v:185627$12032_Y connect \$27 $le$libresoc.v:185628$12033_Y connect \$2 $neg$libresoc.v:185629$12034_Y connect \$30 $sub$libresoc.v:185630$12035_Y connect \$32 $not$libresoc.v:185631$12036_Y connect \$34 $not$libresoc.v:185632$12037_Y connect \$36 $and$libresoc.v:185633$12038_Y connect \$38 $or$libresoc.v:185634$12039_Y connect \$40 $and$libresoc.v:185635$12040_Y connect \$42 $gt$libresoc.v:185636$12041_Y connect \$44 $and$libresoc.v:185637$12042_Y connect \$46 $and$libresoc.v:185638$12043_Y connect \$48 $and$libresoc.v:185639$12044_Y connect \$4 $not$libresoc.v:185640$12045_Y connect \$51 $and$libresoc.v:185641$12046_Y connect \$50 $not$libresoc.v:185642$12047_Y connect \$54 $and$libresoc.v:185643$12048_Y connect \$56 $or$libresoc.v:185644$12049_Y connect \$58 $or$libresoc.v:185645$12050_Y connect \$60 $and$libresoc.v:185646$12051_Y connect \$63 $or$libresoc.v:185647$12052_Y connect \$62 $not$libresoc.v:185648$12053_Y connect \$66 $and$libresoc.v:185649$12054_Y connect \$68 $or$libresoc.v:185650$12055_Y connect \$6 $and$libresoc.v:185651$12056_Y connect \$70 $and$libresoc.v:185652$12057_Y connect \$72 $not$libresoc.v:185653$12058_Y connect \$74 $or$libresoc.v:185654$12059_Y connect \$77 $not$libresoc.v:185655$12060_Y connect \$79 $and$libresoc.v:185656$12061_Y connect \$76 $reduce_or$libresoc.v:185657$12062_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 connect \ml \$32 connect \left_mask_shift \$30 [6:0] connect \sh { \$6 \shift [5:0] } connect \rot \rotl_o connect \rotl_b \rot_count connect \rotl_a \repl32 connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end attribute \src "libresoc.v:185834.1-185848.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl attribute \src "libresoc.v:185846.17-185846.32" wire width 128 $shr$libresoc.v:185846$12080_Y attribute \src "libresoc.v:185845.17-185845.100" wire width 8 $sub$libresoc.v:185845$12079_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" wire width 8 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o attribute \src "libresoc.v:185846.17-185846.32" cell $shr $shr$libresoc.v:185846$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 connect \Y $shr$libresoc.v:185846$12080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" cell $sub $sub$libresoc.v:185845$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b connect \Y $sub$libresoc.v:185845$12079_Y end connect \$2 $sub$libresoc.v:185845$12079_Y connect \$1 $shr$libresoc.v:185846$12080_Y [63:0] connect \o \$1 end attribute \src "libresoc.v:185852.1-185910.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l attribute \src "libresoc.v:185853.7-185853.20" wire $0\initial[0:0] attribute \src "libresoc.v:185898.3-185906.6" wire $0\q_int$next[0:0]$12091 attribute \src "libresoc.v:185896.3-185897.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185898.3-185906.6" wire $1\q_int$next[0:0]$12092 attribute \src "libresoc.v:185875.7-185875.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185888.17-185888.96" wire $and$libresoc.v:185888$12081_Y attribute \src "libresoc.v:185893.17-185893.96" wire $and$libresoc.v:185893$12086_Y attribute \src "libresoc.v:185890.18-185890.93" wire $not$libresoc.v:185890$12083_Y attribute \src "libresoc.v:185892.17-185892.92" wire $not$libresoc.v:185892$12085_Y attribute \src "libresoc.v:185895.17-185895.92" wire $not$libresoc.v:185895$12088_Y attribute \src "libresoc.v:185889.18-185889.98" wire $or$libresoc.v:185889$12082_Y attribute \src "libresoc.v:185891.18-185891.99" wire $or$libresoc.v:185891$12084_Y attribute \src "libresoc.v:185894.17-185894.97" wire $or$libresoc.v:185894$12087_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185853.7-185853.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185888$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185888$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185893$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185893$12086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185890$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:185890$12083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185892$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:185892$12085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185895$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:185895$12088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185889$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:185889$12082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185891$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:185891$12084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185894$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:185894$12087_Y end attribute \src "libresoc.v:185853.7-185853.20" process $proc$libresoc.v:185853$12093 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185875.7-185875.19" process $proc$libresoc.v:185875$12094 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185896.3-185897.27" process $proc$libresoc.v:185896$12089 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185898.3-185906.6" process $proc$libresoc.v:185898$12090 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12091 $1\q_int$next[0:0]$12092 attribute \src "libresoc.v:185899.5-185899.29" switch \initial attribute \src "libresoc.v:185899.9-185899.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12092 1'0 case assign $1\q_int$next[0:0]$12092 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12091 end connect \$9 $and$libresoc.v:185888$12081_Y connect \$11 $or$libresoc.v:185889$12082_Y connect \$13 $not$libresoc.v:185890$12083_Y connect \$15 $or$libresoc.v:185891$12084_Y connect \$1 $not$libresoc.v:185892$12085_Y connect \$3 $and$libresoc.v:185893$12086_Y connect \$5 $or$libresoc.v:185894$12087_Y connect \$7 $not$libresoc.v:185895$12088_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:185914.1-185972.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 attribute \src "libresoc.v:185915.7-185915.20" wire $0\initial[0:0] attribute \src "libresoc.v:185960.3-185968.6" wire $0\q_int$next[0:0]$12105 attribute \src "libresoc.v:185958.3-185959.27" wire $0\q_int[0:0] attribute \src "libresoc.v:185960.3-185968.6" wire $1\q_int$next[0:0]$12106 attribute \src "libresoc.v:185937.7-185937.19" wire $1\q_int[0:0] attribute \src "libresoc.v:185950.17-185950.96" wire $and$libresoc.v:185950$12095_Y attribute \src "libresoc.v:185955.17-185955.96" wire $and$libresoc.v:185955$12100_Y attribute \src "libresoc.v:185952.18-185952.93" wire $not$libresoc.v:185952$12097_Y attribute \src "libresoc.v:185954.17-185954.92" wire $not$libresoc.v:185954$12099_Y attribute \src "libresoc.v:185957.17-185957.92" wire $not$libresoc.v:185957$12102_Y attribute \src "libresoc.v:185951.18-185951.98" wire $or$libresoc.v:185951$12096_Y attribute \src "libresoc.v:185953.18-185953.99" wire $or$libresoc.v:185953$12098_Y attribute \src "libresoc.v:185956.17-185956.97" wire $or$libresoc.v:185956$12101_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185915.7-185915.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:185950$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:185950$12095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:185955$12100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:185955$12100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:185952$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:185952$12097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:185954$12099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:185954$12099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:185957$12102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:185957$12102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:185951$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:185951$12096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:185953$12098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:185953$12098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:185956$12101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:185956$12101_Y end attribute \src "libresoc.v:185915.7-185915.20" process $proc$libresoc.v:185915$12107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185937.7-185937.19" process $proc$libresoc.v:185937$12108 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:185958.3-185959.27" process $proc$libresoc.v:185958$12103 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:185960.3-185968.6" process $proc$libresoc.v:185960$12104 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12105 $1\q_int$next[0:0]$12106 attribute \src "libresoc.v:185961.5-185961.29" switch \initial attribute \src "libresoc.v:185961.9-185961.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12106 1'0 case assign $1\q_int$next[0:0]$12106 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12105 end connect \$9 $and$libresoc.v:185950$12095_Y connect \$11 $or$libresoc.v:185951$12096_Y connect \$13 $not$libresoc.v:185952$12097_Y connect \$15 $or$libresoc.v:185953$12098_Y connect \$1 $not$libresoc.v:185954$12099_Y connect \$3 $and$libresoc.v:185955$12100_Y connect \$5 $or$libresoc.v:185956$12101_Y connect \$7 $not$libresoc.v:185957$12102_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:185976.1-186034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 attribute \src "libresoc.v:185977.7-185977.20" wire $0\initial[0:0] attribute \src "libresoc.v:186022.3-186030.6" wire $0\q_int$next[0:0]$12119 attribute \src "libresoc.v:186020.3-186021.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186022.3-186030.6" wire $1\q_int$next[0:0]$12120 attribute \src "libresoc.v:185999.7-185999.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186012.17-186012.96" wire $and$libresoc.v:186012$12109_Y attribute \src "libresoc.v:186017.17-186017.96" wire $and$libresoc.v:186017$12114_Y attribute \src "libresoc.v:186014.18-186014.93" wire $not$libresoc.v:186014$12111_Y attribute \src "libresoc.v:186016.17-186016.92" wire $not$libresoc.v:186016$12113_Y attribute \src "libresoc.v:186019.17-186019.92" wire $not$libresoc.v:186019$12116_Y attribute \src "libresoc.v:186013.18-186013.98" wire $or$libresoc.v:186013$12110_Y attribute \src "libresoc.v:186015.18-186015.99" wire $or$libresoc.v:186015$12112_Y attribute \src "libresoc.v:186018.17-186018.97" wire $or$libresoc.v:186018$12115_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:185977.7-185977.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186012$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186012$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186017$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186017$12114_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186014$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186014$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186016$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186016$12113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186019$12116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186019$12116_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186013$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186013$12110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186015$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186015$12112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186018$12115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186018$12115_Y end attribute \src "libresoc.v:185977.7-185977.20" process $proc$libresoc.v:185977$12121 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:185999.7-185999.19" process $proc$libresoc.v:185999$12122 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186020.3-186021.27" process $proc$libresoc.v:186020$12117 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186022.3-186030.6" process $proc$libresoc.v:186022$12118 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12119 $1\q_int$next[0:0]$12120 attribute \src "libresoc.v:186023.5-186023.29" switch \initial attribute \src "libresoc.v:186023.9-186023.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12120 1'0 case assign $1\q_int$next[0:0]$12120 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12119 end connect \$9 $and$libresoc.v:186012$12109_Y connect \$11 $or$libresoc.v:186013$12110_Y connect \$13 $not$libresoc.v:186014$12111_Y connect \$15 $or$libresoc.v:186015$12112_Y connect \$1 $not$libresoc.v:186016$12113_Y connect \$3 $and$libresoc.v:186017$12114_Y connect \$5 $or$libresoc.v:186018$12115_Y connect \$7 $not$libresoc.v:186019$12116_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186038.1-186096.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 attribute \src "libresoc.v:186039.7-186039.20" wire $0\initial[0:0] attribute \src "libresoc.v:186084.3-186092.6" wire $0\q_int$next[0:0]$12133 attribute \src "libresoc.v:186082.3-186083.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186084.3-186092.6" wire $1\q_int$next[0:0]$12134 attribute \src "libresoc.v:186061.7-186061.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186074.17-186074.96" wire $and$libresoc.v:186074$12123_Y attribute \src "libresoc.v:186079.17-186079.96" wire $and$libresoc.v:186079$12128_Y attribute \src "libresoc.v:186076.18-186076.93" wire $not$libresoc.v:186076$12125_Y attribute \src "libresoc.v:186078.17-186078.92" wire $not$libresoc.v:186078$12127_Y attribute \src "libresoc.v:186081.17-186081.92" wire $not$libresoc.v:186081$12130_Y attribute \src "libresoc.v:186075.18-186075.98" wire $or$libresoc.v:186075$12124_Y attribute \src "libresoc.v:186077.18-186077.99" wire $or$libresoc.v:186077$12126_Y attribute \src "libresoc.v:186080.17-186080.97" wire $or$libresoc.v:186080$12129_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:186039.7-186039.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186074$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186074$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186079$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186079$12128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186076$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186076$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186078$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186078$12127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186081$12130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186081$12130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186075$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186075$12124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186077$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186077$12126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186080$12129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186080$12129_Y end attribute \src "libresoc.v:186039.7-186039.20" process $proc$libresoc.v:186039$12135 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186061.7-186061.19" process $proc$libresoc.v:186061$12136 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186082.3-186083.27" process $proc$libresoc.v:186082$12131 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186084.3-186092.6" process $proc$libresoc.v:186084$12132 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12133 $1\q_int$next[0:0]$12134 attribute \src "libresoc.v:186085.5-186085.29" switch \initial attribute \src "libresoc.v:186085.9-186085.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12134 1'0 case assign $1\q_int$next[0:0]$12134 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12133 end connect \$9 $and$libresoc.v:186074$12123_Y connect \$11 $or$libresoc.v:186075$12124_Y connect \$13 $not$libresoc.v:186076$12125_Y connect \$15 $or$libresoc.v:186077$12126_Y connect \$1 $not$libresoc.v:186078$12127_Y connect \$3 $and$libresoc.v:186079$12128_Y connect \$5 $or$libresoc.v:186080$12129_Y connect \$7 $not$libresoc.v:186081$12130_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186100.1-186158.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 attribute \src "libresoc.v:186101.7-186101.20" wire $0\initial[0:0] attribute \src "libresoc.v:186146.3-186154.6" wire $0\q_int$next[0:0]$12147 attribute \src "libresoc.v:186144.3-186145.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186146.3-186154.6" wire $1\q_int$next[0:0]$12148 attribute \src "libresoc.v:186123.7-186123.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186136.17-186136.96" wire $and$libresoc.v:186136$12137_Y attribute \src "libresoc.v:186141.17-186141.96" wire $and$libresoc.v:186141$12142_Y attribute \src "libresoc.v:186138.18-186138.93" wire $not$libresoc.v:186138$12139_Y attribute \src "libresoc.v:186140.17-186140.92" wire $not$libresoc.v:186140$12141_Y attribute \src "libresoc.v:186143.17-186143.92" wire $not$libresoc.v:186143$12144_Y attribute \src "libresoc.v:186137.18-186137.98" wire $or$libresoc.v:186137$12138_Y attribute \src "libresoc.v:186139.18-186139.99" wire $or$libresoc.v:186139$12140_Y attribute \src "libresoc.v:186142.17-186142.97" wire $or$libresoc.v:186142$12143_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:186101.7-186101.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186136$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186136$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186141$12142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186141$12142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186138$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186138$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186140$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186140$12141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186143$12144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186143$12144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186137$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186137$12138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186139$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186139$12140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186142$12143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186142$12143_Y end attribute \src "libresoc.v:186101.7-186101.20" process $proc$libresoc.v:186101$12149 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186123.7-186123.19" process $proc$libresoc.v:186123$12150 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186144.3-186145.27" process $proc$libresoc.v:186144$12145 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186146.3-186154.6" process $proc$libresoc.v:186146$12146 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12147 $1\q_int$next[0:0]$12148 attribute \src "libresoc.v:186147.5-186147.29" switch \initial attribute \src "libresoc.v:186147.9-186147.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12148 1'0 case assign $1\q_int$next[0:0]$12148 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12147 end connect \$9 $and$libresoc.v:186136$12137_Y connect \$11 $or$libresoc.v:186137$12138_Y connect \$13 $not$libresoc.v:186138$12139_Y connect \$15 $or$libresoc.v:186139$12140_Y connect \$1 $not$libresoc.v:186140$12141_Y connect \$3 $and$libresoc.v:186141$12142_Y connect \$5 $or$libresoc.v:186142$12143_Y connect \$7 $not$libresoc.v:186143$12144_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186162.1-186220.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 attribute \src "libresoc.v:186163.7-186163.20" wire $0\initial[0:0] attribute \src "libresoc.v:186208.3-186216.6" wire $0\q_int$next[0:0]$12161 attribute \src "libresoc.v:186206.3-186207.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186208.3-186216.6" wire $1\q_int$next[0:0]$12162 attribute \src "libresoc.v:186185.7-186185.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186198.17-186198.96" wire $and$libresoc.v:186198$12151_Y attribute \src "libresoc.v:186203.17-186203.96" wire $and$libresoc.v:186203$12156_Y attribute \src "libresoc.v:186200.18-186200.93" wire $not$libresoc.v:186200$12153_Y attribute \src "libresoc.v:186202.17-186202.92" wire $not$libresoc.v:186202$12155_Y attribute \src "libresoc.v:186205.17-186205.92" wire $not$libresoc.v:186205$12158_Y attribute \src "libresoc.v:186199.18-186199.98" wire $or$libresoc.v:186199$12152_Y attribute \src "libresoc.v:186201.18-186201.99" wire $or$libresoc.v:186201$12154_Y attribute \src "libresoc.v:186204.17-186204.97" wire $or$libresoc.v:186204$12157_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:186163.7-186163.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186198$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186198$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186203$12156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186203$12156_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186200$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186200$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186202$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186202$12155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186205$12158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186205$12158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186199$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186199$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186201$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186201$12154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186204$12157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186204$12157_Y end attribute \src "libresoc.v:186163.7-186163.20" process $proc$libresoc.v:186163$12163 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186185.7-186185.19" process $proc$libresoc.v:186185$12164 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186206.3-186207.27" process $proc$libresoc.v:186206$12159 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186208.3-186216.6" process $proc$libresoc.v:186208$12160 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12161 $1\q_int$next[0:0]$12162 attribute \src "libresoc.v:186209.5-186209.29" switch \initial attribute \src "libresoc.v:186209.9-186209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12162 1'0 case assign $1\q_int$next[0:0]$12162 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12161 end connect \$9 $and$libresoc.v:186198$12151_Y connect \$11 $or$libresoc.v:186199$12152_Y connect \$13 $not$libresoc.v:186200$12153_Y connect \$15 $or$libresoc.v:186201$12154_Y connect \$1 $not$libresoc.v:186202$12155_Y connect \$3 $and$libresoc.v:186203$12156_Y connect \$5 $or$libresoc.v:186204$12157_Y connect \$7 $not$libresoc.v:186205$12158_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186224.1-186282.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 attribute \src "libresoc.v:186225.7-186225.20" wire $0\initial[0:0] attribute \src "libresoc.v:186270.3-186278.6" wire $0\q_int$next[0:0]$12175 attribute \src "libresoc.v:186268.3-186269.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186270.3-186278.6" wire $1\q_int$next[0:0]$12176 attribute \src "libresoc.v:186247.7-186247.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186260.17-186260.96" wire $and$libresoc.v:186260$12165_Y attribute \src "libresoc.v:186265.17-186265.96" wire $and$libresoc.v:186265$12170_Y attribute \src "libresoc.v:186262.18-186262.93" wire $not$libresoc.v:186262$12167_Y attribute \src "libresoc.v:186264.17-186264.92" wire $not$libresoc.v:186264$12169_Y attribute \src "libresoc.v:186267.17-186267.92" wire $not$libresoc.v:186267$12172_Y attribute \src "libresoc.v:186261.18-186261.98" wire $or$libresoc.v:186261$12166_Y attribute \src "libresoc.v:186263.18-186263.99" wire $or$libresoc.v:186263$12168_Y attribute \src "libresoc.v:186266.17-186266.97" wire $or$libresoc.v:186266$12171_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:186225.7-186225.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186260$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186260$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186265$12170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186265$12170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186262$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186262$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186264$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186264$12169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186267$12172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186267$12172_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186261$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186261$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186263$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186263$12168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186266$12171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186266$12171_Y end attribute \src "libresoc.v:186225.7-186225.20" process $proc$libresoc.v:186225$12177 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186247.7-186247.19" process $proc$libresoc.v:186247$12178 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186268.3-186269.27" process $proc$libresoc.v:186268$12173 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186270.3-186278.6" process $proc$libresoc.v:186270$12174 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12175 $1\q_int$next[0:0]$12176 attribute \src "libresoc.v:186271.5-186271.29" switch \initial attribute \src "libresoc.v:186271.9-186271.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12176 1'0 case assign $1\q_int$next[0:0]$12176 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12175 end connect \$9 $and$libresoc.v:186260$12165_Y connect \$11 $or$libresoc.v:186261$12166_Y connect \$13 $not$libresoc.v:186262$12167_Y connect \$15 $or$libresoc.v:186263$12168_Y connect \$1 $not$libresoc.v:186264$12169_Y connect \$3 $and$libresoc.v:186265$12170_Y connect \$5 $or$libresoc.v:186266$12171_Y connect \$7 $not$libresoc.v:186267$12172_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186286.1-186344.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 attribute \src "libresoc.v:186287.7-186287.20" wire $0\initial[0:0] attribute \src "libresoc.v:186332.3-186340.6" wire $0\q_int$next[0:0]$12189 attribute \src "libresoc.v:186330.3-186331.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186332.3-186340.6" wire $1\q_int$next[0:0]$12190 attribute \src "libresoc.v:186309.7-186309.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186322.17-186322.96" wire $and$libresoc.v:186322$12179_Y attribute \src "libresoc.v:186327.17-186327.96" wire $and$libresoc.v:186327$12184_Y attribute \src "libresoc.v:186324.18-186324.93" wire $not$libresoc.v:186324$12181_Y attribute \src "libresoc.v:186326.17-186326.92" wire $not$libresoc.v:186326$12183_Y attribute \src "libresoc.v:186329.17-186329.92" wire $not$libresoc.v:186329$12186_Y attribute \src "libresoc.v:186323.18-186323.98" wire $or$libresoc.v:186323$12180_Y attribute \src "libresoc.v:186325.18-186325.99" wire $or$libresoc.v:186325$12182_Y attribute \src "libresoc.v:186328.17-186328.97" wire $or$libresoc.v:186328$12185_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:186287.7-186287.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186322$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186322$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186327$12184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186327$12184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186324$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186324$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186326$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186326$12183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186329$12186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186329$12186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186323$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186323$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186325$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186325$12182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186328$12185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186328$12185_Y end attribute \src "libresoc.v:186287.7-186287.20" process $proc$libresoc.v:186287$12191 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186309.7-186309.19" process $proc$libresoc.v:186309$12192 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186330.3-186331.27" process $proc$libresoc.v:186330$12187 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186332.3-186340.6" process $proc$libresoc.v:186332$12188 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12189 $1\q_int$next[0:0]$12190 attribute \src "libresoc.v:186333.5-186333.29" switch \initial attribute \src "libresoc.v:186333.9-186333.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12190 1'0 case assign $1\q_int$next[0:0]$12190 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12189 end connect \$9 $and$libresoc.v:186322$12179_Y connect \$11 $or$libresoc.v:186323$12180_Y connect \$13 $not$libresoc.v:186324$12181_Y connect \$15 $or$libresoc.v:186325$12182_Y connect \$1 $not$libresoc.v:186326$12183_Y connect \$3 $and$libresoc.v:186327$12184_Y connect \$5 $or$libresoc.v:186328$12185_Y connect \$7 $not$libresoc.v:186329$12186_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186348.1-186406.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 attribute \src "libresoc.v:186349.7-186349.20" wire $0\initial[0:0] attribute \src "libresoc.v:186394.3-186402.6" wire $0\q_int$next[0:0]$12203 attribute \src "libresoc.v:186392.3-186393.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186394.3-186402.6" wire $1\q_int$next[0:0]$12204 attribute \src "libresoc.v:186371.7-186371.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186384.17-186384.96" wire $and$libresoc.v:186384$12193_Y attribute \src "libresoc.v:186389.17-186389.96" wire $and$libresoc.v:186389$12198_Y attribute \src "libresoc.v:186386.18-186386.93" wire $not$libresoc.v:186386$12195_Y attribute \src "libresoc.v:186388.17-186388.92" wire $not$libresoc.v:186388$12197_Y attribute \src "libresoc.v:186391.17-186391.92" wire $not$libresoc.v:186391$12200_Y attribute \src "libresoc.v:186385.18-186385.98" wire $or$libresoc.v:186385$12194_Y attribute \src "libresoc.v:186387.18-186387.99" wire $or$libresoc.v:186387$12196_Y attribute \src "libresoc.v:186390.17-186390.97" wire $or$libresoc.v:186390$12199_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:186349.7-186349.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186384$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186384$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186389$12198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186389$12198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186386$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186386$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186388$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186388$12197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186391$12200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186391$12200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186385$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186385$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186387$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186387$12196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186390$12199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186390$12199_Y end attribute \src "libresoc.v:186349.7-186349.20" process $proc$libresoc.v:186349$12205 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186371.7-186371.19" process $proc$libresoc.v:186371$12206 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186392.3-186393.27" process $proc$libresoc.v:186392$12201 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186394.3-186402.6" process $proc$libresoc.v:186394$12202 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12203 $1\q_int$next[0:0]$12204 attribute \src "libresoc.v:186395.5-186395.29" switch \initial attribute \src "libresoc.v:186395.9-186395.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12204 1'0 case assign $1\q_int$next[0:0]$12204 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12203 end connect \$9 $and$libresoc.v:186384$12193_Y connect \$11 $or$libresoc.v:186385$12194_Y connect \$13 $not$libresoc.v:186386$12195_Y connect \$15 $or$libresoc.v:186387$12196_Y connect \$1 $not$libresoc.v:186388$12197_Y connect \$3 $and$libresoc.v:186389$12198_Y connect \$5 $or$libresoc.v:186390$12199_Y connect \$7 $not$libresoc.v:186391$12200_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186410.1-186468.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 attribute \src "libresoc.v:186411.7-186411.20" wire $0\initial[0:0] attribute \src "libresoc.v:186456.3-186464.6" wire $0\q_int$next[0:0]$12217 attribute \src "libresoc.v:186454.3-186455.27" wire $0\q_int[0:0] attribute \src "libresoc.v:186456.3-186464.6" wire $1\q_int$next[0:0]$12218 attribute \src "libresoc.v:186433.7-186433.19" wire $1\q_int[0:0] attribute \src "libresoc.v:186446.17-186446.96" wire $and$libresoc.v:186446$12207_Y attribute \src "libresoc.v:186451.17-186451.96" wire $and$libresoc.v:186451$12212_Y attribute \src "libresoc.v:186448.18-186448.93" wire $not$libresoc.v:186448$12209_Y attribute \src "libresoc.v:186450.17-186450.92" wire $not$libresoc.v:186450$12211_Y attribute \src "libresoc.v:186453.17-186453.92" wire $not$libresoc.v:186453$12214_Y attribute \src "libresoc.v:186447.18-186447.98" wire $or$libresoc.v:186447$12208_Y attribute \src "libresoc.v:186449.18-186449.99" wire $or$libresoc.v:186449$12210_Y attribute \src "libresoc.v:186452.17-186452.97" wire $or$libresoc.v:186452$12213_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:186411.7-186411.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \q_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:186446$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:186446$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:186451$12212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:186451$12212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:186448$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \Y $not$libresoc.v:186448$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:186450$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186450$12211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:186453$12214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst connect \Y $not$libresoc.v:186453$12214_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:186447$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst connect \Y $or$libresoc.v:186447$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:186449$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int connect \Y $or$libresoc.v:186449$12210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:186452$12213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst connect \Y $or$libresoc.v:186452$12213_Y end attribute \src "libresoc.v:186411.7-186411.20" process $proc$libresoc.v:186411$12219 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186433.7-186433.19" process $proc$libresoc.v:186433$12220 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:186454.3-186455.27" process $proc$libresoc.v:186454$12215 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:186456.3-186464.6" process $proc$libresoc.v:186456$12216 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12217 $1\q_int$next[0:0]$12218 attribute \src "libresoc.v:186457.5-186457.29" switch \initial attribute \src "libresoc.v:186457.9-186457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$12218 1'0 case assign $1\q_int$next[0:0]$12218 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$12217 end connect \$9 $and$libresoc.v:186446$12207_Y connect \$11 $or$libresoc.v:186447$12208_Y connect \$13 $not$libresoc.v:186448$12209_Y connect \$15 $or$libresoc.v:186449$12210_Y connect \$1 $not$libresoc.v:186450$12211_Y connect \$3 $and$libresoc.v:186451$12212_Y connect \$5 $or$libresoc.v:186452$12213_Y connect \$7 $not$libresoc.v:186453$12214_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end attribute \src "libresoc.v:186472.1-186881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage attribute \src "libresoc.v:186839.3-186864.6" wire width 128 $0\dividend[127:0] attribute \src "libresoc.v:186473.7-186473.20" wire $0\initial[0:0] attribute \src "libresoc.v:186839.3-186864.6" wire width 128 $1\dividend[127:0] attribute \src "libresoc.v:186839.3-186864.6" wire width 128 $2\dividend[127:0] attribute \src "libresoc.v:186818.18-186818.122" wire $and$libresoc.v:186818$12222_Y attribute \src "libresoc.v:186820.18-186820.122" wire $and$libresoc.v:186820$12224_Y attribute \src "libresoc.v:186829.18-186829.105" wire $and$libresoc.v:186829$12237_Y attribute \src "libresoc.v:186832.18-186832.105" wire $and$libresoc.v:186832$12240_Y attribute \src "libresoc.v:186828.18-186828.123" wire $eq$libresoc.v:186828$12236_Y attribute \src "libresoc.v:186831.18-186831.123" wire $eq$libresoc.v:186831$12239_Y attribute \src "libresoc.v:186834.18-186834.117" wire $eq$libresoc.v:186834$12242_Y attribute \src "libresoc.v:186821.18-186821.97" wire width 65 $extend$libresoc.v:186821$12225_Y attribute \src "libresoc.v:186822.18-186822.91" wire width 65 $extend$libresoc.v:186822$12227_Y attribute \src "libresoc.v:186824.18-186824.97" wire width 65 $extend$libresoc.v:186824$12230_Y attribute \src "libresoc.v:186825.18-186825.91" wire width 65 $extend$libresoc.v:186825$12232_Y attribute \src "libresoc.v:186837.18-186837.99" wire width 128 $extend$libresoc.v:186837$12245_Y attribute \src "libresoc.v:186827.18-186827.112" wire $ge$libresoc.v:186827$12235_Y attribute \src "libresoc.v:186830.18-186830.124" wire $ge$libresoc.v:186830$12238_Y attribute \src "libresoc.v:186821.18-186821.97" wire width 65 $neg$libresoc.v:186821$12226_Y attribute \src "libresoc.v:186824.18-186824.97" wire width 65 $neg$libresoc.v:186824$12231_Y attribute \src "libresoc.v:186822.18-186822.91" wire width 65 $pos$libresoc.v:186822$12228_Y attribute \src "libresoc.v:186825.18-186825.91" wire width 65 $pos$libresoc.v:186825$12233_Y attribute \src "libresoc.v:186837.18-186837.99" wire width 128 $pos$libresoc.v:186837$12246_Y attribute \src "libresoc.v:186836.18-186836.117" wire width 95 $sshl$libresoc.v:186836$12244_Y attribute \src "libresoc.v:186838.18-186838.111" wire width 191 $sshl$libresoc.v:186838$12247_Y attribute \src "libresoc.v:186817.18-186817.131" wire $ternary$libresoc.v:186817$12221_Y attribute \src "libresoc.v:186819.18-186819.131" wire $ternary$libresoc.v:186819$12223_Y attribute \src "libresoc.v:186823.18-186823.119" wire width 65 $ternary$libresoc.v:186823$12229_Y attribute \src "libresoc.v:186826.18-186826.120" wire width 65 $ternary$libresoc.v:186826$12234_Y attribute \src "libresoc.v:186833.18-186833.130" wire width 32 $ternary$libresoc.v:186833$12241_Y attribute \src "libresoc.v:186835.18-186835.131" wire width 32 $ternary$libresoc.v:186835$12243_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" wire width 65 \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" wire width 65 \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 65 \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" wire width 65 \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" wire width 65 \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" wire width 65 \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 65 \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" wire width 65 \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" wire \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" wire \$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" wire \$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" wire width 32 \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" wire width 128 \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" wire width 95 \$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" wire width 191 \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" wire width 191 \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" wire width 64 \abs_dend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" wire width 64 \abs_dor attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 46 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" wire output 44 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" wire output 45 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" wire width 128 output 47 \dividend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" wire output 43 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand attribute \src "libresoc.v:186473.7-186473.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 26 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 11 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 output 33 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 40 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 36 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 35 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 32 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 50 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 22 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" wire width 2 output 49 \operation attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" cell $and $and$libresoc.v:186818$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed connect \Y $and$libresoc.v:186818$12222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" cell $and $and$libresoc.v:186820$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed connect \Y $and$libresoc.v:186820$12224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" cell $and $and$libresoc.v:186829$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 connect \Y $and$libresoc.v:186829$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" cell $and $and$libresoc.v:186832$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 connect \Y $and$libresoc.v:186832$12240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" cell $eq $eq$libresoc.v:186828$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 connect \Y $eq$libresoc.v:186828$12236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" cell $eq $eq$libresoc.v:186831$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 connect \Y $eq$libresoc.v:186831$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" cell $eq $eq$libresoc.v:186834$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 connect \Y $eq$libresoc.v:186834$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" cell $pos $extend$libresoc.v:186821$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb connect \Y $extend$libresoc.v:186821$12225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:186822$12227 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb connect \Y $extend$libresoc.v:186822$12227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" cell $pos $extend$libresoc.v:186824$12230 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra connect \Y $extend$libresoc.v:186824$12230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $extend$libresoc.v:186825$12232 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra connect \Y $extend$libresoc.v:186825$12232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" cell $pos $extend$libresoc.v:186837$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 connect \Y $extend$libresoc.v:186837$12245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" cell $ge $ge$libresoc.v:186827$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor connect \Y $ge$libresoc.v:186827$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" cell $ge $ge$libresoc.v:186830$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] connect \Y $ge$libresoc.v:186830$12238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" cell $neg $neg$libresoc.v:186821$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:186821$12225_Y connect \Y $neg$libresoc.v:186821$12226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" cell $neg $neg$libresoc.v:186824$12231 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:186824$12230_Y connect \Y $neg$libresoc.v:186824$12231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:186822$12228 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:186822$12227_Y connect \Y $pos$libresoc.v:186822$12228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" cell $pos $pos$libresoc.v:186825$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 connect \A $extend$libresoc.v:186825$12232_Y connect \Y $pos$libresoc.v:186825$12233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" cell $pos $pos$libresoc.v:186837$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 connect \A $extend$libresoc.v:186837$12245_Y connect \Y $pos$libresoc.v:186837$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" cell $sshl $sshl$libresoc.v:186836$12244 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 connect \Y $sshl$libresoc.v:186836$12244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" cell $sshl $sshl$libresoc.v:186838$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 connect \Y $sshl$libresoc.v:186838$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" cell $mux $ternary$libresoc.v:186817$12221 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit connect \Y $ternary$libresoc.v:186817$12221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" cell $mux $ternary$libresoc.v:186819$12223 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit connect \Y $ternary$libresoc.v:186819$12223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" cell $mux $ternary$libresoc.v:186823$12229 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg connect \Y $ternary$libresoc.v:186823$12229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" cell $mux $ternary$libresoc.v:186826$12234 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg connect \Y $ternary$libresoc.v:186826$12234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" cell $mux $ternary$libresoc.v:186833$12241 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit connect \Y $ternary$libresoc.v:186833$12241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" cell $mux $ternary$libresoc.v:186835$12243 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit connect \Y $ternary$libresoc.v:186835$12243_Y end attribute \src "libresoc.v:186473.7-186473.20" process $proc$libresoc.v:186473$12249 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:186839.3-186864.6" process $proc$libresoc.v:186839$12248 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] attribute \src "libresoc.v:186840.5-186840.29" switch \initial attribute \src "libresoc.v:186840.9-186840.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0011101 , 7'0101111 assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\dividend[127:0] [31:0] \abs_dend [31:0] assign $1\dividend[127:0] [63:32] \$59 attribute \src "libresoc.v:0.0-0.0" case 7'0011110 assign { } { } assign $1\dividend[127:0] $2\dividend[127:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dividend[127:0] \$61 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\dividend[127:0] \$65 [127:0] end case assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end sync always update \dividend $0\dividend[127:0] end connect \$21 $ternary$libresoc.v:186817$12221_Y connect \$23 $and$libresoc.v:186818$12222_Y connect \$25 $ternary$libresoc.v:186819$12223_Y connect \$27 $and$libresoc.v:186820$12224_Y connect \$30 $neg$libresoc.v:186821$12226_Y connect \$32 $pos$libresoc.v:186822$12228_Y connect \$34 $ternary$libresoc.v:186823$12229_Y connect \$37 $neg$libresoc.v:186824$12231_Y connect \$39 $pos$libresoc.v:186825$12233_Y connect \$41 $ternary$libresoc.v:186826$12234_Y connect \$43 $ge$libresoc.v:186827$12235_Y connect \$45 $eq$libresoc.v:186828$12236_Y connect \$47 $and$libresoc.v:186829$12237_Y connect \$49 $ge$libresoc.v:186830$12238_Y connect \$51 $eq$libresoc.v:186831$12239_Y connect \$53 $and$libresoc.v:186832$12240_Y connect \$55 $ternary$libresoc.v:186833$12241_Y connect \$57 $eq$libresoc.v:186834$12242_Y connect \$59 $ternary$libresoc.v:186835$12243_Y connect \$62 $sshl$libresoc.v:186836$12244_Y connect \$61 $pos$libresoc.v:186837$12246_Y connect \$66 $sshl$libresoc.v:186838$12247_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so connect \div_by_zero \$57 connect \divisor_radicand [63:32] \$55 connect \divisor_radicand [31:0] \abs_dor [31:0] connect \dive_abs_ov32 \$53 connect \dive_abs_ov64 \$47 connect \abs_dend \$41 [63:0] connect \abs_dor \$34 [63:0] connect \divisor_neg \$27 connect \dividend_neg \$23 connect \operation 2'01 end attribute \src "libresoc.v:186885.1-188092.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 attribute \src "libresoc.v:187663.3-187664.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:187661.3-187662.46" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:188012.3-188020.6" wire $0\alu_l_r_alu$next[0:0]$12467 attribute \src "libresoc.v:187579.3-187580.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12384 attribute \src "libresoc.v:187607.3-187608.75" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12385 attribute \src "libresoc.v:187609.3-187610.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12386 attribute \src "libresoc.v:187611.3-187612.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12387 attribute \src "libresoc.v:187625.3-187626.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12388 attribute \src "libresoc.v:187629.3-187630.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12389 attribute \src "libresoc.v:187637.3-187638.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12390 attribute \src "libresoc.v:187605.3-187606.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12391 attribute \src "libresoc.v:187623.3-187624.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12392 attribute \src "libresoc.v:187633.3-187634.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12393 attribute \src "libresoc.v:187635.3-187636.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12394 attribute \src "libresoc.v:187617.3-187618.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12395 attribute \src "libresoc.v:187619.3-187620.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12396 attribute \src "libresoc.v:187627.3-187628.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12397 attribute \src "libresoc.v:187631.3-187632.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12398 attribute \src "libresoc.v:187615.3-187616.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12399 attribute \src "libresoc.v:187613.3-187614.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12400 attribute \src "libresoc.v:187621.3-187622.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] attribute \src "libresoc.v:188003.3-188011.6" wire $0\alui_l_r_alui$next[0:0]$12464 attribute \src "libresoc.v:187581.3-187582.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:187887.3-187908.6" wire width 64 $0\data_r0__o$next[63:0]$12425 attribute \src "libresoc.v:187601.3-187602.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:187887.3-187908.6" wire $0\data_r0__o_ok$next[0:0]$12426 attribute \src "libresoc.v:187603.3-187604.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:187909.3-187930.6" wire width 4 $0\data_r1__cr_a$next[3:0]$12433 attribute \src "libresoc.v:187597.3-187598.43" wire width 4 $0\data_r1__cr_a[3:0] attribute \src "libresoc.v:187909.3-187930.6" wire $0\data_r1__cr_a_ok$next[0:0]$12434 attribute \src "libresoc.v:187599.3-187600.49" wire $0\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:187931.3-187952.6" wire width 2 $0\data_r2__xer_ca$next[1:0]$12441 attribute \src "libresoc.v:187593.3-187594.47" wire width 2 $0\data_r2__xer_ca[1:0] attribute \src "libresoc.v:187931.3-187952.6" wire $0\data_r2__xer_ca_ok$next[0:0]$12442 attribute \src "libresoc.v:187595.3-187596.53" wire $0\data_r2__xer_ca_ok[0:0] attribute \src "libresoc.v:188021.3-188030.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:188031.3-188040.6" wire width 4 $0\dest2_o[3:0] attribute \src "libresoc.v:188041.3-188050.6" wire width 2 $0\dest3_o[1:0] attribute \src "libresoc.v:186886.7-186886.20" wire $0\initial[0:0] attribute \src "libresoc.v:187804.3-187812.6" wire $0\opc_l_r_opc$next[0:0]$12369 attribute \src "libresoc.v:187647.3-187648.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:187795.3-187803.6" wire $0\opc_l_s_opc$next[0:0]$12366 attribute \src "libresoc.v:187649.3-187650.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:188051.3-188059.6" wire width 3 $0\prev_wr_go$next[2:0]$12473 attribute \src "libresoc.v:187659.3-187660.37" wire width 3 $0\prev_wr_go[2:0] attribute \src "libresoc.v:187749.3-187758.6" wire $0\req_done[0:0] attribute \src "libresoc.v:187840.3-187848.6" wire width 3 $0\req_l_r_req$next[2:0]$12381 attribute \src "libresoc.v:187639.3-187640.39" wire width 3 $0\req_l_r_req[2:0] attribute \src "libresoc.v:187831.3-187839.6" wire width 3 $0\req_l_s_req$next[2:0]$12378 attribute \src "libresoc.v:187641.3-187642.39" wire width 3 $0\req_l_s_req[2:0] attribute \src "libresoc.v:187768.3-187776.6" wire $0\rok_l_r_rdok$next[0:0]$12357 attribute \src "libresoc.v:187655.3-187656.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:187759.3-187767.6" wire $0\rok_l_s_rdok$next[0:0]$12354 attribute \src "libresoc.v:187657.3-187658.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:187786.3-187794.6" wire $0\rst_l_r_rst$next[0:0]$12363 attribute \src "libresoc.v:187651.3-187652.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:187777.3-187785.6" wire $0\rst_l_s_rst$next[0:0]$12360 attribute \src "libresoc.v:187653.3-187654.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:187822.3-187830.6" wire width 5 $0\src_l_r_src$next[4:0]$12375 attribute \src "libresoc.v:187643.3-187644.39" wire width 5 $0\src_l_r_src[4:0] attribute \src "libresoc.v:187813.3-187821.6" wire width 5 $0\src_l_s_src$next[4:0]$12372 attribute \src "libresoc.v:187645.3-187646.39" wire width 5 $0\src_l_s_src[4:0] attribute \src "libresoc.v:187953.3-187962.6" wire width 64 $0\src_r0$next[63:0]$12449 attribute \src "libresoc.v:187591.3-187592.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:187963.3-187972.6" wire width 64 $0\src_r1$next[63:0]$12452 attribute \src "libresoc.v:187589.3-187590.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:187973.3-187982.6" wire width 64 $0\src_r2$next[63:0]$12455 attribute \src "libresoc.v:187587.3-187588.29" wire width 64 $0\src_r2[63:0] attribute \src "libresoc.v:187983.3-187992.6" wire $0\src_r3$next[0:0]$12458 attribute \src "libresoc.v:187585.3-187586.29" wire $0\src_r3[0:0] attribute \src "libresoc.v:187993.3-188002.6" wire width 2 $0\src_r4$next[1:0]$12461 attribute \src "libresoc.v:187583.3-187584.29" wire width 2 $0\src_r4[1:0] attribute \src "libresoc.v:187008.7-187008.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:187018.7-187018.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:188012.3-188020.6" wire $1\alu_l_r_alu$next[0:0]$12468 attribute \src "libresoc.v:187026.7-187026.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 attribute \src "libresoc.v:187069.14-187069.54" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 attribute \src "libresoc.v:187073.14-187073.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 attribute \src "libresoc.v:187077.7-187077.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 attribute \src "libresoc.v:187085.13-187085.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 attribute \src "libresoc.v:187089.7-187089.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 attribute \src "libresoc.v:187093.14-187093.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 attribute \src "libresoc.v:187172.13-187172.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 attribute \src "libresoc.v:187176.7-187176.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 attribute \src "libresoc.v:187180.7-187180.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 attribute \src "libresoc.v:187184.7-187184.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 attribute \src "libresoc.v:187188.7-187188.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 attribute \src "libresoc.v:187192.7-187192.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 attribute \src "libresoc.v:187196.7-187196.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 attribute \src "libresoc.v:187200.7-187200.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 attribute \src "libresoc.v:187204.7-187204.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 attribute \src "libresoc.v:187208.7-187208.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] attribute \src "libresoc.v:187849.3-187886.6" wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 attribute \src "libresoc.v:187212.7-187212.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] attribute \src "libresoc.v:188003.3-188011.6" wire $1\alui_l_r_alui$next[0:0]$12465 attribute \src "libresoc.v:187224.7-187224.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:187887.3-187908.6" wire width 64 $1\data_r0__o$next[63:0]$12427 attribute \src "libresoc.v:187258.14-187258.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:187887.3-187908.6" wire $1\data_r0__o_ok$next[0:0]$12428 attribute \src "libresoc.v:187262.7-187262.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:187909.3-187930.6" wire width 4 $1\data_r1__cr_a$next[3:0]$12435 attribute \src "libresoc.v:187266.13-187266.33" wire width 4 $1\data_r1__cr_a[3:0] attribute \src "libresoc.v:187909.3-187930.6" wire $1\data_r1__cr_a_ok$next[0:0]$12436 attribute \src "libresoc.v:187270.7-187270.30" wire $1\data_r1__cr_a_ok[0:0] attribute \src "libresoc.v:187931.3-187952.6" wire width 2 $1\data_r2__xer_ca$next[1:0]$12443 attribute \src "libresoc.v:187274.13-187274.35" wire width 2 $1\data_r2__xer_ca[1:0] attribute \src "libresoc.v:187931.3-187952.6" wire $1\data_r2__xer_ca_ok$next[0:0]$12444 attribute \src "libresoc.v:187278.7-187278.32" wire $1\data_r2__xer_ca_ok[0:0] attribute \src "libresoc.v:188021.3-188030.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:188031.3-188040.6" wire width 4 $1\dest2_o[3:0] attribute \src "libresoc.v:188041.3-188050.6" wire width 2 $1\dest3_o[1:0] attribute \src "libresoc.v:187804.3-187812.6" wire $1\opc_l_r_opc$next[0:0]$12370 attribute \src "libresoc.v:187295.7-187295.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:187795.3-187803.6" wire $1\opc_l_s_opc$next[0:0]$12367 attribute \src "libresoc.v:187299.7-187299.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:188051.3-188059.6" wire width 3 $1\prev_wr_go$next[2:0]$12474 attribute \src "libresoc.v:187431.13-187431.30" wire width 3 $1\prev_wr_go[2:0] attribute \src "libresoc.v:187749.3-187758.6" wire $1\req_done[0:0] attribute \src "libresoc.v:187840.3-187848.6" wire width 3 $1\req_l_r_req$next[2:0]$12382 attribute \src "libresoc.v:187439.13-187439.31" wire width 3 $1\req_l_r_req[2:0] attribute \src "libresoc.v:187831.3-187839.6" wire width 3 $1\req_l_s_req$next[2:0]$12379 attribute \src "libresoc.v:187443.13-187443.31" wire width 3 $1\req_l_s_req[2:0] attribute \src "libresoc.v:187768.3-187776.6" wire $1\rok_l_r_rdok$next[0:0]$12358 attribute \src "libresoc.v:187455.7-187455.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:187759.3-187767.6" wire $1\rok_l_s_rdok$next[0:0]$12355 attribute \src "libresoc.v:187459.7-187459.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:187786.3-187794.6" wire $1\rst_l_r_rst$next[0:0]$12364 attribute \src "libresoc.v:187463.7-187463.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:187777.3-187785.6" wire $1\rst_l_s_rst$next[0:0]$12361 attribute \src "libresoc.v:187467.7-187467.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:187822.3-187830.6" wire width 5 $1\src_l_r_src$next[4:0]$12376 attribute \src "libresoc.v:187485.13-187485.32" wire width 5 $1\src_l_r_src[4:0] attribute \src "libresoc.v:187813.3-187821.6" wire width 5 $1\src_l_s_src$next[4:0]$12373 attribute \src "libresoc.v:187489.13-187489.32" wire width 5 $1\src_l_s_src[4:0] attribute \src "libresoc.v:187953.3-187962.6" wire width 64 $1\src_r0$next[63:0]$12450 attribute \src "libresoc.v:187495.14-187495.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:187963.3-187972.6" wire width 64 $1\src_r1$next[63:0]$12453 attribute \src "libresoc.v:187499.14-187499.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:187973.3-187982.6" wire width 64 $1\src_r2$next[63:0]$12456 attribute \src "libresoc.v:187503.14-187503.43" wire width 64 $1\src_r2[63:0] attribute \src "libresoc.v:187983.3-187992.6" wire $1\src_r3$next[0:0]$12459 attribute \src "libresoc.v:187507.7-187507.20" wire $1\src_r3[0:0] attribute \src "libresoc.v:187993.3-188002.6" wire width 2 $1\src_r4$next[1:0]$12462 attribute \src "libresoc.v:187511.13-187511.26" wire width 2 $1\src_r4[1:0] attribute \src "libresoc.v:187849.3-187886.6" wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 attribute \src "libresoc.v:187849.3-187886.6" wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 attribute \src "libresoc.v:187849.3-187886.6" wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 attribute \src "libresoc.v:187849.3-187886.6" wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 attribute \src "libresoc.v:187849.3-187886.6" wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 attribute \src "libresoc.v:187849.3-187886.6" wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 attribute \src "libresoc.v:187887.3-187908.6" wire width 64 $2\data_r0__o$next[63:0]$12429 attribute \src "libresoc.v:187887.3-187908.6" wire $2\data_r0__o_ok$next[0:0]$12430 attribute \src "libresoc.v:187909.3-187930.6" wire width 4 $2\data_r1__cr_a$next[3:0]$12437 attribute \src "libresoc.v:187909.3-187930.6" wire $2\data_r1__cr_a_ok$next[0:0]$12438 attribute \src "libresoc.v:187931.3-187952.6" wire width 2 $2\data_r2__xer_ca$next[1:0]$12445 attribute \src "libresoc.v:187931.3-187952.6" wire $2\data_r2__xer_ca_ok$next[0:0]$12446 attribute \src "libresoc.v:187887.3-187908.6" wire $3\data_r0__o_ok$next[0:0]$12431 attribute \src "libresoc.v:187909.3-187930.6" wire $3\data_r1__cr_a_ok$next[0:0]$12439 attribute \src "libresoc.v:187931.3-187952.6" wire $3\data_r2__xer_ca_ok$next[0:0]$12447 attribute \src "libresoc.v:187521.19-187521.114" wire width 5 $and$libresoc.v:187521$12251_Y attribute \src "libresoc.v:187522.19-187522.125" wire $and$libresoc.v:187522$12252_Y attribute \src "libresoc.v:187523.19-187523.125" wire $and$libresoc.v:187523$12253_Y attribute \src "libresoc.v:187524.19-187524.125" wire $and$libresoc.v:187524$12254_Y attribute \src "libresoc.v:187525.18-187525.110" wire $and$libresoc.v:187525$12255_Y attribute \src "libresoc.v:187526.19-187526.141" wire width 3 $and$libresoc.v:187526$12256_Y attribute \src "libresoc.v:187527.19-187527.121" wire width 3 $and$libresoc.v:187527$12257_Y attribute \src "libresoc.v:187528.19-187528.127" wire $and$libresoc.v:187528$12258_Y attribute \src "libresoc.v:187529.19-187529.127" wire $and$libresoc.v:187529$12259_Y attribute \src "libresoc.v:187530.19-187530.127" wire $and$libresoc.v:187530$12260_Y attribute \src "libresoc.v:187532.18-187532.98" wire $and$libresoc.v:187532$12262_Y attribute \src "libresoc.v:187534.18-187534.100" wire $and$libresoc.v:187534$12264_Y attribute \src "libresoc.v:187535.18-187535.149" wire width 3 $and$libresoc.v:187535$12265_Y attribute \src "libresoc.v:187537.18-187537.119" wire width 3 $and$libresoc.v:187537$12267_Y attribute \src "libresoc.v:187540.17-187540.123" wire $and$libresoc.v:187540$12270_Y attribute \src "libresoc.v:187541.18-187541.116" wire $and$libresoc.v:187541$12271_Y attribute \src "libresoc.v:187546.18-187546.113" wire $and$libresoc.v:187546$12276_Y attribute \src "libresoc.v:187547.18-187547.125" wire width 3 $and$libresoc.v:187547$12277_Y attribute \src "libresoc.v:187549.18-187549.112" wire $and$libresoc.v:187549$12279_Y attribute \src "libresoc.v:187551.18-187551.132" wire $and$libresoc.v:187551$12281_Y attribute \src "libresoc.v:187552.18-187552.132" wire $and$libresoc.v:187552$12282_Y attribute \src "libresoc.v:187553.18-187553.117" wire $and$libresoc.v:187553$12283_Y attribute \src "libresoc.v:187559.18-187559.136" wire $and$libresoc.v:187559$12289_Y attribute \src "libresoc.v:187560.18-187560.124" wire width 3 $and$libresoc.v:187560$12290_Y attribute \src "libresoc.v:187562.18-187562.116" wire $and$libresoc.v:187562$12292_Y attribute \src "libresoc.v:187563.18-187563.119" wire $and$libresoc.v:187563$12293_Y attribute \src "libresoc.v:187564.18-187564.121" wire $and$libresoc.v:187564$12294_Y attribute \src "libresoc.v:187574.18-187574.140" wire $and$libresoc.v:187574$12304_Y attribute \src "libresoc.v:187575.18-187575.138" wire $and$libresoc.v:187575$12305_Y attribute \src "libresoc.v:187576.18-187576.171" wire width 5 $and$libresoc.v:187576$12306_Y attribute \src "libresoc.v:187578.18-187578.129" wire width 5 $and$libresoc.v:187578$12308_Y attribute \src "libresoc.v:187548.18-187548.113" wire $eq$libresoc.v:187548$12278_Y attribute \src "libresoc.v:187550.18-187550.119" wire $eq$libresoc.v:187550$12280_Y attribute \src "libresoc.v:187520.19-187520.115" wire width 5 $not$libresoc.v:187520$12250_Y attribute \src "libresoc.v:187531.18-187531.97" wire $not$libresoc.v:187531$12261_Y attribute \src "libresoc.v:187533.18-187533.99" wire $not$libresoc.v:187533$12263_Y attribute \src "libresoc.v:187536.18-187536.113" wire width 3 $not$libresoc.v:187536$12266_Y attribute \src "libresoc.v:187539.18-187539.106" wire $not$libresoc.v:187539$12269_Y attribute \src "libresoc.v:187545.18-187545.126" wire $not$libresoc.v:187545$12275_Y attribute \src "libresoc.v:187556.17-187556.113" wire width 5 $not$libresoc.v:187556$12286_Y attribute \src "libresoc.v:187577.18-187577.136" wire $not$libresoc.v:187577$12307_Y attribute \src "libresoc.v:187544.18-187544.112" wire $or$libresoc.v:187544$12274_Y attribute \src "libresoc.v:187554.18-187554.122" wire $or$libresoc.v:187554$12284_Y attribute \src "libresoc.v:187555.18-187555.124" wire $or$libresoc.v:187555$12285_Y attribute \src "libresoc.v:187557.18-187557.155" wire width 3 $or$libresoc.v:187557$12287_Y attribute \src "libresoc.v:187558.18-187558.181" wire width 5 $or$libresoc.v:187558$12288_Y attribute \src "libresoc.v:187561.18-187561.120" wire width 3 $or$libresoc.v:187561$12291_Y attribute \src "libresoc.v:187567.17-187567.117" wire width 5 $or$libresoc.v:187567$12297_Y attribute \src "libresoc.v:187573.17-187573.104" wire $reduce_and$libresoc.v:187573$12303_Y attribute \src "libresoc.v:187538.18-187538.106" wire $reduce_or$libresoc.v:187538$12268_Y attribute \src "libresoc.v:187542.18-187542.113" wire $reduce_or$libresoc.v:187542$12272_Y attribute \src "libresoc.v:187543.18-187543.112" wire $reduce_or$libresoc.v:187543$12273_Y attribute \src "libresoc.v:187565.18-187565.165" wire $ternary$libresoc.v:187565$12295_Y attribute \src "libresoc.v:187566.18-187566.182" wire width 64 $ternary$libresoc.v:187566$12296_Y attribute \src "libresoc.v:187568.18-187568.118" wire width 64 $ternary$libresoc.v:187568$12298_Y attribute \src "libresoc.v:187569.18-187569.115" wire width 64 $ternary$libresoc.v:187569$12299_Y attribute \src "libresoc.v:187570.18-187570.118" wire width 64 $ternary$libresoc.v:187570$12300_Y attribute \src "libresoc.v:187571.18-187571.118" wire $ternary$libresoc.v:187571$12301_Y attribute \src "libresoc.v:187572.18-187572.118" wire width 2 $ternary$libresoc.v:187572$12302_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 5 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 5 \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 3 \$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 3 \$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$118 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 3 \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 3 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 3 \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 3 \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 5 \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 3 \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 5 \$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 3 \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 3 \$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" wire \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" wire width 64 \$78 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 5 \$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" wire \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 5 \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 4 \alu_shift_rot0_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_shift_rot0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_shift_rot0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_shift_rot0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_shift_rot0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_shift_rot0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_shift_rot0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_shift_rot0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_shift_rot0_rc attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_shift_rot0_sr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_shift_rot0_sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_shift_rot0_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_shift_rot0_sr_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_shift_rot0_sr_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 \alu_shift_rot0_sr_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__input_cr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_shift_rot0_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_shift_rot0_sr_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_shift_rot0_sr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_shift_rot0_sr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__output_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__output_cr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_shift_rot0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_shift_rot0_xer_ca$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_shift_rot0_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 37 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 33 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 20 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 19 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 input 23 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 output 22 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 5 input 21 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 input 31 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 3 output 30 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 3 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 4 \data_r1__cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r2__xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 32 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o attribute \src "libresoc.v:186886.7-186886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \oper_i_alu_shift_rot0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 2 input 12 \oper_i_alu_shift_rot0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \oper_i_alu_shift_rot0__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \oper_i_alu_shift_rot0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \oper_i_alu_shift_rot0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 16 \oper_i_alu_shift_rot0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 17 \oper_i_alu_shift_rot0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \oper_i_alu_shift_rot0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \oper_i_alu_shift_rot0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \oper_i_alu_shift_rot0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \oper_i_alu_shift_rot0__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \oper_i_alu_shift_rot0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \oper_i_alu_shift_rot0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \oper_i_alu_shift_rot0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 5 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 3 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 26 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 24 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 25 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 27 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 28 \src5_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" wire width 64 \src_or_imm attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:187521$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 connect \Y $and$libresoc.v:187521$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:187522$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:187522$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:187523$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:187523$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:187524$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:187524$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:187525$12255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 connect \Y $and$libresoc.v:187525$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:187526$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } connect \Y $and$libresoc.v:187526$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:187527$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:187527$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:187528$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:187528$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:187529$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:187529$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:187530$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:187530$12260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:187532$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 connect \Y $and$libresoc.v:187532$12262_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:187534$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 connect \Y $and$libresoc.v:187534$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:187535$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:187535$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:187537$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 connect \Y $and$libresoc.v:187537$12267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:187540$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:187540$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:187541$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 connect \Y $and$libresoc.v:187541$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:187546$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 connect \Y $and$libresoc.v:187546$12276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:187547$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:187547$12277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:187549$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 connect \Y $and$libresoc.v:187549$12279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:187551$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i connect \Y $and$libresoc.v:187551$12281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:187552$12282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o connect \Y $and$libresoc.v:187552$12282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:187553$12283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o connect \Y $and$libresoc.v:187553$12283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:187559$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:187559$12289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:187560$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:187560$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:187562$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:187562$12292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:187563$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:187563$12293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:187564$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:187564$12294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:187574$12304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:187574$12304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:187575$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:187575$12305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:187576$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:187576$12306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:187578$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } connect \Y $and$libresoc.v:187578$12308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:187548$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 connect \Y $eq$libresoc.v:187548$12278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:187550$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:187550$12280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:187520$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:187520$12250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:187531$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:187531$12261_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:187533$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:187533$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:187536$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:187536$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:187539$12269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 connect \Y $not$libresoc.v:187539$12269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:187545$12275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i connect \Y $not$libresoc.v:187545$12275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:187556$12286 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:187556$12286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" cell $not $not$libresoc.v:187577$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok connect \Y $not$libresoc.v:187577$12307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:187544$12274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 connect \Y $or$libresoc.v:187544$12274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:187554$12284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:187554$12284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:187555$12285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:187555$12285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:187557$12287 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:187557$12287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:187558$12288 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:187558$12288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:187561$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:187561$12291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:187567$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:187567$12297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:187573$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 connect \Y $reduce_and$libresoc.v:187573$12303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:187538$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 connect \Y $reduce_or$libresoc.v:187538$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:187542$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:187542$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:187543$12273 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:187543$12273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" cell $mux $ternary$libresoc.v:187565$12295 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok connect \Y $ternary$libresoc.v:187565$12295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" cell $mux $ternary$libresoc.v:187566$12296 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok connect \Y $ternary$libresoc.v:187566$12296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:187568$12298 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] connect \Y $ternary$libresoc.v:187568$12298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:187569$12299 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel connect \Y $ternary$libresoc.v:187569$12299_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:187570$12300 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:187570$12300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:187571$12301 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] connect \Y $ternary$libresoc.v:187571$12301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:187572$12302 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] connect \Y $ternary$libresoc.v:187572$12302_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:187665.15-187671.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:187672.18-187707.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \alu_shift_rot0_cr_a connect \cr_a_ok \cr_a_ok connect \n_ready_i \alu_shift_rot0_n_ready_i connect \n_valid_o \alu_shift_rot0_n_valid_o connect \o \alu_shift_rot0_o connect \o_ok \o_ok connect \p_ready_o \alu_shift_rot0_p_ready_o connect \p_valid_i \alu_shift_rot0_p_valid_i connect \ra \alu_shift_rot0_ra connect \rb \alu_shift_rot0_rb connect \rc \alu_shift_rot0_rc connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr connect \sr_op__insn \alu_shift_rot0_sr_op__insn connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type connect \sr_op__invert_in \alu_shift_rot0_sr_op__invert_in connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 connect \xer_ca \alu_shift_rot0_xer_ca connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 connect \xer_ca_ok \xer_ca_ok connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 attribute \src "libresoc.v:187708.16-187714.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:187715.15-187721.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:187722.15-187728.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:187729.15-187735.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:187736.15-187741.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:187742.15-187748.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:186886.7-186886.20" process $proc$libresoc.v:186886$12475 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:187008.7-187008.24" process $proc$libresoc.v:187008$12476 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:187018.7-187018.26" process $proc$libresoc.v:187018$12477 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:187026.7-187026.25" process $proc$libresoc.v:187026$12478 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:187069.14-187069.54" process $proc$libresoc.v:187069$12479 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end attribute \src "libresoc.v:187073.14-187073.73" process $proc$libresoc.v:187073$12480 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end attribute \src "libresoc.v:187077.7-187077.48" process $proc$libresoc.v:187077$12481 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end attribute \src "libresoc.v:187085.13-187085.53" process $proc$libresoc.v:187085$12482 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end attribute \src "libresoc.v:187089.7-187089.44" process $proc$libresoc.v:187089$12483 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end attribute \src "libresoc.v:187093.14-187093.48" process $proc$libresoc.v:187093$12484 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end attribute \src "libresoc.v:187172.13-187172.52" process $proc$libresoc.v:187172$12485 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end attribute \src "libresoc.v:187176.7-187176.45" process $proc$libresoc.v:187176$12486 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end attribute \src "libresoc.v:187180.7-187180.44" process $proc$libresoc.v:187180$12487 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end attribute \src "libresoc.v:187184.7-187184.45" process $proc$libresoc.v:187184$12488 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end attribute \src "libresoc.v:187188.7-187188.42" process $proc$libresoc.v:187188$12489 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end attribute \src "libresoc.v:187192.7-187192.42" process $proc$libresoc.v:187192$12490 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end attribute \src "libresoc.v:187196.7-187196.48" process $proc$libresoc.v:187196$12491 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end attribute \src "libresoc.v:187200.7-187200.45" process $proc$libresoc.v:187200$12492 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end attribute \src "libresoc.v:187204.7-187204.42" process $proc$libresoc.v:187204$12493 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end attribute \src "libresoc.v:187208.7-187208.42" process $proc$libresoc.v:187208$12494 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end attribute \src "libresoc.v:187212.7-187212.45" process $proc$libresoc.v:187212$12495 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end attribute \src "libresoc.v:187224.7-187224.27" process $proc$libresoc.v:187224$12496 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:187258.14-187258.47" process $proc$libresoc.v:187258$12497 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:187262.7-187262.27" process $proc$libresoc.v:187262$12498 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:187266.13-187266.33" process $proc$libresoc.v:187266$12499 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end attribute \src "libresoc.v:187270.7-187270.30" process $proc$libresoc.v:187270$12500 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:187274.13-187274.35" process $proc$libresoc.v:187274$12501 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end attribute \src "libresoc.v:187278.7-187278.32" process $proc$libresoc.v:187278$12502 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end attribute \src "libresoc.v:187295.7-187295.25" process $proc$libresoc.v:187295$12503 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:187299.7-187299.25" process $proc$libresoc.v:187299$12504 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:187431.13-187431.30" process $proc$libresoc.v:187431$12505 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end attribute \src "libresoc.v:187439.13-187439.31" process $proc$libresoc.v:187439$12506 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end attribute \src "libresoc.v:187443.13-187443.31" process $proc$libresoc.v:187443$12507 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end attribute \src "libresoc.v:187455.7-187455.26" process $proc$libresoc.v:187455$12508 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:187459.7-187459.26" process $proc$libresoc.v:187459$12509 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:187463.7-187463.25" process $proc$libresoc.v:187463$12510 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:187467.7-187467.25" process $proc$libresoc.v:187467$12511 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:187485.13-187485.32" process $proc$libresoc.v:187485$12512 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end attribute \src "libresoc.v:187489.13-187489.32" process $proc$libresoc.v:187489$12513 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end attribute \src "libresoc.v:187495.14-187495.43" process $proc$libresoc.v:187495$12514 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:187499.14-187499.43" process $proc$libresoc.v:187499$12515 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:187503.14-187503.43" process $proc$libresoc.v:187503$12516 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end attribute \src "libresoc.v:187507.7-187507.20" process $proc$libresoc.v:187507$12517 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end attribute \src "libresoc.v:187511.13-187511.26" process $proc$libresoc.v:187511$12518 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end attribute \src "libresoc.v:187579.3-187580.39" process $proc$libresoc.v:187579$12309 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:187581.3-187582.43" process $proc$libresoc.v:187581$12310 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:187583.3-187584.29" process $proc$libresoc.v:187583$12311 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end attribute \src "libresoc.v:187585.3-187586.29" process $proc$libresoc.v:187585$12312 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end attribute \src "libresoc.v:187587.3-187588.29" process $proc$libresoc.v:187587$12313 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end attribute \src "libresoc.v:187589.3-187590.29" process $proc$libresoc.v:187589$12314 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:187591.3-187592.29" process $proc$libresoc.v:187591$12315 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:187593.3-187594.47" process $proc$libresoc.v:187593$12316 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end attribute \src "libresoc.v:187595.3-187596.53" process $proc$libresoc.v:187595$12317 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end attribute \src "libresoc.v:187597.3-187598.43" process $proc$libresoc.v:187597$12318 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end attribute \src "libresoc.v:187599.3-187600.49" process $proc$libresoc.v:187599$12319 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end attribute \src "libresoc.v:187601.3-187602.37" process $proc$libresoc.v:187601$12320 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:187603.3-187604.43" process $proc$libresoc.v:187603$12321 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:187605.3-187606.79" process $proc$libresoc.v:187605$12322 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end attribute \src "libresoc.v:187607.3-187608.75" process $proc$libresoc.v:187607$12323 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end attribute \src "libresoc.v:187609.3-187610.89" process $proc$libresoc.v:187609$12324 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end attribute \src "libresoc.v:187611.3-187612.85" process $proc$libresoc.v:187611$12325 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end attribute \src "libresoc.v:187613.3-187614.73" process $proc$libresoc.v:187613$12326 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end attribute \src "libresoc.v:187615.3-187616.73" process $proc$libresoc.v:187615$12327 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end attribute \src "libresoc.v:187617.3-187618.73" process $proc$libresoc.v:187617$12328 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end attribute \src "libresoc.v:187619.3-187620.73" process $proc$libresoc.v:187619$12329 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end attribute \src "libresoc.v:187621.3-187622.79" process $proc$libresoc.v:187621$12330 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end attribute \src "libresoc.v:187623.3-187624.79" process $proc$libresoc.v:187623$12331 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end attribute \src "libresoc.v:187625.3-187626.83" process $proc$libresoc.v:187625$12332 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end attribute \src "libresoc.v:187627.3-187628.85" process $proc$libresoc.v:187627$12333 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end attribute \src "libresoc.v:187629.3-187630.77" process $proc$libresoc.v:187629$12334 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end attribute \src "libresoc.v:187631.3-187632.79" process $proc$libresoc.v:187631$12335 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end attribute \src "libresoc.v:187633.3-187634.77" process $proc$libresoc.v:187633$12336 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end attribute \src "libresoc.v:187635.3-187636.79" process $proc$libresoc.v:187635$12337 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end attribute \src "libresoc.v:187637.3-187638.69" process $proc$libresoc.v:187637$12338 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end attribute \src "libresoc.v:187639.3-187640.39" process $proc$libresoc.v:187639$12339 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end attribute \src "libresoc.v:187641.3-187642.39" process $proc$libresoc.v:187641$12340 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end attribute \src "libresoc.v:187643.3-187644.39" process $proc$libresoc.v:187643$12341 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end attribute \src "libresoc.v:187645.3-187646.39" process $proc$libresoc.v:187645$12342 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end attribute \src "libresoc.v:187647.3-187648.39" process $proc$libresoc.v:187647$12343 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:187649.3-187650.39" process $proc$libresoc.v:187649$12344 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:187651.3-187652.39" process $proc$libresoc.v:187651$12345 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:187653.3-187654.39" process $proc$libresoc.v:187653$12346 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:187655.3-187656.41" process $proc$libresoc.v:187655$12347 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:187657.3-187658.41" process $proc$libresoc.v:187657$12348 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:187659.3-187660.37" process $proc$libresoc.v:187659$12349 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end attribute \src "libresoc.v:187661.3-187662.46" process $proc$libresoc.v:187661$12350 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:187663.3-187664.25" process $proc$libresoc.v:187663$12351 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:187749.3-187758.6" process $proc$libresoc.v:187749$12352 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:187750.5-187750.29" switch \initial attribute \src "libresoc.v:187750.9-187750.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$46 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:187759.3-187767.6" process $proc$libresoc.v:187759$12353 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$12354 $1\rok_l_s_rdok$next[0:0]$12355 attribute \src "libresoc.v:187760.5-187760.29" switch \initial attribute \src "libresoc.v:187760.9-187760.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$12355 1'0 case assign $1\rok_l_s_rdok$next[0:0]$12355 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12354 end attribute \src "libresoc.v:187768.3-187776.6" process $proc$libresoc.v:187768$12356 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$12357 $1\rok_l_r_rdok$next[0:0]$12358 attribute \src "libresoc.v:187769.5-187769.29" switch \initial attribute \src "libresoc.v:187769.9-187769.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$12358 1'1 case assign $1\rok_l_r_rdok$next[0:0]$12358 \$64 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12357 end attribute \src "libresoc.v:187777.3-187785.6" process $proc$libresoc.v:187777$12359 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$12360 $1\rst_l_s_rst$next[0:0]$12361 attribute \src "libresoc.v:187778.5-187778.29" switch \initial attribute \src "libresoc.v:187778.9-187778.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$12361 1'0 case assign $1\rst_l_s_rst$next[0:0]$12361 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12360 end attribute \src "libresoc.v:187786.3-187794.6" process $proc$libresoc.v:187786$12362 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$12363 $1\rst_l_r_rst$next[0:0]$12364 attribute \src "libresoc.v:187787.5-187787.29" switch \initial attribute \src "libresoc.v:187787.9-187787.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$12364 1'1 case assign $1\rst_l_r_rst$next[0:0]$12364 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12363 end attribute \src "libresoc.v:187795.3-187803.6" process $proc$libresoc.v:187795$12365 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$12366 $1\opc_l_s_opc$next[0:0]$12367 attribute \src "libresoc.v:187796.5-187796.29" switch \initial attribute \src "libresoc.v:187796.9-187796.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$12367 1'0 case assign $1\opc_l_s_opc$next[0:0]$12367 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12366 end attribute \src "libresoc.v:187804.3-187812.6" process $proc$libresoc.v:187804$12368 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$12369 $1\opc_l_r_opc$next[0:0]$12370 attribute \src "libresoc.v:187805.5-187805.29" switch \initial attribute \src "libresoc.v:187805.9-187805.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$12370 1'1 case assign $1\opc_l_r_opc$next[0:0]$12370 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12369 end attribute \src "libresoc.v:187813.3-187821.6" process $proc$libresoc.v:187813$12371 assign { } { } assign { } { } assign $0\src_l_s_src$next[4:0]$12372 $1\src_l_s_src$next[4:0]$12373 attribute \src "libresoc.v:187814.5-187814.29" switch \initial attribute \src "libresoc.v:187814.9-187814.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[4:0]$12373 5'00000 case assign $1\src_l_s_src$next[4:0]$12373 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12372 end attribute \src "libresoc.v:187822.3-187830.6" process $proc$libresoc.v:187822$12374 assign { } { } assign { } { } assign $0\src_l_r_src$next[4:0]$12375 $1\src_l_r_src$next[4:0]$12376 attribute \src "libresoc.v:187823.5-187823.29" switch \initial attribute \src "libresoc.v:187823.9-187823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[4:0]$12376 5'11111 case assign $1\src_l_r_src$next[4:0]$12376 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12375 end attribute \src "libresoc.v:187831.3-187839.6" process $proc$libresoc.v:187831$12377 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$12378 $1\req_l_s_req$next[2:0]$12379 attribute \src "libresoc.v:187832.5-187832.29" switch \initial attribute \src "libresoc.v:187832.9-187832.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[2:0]$12379 3'000 case assign $1\req_l_s_req$next[2:0]$12379 \$66 end sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12378 end attribute \src "libresoc.v:187840.3-187848.6" process $proc$libresoc.v:187840$12380 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$12381 $1\req_l_r_req$next[2:0]$12382 attribute \src "libresoc.v:187841.5-187841.29" switch \initial attribute \src "libresoc.v:187841.9-187841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[2:0]$12382 3'111 case assign $1\req_l_r_req$next[2:0]$12382 \$68 end sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12381 end attribute \src "libresoc.v:187849.3-187886.6" process $proc$libresoc.v:187849$12383 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12384 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 assign { } { } assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12387 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12388 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12389 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12390 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12391 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12392 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12393 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 assign { } { } assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12396 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12397 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 assign { } { } assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12400 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12385 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12386 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12394 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12395 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12398 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12399 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 attribute \src "libresoc.v:187850.5-187850.29" switch \initial attribute \src "libresoc.v:187850.9-187850.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12401 \alu_shift_rot0_sr_op__fn_unit assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 \alu_shift_rot0_sr_op__imm_data__data assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 \alu_shift_rot0_sr_op__imm_data__ok assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12404 \alu_shift_rot0_sr_op__input_carry assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12405 \alu_shift_rot0_sr_op__input_cr assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12406 \alu_shift_rot0_sr_op__insn assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12407 \alu_shift_rot0_sr_op__insn_type assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12408 \alu_shift_rot0_sr_op__invert_in assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12409 \alu_shift_rot0_sr_op__is_32bit assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12410 \alu_shift_rot0_sr_op__is_signed assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 \alu_shift_rot0_sr_op__oe__oe assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 \alu_shift_rot0_sr_op__oe__ok assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12413 \alu_shift_rot0_sr_op__output_carry assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12414 \alu_shift_rot0_sr_op__output_cr assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 \alu_shift_rot0_sr_op__rc__ok assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 \alu_shift_rot0_sr_op__rc__rc assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12417 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 1'0 assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 1'0 assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 1'0 assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 1'0 assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 1'0 case assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12418 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12402 assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12419 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12403 assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12420 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12411 assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12421 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12412 assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12422 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12415 assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12423 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12416 end sync always update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12384 update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12385 update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12386 update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12387 update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12388 update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12389 update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12390 update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12391 update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12392 update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12393 update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12394 update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12395 update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12396 update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12397 update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12398 update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12399 update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12400 end attribute \src "libresoc.v:187887.3-187908.6" process $proc$libresoc.v:187887$12424 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$12425 $2\data_r0__o$next[63:0]$12429 assign { } { } assign $0\data_r0__o_ok$next[0:0]$12426 $3\data_r0__o_ok$next[0:0]$12431 attribute \src "libresoc.v:187888.5-187888.29" switch \initial attribute \src "libresoc.v:187888.9-187888.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$12428 $1\data_r0__o$next[63:0]$12427 } { \o_ok \alu_shift_rot0_o } case assign $1\data_r0__o$next[63:0]$12427 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$12428 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$12430 $2\data_r0__o$next[63:0]$12429 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$12429 $1\data_r0__o$next[63:0]$12427 assign $2\data_r0__o_ok$next[0:0]$12430 $1\data_r0__o_ok$next[0:0]$12428 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$12431 1'0 case assign $3\data_r0__o_ok$next[0:0]$12431 $2\data_r0__o_ok$next[0:0]$12430 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$12425 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12426 end attribute \src "libresoc.v:187909.3-187930.6" process $proc$libresoc.v:187909$12432 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__cr_a$next[3:0]$12433 $2\data_r1__cr_a$next[3:0]$12437 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$12434 $3\data_r1__cr_a_ok$next[0:0]$12439 attribute \src "libresoc.v:187910.5-187910.29" switch \initial attribute \src "libresoc.v:187910.9-187910.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__cr_a_ok$next[0:0]$12436 $1\data_r1__cr_a$next[3:0]$12435 } { \cr_a_ok \alu_shift_rot0_cr_a } case assign $1\data_r1__cr_a$next[3:0]$12435 \data_r1__cr_a assign $1\data_r1__cr_a_ok$next[0:0]$12436 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__cr_a_ok$next[0:0]$12438 $2\data_r1__cr_a$next[3:0]$12437 } 5'00000 case assign $2\data_r1__cr_a$next[3:0]$12437 $1\data_r1__cr_a$next[3:0]$12435 assign $2\data_r1__cr_a_ok$next[0:0]$12438 $1\data_r1__cr_a_ok$next[0:0]$12436 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__cr_a_ok$next[0:0]$12439 1'0 case assign $3\data_r1__cr_a_ok$next[0:0]$12439 $2\data_r1__cr_a_ok$next[0:0]$12438 end sync always update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12433 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12434 end attribute \src "libresoc.v:187931.3-187952.6" process $proc$libresoc.v:187931$12440 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__xer_ca$next[1:0]$12441 $2\data_r2__xer_ca$next[1:0]$12445 assign { } { } assign $0\data_r2__xer_ca_ok$next[0:0]$12442 $3\data_r2__xer_ca_ok$next[0:0]$12447 attribute \src "libresoc.v:187932.5-187932.29" switch \initial attribute \src "libresoc.v:187932.9-187932.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__xer_ca_ok$next[0:0]$12444 $1\data_r2__xer_ca$next[1:0]$12443 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case assign $1\data_r2__xer_ca$next[1:0]$12443 \data_r2__xer_ca assign $1\data_r2__xer_ca_ok$next[0:0]$12444 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__xer_ca_ok$next[0:0]$12446 $2\data_r2__xer_ca$next[1:0]$12445 } 3'000 case assign $2\data_r2__xer_ca$next[1:0]$12445 $1\data_r2__xer_ca$next[1:0]$12443 assign $2\data_r2__xer_ca_ok$next[0:0]$12446 $1\data_r2__xer_ca_ok$next[0:0]$12444 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__xer_ca_ok$next[0:0]$12447 1'0 case assign $3\data_r2__xer_ca_ok$next[0:0]$12447 $2\data_r2__xer_ca_ok$next[0:0]$12446 end sync always update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12441 update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12442 end attribute \src "libresoc.v:187953.3-187962.6" process $proc$libresoc.v:187953$12448 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$12449 $1\src_r0$next[63:0]$12450 attribute \src "libresoc.v:187954.5-187954.29" switch \initial attribute \src "libresoc.v:187954.9-187954.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$12450 \src1_i case assign $1\src_r0$next[63:0]$12450 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$12449 end attribute \src "libresoc.v:187963.3-187972.6" process $proc$libresoc.v:187963$12451 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$12452 $1\src_r1$next[63:0]$12453 attribute \src "libresoc.v:187964.5-187964.29" switch \initial attribute \src "libresoc.v:187964.9-187964.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$12453 \src_or_imm case assign $1\src_r1$next[63:0]$12453 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$12452 end attribute \src "libresoc.v:187973.3-187982.6" process $proc$libresoc.v:187973$12454 assign { } { } assign { } { } assign $0\src_r2$next[63:0]$12455 $1\src_r2$next[63:0]$12456 attribute \src "libresoc.v:187974.5-187974.29" switch \initial attribute \src "libresoc.v:187974.9-187974.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[63:0]$12456 \src3_i case assign $1\src_r2$next[63:0]$12456 \src_r2 end sync always update \src_r2$next $0\src_r2$next[63:0]$12455 end attribute \src "libresoc.v:187983.3-187992.6" process $proc$libresoc.v:187983$12457 assign { } { } assign { } { } assign $0\src_r3$next[0:0]$12458 $1\src_r3$next[0:0]$12459 attribute \src "libresoc.v:187984.5-187984.29" switch \initial attribute \src "libresoc.v:187984.9-187984.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r3$next[0:0]$12459 \src4_i case assign $1\src_r3$next[0:0]$12459 \src_r3 end sync always update \src_r3$next $0\src_r3$next[0:0]$12458 end attribute \src "libresoc.v:187993.3-188002.6" process $proc$libresoc.v:187993$12460 assign { } { } assign { } { } assign $0\src_r4$next[1:0]$12461 $1\src_r4$next[1:0]$12462 attribute \src "libresoc.v:187994.5-187994.29" switch \initial attribute \src "libresoc.v:187994.9-187994.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r4$next[1:0]$12462 \src5_i case assign $1\src_r4$next[1:0]$12462 \src_r4 end sync always update \src_r4$next $0\src_r4$next[1:0]$12461 end attribute \src "libresoc.v:188003.3-188011.6" process $proc$libresoc.v:188003$12463 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$12464 $1\alui_l_r_alui$next[0:0]$12465 attribute \src "libresoc.v:188004.5-188004.29" switch \initial attribute \src "libresoc.v:188004.9-188004.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$12465 1'1 case assign $1\alui_l_r_alui$next[0:0]$12465 \$90 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12464 end attribute \src "libresoc.v:188012.3-188020.6" process $proc$libresoc.v:188012$12466 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$12467 $1\alu_l_r_alu$next[0:0]$12468 attribute \src "libresoc.v:188013.5-188013.29" switch \initial attribute \src "libresoc.v:188013.9-188013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$12468 1'1 case assign $1\alu_l_r_alu$next[0:0]$12468 \$92 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12467 end attribute \src "libresoc.v:188021.3-188030.6" process $proc$libresoc.v:188021$12469 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:188022.5-188022.29" switch \initial attribute \src "libresoc.v:188022.9-188022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$114 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:188031.3-188040.6" process $proc$libresoc.v:188031$12470 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] attribute \src "libresoc.v:188032.5-188032.29" switch \initial attribute \src "libresoc.v:188032.9-188032.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[3:0] \data_r1__cr_a case assign $1\dest2_o[3:0] 4'0000 end sync always update \dest2_o $0\dest2_o[3:0] end attribute \src "libresoc.v:188041.3-188050.6" process $proc$libresoc.v:188041$12471 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] attribute \src "libresoc.v:188042.5-188042.29" switch \initial attribute \src "libresoc.v:188042.9-188042.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$118 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[1:0] \data_r2__xer_ca case assign $1\dest3_o[1:0] 2'00 end sync always update \dest3_o $0\dest3_o[1:0] end attribute \src "libresoc.v:188051.3-188059.6" process $proc$libresoc.v:188051$12472 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$12473 $1\prev_wr_go$next[2:0]$12474 attribute \src "libresoc.v:188052.5-188052.29" switch \initial attribute \src "libresoc.v:188052.9-188052.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[2:0]$12474 3'000 case assign $1\prev_wr_go$next[2:0]$12474 \$20 end sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12473 end connect \$100 $not$libresoc.v:187520$12250_Y connect \$102 $and$libresoc.v:187521$12251_Y connect \$104 $and$libresoc.v:187522$12252_Y connect \$106 $and$libresoc.v:187523$12253_Y connect \$108 $and$libresoc.v:187524$12254_Y connect \$10 $and$libresoc.v:187525$12255_Y connect \$110 $and$libresoc.v:187526$12256_Y connect \$112 $and$libresoc.v:187527$12257_Y connect \$114 $and$libresoc.v:187528$12258_Y connect \$116 $and$libresoc.v:187529$12259_Y connect \$118 $and$libresoc.v:187530$12260_Y connect \$12 $not$libresoc.v:187531$12261_Y connect \$14 $and$libresoc.v:187532$12262_Y connect \$16 $not$libresoc.v:187533$12263_Y connect \$18 $and$libresoc.v:187534$12264_Y connect \$20 $and$libresoc.v:187535$12265_Y connect \$24 $not$libresoc.v:187536$12266_Y connect \$26 $and$libresoc.v:187537$12267_Y connect \$23 $reduce_or$libresoc.v:187538$12268_Y connect \$22 $not$libresoc.v:187539$12269_Y connect \$2 $and$libresoc.v:187540$12270_Y connect \$30 $and$libresoc.v:187541$12271_Y connect \$32 $reduce_or$libresoc.v:187542$12272_Y connect \$34 $reduce_or$libresoc.v:187543$12273_Y connect \$36 $or$libresoc.v:187544$12274_Y connect \$38 $not$libresoc.v:187545$12275_Y connect \$40 $and$libresoc.v:187546$12276_Y connect \$42 $and$libresoc.v:187547$12277_Y connect \$44 $eq$libresoc.v:187548$12278_Y connect \$46 $and$libresoc.v:187549$12279_Y connect \$48 $eq$libresoc.v:187550$12280_Y connect \$50 $and$libresoc.v:187551$12281_Y connect \$52 $and$libresoc.v:187552$12282_Y connect \$54 $and$libresoc.v:187553$12283_Y connect \$56 $or$libresoc.v:187554$12284_Y connect \$58 $or$libresoc.v:187555$12285_Y connect \$5 $not$libresoc.v:187556$12286_Y connect \$60 $or$libresoc.v:187557$12287_Y connect \$62 $or$libresoc.v:187558$12288_Y connect \$64 $and$libresoc.v:187559$12289_Y connect \$66 $and$libresoc.v:187560$12290_Y connect \$68 $or$libresoc.v:187561$12291_Y connect \$70 $and$libresoc.v:187562$12292_Y connect \$72 $and$libresoc.v:187563$12293_Y connect \$74 $and$libresoc.v:187564$12294_Y connect \$76 $ternary$libresoc.v:187565$12295_Y connect \$78 $ternary$libresoc.v:187566$12296_Y connect \$7 $or$libresoc.v:187567$12297_Y connect \$80 $ternary$libresoc.v:187568$12298_Y connect \$82 $ternary$libresoc.v:187569$12299_Y connect \$84 $ternary$libresoc.v:187570$12300_Y connect \$86 $ternary$libresoc.v:187571$12301_Y connect \$88 $ternary$libresoc.v:187572$12302_Y connect \$4 $reduce_and$libresoc.v:187573$12303_Y connect \$90 $and$libresoc.v:187574$12304_Y connect \$92 $and$libresoc.v:187575$12305_Y connect \$94 $and$libresoc.v:187576$12306_Y connect \$96 $not$libresoc.v:187577$12307_Y connect \$98 $and$libresoc.v:187578$12308_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 connect \cu_rd__rel_o \$102 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_shift_rot0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_shift_rot0_p_valid_i \alui_l_q_alui connect \alu_shift_rot0_xer_ca$1 \$88 connect \alu_shift_rot0_xer_so \$86 connect \alu_shift_rot0_rc \$84 connect \alu_shift_rot0_rb \$82 connect \alu_shift_rot0_ra \$80 connect \src_or_imm \$78 connect \src_sel \$76 connect \cu_wrmask_o { \$74 \$72 \$70 } connect \reset_r \$62 connect \reset_w \$60 connect \rst_r \$58 connect \reset \$56 connect \wr_any \$36 connect \cu_done_o \$30 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$18 connect \alu_done_dly$next \alu_done connect \alu_done \alu_shift_rot0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$14 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end attribute \src "libresoc.v:188096.1-188174.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr attribute \src "libresoc.v:188144.3-188147.6" wire width 4 $0$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12532 attribute \src "libresoc.v:188144.3-188147.6" wire width 64 $0$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12533 attribute \src "libresoc.v:188144.3-188147.6" wire width 64 $0$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12534 attribute \src "libresoc.v:188144.3-188147.6" wire width 4 $0\_0_[3:0] attribute \src "libresoc.v:188097.7-188097.20" wire $0\initial[0:0] attribute \src "libresoc.v:188151.3-188159.6" wire $0\ren_delay$next[0:0]$12541 attribute \src "libresoc.v:188149.3-188150.35" wire $0\ren_delay[0:0] attribute \src "libresoc.v:188160.3-188169.6" wire width 64 $0\spr1__data_o[63:0] attribute \src "libresoc.v:188144.3-188147.6" wire width 4 $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 attribute \src "libresoc.v:188144.3-188147.6" wire width 64 $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 attribute \src "libresoc.v:188144.3-188147.6" wire width 64 $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 attribute \src "libresoc.v:188151.3-188159.6" wire $1\ren_delay$next[0:0]$12542 attribute \src "libresoc.v:188113.7-188113.23" wire $1\ren_delay[0:0] attribute \src "libresoc.v:188160.3-188169.6" wire width 64 $1\spr1__data_o[63:0] attribute \src "libresoc.v:188148.26-188148.32" wire width 64 $memrd$\memory$libresoc.v:188148$12538_DATA attribute \src "libresoc.v:0.0-0.0" wire width 4 $memwr$\memory$libresoc.v:188146$12530_ADDR attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:188146$12530_DATA attribute \src "libresoc.v:0.0-0.0" wire width 64 $memwr$\memory$libresoc.v:188146$12530_EN attribute \src "libresoc.v:188143.13-188143.16" wire width 4 \_0_ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 8 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:188097.7-188097.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 4 \memory_r_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 64 \memory_r_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 4 \memory_w_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire width 64 \memory_w_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" wire \memory_w_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 3 \spr1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 6 \spr1__addr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 5 \spr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 2 \spr1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen attribute \src "libresoc.v:188129.14-188129.20" memory width 64 size 11 \memory attribute \src "libresoc.v:188131.5-188131.37" cell $meminit $meminit$\memory$libresoc.v:188131$12544 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12544 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188132.5-188132.37" cell $meminit $meminit$\memory$libresoc.v:188132$12545 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12545 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188133.5-188133.37" cell $meminit $meminit$\memory$libresoc.v:188133$12546 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12546 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188134.5-188134.37" cell $meminit $meminit$\memory$libresoc.v:188134$12547 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12547 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188135.5-188135.37" cell $meminit $meminit$\memory$libresoc.v:188135$12548 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12548 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188136.5-188136.37" cell $meminit $meminit$\memory$libresoc.v:188136$12549 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12549 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188137.5-188137.37" cell $meminit $meminit$\memory$libresoc.v:188137$12550 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12550 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188138.5-188138.37" cell $meminit $meminit$\memory$libresoc.v:188138$12551 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12551 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188139.5-188139.37" cell $meminit $meminit$\memory$libresoc.v:188139$12552 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12552 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188140.5-188140.37" cell $meminit $meminit$\memory$libresoc.v:188140$12553 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12553 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188141.5-188141.38" cell $meminit $meminit$\memory$libresoc.v:188141$12554 parameter \ABITS 32 parameter \MEMID "\\memory" parameter \PRIORITY 12554 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:188148.26-188148.32" cell $memrd $memrd$\memory$libresoc.v:188148$12538 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" parameter \TRANSPARENT 0 parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x connect \DATA $memrd$\memory$libresoc.v:188148$12538_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" process $proc$libresoc.v:0$12557 sync always sync init end attribute \src "libresoc.v:188097.7-188097.20" process $proc$libresoc.v:188097$12555 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:188113.7-188113.23" process $proc$libresoc.v:188113$12556 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end attribute \src "libresoc.v:188144.3-188147.6" process $proc$libresoc.v:188144$12531 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\_0_[3:0] \memory_r_addr assign $0$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12532 $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 assign $0$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12533 $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 assign $0$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12534 $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 attribute \src "libresoc.v:188146.5-188146.61" switch \memory_w_en attribute \src "libresoc.v:188146.9-188146.20" case 1'1 assign { } { } assign { } { } assign { } { } assign $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 \memory_w_addr assign $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 \memory_w_data assign $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 64'1111111111111111111111111111111111111111111111111111111111111111 case assign $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 4'xxxx assign $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx assign $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[3:0] update $memwr$\memory$libresoc.v:188146$12530_ADDR $0$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12532 update $memwr$\memory$libresoc.v:188146$12530_DATA $0$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12533 update $memwr$\memory$libresoc.v:188146$12530_EN $0$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12534 attribute \src "libresoc.v:188146.22-188146.60" memwr \memory $1$memwr$\memory$libresoc.v:188146$12530_ADDR[3:0]$12535 $1$memwr$\memory$libresoc.v:188146$12530_DATA[63:0]$12536 $1$memwr$\memory$libresoc.v:188146$12530_EN[63:0]$12537 0' end attribute \src "libresoc.v:188149.3-188150.35" process $proc$libresoc.v:188149$12539 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end attribute \src "libresoc.v:188151.3-188159.6" process $proc$libresoc.v:188151$12540 assign { } { } assign { } { } assign $0\ren_delay$next[0:0]$12541 $1\ren_delay$next[0:0]$12542 attribute \src "libresoc.v:188152.5-188152.29" switch \initial attribute \src "libresoc.v:188152.9-188152.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$next[0:0]$12542 1'0 case assign $1\ren_delay$next[0:0]$12542 \spr1__ren end sync always update \ren_delay$next $0\ren_delay$next[0:0]$12541 end attribute \src "libresoc.v:188160.3-188169.6" process $proc$libresoc.v:188160$12543 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] attribute \src "libresoc.v:188161.5-188161.29" switch \initial attribute \src "libresoc.v:188161.9-188161.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" switch \ren_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\spr1__data_o[63:0] \memory_r_data case assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \spr1__data_o $0\spr1__data_o[63:0] end connect \memory_r_data $memrd$\memory$libresoc.v:188148$12538_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end attribute \src "libresoc.v:188178.1-189431.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 attribute \src "libresoc.v:188928.3-188929.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:188926.3-188927.40" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:189322.3-189330.6" wire $0\alu_l_r_alu$next[0:0]$12771 attribute \src "libresoc.v:188856.3-188857.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:189108.3-189120.6" wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$12693 attribute \src "libresoc.v:188898.3-188899.65" wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] attribute \src "libresoc.v:189108.3-189120.6" wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12694 attribute \src "libresoc.v:188900.3-188901.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] attribute \src "libresoc.v:189108.3-189120.6" wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12695 attribute \src "libresoc.v:188896.3-188897.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] attribute \src "libresoc.v:189108.3-189120.6" wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12696 attribute \src "libresoc.v:188902.3-188903.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] attribute \src "libresoc.v:189313.3-189321.6" wire $0\alui_l_r_alui$next[0:0]$12768 attribute \src "libresoc.v:188858.3-188859.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:189121.3-189142.6" wire width 64 $0\data_r0__o$next[63:0]$12702 attribute \src "libresoc.v:188892.3-188893.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:189121.3-189142.6" wire $0\data_r0__o_ok$next[0:0]$12703 attribute \src "libresoc.v:188894.3-188895.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:189143.3-189164.6" wire width 64 $0\data_r1__spr1$next[63:0]$12710 attribute \src "libresoc.v:188888.3-188889.43" wire width 64 $0\data_r1__spr1[63:0] attribute \src "libresoc.v:189143.3-189164.6" wire $0\data_r1__spr1_ok$next[0:0]$12711 attribute \src "libresoc.v:188890.3-188891.49" wire $0\data_r1__spr1_ok[0:0] attribute \src "libresoc.v:189165.3-189186.6" wire width 64 $0\data_r2__fast1$next[63:0]$12718 attribute \src "libresoc.v:188884.3-188885.45" wire width 64 $0\data_r2__fast1[63:0] attribute \src "libresoc.v:189165.3-189186.6" wire $0\data_r2__fast1_ok$next[0:0]$12719 attribute \src "libresoc.v:188886.3-188887.51" wire $0\data_r2__fast1_ok[0:0] attribute \src "libresoc.v:189187.3-189208.6" wire $0\data_r3__xer_so$next[0:0]$12726 attribute \src "libresoc.v:188880.3-188881.47" wire $0\data_r3__xer_so[0:0] attribute \src "libresoc.v:189187.3-189208.6" wire $0\data_r3__xer_so_ok$next[0:0]$12727 attribute \src "libresoc.v:188882.3-188883.53" wire $0\data_r3__xer_so_ok[0:0] attribute \src "libresoc.v:189209.3-189230.6" wire width 2 $0\data_r4__xer_ov$next[1:0]$12734 attribute \src "libresoc.v:188876.3-188877.47" wire width 2 $0\data_r4__xer_ov[1:0] attribute \src "libresoc.v:189209.3-189230.6" wire $0\data_r4__xer_ov_ok$next[0:0]$12735 attribute \src "libresoc.v:188878.3-188879.53" wire $0\data_r4__xer_ov_ok[0:0] attribute \src "libresoc.v:189231.3-189252.6" wire width 2 $0\data_r5__xer_ca$next[1:0]$12742 attribute \src "libresoc.v:188872.3-188873.47" wire width 2 $0\data_r5__xer_ca[1:0] attribute \src "libresoc.v:189231.3-189252.6" wire $0\data_r5__xer_ca_ok$next[0:0]$12743 attribute \src "libresoc.v:188874.3-188875.53" wire $0\data_r5__xer_ca_ok[0:0] attribute \src "libresoc.v:189331.3-189340.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:189341.3-189350.6" wire width 64 $0\dest2_o[63:0] attribute \src "libresoc.v:189351.3-189360.6" wire width 64 $0\dest3_o[63:0] attribute \src "libresoc.v:189361.3-189370.6" wire $0\dest4_o[0:0] attribute \src "libresoc.v:189371.3-189380.6" wire width 2 $0\dest5_o[1:0] attribute \src "libresoc.v:189381.3-189390.6" wire width 2 $0\dest6_o[1:0] attribute \src "libresoc.v:188179.7-188179.20" wire $0\initial[0:0] attribute \src "libresoc.v:189063.3-189071.6" wire $0\opc_l_r_opc$next[0:0]$12678 attribute \src "libresoc.v:188912.3-188913.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:189054.3-189062.6" wire $0\opc_l_s_opc$next[0:0]$12675 attribute \src "libresoc.v:188914.3-188915.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:189391.3-189399.6" wire width 6 $0\prev_wr_go$next[5:0]$12780 attribute \src "libresoc.v:188924.3-188925.37" wire width 6 $0\prev_wr_go[5:0] attribute \src "libresoc.v:189008.3-189017.6" wire $0\req_done[0:0] attribute \src "libresoc.v:189099.3-189107.6" wire width 6 $0\req_l_r_req$next[5:0]$12690 attribute \src "libresoc.v:188904.3-188905.39" wire width 6 $0\req_l_r_req[5:0] attribute \src "libresoc.v:189090.3-189098.6" wire width 6 $0\req_l_s_req$next[5:0]$12687 attribute \src "libresoc.v:188906.3-188907.39" wire width 6 $0\req_l_s_req[5:0] attribute \src "libresoc.v:189027.3-189035.6" wire $0\rok_l_r_rdok$next[0:0]$12666 attribute \src "libresoc.v:188920.3-188921.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:189018.3-189026.6" wire $0\rok_l_s_rdok$next[0:0]$12663 attribute \src "libresoc.v:188922.3-188923.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:189045.3-189053.6" wire $0\rst_l_r_rst$next[0:0]$12672 attribute \src "libresoc.v:188916.3-188917.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:189036.3-189044.6" wire $0\rst_l_s_rst$next[0:0]$12669 attribute \src "libresoc.v:188918.3-188919.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:189081.3-189089.6" wire width 6 $0\src_l_r_src$next[5:0]$12684 attribute \src "libresoc.v:188908.3-188909.39" wire width 6 $0\src_l_r_src[5:0] attribute \src "libresoc.v:189072.3-189080.6" wire width 6 $0\src_l_s_src$next[5:0]$12681 attribute \src "libresoc.v:188910.3-188911.39" wire width 6 $0\src_l_s_src[5:0] attribute \src "libresoc.v:189253.3-189262.6" wire width 64 $0\src_r0$next[63:0]$12750 attribute \src "libresoc.v:188870.3-188871.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:189263.3-189272.6" wire width 64 $0\src_r1$next[63:0]$12753 attribute \src "libresoc.v:188868.3-188869.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:189273.3-189282.6" wire width 64 $0\src_r2$next[63:0]$12756 attribute \src "libresoc.v:188866.3-188867.29" wire width 64 $0\src_r2[63:0] attribute \src "libresoc.v:189283.3-189292.6" wire $0\src_r3$next[0:0]$12759 attribute \src "libresoc.v:188864.3-188865.29" wire $0\src_r3[0:0] attribute \src "libresoc.v:189293.3-189302.6" wire width 2 $0\src_r4$next[1:0]$12762 attribute \src "libresoc.v:188862.3-188863.29" wire width 2 $0\src_r4[1:0] attribute \src "libresoc.v:189303.3-189312.6" wire width 2 $0\src_r5$next[1:0]$12765 attribute \src "libresoc.v:188860.3-188861.29" wire width 2 $0\src_r5[1:0] attribute \src "libresoc.v:188315.7-188315.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:188325.7-188325.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:189322.3-189330.6" wire $1\alu_l_r_alu$next[0:0]$12772 attribute \src "libresoc.v:188333.7-188333.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:189108.3-189120.6" wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 attribute \src "libresoc.v:188378.14-188378.49" wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] attribute \src "libresoc.v:189108.3-189120.6" wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12698 attribute \src "libresoc.v:188382.14-188382.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] attribute \src "libresoc.v:189108.3-189120.6" wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 attribute \src "libresoc.v:188461.13-188461.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] attribute \src "libresoc.v:189108.3-189120.6" wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 attribute \src "libresoc.v:188465.7-188465.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] attribute \src "libresoc.v:189313.3-189321.6" wire $1\alui_l_r_alui$next[0:0]$12769 attribute \src "libresoc.v:188483.7-188483.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:189121.3-189142.6" wire width 64 $1\data_r0__o$next[63:0]$12704 attribute \src "libresoc.v:188515.14-188515.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:189121.3-189142.6" wire $1\data_r0__o_ok$next[0:0]$12705 attribute \src "libresoc.v:188519.7-188519.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:189143.3-189164.6" wire width 64 $1\data_r1__spr1$next[63:0]$12712 attribute \src "libresoc.v:188523.14-188523.50" wire width 64 $1\data_r1__spr1[63:0] attribute \src "libresoc.v:189143.3-189164.6" wire $1\data_r1__spr1_ok$next[0:0]$12713 attribute \src "libresoc.v:188527.7-188527.30" wire $1\data_r1__spr1_ok[0:0] attribute \src "libresoc.v:189165.3-189186.6" wire width 64 $1\data_r2__fast1$next[63:0]$12720 attribute \src "libresoc.v:188531.14-188531.51" wire width 64 $1\data_r2__fast1[63:0] attribute \src "libresoc.v:189165.3-189186.6" wire $1\data_r2__fast1_ok$next[0:0]$12721 attribute \src "libresoc.v:188535.7-188535.31" wire $1\data_r2__fast1_ok[0:0] attribute \src "libresoc.v:189187.3-189208.6" wire $1\data_r3__xer_so$next[0:0]$12728 attribute \src "libresoc.v:188539.7-188539.29" wire $1\data_r3__xer_so[0:0] attribute \src "libresoc.v:189187.3-189208.6" wire $1\data_r3__xer_so_ok$next[0:0]$12729 attribute \src "libresoc.v:188543.7-188543.32" wire $1\data_r3__xer_so_ok[0:0] attribute \src "libresoc.v:189209.3-189230.6" wire width 2 $1\data_r4__xer_ov$next[1:0]$12736 attribute \src "libresoc.v:188547.13-188547.35" wire width 2 $1\data_r4__xer_ov[1:0] attribute \src "libresoc.v:189209.3-189230.6" wire $1\data_r4__xer_ov_ok$next[0:0]$12737 attribute \src "libresoc.v:188551.7-188551.32" wire $1\data_r4__xer_ov_ok[0:0] attribute \src "libresoc.v:189231.3-189252.6" wire width 2 $1\data_r5__xer_ca$next[1:0]$12744 attribute \src "libresoc.v:188555.13-188555.35" wire width 2 $1\data_r5__xer_ca[1:0] attribute \src "libresoc.v:189231.3-189252.6" wire $1\data_r5__xer_ca_ok$next[0:0]$12745 attribute \src "libresoc.v:188559.7-188559.32" wire $1\data_r5__xer_ca_ok[0:0] attribute \src "libresoc.v:189331.3-189340.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:189341.3-189350.6" wire width 64 $1\dest2_o[63:0] attribute \src "libresoc.v:189351.3-189360.6" wire width 64 $1\dest3_o[63:0] attribute \src "libresoc.v:189361.3-189370.6" wire $1\dest4_o[0:0] attribute \src "libresoc.v:189371.3-189380.6" wire width 2 $1\dest5_o[1:0] attribute \src "libresoc.v:189381.3-189390.6" wire width 2 $1\dest6_o[1:0] attribute \src "libresoc.v:189063.3-189071.6" wire $1\opc_l_r_opc$next[0:0]$12679 attribute \src "libresoc.v:188587.7-188587.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:189054.3-189062.6" wire $1\opc_l_s_opc$next[0:0]$12676 attribute \src "libresoc.v:188591.7-188591.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:189391.3-189399.6" wire width 6 $1\prev_wr_go$next[5:0]$12781 attribute \src "libresoc.v:188693.13-188693.31" wire width 6 $1\prev_wr_go[5:0] attribute \src "libresoc.v:189008.3-189017.6" wire $1\req_done[0:0] attribute \src "libresoc.v:189099.3-189107.6" wire width 6 $1\req_l_r_req$next[5:0]$12691 attribute \src "libresoc.v:188701.13-188701.32" wire width 6 $1\req_l_r_req[5:0] attribute \src "libresoc.v:189090.3-189098.6" wire width 6 $1\req_l_s_req$next[5:0]$12688 attribute \src "libresoc.v:188705.13-188705.32" wire width 6 $1\req_l_s_req[5:0] attribute \src "libresoc.v:189027.3-189035.6" wire $1\rok_l_r_rdok$next[0:0]$12667 attribute \src "libresoc.v:188717.7-188717.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:189018.3-189026.6" wire $1\rok_l_s_rdok$next[0:0]$12664 attribute \src "libresoc.v:188721.7-188721.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:189045.3-189053.6" wire $1\rst_l_r_rst$next[0:0]$12673 attribute \src "libresoc.v:188725.7-188725.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:189036.3-189044.6" wire $1\rst_l_s_rst$next[0:0]$12670 attribute \src "libresoc.v:188729.7-188729.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:189081.3-189089.6" wire width 6 $1\src_l_r_src$next[5:0]$12685 attribute \src "libresoc.v:188751.13-188751.32" wire width 6 $1\src_l_r_src[5:0] attribute \src "libresoc.v:189072.3-189080.6" wire width 6 $1\src_l_s_src$next[5:0]$12682 attribute \src "libresoc.v:188755.13-188755.32" wire width 6 $1\src_l_s_src[5:0] attribute \src "libresoc.v:189253.3-189262.6" wire width 64 $1\src_r0$next[63:0]$12751 attribute \src "libresoc.v:188759.14-188759.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:189263.3-189272.6" wire width 64 $1\src_r1$next[63:0]$12754 attribute \src "libresoc.v:188763.14-188763.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:189273.3-189282.6" wire width 64 $1\src_r2$next[63:0]$12757 attribute \src "libresoc.v:188767.14-188767.43" wire width 64 $1\src_r2[63:0] attribute \src "libresoc.v:189283.3-189292.6" wire $1\src_r3$next[0:0]$12760 attribute \src "libresoc.v:188771.7-188771.20" wire $1\src_r3[0:0] attribute \src "libresoc.v:189293.3-189302.6" wire width 2 $1\src_r4$next[1:0]$12763 attribute \src "libresoc.v:188775.13-188775.26" wire width 2 $1\src_r4[1:0] attribute \src "libresoc.v:189303.3-189312.6" wire width 2 $1\src_r5$next[1:0]$12766 attribute \src "libresoc.v:188779.13-188779.26" wire width 2 $1\src_r5[1:0] attribute \src "libresoc.v:189121.3-189142.6" wire width 64 $2\data_r0__o$next[63:0]$12706 attribute \src "libresoc.v:189121.3-189142.6" wire $2\data_r0__o_ok$next[0:0]$12707 attribute \src "libresoc.v:189143.3-189164.6" wire width 64 $2\data_r1__spr1$next[63:0]$12714 attribute \src "libresoc.v:189143.3-189164.6" wire $2\data_r1__spr1_ok$next[0:0]$12715 attribute \src "libresoc.v:189165.3-189186.6" wire width 64 $2\data_r2__fast1$next[63:0]$12722 attribute \src "libresoc.v:189165.3-189186.6" wire $2\data_r2__fast1_ok$next[0:0]$12723 attribute \src "libresoc.v:189187.3-189208.6" wire $2\data_r3__xer_so$next[0:0]$12730 attribute \src "libresoc.v:189187.3-189208.6" wire $2\data_r3__xer_so_ok$next[0:0]$12731 attribute \src "libresoc.v:189209.3-189230.6" wire width 2 $2\data_r4__xer_ov$next[1:0]$12738 attribute \src "libresoc.v:189209.3-189230.6" wire $2\data_r4__xer_ov_ok$next[0:0]$12739 attribute \src "libresoc.v:189231.3-189252.6" wire width 2 $2\data_r5__xer_ca$next[1:0]$12746 attribute \src "libresoc.v:189231.3-189252.6" wire $2\data_r5__xer_ca_ok$next[0:0]$12747 attribute \src "libresoc.v:189121.3-189142.6" wire $3\data_r0__o_ok$next[0:0]$12708 attribute \src "libresoc.v:189143.3-189164.6" wire $3\data_r1__spr1_ok$next[0:0]$12716 attribute \src "libresoc.v:189165.3-189186.6" wire $3\data_r2__fast1_ok$next[0:0]$12724 attribute \src "libresoc.v:189187.3-189208.6" wire $3\data_r3__xer_so_ok$next[0:0]$12732 attribute \src "libresoc.v:189209.3-189230.6" wire $3\data_r4__xer_ov_ok$next[0:0]$12740 attribute \src "libresoc.v:189231.3-189252.6" wire $3\data_r5__xer_ca_ok$next[0:0]$12748 attribute \src "libresoc.v:188791.19-188791.133" wire $and$libresoc.v:188791$12559_Y attribute \src "libresoc.v:188792.19-188792.183" wire width 6 $and$libresoc.v:188792$12560_Y attribute \src "libresoc.v:188793.19-188793.115" wire width 6 $and$libresoc.v:188793$12561_Y attribute \src "libresoc.v:188795.19-188795.115" wire width 6 $and$libresoc.v:188795$12563_Y attribute \src "libresoc.v:188796.19-188796.125" wire $and$libresoc.v:188796$12564_Y attribute \src "libresoc.v:188797.19-188797.125" wire $and$libresoc.v:188797$12565_Y attribute \src "libresoc.v:188798.19-188798.125" wire $and$libresoc.v:188798$12566_Y attribute \src "libresoc.v:188799.19-188799.125" wire $and$libresoc.v:188799$12567_Y attribute \src "libresoc.v:188800.19-188800.125" wire $and$libresoc.v:188800$12568_Y attribute \src "libresoc.v:188802.19-188802.125" wire $and$libresoc.v:188802$12570_Y attribute \src "libresoc.v:188803.19-188803.165" wire width 6 $and$libresoc.v:188803$12571_Y attribute \src "libresoc.v:188804.19-188804.121" wire width 6 $and$libresoc.v:188804$12572_Y attribute \src "libresoc.v:188805.19-188805.127" wire $and$libresoc.v:188805$12573_Y attribute \src "libresoc.v:188806.19-188806.127" wire $and$libresoc.v:188806$12574_Y attribute \src "libresoc.v:188808.19-188808.127" wire $and$libresoc.v:188808$12576_Y attribute \src "libresoc.v:188809.19-188809.127" wire $and$libresoc.v:188809$12577_Y attribute \src "libresoc.v:188810.19-188810.127" wire $and$libresoc.v:188810$12578_Y attribute \src "libresoc.v:188811.19-188811.127" wire $and$libresoc.v:188811$12579_Y attribute \src "libresoc.v:188812.18-188812.110" wire $and$libresoc.v:188812$12580_Y attribute \src "libresoc.v:188814.18-188814.98" wire $and$libresoc.v:188814$12582_Y attribute \src "libresoc.v:188816.18-188816.100" wire $and$libresoc.v:188816$12584_Y attribute \src "libresoc.v:188817.18-188817.182" wire width 6 $and$libresoc.v:188817$12585_Y attribute \src "libresoc.v:188819.18-188819.119" wire width 6 $and$libresoc.v:188819$12587_Y attribute \src "libresoc.v:188822.18-188822.116" wire $and$libresoc.v:188822$12590_Y attribute \src "libresoc.v:188827.18-188827.113" wire $and$libresoc.v:188827$12595_Y attribute \src "libresoc.v:188828.18-188828.125" wire width 6 $and$libresoc.v:188828$12596_Y attribute \src "libresoc.v:188830.18-188830.112" wire $and$libresoc.v:188830$12598_Y attribute \src "libresoc.v:188832.18-188832.126" wire $and$libresoc.v:188832$12600_Y attribute \src "libresoc.v:188833.18-188833.126" wire $and$libresoc.v:188833$12601_Y attribute \src "libresoc.v:188834.18-188834.117" wire $and$libresoc.v:188834$12602_Y attribute \src "libresoc.v:188839.18-188839.130" wire $and$libresoc.v:188839$12607_Y attribute \src "libresoc.v:188840.17-188840.123" wire $and$libresoc.v:188840$12608_Y attribute \src "libresoc.v:188841.18-188841.124" wire width 6 $and$libresoc.v:188841$12609_Y attribute \src "libresoc.v:188843.18-188843.116" wire $and$libresoc.v:188843$12611_Y attribute \src "libresoc.v:188844.18-188844.119" wire $and$libresoc.v:188844$12612_Y attribute \src "libresoc.v:188845.18-188845.120" wire $and$libresoc.v:188845$12613_Y attribute \src "libresoc.v:188846.18-188846.121" wire $and$libresoc.v:188846$12614_Y attribute \src "libresoc.v:188847.18-188847.121" wire $and$libresoc.v:188847$12615_Y attribute \src "libresoc.v:188848.18-188848.121" wire $and$libresoc.v:188848$12616_Y attribute \src "libresoc.v:188855.18-188855.134" wire $and$libresoc.v:188855$12623_Y attribute \src "libresoc.v:188829.18-188829.113" wire $eq$libresoc.v:188829$12597_Y attribute \src "libresoc.v:188831.18-188831.119" wire $eq$libresoc.v:188831$12599_Y attribute \src "libresoc.v:188790.17-188790.113" wire width 6 $not$libresoc.v:188790$12558_Y attribute \src "libresoc.v:188794.19-188794.115" wire width 6 $not$libresoc.v:188794$12562_Y attribute \src "libresoc.v:188813.18-188813.97" wire $not$libresoc.v:188813$12581_Y attribute \src "libresoc.v:188815.18-188815.99" wire $not$libresoc.v:188815$12583_Y attribute \src "libresoc.v:188818.18-188818.113" wire width 6 $not$libresoc.v:188818$12586_Y attribute \src "libresoc.v:188821.18-188821.106" wire $not$libresoc.v:188821$12589_Y attribute \src "libresoc.v:188826.18-188826.120" wire $not$libresoc.v:188826$12594_Y attribute \src "libresoc.v:188801.18-188801.118" wire width 6 $or$libresoc.v:188801$12569_Y attribute \src "libresoc.v:188825.18-188825.112" wire $or$libresoc.v:188825$12593_Y attribute \src "libresoc.v:188835.18-188835.122" wire $or$libresoc.v:188835$12603_Y attribute \src "libresoc.v:188836.18-188836.124" wire $or$libresoc.v:188836$12604_Y attribute \src "libresoc.v:188837.18-188837.194" wire width 6 $or$libresoc.v:188837$12605_Y attribute \src "libresoc.v:188838.18-188838.194" wire width 6 $or$libresoc.v:188838$12606_Y attribute \src "libresoc.v:188842.18-188842.120" wire width 6 $or$libresoc.v:188842$12610_Y attribute \src "libresoc.v:188807.17-188807.105" wire $reduce_and$libresoc.v:188807$12575_Y attribute \src "libresoc.v:188820.18-188820.106" wire $reduce_or$libresoc.v:188820$12588_Y attribute \src "libresoc.v:188823.18-188823.113" wire $reduce_or$libresoc.v:188823$12591_Y attribute \src "libresoc.v:188824.18-188824.112" wire $reduce_or$libresoc.v:188824$12592_Y attribute \src "libresoc.v:188849.18-188849.118" wire width 64 $ternary$libresoc.v:188849$12617_Y attribute \src "libresoc.v:188850.18-188850.118" wire width 64 $ternary$libresoc.v:188850$12618_Y attribute \src "libresoc.v:188851.18-188851.118" wire width 64 $ternary$libresoc.v:188851$12619_Y attribute \src "libresoc.v:188852.18-188852.118" wire $ternary$libresoc.v:188852$12620_Y attribute \src "libresoc.v:188853.18-188853.118" wire width 2 $ternary$libresoc.v:188853$12621_Y attribute \src "libresoc.v:188854.18-188854.118" wire width 2 $ternary$libresoc.v:188854$12622_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 6 \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 6 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 6 \$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 6 \$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 6 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 6 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 6 \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 6 \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 6 \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 6 \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 6 \$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 6 \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 6 \$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire \$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 2 \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 6 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_spr0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_fast1$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_spr0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_spr0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_spr0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_spr0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_spr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_spr0_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_spr1$1 attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_spr0_spr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_spr0_spr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_spr0_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_spr0_spr_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_spr0_spr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_spr0_spr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_spr0_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_spr0_spr_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_spr0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_spr0_xer_ca$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 \alu_spr0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_spr0_xer_ov$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \alu_spr0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_spr0_xer_so$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 31 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 6 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 input 10 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 output 9 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 6 input 8 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 input 19 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 6 output 18 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 6 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r1__spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r1__spr1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__spr1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r2__fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r2__fast1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r4__xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r4__xer_ov$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r5__xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 2 \data_r5__xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r5__xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r5__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 20 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 30 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 28 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 26 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 24 \dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \fast1_ok attribute \src "libresoc.v:188179.7-188179.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \oper_i_alu_spr0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 6 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 6 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 6 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 6 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 29 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 11 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 16 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 15 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire input 12 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 14 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 input 13 \src6_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \src_r3$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r4$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 2 \src_r5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:188791$12559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:188791$12559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:188792$12560 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:188792$12560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:188793$12561 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 connect \Y $and$libresoc.v:188793$12561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:188795$12563 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 connect \Y $and$libresoc.v:188795$12563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:188796$12564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:188796$12564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:188797$12565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:188797$12565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:188798$12566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:188798$12566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:188799$12567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:188799$12567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:188800$12568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:188800$12568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:188802$12570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:188802$12570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:188803$12571 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } connect \Y $and$libresoc.v:188803$12571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:188804$12572 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:188804$12572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:188805$12573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:188805$12573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:188806$12574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:188806$12574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:188808$12576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:188808$12576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:188809$12577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o connect \Y $and$libresoc.v:188809$12577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:188810$12578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o connect \Y $and$libresoc.v:188810$12578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:188811$12579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o connect \Y $and$libresoc.v:188811$12579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:188812$12580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 connect \Y $and$libresoc.v:188812$12580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:188814$12582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 connect \Y $and$libresoc.v:188814$12582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:188816$12584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 connect \Y $and$libresoc.v:188816$12584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:188817$12585 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:188817$12585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:188819$12587 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 connect \Y $and$libresoc.v:188819$12587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:188822$12590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 connect \Y $and$libresoc.v:188822$12590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:188827$12595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 connect \Y $and$libresoc.v:188827$12595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:188828$12596 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:188828$12596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:188830$12598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 connect \Y $and$libresoc.v:188830$12598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:188832$12600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i connect \Y $and$libresoc.v:188832$12600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:188833$12601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o connect \Y $and$libresoc.v:188833$12601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:188834$12602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o connect \Y $and$libresoc.v:188834$12602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:188839$12607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:188839$12607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:188840$12608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:188840$12608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:188841$12609 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:188841$12609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:188843$12611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:188843$12611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:188844$12612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:188844$12612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:188845$12613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:188845$12613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:188846$12614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:188846$12614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:188847$12615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:188847$12615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:188848$12616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:188848$12616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:188855$12623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:188855$12623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:188829$12597 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 connect \Y $eq$libresoc.v:188829$12597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:188831$12599 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:188831$12599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:188790$12558 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:188790$12558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:188794$12562 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:188794$12562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:188813$12581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:188813$12581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:188815$12583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:188815$12583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:188818$12586 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:188818$12586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:188821$12589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 connect \Y $not$libresoc.v:188821$12589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:188826$12594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i connect \Y $not$libresoc.v:188826$12594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:188801$12569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:188801$12569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:188825$12593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 connect \Y $or$libresoc.v:188825$12593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:188835$12603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:188835$12603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:188836$12604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:188836$12604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:188837$12605 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:188837$12605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:188838$12606 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:188838$12606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:188842$12610 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:188842$12610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:188807$12575 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 connect \Y $reduce_and$libresoc.v:188807$12575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:188820$12588 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 connect \Y $reduce_or$libresoc.v:188820$12588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:188823$12591 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:188823$12591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:188824$12592 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:188824$12592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:188849$12617 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] connect \Y $ternary$libresoc.v:188849$12617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:188850$12618 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] connect \Y $ternary$libresoc.v:188850$12618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:188851$12619 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:188851$12619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:188852$12620 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] connect \Y $ternary$libresoc.v:188852$12620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:188853$12621 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] connect \Y $ternary$libresoc.v:188853$12621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:188854$12622 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] connect \Y $ternary$libresoc.v:188854$12622_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:188930.14-188936.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:188937.12-188966.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \fast1 \alu_spr0_fast1 connect \fast1$2 \alu_spr0_fast1$2 connect \fast1_ok \fast1_ok connect \n_ready_i \alu_spr0_n_ready_i connect \n_valid_o \alu_spr0_n_valid_o connect \o \alu_spr0_o connect \o_ok \o_ok connect \p_ready_o \alu_spr0_p_ready_o connect \p_valid_i \alu_spr0_p_valid_i connect \ra \alu_spr0_ra connect \spr1 \alu_spr0_spr1 connect \spr1$1 \alu_spr0_spr1$1 connect \spr1_ok \spr1_ok connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit connect \spr_op__insn \alu_spr0_spr_op__insn connect \spr_op__insn_type \alu_spr0_spr_op__insn_type connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit connect \xer_ca \alu_spr0_xer_ca connect \xer_ca$5 \alu_spr0_xer_ca$5 connect \xer_ca_ok \xer_ca_ok connect \xer_ov \alu_spr0_xer_ov connect \xer_ov$4 \alu_spr0_xer_ov$4 connect \xer_ov_ok \xer_ov_ok connect \xer_so \alu_spr0_xer_so connect \xer_so$3 \alu_spr0_xer_so$3 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 attribute \src "libresoc.v:188967.15-188973.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:188974.14-188980.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:188981.14-188987.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:188988.14-188994.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:188995.14-189000.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:189001.14-189007.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:188179.7-188179.20" process $proc$libresoc.v:188179$12782 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:188315.7-188315.24" process $proc$libresoc.v:188315$12783 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:188325.7-188325.26" process $proc$libresoc.v:188325$12784 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:188333.7-188333.25" process $proc$libresoc.v:188333$12785 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:188378.14-188378.49" process $proc$libresoc.v:188378$12786 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end attribute \src "libresoc.v:188382.14-188382.43" process $proc$libresoc.v:188382$12787 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end attribute \src "libresoc.v:188461.13-188461.47" process $proc$libresoc.v:188461$12788 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end attribute \src "libresoc.v:188465.7-188465.39" process $proc$libresoc.v:188465$12789 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end attribute \src "libresoc.v:188483.7-188483.27" process $proc$libresoc.v:188483$12790 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:188515.14-188515.47" process $proc$libresoc.v:188515$12791 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:188519.7-188519.27" process $proc$libresoc.v:188519$12792 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:188523.14-188523.50" process $proc$libresoc.v:188523$12793 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end attribute \src "libresoc.v:188527.7-188527.30" process $proc$libresoc.v:188527$12794 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end attribute \src "libresoc.v:188531.14-188531.51" process $proc$libresoc.v:188531$12795 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end attribute \src "libresoc.v:188535.7-188535.31" process $proc$libresoc.v:188535$12796 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end attribute \src "libresoc.v:188539.7-188539.29" process $proc$libresoc.v:188539$12797 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end attribute \src "libresoc.v:188543.7-188543.32" process $proc$libresoc.v:188543$12798 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end attribute \src "libresoc.v:188547.13-188547.35" process $proc$libresoc.v:188547$12799 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end attribute \src "libresoc.v:188551.7-188551.32" process $proc$libresoc.v:188551$12800 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end attribute \src "libresoc.v:188555.13-188555.35" process $proc$libresoc.v:188555$12801 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end attribute \src "libresoc.v:188559.7-188559.32" process $proc$libresoc.v:188559$12802 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end attribute \src "libresoc.v:188587.7-188587.25" process $proc$libresoc.v:188587$12803 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:188591.7-188591.25" process $proc$libresoc.v:188591$12804 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:188693.13-188693.31" process $proc$libresoc.v:188693$12805 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end attribute \src "libresoc.v:188701.13-188701.32" process $proc$libresoc.v:188701$12806 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end attribute \src "libresoc.v:188705.13-188705.32" process $proc$libresoc.v:188705$12807 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end attribute \src "libresoc.v:188717.7-188717.26" process $proc$libresoc.v:188717$12808 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:188721.7-188721.26" process $proc$libresoc.v:188721$12809 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:188725.7-188725.25" process $proc$libresoc.v:188725$12810 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:188729.7-188729.25" process $proc$libresoc.v:188729$12811 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:188751.13-188751.32" process $proc$libresoc.v:188751$12812 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end attribute \src "libresoc.v:188755.13-188755.32" process $proc$libresoc.v:188755$12813 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end attribute \src "libresoc.v:188759.14-188759.43" process $proc$libresoc.v:188759$12814 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:188763.14-188763.43" process $proc$libresoc.v:188763$12815 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:188767.14-188767.43" process $proc$libresoc.v:188767$12816 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end attribute \src "libresoc.v:188771.7-188771.20" process $proc$libresoc.v:188771$12817 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end attribute \src "libresoc.v:188775.13-188775.26" process $proc$libresoc.v:188775$12818 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end attribute \src "libresoc.v:188779.13-188779.26" process $proc$libresoc.v:188779$12819 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end attribute \src "libresoc.v:188856.3-188857.39" process $proc$libresoc.v:188856$12624 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:188858.3-188859.43" process $proc$libresoc.v:188858$12625 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:188860.3-188861.29" process $proc$libresoc.v:188860$12626 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end attribute \src "libresoc.v:188862.3-188863.29" process $proc$libresoc.v:188862$12627 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end attribute \src "libresoc.v:188864.3-188865.29" process $proc$libresoc.v:188864$12628 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end attribute \src "libresoc.v:188866.3-188867.29" process $proc$libresoc.v:188866$12629 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end attribute \src "libresoc.v:188868.3-188869.29" process $proc$libresoc.v:188868$12630 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:188870.3-188871.29" process $proc$libresoc.v:188870$12631 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:188872.3-188873.47" process $proc$libresoc.v:188872$12632 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end attribute \src "libresoc.v:188874.3-188875.53" process $proc$libresoc.v:188874$12633 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end attribute \src "libresoc.v:188876.3-188877.47" process $proc$libresoc.v:188876$12634 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end attribute \src "libresoc.v:188878.3-188879.53" process $proc$libresoc.v:188878$12635 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end attribute \src "libresoc.v:188880.3-188881.47" process $proc$libresoc.v:188880$12636 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end attribute \src "libresoc.v:188882.3-188883.53" process $proc$libresoc.v:188882$12637 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end attribute \src "libresoc.v:188884.3-188885.45" process $proc$libresoc.v:188884$12638 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end attribute \src "libresoc.v:188886.3-188887.51" process $proc$libresoc.v:188886$12639 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end attribute \src "libresoc.v:188888.3-188889.43" process $proc$libresoc.v:188888$12640 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end attribute \src "libresoc.v:188890.3-188891.49" process $proc$libresoc.v:188890$12641 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end attribute \src "libresoc.v:188892.3-188893.37" process $proc$libresoc.v:188892$12642 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:188894.3-188895.43" process $proc$libresoc.v:188894$12643 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:188896.3-188897.69" process $proc$libresoc.v:188896$12644 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end attribute \src "libresoc.v:188898.3-188899.65" process $proc$libresoc.v:188898$12645 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end attribute \src "libresoc.v:188900.3-188901.59" process $proc$libresoc.v:188900$12646 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end attribute \src "libresoc.v:188902.3-188903.67" process $proc$libresoc.v:188902$12647 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end attribute \src "libresoc.v:188904.3-188905.39" process $proc$libresoc.v:188904$12648 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end attribute \src "libresoc.v:188906.3-188907.39" process $proc$libresoc.v:188906$12649 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end attribute \src "libresoc.v:188908.3-188909.39" process $proc$libresoc.v:188908$12650 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end attribute \src "libresoc.v:188910.3-188911.39" process $proc$libresoc.v:188910$12651 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end attribute \src "libresoc.v:188912.3-188913.39" process $proc$libresoc.v:188912$12652 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:188914.3-188915.39" process $proc$libresoc.v:188914$12653 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:188916.3-188917.39" process $proc$libresoc.v:188916$12654 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:188918.3-188919.39" process $proc$libresoc.v:188918$12655 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:188920.3-188921.41" process $proc$libresoc.v:188920$12656 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:188922.3-188923.41" process $proc$libresoc.v:188922$12657 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:188924.3-188925.37" process $proc$libresoc.v:188924$12658 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end attribute \src "libresoc.v:188926.3-188927.40" process $proc$libresoc.v:188926$12659 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:188928.3-188929.25" process $proc$libresoc.v:188928$12660 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:189008.3-189017.6" process $proc$libresoc.v:189008$12661 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:189009.5-189009.29" switch \initial attribute \src "libresoc.v:189009.9-189009.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$50 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:189018.3-189026.6" process $proc$libresoc.v:189018$12662 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$12663 $1\rok_l_s_rdok$next[0:0]$12664 attribute \src "libresoc.v:189019.5-189019.29" switch \initial attribute \src "libresoc.v:189019.9-189019.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$12664 1'0 case assign $1\rok_l_s_rdok$next[0:0]$12664 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12663 end attribute \src "libresoc.v:189027.3-189035.6" process $proc$libresoc.v:189027$12665 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$12666 $1\rok_l_r_rdok$next[0:0]$12667 attribute \src "libresoc.v:189028.5-189028.29" switch \initial attribute \src "libresoc.v:189028.9-189028.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$12667 1'1 case assign $1\rok_l_r_rdok$next[0:0]$12667 \$68 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12666 end attribute \src "libresoc.v:189036.3-189044.6" process $proc$libresoc.v:189036$12668 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$12669 $1\rst_l_s_rst$next[0:0]$12670 attribute \src "libresoc.v:189037.5-189037.29" switch \initial attribute \src "libresoc.v:189037.9-189037.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$12670 1'0 case assign $1\rst_l_s_rst$next[0:0]$12670 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12669 end attribute \src "libresoc.v:189045.3-189053.6" process $proc$libresoc.v:189045$12671 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$12672 $1\rst_l_r_rst$next[0:0]$12673 attribute \src "libresoc.v:189046.5-189046.29" switch \initial attribute \src "libresoc.v:189046.9-189046.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$12673 1'1 case assign $1\rst_l_r_rst$next[0:0]$12673 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12672 end attribute \src "libresoc.v:189054.3-189062.6" process $proc$libresoc.v:189054$12674 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$12675 $1\opc_l_s_opc$next[0:0]$12676 attribute \src "libresoc.v:189055.5-189055.29" switch \initial attribute \src "libresoc.v:189055.9-189055.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$12676 1'0 case assign $1\opc_l_s_opc$next[0:0]$12676 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12675 end attribute \src "libresoc.v:189063.3-189071.6" process $proc$libresoc.v:189063$12677 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$12678 $1\opc_l_r_opc$next[0:0]$12679 attribute \src "libresoc.v:189064.5-189064.29" switch \initial attribute \src "libresoc.v:189064.9-189064.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$12679 1'1 case assign $1\opc_l_r_opc$next[0:0]$12679 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12678 end attribute \src "libresoc.v:189072.3-189080.6" process $proc$libresoc.v:189072$12680 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$12681 $1\src_l_s_src$next[5:0]$12682 attribute \src "libresoc.v:189073.5-189073.29" switch \initial attribute \src "libresoc.v:189073.9-189073.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[5:0]$12682 6'000000 case assign $1\src_l_s_src$next[5:0]$12682 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12681 end attribute \src "libresoc.v:189081.3-189089.6" process $proc$libresoc.v:189081$12683 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$12684 $1\src_l_r_src$next[5:0]$12685 attribute \src "libresoc.v:189082.5-189082.29" switch \initial attribute \src "libresoc.v:189082.9-189082.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[5:0]$12685 6'111111 case assign $1\src_l_r_src$next[5:0]$12685 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12684 end attribute \src "libresoc.v:189090.3-189098.6" process $proc$libresoc.v:189090$12686 assign { } { } assign { } { } assign $0\req_l_s_req$next[5:0]$12687 $1\req_l_s_req$next[5:0]$12688 attribute \src "libresoc.v:189091.5-189091.29" switch \initial attribute \src "libresoc.v:189091.9-189091.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[5:0]$12688 6'000000 case assign $1\req_l_s_req$next[5:0]$12688 \$70 end sync always update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12687 end attribute \src "libresoc.v:189099.3-189107.6" process $proc$libresoc.v:189099$12689 assign { } { } assign { } { } assign $0\req_l_r_req$next[5:0]$12690 $1\req_l_r_req$next[5:0]$12691 attribute \src "libresoc.v:189100.5-189100.29" switch \initial attribute \src "libresoc.v:189100.9-189100.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[5:0]$12691 6'111111 case assign $1\req_l_r_req$next[5:0]$12691 \$72 end sync always update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12690 end attribute \src "libresoc.v:189108.3-189120.6" process $proc$libresoc.v:189108$12692 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$12693 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 assign $0\alu_spr0_spr_op__insn$next[31:0]$12694 $1\alu_spr0_spr_op__insn$next[31:0]$12698 assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12695 $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12696 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 attribute \src "libresoc.v:189109.5-189109.29" switch \initial attribute \src "libresoc.v:189109.9-189109.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 $1\alu_spr0_spr_op__insn$next[31:0]$12698 $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$12697 \alu_spr0_spr_op__fn_unit assign $1\alu_spr0_spr_op__insn$next[31:0]$12698 \alu_spr0_spr_op__insn assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12699 \alu_spr0_spr_op__insn_type assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12700 \alu_spr0_spr_op__is_32bit end sync always update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$12693 update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12694 update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12695 update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12696 end attribute \src "libresoc.v:189121.3-189142.6" process $proc$libresoc.v:189121$12701 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$12702 $2\data_r0__o$next[63:0]$12706 assign { } { } assign $0\data_r0__o_ok$next[0:0]$12703 $3\data_r0__o_ok$next[0:0]$12708 attribute \src "libresoc.v:189122.5-189122.29" switch \initial attribute \src "libresoc.v:189122.9-189122.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$12705 $1\data_r0__o$next[63:0]$12704 } { \o_ok \alu_spr0_o } case assign $1\data_r0__o$next[63:0]$12704 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$12705 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$12707 $2\data_r0__o$next[63:0]$12706 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$12706 $1\data_r0__o$next[63:0]$12704 assign $2\data_r0__o_ok$next[0:0]$12707 $1\data_r0__o_ok$next[0:0]$12705 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$12708 1'0 case assign $3\data_r0__o_ok$next[0:0]$12708 $2\data_r0__o_ok$next[0:0]$12707 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$12702 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12703 end attribute \src "libresoc.v:189143.3-189164.6" process $proc$libresoc.v:189143$12709 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__spr1$next[63:0]$12710 $2\data_r1__spr1$next[63:0]$12714 assign { } { } assign $0\data_r1__spr1_ok$next[0:0]$12711 $3\data_r1__spr1_ok$next[0:0]$12716 attribute \src "libresoc.v:189144.5-189144.29" switch \initial attribute \src "libresoc.v:189144.9-189144.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__spr1_ok$next[0:0]$12713 $1\data_r1__spr1$next[63:0]$12712 } { \spr1_ok \alu_spr0_spr1 } case assign $1\data_r1__spr1$next[63:0]$12712 \data_r1__spr1 assign $1\data_r1__spr1_ok$next[0:0]$12713 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__spr1_ok$next[0:0]$12715 $2\data_r1__spr1$next[63:0]$12714 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r1__spr1$next[63:0]$12714 $1\data_r1__spr1$next[63:0]$12712 assign $2\data_r1__spr1_ok$next[0:0]$12715 $1\data_r1__spr1_ok$next[0:0]$12713 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__spr1_ok$next[0:0]$12716 1'0 case assign $3\data_r1__spr1_ok$next[0:0]$12716 $2\data_r1__spr1_ok$next[0:0]$12715 end sync always update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12710 update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12711 end attribute \src "libresoc.v:189165.3-189186.6" process $proc$libresoc.v:189165$12717 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__fast1$next[63:0]$12718 $2\data_r2__fast1$next[63:0]$12722 assign { } { } assign $0\data_r2__fast1_ok$next[0:0]$12719 $3\data_r2__fast1_ok$next[0:0]$12724 attribute \src "libresoc.v:189166.5-189166.29" switch \initial attribute \src "libresoc.v:189166.9-189166.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__fast1_ok$next[0:0]$12721 $1\data_r2__fast1$next[63:0]$12720 } { \fast1_ok \alu_spr0_fast1 } case assign $1\data_r2__fast1$next[63:0]$12720 \data_r2__fast1 assign $1\data_r2__fast1_ok$next[0:0]$12721 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__fast1_ok$next[0:0]$12723 $2\data_r2__fast1$next[63:0]$12722 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r2__fast1$next[63:0]$12722 $1\data_r2__fast1$next[63:0]$12720 assign $2\data_r2__fast1_ok$next[0:0]$12723 $1\data_r2__fast1_ok$next[0:0]$12721 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__fast1_ok$next[0:0]$12724 1'0 case assign $3\data_r2__fast1_ok$next[0:0]$12724 $2\data_r2__fast1_ok$next[0:0]$12723 end sync always update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12718 update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12719 end attribute \src "libresoc.v:189187.3-189208.6" process $proc$libresoc.v:189187$12725 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r3__xer_so$next[0:0]$12726 $2\data_r3__xer_so$next[0:0]$12730 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$12727 $3\data_r3__xer_so_ok$next[0:0]$12732 attribute \src "libresoc.v:189188.5-189188.29" switch \initial attribute \src "libresoc.v:189188.9-189188.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r3__xer_so_ok$next[0:0]$12729 $1\data_r3__xer_so$next[0:0]$12728 } { \xer_so_ok \alu_spr0_xer_so } case assign $1\data_r3__xer_so$next[0:0]$12728 \data_r3__xer_so assign $1\data_r3__xer_so_ok$next[0:0]$12729 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r3__xer_so_ok$next[0:0]$12731 $2\data_r3__xer_so$next[0:0]$12730 } 2'00 case assign $2\data_r3__xer_so$next[0:0]$12730 $1\data_r3__xer_so$next[0:0]$12728 assign $2\data_r3__xer_so_ok$next[0:0]$12731 $1\data_r3__xer_so_ok$next[0:0]$12729 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r3__xer_so_ok$next[0:0]$12732 1'0 case assign $3\data_r3__xer_so_ok$next[0:0]$12732 $2\data_r3__xer_so_ok$next[0:0]$12731 end sync always update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12726 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12727 end attribute \src "libresoc.v:189209.3-189230.6" process $proc$libresoc.v:189209$12733 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r4__xer_ov$next[1:0]$12734 $2\data_r4__xer_ov$next[1:0]$12738 assign { } { } assign $0\data_r4__xer_ov_ok$next[0:0]$12735 $3\data_r4__xer_ov_ok$next[0:0]$12740 attribute \src "libresoc.v:189210.5-189210.29" switch \initial attribute \src "libresoc.v:189210.9-189210.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r4__xer_ov_ok$next[0:0]$12737 $1\data_r4__xer_ov$next[1:0]$12736 } { \xer_ov_ok \alu_spr0_xer_ov } case assign $1\data_r4__xer_ov$next[1:0]$12736 \data_r4__xer_ov assign $1\data_r4__xer_ov_ok$next[0:0]$12737 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r4__xer_ov_ok$next[0:0]$12739 $2\data_r4__xer_ov$next[1:0]$12738 } 3'000 case assign $2\data_r4__xer_ov$next[1:0]$12738 $1\data_r4__xer_ov$next[1:0]$12736 assign $2\data_r4__xer_ov_ok$next[0:0]$12739 $1\data_r4__xer_ov_ok$next[0:0]$12737 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r4__xer_ov_ok$next[0:0]$12740 1'0 case assign $3\data_r4__xer_ov_ok$next[0:0]$12740 $2\data_r4__xer_ov_ok$next[0:0]$12739 end sync always update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12734 update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12735 end attribute \src "libresoc.v:189231.3-189252.6" process $proc$libresoc.v:189231$12741 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r5__xer_ca$next[1:0]$12742 $2\data_r5__xer_ca$next[1:0]$12746 assign { } { } assign $0\data_r5__xer_ca_ok$next[0:0]$12743 $3\data_r5__xer_ca_ok$next[0:0]$12748 attribute \src "libresoc.v:189232.5-189232.29" switch \initial attribute \src "libresoc.v:189232.9-189232.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r5__xer_ca_ok$next[0:0]$12745 $1\data_r5__xer_ca$next[1:0]$12744 } { \xer_ca_ok \alu_spr0_xer_ca } case assign $1\data_r5__xer_ca$next[1:0]$12744 \data_r5__xer_ca assign $1\data_r5__xer_ca_ok$next[0:0]$12745 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r5__xer_ca_ok$next[0:0]$12747 $2\data_r5__xer_ca$next[1:0]$12746 } 3'000 case assign $2\data_r5__xer_ca$next[1:0]$12746 $1\data_r5__xer_ca$next[1:0]$12744 assign $2\data_r5__xer_ca_ok$next[0:0]$12747 $1\data_r5__xer_ca_ok$next[0:0]$12745 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r5__xer_ca_ok$next[0:0]$12748 1'0 case assign $3\data_r5__xer_ca_ok$next[0:0]$12748 $2\data_r5__xer_ca_ok$next[0:0]$12747 end sync always update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12742 update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12743 end attribute \src "libresoc.v:189253.3-189262.6" process $proc$libresoc.v:189253$12749 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$12750 $1\src_r0$next[63:0]$12751 attribute \src "libresoc.v:189254.5-189254.29" switch \initial attribute \src "libresoc.v:189254.9-189254.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$12751 \src1_i case assign $1\src_r0$next[63:0]$12751 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$12750 end attribute \src "libresoc.v:189263.3-189272.6" process $proc$libresoc.v:189263$12752 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$12753 $1\src_r1$next[63:0]$12754 attribute \src "libresoc.v:189264.5-189264.29" switch \initial attribute \src "libresoc.v:189264.9-189264.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$12754 \src2_i case assign $1\src_r1$next[63:0]$12754 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$12753 end attribute \src "libresoc.v:189273.3-189282.6" process $proc$libresoc.v:189273$12755 assign { } { } assign { } { } assign $0\src_r2$next[63:0]$12756 $1\src_r2$next[63:0]$12757 attribute \src "libresoc.v:189274.5-189274.29" switch \initial attribute \src "libresoc.v:189274.9-189274.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[63:0]$12757 \src3_i case assign $1\src_r2$next[63:0]$12757 \src_r2 end sync always update \src_r2$next $0\src_r2$next[63:0]$12756 end attribute \src "libresoc.v:189283.3-189292.6" process $proc$libresoc.v:189283$12758 assign { } { } assign { } { } assign $0\src_r3$next[0:0]$12759 $1\src_r3$next[0:0]$12760 attribute \src "libresoc.v:189284.5-189284.29" switch \initial attribute \src "libresoc.v:189284.9-189284.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r3$next[0:0]$12760 \src4_i case assign $1\src_r3$next[0:0]$12760 \src_r3 end sync always update \src_r3$next $0\src_r3$next[0:0]$12759 end attribute \src "libresoc.v:189293.3-189302.6" process $proc$libresoc.v:189293$12761 assign { } { } assign { } { } assign $0\src_r4$next[1:0]$12762 $1\src_r4$next[1:0]$12763 attribute \src "libresoc.v:189294.5-189294.29" switch \initial attribute \src "libresoc.v:189294.9-189294.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r4$next[1:0]$12763 \src5_i case assign $1\src_r4$next[1:0]$12763 \src_r4 end sync always update \src_r4$next $0\src_r4$next[1:0]$12762 end attribute \src "libresoc.v:189303.3-189312.6" process $proc$libresoc.v:189303$12764 assign { } { } assign { } { } assign $0\src_r5$next[1:0]$12765 $1\src_r5$next[1:0]$12766 attribute \src "libresoc.v:189304.5-189304.29" switch \initial attribute \src "libresoc.v:189304.9-189304.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r5$next[1:0]$12766 \src6_i case assign $1\src_r5$next[1:0]$12766 \src_r5 end sync always update \src_r5$next $0\src_r5$next[1:0]$12765 end attribute \src "libresoc.v:189313.3-189321.6" process $proc$libresoc.v:189313$12767 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$12768 $1\alui_l_r_alui$next[0:0]$12769 attribute \src "libresoc.v:189314.5-189314.29" switch \initial attribute \src "libresoc.v:189314.9-189314.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$12769 1'1 case assign $1\alui_l_r_alui$next[0:0]$12769 \$98 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12768 end attribute \src "libresoc.v:189322.3-189330.6" process $proc$libresoc.v:189322$12770 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$12771 $1\alu_l_r_alu$next[0:0]$12772 attribute \src "libresoc.v:189323.5-189323.29" switch \initial attribute \src "libresoc.v:189323.9-189323.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$12772 1'1 case assign $1\alu_l_r_alu$next[0:0]$12772 \$100 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12771 end attribute \src "libresoc.v:189331.3-189340.6" process $proc$libresoc.v:189331$12773 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:189332.5-189332.29" switch \initial attribute \src "libresoc.v:189332.9-189332.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:189341.3-189350.6" process $proc$libresoc.v:189341$12774 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] attribute \src "libresoc.v:189342.5-189342.29" switch \initial attribute \src "libresoc.v:189342.9-189342.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$128 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[63:0] \data_r1__spr1 case assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest2_o $0\dest2_o[63:0] end attribute \src "libresoc.v:189351.3-189360.6" process $proc$libresoc.v:189351$12775 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] attribute \src "libresoc.v:189352.5-189352.29" switch \initial attribute \src "libresoc.v:189352.9-189352.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[63:0] \data_r2__fast1 case assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest3_o $0\dest3_o[63:0] end attribute \src "libresoc.v:189361.3-189370.6" process $proc$libresoc.v:189361$12776 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] attribute \src "libresoc.v:189362.5-189362.29" switch \initial attribute \src "libresoc.v:189362.9-189362.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest4_o[0:0] \data_r3__xer_so case assign $1\dest4_o[0:0] 1'0 end sync always update \dest4_o $0\dest4_o[0:0] end attribute \src "libresoc.v:189371.3-189380.6" process $proc$libresoc.v:189371$12777 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] attribute \src "libresoc.v:189372.5-189372.29" switch \initial attribute \src "libresoc.v:189372.9-189372.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest5_o[1:0] \data_r4__xer_ov case assign $1\dest5_o[1:0] 2'00 end sync always update \dest5_o $0\dest5_o[1:0] end attribute \src "libresoc.v:189381.3-189390.6" process $proc$libresoc.v:189381$12778 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] attribute \src "libresoc.v:189382.5-189382.29" switch \initial attribute \src "libresoc.v:189382.9-189382.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest6_o[1:0] \data_r5__xer_ca case assign $1\dest6_o[1:0] 2'00 end sync always update \dest6_o $0\dest6_o[1:0] end attribute \src "libresoc.v:189391.3-189399.6" process $proc$libresoc.v:189391$12779 assign { } { } assign { } { } assign $0\prev_wr_go$next[5:0]$12780 $1\prev_wr_go$next[5:0]$12781 attribute \src "libresoc.v:189392.5-189392.29" switch \initial attribute \src "libresoc.v:189392.9-189392.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[5:0]$12781 6'000000 case assign $1\prev_wr_go$next[5:0]$12781 \$24 end sync always update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12780 end connect \$9 $not$libresoc.v:188790$12558_Y connect \$100 $and$libresoc.v:188791$12559_Y connect \$102 $and$libresoc.v:188792$12560_Y connect \$104 $and$libresoc.v:188793$12561_Y connect \$106 $not$libresoc.v:188794$12562_Y connect \$108 $and$libresoc.v:188795$12563_Y connect \$110 $and$libresoc.v:188796$12564_Y connect \$112 $and$libresoc.v:188797$12565_Y connect \$114 $and$libresoc.v:188798$12566_Y connect \$116 $and$libresoc.v:188799$12567_Y connect \$118 $and$libresoc.v:188800$12568_Y connect \$11 $or$libresoc.v:188801$12569_Y connect \$120 $and$libresoc.v:188802$12570_Y connect \$122 $and$libresoc.v:188803$12571_Y connect \$124 $and$libresoc.v:188804$12572_Y connect \$126 $and$libresoc.v:188805$12573_Y connect \$128 $and$libresoc.v:188806$12574_Y connect \$8 $reduce_and$libresoc.v:188807$12575_Y connect \$130 $and$libresoc.v:188808$12576_Y connect \$132 $and$libresoc.v:188809$12577_Y connect \$134 $and$libresoc.v:188810$12578_Y connect \$136 $and$libresoc.v:188811$12579_Y connect \$14 $and$libresoc.v:188812$12580_Y connect \$16 $not$libresoc.v:188813$12581_Y connect \$18 $and$libresoc.v:188814$12582_Y connect \$20 $not$libresoc.v:188815$12583_Y connect \$22 $and$libresoc.v:188816$12584_Y connect \$24 $and$libresoc.v:188817$12585_Y connect \$28 $not$libresoc.v:188818$12586_Y connect \$30 $and$libresoc.v:188819$12587_Y connect \$27 $reduce_or$libresoc.v:188820$12588_Y connect \$26 $not$libresoc.v:188821$12589_Y connect \$34 $and$libresoc.v:188822$12590_Y connect \$36 $reduce_or$libresoc.v:188823$12591_Y connect \$38 $reduce_or$libresoc.v:188824$12592_Y connect \$40 $or$libresoc.v:188825$12593_Y connect \$42 $not$libresoc.v:188826$12594_Y connect \$44 $and$libresoc.v:188827$12595_Y connect \$46 $and$libresoc.v:188828$12596_Y connect \$48 $eq$libresoc.v:188829$12597_Y connect \$50 $and$libresoc.v:188830$12598_Y connect \$52 $eq$libresoc.v:188831$12599_Y connect \$54 $and$libresoc.v:188832$12600_Y connect \$56 $and$libresoc.v:188833$12601_Y connect \$58 $and$libresoc.v:188834$12602_Y connect \$60 $or$libresoc.v:188835$12603_Y connect \$62 $or$libresoc.v:188836$12604_Y connect \$64 $or$libresoc.v:188837$12605_Y connect \$66 $or$libresoc.v:188838$12606_Y connect \$68 $and$libresoc.v:188839$12607_Y connect \$6 $and$libresoc.v:188840$12608_Y connect \$70 $and$libresoc.v:188841$12609_Y connect \$72 $or$libresoc.v:188842$12610_Y connect \$74 $and$libresoc.v:188843$12611_Y connect \$76 $and$libresoc.v:188844$12612_Y connect \$78 $and$libresoc.v:188845$12613_Y connect \$80 $and$libresoc.v:188846$12614_Y connect \$82 $and$libresoc.v:188847$12615_Y connect \$84 $and$libresoc.v:188848$12616_Y connect \$86 $ternary$libresoc.v:188849$12617_Y connect \$88 $ternary$libresoc.v:188850$12618_Y connect \$90 $ternary$libresoc.v:188851$12619_Y connect \$92 $ternary$libresoc.v:188852$12620_Y connect \$94 $ternary$libresoc.v:188853$12621_Y connect \$96 $ternary$libresoc.v:188854$12622_Y connect \$98 $and$libresoc.v:188855$12623_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 connect \cu_rd__rel_o \$108 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_spr0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_spr0_p_valid_i \alui_l_q_alui connect \alu_spr0_xer_ca$5 \$96 connect \alu_spr0_xer_ov$4 \$94 connect \alu_spr0_xer_so$3 \$92 connect \alu_spr0_fast1$2 \$90 connect \alu_spr0_spr1$1 \$88 connect \alu_spr0_ra \$86 connect \cu_wrmask_o { \$84 \$82 \$80 \$78 \$76 \$74 } connect \reset_r \$66 connect \reset_w \$64 connect \rst_r \$62 connect \reset \$60 connect \wr_any \$40 connect \cu_done_o \$34 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$22 connect \alu_done_dly$next \alu_done connect \alu_done \alu_spr0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$18 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end attribute \src "libresoc.v:189435.1-189959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main attribute \src "libresoc.v:189708.3-189723.6" wire width 64 $0\fast1$7[63:0]$12828 attribute \src "libresoc.v:189789.3-189804.6" wire $0\fast1_ok[0:0] attribute \src "libresoc.v:189436.7-189436.20" wire $0\initial[0:0] attribute \src "libresoc.v:189743.3-189788.6" wire width 64 $0\o[63:0] attribute \src "libresoc.v:189743.3-189788.6" wire $0\o_ok[0:0] attribute \src "libresoc.v:189937.3-189955.6" wire width 64 $0\spr1$6[63:0]$12853 attribute \src "libresoc.v:189724.3-189742.6" wire $0\spr1_ok[0:0] attribute \src "libresoc.v:189892.3-189915.6" wire width 2 $0\xer_ca$10[1:0]$12847 attribute \src "libresoc.v:189916.3-189936.6" wire $0\xer_ca_ok[0:0] attribute \src "libresoc.v:189847.3-189870.6" wire width 2 $0\xer_ov$9[1:0]$12841 attribute \src "libresoc.v:189871.3-189891.6" wire $0\xer_ov_ok[0:0] attribute \src "libresoc.v:189805.3-189825.6" wire $0\xer_so$8[0:0]$12835 attribute \src "libresoc.v:189826.3-189846.6" wire $0\xer_so_ok[0:0] attribute \src "libresoc.v:189708.3-189723.6" wire width 64 $1\fast1$7[63:0]$12829 attribute \src "libresoc.v:189789.3-189804.6" wire $1\fast1_ok[0:0] attribute \src "libresoc.v:189743.3-189788.6" wire width 64 $1\o[63:0] attribute \src "libresoc.v:189743.3-189788.6" wire $1\o_ok[0:0] attribute \src "libresoc.v:189937.3-189955.6" wire width 64 $1\spr1$6[63:0]$12854 attribute \src "libresoc.v:189724.3-189742.6" wire $1\spr1_ok[0:0] attribute \src "libresoc.v:189892.3-189915.6" wire width 2 $1\xer_ca$10[1:0]$12848 attribute \src "libresoc.v:189916.3-189936.6" wire $1\xer_ca_ok[0:0] attribute \src "libresoc.v:189847.3-189870.6" wire width 2 $1\xer_ov$9[1:0]$12842 attribute \src "libresoc.v:189871.3-189891.6" wire $1\xer_ov_ok[0:0] attribute \src "libresoc.v:189805.3-189825.6" wire $1\xer_so$8[0:0]$12836 attribute \src "libresoc.v:189826.3-189846.6" wire $1\xer_so_ok[0:0] attribute \src "libresoc.v:189708.3-189723.6" wire width 64 $2\fast1$7[63:0]$12830 attribute \src "libresoc.v:189789.3-189804.6" wire $2\fast1_ok[0:0] attribute \src "libresoc.v:189743.3-189788.6" wire width 64 $2\o[63:0] attribute \src "libresoc.v:189937.3-189955.6" wire width 64 $2\spr1$6[63:0]$12855 attribute \src "libresoc.v:189724.3-189742.6" wire $2\spr1_ok[0:0] attribute \src "libresoc.v:189892.3-189915.6" wire width 2 $2\xer_ca$10[1:0]$12849 attribute \src "libresoc.v:189916.3-189936.6" wire $2\xer_ca_ok[0:0] attribute \src "libresoc.v:189847.3-189870.6" wire width 2 $2\xer_ov$9[1:0]$12843 attribute \src "libresoc.v:189871.3-189891.6" wire $2\xer_ov_ok[0:0] attribute \src "libresoc.v:189805.3-189825.6" wire $2\xer_so$8[0:0]$12837 attribute \src "libresoc.v:189826.3-189846.6" wire $2\xer_so_ok[0:0] attribute \src "libresoc.v:189743.3-189788.6" wire width 46 $3\o[63:18] attribute \src "libresoc.v:189892.3-189915.6" wire width 2 $3\xer_ca$10[1:0]$12850 attribute \src "libresoc.v:189916.3-189936.6" wire $3\xer_ca_ok[0:0] attribute \src "libresoc.v:189847.3-189870.6" wire width 2 $3\xer_ov$9[1:0]$12844 attribute \src "libresoc.v:189871.3-189891.6" wire $3\xer_ov_ok[0:0] attribute \src "libresoc.v:189805.3-189825.6" wire $3\xer_so$8[0:0]$12838 attribute \src "libresoc.v:189826.3-189846.6" wire $3\xer_so_ok[0:0] attribute \src "libresoc.v:189701.18-189701.106" wire $eq$libresoc.v:189701$12820_Y attribute \src "libresoc.v:189702.18-189702.106" wire $eq$libresoc.v:189702$12821_Y attribute \src "libresoc.v:189703.18-189703.106" wire $eq$libresoc.v:189703$12822_Y attribute \src "libresoc.v:189704.18-189704.106" wire $eq$libresoc.v:189704$12823_Y attribute \src "libresoc.v:189705.18-189705.106" wire $eq$libresoc.v:189705$12824_Y attribute \src "libresoc.v:189706.18-189706.106" wire $eq$libresoc.v:189706$12825_Y attribute \src "libresoc.v:189707.18-189707.106" wire $eq$libresoc.v:189707$12826_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 7 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 21 \fast1_ok attribute \src "libresoc.v:189436.7-189436.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 11 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 16 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:50" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 6 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 output 18 \spr1$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 19 \spr1_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 2 \spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 output 13 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 output 14 \spr_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 1 \spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 output 12 \spr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 15 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 10 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 26 \xer_ca$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 27 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 9 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 2 output 24 \xer_ov$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 8 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 22 \xer_so$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" cell $eq $eq$libresoc.v:189701$12820 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 connect \Y $eq$libresoc.v:189701$12820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" cell $eq $eq$libresoc.v:189702$12821 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 connect \Y $eq$libresoc.v:189702$12821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" cell $eq $eq$libresoc.v:189703$12822 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 connect \Y $eq$libresoc.v:189703$12822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" cell $eq $eq$libresoc.v:189704$12823 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 connect \Y $eq$libresoc.v:189704$12823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" cell $eq $eq$libresoc.v:189705$12824 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 connect \Y $eq$libresoc.v:189705$12824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" cell $eq $eq$libresoc.v:189706$12825 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 connect \Y $eq$libresoc.v:189706$12825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" cell $eq $eq$libresoc.v:189707$12826 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 connect \Y $eq$libresoc.v:189707$12826_Y end attribute \src "libresoc.v:189436.7-189436.20" process $proc$libresoc.v:189436$12856 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:189708.3-189723.6" process $proc$libresoc.v:189708$12827 assign { } { } assign { } { } assign $0\fast1$7[63:0]$12828 $1\fast1$7[63:0]$12829 attribute \src "libresoc.v:189709.5-189709.29" switch \initial attribute \src "libresoc.v:189709.9-189709.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\fast1$7[63:0]$12829 $2\fast1$7[63:0]$12830 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\fast1$7[63:0]$12830 \ra case assign $2\fast1$7[63:0]$12830 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $1\fast1$7[63:0]$12829 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \fast1$7 $0\fast1$7[63:0]$12828 end attribute \src "libresoc.v:189724.3-189742.6" process $proc$libresoc.v:189724$12831 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] attribute \src "libresoc.v:189725.5-189725.29" switch \initial attribute \src "libresoc.v:189725.9-189725.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign $2\spr1_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\spr1_ok[0:0] 1'1 end case assign $1\spr1_ok[0:0] 1'0 end sync always update \spr1_ok $0\spr1_ok[0:0] end attribute \src "libresoc.v:189743.3-189788.6" process $proc$libresoc.v:189743$12832 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] attribute \src "libresoc.v:189744.5-189744.29" switch \initial attribute \src "libresoc.v:189744.9-189744.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign $1\o_ok[0:0] 1'0 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign { } { } assign $1\o_ok[0:0] 1'1 assign $1\o[63:0] $2\o[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:85" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 assign { } { } assign $2\o[63:0] [17:0] \fast1 [17:0] assign $2\o[63:0] [63:18] $3\o[63:18] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\o[63:18] [45:14] 0 assign $3\o[63:18] [10:2] 9'000000000 assign $3\o[63:18] [13] \xer_so assign $3\o[63:18] [12] \xer_ov [0] assign $3\o[63:18] [1] \xer_ov [1] assign $3\o[63:18] [11] \xer_ca [0] assign $3\o[63:18] [0] \xer_ca [1] case assign $3\o[63:18] \fast1 [63:18] end attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign $2\o[63:0] [63:32] 0 assign $2\o[63:0] [31:0] \fast1 [63:32] attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\o[63:0] \spr1 end case assign $1\o_ok[0:0] 1'0 assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end attribute \src "libresoc.v:189789.3-189804.6" process $proc$libresoc.v:189789$12833 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] attribute \src "libresoc.v:189790.5-189790.29" switch \initial attribute \src "libresoc.v:189790.9-189790.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\fast1_ok[0:0] 1'1 case assign $2\fast1_ok[0:0] 1'0 end case assign $1\fast1_ok[0:0] 1'0 end sync always update \fast1_ok $0\fast1_ok[0:0] end attribute \src "libresoc.v:189805.3-189825.6" process $proc$libresoc.v:189805$12834 assign { } { } assign { } { } assign $0\xer_so$8[0:0]$12835 $1\xer_so$8[0:0]$12836 attribute \src "libresoc.v:189806.5-189806.29" switch \initial attribute \src "libresoc.v:189806.9-189806.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_so$8[0:0]$12836 $2\xer_so$8[0:0]$12837 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_so$8[0:0]$12837 $3\xer_so$8[0:0]$12838 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\xer_so$8[0:0]$12838 \ra [31] case assign $3\xer_so$8[0:0]$12838 1'0 end case assign $2\xer_so$8[0:0]$12837 1'0 end case assign $1\xer_so$8[0:0]$12836 1'0 end sync always update \xer_so$8 $0\xer_so$8[0:0]$12835 end attribute \src "libresoc.v:189826.3-189846.6" process $proc$libresoc.v:189826$12839 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] attribute \src "libresoc.v:189827.5-189827.29" switch \initial attribute \src "libresoc.v:189827.9-189827.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\xer_so_ok[0:0] 1'1 case assign $3\xer_so_ok[0:0] 1'0 end case assign $2\xer_so_ok[0:0] 1'0 end case assign $1\xer_so_ok[0:0] 1'0 end sync always update \xer_so_ok $0\xer_so_ok[0:0] end attribute \src "libresoc.v:189847.3-189870.6" process $proc$libresoc.v:189847$12840 assign { } { } assign { } { } assign $0\xer_ov$9[1:0]$12841 $1\xer_ov$9[1:0]$12842 attribute \src "libresoc.v:189848.5-189848.29" switch \initial attribute \src "libresoc.v:189848.9-189848.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_ov$9[1:0]$12842 $2\xer_ov$9[1:0]$12843 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_ov$9[1:0]$12843 $3\xer_ov$9[1:0]$12844 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\xer_ov$9[1:0]$12844 [0] \ra [30] assign $3\xer_ov$9[1:0]$12844 [1] \ra [19] case assign $3\xer_ov$9[1:0]$12844 2'00 end case assign $2\xer_ov$9[1:0]$12843 2'00 end case assign $1\xer_ov$9[1:0]$12842 2'00 end sync always update \xer_ov$9 $0\xer_ov$9[1:0]$12841 end attribute \src "libresoc.v:189871.3-189891.6" process $proc$libresoc.v:189871$12845 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] attribute \src "libresoc.v:189872.5-189872.29" switch \initial attribute \src "libresoc.v:189872.9-189872.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\xer_ov_ok[0:0] 1'1 case assign $3\xer_ov_ok[0:0] 1'0 end case assign $2\xer_ov_ok[0:0] 1'0 end case assign $1\xer_ov_ok[0:0] 1'0 end sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end attribute \src "libresoc.v:189892.3-189915.6" process $proc$libresoc.v:189892$12846 assign { } { } assign { } { } assign $0\xer_ca$10[1:0]$12847 $1\xer_ca$10[1:0]$12848 attribute \src "libresoc.v:189893.5-189893.29" switch \initial attribute \src "libresoc.v:189893.9-189893.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_ca$10[1:0]$12848 $2\xer_ca$10[1:0]$12849 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_ca$10[1:0]$12849 $3\xer_ca$10[1:0]$12850 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\xer_ca$10[1:0]$12850 [0] \ra [29] assign $3\xer_ca$10[1:0]$12850 [1] \ra [18] case assign $3\xer_ca$10[1:0]$12850 2'00 end case assign $2\xer_ca$10[1:0]$12849 2'00 end case assign $1\xer_ca$10[1:0]$12848 2'00 end sync always update \xer_ca$10 $0\xer_ca$10[1:0]$12847 end attribute \src "libresoc.v:189916.3-189936.6" process $proc$libresoc.v:189916$12851 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] attribute \src "libresoc.v:189917.5-189917.29" switch \initial attribute \src "libresoc.v:189917.9-189917.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\xer_ca_ok[0:0] 1'1 case assign $3\xer_ca_ok[0:0] 1'0 end case assign $2\xer_ca_ok[0:0] 1'0 end case assign $1\xer_ca_ok[0:0] 1'0 end sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end attribute \src "libresoc.v:189937.3-189955.6" process $proc$libresoc.v:189937$12852 assign { } { } assign { } { } assign $0\spr1$6[63:0]$12853 $1\spr1$6[63:0]$12854 attribute \src "libresoc.v:189938.5-189938.29" switch \initial attribute \src "libresoc.v:189938.9-189938.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } assign $1\spr1$6[63:0]$12854 $2\spr1$6[63:0]$12855 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign $2\spr1$6[63:0]$12855 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\spr1$6[63:0]$12855 \ra end case assign $1\spr1$6[63:0]$12854 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \spr1$6 $0\spr1$6[63:0]$12853 end connect \$11 $eq$libresoc.v:189701$12820_Y connect \$13 $eq$libresoc.v:189702$12821_Y connect \$15 $eq$libresoc.v:189703$12822_Y connect \$17 $eq$libresoc.v:189704$12823_Y connect \$19 $eq$libresoc.v:189705$12824_Y connect \$21 $eq$libresoc.v:189706$12825_Y connect \$23 $eq$libresoc.v:189707$12826_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end attribute \src "libresoc.v:189963.1-191429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap attribute \src "libresoc.v:190093.3-190414.6" wire width 3 $0\fast_o[2:0] attribute \src "libresoc.v:190415.3-190736.6" wire $0\fast_o_ok[0:0] attribute \src "libresoc.v:189964.7-189964.20" wire $0\initial[0:0] attribute \src "libresoc.v:190737.3-191082.6" wire width 10 $0\spr_o[9:0] attribute \src "libresoc.v:191083.3-191428.6" wire $0\spr_o_ok[0:0] attribute \src "libresoc.v:190093.3-190414.6" wire width 3 $1\fast_o[2:0] attribute \src "libresoc.v:190415.3-190736.6" wire $1\fast_o_ok[0:0] attribute \src "libresoc.v:190737.3-191082.6" wire width 10 $1\spr_o[9:0] attribute \src "libresoc.v:191083.3-191428.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast_o_ok attribute \src "libresoc.v:189964.7-189964.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \spr_o_ok attribute \src "libresoc.v:189964.7-189964.20" process $proc$libresoc.v:189964$12861 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:190093.3-190414.6" process $proc$libresoc.v:190093$12857 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] attribute \src "libresoc.v:190094.5-190094.29" switch \initial attribute \src "libresoc.v:190094.9-190094.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign { } { } assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign { } { } assign $1\fast_o[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign { } { } assign $1\fast_o[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o[2:0] 3'111 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o[2:0] 3'010 case assign $1\fast_o[2:0] 3'000 end sync always update \fast_o $0\fast_o[2:0] end attribute \src "libresoc.v:190415.3-190736.6" process $proc$libresoc.v:190415$12858 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] attribute \src "libresoc.v:190416.5-190416.29" switch \initial attribute \src "libresoc.v:190416.9-190416.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o_ok[0:0] 1'1 case assign $1\fast_o_ok[0:0] 1'0 end sync always update \fast_o_ok $0\fast_o_ok[0:0] end attribute \src "libresoc.v:190737.3-191082.6" process $proc$libresoc.v:190737$12859 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] attribute \src "libresoc.v:190738.5-190738.29" switch \initial attribute \src "libresoc.v:190738.9-190738.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o[9:0] 10'0000000001 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o[9:0] 10'0000000100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign { } { } assign $1\spr_o[9:0] 10'0000000101 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\spr_o[9:0] 10'0000000110 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign { } { } assign $1\spr_o[9:0] 10'0000000111 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o[9:0] 10'0000001011 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign { } { } assign $1\spr_o[9:0] 10'0000001100 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign { } { } assign $1\spr_o[9:0] 10'0000001101 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign { } { } assign $1\spr_o[9:0] 10'0000001110 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign { } { } assign $1\spr_o[9:0] 10'0000001111 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\spr_o[9:0] 10'0000010000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign { } { } assign $1\spr_o[9:0] 10'0000010001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign { } { } assign $1\spr_o[9:0] 10'0000010010 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign { } { } assign $1\spr_o[9:0] 10'0000010011 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign { } { } assign $1\spr_o[9:0] 10'0000010100 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign { } { } assign $1\spr_o[9:0] 10'0000010101 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign { } { } assign $1\spr_o[9:0] 10'0000010110 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign { } { } assign $1\spr_o[9:0] 10'0000010111 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign { } { } assign $1\spr_o[9:0] 10'0000011000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign { } { } assign $1\spr_o[9:0] 10'0000011001 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign { } { } assign $1\spr_o[9:0] 10'0000011010 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign { } { } assign $1\spr_o[9:0] 10'0000011011 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign { } { } assign $1\spr_o[9:0] 10'0000011100 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign { } { } assign $1\spr_o[9:0] 10'0000011101 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign { } { } assign $1\spr_o[9:0] 10'0000011110 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign { } { } assign $1\spr_o[9:0] 10'0000011111 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign { } { } assign $1\spr_o[9:0] 10'0000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign { } { } assign $1\spr_o[9:0] 10'0000100001 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o[9:0] 10'0000100011 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign { } { } assign $1\spr_o[9:0] 10'0000100100 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign { } { } assign $1\spr_o[9:0] 10'0000100101 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\spr_o[9:0] 10'0000100110 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign { } { } assign $1\spr_o[9:0] 10'0000100111 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign { } { } assign $1\spr_o[9:0] 10'0000101000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign { } { } assign $1\spr_o[9:0] 10'0000101001 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign { } { } assign $1\spr_o[9:0] 10'0000101010 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign { } { } assign $1\spr_o[9:0] 10'0000101011 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign { } { } assign $1\spr_o[9:0] 10'0000101100 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign { } { } assign $1\spr_o[9:0] 10'0000101101 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign { } { } assign $1\spr_o[9:0] 10'0000101110 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign { } { } assign $1\spr_o[9:0] 10'0000101111 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign { } { } assign $1\spr_o[9:0] 10'0000110000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign { } { } assign $1\spr_o[9:0] 10'0000110001 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign { } { } assign $1\spr_o[9:0] 10'0000110010 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign { } { } assign $1\spr_o[9:0] 10'0000110011 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign { } { } assign $1\spr_o[9:0] 10'0000110100 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign { } { } assign $1\spr_o[9:0] 10'0000110101 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign { } { } assign $1\spr_o[9:0] 10'0000110110 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign { } { } assign $1\spr_o[9:0] 10'0000110111 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign { } { } assign $1\spr_o[9:0] 10'0000111000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign { } { } assign $1\spr_o[9:0] 10'0000111001 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign { } { } assign $1\spr_o[9:0] 10'0000111010 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign { } { } assign $1\spr_o[9:0] 10'0000111011 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign { } { } assign $1\spr_o[9:0] 10'0000111100 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign { } { } assign $1\spr_o[9:0] 10'0000111101 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign { } { } assign $1\spr_o[9:0] 10'0000111110 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign { } { } assign $1\spr_o[9:0] 10'0000111111 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign { } { } assign $1\spr_o[9:0] 10'0001000000 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign { } { } assign $1\spr_o[9:0] 10'0001000001 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign { } { } assign $1\spr_o[9:0] 10'0001000010 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o[9:0] 10'0001000011 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign { } { } assign $1\spr_o[9:0] 10'0001000100 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign { } { } assign $1\spr_o[9:0] 10'0001000101 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign { } { } assign $1\spr_o[9:0] 10'0001000110 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign { } { } assign $1\spr_o[9:0] 10'0001000111 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign { } { } assign $1\spr_o[9:0] 10'0001001000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign { } { } assign $1\spr_o[9:0] 10'0001001001 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign { } { } assign $1\spr_o[9:0] 10'0001001010 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign { } { } assign $1\spr_o[9:0] 10'0001001011 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign { } { } assign $1\spr_o[9:0] 10'0001001100 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign { } { } assign $1\spr_o[9:0] 10'0001001101 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign { } { } assign $1\spr_o[9:0] 10'0001001110 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign { } { } assign $1\spr_o[9:0] 10'0001001111 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign { } { } assign $1\spr_o[9:0] 10'0001010000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign { } { } assign $1\spr_o[9:0] 10'0001010001 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign { } { } assign $1\spr_o[9:0] 10'0001010010 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign { } { } assign $1\spr_o[9:0] 10'0001010011 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign { } { } assign $1\spr_o[9:0] 10'0001010100 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign { } { } assign $1\spr_o[9:0] 10'0001010101 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign { } { } assign $1\spr_o[9:0] 10'0001010110 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign { } { } assign $1\spr_o[9:0] 10'0001010111 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign { } { } assign $1\spr_o[9:0] 10'0001011000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign { } { } assign $1\spr_o[9:0] 10'0001011001 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign { } { } assign $1\spr_o[9:0] 10'0001011010 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign { } { } assign $1\spr_o[9:0] 10'0001011011 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign { } { } assign $1\spr_o[9:0] 10'0001011100 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign { } { } assign $1\spr_o[9:0] 10'0001011101 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign { } { } assign $1\spr_o[9:0] 10'0001011110 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign { } { } assign $1\spr_o[9:0] 10'0001011111 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign { } { } assign $1\spr_o[9:0] 10'0001100000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign { } { } assign $1\spr_o[9:0] 10'0001100001 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign { } { } assign $1\spr_o[9:0] 10'0001100010 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign { } { } assign $1\spr_o[9:0] 10'0001100011 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign { } { } assign $1\spr_o[9:0] 10'0001100100 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign { } { } assign $1\spr_o[9:0] 10'0001100101 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign { } { } assign $1\spr_o[9:0] 10'0001100110 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o[9:0] 10'0001101001 attribute \src "libresoc.v:0.0-0.0" case 10'1100110111 assign { } { } assign $1\spr_o[9:0] 10'0001101010 attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } assign $1\spr_o[9:0] 10'0001101011 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } assign $1\spr_o[9:0] 10'0001101100 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } assign $1\spr_o[9:0] 10'0001101101 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } assign $1\spr_o[9:0] 10'0001101110 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } assign $1\spr_o[9:0] 10'0001101111 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } assign $1\spr_o[9:0] 10'0001110000 case assign $1\spr_o[9:0] 10'0000000000 end sync always update \spr_o $0\spr_o[9:0] end attribute \src "libresoc.v:191083.3-191428.6" process $proc$libresoc.v:191083$12860 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] attribute \src "libresoc.v:191084.5-191084.29" switch \initial attribute \src "libresoc.v:191084.9-191084.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100110111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 case assign $1\spr_o_ok[0:0] 1'0 end sync always update \spr_o_ok $0\spr_o_ok[0:0] end end attribute \src "libresoc.v:191433.1-192899.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 attribute \src "libresoc.v:191563.3-191884.6" wire width 3 $0\fast_o[2:0] attribute \src "libresoc.v:191885.3-192206.6" wire $0\fast_o_ok[0:0] attribute \src "libresoc.v:191434.7-191434.20" wire $0\initial[0:0] attribute \src "libresoc.v:192207.3-192552.6" wire width 10 $0\spr_o[9:0] attribute \src "libresoc.v:192553.3-192898.6" wire $0\spr_o_ok[0:0] attribute \src "libresoc.v:191563.3-191884.6" wire width 3 $1\fast_o[2:0] attribute \src "libresoc.v:191885.3-192206.6" wire $1\fast_o_ok[0:0] attribute \src "libresoc.v:192207.3-192552.6" wire width 10 $1\spr_o[9:0] attribute \src "libresoc.v:192553.3-192898.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 4 \fast_o_ok attribute \src "libresoc.v:191434.7-191434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 2 \spr_o_ok attribute \src "libresoc.v:191434.7-191434.20" process $proc$libresoc.v:191434$12866 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:191563.3-191884.6" process $proc$libresoc.v:191563$12862 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] attribute \src "libresoc.v:191564.5-191564.29" switch \initial attribute \src "libresoc.v:191564.9-191564.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign { } { } assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign { } { } assign $1\fast_o[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign { } { } assign $1\fast_o[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o[2:0] 3'111 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o[2:0] 3'010 case assign $1\fast_o[2:0] 3'000 end sync always update \fast_o $0\fast_o[2:0] end attribute \src "libresoc.v:191885.3-192206.6" process $proc$libresoc.v:191885$12863 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] attribute \src "libresoc.v:191886.5-191886.29" switch \initial attribute \src "libresoc.v:191886.9-191886.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign $1\fast_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o_ok[0:0] 1'1 case assign $1\fast_o_ok[0:0] 1'0 end sync always update \fast_o_ok $0\fast_o_ok[0:0] end attribute \src "libresoc.v:192207.3-192552.6" process $proc$libresoc.v:192207$12864 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] attribute \src "libresoc.v:192208.5-192208.29" switch \initial attribute \src "libresoc.v:192208.9-192208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o[9:0] 10'0000000001 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o[9:0] 10'0000000100 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign { } { } assign $1\spr_o[9:0] 10'0000000101 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\spr_o[9:0] 10'0000000110 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign { } { } assign $1\spr_o[9:0] 10'0000000111 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o[9:0] 10'0000001011 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign { } { } assign $1\spr_o[9:0] 10'0000001100 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign { } { } assign $1\spr_o[9:0] 10'0000001101 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign { } { } assign $1\spr_o[9:0] 10'0000001110 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign { } { } assign $1\spr_o[9:0] 10'0000001111 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\spr_o[9:0] 10'0000010000 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign { } { } assign $1\spr_o[9:0] 10'0000010001 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign { } { } assign $1\spr_o[9:0] 10'0000010010 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign { } { } assign $1\spr_o[9:0] 10'0000010011 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign { } { } assign $1\spr_o[9:0] 10'0000010100 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign { } { } assign $1\spr_o[9:0] 10'0000010101 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign { } { } assign $1\spr_o[9:0] 10'0000010110 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign { } { } assign $1\spr_o[9:0] 10'0000010111 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign { } { } assign $1\spr_o[9:0] 10'0000011000 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign { } { } assign $1\spr_o[9:0] 10'0000011001 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign { } { } assign $1\spr_o[9:0] 10'0000011010 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign { } { } assign $1\spr_o[9:0] 10'0000011011 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign { } { } assign $1\spr_o[9:0] 10'0000011100 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign { } { } assign $1\spr_o[9:0] 10'0000011101 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign { } { } assign $1\spr_o[9:0] 10'0000011110 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign { } { } assign $1\spr_o[9:0] 10'0000011111 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign { } { } assign $1\spr_o[9:0] 10'0000100000 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign { } { } assign $1\spr_o[9:0] 10'0000100001 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o[9:0] 10'0000100011 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign { } { } assign $1\spr_o[9:0] 10'0000100100 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign { } { } assign $1\spr_o[9:0] 10'0000100101 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\spr_o[9:0] 10'0000100110 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign { } { } assign $1\spr_o[9:0] 10'0000100111 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign { } { } assign $1\spr_o[9:0] 10'0000101000 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign { } { } assign $1\spr_o[9:0] 10'0000101001 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign { } { } assign $1\spr_o[9:0] 10'0000101010 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign { } { } assign $1\spr_o[9:0] 10'0000101011 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign { } { } assign $1\spr_o[9:0] 10'0000101100 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign { } { } assign $1\spr_o[9:0] 10'0000101101 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign { } { } assign $1\spr_o[9:0] 10'0000101110 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign { } { } assign $1\spr_o[9:0] 10'0000101111 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign { } { } assign $1\spr_o[9:0] 10'0000110000 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign { } { } assign $1\spr_o[9:0] 10'0000110001 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign { } { } assign $1\spr_o[9:0] 10'0000110010 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign { } { } assign $1\spr_o[9:0] 10'0000110011 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign { } { } assign $1\spr_o[9:0] 10'0000110100 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign { } { } assign $1\spr_o[9:0] 10'0000110101 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign { } { } assign $1\spr_o[9:0] 10'0000110110 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign { } { } assign $1\spr_o[9:0] 10'0000110111 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign { } { } assign $1\spr_o[9:0] 10'0000111000 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign { } { } assign $1\spr_o[9:0] 10'0000111001 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign { } { } assign $1\spr_o[9:0] 10'0000111010 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign { } { } assign $1\spr_o[9:0] 10'0000111011 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign { } { } assign $1\spr_o[9:0] 10'0000111100 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign { } { } assign $1\spr_o[9:0] 10'0000111101 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign { } { } assign $1\spr_o[9:0] 10'0000111110 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign { } { } assign $1\spr_o[9:0] 10'0000111111 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign { } { } assign $1\spr_o[9:0] 10'0001000000 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign { } { } assign $1\spr_o[9:0] 10'0001000001 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign { } { } assign $1\spr_o[9:0] 10'0001000010 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o[9:0] 10'0001000011 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign { } { } assign $1\spr_o[9:0] 10'0001000100 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign { } { } assign $1\spr_o[9:0] 10'0001000101 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign { } { } assign $1\spr_o[9:0] 10'0001000110 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign { } { } assign $1\spr_o[9:0] 10'0001000111 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign { } { } assign $1\spr_o[9:0] 10'0001001000 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign { } { } assign $1\spr_o[9:0] 10'0001001001 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign { } { } assign $1\spr_o[9:0] 10'0001001010 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign { } { } assign $1\spr_o[9:0] 10'0001001011 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign { } { } assign $1\spr_o[9:0] 10'0001001100 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign { } { } assign $1\spr_o[9:0] 10'0001001101 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign { } { } assign $1\spr_o[9:0] 10'0001001110 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign { } { } assign $1\spr_o[9:0] 10'0001001111 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign { } { } assign $1\spr_o[9:0] 10'0001010000 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign { } { } assign $1\spr_o[9:0] 10'0001010001 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign { } { } assign $1\spr_o[9:0] 10'0001010010 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign { } { } assign $1\spr_o[9:0] 10'0001010011 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign { } { } assign $1\spr_o[9:0] 10'0001010100 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign { } { } assign $1\spr_o[9:0] 10'0001010101 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign { } { } assign $1\spr_o[9:0] 10'0001010110 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign { } { } assign $1\spr_o[9:0] 10'0001010111 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign { } { } assign $1\spr_o[9:0] 10'0001011000 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign { } { } assign $1\spr_o[9:0] 10'0001011001 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign { } { } assign $1\spr_o[9:0] 10'0001011010 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign { } { } assign $1\spr_o[9:0] 10'0001011011 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign { } { } assign $1\spr_o[9:0] 10'0001011100 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign { } { } assign $1\spr_o[9:0] 10'0001011101 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign { } { } assign $1\spr_o[9:0] 10'0001011110 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign { } { } assign $1\spr_o[9:0] 10'0001011111 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign { } { } assign $1\spr_o[9:0] 10'0001100000 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign { } { } assign $1\spr_o[9:0] 10'0001100001 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign { } { } assign $1\spr_o[9:0] 10'0001100010 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign { } { } assign $1\spr_o[9:0] 10'0001100011 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign { } { } assign $1\spr_o[9:0] 10'0001100100 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign { } { } assign $1\spr_o[9:0] 10'0001100101 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign { } { } assign $1\spr_o[9:0] 10'0001100110 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign $1\spr_o[9:0] 10'0000000000 attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o[9:0] 10'0001101001 attribute \src "libresoc.v:0.0-0.0" case 10'1100110111 assign { } { } assign $1\spr_o[9:0] 10'0001101010 attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } assign $1\spr_o[9:0] 10'0001101011 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } assign $1\spr_o[9:0] 10'0001101100 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } assign $1\spr_o[9:0] 10'0001101101 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } assign $1\spr_o[9:0] 10'0001101110 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } assign $1\spr_o[9:0] 10'0001101111 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } assign $1\spr_o[9:0] 10'0001110000 case assign $1\spr_o[9:0] 10'0000000000 end sync always update \spr_o $0\spr_o[9:0] end attribute \src "libresoc.v:192553.3-192898.6" process $proc$libresoc.v:192553$12865 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] attribute \src "libresoc.v:192554.5-192554.29" switch \initial attribute \src "libresoc.v:192554.9-192554.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011010 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011011 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0000111101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010001000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010011111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010110100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0010111110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100011111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100110110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0100111111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0101011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0110111110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'0111010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1011000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1011010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1011010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100000111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100001110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100010111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100011110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100100110 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign $1\spr_o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1100110111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } assign $1\spr_o_ok[0:0] 1'1 case assign $1\spr_o_ok[0:0] 1'0 end sync always update \spr_o_ok $0\spr_o_ok[0:0] end end attribute \src "libresoc.v:192903.1-192961.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l attribute \src "libresoc.v:192904.7-192904.20" wire $0\initial[0:0] attribute \src "libresoc.v:192949.3-192957.6" wire width 4 $0\q_int$next[3:0]$12877 attribute \src "libresoc.v:192947.3-192948.27" wire width 4 $0\q_int[3:0] attribute \src "libresoc.v:192949.3-192957.6" wire width 4 $1\q_int$next[3:0]$12878 attribute \src "libresoc.v:192926.13-192926.25" wire width 4 $1\q_int[3:0] attribute \src "libresoc.v:192939.17-192939.96" wire width 4 $and$libresoc.v:192939$12867_Y attribute \src "libresoc.v:192944.17-192944.96" wire width 4 $and$libresoc.v:192944$12872_Y attribute \src "libresoc.v:192941.18-192941.93" wire width 4 $not$libresoc.v:192941$12869_Y attribute \src "libresoc.v:192943.17-192943.92" wire width 4 $not$libresoc.v:192943$12871_Y attribute \src "libresoc.v:192946.17-192946.92" wire width 4 $not$libresoc.v:192946$12874_Y attribute \src "libresoc.v:192940.18-192940.98" wire width 4 $or$libresoc.v:192940$12868_Y attribute \src "libresoc.v:192942.18-192942.99" wire width 4 $or$libresoc.v:192942$12870_Y attribute \src "libresoc.v:192945.17-192945.97" wire width 4 $or$libresoc.v:192945$12873_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:192904.7-192904.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:192939$12867 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:192939$12867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:192944$12872 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:192944$12872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:192941$12869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src connect \Y $not$libresoc.v:192941$12869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:192943$12871 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src connect \Y $not$libresoc.v:192943$12871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:192946$12874 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src connect \Y $not$libresoc.v:192946$12874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:192940$12868 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:192940$12868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:192942$12870 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:192942$12870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:192945$12873 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:192945$12873_Y end attribute \src "libresoc.v:192904.7-192904.20" process $proc$libresoc.v:192904$12879 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:192926.13-192926.25" process $proc$libresoc.v:192926$12880 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end attribute \src "libresoc.v:192947.3-192948.27" process $proc$libresoc.v:192947$12875 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end attribute \src "libresoc.v:192949.3-192957.6" process $proc$libresoc.v:192949$12876 assign { } { } assign { } { } assign $0\q_int$next[3:0]$12877 $1\q_int$next[3:0]$12878 attribute \src "libresoc.v:192950.5-192950.29" switch \initial attribute \src "libresoc.v:192950.9-192950.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[3:0]$12878 4'0000 case assign $1\q_int$next[3:0]$12878 \$5 end sync always update \q_int$next $0\q_int$next[3:0]$12877 end connect \$9 $and$libresoc.v:192939$12867_Y connect \$11 $or$libresoc.v:192940$12868_Y connect \$13 $not$libresoc.v:192941$12869_Y connect \$15 $or$libresoc.v:192942$12870_Y connect \$1 $not$libresoc.v:192943$12871_Y connect \$3 $and$libresoc.v:192944$12872_Y connect \$5 $or$libresoc.v:192945$12873_Y connect \$7 $not$libresoc.v:192946$12874_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:192965.1-193023.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 attribute \src "libresoc.v:192966.7-192966.20" wire $0\initial[0:0] attribute \src "libresoc.v:193011.3-193019.6" wire width 6 $0\q_int$next[5:0]$12891 attribute \src "libresoc.v:193009.3-193010.27" wire width 6 $0\q_int[5:0] attribute \src "libresoc.v:193011.3-193019.6" wire width 6 $1\q_int$next[5:0]$12892 attribute \src "libresoc.v:192988.13-192988.26" wire width 6 $1\q_int[5:0] attribute \src "libresoc.v:193001.17-193001.96" wire width 6 $and$libresoc.v:193001$12881_Y attribute \src "libresoc.v:193006.17-193006.96" wire width 6 $and$libresoc.v:193006$12886_Y attribute \src "libresoc.v:193003.18-193003.93" wire width 6 $not$libresoc.v:193003$12883_Y attribute \src "libresoc.v:193005.17-193005.92" wire width 6 $not$libresoc.v:193005$12885_Y attribute \src "libresoc.v:193008.17-193008.92" wire width 6 $not$libresoc.v:193008$12888_Y attribute \src "libresoc.v:193002.18-193002.98" wire width 6 $or$libresoc.v:193002$12882_Y attribute \src "libresoc.v:193004.18-193004.99" wire width 6 $or$libresoc.v:193004$12884_Y attribute \src "libresoc.v:193007.17-193007.97" wire width 6 $or$libresoc.v:193007$12887_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 6 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 6 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:192966.7-192966.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 6 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193001$12881 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193001$12881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193006$12886 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193006$12886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193003$12883 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src connect \Y $not$libresoc.v:193003$12883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193005$12885 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src connect \Y $not$libresoc.v:193005$12885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193008$12888 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src connect \Y $not$libresoc.v:193008$12888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193002$12882 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193002$12882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193004$12884 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193004$12884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193007$12887 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193007$12887_Y end attribute \src "libresoc.v:192966.7-192966.20" process $proc$libresoc.v:192966$12893 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:192988.13-192988.26" process $proc$libresoc.v:192988$12894 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end attribute \src "libresoc.v:193009.3-193010.27" process $proc$libresoc.v:193009$12889 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end attribute \src "libresoc.v:193011.3-193019.6" process $proc$libresoc.v:193011$12890 assign { } { } assign { } { } assign $0\q_int$next[5:0]$12891 $1\q_int$next[5:0]$12892 attribute \src "libresoc.v:193012.5-193012.29" switch \initial attribute \src "libresoc.v:193012.9-193012.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[5:0]$12892 6'000000 case assign $1\q_int$next[5:0]$12892 \$5 end sync always update \q_int$next $0\q_int$next[5:0]$12891 end connect \$9 $and$libresoc.v:193001$12881_Y connect \$11 $or$libresoc.v:193002$12882_Y connect \$13 $not$libresoc.v:193003$12883_Y connect \$15 $or$libresoc.v:193004$12884_Y connect \$1 $not$libresoc.v:193005$12885_Y connect \$3 $and$libresoc.v:193006$12886_Y connect \$5 $or$libresoc.v:193007$12887_Y connect \$7 $not$libresoc.v:193008$12888_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193027.1-193085.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 attribute \src "libresoc.v:193028.7-193028.20" wire $0\initial[0:0] attribute \src "libresoc.v:193073.3-193081.6" wire width 3 $0\q_int$next[2:0]$12905 attribute \src "libresoc.v:193071.3-193072.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:193073.3-193081.6" wire width 3 $1\q_int$next[2:0]$12906 attribute \src "libresoc.v:193050.13-193050.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:193063.17-193063.96" wire width 3 $and$libresoc.v:193063$12895_Y attribute \src "libresoc.v:193068.17-193068.96" wire width 3 $and$libresoc.v:193068$12900_Y attribute \src "libresoc.v:193065.18-193065.93" wire width 3 $not$libresoc.v:193065$12897_Y attribute \src "libresoc.v:193067.17-193067.92" wire width 3 $not$libresoc.v:193067$12899_Y attribute \src "libresoc.v:193070.17-193070.92" wire width 3 $not$libresoc.v:193070$12902_Y attribute \src "libresoc.v:193064.18-193064.98" wire width 3 $or$libresoc.v:193064$12896_Y attribute \src "libresoc.v:193066.18-193066.99" wire width 3 $or$libresoc.v:193066$12898_Y attribute \src "libresoc.v:193069.17-193069.97" wire width 3 $or$libresoc.v:193069$12901_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193028.7-193028.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193063$12895 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193063$12895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193068$12900 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193068$12900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193065$12897 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \Y $not$libresoc.v:193065$12897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193067$12899 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193067$12899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193070$12902 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193070$12902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193064$12896 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193064$12896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193066$12898 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193066$12898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193069$12901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193069$12901_Y end attribute \src "libresoc.v:193028.7-193028.20" process $proc$libresoc.v:193028$12907 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193050.13-193050.25" process $proc$libresoc.v:193050$12908 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:193071.3-193072.27" process $proc$libresoc.v:193071$12903 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:193073.3-193081.6" process $proc$libresoc.v:193073$12904 assign { } { } assign { } { } assign $0\q_int$next[2:0]$12905 $1\q_int$next[2:0]$12906 attribute \src "libresoc.v:193074.5-193074.29" switch \initial attribute \src "libresoc.v:193074.9-193074.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$12906 3'000 case assign $1\q_int$next[2:0]$12906 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$12905 end connect \$9 $and$libresoc.v:193063$12895_Y connect \$11 $or$libresoc.v:193064$12896_Y connect \$13 $not$libresoc.v:193065$12897_Y connect \$15 $or$libresoc.v:193066$12898_Y connect \$1 $not$libresoc.v:193067$12899_Y connect \$3 $and$libresoc.v:193068$12900_Y connect \$5 $or$libresoc.v:193069$12901_Y connect \$7 $not$libresoc.v:193070$12902_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193089.1-193147.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 attribute \src "libresoc.v:193090.7-193090.20" wire $0\initial[0:0] attribute \src "libresoc.v:193135.3-193143.6" wire width 5 $0\q_int$next[4:0]$12919 attribute \src "libresoc.v:193133.3-193134.27" wire width 5 $0\q_int[4:0] attribute \src "libresoc.v:193135.3-193143.6" wire width 5 $1\q_int$next[4:0]$12920 attribute \src "libresoc.v:193112.13-193112.26" wire width 5 $1\q_int[4:0] attribute \src "libresoc.v:193125.17-193125.96" wire width 5 $and$libresoc.v:193125$12909_Y attribute \src "libresoc.v:193130.17-193130.96" wire width 5 $and$libresoc.v:193130$12914_Y attribute \src "libresoc.v:193127.18-193127.93" wire width 5 $not$libresoc.v:193127$12911_Y attribute \src "libresoc.v:193129.17-193129.92" wire width 5 $not$libresoc.v:193129$12913_Y attribute \src "libresoc.v:193132.17-193132.92" wire width 5 $not$libresoc.v:193132$12916_Y attribute \src "libresoc.v:193126.18-193126.98" wire width 5 $or$libresoc.v:193126$12910_Y attribute \src "libresoc.v:193128.18-193128.99" wire width 5 $or$libresoc.v:193128$12912_Y attribute \src "libresoc.v:193131.17-193131.97" wire width 5 $or$libresoc.v:193131$12915_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 5 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 5 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193090.7-193090.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 5 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193125$12909 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193125$12909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193130$12914 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193130$12914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193127$12911 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src connect \Y $not$libresoc.v:193127$12911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193129$12913 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src connect \Y $not$libresoc.v:193129$12913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193132$12916 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src connect \Y $not$libresoc.v:193132$12916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193126$12910 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193126$12910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193128$12912 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193128$12912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193131$12915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193131$12915_Y end attribute \src "libresoc.v:193090.7-193090.20" process $proc$libresoc.v:193090$12921 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193112.13-193112.26" process $proc$libresoc.v:193112$12922 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end attribute \src "libresoc.v:193133.3-193134.27" process $proc$libresoc.v:193133$12917 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end attribute \src "libresoc.v:193135.3-193143.6" process $proc$libresoc.v:193135$12918 assign { } { } assign { } { } assign $0\q_int$next[4:0]$12919 $1\q_int$next[4:0]$12920 attribute \src "libresoc.v:193136.5-193136.29" switch \initial attribute \src "libresoc.v:193136.9-193136.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[4:0]$12920 5'00000 case assign $1\q_int$next[4:0]$12920 \$5 end sync always update \q_int$next $0\q_int$next[4:0]$12919 end connect \$9 $and$libresoc.v:193125$12909_Y connect \$11 $or$libresoc.v:193126$12910_Y connect \$13 $not$libresoc.v:193127$12911_Y connect \$15 $or$libresoc.v:193128$12912_Y connect \$1 $not$libresoc.v:193129$12913_Y connect \$3 $and$libresoc.v:193130$12914_Y connect \$5 $or$libresoc.v:193131$12915_Y connect \$7 $not$libresoc.v:193132$12916_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193151.1-193209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 attribute \src "libresoc.v:193152.7-193152.20" wire $0\initial[0:0] attribute \src "libresoc.v:193197.3-193205.6" wire width 3 $0\q_int$next[2:0]$12933 attribute \src "libresoc.v:193195.3-193196.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:193197.3-193205.6" wire width 3 $1\q_int$next[2:0]$12934 attribute \src "libresoc.v:193174.13-193174.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:193187.17-193187.96" wire width 3 $and$libresoc.v:193187$12923_Y attribute \src "libresoc.v:193192.17-193192.96" wire width 3 $and$libresoc.v:193192$12928_Y attribute \src "libresoc.v:193189.18-193189.93" wire width 3 $not$libresoc.v:193189$12925_Y attribute \src "libresoc.v:193191.17-193191.92" wire width 3 $not$libresoc.v:193191$12927_Y attribute \src "libresoc.v:193194.17-193194.92" wire width 3 $not$libresoc.v:193194$12930_Y attribute \src "libresoc.v:193188.18-193188.98" wire width 3 $or$libresoc.v:193188$12924_Y attribute \src "libresoc.v:193190.18-193190.99" wire width 3 $or$libresoc.v:193190$12926_Y attribute \src "libresoc.v:193193.17-193193.97" wire width 3 $or$libresoc.v:193193$12929_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193152.7-193152.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193187$12923 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193187$12923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193192$12928 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193192$12928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193189$12925 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \Y $not$libresoc.v:193189$12925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193191$12927 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193191$12927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193194$12930 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193194$12930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193188$12924 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193188$12924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193190$12926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193190$12926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193193$12929 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193193$12929_Y end attribute \src "libresoc.v:193152.7-193152.20" process $proc$libresoc.v:193152$12935 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193174.13-193174.25" process $proc$libresoc.v:193174$12936 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:193195.3-193196.27" process $proc$libresoc.v:193195$12931 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:193197.3-193205.6" process $proc$libresoc.v:193197$12932 assign { } { } assign { } { } assign $0\q_int$next[2:0]$12933 $1\q_int$next[2:0]$12934 attribute \src "libresoc.v:193198.5-193198.29" switch \initial attribute \src "libresoc.v:193198.9-193198.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$12934 3'000 case assign $1\q_int$next[2:0]$12934 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$12933 end connect \$9 $and$libresoc.v:193187$12923_Y connect \$11 $or$libresoc.v:193188$12924_Y connect \$13 $not$libresoc.v:193189$12925_Y connect \$15 $or$libresoc.v:193190$12926_Y connect \$1 $not$libresoc.v:193191$12927_Y connect \$3 $and$libresoc.v:193192$12928_Y connect \$5 $or$libresoc.v:193193$12929_Y connect \$7 $not$libresoc.v:193194$12930_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193213.1-193271.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 attribute \src "libresoc.v:193214.7-193214.20" wire $0\initial[0:0] attribute \src "libresoc.v:193259.3-193267.6" wire width 3 $0\q_int$next[2:0]$12947 attribute \src "libresoc.v:193257.3-193258.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:193259.3-193267.6" wire width 3 $1\q_int$next[2:0]$12948 attribute \src "libresoc.v:193236.13-193236.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:193249.17-193249.96" wire width 3 $and$libresoc.v:193249$12937_Y attribute \src "libresoc.v:193254.17-193254.96" wire width 3 $and$libresoc.v:193254$12942_Y attribute \src "libresoc.v:193251.18-193251.93" wire width 3 $not$libresoc.v:193251$12939_Y attribute \src "libresoc.v:193253.17-193253.92" wire width 3 $not$libresoc.v:193253$12941_Y attribute \src "libresoc.v:193256.17-193256.92" wire width 3 $not$libresoc.v:193256$12944_Y attribute \src "libresoc.v:193250.18-193250.98" wire width 3 $or$libresoc.v:193250$12938_Y attribute \src "libresoc.v:193252.18-193252.99" wire width 3 $or$libresoc.v:193252$12940_Y attribute \src "libresoc.v:193255.17-193255.97" wire width 3 $or$libresoc.v:193255$12943_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193214.7-193214.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193249$12937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193249$12937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193254$12942 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193254$12942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193251$12939 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \Y $not$libresoc.v:193251$12939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193253$12941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193253$12941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193256$12944 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193256$12944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193250$12938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193250$12938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193252$12940 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193252$12940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193255$12943 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193255$12943_Y end attribute \src "libresoc.v:193214.7-193214.20" process $proc$libresoc.v:193214$12949 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193236.13-193236.25" process $proc$libresoc.v:193236$12950 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:193257.3-193258.27" process $proc$libresoc.v:193257$12945 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:193259.3-193267.6" process $proc$libresoc.v:193259$12946 assign { } { } assign { } { } assign $0\q_int$next[2:0]$12947 $1\q_int$next[2:0]$12948 attribute \src "libresoc.v:193260.5-193260.29" switch \initial attribute \src "libresoc.v:193260.9-193260.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$12948 3'000 case assign $1\q_int$next[2:0]$12948 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$12947 end connect \$9 $and$libresoc.v:193249$12937_Y connect \$11 $or$libresoc.v:193250$12938_Y connect \$13 $not$libresoc.v:193251$12939_Y connect \$15 $or$libresoc.v:193252$12940_Y connect \$1 $not$libresoc.v:193253$12941_Y connect \$3 $and$libresoc.v:193254$12942_Y connect \$5 $or$libresoc.v:193255$12943_Y connect \$7 $not$libresoc.v:193256$12944_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193275.1-193333.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 attribute \src "libresoc.v:193276.7-193276.20" wire $0\initial[0:0] attribute \src "libresoc.v:193321.3-193329.6" wire width 4 $0\q_int$next[3:0]$12961 attribute \src "libresoc.v:193319.3-193320.27" wire width 4 $0\q_int[3:0] attribute \src "libresoc.v:193321.3-193329.6" wire width 4 $1\q_int$next[3:0]$12962 attribute \src "libresoc.v:193298.13-193298.25" wire width 4 $1\q_int[3:0] attribute \src "libresoc.v:193311.17-193311.96" wire width 4 $and$libresoc.v:193311$12951_Y attribute \src "libresoc.v:193316.17-193316.96" wire width 4 $and$libresoc.v:193316$12956_Y attribute \src "libresoc.v:193313.18-193313.93" wire width 4 $not$libresoc.v:193313$12953_Y attribute \src "libresoc.v:193315.17-193315.92" wire width 4 $not$libresoc.v:193315$12955_Y attribute \src "libresoc.v:193318.17-193318.92" wire width 4 $not$libresoc.v:193318$12958_Y attribute \src "libresoc.v:193312.18-193312.98" wire width 4 $or$libresoc.v:193312$12952_Y attribute \src "libresoc.v:193314.18-193314.99" wire width 4 $or$libresoc.v:193314$12954_Y attribute \src "libresoc.v:193317.17-193317.97" wire width 4 $or$libresoc.v:193317$12957_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 4 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 4 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193276.7-193276.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 4 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193311$12951 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193311$12951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193316$12956 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193316$12956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193313$12953 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src connect \Y $not$libresoc.v:193313$12953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193315$12955 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src connect \Y $not$libresoc.v:193315$12955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193318$12958 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src connect \Y $not$libresoc.v:193318$12958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193312$12952 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193312$12952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193314$12954 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193314$12954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193317$12957 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193317$12957_Y end attribute \src "libresoc.v:193276.7-193276.20" process $proc$libresoc.v:193276$12963 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193298.13-193298.25" process $proc$libresoc.v:193298$12964 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end attribute \src "libresoc.v:193319.3-193320.27" process $proc$libresoc.v:193319$12959 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end attribute \src "libresoc.v:193321.3-193329.6" process $proc$libresoc.v:193321$12960 assign { } { } assign { } { } assign $0\q_int$next[3:0]$12961 $1\q_int$next[3:0]$12962 attribute \src "libresoc.v:193322.5-193322.29" switch \initial attribute \src "libresoc.v:193322.9-193322.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[3:0]$12962 4'0000 case assign $1\q_int$next[3:0]$12962 \$5 end sync always update \q_int$next $0\q_int$next[3:0]$12961 end connect \$9 $and$libresoc.v:193311$12951_Y connect \$11 $or$libresoc.v:193312$12952_Y connect \$13 $not$libresoc.v:193313$12953_Y connect \$15 $or$libresoc.v:193314$12954_Y connect \$1 $not$libresoc.v:193315$12955_Y connect \$3 $and$libresoc.v:193316$12956_Y connect \$5 $or$libresoc.v:193317$12957_Y connect \$7 $not$libresoc.v:193318$12958_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193337.1-193395.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 attribute \src "libresoc.v:193338.7-193338.20" wire $0\initial[0:0] attribute \src "libresoc.v:193383.3-193391.6" wire width 3 $0\q_int$next[2:0]$12975 attribute \src "libresoc.v:193381.3-193382.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:193383.3-193391.6" wire width 3 $1\q_int$next[2:0]$12976 attribute \src "libresoc.v:193360.13-193360.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:193373.17-193373.96" wire width 3 $and$libresoc.v:193373$12965_Y attribute \src "libresoc.v:193378.17-193378.96" wire width 3 $and$libresoc.v:193378$12970_Y attribute \src "libresoc.v:193375.18-193375.93" wire width 3 $not$libresoc.v:193375$12967_Y attribute \src "libresoc.v:193377.17-193377.92" wire width 3 $not$libresoc.v:193377$12969_Y attribute \src "libresoc.v:193380.17-193380.92" wire width 3 $not$libresoc.v:193380$12972_Y attribute \src "libresoc.v:193374.18-193374.98" wire width 3 $or$libresoc.v:193374$12966_Y attribute \src "libresoc.v:193376.18-193376.99" wire width 3 $or$libresoc.v:193376$12968_Y attribute \src "libresoc.v:193379.17-193379.97" wire width 3 $or$libresoc.v:193379$12971_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193338.7-193338.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193373$12965 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193373$12965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193378$12970 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193378$12970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193375$12967 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \Y $not$libresoc.v:193375$12967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193377$12969 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193377$12969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193380$12972 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193380$12972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193374$12966 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193374$12966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193376$12968 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193376$12968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193379$12971 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193379$12971_Y end attribute \src "libresoc.v:193338.7-193338.20" process $proc$libresoc.v:193338$12977 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193360.13-193360.25" process $proc$libresoc.v:193360$12978 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:193381.3-193382.27" process $proc$libresoc.v:193381$12973 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:193383.3-193391.6" process $proc$libresoc.v:193383$12974 assign { } { } assign { } { } assign $0\q_int$next[2:0]$12975 $1\q_int$next[2:0]$12976 attribute \src "libresoc.v:193384.5-193384.29" switch \initial attribute \src "libresoc.v:193384.9-193384.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$12976 3'000 case assign $1\q_int$next[2:0]$12976 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$12975 end connect \$9 $and$libresoc.v:193373$12965_Y connect \$11 $or$libresoc.v:193374$12966_Y connect \$13 $not$libresoc.v:193375$12967_Y connect \$15 $or$libresoc.v:193376$12968_Y connect \$1 $not$libresoc.v:193377$12969_Y connect \$3 $and$libresoc.v:193378$12970_Y connect \$5 $or$libresoc.v:193379$12971_Y connect \$7 $not$libresoc.v:193380$12972_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193399.1-193457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 attribute \src "libresoc.v:193400.7-193400.20" wire $0\initial[0:0] attribute \src "libresoc.v:193445.3-193453.6" wire width 6 $0\q_int$next[5:0]$12989 attribute \src "libresoc.v:193443.3-193444.27" wire width 6 $0\q_int[5:0] attribute \src "libresoc.v:193445.3-193453.6" wire width 6 $1\q_int$next[5:0]$12990 attribute \src "libresoc.v:193422.13-193422.26" wire width 6 $1\q_int[5:0] attribute \src "libresoc.v:193435.17-193435.96" wire width 6 $and$libresoc.v:193435$12979_Y attribute \src "libresoc.v:193440.17-193440.96" wire width 6 $and$libresoc.v:193440$12984_Y attribute \src "libresoc.v:193437.18-193437.93" wire width 6 $not$libresoc.v:193437$12981_Y attribute \src "libresoc.v:193439.17-193439.92" wire width 6 $not$libresoc.v:193439$12983_Y attribute \src "libresoc.v:193442.17-193442.92" wire width 6 $not$libresoc.v:193442$12986_Y attribute \src "libresoc.v:193436.18-193436.98" wire width 6 $or$libresoc.v:193436$12980_Y attribute \src "libresoc.v:193438.18-193438.99" wire width 6 $or$libresoc.v:193438$12982_Y attribute \src "libresoc.v:193441.17-193441.97" wire width 6 $or$libresoc.v:193441$12985_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 6 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 6 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193400.7-193400.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 6 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 6 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193435$12979 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193435$12979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193440$12984 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193440$12984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193437$12981 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src connect \Y $not$libresoc.v:193437$12981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193439$12983 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src connect \Y $not$libresoc.v:193439$12983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193442$12986 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src connect \Y $not$libresoc.v:193442$12986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193436$12980 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193436$12980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193438$12982 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193438$12982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193441$12985 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193441$12985_Y end attribute \src "libresoc.v:193400.7-193400.20" process $proc$libresoc.v:193400$12991 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193422.13-193422.26" process $proc$libresoc.v:193422$12992 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end attribute \src "libresoc.v:193443.3-193444.27" process $proc$libresoc.v:193443$12987 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end attribute \src "libresoc.v:193445.3-193453.6" process $proc$libresoc.v:193445$12988 assign { } { } assign { } { } assign $0\q_int$next[5:0]$12989 $1\q_int$next[5:0]$12990 attribute \src "libresoc.v:193446.5-193446.29" switch \initial attribute \src "libresoc.v:193446.9-193446.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[5:0]$12990 6'000000 case assign $1\q_int$next[5:0]$12990 \$5 end sync always update \q_int$next $0\q_int$next[5:0]$12989 end connect \$9 $and$libresoc.v:193435$12979_Y connect \$11 $or$libresoc.v:193436$12980_Y connect \$13 $not$libresoc.v:193437$12981_Y connect \$15 $or$libresoc.v:193438$12982_Y connect \$1 $not$libresoc.v:193439$12983_Y connect \$3 $and$libresoc.v:193440$12984_Y connect \$5 $or$libresoc.v:193441$12985_Y connect \$7 $not$libresoc.v:193442$12986_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193461.1-193519.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 attribute \src "libresoc.v:193462.7-193462.20" wire $0\initial[0:0] attribute \src "libresoc.v:193507.3-193515.6" wire width 3 $0\q_int$next[2:0]$13003 attribute \src "libresoc.v:193505.3-193506.27" wire width 3 $0\q_int[2:0] attribute \src "libresoc.v:193507.3-193515.6" wire width 3 $1\q_int$next[2:0]$13004 attribute \src "libresoc.v:193484.13-193484.25" wire width 3 $1\q_int[2:0] attribute \src "libresoc.v:193497.17-193497.96" wire width 3 $and$libresoc.v:193497$12993_Y attribute \src "libresoc.v:193502.17-193502.96" wire width 3 $and$libresoc.v:193502$12998_Y attribute \src "libresoc.v:193499.18-193499.93" wire width 3 $not$libresoc.v:193499$12995_Y attribute \src "libresoc.v:193501.17-193501.92" wire width 3 $not$libresoc.v:193501$12997_Y attribute \src "libresoc.v:193504.17-193504.92" wire width 3 $not$libresoc.v:193504$13000_Y attribute \src "libresoc.v:193498.18-193498.98" wire width 3 $or$libresoc.v:193498$12994_Y attribute \src "libresoc.v:193500.18-193500.99" wire width 3 $or$libresoc.v:193500$12996_Y attribute \src "libresoc.v:193503.17-193503.97" wire width 3 $or$libresoc.v:193503$12999_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire width 3 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire width 3 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193462.7-193462.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire width 3 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193497$12993 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193497$12993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193502$12998 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193502$12998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193499$12995 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \Y $not$libresoc.v:193499$12995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193501$12997 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193501$12997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193504$13000 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src connect \Y $not$libresoc.v:193504$13000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193498$12994 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src connect \Y $or$libresoc.v:193498$12994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193500$12996 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int connect \Y $or$libresoc.v:193500$12996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193503$12999 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src connect \Y $or$libresoc.v:193503$12999_Y end attribute \src "libresoc.v:193462.7-193462.20" process $proc$libresoc.v:193462$13005 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193484.13-193484.25" process $proc$libresoc.v:193484$13006 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end attribute \src "libresoc.v:193505.3-193506.27" process $proc$libresoc.v:193505$13001 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end attribute \src "libresoc.v:193507.3-193515.6" process $proc$libresoc.v:193507$13002 assign { } { } assign { } { } assign $0\q_int$next[2:0]$13003 $1\q_int$next[2:0]$13004 attribute \src "libresoc.v:193508.5-193508.29" switch \initial attribute \src "libresoc.v:193508.9-193508.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[2:0]$13004 3'000 case assign $1\q_int$next[2:0]$13004 \$5 end sync always update \q_int$next $0\q_int$next[2:0]$13003 end connect \$9 $and$libresoc.v:193497$12993_Y connect \$11 $or$libresoc.v:193498$12994_Y connect \$13 $not$libresoc.v:193499$12995_Y connect \$15 $or$libresoc.v:193500$12996_Y connect \$1 $not$libresoc.v:193501$12997_Y connect \$3 $and$libresoc.v:193502$12998_Y connect \$5 $or$libresoc.v:193503$12999_Y connect \$7 $not$libresoc.v:193504$13000_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end attribute \src "libresoc.v:193523.1-193581.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active attribute \src "libresoc.v:193524.7-193524.20" wire $0\initial[0:0] attribute \src "libresoc.v:193569.3-193577.6" wire $0\q_int$next[0:0]$13017 attribute \src "libresoc.v:193567.3-193568.27" wire $0\q_int[0:0] attribute \src "libresoc.v:193569.3-193577.6" wire $1\q_int$next[0:0]$13018 attribute \src "libresoc.v:193546.7-193546.19" wire $1\q_int[0:0] attribute \src "libresoc.v:193559.17-193559.96" wire $and$libresoc.v:193559$13007_Y attribute \src "libresoc.v:193564.17-193564.96" wire $and$libresoc.v:193564$13012_Y attribute \src "libresoc.v:193561.18-193561.99" wire $not$libresoc.v:193561$13009_Y attribute \src "libresoc.v:193563.17-193563.98" wire $not$libresoc.v:193563$13011_Y attribute \src "libresoc.v:193566.17-193566.98" wire $not$libresoc.v:193566$13014_Y attribute \src "libresoc.v:193560.18-193560.104" wire $or$libresoc.v:193560$13008_Y attribute \src "libresoc.v:193562.18-193562.105" wire $or$libresoc.v:193562$13010_Y attribute \src "libresoc.v:193565.17-193565.103" wire $or$libresoc.v:193565$13013_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193524.7-193524.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 2 \r_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193559$13007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193559$13007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193564$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193564$13012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193561$13009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active connect \Y $not$libresoc.v:193561$13009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193563$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active connect \Y $not$libresoc.v:193563$13011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193566$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active connect \Y $not$libresoc.v:193566$13014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193560$13008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active connect \Y $or$libresoc.v:193560$13008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193562$13010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int connect \Y $or$libresoc.v:193562$13010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193565$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active connect \Y $or$libresoc.v:193565$13013_Y end attribute \src "libresoc.v:193524.7-193524.20" process $proc$libresoc.v:193524$13019 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193546.7-193546.19" process $proc$libresoc.v:193546$13020 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:193567.3-193568.27" process $proc$libresoc.v:193567$13015 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:193569.3-193577.6" process $proc$libresoc.v:193569$13016 assign { } { } assign { } { } assign $0\q_int$next[0:0]$13017 $1\q_int$next[0:0]$13018 attribute \src "libresoc.v:193570.5-193570.29" switch \initial attribute \src "libresoc.v:193570.9-193570.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$13018 1'0 case assign $1\q_int$next[0:0]$13018 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$13017 end connect \$9 $and$libresoc.v:193559$13007_Y connect \$11 $or$libresoc.v:193560$13008_Y connect \$13 $not$libresoc.v:193561$13009_Y connect \$15 $or$libresoc.v:193562$13010_Y connect \$1 $not$libresoc.v:193563$13011_Y connect \$3 $and$libresoc.v:193564$13012_Y connect \$5 $or$libresoc.v:193565$13013_Y connect \$7 $not$libresoc.v:193566$13014_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end attribute \src "libresoc.v:193585.1-193643.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done attribute \src "libresoc.v:193586.7-193586.20" wire $0\initial[0:0] attribute \src "libresoc.v:193631.3-193639.6" wire $0\q_int$next[0:0]$13031 attribute \src "libresoc.v:193629.3-193630.27" wire $0\q_int[0:0] attribute \src "libresoc.v:193631.3-193639.6" wire $1\q_int$next[0:0]$13032 attribute \src "libresoc.v:193608.7-193608.19" wire $1\q_int[0:0] attribute \src "libresoc.v:193621.17-193621.96" wire $and$libresoc.v:193621$13021_Y attribute \src "libresoc.v:193626.17-193626.96" wire $and$libresoc.v:193626$13026_Y attribute \src "libresoc.v:193623.18-193623.97" wire $not$libresoc.v:193623$13023_Y attribute \src "libresoc.v:193625.17-193625.96" wire $not$libresoc.v:193625$13025_Y attribute \src "libresoc.v:193628.17-193628.96" wire $not$libresoc.v:193628$13028_Y attribute \src "libresoc.v:193622.18-193622.102" wire $or$libresoc.v:193622$13022_Y attribute \src "libresoc.v:193624.18-193624.103" wire $or$libresoc.v:193624$13024_Y attribute \src "libresoc.v:193627.17-193627.101" wire $or$libresoc.v:193627$13027_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193586.7-193586.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193621$13021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193621$13021_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193626$13026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193626$13026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193623$13023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done connect \Y $not$libresoc.v:193623$13023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193625$13025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done connect \Y $not$libresoc.v:193625$13025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193628$13028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done connect \Y $not$libresoc.v:193628$13028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193622$13022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done connect \Y $or$libresoc.v:193622$13022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193624$13024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int connect \Y $or$libresoc.v:193624$13024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193627$13027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done connect \Y $or$libresoc.v:193627$13027_Y end attribute \src "libresoc.v:193586.7-193586.20" process $proc$libresoc.v:193586$13033 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193608.7-193608.19" process $proc$libresoc.v:193608$13034 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:193629.3-193630.27" process $proc$libresoc.v:193629$13029 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:193631.3-193639.6" process $proc$libresoc.v:193631$13030 assign { } { } assign { } { } assign $0\q_int$next[0:0]$13031 $1\q_int$next[0:0]$13032 attribute \src "libresoc.v:193632.5-193632.29" switch \initial attribute \src "libresoc.v:193632.9-193632.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$13032 1'0 case assign $1\q_int$next[0:0]$13032 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$13031 end connect \$9 $and$libresoc.v:193621$13021_Y connect \$11 $or$libresoc.v:193622$13022_Y connect \$13 $not$libresoc.v:193623$13023_Y connect \$15 $or$libresoc.v:193624$13024_Y connect \$1 $not$libresoc.v:193625$13025_Y connect \$3 $and$libresoc.v:193626$13026_Y connect \$5 $or$libresoc.v:193627$13027_Y connect \$7 $not$libresoc.v:193628$13028_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end attribute \src "libresoc.v:193647.1-193943.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state attribute \src "libresoc.v:193895.3-193904.6" wire width 64 $0\cia__data_o[63:0] attribute \src "libresoc.v:193648.7-193648.20" wire $0\initial[0:0] attribute \src "libresoc.v:193914.3-193923.6" wire width 64 $0\msr__data_o[63:0] attribute \src "libresoc.v:193905.3-193913.6" wire width 3 $0\ren_delay$12$next[2:0]$13058 attribute \src "libresoc.v:193809.3-193810.43" wire width 3 $0\ren_delay$12[2:0]$13047 attribute \src "libresoc.v:193776.13-193776.34" wire width 3 $0\ren_delay$12[2:0]$13064 attribute \src "libresoc.v:193867.3-193875.6" wire width 3 $0\ren_delay$19$next[2:0]$13050 attribute \src "libresoc.v:193807.3-193808.43" wire width 3 $0\ren_delay$19[2:0]$13045 attribute \src "libresoc.v:193780.13-193780.34" wire width 3 $0\ren_delay$19[2:0]$13066 attribute \src "libresoc.v:193886.3-193894.6" wire width 3 $0\ren_delay$next[2:0]$13054 attribute \src "libresoc.v:193811.3-193812.35" wire width 3 $0\ren_delay[2:0] attribute \src "libresoc.v:193876.3-193885.6" wire width 64 $0\sv__data_o[63:0] attribute \src "libresoc.v:193895.3-193904.6" wire width 64 $1\cia__data_o[63:0] attribute \src "libresoc.v:193914.3-193923.6" wire width 64 $1\msr__data_o[63:0] attribute \src "libresoc.v:193905.3-193913.6" wire width 3 $1\ren_delay$12$next[2:0]$13059 attribute \src "libresoc.v:193867.3-193875.6" wire width 3 $1\ren_delay$19$next[2:0]$13051 attribute \src "libresoc.v:193886.3-193894.6" wire width 3 $1\ren_delay$next[2:0]$13055 attribute \src "libresoc.v:193774.13-193774.29" wire width 3 $1\ren_delay[2:0] attribute \src "libresoc.v:193876.3-193885.6" wire width 64 $1\sv__data_o[63:0] attribute \src "libresoc.v:193798.18-193798.109" wire width 64 $or$libresoc.v:193798$13035_Y attribute \src "libresoc.v:193800.18-193800.124" wire width 64 $or$libresoc.v:193800$13037_Y attribute \src "libresoc.v:193801.18-193801.110" wire width 64 $or$libresoc.v:193801$13038_Y attribute \src "libresoc.v:193803.18-193803.122" wire width 64 $or$libresoc.v:193803$13040_Y attribute \src "libresoc.v:193804.18-193804.109" wire width 64 $or$libresoc.v:193804$13041_Y attribute \src "libresoc.v:193806.17-193806.123" wire width 64 $or$libresoc.v:193806$13043_Y attribute \src "libresoc.v:193799.18-193799.100" wire $reduce_or$libresoc.v:193799$13036_Y attribute \src "libresoc.v:193802.18-193802.100" wire $reduce_or$libresoc.v:193802$13039_Y attribute \src "libresoc.v:193805.17-193805.95" wire $reduce_or$libresoc.v:193805$13042_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$17 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 64 \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \data_i$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 attribute \src "libresoc.v:193648.7-193648.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 8 \msr__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_cia0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_cia0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_d_wr10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_msr0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_msr0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_msr0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_msr0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_nia0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_nia0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_sv0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_sv0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_sv0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_sv0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_cia1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_cia1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_d_wr11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_msr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_msr1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_msr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_msr1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_nia1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_nia1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_sv1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_1_sv1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_sv1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_sv1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_cia2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_cia2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_d_wr12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_msr2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_msr2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_msr2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_msr2__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_nia2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_nia2__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_sv2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_2_sv2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_sv2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_sv2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 12 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 5 \sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 4 \sv__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 6 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 10 \wen$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:193798$13035 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 connect \Y $or$libresoc.v:193798$13035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:193800$13037 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o connect \Y $or$libresoc.v:193800$13037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:193801$13038 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 connect \Y $or$libresoc.v:193801$13038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:193803$13040 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o connect \Y $or$libresoc.v:193803$13040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:193804$13041 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 connect \Y $or$libresoc.v:193804$13041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:193806$13043 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o connect \Y $or$libresoc.v:193806$13043_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:193799$13036 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 connect \Y $reduce_or$libresoc.v:193799$13036_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:193802$13039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 connect \Y $reduce_or$libresoc.v:193802$13039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:193805$13042 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay connect \Y $reduce_or$libresoc.v:193805$13042_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:193813.15-193830.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \d_wr10__data_i \reg_0_d_wr10__data_i connect \d_wr10__wen \reg_0_d_wr10__wen connect \msr0__data_i \reg_0_msr0__data_i connect \msr0__data_o \reg_0_msr0__data_o connect \msr0__ren \reg_0_msr0__ren connect \msr0__wen \reg_0_msr0__wen connect \nia0__data_i \reg_0_nia0__data_i connect \nia0__wen \reg_0_nia0__wen connect \sv0__data_i \reg_0_sv0__data_i connect \sv0__data_o \reg_0_sv0__data_o connect \sv0__ren \reg_0_sv0__ren connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:193831.15-193848.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \d_wr11__data_i \reg_1_d_wr11__data_i connect \d_wr11__wen \reg_1_d_wr11__wen connect \msr1__data_i \reg_1_msr1__data_i connect \msr1__data_o \reg_1_msr1__data_o connect \msr1__ren \reg_1_msr1__ren connect \msr1__wen \reg_1_msr1__wen connect \nia1__data_i \reg_1_nia1__data_i connect \nia1__wen \reg_1_nia1__wen connect \sv1__data_i \reg_1_sv1__data_i connect \sv1__data_o \reg_1_sv1__data_o connect \sv1__ren \reg_1_sv1__ren connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:193849.15-193866.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \d_wr12__data_i \reg_2_d_wr12__data_i connect \d_wr12__wen \reg_2_d_wr12__wen connect \msr2__data_i \reg_2_msr2__data_i connect \msr2__data_o \reg_2_msr2__data_o connect \msr2__ren \reg_2_msr2__ren connect \msr2__wen \reg_2_msr2__wen connect \nia2__data_i \reg_2_nia2__data_i connect \nia2__wen \reg_2_nia2__wen connect \sv2__data_i \reg_2_sv2__data_i connect \sv2__data_o \reg_2_sv2__data_o connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end attribute \src "libresoc.v:193648.7-193648.20" process $proc$libresoc.v:193648$13061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193774.13-193774.29" process $proc$libresoc.v:193774$13062 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end attribute \src "libresoc.v:193776.13-193776.34" process $proc$libresoc.v:193776$13063 assign { } { } assign $0\ren_delay$12[2:0]$13064 3'000 sync always sync init update \ren_delay$12 $0\ren_delay$12[2:0]$13064 end attribute \src "libresoc.v:193780.13-193780.34" process $proc$libresoc.v:193780$13065 assign { } { } assign $0\ren_delay$19[2:0]$13066 3'000 sync always sync init update \ren_delay$19 $0\ren_delay$19[2:0]$13066 end attribute \src "libresoc.v:193807.3-193808.43" process $proc$libresoc.v:193807$13044 assign { } { } assign $0\ren_delay$19[2:0]$13045 \ren_delay$19$next sync posedge \coresync_clk update \ren_delay$19 $0\ren_delay$19[2:0]$13045 end attribute \src "libresoc.v:193809.3-193810.43" process $proc$libresoc.v:193809$13046 assign { } { } assign $0\ren_delay$12[2:0]$13047 \ren_delay$12$next sync posedge \coresync_clk update \ren_delay$12 $0\ren_delay$12[2:0]$13047 end attribute \src "libresoc.v:193811.3-193812.35" process $proc$libresoc.v:193811$13048 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end attribute \src "libresoc.v:193867.3-193875.6" process $proc$libresoc.v:193867$13049 assign { } { } assign { } { } assign $0\ren_delay$19$next[2:0]$13050 $1\ren_delay$19$next[2:0]$13051 attribute \src "libresoc.v:193868.5-193868.29" switch \initial attribute \src "libresoc.v:193868.9-193868.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$19$next[2:0]$13051 3'000 case assign $1\ren_delay$19$next[2:0]$13051 \sv__ren end sync always update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13050 end attribute \src "libresoc.v:193876.3-193885.6" process $proc$libresoc.v:193876$13052 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] attribute \src "libresoc.v:193877.5-193877.29" switch \initial attribute \src "libresoc.v:193877.9-193877.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$20 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\sv__data_o[63:0] \$24 case assign $1\sv__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \sv__data_o $0\sv__data_o[63:0] end attribute \src "libresoc.v:193886.3-193894.6" process $proc$libresoc.v:193886$13053 assign { } { } assign { } { } assign $0\ren_delay$next[2:0]$13054 $1\ren_delay$next[2:0]$13055 attribute \src "libresoc.v:193887.5-193887.29" switch \initial attribute \src "libresoc.v:193887.9-193887.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$next[2:0]$13055 3'000 case assign $1\ren_delay$next[2:0]$13055 \cia__ren end sync always update \ren_delay$next $0\ren_delay$next[2:0]$13054 end attribute \src "libresoc.v:193895.3-193904.6" process $proc$libresoc.v:193895$13056 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] attribute \src "libresoc.v:193896.5-193896.29" switch \initial attribute \src "libresoc.v:193896.9-193896.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cia__data_o[63:0] \$10 case assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \cia__data_o $0\cia__data_o[63:0] end attribute \src "libresoc.v:193905.3-193913.6" process $proc$libresoc.v:193905$13057 assign { } { } assign { } { } assign $0\ren_delay$12$next[2:0]$13058 $1\ren_delay$12$next[2:0]$13059 attribute \src "libresoc.v:193906.5-193906.29" switch \initial attribute \src "libresoc.v:193906.9-193906.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$12$next[2:0]$13059 3'000 case assign $1\ren_delay$12$next[2:0]$13059 \msr__ren end sync always update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13058 end attribute \src "libresoc.v:193914.3-193923.6" process $proc$libresoc.v:193914$13060 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] attribute \src "libresoc.v:193915.5-193915.29" switch \initial attribute \src "libresoc.v:193915.9-193915.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\msr__data_o[63:0] \$17 case assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \msr__data_o $0\msr__data_o[63:0] end connect \$10 $or$libresoc.v:193798$13035_Y connect \$13 $reduce_or$libresoc.v:193799$13036_Y connect \$15 $or$libresoc.v:193800$13037_Y connect \$17 $or$libresoc.v:193801$13038_Y connect \$20 $reduce_or$libresoc.v:193802$13039_Y connect \$22 $or$libresoc.v:193803$13040_Y connect \$24 $or$libresoc.v:193804$13041_Y connect \$6 $reduce_or$libresoc.v:193805$13042_Y connect \$8 $or$libresoc.v:193806$13043_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i connect { \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen connect \reg_2_sv2__data_i \data_i$2 connect \reg_1_sv1__data_i \data_i$2 connect \reg_0_sv0__data_i \data_i$2 connect { \reg_2_sv2__wen \reg_1_sv1__wen \reg_0_sv0__wen } \wen$1 connect \reg_2_msr2__data_i \data_i$4 connect \reg_1_msr1__data_i \data_i$4 connect \reg_0_msr0__data_i \data_i$4 connect { \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$5 connect \reg_2_nia2__data_i \data_i$3 connect \reg_1_nia1__data_i \data_i$3 connect \reg_0_nia0__data_i \data_i$3 connect { \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen connect { \reg_2_sv2__ren \reg_1_sv1__ren \reg_0_sv0__ren } \sv__ren connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end attribute \src "libresoc.v:193947.1-194005.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l attribute \src "libresoc.v:193948.7-193948.20" wire $0\initial[0:0] attribute \src "libresoc.v:193993.3-194001.6" wire $0\q_int$next[0:0]$13077 attribute \src "libresoc.v:193991.3-193992.27" wire $0\q_int[0:0] attribute \src "libresoc.v:193993.3-194001.6" wire $1\q_int$next[0:0]$13078 attribute \src "libresoc.v:193970.7-193970.19" wire $1\q_int[0:0] attribute \src "libresoc.v:193983.17-193983.96" wire $and$libresoc.v:193983$13067_Y attribute \src "libresoc.v:193988.17-193988.96" wire $and$libresoc.v:193988$13072_Y attribute \src "libresoc.v:193985.18-193985.93" wire $not$libresoc.v:193985$13069_Y attribute \src "libresoc.v:193987.17-193987.92" wire $not$libresoc.v:193987$13071_Y attribute \src "libresoc.v:193990.17-193990.92" wire $not$libresoc.v:193990$13074_Y attribute \src "libresoc.v:193984.18-193984.98" wire $or$libresoc.v:193984$13068_Y attribute \src "libresoc.v:193986.18-193986.99" wire $or$libresoc.v:193986$13070_Y attribute \src "libresoc.v:193989.17-193989.97" wire $or$libresoc.v:193989$13073_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:193948.7-193948.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:193983$13067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:193983$13067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:193988$13072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:193988$13072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:193985$13069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto connect \Y $not$libresoc.v:193985$13069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:193987$13071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto connect \Y $not$libresoc.v:193987$13071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:193990$13074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto connect \Y $not$libresoc.v:193990$13074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:193984$13068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto connect \Y $or$libresoc.v:193984$13068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:193986$13070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int connect \Y $or$libresoc.v:193986$13070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:193989$13073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto connect \Y $or$libresoc.v:193989$13073_Y end attribute \src "libresoc.v:193948.7-193948.20" process $proc$libresoc.v:193948$13079 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:193970.7-193970.19" process $proc$libresoc.v:193970$13080 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:193991.3-193992.27" process $proc$libresoc.v:193991$13075 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:193993.3-194001.6" process $proc$libresoc.v:193993$13076 assign { } { } assign { } { } assign $0\q_int$next[0:0]$13077 $1\q_int$next[0:0]$13078 attribute \src "libresoc.v:193994.5-193994.29" switch \initial attribute \src "libresoc.v:193994.9-193994.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$13078 1'0 case assign $1\q_int$next[0:0]$13078 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$13077 end connect \$9 $and$libresoc.v:193983$13067_Y connect \$11 $or$libresoc.v:193984$13068_Y connect \$13 $not$libresoc.v:193985$13069_Y connect \$15 $or$libresoc.v:193986$13070_Y connect \$1 $not$libresoc.v:193987$13071_Y connect \$3 $and$libresoc.v:193988$13072_Y connect \$5 $or$libresoc.v:193989$13073_Y connect \$7 $not$libresoc.v:193990$13074_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end attribute \src "libresoc.v:194010.1-194972.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" attribute \generator "nMigen" module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 9 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 7 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire output 6 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 8 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" wire output 5 \busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 320 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 296 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 45 output 290 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 2 input 300 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 3 input 299 \dbus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 294 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 input 292 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 output 291 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 298 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 8 output 293 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 295 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 297 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 273 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 274 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 275 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 276 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 277 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 278 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 181 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 182 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 183 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 184 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 185 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 186 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 187 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 188 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 189 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 190 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 191 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 192 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 193 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 194 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 195 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 196 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 197 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 198 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 199 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 200 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 201 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 202 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 203 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 204 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 205 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 206 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 207 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 208 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 209 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 210 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 211 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 212 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 213 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 214 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 215 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 216 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 169 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 170 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 171 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 172 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 173 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 174 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 175 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 176 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 177 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 178 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 179 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 180 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 217 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 218 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 219 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 220 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 221 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 222 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 223 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 224 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 225 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 226 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 227 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 228 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 229 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 230 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 231 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 232 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 233 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 234 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 235 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 236 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 237 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 238 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 239 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 240 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 241 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 242 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 243 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 244 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 245 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 246 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 247 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 248 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 249 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 250 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 251 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 252 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 253 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 254 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 255 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 256 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 257 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 258 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 259 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 260 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 261 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 262 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 263 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 285 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 45 output 279 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 2 input 289 \ibus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 3 input 288 \ibus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 283 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 64 input 281 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 64 input 280 \ibus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 287 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 8 output 282 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 284 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 286 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire output 307 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 28 input 301 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 305 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 32 output 303 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 32 input 302 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 309 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 4 input 304 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 306 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 308 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire output 316 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 28 input 310 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 314 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 32 output 312 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 32 input 311 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 318 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 4 input 313 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 315 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 317 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 319 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 output 10 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 14 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 input 12 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 output 11 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 18 \jtag_wb__err attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 13 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 15 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 16 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" wire input 3 \memerr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 19 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 20 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 21 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 22 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 25 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 23 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 24 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 271 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 272 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 265 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 266 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 267 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 268 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 269 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 270 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 322 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 1 \pc_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234" wire width 64 output 2 \pc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 321 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 78 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 113 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 114 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 115 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 116 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 117 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 118 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 79 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 80 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 81 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 82 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 83 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 84 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 85 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 86 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 88 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 89 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 90 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 91 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 92 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 93 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 94 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 95 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 96 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 97 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 98 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 99 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 100 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 107 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 108 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 103 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 104 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 101 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 102 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 111 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 112 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 28 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 119 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 120 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 29 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 32 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 33 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 34 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 133 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 134 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 135 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 136 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 137 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 138 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 139 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 140 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 141 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 142 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 143 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 144 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 145 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 146 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 147 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 148 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 149 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 150 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 151 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 152 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 153 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 154 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 155 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 156 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 157 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 158 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 159 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 160 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 161 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 162 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 163 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 164 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 165 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 166 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 167 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 168 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 35 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 38 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 39 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 40 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 41 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 44 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 45 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 46 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 47 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 50 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 51 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 52 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 53 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 56 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 57 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 58 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 59 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 62 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 63 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 64 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 65 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 68 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 69 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 70 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 71 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 72 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 74 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 75 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 76 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 121 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 122 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 123 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 124 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 125 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 126 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 127 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 128 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 129 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 130 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 131 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 132 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 105 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 106 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 109 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 110 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire \ti_coresync_clk attribute \module_not_derived 1 attribute \src "libresoc.v:194657.6-194970.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_bus__tdo \TAP_bus__tdo connect \TAP_bus__tms \TAP_bus__tms connect \busy_o \busy_o connect \clk \clk connect \core_bigendian_i \core_bigendian_i connect \coresync_clk \ti_coresync_clk connect \dbus__ack \dbus__ack connect \dbus__adr \dbus__adr connect \dbus__cyc \dbus__cyc connect \dbus__dat_r \dbus__dat_r connect \dbus__dat_w \dbus__dat_w connect \dbus__err \dbus__err connect \dbus__sel \dbus__sel connect \dbus__stb \dbus__stb connect \dbus__we \dbus__we connect \eint_0__core__i \eint_0__core__i connect \eint_0__pad__i \eint_0__pad__i connect \eint_1__core__i \eint_1__core__i connect \eint_1__pad__i \eint_1__pad__i connect \eint_2__core__i \eint_2__core__i connect \eint_2__pad__i \eint_2__pad__i connect \gpio_e10__core__i \gpio_e10__core__i connect \gpio_e10__core__o \gpio_e10__core__o connect \gpio_e10__core__oe \gpio_e10__core__oe connect \gpio_e10__pad__i \gpio_e10__pad__i connect \gpio_e10__pad__o \gpio_e10__pad__o connect \gpio_e10__pad__oe \gpio_e10__pad__oe connect \gpio_e11__core__i \gpio_e11__core__i connect \gpio_e11__core__o \gpio_e11__core__o connect \gpio_e11__core__oe \gpio_e11__core__oe connect \gpio_e11__pad__i \gpio_e11__pad__i connect \gpio_e11__pad__o \gpio_e11__pad__o connect \gpio_e11__pad__oe \gpio_e11__pad__oe connect \gpio_e12__core__i \gpio_e12__core__i connect \gpio_e12__core__o \gpio_e12__core__o connect \gpio_e12__core__oe \gpio_e12__core__oe connect \gpio_e12__pad__i \gpio_e12__pad__i connect \gpio_e12__pad__o \gpio_e12__pad__o connect \gpio_e12__pad__oe \gpio_e12__pad__oe connect \gpio_e13__core__i \gpio_e13__core__i connect \gpio_e13__core__o \gpio_e13__core__o connect \gpio_e13__core__oe \gpio_e13__core__oe connect \gpio_e13__pad__i \gpio_e13__pad__i connect \gpio_e13__pad__o \gpio_e13__pad__o connect \gpio_e13__pad__oe \gpio_e13__pad__oe connect \gpio_e14__core__i \gpio_e14__core__i connect \gpio_e14__core__o \gpio_e14__core__o connect \gpio_e14__core__oe \gpio_e14__core__oe connect \gpio_e14__pad__i \gpio_e14__pad__i connect \gpio_e14__pad__o \gpio_e14__pad__o connect \gpio_e14__pad__oe \gpio_e14__pad__oe connect \gpio_e15__core__i \gpio_e15__core__i connect \gpio_e15__core__o \gpio_e15__core__o connect \gpio_e15__core__oe \gpio_e15__core__oe connect \gpio_e15__pad__i \gpio_e15__pad__i connect \gpio_e15__pad__o \gpio_e15__pad__o connect \gpio_e15__pad__oe \gpio_e15__pad__oe connect \gpio_e8__core__i \gpio_e8__core__i connect \gpio_e8__core__o \gpio_e8__core__o connect \gpio_e8__core__oe \gpio_e8__core__oe connect \gpio_e8__pad__i \gpio_e8__pad__i connect \gpio_e8__pad__o \gpio_e8__pad__o connect \gpio_e8__pad__oe \gpio_e8__pad__oe connect \gpio_e9__core__i \gpio_e9__core__i connect \gpio_e9__core__o \gpio_e9__core__o connect \gpio_e9__core__oe \gpio_e9__core__oe connect \gpio_e9__pad__i \gpio_e9__pad__i connect \gpio_e9__pad__o \gpio_e9__pad__o connect \gpio_e9__pad__oe \gpio_e9__pad__oe connect \gpio_s0__core__i \gpio_s0__core__i connect \gpio_s0__core__o \gpio_s0__core__o connect \gpio_s0__core__oe \gpio_s0__core__oe connect \gpio_s0__pad__i \gpio_s0__pad__i connect \gpio_s0__pad__o \gpio_s0__pad__o connect \gpio_s0__pad__oe \gpio_s0__pad__oe connect \gpio_s1__core__i \gpio_s1__core__i connect \gpio_s1__core__o \gpio_s1__core__o connect \gpio_s1__core__oe \gpio_s1__core__oe connect \gpio_s1__pad__i \gpio_s1__pad__i connect \gpio_s1__pad__o \gpio_s1__pad__o connect \gpio_s1__pad__oe \gpio_s1__pad__oe connect \gpio_s2__core__i \gpio_s2__core__i connect \gpio_s2__core__o \gpio_s2__core__o connect \gpio_s2__core__oe \gpio_s2__core__oe connect \gpio_s2__pad__i \gpio_s2__pad__i connect \gpio_s2__pad__o \gpio_s2__pad__o connect \gpio_s2__pad__oe \gpio_s2__pad__oe connect \gpio_s3__core__i \gpio_s3__core__i connect \gpio_s3__core__o \gpio_s3__core__o connect \gpio_s3__core__oe \gpio_s3__core__oe connect \gpio_s3__pad__i \gpio_s3__pad__i connect \gpio_s3__pad__o \gpio_s3__pad__o connect \gpio_s3__pad__oe \gpio_s3__pad__oe connect \gpio_s4__core__i \gpio_s4__core__i connect \gpio_s4__core__o \gpio_s4__core__o connect \gpio_s4__core__oe \gpio_s4__core__oe connect \gpio_s4__pad__i \gpio_s4__pad__i connect \gpio_s4__pad__o \gpio_s4__pad__o connect \gpio_s4__pad__oe \gpio_s4__pad__oe connect \gpio_s5__core__i \gpio_s5__core__i connect \gpio_s5__core__o \gpio_s5__core__o connect \gpio_s5__core__oe \gpio_s5__core__oe connect \gpio_s5__pad__i \gpio_s5__pad__i connect \gpio_s5__pad__o \gpio_s5__pad__o connect \gpio_s5__pad__oe \gpio_s5__pad__oe connect \gpio_s6__core__i \gpio_s6__core__i connect \gpio_s6__core__o \gpio_s6__core__o connect \gpio_s6__core__oe \gpio_s6__core__oe connect \gpio_s6__pad__i \gpio_s6__pad__i connect \gpio_s6__pad__o \gpio_s6__pad__o connect \gpio_s6__pad__oe \gpio_s6__pad__oe connect \gpio_s7__core__i \gpio_s7__core__i connect \gpio_s7__core__o \gpio_s7__core__o connect \gpio_s7__core__oe \gpio_s7__core__oe connect \gpio_s7__pad__i \gpio_s7__pad__i connect \gpio_s7__pad__o \gpio_s7__pad__o connect \gpio_s7__pad__oe \gpio_s7__pad__oe connect \ibus__ack \ibus__ack connect \ibus__adr \ibus__adr connect \ibus__cyc \ibus__cyc connect \ibus__dat_r \ibus__dat_r connect \ibus__err \ibus__err connect \ibus__sel \ibus__sel connect \ibus__stb \ibus__stb connect \icp_wb__ack \icp_wb__ack connect \icp_wb__adr \icp_wb__adr connect \icp_wb__cyc \icp_wb__cyc connect \icp_wb__dat_r \icp_wb__dat_r connect \icp_wb__dat_w \icp_wb__dat_w connect \icp_wb__sel \icp_wb__sel connect \icp_wb__stb \icp_wb__stb connect \icp_wb__we \icp_wb__we connect \ics_wb__ack \ics_wb__ack connect \ics_wb__adr \ics_wb__adr connect \ics_wb__cyc \ics_wb__cyc connect \ics_wb__dat_r \ics_wb__dat_r connect \ics_wb__dat_w \ics_wb__dat_w connect \ics_wb__stb \ics_wb__stb connect \ics_wb__we \ics_wb__we connect \int_level_i \int_level_i connect \jtag_wb__ack \jtag_wb__ack connect \jtag_wb__adr \jtag_wb__adr connect \jtag_wb__cyc \jtag_wb__cyc connect \jtag_wb__dat_r \jtag_wb__dat_r connect \jtag_wb__dat_w \jtag_wb__dat_w connect \jtag_wb__sel \jtag_wb__sel connect \jtag_wb__stb \jtag_wb__stb connect \jtag_wb__we \jtag_wb__we connect \mspi0_clk__core__o \mspi0_clk__core__o connect \mspi0_clk__pad__o \mspi0_clk__pad__o connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o connect \mspi0_miso__core__i \mspi0_miso__core__i connect \mspi0_miso__pad__i \mspi0_miso__pad__i connect \mspi0_mosi__core__o \mspi0_mosi__core__o connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o connect \mtwi_scl__core__o \mtwi_scl__core__o connect \mtwi_scl__pad__o \mtwi_scl__pad__o connect \mtwi_sda__core__i \mtwi_sda__core__i connect \mtwi_sda__core__o \mtwi_sda__core__o connect \mtwi_sda__core__oe \mtwi_sda__core__oe connect \mtwi_sda__pad__i \mtwi_sda__pad__i connect \mtwi_sda__pad__o \mtwi_sda__pad__o connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe connect \pc_i \pc_i connect \pc_i_ok \pc_i_ok connect \pc_o \pc_o connect \rst \rst connect \sdr_a_0__core__o \sdr_a_0__core__o connect \sdr_a_0__pad__o \sdr_a_0__pad__o connect \sdr_a_10__core__o \sdr_a_10__core__o connect \sdr_a_10__pad__o \sdr_a_10__pad__o connect \sdr_a_11__core__o \sdr_a_11__core__o connect \sdr_a_11__pad__o \sdr_a_11__pad__o connect \sdr_a_12__core__o \sdr_a_12__core__o connect \sdr_a_12__pad__o \sdr_a_12__pad__o connect \sdr_a_1__core__o \sdr_a_1__core__o connect \sdr_a_1__pad__o \sdr_a_1__pad__o connect \sdr_a_2__core__o \sdr_a_2__core__o connect \sdr_a_2__pad__o \sdr_a_2__pad__o connect \sdr_a_3__core__o \sdr_a_3__core__o connect \sdr_a_3__pad__o \sdr_a_3__pad__o connect \sdr_a_4__core__o \sdr_a_4__core__o connect \sdr_a_4__pad__o \sdr_a_4__pad__o connect \sdr_a_5__core__o \sdr_a_5__core__o connect \sdr_a_5__pad__o \sdr_a_5__pad__o connect \sdr_a_6__core__o \sdr_a_6__core__o connect \sdr_a_6__pad__o \sdr_a_6__pad__o connect \sdr_a_7__core__o \sdr_a_7__core__o connect \sdr_a_7__pad__o \sdr_a_7__pad__o connect \sdr_a_8__core__o \sdr_a_8__core__o connect \sdr_a_8__pad__o \sdr_a_8__pad__o connect \sdr_a_9__core__o \sdr_a_9__core__o connect \sdr_a_9__pad__o \sdr_a_9__pad__o connect \sdr_ba_0__core__o \sdr_ba_0__core__o connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o connect \sdr_ba_1__core__o \sdr_ba_1__core__o connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o connect \sdr_cas_n__core__o \sdr_cas_n__core__o connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o connect \sdr_cke__core__o \sdr_cke__core__o connect \sdr_cke__pad__o \sdr_cke__pad__o connect \sdr_clock__core__o \sdr_clock__core__o connect \sdr_clock__pad__o \sdr_clock__pad__o connect \sdr_cs_n__core__o \sdr_cs_n__core__o connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o connect \sdr_dm_0__core__o \sdr_dm_0__core__o connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o connect \sdr_dm_1__core__o \sdr_dm_1__core__o connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o connect \sdr_dq_0__core__i \sdr_dq_0__core__i connect \sdr_dq_0__core__o \sdr_dq_0__core__o connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o 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connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe connect \sdr_dq_6__core__i \sdr_dq_6__core__i connect \sdr_dq_6__core__o \sdr_dq_6__core__o connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe connect \sdr_dq_7__core__i \sdr_dq_7__core__i connect \sdr_dq_7__core__o \sdr_dq_7__core__o connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe connect \sdr_dq_8__core__i \sdr_dq_8__core__i connect \sdr_dq_8__core__o \sdr_dq_8__core__o connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe connect \sdr_dq_9__core__i \sdr_dq_9__core__i connect \sdr_dq_9__core__o \sdr_dq_9__core__o connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe connect \sdr_ras_n__core__o \sdr_ras_n__core__o connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o connect \sdr_we_n__core__o \sdr_we_n__core__o connect \sdr_we_n__pad__o \sdr_we_n__pad__o end connect \ti_coresync_clk \clk end attribute \src "libresoc.v:194976.1-200172.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $0\core_asmcode$next[7:0]$13561 attribute \src "libresoc.v:197205.3-197206.41" wire width 8 $0\core_asmcode[7:0] attribute \src "libresoc.v:198018.3-198053.6" wire $0\core_bigendian_i$10$next[0:0]$13357 attribute \src "libresoc.v:197335.3-197336.57" wire $0\core_bigendian_i$10[0:0]$13293 attribute \src "libresoc.v:195253.7-195253.35" wire $0\core_bigendian_i$10[0:0]$13715 attribute \src "libresoc.v:198699.3-198711.6" wire width 3 $0\core_cia__ren[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 64 $0\core_core_core_cia$next[63:0]$13562 attribute \src "libresoc.v:197279.3-197280.53" wire width 64 $0\core_core_core_cia[63:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $0\core_core_core_cr_rd$next[7:0]$13563 attribute \src "libresoc.v:197323.3-197324.57" wire width 8 $0\core_core_core_cr_rd[7:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_cr_rd_ok$next[0:0]$13564 attribute \src "libresoc.v:197325.3-197326.63" wire $0\core_core_core_cr_rd_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $0\core_core_core_cr_wr$next[7:0]$13565 attribute \src "libresoc.v:197327.3-197328.57" wire width 8 $0\core_core_core_cr_wr[7:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_exc_$signal$3$next[0:0]$13566 attribute \src "libresoc.v:197305.3-197306.75" wire $0\core_core_core_exc_$signal$3[0:0]$13271 attribute \src "libresoc.v:195279.7-195279.44" wire $0\core_core_core_exc_$signal$3[0:0]$13723 attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_exc_$signal$4$next[0:0]$13567 attribute \src "libresoc.v:197307.3-197308.75" wire $0\core_core_core_exc_$signal$4[0:0]$13273 attribute \src "libresoc.v:195283.7-195283.44" wire $0\core_core_core_exc_$signal$4[0:0]$13725 attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_exc_$signal$5$next[0:0]$13568 attribute \src "libresoc.v:197309.3-197310.75" wire $0\core_core_core_exc_$signal$5[0:0]$13275 attribute \src "libresoc.v:195287.7-195287.44" wire $0\core_core_core_exc_$signal$5[0:0]$13727 attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_exc_$signal$6$next[0:0]$13569 attribute \src "libresoc.v:197311.3-197312.75" wire $0\core_core_core_exc_$signal$6[0:0]$13277 attribute \src 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$0\core_core_core_exc_$signal$next[0:0]$13573 attribute \src "libresoc.v:197303.3-197304.71" wire $0\core_core_core_exc_$signal[0:0]$13269 attribute \src "libresoc.v:195277.7-195277.42" wire $0\core_core_core_exc_$signal[0:0]$13721 attribute \src "libresoc.v:200001.3-200122.6" wire width 14 $0\core_core_core_fn_unit$next[13:0]$13574 attribute \src "libresoc.v:197285.3-197286.61" wire width 14 $0\core_core_core_fn_unit[13:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 2 $0\core_core_core_input_carry$next[1:0]$13575 attribute \src "libresoc.v:197299.3-197300.69" wire width 2 $0\core_core_core_input_carry[1:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 32 $0\core_core_core_insn$next[31:0]$13576 attribute \src "libresoc.v:197281.3-197282.55" wire width 32 $0\core_core_core_insn[31:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_core_insn_type$next[6:0]$13577 attribute \src "libresoc.v:197283.3-197284.65" wire width 7 $0\core_core_core_insn_type[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_is_32bit$next[0:0]$13578 attribute \src "libresoc.v:197331.3-197332.63" wire $0\core_core_core_is_32bit[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 64 $0\core_core_core_msr$next[63:0]$13579 attribute \src "libresoc.v:197277.3-197278.53" wire width 64 $0\core_core_core_msr[63:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_oe$next[0:0]$13580 attribute \src "libresoc.v:197295.3-197296.51" wire $0\core_core_core_oe[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_oe_ok$next[0:0]$13581 attribute \src "libresoc.v:197297.3-197298.57" wire $0\core_core_core_oe_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_rc$next[0:0]$13582 attribute \src "libresoc.v:197289.3-197290.51" wire $0\core_core_core_rc[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_core_rc_ok$next[0:0]$13583 attribute \src "libresoc.v:197293.3-197294.57" wire $0\core_core_core_rc_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 13 $0\core_core_core_trapaddr$next[12:0]$13584 attribute \src "libresoc.v:197321.3-197322.63" wire width 13 $0\core_core_core_trapaddr[12:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $0\core_core_core_traptype$next[7:0]$13585 attribute \src "libresoc.v:197301.3-197302.63" wire width 8 $0\core_core_core_traptype[7:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_cr_in1$next[6:0]$13586 attribute \src "libresoc.v:197259.3-197260.49" wire width 7 $0\core_core_cr_in1[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_cr_in1_ok$next[0:0]$13587 attribute \src "libresoc.v:197261.3-197262.55" wire $0\core_core_cr_in1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_cr_in2$1$next[6:0]$13588 attribute \src "libresoc.v:197267.3-197268.55" wire width 7 $0\core_core_cr_in2$1[6:0]$13249 attribute \src "libresoc.v:195461.13-195461.41" wire width 7 $0\core_core_cr_in2$1[6:0]$13752 attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_cr_in2$next[6:0]$13589 attribute \src "libresoc.v:197263.3-197264.49" wire width 7 $0\core_core_cr_in2[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_cr_in2_ok$2$next[0:0]$13590 attribute \src "libresoc.v:197271.3-197272.61" wire $0\core_core_cr_in2_ok$2[0:0]$13252 attribute \src "libresoc.v:195469.7-195469.37" wire $0\core_core_cr_in2_ok$2[0:0]$13755 attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_cr_in2_ok$next[0:0]$13591 attribute \src "libresoc.v:197265.3-197266.55" wire $0\core_core_cr_in2_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_cr_out$next[6:0]$13592 attribute \src "libresoc.v:197273.3-197274.49" wire width 7 $0\core_core_cr_out[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_cr_wr_ok$next[0:0]$13593 attribute \src "libresoc.v:197329.3-197330.53" wire $0\core_core_cr_wr_ok[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $0\core_core_dststep$next[6:0]$13322 attribute \src "libresoc.v:197195.3-197196.51" wire width 7 $0\core_core_dststep[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_ea$next[6:0]$13594 attribute \src "libresoc.v:197211.3-197212.41" wire width 7 $0\core_core_ea[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $0\core_core_fast1$next[2:0]$13595 attribute \src "libresoc.v:197241.3-197242.47" wire width 3 $0\core_core_fast1[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_fast1_ok$next[0:0]$13596 attribute \src "libresoc.v:197243.3-197244.53" wire $0\core_core_fast1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $0\core_core_fast2$next[2:0]$13597 attribute \src "libresoc.v:197245.3-197246.47" wire width 3 $0\core_core_fast2[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_fast2_ok$next[0:0]$13598 attribute \src "libresoc.v:197249.3-197250.53" wire $0\core_core_fast2_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $0\core_core_fasto1$next[2:0]$13599 attribute \src "libresoc.v:197251.3-197252.49" wire width 3 $0\core_core_fasto1[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $0\core_core_fasto2$next[2:0]$13600 attribute \src "libresoc.v:197255.3-197256.49" wire width 3 $0\core_core_fasto2[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_lk$next[0:0]$13601 attribute \src "libresoc.v:197287.3-197288.41" wire $0\core_core_lk[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $0\core_core_maxvl$next[6:0]$13323 attribute \src "libresoc.v:197201.3-197202.47" wire width 7 $0\core_core_maxvl[6:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $0\core_core_pc$next[63:0]$13324 attribute \src "libresoc.v:197173.3-197174.41" wire width 64 $0\core_core_pc[63:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_reg1$next[6:0]$13602 attribute \src "libresoc.v:197215.3-197216.45" wire width 7 $0\core_core_reg1[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_reg1_ok$next[0:0]$13603 attribute \src "libresoc.v:197217.3-197218.51" wire $0\core_core_reg1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_reg2$next[6:0]$13604 attribute \src "libresoc.v:197219.3-197220.45" wire width 7 $0\core_core_reg2[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_reg2_ok$next[0:0]$13605 attribute \src "libresoc.v:197221.3-197222.51" wire $0\core_core_reg2_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_reg3$next[6:0]$13606 attribute \src "libresoc.v:197223.3-197224.45" wire width 7 $0\core_core_reg3[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_reg3_ok$next[0:0]$13607 attribute \src "libresoc.v:197227.3-197228.51" wire $0\core_core_reg3_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $0\core_core_rego$next[6:0]$13608 attribute \src "libresoc.v:197207.3-197208.45" wire width 7 $0\core_core_rego[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 10 $0\core_core_spr1$next[9:0]$13609 attribute \src "libresoc.v:197233.3-197234.45" wire width 10 $0\core_core_spr1[9:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_core_spr1_ok$next[0:0]$13610 attribute \src "libresoc.v:197235.3-197236.51" wire $0\core_core_spr1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 10 $0\core_core_spro$next[9:0]$13611 attribute \src "libresoc.v:197229.3-197230.45" wire width 10 $0\core_core_spro[9:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $0\core_core_srcstep$next[6:0]$13325 attribute \src "libresoc.v:197197.3-197198.51" wire width 7 $0\core_core_srcstep[6:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 2 $0\core_core_subvl$next[1:0]$13326 attribute \src "libresoc.v:197193.3-197194.47" wire width 2 $0\core_core_subvl[1:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 2 $0\core_core_svstep$next[1:0]$13327 attribute \src "libresoc.v:197191.3-197192.49" wire width 2 $0\core_core_svstep[1:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $0\core_core_vl$next[6:0]$13328 attribute \src "libresoc.v:197199.3-197200.41" wire width 7 $0\core_core_vl[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $0\core_core_xer_in$next[2:0]$13612 attribute \src "libresoc.v:197237.3-197238.49" wire width 3 $0\core_core_xer_in[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_cr_out_ok$next[0:0]$13613 attribute \src "libresoc.v:197275.3-197276.45" wire $0\core_cr_out_ok[0:0] attribute \src "libresoc.v:198228.3-198237.6" wire width 64 $0\core_data_i$12[63:0]$13371 attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $0\core_data_i[63:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $0\core_dec$next[63:0]$13329 attribute \src "libresoc.v:197189.3-197190.33" wire width 64 $0\core_dec[63:0] attribute \src "libresoc.v:198345.3-198354.6" wire width 5 $0\core_dmi__addr[4:0] attribute \src "libresoc.v:198355.3-198364.6" wire $0\core_dmi__ren[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_ea_ok$next[0:0]$13614 attribute \src "libresoc.v:197213.3-197214.37" wire $0\core_ea_ok[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire $0\core_eint$next[0:0]$13330 attribute \src "libresoc.v:197187.3-197188.35" wire $0\core_eint[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_fasto1_ok$next[0:0]$13615 attribute \src "libresoc.v:197253.3-197254.45" wire $0\core_fasto1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_fasto2_ok$next[0:0]$13616 attribute \src "libresoc.v:197257.3-197258.45" wire $0\core_fasto2_ok[0:0] attribute \src "libresoc.v:198394.3-198403.6" wire width 8 $0\core_full_rd2__ren[7:0] attribute \src "libresoc.v:198433.3-198442.6" wire width 3 $0\core_full_rd__ren[2:0] attribute \src "libresoc.v:198553.3-198575.6" wire width 3 $0\core_issue__addr$13[2:0]$13411 attribute \src "libresoc.v:198472.3-198490.6" wire width 3 $0\core_issue__addr[2:0] attribute \src "libresoc.v:198599.3-198621.6" wire width 64 $0\core_issue__data_i[63:0] attribute \src "libresoc.v:198491.3-198509.6" wire $0\core_issue__ren[0:0] attribute \src "libresoc.v:198576.3-198598.6" wire $0\core_issue__wen[0:0] attribute \src "libresoc.v:198274.3-198289.6" wire $0\core_issue_i[0:0] attribute \src "libresoc.v:198249.3-198273.6" wire $0\core_ivalid_i[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $0\core_msr$next[63:0]$13331 attribute \src "libresoc.v:197185.3-197186.33" wire width 64 $0\core_msr[63:0] attribute \src "libresoc.v:198926.3-198941.6" wire width 3 $0\core_msr__ren[2:0] attribute \src "libresoc.v:197982.3-198017.6" wire width 32 $0\core_raw_insn_i$next[31:0]$13353 attribute \src "libresoc.v:197357.3-197358.47" wire width 32 $0\core_raw_insn_i[31:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_rego_ok$next[0:0]$13617 attribute \src "libresoc.v:197209.3-197210.41" wire $0\core_rego_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_spro_ok$next[0:0]$13618 attribute \src "libresoc.v:197231.3-197232.41" wire $0\core_spro_ok[0:0] attribute \src "libresoc.v:199525.3-199579.6" wire $0\core_stopped_i[0:0] attribute \src "libresoc.v:198737.3-198749.6" wire width 3 $0\core_sv__ren[2:0] attribute \src "libresoc.v:198054.3-198089.6" wire $0\core_sv_a_nz$next[0:0]$13361 attribute \src "libresoc.v:197313.3-197314.41" wire $0\core_sv_a_nz[0:0] attribute \src "libresoc.v:198218.3-198227.6" wire width 3 $0\core_wen$11[2:0]$13368 attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $0\core_wen[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $0\core_xer_out$next[0:0]$13619 attribute \src "libresoc.v:197239.3-197240.41" wire $0\core_xer_out[0:0] attribute \src "libresoc.v:197371.3-197372.43" wire $0\cu_st__rel_o_dly[0:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $0\cur_cur_dststep$next[6:0]$13452 attribute \src "libresoc.v:197355.3-197356.47" wire width 7 $0\cur_cur_dststep[6:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $0\cur_cur_maxvl$next[6:0]$13453 attribute \src "libresoc.v:197363.3-197364.43" wire width 7 $0\cur_cur_maxvl[6:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $0\cur_cur_srcstep$next[6:0]$13454 attribute \src "libresoc.v:197359.3-197360.47" wire width 7 $0\cur_cur_srcstep[6:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $0\cur_cur_subvl$next[1:0]$13455 attribute \src "libresoc.v:197353.3-197354.43" wire width 2 $0\cur_cur_subvl[1:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $0\cur_cur_svstep$next[1:0]$13456 attribute \src "libresoc.v:197351.3-197352.45" wire width 2 $0\cur_cur_svstep[1:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $0\cur_cur_vl$next[6:0]$13457 attribute \src "libresoc.v:197361.3-197362.37" wire width 7 $0\cur_cur_vl[6:0] attribute \src "libresoc.v:198404.3-198412.6" wire $0\d_cr_delay$next[0:0]$13393 attribute \src "libresoc.v:197247.3-197248.37" wire $0\d_cr_delay[0:0] attribute \src "libresoc.v:198365.3-198373.6" wire $0\d_reg_delay$next[0:0]$13387 attribute \src "libresoc.v:197269.3-197270.39" wire $0\d_reg_delay[0:0] attribute \src "libresoc.v:198443.3-198451.6" wire $0\d_xer_delay$next[0:0]$13399 attribute \src "libresoc.v:197225.3-197226.39" wire $0\d_xer_delay[0:0] attribute \src "libresoc.v:199580.3-199634.6" wire $0\dbg_core_stopped_i[0:0] attribute \src "libresoc.v:198423.3-198432.6" wire $0\dbg_d_cr_ack[0:0] attribute \src "libresoc.v:198413.3-198422.6" wire width 64 $0\dbg_d_cr_data[63:0] attribute \src "libresoc.v:198384.3-198393.6" wire $0\dbg_d_gpr_ack[0:0] attribute \src "libresoc.v:198374.3-198383.6" wire width 64 $0\dbg_d_gpr_data[63:0] attribute \src "libresoc.v:198462.3-198471.6" wire $0\dbg_d_xer_ack[0:0] attribute \src "libresoc.v:198452.3-198461.6" wire width 64 $0\dbg_d_xer_data[63:0] attribute \src "libresoc.v:197908.3-197916.6" wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13316 attribute \src "libresoc.v:197183.3-197184.45" wire width 4 $0\dbg_dmi_addr_i[3:0] attribute \src "libresoc.v:198942.3-198950.6" wire width 64 $0\dbg_dmi_din$next[63:0]$13437 attribute \src "libresoc.v:197177.3-197178.39" wire width 64 $0\dbg_dmi_din[63:0] attribute \src "libresoc.v:197917.3-197925.6" wire $0\dbg_dmi_req_i$next[0:0]$13319 attribute \src "libresoc.v:197181.3-197182.43" wire $0\dbg_dmi_req_i[0:0] attribute \src "libresoc.v:198665.3-198673.6" wire $0\dbg_dmi_we_i$next[0:0]$13421 attribute \src "libresoc.v:197179.3-197180.41" wire $0\dbg_dmi_we_i[0:0] attribute \src "libresoc.v:198622.3-198641.6" wire width 64 $0\dec2_cur_dec$next[63:0]$13416 attribute \src "libresoc.v:197171.3-197172.41" wire width 64 $0\dec2_cur_dec[63:0] attribute \src "libresoc.v:200123.3-200131.6" wire $0\dec2_cur_eint$next[0:0]$13707 attribute \src "libresoc.v:197375.3-197376.43" wire $0\dec2_cur_eint[0:0] attribute \src "libresoc.v:199208.3-199232.6" wire width 64 $0\dec2_cur_msr$next[63:0]$13500 attribute \src "libresoc.v:197345.3-197346.41" wire width 64 $0\dec2_cur_msr[63:0] attribute \src "libresoc.v:199055.3-199075.6" wire width 64 $0\dec2_cur_pc$next[63:0]$13447 attribute \src "libresoc.v:197365.3-197366.39" wire width 64 $0\dec2_cur_pc[63:0] attribute \src "libresoc.v:199256.3-199290.6" wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13509 attribute \src "libresoc.v:197341.3-197342.53" wire width 32 $0\dec2_raw_opcode_in[31:0] attribute \src "libresoc.v:200132.3-200141.6" wire width 2 $0\delay$next[1:0]$13710 attribute \src "libresoc.v:197373.3-197374.27" wire width 2 $0\delay[1:0] attribute \src "libresoc.v:198290.3-198324.6" wire $0\exec_fsm_state$next[0:0]$13377 attribute \src "libresoc.v:197291.3-197292.45" wire $0\exec_fsm_state[0:0] attribute \src "libresoc.v:198238.3-198248.6" wire $0\exec_insn_ready_o[0:0] attribute \src "libresoc.v:198090.3-198124.6" wire $0\exec_insn_valid_i[0:0] attribute \src "libresoc.v:198125.3-198168.6" wire $0\exec_pc_ready_i[0:0] attribute \src "libresoc.v:198325.3-198344.6" wire $0\exec_pc_valid_o[0:0] attribute \src "libresoc.v:199154.3-199207.6" wire width 2 $0\fetch_fsm_state$next[1:0]$13492 attribute \src "libresoc.v:197347.3-197348.47" wire width 2 $0\fetch_fsm_state[1:0] attribute \src "libresoc.v:199898.3-199912.6" wire $0\fetch_insn_ready_i[0:0] attribute \src "libresoc.v:199291.3-199313.6" wire $0\fetch_insn_valid_o[0:0] attribute \src "libresoc.v:198951.3-198961.6" wire $0\fetch_pc_ready_o[0:0] attribute \src "libresoc.v:199401.3-199416.6" wire $0\fetch_pc_valid_i[0:0] attribute \src "libresoc.v:198510.3-198537.6" wire width 2 $0\fsm_state$next[1:0]$13406 attribute \src "libresoc.v:197203.3-197204.35" wire width 2 $0\fsm_state[1:0] attribute \src "libresoc.v:198962.3-198977.6" wire width 48 $0\imem_a_pc_i[47:0] attribute \src "libresoc.v:198987.3-199020.6" wire $0\imem_a_valid_i[0:0] attribute \src "libresoc.v:199021.3-199054.6" wire $0\imem_f_valid_i[0:0] attribute \src "libresoc.v:194977.7-194977.20" wire $0\initial[0:0] attribute \src "libresoc.v:199913.3-199958.6" wire $0\insn_done[0:0] attribute \src "libresoc.v:198169.3-198217.6" wire $0\is_last[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $0\issue_fsm_state$next[2:0]$13517 attribute \src "libresoc.v:197339.3-197340.47" wire width 3 $0\issue_fsm_state[2:0] attribute \src "libresoc.v:198978.3-198986.6" wire $0\jtag_dmi0__ack_o$next[0:0]$13442 attribute \src "libresoc.v:197175.3-197176.49" wire $0\jtag_dmi0__ack_o[0:0] attribute \src "libresoc.v:199145.3-199153.6" wire width 64 $0\jtag_dmi0__dout$next[63:0]$13489 attribute \src "libresoc.v:197377.3-197378.47" wire width 64 $0\jtag_dmi0__dout[63:0] attribute \src "libresoc.v:199115.3-199144.6" wire $0\msr_read$next[0:0]$13483 attribute \src "libresoc.v:197349.3-197350.33" wire $0\msr_read[0:0] attribute \src "libresoc.v:198538.3-198552.6" wire width 64 $0\new_dec[63:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_maxvl[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $0\new_svstate_subvl[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $0\new_svstate_svstep[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $0\new_svstate_vl[6:0] attribute \src "libresoc.v:198642.3-198664.6" wire width 64 $0\new_tb[63:0] attribute \src "libresoc.v:199233.3-199255.6" wire width 64 $0\nia$next[63:0]$13505 attribute \src "libresoc.v:197343.3-197344.23" wire width 64 $0\nia[63:0] attribute \src "libresoc.v:198683.3-198698.6" wire width 64 $0\pc[63:0] attribute \src "libresoc.v:199635.3-199725.6" wire $0\pc_changed$next[0:0]$13534 attribute \src "libresoc.v:197337.3-197338.37" wire $0\pc_changed[0:0] attribute \src "libresoc.v:198674.3-198682.6" wire $0\pc_ok_delay$next[0:0]$13424 attribute \src "libresoc.v:197369.3-197370.39" wire $0\pc_ok_delay[0:0] attribute \src "libresoc.v:199959.3-199977.6" wire $0\pred_insn_valid_i[0:0] attribute \src "libresoc.v:199978.3-200000.6" wire $0\pred_mask_ready_i[0:0] attribute \src "libresoc.v:199807.3-199897.6" wire $0\sv_changed$next[0:0]$13546 attribute \src "libresoc.v:197333.3-197334.37" wire $0\sv_changed[0:0] attribute \src "libresoc.v:198721.3-198736.6" wire width 64 $0\svstate[63:0] attribute \src "libresoc.v:198712.3-198720.6" wire $0\svstate_ok_delay$next[0:0]$13429 attribute \src "libresoc.v:197367.3-197368.49" wire $0\svstate_ok_delay[0:0] attribute \src "libresoc.v:199726.3-199806.6" wire $0\update_svstate[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $10\issue_fsm_state$next[2:0]$13527 attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $11\issue_fsm_state$next[2:0]$13528 attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $12\issue_fsm_state$next[2:0]$13529 attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $13\issue_fsm_state$next[2:0]$13530 attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $1\core_asmcode$next[7:0]$13620 attribute \src "libresoc.v:195247.13-195247.33" wire width 8 $1\core_asmcode[7:0] attribute \src "libresoc.v:198018.3-198053.6" wire $1\core_bigendian_i$10$next[0:0]$13358 attribute \src "libresoc.v:198699.3-198711.6" wire width 3 $1\core_cia__ren[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 64 $1\core_core_core_cia$next[63:0]$13621 attribute \src "libresoc.v:195261.14-195261.55" wire width 64 $1\core_core_core_cia[63:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $1\core_core_core_cr_rd$next[7:0]$13622 attribute \src "libresoc.v:195265.13-195265.41" wire width 8 $1\core_core_core_cr_rd[7:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_cr_rd_ok$next[0:0]$13623 attribute \src "libresoc.v:195269.7-195269.37" wire $1\core_core_core_cr_rd_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $1\core_core_core_cr_wr$next[7:0]$13624 attribute \src "libresoc.v:195273.13-195273.41" wire width 8 $1\core_core_core_cr_wr[7:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$3$next[0:0]$13625 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$4$next[0:0]$13626 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$5$next[0:0]$13627 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$6$next[0:0]$13628 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$7$next[0:0]$13629 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$8$next[0:0]$13630 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$9$next[0:0]$13631 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_exc_$signal$next[0:0]$13632 attribute \src "libresoc.v:200001.3-200122.6" wire width 14 $1\core_core_core_fn_unit$next[13:0]$13633 attribute \src "libresoc.v:195324.14-195324.47" wire width 14 $1\core_core_core_fn_unit[13:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 2 $1\core_core_core_input_carry$next[1:0]$13634 attribute \src "libresoc.v:195332.13-195332.46" wire width 2 $1\core_core_core_input_carry[1:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 32 $1\core_core_core_insn$next[31:0]$13635 attribute \src "libresoc.v:195336.14-195336.41" wire width 32 $1\core_core_core_insn[31:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_core_insn_type$next[6:0]$13636 attribute \src "libresoc.v:195415.13-195415.45" wire width 7 $1\core_core_core_insn_type[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_is_32bit$next[0:0]$13637 attribute \src "libresoc.v:195419.7-195419.37" wire $1\core_core_core_is_32bit[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 64 $1\core_core_core_msr$next[63:0]$13638 attribute \src "libresoc.v:195423.14-195423.55" wire width 64 $1\core_core_core_msr[63:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_oe$next[0:0]$13639 attribute \src "libresoc.v:195427.7-195427.31" wire $1\core_core_core_oe[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_oe_ok$next[0:0]$13640 attribute \src "libresoc.v:195431.7-195431.34" wire $1\core_core_core_oe_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_rc$next[0:0]$13641 attribute \src "libresoc.v:195435.7-195435.31" wire $1\core_core_core_rc[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_core_rc_ok$next[0:0]$13642 attribute \src "libresoc.v:195439.7-195439.34" wire $1\core_core_core_rc_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 13 $1\core_core_core_trapaddr$next[12:0]$13643 attribute \src "libresoc.v:195443.14-195443.48" wire width 13 $1\core_core_core_trapaddr[12:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 8 $1\core_core_core_traptype$next[7:0]$13644 attribute \src "libresoc.v:195447.13-195447.44" wire width 8 $1\core_core_core_traptype[7:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_cr_in1$next[6:0]$13645 attribute \src "libresoc.v:195451.13-195451.37" wire width 7 $1\core_core_cr_in1[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_cr_in1_ok$next[0:0]$13646 attribute \src "libresoc.v:195455.7-195455.33" wire $1\core_core_cr_in1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_cr_in2$1$next[6:0]$13647 attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_cr_in2$next[6:0]$13648 attribute \src "libresoc.v:195459.13-195459.37" wire width 7 $1\core_core_cr_in2[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_cr_in2_ok$2$next[0:0]$13649 attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_cr_in2_ok$next[0:0]$13650 attribute \src "libresoc.v:195467.7-195467.33" wire $1\core_core_cr_in2_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_cr_out$next[6:0]$13651 attribute \src "libresoc.v:195475.13-195475.37" wire width 7 $1\core_core_cr_out[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_cr_wr_ok$next[0:0]$13652 attribute \src "libresoc.v:195479.7-195479.32" wire $1\core_core_cr_wr_ok[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $1\core_core_dststep$next[6:0]$13332 attribute \src "libresoc.v:195483.13-195483.38" wire width 7 $1\core_core_dststep[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_ea$next[6:0]$13653 attribute \src "libresoc.v:195487.13-195487.33" wire width 7 $1\core_core_ea[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $1\core_core_fast1$next[2:0]$13654 attribute \src "libresoc.v:195491.13-195491.35" wire width 3 $1\core_core_fast1[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_fast1_ok$next[0:0]$13655 attribute \src "libresoc.v:195495.7-195495.32" wire $1\core_core_fast1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $1\core_core_fast2$next[2:0]$13656 attribute \src "libresoc.v:195499.13-195499.35" wire width 3 $1\core_core_fast2[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_fast2_ok$next[0:0]$13657 attribute \src "libresoc.v:195503.7-195503.32" wire $1\core_core_fast2_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $1\core_core_fasto1$next[2:0]$13658 attribute \src "libresoc.v:195507.13-195507.36" wire width 3 $1\core_core_fasto1[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $1\core_core_fasto2$next[2:0]$13659 attribute \src "libresoc.v:195511.13-195511.36" wire width 3 $1\core_core_fasto2[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_lk$next[0:0]$13660 attribute \src "libresoc.v:195515.7-195515.26" wire $1\core_core_lk[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $1\core_core_maxvl$next[6:0]$13333 attribute \src "libresoc.v:195519.13-195519.36" wire width 7 $1\core_core_maxvl[6:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $1\core_core_pc$next[63:0]$13334 attribute \src "libresoc.v:195523.14-195523.49" wire width 64 $1\core_core_pc[63:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_reg1$next[6:0]$13661 attribute \src "libresoc.v:195527.13-195527.35" wire width 7 $1\core_core_reg1[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_reg1_ok$next[0:0]$13662 attribute \src "libresoc.v:195531.7-195531.31" wire $1\core_core_reg1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_reg2$next[6:0]$13663 attribute \src "libresoc.v:195535.13-195535.35" wire width 7 $1\core_core_reg2[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_reg2_ok$next[0:0]$13664 attribute \src "libresoc.v:195539.7-195539.31" wire $1\core_core_reg2_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_reg3$next[6:0]$13665 attribute \src "libresoc.v:195543.13-195543.35" wire width 7 $1\core_core_reg3[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_reg3_ok$next[0:0]$13666 attribute \src "libresoc.v:195547.7-195547.31" wire $1\core_core_reg3_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 7 $1\core_core_rego$next[6:0]$13667 attribute \src "libresoc.v:195551.13-195551.35" wire width 7 $1\core_core_rego[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 10 $1\core_core_spr1$next[9:0]$13668 attribute \src "libresoc.v:195567.13-195567.37" wire width 10 $1\core_core_spr1[9:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_core_spr1_ok$next[0:0]$13669 attribute \src "libresoc.v:195571.7-195571.31" wire $1\core_core_spr1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 10 $1\core_core_spro$next[9:0]$13670 attribute \src "libresoc.v:195587.13-195587.37" wire width 10 $1\core_core_spro[9:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $1\core_core_srcstep$next[6:0]$13335 attribute \src "libresoc.v:195591.13-195591.38" wire width 7 $1\core_core_srcstep[6:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 2 $1\core_core_subvl$next[1:0]$13336 attribute \src "libresoc.v:195595.13-195595.35" wire width 2 $1\core_core_subvl[1:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 2 $1\core_core_svstep$next[1:0]$13337 attribute \src "libresoc.v:195599.13-195599.36" wire width 2 $1\core_core_svstep[1:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $1\core_core_vl$next[6:0]$13338 attribute \src "libresoc.v:195605.13-195605.33" wire width 7 $1\core_core_vl[6:0] attribute \src "libresoc.v:200001.3-200122.6" wire width 3 $1\core_core_xer_in$next[2:0]$13671 attribute \src "libresoc.v:195609.13-195609.36" wire width 3 $1\core_core_xer_in[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_cr_out_ok$next[0:0]$13672 attribute \src "libresoc.v:195617.7-195617.28" wire $1\core_cr_out_ok[0:0] attribute \src "libresoc.v:198228.3-198237.6" wire width 64 $1\core_data_i$12[63:0]$13372 attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $1\core_data_i[63:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $1\core_dec$next[63:0]$13339 attribute \src "libresoc.v:195633.14-195633.45" wire width 64 $1\core_dec[63:0] attribute \src "libresoc.v:198345.3-198354.6" wire width 5 $1\core_dmi__addr[4:0] attribute \src "libresoc.v:198355.3-198364.6" wire $1\core_dmi__ren[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_ea_ok$next[0:0]$13673 attribute \src "libresoc.v:195643.7-195643.24" wire $1\core_ea_ok[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire $1\core_eint$next[0:0]$13340 attribute \src "libresoc.v:195647.7-195647.23" wire $1\core_eint[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_fasto1_ok$next[0:0]$13674 attribute \src "libresoc.v:195651.7-195651.28" wire $1\core_fasto1_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_fasto2_ok$next[0:0]$13675 attribute \src "libresoc.v:195655.7-195655.28" wire $1\core_fasto2_ok[0:0] attribute \src "libresoc.v:198394.3-198403.6" wire width 8 $1\core_full_rd2__ren[7:0] attribute \src "libresoc.v:198433.3-198442.6" wire width 3 $1\core_full_rd__ren[2:0] attribute \src "libresoc.v:198553.3-198575.6" wire width 3 $1\core_issue__addr$13[2:0]$13412 attribute \src "libresoc.v:198472.3-198490.6" wire width 3 $1\core_issue__addr[2:0] attribute \src "libresoc.v:198599.3-198621.6" wire width 64 $1\core_issue__data_i[63:0] attribute \src "libresoc.v:198491.3-198509.6" wire $1\core_issue__ren[0:0] attribute \src "libresoc.v:198576.3-198598.6" wire $1\core_issue__wen[0:0] attribute \src "libresoc.v:198274.3-198289.6" wire $1\core_issue_i[0:0] attribute \src "libresoc.v:198249.3-198273.6" wire $1\core_ivalid_i[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $1\core_msr$next[63:0]$13341 attribute \src "libresoc.v:195683.14-195683.45" wire width 64 $1\core_msr[63:0] attribute \src "libresoc.v:198926.3-198941.6" wire width 3 $1\core_msr__ren[2:0] attribute \src "libresoc.v:197982.3-198017.6" wire width 32 $1\core_raw_insn_i$next[31:0]$13354 attribute \src "libresoc.v:195691.14-195691.37" wire width 32 $1\core_raw_insn_i[31:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_rego_ok$next[0:0]$13676 attribute \src "libresoc.v:195695.7-195695.26" wire $1\core_rego_ok[0:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_spro_ok$next[0:0]$13677 attribute \src "libresoc.v:195699.7-195699.26" wire $1\core_spro_ok[0:0] attribute \src "libresoc.v:199525.3-199579.6" wire $1\core_stopped_i[0:0] attribute \src "libresoc.v:198737.3-198749.6" wire width 3 $1\core_sv__ren[2:0] attribute \src "libresoc.v:198054.3-198089.6" wire $1\core_sv_a_nz$next[0:0]$13362 attribute \src "libresoc.v:195711.7-195711.26" wire $1\core_sv_a_nz[0:0] attribute \src "libresoc.v:198218.3-198227.6" wire width 3 $1\core_wen$11[2:0]$13369 attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $1\core_wen[2:0] attribute \src "libresoc.v:200001.3-200122.6" wire $1\core_xer_out$next[0:0]$13678 attribute \src "libresoc.v:195721.7-195721.26" wire $1\core_xer_out[0:0] attribute \src "libresoc.v:195727.7-195727.30" wire $1\cu_st__rel_o_dly[0:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $1\cur_cur_dststep$next[6:0]$13458 attribute \src "libresoc.v:195733.13-195733.36" wire width 7 $1\cur_cur_dststep[6:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $1\cur_cur_maxvl$next[6:0]$13459 attribute \src "libresoc.v:195737.13-195737.34" wire width 7 $1\cur_cur_maxvl[6:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $1\cur_cur_srcstep$next[6:0]$13460 attribute \src "libresoc.v:195741.13-195741.36" wire width 7 $1\cur_cur_srcstep[6:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $1\cur_cur_subvl$next[1:0]$13461 attribute \src "libresoc.v:195745.13-195745.33" wire width 2 $1\cur_cur_subvl[1:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $1\cur_cur_svstep$next[1:0]$13462 attribute \src "libresoc.v:195749.13-195749.34" wire width 2 $1\cur_cur_svstep[1:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $1\cur_cur_vl$next[6:0]$13463 attribute \src "libresoc.v:195753.13-195753.31" wire width 7 $1\cur_cur_vl[6:0] attribute \src "libresoc.v:198404.3-198412.6" wire $1\d_cr_delay$next[0:0]$13394 attribute \src "libresoc.v:195757.7-195757.24" wire $1\d_cr_delay[0:0] attribute \src "libresoc.v:198365.3-198373.6" wire $1\d_reg_delay$next[0:0]$13388 attribute \src "libresoc.v:195761.7-195761.25" wire $1\d_reg_delay[0:0] attribute \src "libresoc.v:198443.3-198451.6" wire $1\d_xer_delay$next[0:0]$13400 attribute \src "libresoc.v:195765.7-195765.25" wire $1\d_xer_delay[0:0] attribute \src "libresoc.v:199580.3-199634.6" wire $1\dbg_core_stopped_i[0:0] attribute \src "libresoc.v:198423.3-198432.6" wire $1\dbg_d_cr_ack[0:0] attribute \src "libresoc.v:198413.3-198422.6" wire width 64 $1\dbg_d_cr_data[63:0] attribute \src "libresoc.v:198384.3-198393.6" wire $1\dbg_d_gpr_ack[0:0] attribute \src "libresoc.v:198374.3-198383.6" wire width 64 $1\dbg_d_gpr_data[63:0] attribute \src "libresoc.v:198462.3-198471.6" wire $1\dbg_d_xer_ack[0:0] attribute \src "libresoc.v:198452.3-198461.6" wire width 64 $1\dbg_d_xer_data[63:0] attribute \src "libresoc.v:197908.3-197916.6" wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13317 attribute \src "libresoc.v:195813.13-195813.34" wire width 4 $1\dbg_dmi_addr_i[3:0] attribute \src "libresoc.v:198942.3-198950.6" wire width 64 $1\dbg_dmi_din$next[63:0]$13438 attribute \src "libresoc.v:195817.14-195817.48" wire width 64 $1\dbg_dmi_din[63:0] attribute \src "libresoc.v:197917.3-197925.6" wire $1\dbg_dmi_req_i$next[0:0]$13320 attribute \src "libresoc.v:195823.7-195823.27" wire $1\dbg_dmi_req_i[0:0] attribute \src "libresoc.v:198665.3-198673.6" wire $1\dbg_dmi_we_i$next[0:0]$13422 attribute \src "libresoc.v:195827.7-195827.26" wire $1\dbg_dmi_we_i[0:0] attribute \src "libresoc.v:198622.3-198641.6" wire width 64 $1\dec2_cur_dec$next[63:0]$13417 attribute \src "libresoc.v:195881.14-195881.49" wire width 64 $1\dec2_cur_dec[63:0] attribute \src "libresoc.v:200123.3-200131.6" wire $1\dec2_cur_eint$next[0:0]$13708 attribute \src "libresoc.v:195885.7-195885.27" wire $1\dec2_cur_eint[0:0] attribute \src "libresoc.v:199208.3-199232.6" wire width 64 $1\dec2_cur_msr$next[63:0]$13501 attribute \src "libresoc.v:195889.14-195889.49" wire width 64 $1\dec2_cur_msr[63:0] attribute \src "libresoc.v:199055.3-199075.6" wire width 64 $1\dec2_cur_pc$next[63:0]$13448 attribute \src "libresoc.v:195893.14-195893.48" wire width 64 $1\dec2_cur_pc[63:0] attribute \src "libresoc.v:199256.3-199290.6" wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13510 attribute \src "libresoc.v:196045.14-196045.40" wire width 32 $1\dec2_raw_opcode_in[31:0] attribute \src "libresoc.v:200132.3-200141.6" wire width 2 $1\delay$next[1:0]$13711 attribute \src "libresoc.v:196315.13-196315.25" wire width 2 $1\delay[1:0] attribute \src "libresoc.v:198290.3-198324.6" wire $1\exec_fsm_state$next[0:0]$13378 attribute \src "libresoc.v:196331.7-196331.28" wire $1\exec_fsm_state[0:0] attribute \src "libresoc.v:198238.3-198248.6" wire $1\exec_insn_ready_o[0:0] attribute \src "libresoc.v:198090.3-198124.6" wire $1\exec_insn_valid_i[0:0] attribute \src "libresoc.v:198125.3-198168.6" wire $1\exec_pc_ready_i[0:0] attribute \src "libresoc.v:198325.3-198344.6" wire $1\exec_pc_valid_o[0:0] attribute \src "libresoc.v:199154.3-199207.6" wire width 2 $1\fetch_fsm_state$next[1:0]$13493 attribute \src "libresoc.v:196343.13-196343.35" wire width 2 $1\fetch_fsm_state[1:0] attribute \src "libresoc.v:199898.3-199912.6" wire $1\fetch_insn_ready_i[0:0] attribute \src "libresoc.v:199291.3-199313.6" wire $1\fetch_insn_valid_o[0:0] attribute \src "libresoc.v:198951.3-198961.6" wire $1\fetch_pc_ready_o[0:0] attribute \src "libresoc.v:199401.3-199416.6" wire $1\fetch_pc_valid_i[0:0] attribute \src "libresoc.v:198510.3-198537.6" wire width 2 $1\fsm_state$next[1:0]$13407 attribute \src "libresoc.v:196355.13-196355.29" wire width 2 $1\fsm_state[1:0] attribute \src "libresoc.v:198962.3-198977.6" wire width 48 $1\imem_a_pc_i[47:0] attribute \src "libresoc.v:198987.3-199020.6" wire $1\imem_a_valid_i[0:0] attribute \src "libresoc.v:199021.3-199054.6" wire $1\imem_f_valid_i[0:0] attribute \src "libresoc.v:199913.3-199958.6" wire $1\insn_done[0:0] attribute \src "libresoc.v:198169.3-198217.6" wire $1\is_last[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $1\issue_fsm_state$next[2:0]$13518 attribute \src "libresoc.v:196615.13-196615.35" wire width 3 $1\issue_fsm_state[2:0] attribute \src "libresoc.v:198978.3-198986.6" wire $1\jtag_dmi0__ack_o$next[0:0]$13443 attribute \src "libresoc.v:196619.7-196619.30" wire $1\jtag_dmi0__ack_o[0:0] attribute \src "libresoc.v:199145.3-199153.6" wire width 64 $1\jtag_dmi0__dout$next[63:0]$13490 attribute \src "libresoc.v:196627.14-196627.52" wire width 64 $1\jtag_dmi0__dout[63:0] attribute \src "libresoc.v:199115.3-199144.6" wire $1\msr_read$next[0:0]$13484 attribute \src "libresoc.v:196667.7-196667.22" wire $1\msr_read[0:0] attribute \src "libresoc.v:198538.3-198552.6" wire width 64 $1\new_dec[63:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_maxvl[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $1\new_svstate_subvl[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $1\new_svstate_svstep[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $1\new_svstate_vl[6:0] attribute \src "libresoc.v:198642.3-198664.6" wire width 64 $1\new_tb[63:0] attribute \src "libresoc.v:199233.3-199255.6" wire width 64 $1\nia$next[63:0]$13506 attribute \src "libresoc.v:196707.14-196707.40" wire width 64 $1\nia[63:0] attribute \src "libresoc.v:198683.3-198698.6" wire width 64 $1\pc[63:0] attribute \src "libresoc.v:199635.3-199725.6" wire $1\pc_changed$next[0:0]$13535 attribute \src "libresoc.v:196713.7-196713.24" wire $1\pc_changed[0:0] attribute \src "libresoc.v:198674.3-198682.6" wire $1\pc_ok_delay$next[0:0]$13425 attribute \src "libresoc.v:196723.7-196723.25" wire $1\pc_ok_delay[0:0] attribute \src "libresoc.v:199959.3-199977.6" wire $1\pred_insn_valid_i[0:0] attribute \src "libresoc.v:199978.3-200000.6" wire $1\pred_mask_ready_i[0:0] attribute \src "libresoc.v:199807.3-199897.6" wire $1\sv_changed$next[0:0]$13547 attribute \src "libresoc.v:197023.7-197023.24" wire $1\sv_changed[0:0] attribute \src "libresoc.v:198721.3-198736.6" wire width 64 $1\svstate[63:0] attribute \src "libresoc.v:198712.3-198720.6" wire $1\svstate_ok_delay$next[0:0]$13430 attribute \src "libresoc.v:197033.7-197033.30" wire $1\svstate_ok_delay[0:0] attribute \src "libresoc.v:199726.3-199806.6" wire $1\update_svstate[0:0] attribute \src "libresoc.v:198018.3-198053.6" wire $2\core_bigendian_i$10$next[0:0]$13359 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_cr_rd_ok$next[0:0]$13679 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$3$next[0:0]$13680 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$4$next[0:0]$13681 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$5$next[0:0]$13682 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$6$next[0:0]$13683 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$7$next[0:0]$13684 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$8$next[0:0]$13685 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$9$next[0:0]$13686 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_exc_$signal$next[0:0]$13687 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_oe_ok$next[0:0]$13688 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_core_rc_ok$next[0:0]$13689 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_cr_in1_ok$next[0:0]$13690 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_cr_in2_ok$2$next[0:0]$13691 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_cr_in2_ok$next[0:0]$13692 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_cr_wr_ok$next[0:0]$13693 attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $2\core_core_dststep$next[6:0]$13342 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_fast1_ok$next[0:0]$13694 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_fast2_ok$next[0:0]$13695 attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $2\core_core_maxvl$next[6:0]$13343 attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $2\core_core_pc$next[63:0]$13344 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_reg1_ok$next[0:0]$13696 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_reg2_ok$next[0:0]$13697 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_reg3_ok$next[0:0]$13698 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_core_spr1_ok$next[0:0]$13699 attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $2\core_core_srcstep$next[6:0]$13345 attribute \src "libresoc.v:197926.3-197981.6" wire width 2 $2\core_core_subvl$next[1:0]$13346 attribute \src "libresoc.v:197926.3-197981.6" wire width 2 $2\core_core_svstep$next[1:0]$13347 attribute \src "libresoc.v:197926.3-197981.6" wire width 7 $2\core_core_vl$next[6:0]$13348 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_cr_out_ok$next[0:0]$13700 attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $2\core_data_i[63:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $2\core_dec$next[63:0]$13349 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_ea_ok$next[0:0]$13701 attribute \src "libresoc.v:197926.3-197981.6" wire $2\core_eint$next[0:0]$13350 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_fasto1_ok$next[0:0]$13702 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_fasto2_ok$next[0:0]$13703 attribute \src "libresoc.v:198274.3-198289.6" wire $2\core_issue_i[0:0] attribute \src "libresoc.v:198249.3-198273.6" wire $2\core_ivalid_i[0:0] attribute \src "libresoc.v:197926.3-197981.6" wire width 64 $2\core_msr$next[63:0]$13351 attribute \src "libresoc.v:198926.3-198941.6" wire width 3 $2\core_msr__ren[2:0] attribute \src "libresoc.v:197982.3-198017.6" wire width 32 $2\core_raw_insn_i$next[31:0]$13355 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_rego_ok$next[0:0]$13704 attribute \src "libresoc.v:200001.3-200122.6" wire $2\core_spro_ok$next[0:0]$13705 attribute \src "libresoc.v:199525.3-199579.6" wire $2\core_stopped_i[0:0] attribute \src "libresoc.v:198054.3-198089.6" wire $2\core_sv_a_nz$next[0:0]$13363 attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $2\core_wen[2:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $2\cur_cur_dststep$next[6:0]$13464 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $2\cur_cur_maxvl$next[6:0]$13465 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $2\cur_cur_srcstep$next[6:0]$13466 attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $2\cur_cur_subvl$next[1:0]$13467 attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $2\cur_cur_svstep$next[1:0]$13468 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $2\cur_cur_vl$next[6:0]$13469 attribute \src "libresoc.v:199580.3-199634.6" wire $2\dbg_core_stopped_i[0:0] attribute \src "libresoc.v:198622.3-198641.6" wire width 64 $2\dec2_cur_dec$next[63:0]$13418 attribute \src "libresoc.v:199208.3-199232.6" wire width 64 $2\dec2_cur_msr$next[63:0]$13502 attribute \src "libresoc.v:199055.3-199075.6" wire width 64 $2\dec2_cur_pc$next[63:0]$13449 attribute \src "libresoc.v:199256.3-199290.6" wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13511 attribute \src "libresoc.v:198290.3-198324.6" wire $2\exec_fsm_state$next[0:0]$13379 attribute \src "libresoc.v:198125.3-198168.6" wire $2\exec_pc_ready_i[0:0] attribute \src "libresoc.v:198325.3-198344.6" wire $2\exec_pc_valid_o[0:0] attribute \src "libresoc.v:199154.3-199207.6" wire width 2 $2\fetch_fsm_state$next[1:0]$13494 attribute \src "libresoc.v:199401.3-199416.6" wire $2\fetch_pc_valid_i[0:0] attribute \src "libresoc.v:198510.3-198537.6" wire width 2 $2\fsm_state$next[1:0]$13408 attribute \src "libresoc.v:198962.3-198977.6" wire width 48 $2\imem_a_pc_i[47:0] attribute \src "libresoc.v:198987.3-199020.6" wire $2\imem_a_valid_i[0:0] attribute \src "libresoc.v:199021.3-199054.6" wire $2\imem_f_valid_i[0:0] attribute \src "libresoc.v:199913.3-199958.6" wire $2\insn_done[0:0] attribute \src "libresoc.v:198169.3-198217.6" wire $2\is_last[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $2\issue_fsm_state$next[2:0]$13519 attribute \src "libresoc.v:199115.3-199144.6" wire $2\msr_read$next[0:0]$13485 attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_maxvl[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $2\new_svstate_subvl[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $2\new_svstate_svstep[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $2\new_svstate_vl[6:0] attribute \src "libresoc.v:199233.3-199255.6" wire width 64 $2\nia$next[63:0]$13507 attribute \src "libresoc.v:198683.3-198698.6" wire width 64 $2\pc[63:0] attribute \src "libresoc.v:199635.3-199725.6" wire $2\pc_changed$next[0:0]$13536 attribute \src "libresoc.v:199807.3-199897.6" wire $2\sv_changed$next[0:0]$13548 attribute \src "libresoc.v:198721.3-198736.6" wire width 64 $2\svstate[63:0] attribute \src "libresoc.v:199726.3-199806.6" wire $2\update_svstate[0:0] attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $3\core_data_i[63:0] attribute \src "libresoc.v:198249.3-198273.6" wire $3\core_ivalid_i[0:0] attribute \src "libresoc.v:199525.3-199579.6" wire $3\core_stopped_i[0:0] attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $3\core_wen[2:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $3\cur_cur_dststep$next[6:0]$13470 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $3\cur_cur_maxvl$next[6:0]$13471 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $3\cur_cur_srcstep$next[6:0]$13472 attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $3\cur_cur_subvl$next[1:0]$13473 attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $3\cur_cur_svstep$next[1:0]$13474 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $3\cur_cur_vl$next[6:0]$13475 attribute \src "libresoc.v:199580.3-199634.6" wire $3\dbg_core_stopped_i[0:0] attribute \src "libresoc.v:199208.3-199232.6" wire width 64 $3\dec2_cur_msr$next[63:0]$13503 attribute \src "libresoc.v:199055.3-199075.6" wire width 64 $3\dec2_cur_pc$next[63:0]$13450 attribute \src "libresoc.v:199256.3-199290.6" wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13512 attribute \src "libresoc.v:198290.3-198324.6" wire $3\exec_fsm_state$next[0:0]$13380 attribute \src "libresoc.v:199154.3-199207.6" wire width 2 $3\fetch_fsm_state$next[1:0]$13495 attribute \src "libresoc.v:198987.3-199020.6" wire $3\imem_a_valid_i[0:0] attribute \src "libresoc.v:199021.3-199054.6" wire $3\imem_f_valid_i[0:0] attribute \src "libresoc.v:199913.3-199958.6" wire $3\insn_done[0:0] attribute \src "libresoc.v:198169.3-198217.6" wire $3\is_last[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $3\issue_fsm_state$next[2:0]$13520 attribute \src "libresoc.v:199115.3-199144.6" wire $3\msr_read$next[0:0]$13486 attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_maxvl[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $3\new_svstate_subvl[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $3\new_svstate_svstep[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $3\new_svstate_vl[6:0] attribute \src "libresoc.v:199635.3-199725.6" wire $3\pc_changed$next[0:0]$13537 attribute \src "libresoc.v:199807.3-199897.6" wire $3\sv_changed$next[0:0]$13549 attribute \src "libresoc.v:199726.3-199806.6" wire $3\update_svstate[0:0] attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $4\core_data_i[63:0] attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $4\core_wen[2:0] attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $4\cur_cur_dststep$next[6:0]$13476 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $4\cur_cur_maxvl$next[6:0]$13477 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $4\cur_cur_srcstep$next[6:0]$13478 attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $4\cur_cur_subvl$next[1:0]$13479 attribute \src "libresoc.v:199076.3-199114.6" wire width 2 $4\cur_cur_svstep$next[1:0]$13480 attribute \src "libresoc.v:199076.3-199114.6" wire width 7 $4\cur_cur_vl$next[6:0]$13481 attribute \src "libresoc.v:198290.3-198324.6" wire $4\exec_fsm_state$next[0:0]$13381 attribute \src "libresoc.v:199154.3-199207.6" wire width 2 $4\fetch_fsm_state$next[1:0]$13496 attribute \src "libresoc.v:198987.3-199020.6" wire $4\imem_a_valid_i[0:0] attribute \src "libresoc.v:199021.3-199054.6" wire $4\imem_f_valid_i[0:0] attribute \src "libresoc.v:199913.3-199958.6" wire $4\insn_done[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $4\issue_fsm_state$next[2:0]$13521 attribute \src "libresoc.v:199115.3-199144.6" wire $4\msr_read$next[0:0]$13487 attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_maxvl[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $4\new_svstate_subvl[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $4\new_svstate_svstep[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $4\new_svstate_vl[6:0] attribute \src "libresoc.v:199635.3-199725.6" wire $4\pc_changed$next[0:0]$13538 attribute \src "libresoc.v:199807.3-199897.6" wire $4\sv_changed$next[0:0]$13550 attribute \src "libresoc.v:199726.3-199806.6" wire $4\update_svstate[0:0] attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $5\core_data_i[63:0] attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $5\core_wen[2:0] attribute \src "libresoc.v:198290.3-198324.6" wire $5\exec_fsm_state$next[0:0]$13382 attribute \src "libresoc.v:199154.3-199207.6" wire width 2 $5\fetch_fsm_state$next[1:0]$13497 attribute \src "libresoc.v:199913.3-199958.6" wire $5\insn_done[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $5\issue_fsm_state$next[2:0]$13522 attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_maxvl[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $5\new_svstate_subvl[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 2 $5\new_svstate_svstep[1:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $5\new_svstate_vl[6:0] attribute \src "libresoc.v:199635.3-199725.6" wire $5\pc_changed$next[0:0]$13539 attribute \src "libresoc.v:199807.3-199897.6" wire $5\sv_changed$next[0:0]$13551 attribute \src "libresoc.v:199726.3-199806.6" wire $5\update_svstate[0:0] attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $6\core_data_i[63:0] attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $6\core_wen[2:0] attribute \src "libresoc.v:199154.3-199207.6" wire width 2 $6\fetch_fsm_state$next[1:0]$13498 attribute \src "libresoc.v:199913.3-199958.6" wire $6\insn_done[0:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $6\issue_fsm_state$next[2:0]$13523 attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $6\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $6\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199635.3-199725.6" wire $6\pc_changed$next[0:0]$13540 attribute \src "libresoc.v:199807.3-199897.6" wire $6\sv_changed$next[0:0]$13552 attribute \src "libresoc.v:199726.3-199806.6" wire $6\update_svstate[0:0] attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $7\core_data_i[63:0] attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $7\core_wen[2:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $7\issue_fsm_state$next[2:0]$13524 attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $7\new_svstate_dststep[6:0] attribute \src "libresoc.v:199314.3-199400.6" wire width 7 $7\new_svstate_srcstep[6:0] attribute \src "libresoc.v:199635.3-199725.6" wire $7\pc_changed$next[0:0]$13541 attribute \src "libresoc.v:199807.3-199897.6" wire $7\sv_changed$next[0:0]$13553 attribute \src "libresoc.v:199726.3-199806.6" wire $7\update_svstate[0:0] attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $8\core_data_i[63:0] attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $8\core_wen[2:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $8\issue_fsm_state$next[2:0]$13525 attribute \src "libresoc.v:199635.3-199725.6" wire $8\pc_changed$next[0:0]$13542 attribute \src "libresoc.v:199807.3-199897.6" wire $8\sv_changed$next[0:0]$13554 attribute \src "libresoc.v:198838.3-198925.6" wire width 64 $9\core_data_i[63:0] attribute \src "libresoc.v:198750.3-198837.6" wire width 3 $9\core_wen[2:0] attribute \src "libresoc.v:199417.3-199524.6" wire width 3 $9\issue_fsm_state$next[2:0]$13526 attribute \src "libresoc.v:199635.3-199725.6" wire $9\pc_changed$next[0:0]$13543 attribute \src "libresoc.v:199807.3-199897.6" wire $9\sv_changed$next[0:0]$13555 attribute \src "libresoc.v:197050.19-197050.108" wire width 65 $add$libresoc.v:197050$13081_Y attribute \src "libresoc.v:197062.19-197062.112" wire width 8 $add$libresoc.v:197062$13092_Y attribute \src "libresoc.v:197063.19-197063.112" wire width 8 $add$libresoc.v:197063$13093_Y attribute \src "libresoc.v:197135.19-197135.116" wire width 65 $add$libresoc.v:197135$13165_Y attribute \src "libresoc.v:197168.18-197168.107" wire width 65 $add$libresoc.v:197168$13197_Y attribute \src "libresoc.v:197055.19-197055.104" wire $and$libresoc.v:197055$13086_Y attribute \src "libresoc.v:197058.19-197058.104" wire $and$libresoc.v:197058$13089_Y attribute \src "libresoc.v:197066.19-197066.104" wire $and$libresoc.v:197066$13096_Y attribute \src "libresoc.v:197069.19-197069.104" wire $and$libresoc.v:197069$13099_Y attribute \src "libresoc.v:197071.19-197071.111" wire $and$libresoc.v:197071$13101_Y attribute \src "libresoc.v:197075.19-197075.104" wire $and$libresoc.v:197075$13105_Y attribute \src "libresoc.v:197081.19-197081.104" wire $and$libresoc.v:197081$13110_Y attribute \src "libresoc.v:197084.19-197084.104" wire $and$libresoc.v:197084$13113_Y attribute \src "libresoc.v:197087.19-197087.104" wire $and$libresoc.v:197087$13116_Y attribute \src "libresoc.v:197090.19-197090.104" wire $and$libresoc.v:197090$13119_Y attribute \src "libresoc.v:197093.19-197093.104" wire $and$libresoc.v:197093$13122_Y attribute \src "libresoc.v:197096.19-197096.104" wire $and$libresoc.v:197096$13125_Y attribute \src "libresoc.v:197097.19-197097.115" wire width 3 $and$libresoc.v:197097$13126_Y attribute \src "libresoc.v:197101.19-197101.104" wire $and$libresoc.v:197101$13130_Y attribute \src "libresoc.v:197104.19-197104.104" wire $and$libresoc.v:197104$13133_Y attribute \src "libresoc.v:197110.19-197110.104" wire $and$libresoc.v:197110$13138_Y attribute \src "libresoc.v:197113.19-197113.104" wire $and$libresoc.v:197113$13141_Y attribute \src "libresoc.v:197114.19-197114.115" wire width 3 $and$libresoc.v:197114$13142_Y attribute \src "libresoc.v:197117.19-197117.111" wire $and$libresoc.v:197117$13145_Y attribute \src "libresoc.v:197122.19-197122.104" wire $and$libresoc.v:197122$13150_Y attribute \src "libresoc.v:197125.19-197125.104" wire $and$libresoc.v:197125$13153_Y attribute \src "libresoc.v:197140.18-197140.109" wire $and$libresoc.v:197140$13170_Y attribute \src "libresoc.v:197146.18-197146.101" wire $and$libresoc.v:197146$13177_Y attribute \src "libresoc.v:197148.18-197148.109" wire $and$libresoc.v:197148$13179_Y attribute \src "libresoc.v:197151.18-197151.101" wire $and$libresoc.v:197151$13182_Y attribute \src "libresoc.v:197157.18-197157.101" wire $and$libresoc.v:197157$13187_Y attribute \src "libresoc.v:197159.18-197159.109" wire $and$libresoc.v:197159$13189_Y attribute \src "libresoc.v:197162.18-197162.101" wire $and$libresoc.v:197162$13192_Y attribute \src "libresoc.v:197070.19-197070.108" wire $eq$libresoc.v:197070$13100_Y attribute \src "libresoc.v:197116.19-197116.108" wire $eq$libresoc.v:197116$13144_Y attribute \src "libresoc.v:197126.19-197126.116" wire $eq$libresoc.v:197126$13154_Y attribute \src "libresoc.v:197147.18-197147.107" wire $eq$libresoc.v:197147$13178_Y attribute \src "libresoc.v:197158.18-197158.107" wire $eq$libresoc.v:197158$13188_Y attribute \src "libresoc.v:197131.19-197131.114" wire width 64 $extend$libresoc.v:197131$13159_Y attribute \src "libresoc.v:197132.19-197132.113" wire width 64 $extend$libresoc.v:197132$13161_Y attribute \src "libresoc.v:197143.18-197143.109" wire width 64 $extend$libresoc.v:197143$13173_Y attribute \src "libresoc.v:197051.19-197051.106" wire width 7 $mul$libresoc.v:197051$13082_Y attribute \src "libresoc.v:197169.18-197169.110" wire width 7 $mul$libresoc.v:197169$13198_Y attribute \src "libresoc.v:197119.18-197119.102" wire $ne$libresoc.v:197119$13147_Y attribute \src "libresoc.v:197128.19-197128.123" wire $ne$libresoc.v:197128$13156_Y attribute \src "libresoc.v:197138.18-197138.102" wire $ne$libresoc.v:197138$13168_Y attribute \src "libresoc.v:197053.19-197053.107" wire $not$libresoc.v:197053$13084_Y attribute \src "libresoc.v:197054.19-197054.109" wire $not$libresoc.v:197054$13085_Y attribute \src "libresoc.v:197056.19-197056.107" wire $not$libresoc.v:197056$13087_Y attribute \src "libresoc.v:197057.19-197057.109" wire $not$libresoc.v:197057$13088_Y attribute \src "libresoc.v:197064.19-197064.107" wire $not$libresoc.v:197064$13094_Y attribute \src "libresoc.v:197065.19-197065.109" wire $not$libresoc.v:197065$13095_Y attribute \src "libresoc.v:197067.19-197067.107" wire $not$libresoc.v:197067$13097_Y attribute \src "libresoc.v:197068.19-197068.109" wire $not$libresoc.v:197068$13098_Y attribute \src "libresoc.v:197072.19-197072.105" wire $not$libresoc.v:197072$13102_Y attribute \src "libresoc.v:197073.19-197073.107" wire $not$libresoc.v:197073$13103_Y attribute \src "libresoc.v:197074.19-197074.109" wire $not$libresoc.v:197074$13104_Y attribute \src "libresoc.v:197079.19-197079.107" wire $not$libresoc.v:197079$13108_Y attribute \src "libresoc.v:197080.19-197080.109" wire $not$libresoc.v:197080$13109_Y attribute \src "libresoc.v:197082.19-197082.107" wire $not$libresoc.v:197082$13111_Y attribute \src "libresoc.v:197083.19-197083.109" wire $not$libresoc.v:197083$13112_Y attribute \src "libresoc.v:197085.19-197085.107" wire $not$libresoc.v:197085$13114_Y attribute \src "libresoc.v:197086.19-197086.109" wire $not$libresoc.v:197086$13115_Y attribute \src "libresoc.v:197088.19-197088.107" wire $not$libresoc.v:197088$13117_Y attribute \src "libresoc.v:197089.19-197089.109" wire $not$libresoc.v:197089$13118_Y attribute \src "libresoc.v:197091.19-197091.107" wire $not$libresoc.v:197091$13120_Y attribute \src "libresoc.v:197092.19-197092.109" wire $not$libresoc.v:197092$13121_Y attribute \src "libresoc.v:197094.19-197094.107" wire $not$libresoc.v:197094$13123_Y attribute \src "libresoc.v:197095.19-197095.109" wire $not$libresoc.v:197095$13124_Y attribute \src "libresoc.v:197099.19-197099.107" wire $not$libresoc.v:197099$13128_Y attribute \src "libresoc.v:197100.19-197100.109" wire $not$libresoc.v:197100$13129_Y attribute \src "libresoc.v:197102.19-197102.107" wire $not$libresoc.v:197102$13131_Y attribute \src "libresoc.v:197103.19-197103.109" wire $not$libresoc.v:197103$13132_Y attribute \src "libresoc.v:197108.19-197108.107" wire $not$libresoc.v:197108$13136_Y attribute \src "libresoc.v:197109.19-197109.109" wire $not$libresoc.v:197109$13137_Y attribute \src "libresoc.v:197111.19-197111.107" wire $not$libresoc.v:197111$13139_Y attribute \src "libresoc.v:197112.19-197112.109" wire $not$libresoc.v:197112$13140_Y attribute \src "libresoc.v:197118.19-197118.107" wire $not$libresoc.v:197118$13146_Y attribute \src "libresoc.v:197120.19-197120.107" wire $not$libresoc.v:197120$13148_Y attribute \src "libresoc.v:197121.19-197121.109" wire $not$libresoc.v:197121$13149_Y attribute \src "libresoc.v:197123.19-197123.107" wire $not$libresoc.v:197123$13151_Y attribute \src "libresoc.v:197124.19-197124.109" wire $not$libresoc.v:197124$13152_Y attribute \src "libresoc.v:197129.19-197129.107" wire $not$libresoc.v:197129$13157_Y attribute \src "libresoc.v:197130.19-197130.107" wire $not$libresoc.v:197130$13158_Y attribute \src "libresoc.v:197139.18-197139.103" wire $not$libresoc.v:197139$13169_Y attribute \src "libresoc.v:197141.18-197141.97" wire $not$libresoc.v:197141$13171_Y attribute \src "libresoc.v:197142.18-197142.102" wire $not$libresoc.v:197142$13172_Y attribute \src "libresoc.v:197144.18-197144.106" wire $not$libresoc.v:197144$13175_Y attribute \src "libresoc.v:197145.18-197145.108" wire $not$libresoc.v:197145$13176_Y attribute \src "libresoc.v:197149.18-197149.106" wire $not$libresoc.v:197149$13180_Y attribute \src "libresoc.v:197150.18-197150.108" wire $not$libresoc.v:197150$13181_Y attribute \src "libresoc.v:197155.18-197155.106" wire $not$libresoc.v:197155$13185_Y attribute \src "libresoc.v:197156.18-197156.108" wire $not$libresoc.v:197156$13186_Y attribute \src "libresoc.v:197160.18-197160.106" wire $not$libresoc.v:197160$13190_Y attribute \src "libresoc.v:197161.18-197161.108" wire $not$libresoc.v:197161$13191_Y attribute \src "libresoc.v:197166.18-197166.99" wire $not$libresoc.v:197166$13195_Y attribute \src "libresoc.v:197167.18-197167.99" wire $not$libresoc.v:197167$13196_Y attribute \src "libresoc.v:197059.19-197059.113" wire $or$libresoc.v:197059$13090_Y attribute \src "libresoc.v:197061.19-197061.106" wire $or$libresoc.v:197061$13091_Y attribute \src "libresoc.v:197076.19-197076.113" wire $or$libresoc.v:197076$13106_Y attribute \src "libresoc.v:197078.19-197078.106" wire $or$libresoc.v:197078$13107_Y attribute \src "libresoc.v:197105.19-197105.113" wire $or$libresoc.v:197105$13134_Y attribute \src "libresoc.v:197107.19-197107.106" wire $or$libresoc.v:197107$13135_Y attribute \src "libresoc.v:197136.18-197136.110" wire $or$libresoc.v:197136$13166_Y attribute \src "libresoc.v:197137.18-197137.100" wire $or$libresoc.v:197137$13167_Y attribute \src "libresoc.v:197152.18-197152.112" wire $or$libresoc.v:197152$13183_Y attribute \src "libresoc.v:197154.18-197154.104" wire $or$libresoc.v:197154$13184_Y attribute \src "libresoc.v:197163.18-197163.112" wire $or$libresoc.v:197163$13193_Y attribute \src "libresoc.v:197165.18-197165.104" wire $or$libresoc.v:197165$13194_Y attribute \src "libresoc.v:197127.19-197127.211" wire width 64 $pos$libresoc.v:197127$13155_Y attribute \src "libresoc.v:197131.19-197131.114" wire width 64 $pos$libresoc.v:197131$13160_Y attribute \src "libresoc.v:197132.19-197132.113" wire width 64 $pos$libresoc.v:197132$13162_Y attribute \src "libresoc.v:197143.18-197143.109" wire width 64 $pos$libresoc.v:197143$13174_Y attribute \src "libresoc.v:197098.19-197098.93" wire $reduce_or$libresoc.v:197098$13127_Y attribute \src "libresoc.v:197115.19-197115.93" wire $reduce_or$libresoc.v:197115$13143_Y attribute \src "libresoc.v:197052.18-197052.41" wire width 64 $shr$libresoc.v:197052$13083_Y attribute \src "libresoc.v:197170.18-197170.40" wire width 64 $shr$libresoc.v:197170$13199_Y attribute \src "libresoc.v:197133.19-197133.116" wire width 65 $sub$libresoc.v:197133$13163_Y attribute \src "libresoc.v:197134.18-197134.101" wire width 3 $sub$libresoc.v:197134$13164_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" wire width 65 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" wire width 65 \$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523" wire width 8 \$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523" wire width 8 \$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:524" wire width 8 \$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:524" wire width 8 \$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" wire \$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$188 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$194 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$196 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" wire width 3 \$197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$200 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$202 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$206 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$208 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$210 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$212 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$216 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$218 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$220 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$222 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$224 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$226 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$230 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:765" wire width 3 \$231 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$234 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$236 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" wire \$238 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$240 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$242 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$244 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$246 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$248 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831" wire width 3 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" wire \$252 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$254 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:762" wire \$256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" wire \$258 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831" wire width 3 \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" wire \$260 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$262 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$264 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1040" wire width 65 \$266 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1040" wire width 65 \$267 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1056" wire width 65 \$269 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1056" wire width 65 \$270 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" wire \$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" wire \$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" wire \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" wire \$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" wire \$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" wire \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" wire \$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" wire \$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" wire width 65 \$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" wire width 65 \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" wire width 32 \$95 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" wire width 7 \$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" wire width 32 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 294 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 154 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire output 285 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 295 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" wire output 3 \busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 1 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \core_asmcode$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_bigendian_i$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_bigendian_i$10$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_cia__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \core_core_core_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \core_core_core_cia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_rd$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_cr_rd_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \core_core_core_cr_wr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \core_core_core_exc_$signal$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \core_core_core_fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \core_core_core_fn_unit$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \core_core_core_input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \core_core_core_input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \core_core_core_insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \core_core_core_insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \core_core_core_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \core_core_core_insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \core_core_core_is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \core_core_core_is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \core_core_core_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \core_core_core_msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_oe_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_core_rc_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \core_core_core_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \core_core_core_trapaddr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \core_core_core_traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \core_core_core_traptype$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2$1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_in2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok$2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_in2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_cr_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_cr_wr_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \core_core_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \core_core_dststep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_ea$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fast2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_fast2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \core_core_fasto2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \core_core_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \core_core_lk$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \core_core_maxvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \core_core_maxvl$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \core_core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \core_core_pc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_reg3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_reg3_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \core_core_rego$next attribute \enum_base_type "SPR" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spr1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_core_spr1_ok$next attribute \enum_base_type "SPR" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \core_core_spro$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \core_core_srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \core_core_srcstep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" wire width 2 \core_core_subvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" wire width 2 \core_core_subvl$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \core_core_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \core_core_svstep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire \core_core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \core_core_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \core_core_vl$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \core_core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" wire \core_corebusy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_cr_out_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire \core_cu_ad__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire \core_cu_ad__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire \core_cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire \core_cu_st__rel_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_data_i$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \core_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \core_dec$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \core_dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_dmi__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_ea_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_fasto2_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 32 \core_full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \core_full_rd2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 6 \core_full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_issue__addr$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_issue__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \core_issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" wire \core_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" wire \core_ivalid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_msr__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 \core_raw_insn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" wire width 32 \core_raw_insn_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_rego_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_rego_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \core_spro_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_state_nia_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" wire \core_stopped_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_sv__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" wire \core_sv_a_nz$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \core_wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_wen$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \core_xer_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 312 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \cu_st__rel_o_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \cur_cur_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \cur_cur_dststep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \cur_cur_maxvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \cur_cur_maxvl$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \cur_cur_srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \cur_cur_srcstep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" wire width 2 \cur_cur_subvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" wire width 2 \cur_cur_subvl$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \cur_cur_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \cur_cur_svstep$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:995" wire \d_cr_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:995" wire \d_cr_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:985" wire \d_reg_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:985" wire \d_reg_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005" wire \d_xer_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1005" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \dbg_core_dbg_core_dbg_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \dbg_core_dbg_core_dbg_maxvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \dbg_core_dbg_core_dbg_srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" wire width 2 \dbg_core_dbg_core_dbg_subvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \dbg_core_dbg_core_dbg_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \dbg_core_dbg_core_dbg_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dbg_core_dbg_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dbg_core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" wire \dbg_core_rst_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" wire \dbg_core_stop_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" wire \dbg_core_stopped_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire \dbg_d_cr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 \dbg_d_cr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire \dbg_d_cr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire \dbg_d_gpr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" wire width 7 \dbg_d_gpr_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 \dbg_d_gpr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire \dbg_d_gpr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" wire \dbg_d_xer_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" wire width 64 \dbg_d_xer_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" wire \dbg_d_xer_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" wire \dbg_dmi_ack_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" wire width 4 \dbg_dmi_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" wire width 4 \dbg_dmi_addr_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" wire width 64 \dbg_dmi_din attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" wire width 64 \dbg_dmi_din$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" wire width 64 \dbg_dmi_dout attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" wire \dbg_dmi_req_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" wire \dbg_dmi_req_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire \dbg_dmi_we_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" wire \dbg_dmi_we_i$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" wire \dbg_terminate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 9 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 45 output 14 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 8 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 input 13 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 output 16 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 10 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 8 output 12 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 11 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire output 15 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" wire width 8 \dec2_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire \dec2_bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" wire width 64 \dec2_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_in2$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_in2_ok$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec2_cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 8 \dec2_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \dec2_cur_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \dec2_cur_dec$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \dec2_cur_eint attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \dec2_cur_eint$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dec2_cur_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dec2_cur_msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dec2_cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dec2_cur_pc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 3 \dec2_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire width 14 \dec2_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" wire width 2 \dec2_input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 32 \dec2_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 7 \dec2_insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" wire \dec2_is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" wire \dec2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \dec2_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 \dec2_raw_opcode_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 7 \dec2_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_rego_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec2_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" attribute \enum_value_0000001000 "LR" attribute \enum_value_0000001001 "CTR" attribute \enum_value_0000001101 "AMR" attribute \enum_value_0000010001 "DSCR_priv" attribute \enum_value_0000010010 "DSISR" attribute \enum_value_0000010011 "DAR" attribute \enum_value_0000010110 "DEC" attribute \enum_value_0000011010 "SRR0" attribute \enum_value_0000011011 "SRR1" attribute \enum_value_0000011100 "CFAR" attribute \enum_value_0000011101 "AMR_priv" attribute \enum_value_0000110000 "PIDR" attribute \enum_value_0000111101 "IAMR" attribute \enum_value_0010000000 "TFHAR" attribute \enum_value_0010000001 "TFIAR" attribute \enum_value_0010000010 "TEXASR" attribute \enum_value_0010000011 "TEXASRU" attribute \enum_value_0010001000 "CTRL" attribute \enum_value_0010010000 "TIDR" attribute \enum_value_0010011000 "CTRL_priv" attribute \enum_value_0010011001 "FSCR" attribute \enum_value_0010011101 "UAMOR" attribute \enum_value_0010011110 "GSR" attribute \enum_value_0010011111 "PSPB" attribute \enum_value_0010110000 "DPDES" attribute \enum_value_0010110100 "DAWR0" attribute \enum_value_0010111010 "RPR" attribute \enum_value_0010111011 "CIABR" attribute \enum_value_0010111100 "DAWRX0" attribute \enum_value_0010111110 "HFSCR" attribute \enum_value_0100000000 "VRSAVE" attribute \enum_value_0100000011 "SPRG3" attribute \enum_value_0100001100 "TB" attribute \enum_value_0100001101 "TBU" attribute \enum_value_0100010000 "SPRG0_priv" attribute \enum_value_0100010001 "SPRG1_priv" attribute \enum_value_0100010010 "SPRG2_priv" attribute \enum_value_0100010011 "SPRG3_priv" attribute \enum_value_0100011011 "CIR" attribute \enum_value_0100011100 "TBL" attribute \enum_value_0100011101 "TBU_hypv" attribute \enum_value_0100011110 "TBU40" attribute \enum_value_0100011111 "PVR" attribute \enum_value_0100110000 "HSPRG0" attribute \enum_value_0100110001 "HSPRG1" attribute \enum_value_0100110010 "HDSISR" attribute \enum_value_0100110011 "HDAR" attribute \enum_value_0100110100 "SPURR" attribute \enum_value_0100110101 "PURR" attribute \enum_value_0100110110 "HDEC" attribute \enum_value_0100111001 "HRMOR" attribute \enum_value_0100111010 "HSRR0" attribute \enum_value_0100111011 "HSRR1" attribute \enum_value_0100111110 "LPCR" attribute \enum_value_0100111111 "LPIDR" attribute \enum_value_0101010000 "HMER" attribute \enum_value_0101010001 "HMEER" attribute \enum_value_0101010010 "PCR" attribute \enum_value_0101010011 "HEIR" attribute \enum_value_0101011101 "AMOR" attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" attribute \enum_value_1011010000 "PRTBL" attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" attribute \enum_value_1100000011 "PMC1" attribute \enum_value_1100000100 "PMC2" attribute \enum_value_1100000101 "PMC3" attribute \enum_value_1100000110 "PMC4" attribute \enum_value_1100000111 "PMC5" attribute \enum_value_1100001000 "PMC6" attribute \enum_value_1100001011 "MMCR0" attribute \enum_value_1100001100 "SIAR" attribute \enum_value_1100001101 "SDAR" attribute \enum_value_1100001110 "MMCR1" attribute \enum_value_1100010000 "SIER_priv" attribute \enum_value_1100010001 "MMCR2_priv" attribute \enum_value_1100010010 "MMCRA_priv" attribute \enum_value_1100010011 "PMC1_priv" attribute \enum_value_1100010100 "PMC2_priv" attribute \enum_value_1100010101 "PMC3_priv" attribute \enum_value_1100010110 "PMC4_priv" attribute \enum_value_1100010111 "PMC5_priv" attribute \enum_value_1100011000 "PMC6_priv" attribute \enum_value_1100011011 "MMCR0_priv" attribute \enum_value_1100011100 "SIAR_priv" attribute \enum_value_1100011101 "SDAR_priv" attribute \enum_value_1100011110 "MMCR1_priv" attribute \enum_value_1100100000 "BESCRS" attribute \enum_value_1100100001 "BESCRSU" attribute \enum_value_1100100010 "BESCRR" attribute \enum_value_1100100011 "BESCRRU" attribute \enum_value_1100100100 "EBBHR" attribute \enum_value_1100100101 "EBBRR" attribute \enum_value_1100100110 "BESCR" attribute \enum_value_1100101000 "reserved808" attribute \enum_value_1100101001 "reserved809" attribute \enum_value_1100101010 "reserved810" attribute \enum_value_1100101011 "reserved811" attribute \enum_value_1100101111 "TAR" attribute \enum_value_1100110000 "ASDR" attribute \enum_value_1100110111 "PSSCR" attribute \enum_value_1101010000 "IC" attribute \enum_value_1101010001 "VTB" attribute \enum_value_1101010111 "PSSCR_hypv" attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 10 \dec2_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \dec2_spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" wire \dec2_sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" wire width 13 \dec2_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" wire width 8 \dec2_traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" wire \dec2_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire width 2 \delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 282 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 151 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 283 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 152 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 284 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 153 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" wire \exec_fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" wire \exec_fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:919" wire \exec_insn_ready_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:918" wire \exec_insn_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:923" wire \exec_pc_ready_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" wire \exec_pc_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" wire width 2 \fetch_fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" wire width 2 \fetch_fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:907" wire \fetch_insn_ready_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:906" wire \fetch_insn_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:903" wire \fetch_pc_ready_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" wire \fetch_pc_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 236 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 106 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 107 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 105 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 237 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 238 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 239 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 109 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 110 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 108 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 240 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 241 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 242 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 112 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 113 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 111 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 243 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 244 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 245 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 115 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 116 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 114 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 246 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 247 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 248 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 118 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 119 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 117 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 249 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 250 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 251 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 122 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 120 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 252 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 253 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 230 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 100 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 101 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 99 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 231 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 232 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 233 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 103 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 104 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 102 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 234 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 235 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 254 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 124 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 125 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 123 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 255 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 256 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 257 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 127 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 128 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 126 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 258 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 259 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 260 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 130 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 131 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 129 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 261 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 262 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 263 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 133 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 134 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 132 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 265 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 266 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 136 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 137 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 135 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 267 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 268 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 269 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 139 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 140 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 138 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 270 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 271 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 272 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 142 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 143 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 141 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 273 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 274 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 275 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 146 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 144 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 276 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 277 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 18 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 45 output 23 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 17 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 64 input 22 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 19 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 8 output 21 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire output 296 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 28 input 302 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 297 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 32 output 298 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 32 input 299 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 4 input 303 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 300 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 301 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire output 309 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 28 input 304 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 306 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 32 output 308 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 32 input 310 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 307 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 311 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire \imem_a_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" wire \imem_f_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" wire width 64 \imem_f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en attribute \src "libresoc.v:194977.7-194977.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:267" wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 305 \int_level_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667" wire \is_last attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" wire \is_svp64_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire width 3 \issue_fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 4 \jtag_dmi0__addr_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 \jtag_dmi0__din attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 \jtag_dmi0__dout attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire width 64 \jtag_dmi0__dout$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__req_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 292 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 output 286 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 288 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 input 293 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 output 291 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 287 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 289 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 290 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 155 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 25 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 156 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 158 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 157 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" wire \msr_read attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 150 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 281 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 278 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 148 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 149 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 147 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 279 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 280 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \new_svstate_maxvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \new_svstate_srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" wire width 2 \new_svstate_subvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" wire width 64 \new_tb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:522" wire width 7 \next_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:521" wire width 7 \next_srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885" wire width 64 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885" wire width 64 \nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire width 64 \pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:866" wire \pc_changed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:866" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 input 7 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire input 6 \pc_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:234" wire width 64 output 5 \pc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \pc_ok_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \pc_ok_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" wire \por_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" wire \pred_insn_ready_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:910" wire \pred_insn_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:915" wire \pred_mask_ready_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:914" wire \pred_mask_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 2 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 53 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 184 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 71 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 202 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 72 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 203 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 204 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 185 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 186 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 56 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 187 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 188 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 58 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 189 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 59 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 190 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 191 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 192 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 62 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 193 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 194 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 195 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 68 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 199 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 197 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 65 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 196 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 201 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 28 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 159 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 74 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 205 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 160 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 29 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 161 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 162 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 212 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 82 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 83 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 81 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 213 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 214 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 215 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 85 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 84 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 216 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 217 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 218 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 88 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 89 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 219 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 220 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 221 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 91 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 90 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 222 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 223 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 224 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 94 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 95 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 93 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 225 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 226 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 227 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 97 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 98 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 96 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 228 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 229 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 163 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 34 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 32 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 164 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 165 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 166 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 35 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 167 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 168 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 169 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 40 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 38 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 170 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 171 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 172 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 41 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 173 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 174 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 175 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 46 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 44 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 176 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 177 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 178 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 47 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 179 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 180 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 181 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 52 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 50 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 182 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 183 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 206 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 207 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 208 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 209 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 79 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 80 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 78 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 210 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 211 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 198 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 200 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" wire \sv_changed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" wire \sv_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" wire width 64 \svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 32 \svstate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire \svstate_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \svstate_ok_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" wire \svstate_ok_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \ti_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:514" wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 \xics_icp_ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_icp_ics_i_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" cell $add $add$libresoc.v:197050$13081 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 connect \Y $add$libresoc.v:197050$13081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:523" cell $add $add$libresoc.v:197062$13092 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 connect \Y $add$libresoc.v:197062$13092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:524" cell $add $add$libresoc.v:197063$13093 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 8 connect \A \cur_cur_dststep connect \B 1'1 connect \Y $add$libresoc.v:197063$13093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1056" cell $add $add$libresoc.v:197135$13165 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 connect \Y $add$libresoc.v:197135$13165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" cell $add $add$libresoc.v:197168$13197 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 connect \Y $add$libresoc.v:197168$13197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197055$13086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 connect \Y $and$libresoc.v:197055$13086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197058$13089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 connect \Y $and$libresoc.v:197058$13089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197066$13096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 connect \Y $and$libresoc.v:197066$13096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197069$13099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$136 connect \B \$138 connect \Y $and$libresoc.v:197069$13099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $and $and$libresoc.v:197071$13101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$142 connect \Y $and$libresoc.v:197071$13101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197075$13105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$148 connect \B \$150 connect \Y $and$libresoc.v:197075$13105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197081$13110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$160 connect \B \$162 connect \Y $and$libresoc.v:197081$13110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197084$13113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$166 connect \B \$168 connect \Y $and$libresoc.v:197084$13113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197087$13116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$172 connect \B \$174 connect \Y $and$libresoc.v:197087$13116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197090$13119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$178 connect \B \$180 connect \Y $and$libresoc.v:197090$13119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197093$13122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$184 connect \B \$186 connect \Y $and$libresoc.v:197093$13122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197096$13125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$190 connect \B \$192 connect \Y $and$libresoc.v:197096$13125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" cell $and $and$libresoc.v:197097$13126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 connect \Y $and$libresoc.v:197097$13126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197101$13130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$200 connect \B \$202 connect \Y $and$libresoc.v:197101$13130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197104$13133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$206 connect \B \$208 connect \Y $and$libresoc.v:197104$13133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197110$13138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$218 connect \B \$220 connect \Y $and$libresoc.v:197110$13138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197113$13141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$224 connect \B \$226 connect \Y $and$libresoc.v:197113$13141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:765" cell $and $and$libresoc.v:197114$13142 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 connect \Y $and$libresoc.v:197114$13142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $and $and$libresoc.v:197117$13145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$234 connect \Y $and$libresoc.v:197117$13145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197122$13150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$240 connect \B \$242 connect \Y $and$libresoc.v:197122$13150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197125$13153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$246 connect \B \$248 connect \Y $and$libresoc.v:197125$13153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:197140$13170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 connect \Y $and$libresoc.v:197140$13170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197146$13177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 connect \Y $and$libresoc.v:197146$13177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $and $and$libresoc.v:197148$13179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$50 connect \Y $and$libresoc.v:197148$13179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197151$13182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$54 connect \B \$56 connect \Y $and$libresoc.v:197151$13182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $and $and$libresoc.v:197157$13187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 connect \Y $and$libresoc.v:197157$13187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $and $and$libresoc.v:197159$13189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$72 connect \Y $and$libresoc.v:197159$13189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $and $and$libresoc.v:197162$13192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$76 connect \B \$78 connect \Y $and$libresoc.v:197162$13192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $eq $eq$libresoc.v:197070$13100 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 connect \Y $eq$libresoc.v:197070$13100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $eq $eq$libresoc.v:197116$13144 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 connect \Y $eq$libresoc.v:197116$13144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:669" cell $eq $eq$libresoc.v:197126$13154 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl connect \Y $eq$libresoc.v:197126$13154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $eq $eq$libresoc.v:197147$13178 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 connect \Y $eq$libresoc.v:197147$13178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" cell $eq $eq$libresoc.v:197158$13188 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 connect \Y $eq$libresoc.v:197158$13188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" cell $pos $extend$libresoc.v:197131$13159 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o connect \Y $extend$libresoc.v:197131$13159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" cell $pos $extend$libresoc.v:197132$13161 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o connect \Y $extend$libresoc.v:197132$13161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $extend$libresoc.v:197143$13173 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i connect \Y $extend$libresoc.v:197143$13173_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" cell $mul $mul$libresoc.v:197051$13082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 connect \Y $mul$libresoc.v:197051$13082_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" cell $mul $mul$libresoc.v:197169$13198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 connect \Y $mul$libresoc.v:197169$13198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" cell $ne $ne$libresoc.v:197119$13147 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 connect \Y $ne$libresoc.v:197119$13147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:762" cell $ne $ne$libresoc.v:197128$13156 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 connect \Y $ne$libresoc.v:197128$13156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" cell $ne $ne$libresoc.v:197138$13168 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 connect \Y $ne$libresoc.v:197138$13168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197053$13084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197053$13084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197054$13085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197054$13085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197056$13087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197056$13087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197057$13088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197057$13088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197064$13094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197064$13094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197065$13095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197065$13095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197067$13097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197067$13097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197068$13098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197068$13098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" cell $not $not$libresoc.v:197072$13102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \Y $not$libresoc.v:197072$13102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197073$13103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197073$13103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197074$13104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197074$13104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197079$13108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197079$13108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197080$13109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197080$13109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197082$13111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197082$13111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197083$13112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197083$13112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197085$13114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197085$13114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197086$13115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197086$13115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197088$13117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197088$13117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197089$13118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197089$13118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197091$13120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197091$13120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197092$13121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197092$13121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197094$13123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197094$13123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197095$13124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197095$13124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197099$13128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197099$13128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197100$13129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197100$13129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197102$13131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197102$13131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197103$13132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197103$13132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197108$13136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197108$13136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197109$13137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197109$13137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197111$13139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197111$13139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197112$13140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197112$13140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" cell $not $not$libresoc.v:197118$13146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o connect \Y $not$libresoc.v:197118$13146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197120$13148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197120$13148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197121$13149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197121$13149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197123$13151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197123$13151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197124$13152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197124$13152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" cell $not $not$libresoc.v:197129$13157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o connect \Y $not$libresoc.v:197129$13157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" cell $not $not$libresoc.v:197130$13158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o connect \Y $not$libresoc.v:197130$13158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:197139$13169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly connect \Y $not$libresoc.v:197139$13169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" cell $not $not$libresoc.v:197141$13171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok connect \Y $not$libresoc.v:197141$13171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" cell $not $not$libresoc.v:197142$13172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok connect \Y $not$libresoc.v:197142$13172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197144$13175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197144$13175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197145$13176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197145$13176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197149$13180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197149$13180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197150$13181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197150$13181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197155$13185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197155$13185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" cell $not $not$libresoc.v:197156$13186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197156$13186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197160$13190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o connect \Y $not$libresoc.v:197160$13190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" cell $not $not$libresoc.v:197161$13191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst connect \Y $not$libresoc.v:197161$13191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" cell $not $not$libresoc.v:197166$13195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read connect \Y $not$libresoc.v:197166$13195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" cell $not $not$libresoc.v:197167$13196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read connect \Y $not$libresoc.v:197167$13196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" cell $or $or$libresoc.v:197059$13090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed connect \Y $or$libresoc.v:197059$13090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" cell $or $or$libresoc.v:197061$13091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$120 connect \B \is_last connect \Y $or$libresoc.v:197061$13091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" cell $or $or$libresoc.v:197076$13106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed connect \Y $or$libresoc.v:197076$13106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" cell $or $or$libresoc.v:197078$13107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$156 connect \B \is_last connect \Y $or$libresoc.v:197078$13107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" cell $or $or$libresoc.v:197105$13134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed connect \Y $or$libresoc.v:197105$13134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" cell $or $or$libresoc.v:197107$13135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$214 connect \B \is_last connect \Y $or$libresoc.v:197107$13135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" cell $or $or$libresoc.v:197136$13166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o connect \Y $or$libresoc.v:197136$13166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:836" cell $or $or$libresoc.v:197137$13167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst connect \Y $or$libresoc.v:197137$13167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" cell $or $or$libresoc.v:197152$13183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed connect \Y $or$libresoc.v:197152$13183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" cell $or $or$libresoc.v:197154$13184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$62 connect \B \is_last connect \Y $or$libresoc.v:197154$13184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" cell $or $or$libresoc.v:197163$13193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed connect \Y $or$libresoc.v:197163$13193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:680" cell $or $or$libresoc.v:197165$13194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$84 connect \B \is_last connect \Y $or$libresoc.v:197165$13194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" cell $pos $pos$libresoc.v:197127$13155 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } connect \Y $pos$libresoc.v:197127$13155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" cell $pos $pos$libresoc.v:197131$13160 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:197131$13159_Y connect \Y $pos$libresoc.v:197131$13160_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" cell $pos $pos$libresoc.v:197132$13162 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:197132$13161_Y connect \Y $pos$libresoc.v:197132$13162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" cell $pos $pos$libresoc.v:197143$13174 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A $extend$libresoc.v:197143$13173_Y connect \Y $pos$libresoc.v:197143$13174_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:197098$13127 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$197 connect \Y $reduce_or$libresoc.v:197098$13127_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:197115$13143 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$231 connect \Y $reduce_or$libresoc.v:197115$13143_Y end attribute \src "libresoc.v:197052.18-197052.41" cell $shr $shr$libresoc.v:197052$13083 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 connect \Y $shr$libresoc.v:197052$13083_Y end attribute \src "libresoc.v:197170.18-197170.40" cell $shr $shr$libresoc.v:197170$13199 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 connect \Y $shr$libresoc.v:197170$13199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1040" cell $sub $sub$libresoc.v:197133$13163 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 connect \Y $sub$libresoc.v:197133$13163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:831" cell $sub $sub$libresoc.v:197134$13164 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 connect \Y $sub$libresoc.v:197134$13164_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:197379.8-197477.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o connect \cia__ren \core_cia__ren connect \core_core_cia \core_core_core_cia connect \core_core_cr_rd \core_core_core_cr_rd connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok connect \core_core_cr_wr \core_core_core_cr_wr connect \core_core_exc_$signal \core_core_core_exc_$signal connect \core_core_exc_$signal$3 \core_core_core_exc_$signal$3 connect \core_core_exc_$signal$4 \core_core_core_exc_$signal$4 connect \core_core_exc_$signal$5 \core_core_core_exc_$signal$5 connect \core_core_exc_$signal$6 \core_core_core_exc_$signal$6 connect \core_core_exc_$signal$7 \core_core_core_exc_$signal$7 connect \core_core_exc_$signal$8 \core_core_core_exc_$signal$8 connect \core_core_exc_$signal$9 \core_core_core_exc_$signal$9 connect \core_core_fn_unit \core_core_core_fn_unit connect \core_core_input_carry \core_core_core_input_carry connect \core_core_insn \core_core_core_insn connect \core_core_insn_type \core_core_core_insn_type connect \core_core_is_32bit \core_core_core_is_32bit connect \core_core_msr \core_core_core_msr connect \core_core_oe \core_core_core_oe connect \core_core_oe_ok \core_core_core_oe_ok connect \core_core_rc \core_core_core_rc connect \core_core_rc_ok \core_core_core_rc_ok connect \core_core_trapaddr \core_core_core_trapaddr connect \core_core_traptype \core_core_core_traptype connect \core_cr_in1 \core_core_cr_in1 connect \core_cr_in1_ok \core_core_cr_in1_ok connect \core_cr_in2 \core_core_cr_in2 connect \core_cr_in2$1 \core_core_cr_in2$1 connect \core_cr_in2_ok \core_core_cr_in2_ok connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 connect \core_cr_out \core_core_cr_out connect \core_ea \core_core_ea connect \core_fast1 \core_core_fast1 connect \core_fast1_ok \core_core_fast1_ok connect \core_fast2 \core_core_fast2 connect \core_fast2_ok \core_core_fast2_ok connect \core_fasto1 \core_core_fasto1 connect \core_fasto2 \core_core_fasto2 connect \core_pc \core_core_pc connect \core_reg1 \core_core_reg1 connect \core_reg1_ok \core_core_reg1_ok connect \core_reg2 \core_core_reg2 connect \core_reg2_ok \core_core_reg2_ok connect \core_reg3 \core_core_reg3 connect \core_reg3_ok \core_core_reg3_ok connect \core_rego \core_core_rego connect \core_spr1 \core_core_spr1 connect \core_spr1_ok \core_core_spr1_ok connect \core_spro \core_core_spro connect \core_terminate_o \core_core_terminate_o connect \core_xer_in \core_core_xer_in connect \corebusy_o \core_corebusy_o connect \coresync_clk \coresync_clk connect \coresync_rst \core_coresync_rst connect \cu_ad__go_i \core_cu_ad__go_i connect \cu_ad__rel_o \core_cu_ad__rel_o connect \cu_st__go_i \core_cu_st__go_i connect \cu_st__rel_o \core_cu_st__rel_o connect \data_i \core_data_i connect \data_i$11 \core_data_i$12 connect \dbus__ack \dbus__ack connect \dbus__adr \dbus__adr connect \dbus__cyc \dbus__cyc connect \dbus__dat_r \dbus__dat_r connect \dbus__dat_w \dbus__dat_w connect \dbus__err \dbus__err connect \dbus__sel \dbus__sel connect \dbus__stb \dbus__stb connect \dbus__we \dbus__we connect \dmi__addr \core_dmi__addr connect \dmi__data_o \core_dmi__data_o connect \dmi__ren \core_dmi__ren connect \full_rd2__data_o \core_full_rd2__data_o connect \full_rd2__ren \core_full_rd2__ren connect \full_rd__data_o \core_full_rd__data_o connect \full_rd__ren \core_full_rd__ren connect \issue__addr \core_issue__addr connect \issue__addr$12 \core_issue__addr$13 connect \issue__data_i \core_issue__data_i connect \issue__data_o \core_issue__data_o connect \issue__ren \core_issue__ren connect \issue__wen \core_issue__wen connect \issue_i \core_issue_i connect \ivalid_i \core_ivalid_i connect \msr__data_o \core_msr__data_o connect \msr__ren \core_msr__ren connect \raw_insn_i \core_raw_insn_i connect \state_nia_wen \core_state_nia_wen connect \sv__data_o \core_sv__data_o connect \sv__ren \core_sv__ren connect \sv_a_nz \core_sv_a_nz connect \wb_dcache_en \core_wb_dcache_en connect \wen \core_wen connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 attribute \src "libresoc.v:197478.7-197509.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep connect \core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_maxvl connect \core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_srcstep connect \core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_subvl connect \core_dbg_core_dbg_svstep \dbg_core_dbg_core_dbg_svstep connect \core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_vl connect \core_dbg_msr \dbg_core_dbg_msr connect \core_dbg_pc \dbg_core_dbg_pc connect \core_rst_o \dbg_core_rst_o connect \core_stop_o \dbg_core_stop_o connect \core_stopped_i \dbg_core_stopped_i connect \d_cr_ack \dbg_d_cr_ack connect \d_cr_data \dbg_d_cr_data connect \d_cr_req \dbg_d_cr_req connect \d_gpr_ack \dbg_d_gpr_ack connect \d_gpr_addr \dbg_d_gpr_addr connect \d_gpr_data \dbg_d_gpr_data connect \d_gpr_req \dbg_d_gpr_req connect \d_xer_ack \dbg_d_xer_ack connect \d_xer_data \dbg_d_xer_data connect \d_xer_req \dbg_d_xer_req connect \dmi_ack_o \dbg_dmi_ack_o connect \dmi_addr_i \dbg_dmi_addr_i connect \dmi_din \dbg_dmi_din connect \dmi_dout \dbg_dmi_dout connect \dmi_req_i \dbg_dmi_req_i connect \dmi_we_i \dbg_dmi_we_i connect \rst \rst connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 attribute \src "libresoc.v:197510.8-197577.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian connect \cia \dec2_cia connect \cr_in1 \dec2_cr_in1 connect \cr_in1_ok \dec2_cr_in1_ok connect \cr_in2 \dec2_cr_in2 connect \cr_in2$1 \dec2_cr_in2$14 connect \cr_in2_ok \dec2_cr_in2_ok connect \cr_in2_ok$2 \dec2_cr_in2_ok$15 connect \cr_out \dec2_cr_out connect \cr_out_ok \dec2_cr_out_ok connect \cr_rd \dec2_cr_rd connect \cr_rd_ok \dec2_cr_rd_ok connect \cr_wr \dec2_cr_wr connect \cr_wr_ok \dec2_cr_wr_ok connect \cur_dec \dec2_cur_dec connect \cur_eint \dec2_cur_eint connect \cur_msr \dec2_cur_msr connect \cur_pc \dec2_cur_pc connect \ea \dec2_ea connect \ea_ok \dec2_ea_ok connect \exc_$signal \dec2_exc_$signal connect \exc_$signal$3 \dec2_exc_$signal$16 connect \exc_$signal$4 \dec2_exc_$signal$17 connect \exc_$signal$5 \dec2_exc_$signal$18 connect \exc_$signal$6 \dec2_exc_$signal$19 connect \exc_$signal$7 \dec2_exc_$signal$20 connect \exc_$signal$8 \dec2_exc_$signal$21 connect \exc_$signal$9 \dec2_exc_$signal$22 connect \fast1 \dec2_fast1 connect \fast1_ok \dec2_fast1_ok connect \fast2 \dec2_fast2 connect \fast2_ok \dec2_fast2_ok connect \fasto1 \dec2_fasto1 connect \fasto1_ok \dec2_fasto1_ok connect \fasto2 \dec2_fasto2 connect \fasto2_ok \dec2_fasto2_ok connect \fn_unit \dec2_fn_unit connect \input_carry \dec2_input_carry connect \insn \dec2_insn connect \insn_type \dec2_insn_type connect \is_32bit \dec2_is_32bit connect \lk \dec2_lk connect \msr \dec2_msr connect \oe \dec2_oe connect \oe_ok \dec2_oe_ok connect \raw_opcode_in \dec2_raw_opcode_in connect \rc \dec2_rc connect \rc_ok \dec2_rc_ok connect \reg1 \dec2_reg1 connect \reg1_ok \dec2_reg1_ok connect \reg2 \dec2_reg2 connect \reg2_ok \dec2_reg2_ok connect \reg3 \dec2_reg3 connect \reg3_ok \dec2_reg3_ok connect \rego \dec2_rego connect \rego_ok \dec2_rego_ok connect \spr1 \dec2_spr1 connect \spr1_ok \dec2_spr1_ok connect \spro \dec2_spro connect \spro_ok \dec2_spro_ok connect \sv_a_nz \dec2_sv_a_nz connect \trapaddr \dec2_trapaddr connect \traptype \dec2_traptype connect \xer_in \dec2_xer_in connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 attribute \src "libresoc.v:197578.8-197594.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i connect \clk \clk connect \f_busy_o \imem_f_busy_o connect \f_instr_o \imem_f_instr_o connect \f_valid_i \imem_f_valid_i connect \ibus__ack \ibus__ack connect \ibus__adr \ibus__adr connect \ibus__cyc \ibus__cyc connect \ibus__dat_r \ibus__dat_r connect \ibus__err \ibus__err connect \ibus__sel \ibus__sel connect \ibus__stb \ibus__stb connect \rst \rst connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 attribute \src "libresoc.v:197595.8-197878.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_bus__tdo \TAP_bus__tdo connect \TAP_bus__tms \TAP_bus__tms connect \clk \clk connect \dmi0__ack_o \jtag_dmi0__ack_o connect \dmi0__addr_i \jtag_dmi0__addr_i connect \dmi0__din \jtag_dmi0__din connect \dmi0__dout \jtag_dmi0__dout connect \dmi0__req_i \jtag_dmi0__req_i connect \dmi0__we_i \jtag_dmi0__we_i connect \eint_0__core__i \eint_0__core__i connect \eint_0__pad__i \eint_0__pad__i connect \eint_1__core__i \eint_1__core__i connect \eint_1__pad__i \eint_1__pad__i connect \eint_2__core__i \eint_2__core__i connect \eint_2__pad__i \eint_2__pad__i connect \gpio_e10__core__i \gpio_e10__core__i connect \gpio_e10__core__o \gpio_e10__core__o connect \gpio_e10__core__oe \gpio_e10__core__oe connect \gpio_e10__pad__i \gpio_e10__pad__i connect \gpio_e10__pad__o \gpio_e10__pad__o connect \gpio_e10__pad__oe \gpio_e10__pad__oe connect \gpio_e11__core__i \gpio_e11__core__i connect \gpio_e11__core__o \gpio_e11__core__o connect \gpio_e11__core__oe \gpio_e11__core__oe connect \gpio_e11__pad__i \gpio_e11__pad__i connect \gpio_e11__pad__o \gpio_e11__pad__o connect \gpio_e11__pad__oe \gpio_e11__pad__oe connect \gpio_e12__core__i \gpio_e12__core__i connect \gpio_e12__core__o \gpio_e12__core__o connect \gpio_e12__core__oe \gpio_e12__core__oe connect \gpio_e12__pad__i \gpio_e12__pad__i connect \gpio_e12__pad__o \gpio_e12__pad__o connect \gpio_e12__pad__oe \gpio_e12__pad__oe connect \gpio_e13__core__i \gpio_e13__core__i connect \gpio_e13__core__o \gpio_e13__core__o connect \gpio_e13__core__oe \gpio_e13__core__oe connect \gpio_e13__pad__i \gpio_e13__pad__i connect \gpio_e13__pad__o \gpio_e13__pad__o connect \gpio_e13__pad__oe \gpio_e13__pad__oe connect \gpio_e14__core__i \gpio_e14__core__i connect \gpio_e14__core__o \gpio_e14__core__o connect \gpio_e14__core__oe \gpio_e14__core__oe connect \gpio_e14__pad__i \gpio_e14__pad__i connect \gpio_e14__pad__o \gpio_e14__pad__o connect \gpio_e14__pad__oe \gpio_e14__pad__oe connect \gpio_e15__core__i \gpio_e15__core__i connect \gpio_e15__core__o \gpio_e15__core__o connect \gpio_e15__core__oe \gpio_e15__core__oe connect \gpio_e15__pad__i \gpio_e15__pad__i connect \gpio_e15__pad__o \gpio_e15__pad__o connect \gpio_e15__pad__oe \gpio_e15__pad__oe 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\mspi0_clk__pad__o \mspi0_clk__pad__o connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o connect \mspi0_miso__core__i \mspi0_miso__core__i connect \mspi0_miso__pad__i \mspi0_miso__pad__i connect \mspi0_mosi__core__o \mspi0_mosi__core__o connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o connect \mtwi_scl__core__o \mtwi_scl__core__o connect \mtwi_scl__pad__o \mtwi_scl__pad__o connect \mtwi_sda__core__i \mtwi_sda__core__i connect \mtwi_sda__core__o \mtwi_sda__core__o connect \mtwi_sda__core__oe \mtwi_sda__core__oe connect \mtwi_sda__pad__i \mtwi_sda__pad__i connect \mtwi_sda__pad__o \mtwi_sda__pad__o connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe connect \rst \rst connect \sdr_a_0__core__o \sdr_a_0__core__o connect \sdr_a_0__pad__o \sdr_a_0__pad__o connect \sdr_a_10__core__o \sdr_a_10__core__o connect \sdr_a_10__pad__o \sdr_a_10__pad__o connect \sdr_a_11__core__o \sdr_a_11__core__o connect \sdr_a_11__pad__o \sdr_a_11__pad__o connect \sdr_a_12__core__o \sdr_a_12__core__o connect \sdr_a_12__pad__o \sdr_a_12__pad__o connect \sdr_a_1__core__o \sdr_a_1__core__o connect \sdr_a_1__pad__o \sdr_a_1__pad__o connect \sdr_a_2__core__o \sdr_a_2__core__o connect \sdr_a_2__pad__o \sdr_a_2__pad__o connect \sdr_a_3__core__o \sdr_a_3__core__o connect \sdr_a_3__pad__o \sdr_a_3__pad__o connect \sdr_a_4__core__o \sdr_a_4__core__o connect \sdr_a_4__pad__o \sdr_a_4__pad__o connect \sdr_a_5__core__o \sdr_a_5__core__o connect \sdr_a_5__pad__o \sdr_a_5__pad__o connect \sdr_a_6__core__o \sdr_a_6__core__o connect \sdr_a_6__pad__o \sdr_a_6__pad__o connect \sdr_a_7__core__o \sdr_a_7__core__o connect \sdr_a_7__pad__o \sdr_a_7__pad__o connect \sdr_a_8__core__o \sdr_a_8__core__o connect \sdr_a_8__pad__o \sdr_a_8__pad__o connect \sdr_a_9__core__o \sdr_a_9__core__o connect \sdr_a_9__pad__o \sdr_a_9__pad__o connect \sdr_ba_0__core__o \sdr_ba_0__core__o connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o connect \sdr_ba_1__core__o \sdr_ba_1__core__o connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o connect \sdr_cas_n__core__o \sdr_cas_n__core__o connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o connect \sdr_cke__core__o \sdr_cke__core__o connect \sdr_cke__pad__o \sdr_cke__pad__o connect \sdr_clock__core__o \sdr_clock__core__o connect \sdr_clock__pad__o \sdr_clock__pad__o connect \sdr_cs_n__core__o \sdr_cs_n__core__o connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o connect \sdr_dm_0__core__o \sdr_dm_0__core__o connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o connect \sdr_dm_1__core__o \sdr_dm_1__core__o connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o connect \sdr_dq_0__core__i \sdr_dq_0__core__i connect \sdr_dq_0__core__o \sdr_dq_0__core__o connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe connect \sdr_dq_10__core__i \sdr_dq_10__core__i connect \sdr_dq_10__core__o \sdr_dq_10__core__o connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe connect \sdr_dq_11__core__i \sdr_dq_11__core__i connect \sdr_dq_11__core__o \sdr_dq_11__core__o connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe connect \sdr_dq_12__core__i \sdr_dq_12__core__i connect \sdr_dq_12__core__o \sdr_dq_12__core__o connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe connect \sdr_dq_13__core__i \sdr_dq_13__core__i connect \sdr_dq_13__core__o \sdr_dq_13__core__o connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe connect \sdr_dq_14__core__i \sdr_dq_14__core__i connect \sdr_dq_14__core__o \sdr_dq_14__core__o connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe connect \sdr_dq_15__core__i \sdr_dq_15__core__i connect \sdr_dq_15__core__o \sdr_dq_15__core__o connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe connect \sdr_dq_1__core__i \sdr_dq_1__core__i connect \sdr_dq_1__core__o \sdr_dq_1__core__o connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe connect \sdr_dq_2__core__i \sdr_dq_2__core__i connect \sdr_dq_2__core__o \sdr_dq_2__core__o connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe connect \sdr_dq_3__core__i \sdr_dq_3__core__i connect \sdr_dq_3__core__o \sdr_dq_3__core__o connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe connect \sdr_dq_4__core__i \sdr_dq_4__core__i connect \sdr_dq_4__core__o \sdr_dq_4__core__o connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe connect \sdr_dq_5__core__i \sdr_dq_5__core__i connect \sdr_dq_5__core__o \sdr_dq_5__core__o connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe connect \sdr_dq_6__core__i \sdr_dq_6__core__i connect \sdr_dq_6__core__o \sdr_dq_6__core__o connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe connect \sdr_dq_7__core__i \sdr_dq_7__core__i connect \sdr_dq_7__core__o \sdr_dq_7__core__o connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe connect \sdr_dq_8__core__i \sdr_dq_8__core__i connect \sdr_dq_8__core__o \sdr_dq_8__core__o connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe connect \sdr_dq_9__core__i \sdr_dq_9__core__i connect \sdr_dq_9__core__o \sdr_dq_9__core__o connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe connect \sdr_ras_n__core__o \sdr_ras_n__core__o connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o connect \sdr_we_n__core__o \sdr_we_n__core__o connect \sdr_we_n__pad__o \sdr_we_n__pad__o connect \wb_dcache_en \core_wb_dcache_en connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 attribute \src "libresoc.v:197879.12-197893.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o connect \icp_wb__ack \icp_wb__ack connect \icp_wb__adr \icp_wb__adr connect \icp_wb__cyc \icp_wb__cyc connect \icp_wb__dat_r \icp_wb__dat_r connect \icp_wb__dat_w \icp_wb__dat_w connect \icp_wb__sel \icp_wb__sel connect \icp_wb__stb \icp_wb__stb connect \icp_wb__we \icp_wb__we connect \ics_i_pri \xics_icp_ics_i_pri connect \ics_i_src \xics_icp_ics_i_src connect \rst \rst end attribute \module_not_derived 1 attribute \src "libresoc.v:197894.12-197907.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri connect \icp_o_src \xics_ics_icp_o_src connect \ics_wb__ack \ics_wb__ack connect \ics_wb__adr \ics_wb__adr connect \ics_wb__cyc \ics_wb__cyc connect \ics_wb__dat_r \ics_wb__dat_r connect \ics_wb__dat_w \ics_wb__dat_w connect \ics_wb__stb \ics_wb__stb connect \ics_wb__we \ics_wb__we connect \int_level_i \int_level_i connect \rst \rst end attribute \src "libresoc.v:194977.7-194977.20" process $proc$libresoc.v:194977$13712 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:195247.13-195247.33" process $proc$libresoc.v:195247$13713 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end attribute \src "libresoc.v:195253.7-195253.35" process $proc$libresoc.v:195253$13714 assign { } { } assign $0\core_bigendian_i$10[0:0]$13715 1'0 sync always sync init update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13715 end attribute \src "libresoc.v:195261.14-195261.55" process $proc$libresoc.v:195261$13716 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end attribute \src "libresoc.v:195265.13-195265.41" process $proc$libresoc.v:195265$13717 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end attribute \src "libresoc.v:195269.7-195269.37" process $proc$libresoc.v:195269$13718 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end attribute \src "libresoc.v:195273.13-195273.41" process $proc$libresoc.v:195273$13719 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end attribute \src "libresoc.v:195277.7-195277.42" process $proc$libresoc.v:195277$13720 assign { } { } assign $0\core_core_core_exc_$signal[0:0]$13721 1'0 sync always sync init update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13721 end attribute \src "libresoc.v:195279.7-195279.44" process $proc$libresoc.v:195279$13722 assign { } { } assign $0\core_core_core_exc_$signal$3[0:0]$13723 1'0 sync always sync init update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13723 end attribute \src "libresoc.v:195283.7-195283.44" process $proc$libresoc.v:195283$13724 assign { } { } assign $0\core_core_core_exc_$signal$4[0:0]$13725 1'0 sync always sync init update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13725 end attribute \src "libresoc.v:195287.7-195287.44" process $proc$libresoc.v:195287$13726 assign { } { } assign $0\core_core_core_exc_$signal$5[0:0]$13727 1'0 sync always sync init update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13727 end attribute \src "libresoc.v:195291.7-195291.44" process $proc$libresoc.v:195291$13728 assign { } { } assign $0\core_core_core_exc_$signal$6[0:0]$13729 1'0 sync always sync init update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13729 end attribute \src "libresoc.v:195295.7-195295.44" process $proc$libresoc.v:195295$13730 assign { } { } assign $0\core_core_core_exc_$signal$7[0:0]$13731 1'0 sync always sync init update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13731 end attribute \src "libresoc.v:195299.7-195299.44" process $proc$libresoc.v:195299$13732 assign { } { } assign $0\core_core_core_exc_$signal$8[0:0]$13733 1'0 sync always sync init update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13733 end attribute \src "libresoc.v:195303.7-195303.44" process $proc$libresoc.v:195303$13734 assign { } { } assign $0\core_core_core_exc_$signal$9[0:0]$13735 1'0 sync always sync init update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13735 end attribute \src "libresoc.v:195324.14-195324.47" process $proc$libresoc.v:195324$13736 assign { } { } assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end attribute \src "libresoc.v:195332.13-195332.46" process $proc$libresoc.v:195332$13737 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end attribute \src "libresoc.v:195336.14-195336.41" process $proc$libresoc.v:195336$13738 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end attribute \src "libresoc.v:195415.13-195415.45" process $proc$libresoc.v:195415$13739 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end attribute \src "libresoc.v:195419.7-195419.37" process $proc$libresoc.v:195419$13740 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end attribute \src "libresoc.v:195423.14-195423.55" process $proc$libresoc.v:195423$13741 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end attribute \src "libresoc.v:195427.7-195427.31" process $proc$libresoc.v:195427$13742 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end attribute \src "libresoc.v:195431.7-195431.34" process $proc$libresoc.v:195431$13743 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end attribute \src "libresoc.v:195435.7-195435.31" process $proc$libresoc.v:195435$13744 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end attribute \src "libresoc.v:195439.7-195439.34" process $proc$libresoc.v:195439$13745 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end attribute \src "libresoc.v:195443.14-195443.48" process $proc$libresoc.v:195443$13746 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end attribute \src "libresoc.v:195447.13-195447.44" process $proc$libresoc.v:195447$13747 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end attribute \src "libresoc.v:195451.13-195451.37" process $proc$libresoc.v:195451$13748 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end attribute \src "libresoc.v:195455.7-195455.33" process $proc$libresoc.v:195455$13749 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end attribute \src "libresoc.v:195459.13-195459.37" process $proc$libresoc.v:195459$13750 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end attribute \src "libresoc.v:195461.13-195461.41" process $proc$libresoc.v:195461$13751 assign { } { } assign $0\core_core_cr_in2$1[6:0]$13752 7'0000000 sync always sync init update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13752 end attribute \src "libresoc.v:195467.7-195467.33" process $proc$libresoc.v:195467$13753 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end attribute \src "libresoc.v:195469.7-195469.37" process $proc$libresoc.v:195469$13754 assign { } { } assign $0\core_core_cr_in2_ok$2[0:0]$13755 1'0 sync always sync init update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13755 end attribute \src "libresoc.v:195475.13-195475.37" process $proc$libresoc.v:195475$13756 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end attribute \src "libresoc.v:195479.7-195479.32" process $proc$libresoc.v:195479$13757 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end attribute \src "libresoc.v:195483.13-195483.38" process $proc$libresoc.v:195483$13758 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end attribute \src "libresoc.v:195487.13-195487.33" process $proc$libresoc.v:195487$13759 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end attribute \src "libresoc.v:195491.13-195491.35" process $proc$libresoc.v:195491$13760 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end attribute \src "libresoc.v:195495.7-195495.32" process $proc$libresoc.v:195495$13761 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end attribute \src "libresoc.v:195499.13-195499.35" process $proc$libresoc.v:195499$13762 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end attribute \src "libresoc.v:195503.7-195503.32" process $proc$libresoc.v:195503$13763 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end attribute \src "libresoc.v:195507.13-195507.36" process $proc$libresoc.v:195507$13764 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end attribute \src "libresoc.v:195511.13-195511.36" process $proc$libresoc.v:195511$13765 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end attribute \src "libresoc.v:195515.7-195515.26" process $proc$libresoc.v:195515$13766 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end attribute \src "libresoc.v:195519.13-195519.36" process $proc$libresoc.v:195519$13767 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end attribute \src "libresoc.v:195523.14-195523.49" process $proc$libresoc.v:195523$13768 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end attribute \src "libresoc.v:195527.13-195527.35" process $proc$libresoc.v:195527$13769 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end attribute \src "libresoc.v:195531.7-195531.31" process $proc$libresoc.v:195531$13770 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end attribute \src "libresoc.v:195535.13-195535.35" process $proc$libresoc.v:195535$13771 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end attribute \src "libresoc.v:195539.7-195539.31" process $proc$libresoc.v:195539$13772 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end attribute \src "libresoc.v:195543.13-195543.35" process $proc$libresoc.v:195543$13773 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end attribute \src "libresoc.v:195547.7-195547.31" process $proc$libresoc.v:195547$13774 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end attribute \src "libresoc.v:195551.13-195551.35" process $proc$libresoc.v:195551$13775 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end attribute \src "libresoc.v:195567.13-195567.37" process $proc$libresoc.v:195567$13776 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end attribute \src "libresoc.v:195571.7-195571.31" process $proc$libresoc.v:195571$13777 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end attribute \src "libresoc.v:195587.13-195587.37" process $proc$libresoc.v:195587$13778 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end attribute \src "libresoc.v:195591.13-195591.38" process $proc$libresoc.v:195591$13779 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end attribute \src "libresoc.v:195595.13-195595.35" process $proc$libresoc.v:195595$13780 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end attribute \src "libresoc.v:195599.13-195599.36" process $proc$libresoc.v:195599$13781 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end attribute \src "libresoc.v:195605.13-195605.33" process $proc$libresoc.v:195605$13782 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end attribute \src "libresoc.v:195609.13-195609.36" process $proc$libresoc.v:195609$13783 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end attribute \src "libresoc.v:195617.7-195617.28" process $proc$libresoc.v:195617$13784 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end attribute \src "libresoc.v:195633.14-195633.45" process $proc$libresoc.v:195633$13785 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end attribute \src "libresoc.v:195643.7-195643.24" process $proc$libresoc.v:195643$13786 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end attribute \src "libresoc.v:195647.7-195647.23" process $proc$libresoc.v:195647$13787 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end attribute \src "libresoc.v:195651.7-195651.28" process $proc$libresoc.v:195651$13788 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end attribute \src "libresoc.v:195655.7-195655.28" process $proc$libresoc.v:195655$13789 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end attribute \src "libresoc.v:195683.14-195683.45" process $proc$libresoc.v:195683$13790 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end attribute \src "libresoc.v:195691.14-195691.37" process $proc$libresoc.v:195691$13791 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end attribute \src "libresoc.v:195695.7-195695.26" process $proc$libresoc.v:195695$13792 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end attribute \src "libresoc.v:195699.7-195699.26" process $proc$libresoc.v:195699$13793 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end attribute \src "libresoc.v:195711.7-195711.26" process $proc$libresoc.v:195711$13794 assign { } { } assign $1\core_sv_a_nz[0:0] 1'0 sync always sync init update \core_sv_a_nz $1\core_sv_a_nz[0:0] end attribute \src "libresoc.v:195721.7-195721.26" process $proc$libresoc.v:195721$13795 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end attribute \src "libresoc.v:195727.7-195727.30" process $proc$libresoc.v:195727$13796 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end attribute \src "libresoc.v:195733.13-195733.36" process $proc$libresoc.v:195733$13797 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end attribute \src "libresoc.v:195737.13-195737.34" process $proc$libresoc.v:195737$13798 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end attribute \src "libresoc.v:195741.13-195741.36" process $proc$libresoc.v:195741$13799 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end attribute \src "libresoc.v:195745.13-195745.33" process $proc$libresoc.v:195745$13800 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end attribute \src "libresoc.v:195749.13-195749.34" process $proc$libresoc.v:195749$13801 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end attribute \src "libresoc.v:195753.13-195753.31" process $proc$libresoc.v:195753$13802 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end attribute \src "libresoc.v:195757.7-195757.24" process $proc$libresoc.v:195757$13803 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end attribute \src "libresoc.v:195761.7-195761.25" process $proc$libresoc.v:195761$13804 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end attribute \src "libresoc.v:195765.7-195765.25" process $proc$libresoc.v:195765$13805 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end attribute \src "libresoc.v:195813.13-195813.34" process $proc$libresoc.v:195813$13806 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end attribute \src "libresoc.v:195817.14-195817.48" process $proc$libresoc.v:195817$13807 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end attribute \src "libresoc.v:195823.7-195823.27" process $proc$libresoc.v:195823$13808 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end attribute \src "libresoc.v:195827.7-195827.26" process $proc$libresoc.v:195827$13809 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end attribute \src "libresoc.v:195881.14-195881.49" process $proc$libresoc.v:195881$13810 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end attribute \src "libresoc.v:195885.7-195885.27" process $proc$libresoc.v:195885$13811 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end attribute \src "libresoc.v:195889.14-195889.49" process $proc$libresoc.v:195889$13812 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end attribute \src "libresoc.v:195893.14-195893.48" process $proc$libresoc.v:195893$13813 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end attribute \src "libresoc.v:196045.14-196045.40" process $proc$libresoc.v:196045$13814 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end attribute \src "libresoc.v:196315.13-196315.25" process $proc$libresoc.v:196315$13815 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end attribute \src "libresoc.v:196331.7-196331.28" process $proc$libresoc.v:196331$13816 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end attribute \src "libresoc.v:196343.13-196343.35" process $proc$libresoc.v:196343$13817 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end attribute \src "libresoc.v:196355.13-196355.29" process $proc$libresoc.v:196355$13818 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end attribute \src "libresoc.v:196615.13-196615.35" process $proc$libresoc.v:196615$13819 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end attribute \src "libresoc.v:196619.7-196619.30" process $proc$libresoc.v:196619$13820 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end attribute \src "libresoc.v:196627.14-196627.52" process $proc$libresoc.v:196627$13821 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end attribute \src "libresoc.v:196667.7-196667.22" process $proc$libresoc.v:196667$13822 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end attribute \src "libresoc.v:196707.14-196707.40" process $proc$libresoc.v:196707$13823 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end attribute \src "libresoc.v:196713.7-196713.24" process $proc$libresoc.v:196713$13824 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end attribute \src "libresoc.v:196723.7-196723.25" process $proc$libresoc.v:196723$13825 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end attribute \src "libresoc.v:197023.7-197023.24" process $proc$libresoc.v:197023$13826 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end attribute \src "libresoc.v:197033.7-197033.30" process $proc$libresoc.v:197033$13827 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end attribute \src "libresoc.v:197171.3-197172.41" process $proc$libresoc.v:197171$13200 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end attribute \src "libresoc.v:197173.3-197174.41" process $proc$libresoc.v:197173$13201 assign { } { } assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk update \core_core_pc $0\core_core_pc[63:0] end attribute \src "libresoc.v:197175.3-197176.49" process $proc$libresoc.v:197175$13202 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end attribute \src "libresoc.v:197177.3-197178.39" process $proc$libresoc.v:197177$13203 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end attribute \src "libresoc.v:197179.3-197180.41" process $proc$libresoc.v:197179$13204 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end attribute \src "libresoc.v:197181.3-197182.43" process $proc$libresoc.v:197181$13205 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end attribute \src "libresoc.v:197183.3-197184.45" process $proc$libresoc.v:197183$13206 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end attribute \src "libresoc.v:197185.3-197186.33" process $proc$libresoc.v:197185$13207 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end attribute \src "libresoc.v:197187.3-197188.35" process $proc$libresoc.v:197187$13208 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end attribute \src "libresoc.v:197189.3-197190.33" process $proc$libresoc.v:197189$13209 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end attribute \src "libresoc.v:197191.3-197192.49" process $proc$libresoc.v:197191$13210 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end attribute \src "libresoc.v:197193.3-197194.47" process $proc$libresoc.v:197193$13211 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end attribute \src "libresoc.v:197195.3-197196.51" process $proc$libresoc.v:197195$13212 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end attribute \src "libresoc.v:197197.3-197198.51" process $proc$libresoc.v:197197$13213 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end attribute \src "libresoc.v:197199.3-197200.41" process $proc$libresoc.v:197199$13214 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end attribute \src "libresoc.v:197201.3-197202.47" process $proc$libresoc.v:197201$13215 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end attribute \src "libresoc.v:197203.3-197204.35" process $proc$libresoc.v:197203$13216 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end attribute \src "libresoc.v:197205.3-197206.41" process $proc$libresoc.v:197205$13217 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end attribute \src "libresoc.v:197207.3-197208.45" process $proc$libresoc.v:197207$13218 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end attribute \src "libresoc.v:197209.3-197210.41" process $proc$libresoc.v:197209$13219 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end attribute \src "libresoc.v:197211.3-197212.41" process $proc$libresoc.v:197211$13220 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end attribute \src "libresoc.v:197213.3-197214.37" process $proc$libresoc.v:197213$13221 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end attribute \src "libresoc.v:197215.3-197216.45" process $proc$libresoc.v:197215$13222 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end attribute \src "libresoc.v:197217.3-197218.51" process $proc$libresoc.v:197217$13223 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end attribute \src "libresoc.v:197219.3-197220.45" process $proc$libresoc.v:197219$13224 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end attribute \src "libresoc.v:197221.3-197222.51" process $proc$libresoc.v:197221$13225 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end attribute \src "libresoc.v:197223.3-197224.45" process $proc$libresoc.v:197223$13226 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end attribute \src "libresoc.v:197225.3-197226.39" process $proc$libresoc.v:197225$13227 assign { } { } assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk update \d_xer_delay $0\d_xer_delay[0:0] end attribute \src "libresoc.v:197227.3-197228.51" process $proc$libresoc.v:197227$13228 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end attribute \src "libresoc.v:197229.3-197230.45" process $proc$libresoc.v:197229$13229 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end attribute \src "libresoc.v:197231.3-197232.41" process $proc$libresoc.v:197231$13230 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end attribute \src "libresoc.v:197233.3-197234.45" process $proc$libresoc.v:197233$13231 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end attribute \src "libresoc.v:197235.3-197236.51" process $proc$libresoc.v:197235$13232 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end attribute \src "libresoc.v:197237.3-197238.49" process $proc$libresoc.v:197237$13233 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end attribute \src "libresoc.v:197239.3-197240.41" process $proc$libresoc.v:197239$13234 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end attribute \src "libresoc.v:197241.3-197242.47" process $proc$libresoc.v:197241$13235 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end attribute \src "libresoc.v:197243.3-197244.53" process $proc$libresoc.v:197243$13236 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end attribute \src "libresoc.v:197245.3-197246.47" process $proc$libresoc.v:197245$13237 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end attribute \src "libresoc.v:197247.3-197248.37" process $proc$libresoc.v:197247$13238 assign { } { } assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk update \d_cr_delay $0\d_cr_delay[0:0] end attribute \src "libresoc.v:197249.3-197250.53" process $proc$libresoc.v:197249$13239 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end attribute \src "libresoc.v:197251.3-197252.49" process $proc$libresoc.v:197251$13240 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end attribute \src "libresoc.v:197253.3-197254.45" process $proc$libresoc.v:197253$13241 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end attribute \src "libresoc.v:197255.3-197256.49" process $proc$libresoc.v:197255$13242 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end attribute \src "libresoc.v:197257.3-197258.45" process $proc$libresoc.v:197257$13243 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end attribute \src "libresoc.v:197259.3-197260.49" process $proc$libresoc.v:197259$13244 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end attribute \src "libresoc.v:197261.3-197262.55" process $proc$libresoc.v:197261$13245 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end attribute \src "libresoc.v:197263.3-197264.49" process $proc$libresoc.v:197263$13246 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end attribute \src "libresoc.v:197265.3-197266.55" process $proc$libresoc.v:197265$13247 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end attribute \src "libresoc.v:197267.3-197268.55" process $proc$libresoc.v:197267$13248 assign { } { } assign $0\core_core_cr_in2$1[6:0]$13249 \core_core_cr_in2$1$next sync posedge \clk update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13249 end attribute \src "libresoc.v:197269.3-197270.39" process $proc$libresoc.v:197269$13250 assign { } { } assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk update \d_reg_delay $0\d_reg_delay[0:0] end attribute \src "libresoc.v:197271.3-197272.61" process $proc$libresoc.v:197271$13251 assign { } { } assign $0\core_core_cr_in2_ok$2[0:0]$13252 \core_core_cr_in2_ok$2$next sync posedge \clk update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13252 end attribute \src "libresoc.v:197273.3-197274.49" process $proc$libresoc.v:197273$13253 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end attribute \src "libresoc.v:197275.3-197276.45" process $proc$libresoc.v:197275$13254 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end attribute \src "libresoc.v:197277.3-197278.53" process $proc$libresoc.v:197277$13255 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end attribute \src "libresoc.v:197279.3-197280.53" process $proc$libresoc.v:197279$13256 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end attribute \src "libresoc.v:197281.3-197282.55" process $proc$libresoc.v:197281$13257 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end attribute \src "libresoc.v:197283.3-197284.65" process $proc$libresoc.v:197283$13258 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end attribute \src "libresoc.v:197285.3-197286.61" process $proc$libresoc.v:197285$13259 assign { } { } assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end attribute \src "libresoc.v:197287.3-197288.41" process $proc$libresoc.v:197287$13260 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end attribute \src "libresoc.v:197289.3-197290.51" process $proc$libresoc.v:197289$13261 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end attribute \src "libresoc.v:197291.3-197292.45" process $proc$libresoc.v:197291$13262 assign { } { } assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk update \exec_fsm_state $0\exec_fsm_state[0:0] end attribute \src "libresoc.v:197293.3-197294.57" process $proc$libresoc.v:197293$13263 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end attribute \src "libresoc.v:197295.3-197296.51" process $proc$libresoc.v:197295$13264 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end attribute \src "libresoc.v:197297.3-197298.57" process $proc$libresoc.v:197297$13265 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end attribute \src "libresoc.v:197299.3-197300.69" process $proc$libresoc.v:197299$13266 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end attribute \src "libresoc.v:197301.3-197302.63" process $proc$libresoc.v:197301$13267 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end attribute \src "libresoc.v:197303.3-197304.71" process $proc$libresoc.v:197303$13268 assign { } { } assign $0\core_core_core_exc_$signal[0:0]$13269 \core_core_core_exc_$signal$next sync posedge \clk update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13269 end attribute \src "libresoc.v:197305.3-197306.75" process $proc$libresoc.v:197305$13270 assign { } { } assign $0\core_core_core_exc_$signal$3[0:0]$13271 \core_core_core_exc_$signal$3$next sync posedge \clk update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13271 end attribute \src "libresoc.v:197307.3-197308.75" process $proc$libresoc.v:197307$13272 assign { } { } assign $0\core_core_core_exc_$signal$4[0:0]$13273 \core_core_core_exc_$signal$4$next sync posedge \clk update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13273 end attribute \src "libresoc.v:197309.3-197310.75" process $proc$libresoc.v:197309$13274 assign { } { } assign $0\core_core_core_exc_$signal$5[0:0]$13275 \core_core_core_exc_$signal$5$next sync posedge \clk update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13275 end attribute \src "libresoc.v:197311.3-197312.75" process $proc$libresoc.v:197311$13276 assign { } { } assign $0\core_core_core_exc_$signal$6[0:0]$13277 \core_core_core_exc_$signal$6$next sync posedge \clk update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13277 end attribute \src "libresoc.v:197313.3-197314.41" process $proc$libresoc.v:197313$13278 assign { } { } assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk update \core_sv_a_nz $0\core_sv_a_nz[0:0] end attribute \src "libresoc.v:197315.3-197316.75" process $proc$libresoc.v:197315$13279 assign { } { } assign $0\core_core_core_exc_$signal$7[0:0]$13280 \core_core_core_exc_$signal$7$next sync posedge \clk update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13280 end attribute \src "libresoc.v:197317.3-197318.75" process $proc$libresoc.v:197317$13281 assign { } { } assign $0\core_core_core_exc_$signal$8[0:0]$13282 \core_core_core_exc_$signal$8$next sync posedge \clk update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13282 end attribute \src "libresoc.v:197319.3-197320.75" process $proc$libresoc.v:197319$13283 assign { } { } assign $0\core_core_core_exc_$signal$9[0:0]$13284 \core_core_core_exc_$signal$9$next sync posedge \clk update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13284 end attribute \src "libresoc.v:197321.3-197322.63" process $proc$libresoc.v:197321$13285 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end attribute \src "libresoc.v:197323.3-197324.57" process $proc$libresoc.v:197323$13286 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end attribute \src "libresoc.v:197325.3-197326.63" process $proc$libresoc.v:197325$13287 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end attribute \src "libresoc.v:197327.3-197328.57" process $proc$libresoc.v:197327$13288 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end attribute \src "libresoc.v:197329.3-197330.53" process $proc$libresoc.v:197329$13289 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end attribute \src "libresoc.v:197331.3-197332.63" process $proc$libresoc.v:197331$13290 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end attribute \src "libresoc.v:197333.3-197334.37" process $proc$libresoc.v:197333$13291 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end attribute \src "libresoc.v:197335.3-197336.57" process $proc$libresoc.v:197335$13292 assign { } { } assign $0\core_bigendian_i$10[0:0]$13293 \core_bigendian_i$10$next sync posedge \clk update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13293 end attribute \src "libresoc.v:197337.3-197338.37" process $proc$libresoc.v:197337$13294 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end attribute \src "libresoc.v:197339.3-197340.47" process $proc$libresoc.v:197339$13295 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end attribute \src "libresoc.v:197341.3-197342.53" process $proc$libresoc.v:197341$13296 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end attribute \src "libresoc.v:197343.3-197344.23" process $proc$libresoc.v:197343$13297 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end attribute \src "libresoc.v:197345.3-197346.41" process $proc$libresoc.v:197345$13298 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end attribute \src "libresoc.v:197347.3-197348.47" process $proc$libresoc.v:197347$13299 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end attribute \src "libresoc.v:197349.3-197350.33" process $proc$libresoc.v:197349$13300 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end attribute \src "libresoc.v:197351.3-197352.45" process $proc$libresoc.v:197351$13301 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end attribute \src "libresoc.v:197353.3-197354.43" process $proc$libresoc.v:197353$13302 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end attribute \src "libresoc.v:197355.3-197356.47" process $proc$libresoc.v:197355$13303 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end attribute \src "libresoc.v:197357.3-197358.47" process $proc$libresoc.v:197357$13304 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end attribute \src "libresoc.v:197359.3-197360.47" process $proc$libresoc.v:197359$13305 assign { } { } assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end attribute \src "libresoc.v:197361.3-197362.37" process $proc$libresoc.v:197361$13306 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end attribute \src "libresoc.v:197363.3-197364.43" process $proc$libresoc.v:197363$13307 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end attribute \src "libresoc.v:197365.3-197366.39" process $proc$libresoc.v:197365$13308 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end attribute \src "libresoc.v:197367.3-197368.49" process $proc$libresoc.v:197367$13309 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end attribute \src "libresoc.v:197369.3-197370.39" process $proc$libresoc.v:197369$13310 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end attribute \src "libresoc.v:197371.3-197372.43" process $proc$libresoc.v:197371$13311 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end attribute \src "libresoc.v:197373.3-197374.27" process $proc$libresoc.v:197373$13312 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end attribute \src "libresoc.v:197375.3-197376.43" process $proc$libresoc.v:197375$13313 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end attribute \src "libresoc.v:197377.3-197378.47" process $proc$libresoc.v:197377$13314 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end attribute \src "libresoc.v:197908.3-197916.6" process $proc$libresoc.v:197908$13315 assign { } { } assign { } { } assign $0\dbg_dmi_addr_i$next[3:0]$13316 $1\dbg_dmi_addr_i$next[3:0]$13317 attribute \src "libresoc.v:197909.5-197909.29" switch \initial attribute \src "libresoc.v:197909.9-197909.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_dmi_addr_i$next[3:0]$13317 4'0000 case assign $1\dbg_dmi_addr_i$next[3:0]$13317 \jtag_dmi0__addr_i end sync always update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13316 end attribute \src "libresoc.v:197917.3-197925.6" process $proc$libresoc.v:197917$13318 assign { } { } assign { } { } assign $0\dbg_dmi_req_i$next[0:0]$13319 $1\dbg_dmi_req_i$next[0:0]$13320 attribute \src "libresoc.v:197918.5-197918.29" switch \initial attribute \src "libresoc.v:197918.9-197918.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_dmi_req_i$next[0:0]$13320 1'0 case assign $1\dbg_dmi_req_i$next[0:0]$13320 \jtag_dmi0__req_i end sync always update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13319 end attribute \src "libresoc.v:197926.3-197981.6" process $proc$libresoc.v:197926$13321 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\core_core_dststep$next[6:0]$13322 $2\core_core_dststep$next[6:0]$13342 assign $0\core_core_maxvl$next[6:0]$13323 $2\core_core_maxvl$next[6:0]$13343 assign $0\core_core_pc$next[63:0]$13324 $2\core_core_pc$next[63:0]$13344 assign $0\core_core_srcstep$next[6:0]$13325 $2\core_core_srcstep$next[6:0]$13345 assign $0\core_core_subvl$next[1:0]$13326 $2\core_core_subvl$next[1:0]$13346 assign $0\core_core_svstep$next[1:0]$13327 $2\core_core_svstep$next[1:0]$13347 assign $0\core_core_vl$next[6:0]$13328 $2\core_core_vl$next[6:0]$13348 assign $0\core_dec$next[63:0]$13329 $2\core_dec$next[63:0]$13349 assign $0\core_eint$next[0:0]$13330 $2\core_eint$next[0:0]$13350 assign $0\core_msr$next[63:0]$13331 $2\core_msr$next[63:0]$13351 attribute \src "libresoc.v:197927.5-197927.29" switch \initial attribute \src "libresoc.v:197927.9-197927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl assign $1\core_core_pc$next[63:0]$13334 \core_core_pc assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep assign $1\core_core_vl$next[6:0]$13338 \core_core_vl assign $1\core_dec$next[63:0]$13339 \core_dec assign $1\core_eint$next[0:0]$13340 \core_eint assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl assign $1\core_core_pc$next[63:0]$13334 \core_core_pc assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep assign $1\core_core_vl$next[6:0]$13338 \core_core_vl assign $1\core_dec$next[63:0]$13339 \core_dec assign $1\core_eint$next[0:0]$13340 \core_eint assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl assign $1\core_core_pc$next[63:0]$13334 \core_core_pc assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep assign $1\core_core_vl$next[6:0]$13338 \core_core_vl assign $1\core_dec$next[63:0]$13339 \core_dec assign $1\core_eint$next[0:0]$13340 \core_eint assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl assign $1\core_core_pc$next[63:0]$13334 \core_core_pc assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep assign $1\core_core_vl$next[6:0]$13338 \core_core_vl assign $1\core_dec$next[63:0]$13339 \core_dec assign $1\core_eint$next[0:0]$13340 \core_eint assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl assign $1\core_core_pc$next[63:0]$13334 \core_core_pc assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep assign $1\core_core_vl$next[6:0]$13338 \core_core_vl assign $1\core_dec$next[63:0]$13339 \core_dec assign $1\core_eint$next[0:0]$13340 \core_eint assign $1\core_msr$next[63:0]$13341 \core_msr attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\core_core_maxvl$next[6:0]$13333 $1\core_core_vl$next[6:0]$13338 $1\core_core_srcstep$next[6:0]$13335 $1\core_core_dststep$next[6:0]$13332 $1\core_core_subvl$next[1:0]$13336 $1\core_core_svstep$next[1:0]$13337 $1\core_dec$next[63:0]$13339 $1\core_eint$next[0:0]$13340 $1\core_msr$next[63:0]$13341 $1\core_core_pc$next[63:0]$13334 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case assign $1\core_core_dststep$next[6:0]$13332 \core_core_dststep assign $1\core_core_maxvl$next[6:0]$13333 \core_core_maxvl assign $1\core_core_pc$next[63:0]$13334 \core_core_pc assign $1\core_core_srcstep$next[6:0]$13335 \core_core_srcstep assign $1\core_core_subvl$next[1:0]$13336 \core_core_subvl assign $1\core_core_svstep$next[1:0]$13337 \core_core_svstep assign $1\core_core_vl$next[6:0]$13338 \core_core_vl assign $1\core_dec$next[63:0]$13339 \core_dec assign $1\core_eint$next[0:0]$13340 \core_eint assign $1\core_msr$next[63:0]$13341 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\core_core_pc$next[63:0]$13344 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\core_msr$next[63:0]$13351 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\core_eint$next[0:0]$13350 1'0 assign $2\core_dec$next[63:0]$13349 64'0000000000000000000000000000000000000000000000000000000000000000 assign $2\core_core_svstep$next[1:0]$13347 2'00 assign $2\core_core_subvl$next[1:0]$13346 2'00 assign $2\core_core_dststep$next[6:0]$13342 7'0000000 assign $2\core_core_srcstep$next[6:0]$13345 7'0000000 assign $2\core_core_vl$next[6:0]$13348 7'0000000 assign $2\core_core_maxvl$next[6:0]$13343 7'0000000 case assign $2\core_core_dststep$next[6:0]$13342 $1\core_core_dststep$next[6:0]$13332 assign $2\core_core_maxvl$next[6:0]$13343 $1\core_core_maxvl$next[6:0]$13333 assign $2\core_core_pc$next[63:0]$13344 $1\core_core_pc$next[63:0]$13334 assign $2\core_core_srcstep$next[6:0]$13345 $1\core_core_srcstep$next[6:0]$13335 assign $2\core_core_subvl$next[1:0]$13346 $1\core_core_subvl$next[1:0]$13336 assign $2\core_core_svstep$next[1:0]$13347 $1\core_core_svstep$next[1:0]$13337 assign $2\core_core_vl$next[6:0]$13348 $1\core_core_vl$next[6:0]$13338 assign $2\core_dec$next[63:0]$13349 $1\core_dec$next[63:0]$13339 assign $2\core_eint$next[0:0]$13350 $1\core_eint$next[0:0]$13340 assign $2\core_msr$next[63:0]$13351 $1\core_msr$next[63:0]$13341 end sync always update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13322 update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13323 update \core_core_pc$next $0\core_core_pc$next[63:0]$13324 update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13325 update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13326 update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13327 update \core_core_vl$next $0\core_core_vl$next[6:0]$13328 update \core_dec$next $0\core_dec$next[63:0]$13329 update \core_eint$next $0\core_eint$next[0:0]$13330 update \core_msr$next $0\core_msr$next[63:0]$13331 end attribute \src "libresoc.v:197982.3-198017.6" process $proc$libresoc.v:197982$13352 assign { } { } assign { } { } assign { } { } assign $0\core_raw_insn_i$next[31:0]$13353 $2\core_raw_insn_i$next[31:0]$13355 attribute \src "libresoc.v:197983.5-197983.29" switch \initial attribute \src "libresoc.v:197983.9-197983.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\core_raw_insn_i$next[31:0]$13354 \dec2_raw_opcode_in case assign $1\core_raw_insn_i$next[31:0]$13354 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_raw_insn_i$next[31:0]$13355 0 case assign $2\core_raw_insn_i$next[31:0]$13355 $1\core_raw_insn_i$next[31:0]$13354 end sync always update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13353 end attribute \src "libresoc.v:198018.3-198053.6" process $proc$libresoc.v:198018$13356 assign { } { } assign { } { } assign { } { } assign $0\core_bigendian_i$10$next[0:0]$13357 $2\core_bigendian_i$10$next[0:0]$13359 attribute \src "libresoc.v:198019.5-198019.29" switch \initial attribute \src "libresoc.v:198019.9-198019.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i case assign $1\core_bigendian_i$10$next[0:0]$13358 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_bigendian_i$10$next[0:0]$13359 1'0 case assign $2\core_bigendian_i$10$next[0:0]$13359 $1\core_bigendian_i$10$next[0:0]$13358 end sync always update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13357 end attribute \src "libresoc.v:198054.3-198089.6" process $proc$libresoc.v:198054$13360 assign { } { } assign { } { } assign { } { } assign $0\core_sv_a_nz$next[0:0]$13361 $2\core_sv_a_nz$next[0:0]$13363 attribute \src "libresoc.v:198055.5-198055.29" switch \initial attribute \src "libresoc.v:198055.9-198055.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\core_sv_a_nz$next[0:0]$13362 \dec2_sv_a_nz case assign $1\core_sv_a_nz$next[0:0]$13362 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_sv_a_nz$next[0:0]$13363 1'0 case assign $2\core_sv_a_nz$next[0:0]$13363 $1\core_sv_a_nz$next[0:0]$13362 end sync always update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13361 end attribute \src "libresoc.v:198090.3-198124.6" process $proc$libresoc.v:198090$13364 assign { } { } assign { } { } assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] attribute \src "libresoc.v:198091.5-198091.29" switch \initial attribute \src "libresoc.v:198091.9-198091.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\exec_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\exec_insn_valid_i[0:0] 1'1 case assign $1\exec_insn_valid_i[0:0] 1'0 end sync always update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] end attribute \src "libresoc.v:198125.3-198168.6" process $proc$libresoc.v:198125$13365 assign { } { } assign { } { } assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] attribute \src "libresoc.v:198126.5-198126.29" switch \initial attribute \src "libresoc.v:198126.9-198126.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\exec_pc_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$244 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\exec_pc_ready_i[0:0] 1'1 case assign $2\exec_pc_ready_i[0:0] 1'0 end case assign $1\exec_pc_ready_i[0:0] 1'0 end sync always update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end attribute \src "libresoc.v:198169.3-198217.6" process $proc$libresoc.v:198169$13366 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] attribute \src "libresoc.v:198170.5-198170.29" switch \initial attribute \src "libresoc.v:198170.9-198170.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\is_last[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\is_last[0:0] $2\is_last[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$250 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_last[0:0] $3\is_last[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\is_last[0:0] \$252 case assign $3\is_last[0:0] 1'0 end case assign $2\is_last[0:0] 1'0 end case assign $1\is_last[0:0] 1'0 end sync always update \is_last $0\is_last[0:0] end attribute \src "libresoc.v:198218.3-198227.6" process $proc$libresoc.v:198218$13367 assign { } { } assign { } { } assign $0\core_wen$11[2:0]$13368 $1\core_wen$11[2:0]$13369 attribute \src "libresoc.v:198219.5-198219.29" switch \initial attribute \src "libresoc.v:198219.9-198219.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:722" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_wen$11[2:0]$13369 3'100 case assign $1\core_wen$11[2:0]$13369 3'000 end sync always update \core_wen$11 $0\core_wen$11[2:0]$13368 end attribute \src "libresoc.v:198228.3-198237.6" process $proc$libresoc.v:198228$13370 assign { } { } assign { } { } assign $0\core_data_i$12[63:0]$13371 $1\core_data_i$12[63:0]$13372 attribute \src "libresoc.v:198229.5-198229.29" switch \initial attribute \src "libresoc.v:198229.9-198229.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:722" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_data_i$12[63:0]$13372 \$254 case assign $1\core_data_i$12[63:0]$13372 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \core_data_i$12 $0\core_data_i$12[63:0]$13371 end attribute \src "libresoc.v:198238.3-198248.6" process $proc$libresoc.v:198238$13373 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] attribute \src "libresoc.v:198239.5-198239.29" switch \initial attribute \src "libresoc.v:198239.9-198239.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\exec_insn_ready_o[0:0] 1'1 case assign $1\exec_insn_ready_o[0:0] 1'0 end sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end attribute \src "libresoc.v:198249.3-198273.6" process $proc$libresoc.v:198249$13374 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] attribute \src "libresoc.v:198250.5-198250.29" switch \initial attribute \src "libresoc.v:198250.9-198250.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_ivalid_i[0:0] 1'1 case assign $2\core_ivalid_i[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:762" switch \$256 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\core_ivalid_i[0:0] 1'1 case assign $3\core_ivalid_i[0:0] 1'0 end case assign $1\core_ivalid_i[0:0] 1'0 end sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end attribute \src "libresoc.v:198274.3-198289.6" process $proc$libresoc.v:198274$13375 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] attribute \src "libresoc.v:198275.5-198275.29" switch \initial attribute \src "libresoc.v:198275.9-198275.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_issue_i[0:0] 1'1 case assign $2\core_issue_i[0:0] 1'0 end case assign $1\core_issue_i[0:0] 1'0 end sync always update \core_issue_i $0\core_issue_i[0:0] end attribute \src "libresoc.v:198290.3-198324.6" process $proc$libresoc.v:198290$13376 assign { } { } assign { } { } assign { } { } assign $0\exec_fsm_state$next[0:0]$13377 $5\exec_fsm_state$next[0:0]$13382 attribute \src "libresoc.v:198291.5-198291.29" switch \initial attribute \src "libresoc.v:198291.9-198291.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\exec_fsm_state$next[0:0]$13378 $2\exec_fsm_state$next[0:0]$13379 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\exec_fsm_state$next[0:0]$13379 1'1 case assign $2\exec_fsm_state$next[0:0]$13379 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\exec_fsm_state$next[0:0]$13378 $3\exec_fsm_state$next[0:0]$13380 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" switch \$258 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\exec_fsm_state$next[0:0]$13380 $4\exec_fsm_state$next[0:0]$13381 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\exec_fsm_state$next[0:0]$13381 1'0 case assign $4\exec_fsm_state$next[0:0]$13381 \exec_fsm_state end case assign $3\exec_fsm_state$next[0:0]$13380 \exec_fsm_state end case assign $1\exec_fsm_state$next[0:0]$13378 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\exec_fsm_state$next[0:0]$13382 1'0 case assign $5\exec_fsm_state$next[0:0]$13382 $1\exec_fsm_state$next[0:0]$13378 end sync always update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13377 end attribute \src "libresoc.v:198325.3-198344.6" process $proc$libresoc.v:198325$13383 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] attribute \src "libresoc.v:198326.5-198326.29" switch \initial attribute \src "libresoc.v:198326.9-198326.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign $1\exec_pc_valid_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" switch \$260 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\exec_pc_valid_o[0:0] 1'1 case assign $2\exec_pc_valid_o[0:0] 1'0 end case assign $1\exec_pc_valid_o[0:0] 1'0 end sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end attribute \src "libresoc.v:198345.3-198354.6" process $proc$libresoc.v:198345$13384 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] attribute \src "libresoc.v:198346.5-198346.29" switch \initial attribute \src "libresoc.v:198346.9-198346.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] case assign $1\core_dmi__addr[4:0] 5'00000 end sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end attribute \src "libresoc.v:198355.3-198364.6" process $proc$libresoc.v:198355$13385 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] attribute \src "libresoc.v:198356.5-198356.29" switch \initial attribute \src "libresoc.v:198356.9-198356.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_dmi__ren[0:0] 1'1 case assign $1\core_dmi__ren[0:0] 1'0 end sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end attribute \src "libresoc.v:198365.3-198373.6" process $proc$libresoc.v:198365$13386 assign { } { } assign { } { } assign $0\d_reg_delay$next[0:0]$13387 $1\d_reg_delay$next[0:0]$13388 attribute \src "libresoc.v:198366.5-198366.29" switch \initial attribute \src "libresoc.v:198366.9-198366.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\d_reg_delay$next[0:0]$13388 1'0 case assign $1\d_reg_delay$next[0:0]$13388 \dbg_d_gpr_req end sync always update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13387 end attribute \src "libresoc.v:198374.3-198383.6" process $proc$libresoc.v:198374$13389 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] attribute \src "libresoc.v:198375.5-198375.29" switch \initial attribute \src "libresoc.v:198375.9-198375.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:987" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o case assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end attribute \src "libresoc.v:198384.3-198393.6" process $proc$libresoc.v:198384$13390 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] attribute \src "libresoc.v:198385.5-198385.29" switch \initial attribute \src "libresoc.v:198385.9-198385.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:987" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_d_gpr_ack[0:0] 1'1 case assign $1\dbg_d_gpr_ack[0:0] 1'0 end sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end attribute \src "libresoc.v:198394.3-198403.6" process $proc$libresoc.v:198394$13391 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] attribute \src "libresoc.v:198395.5-198395.29" switch \initial attribute \src "libresoc.v:198395.9-198395.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:993" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_full_rd2__ren[7:0] 8'11111111 case assign $1\core_full_rd2__ren[7:0] 8'00000000 end sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end attribute \src "libresoc.v:198404.3-198412.6" process $proc$libresoc.v:198404$13392 assign { } { } assign { } { } assign $0\d_cr_delay$next[0:0]$13393 $1\d_cr_delay$next[0:0]$13394 attribute \src "libresoc.v:198405.5-198405.29" switch \initial attribute \src "libresoc.v:198405.9-198405.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\d_cr_delay$next[0:0]$13394 1'0 case assign $1\d_cr_delay$next[0:0]$13394 \dbg_d_cr_req end sync always update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13393 end attribute \src "libresoc.v:198413.3-198422.6" process $proc$libresoc.v:198413$13395 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] attribute \src "libresoc.v:198414.5-198414.29" switch \initial attribute \src "libresoc.v:198414.9-198414.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_d_cr_data[63:0] \$262 case assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end attribute \src "libresoc.v:198423.3-198432.6" process $proc$libresoc.v:198423$13396 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] attribute \src "libresoc.v:198424.5-198424.29" switch \initial attribute \src "libresoc.v:198424.9-198424.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_d_cr_ack[0:0] 1'1 case assign $1\dbg_d_cr_ack[0:0] 1'0 end sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end attribute \src "libresoc.v:198433.3-198442.6" process $proc$libresoc.v:198433$13397 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] attribute \src "libresoc.v:198434.5-198434.29" switch \initial attribute \src "libresoc.v:198434.9-198434.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1003" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_full_rd__ren[2:0] 3'111 case assign $1\core_full_rd__ren[2:0] 3'000 end sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end attribute \src "libresoc.v:198443.3-198451.6" process $proc$libresoc.v:198443$13398 assign { } { } assign { } { } assign $0\d_xer_delay$next[0:0]$13399 $1\d_xer_delay$next[0:0]$13400 attribute \src "libresoc.v:198444.5-198444.29" switch \initial attribute \src "libresoc.v:198444.9-198444.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\d_xer_delay$next[0:0]$13400 1'0 case assign $1\d_xer_delay$next[0:0]$13400 \dbg_d_xer_req end sync always update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13399 end attribute \src "libresoc.v:198452.3-198461.6" process $proc$libresoc.v:198452$13401 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] attribute \src "libresoc.v:198453.5-198453.29" switch \initial attribute \src "libresoc.v:198453.9-198453.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1007" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_d_xer_data[63:0] \$264 case assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end attribute \src "libresoc.v:198462.3-198471.6" process $proc$libresoc.v:198462$13402 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] attribute \src "libresoc.v:198463.5-198463.29" switch \initial attribute \src "libresoc.v:198463.9-198463.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1007" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_d_xer_ack[0:0] 1'1 case assign $1\dbg_d_xer_ack[0:0] 1'0 end sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end attribute \src "libresoc.v:198472.3-198490.6" process $proc$libresoc.v:198472$13403 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] attribute \src "libresoc.v:198473.5-198473.29" switch \initial attribute \src "libresoc.v:198473.9-198473.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_issue__addr[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\core_issue__addr[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\core_issue__addr[2:0] 3'111 case assign $1\core_issue__addr[2:0] 3'000 end sync always update \core_issue__addr $0\core_issue__addr[2:0] end attribute \src "libresoc.v:198491.3-198509.6" process $proc$libresoc.v:198491$13404 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] attribute \src "libresoc.v:198492.5-198492.29" switch \initial attribute \src "libresoc.v:198492.9-198492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_issue__ren[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\core_issue__ren[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\core_issue__ren[0:0] 1'1 case assign $1\core_issue__ren[0:0] 1'0 end sync always update \core_issue__ren $0\core_issue__ren[0:0] end attribute \src "libresoc.v:198510.3-198537.6" process $proc$libresoc.v:198510$13405 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$next[1:0]$13406 $2\fsm_state$next[1:0]$13408 attribute \src "libresoc.v:198511.5-198511.29" switch \initial attribute \src "libresoc.v:198511.9-198511.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\fsm_state$next[1:0]$13407 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\fsm_state$next[1:0]$13407 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\fsm_state$next[1:0]$13407 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\fsm_state$next[1:0]$13407 2'00 case assign $1\fsm_state$next[1:0]$13407 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fsm_state$next[1:0]$13408 2'00 case assign $2\fsm_state$next[1:0]$13408 $1\fsm_state$next[1:0]$13407 end sync always update \fsm_state$next $0\fsm_state$next[1:0]$13406 end attribute \src "libresoc.v:198538.3-198552.6" process $proc$libresoc.v:198538$13409 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] attribute \src "libresoc.v:198539.5-198539.29" switch \initial attribute \src "libresoc.v:198539.9-198539.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\new_dec[63:0] \$266 [63:0] case assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_dec $0\new_dec[63:0] end attribute \src "libresoc.v:198553.3-198575.6" process $proc$libresoc.v:198553$13410 assign { } { } assign { } { } assign $0\core_issue__addr$13[2:0]$13411 $1\core_issue__addr$13[2:0]$13412 attribute \src "libresoc.v:198554.5-198554.29" switch \initial attribute \src "libresoc.v:198554.9-198554.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\core_issue__addr$13[2:0]$13412 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\core_issue__addr$13[2:0]$13412 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign $1\core_issue__addr$13[2:0]$13412 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_issue__addr$13[2:0]$13412 3'111 case assign $1\core_issue__addr$13[2:0]$13412 3'000 end sync always update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13411 end attribute \src "libresoc.v:198576.3-198598.6" process $proc$libresoc.v:198576$13413 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] attribute \src "libresoc.v:198577.5-198577.29" switch \initial attribute \src "libresoc.v:198577.9-198577.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\core_issue__wen[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\core_issue__wen[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign $1\core_issue__wen[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_issue__wen[0:0] 1'1 case assign $1\core_issue__wen[0:0] 1'0 end sync always update \core_issue__wen $0\core_issue__wen[0:0] end attribute \src "libresoc.v:198599.3-198621.6" process $proc$libresoc.v:198599$13414 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] attribute \src "libresoc.v:198600.5-198600.29" switch \initial attribute \src "libresoc.v:198600.9-198600.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\core_issue__data_i[63:0] \new_dec attribute \src "libresoc.v:0.0-0.0" case 2'10 assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_issue__data_i[63:0] \new_tb case assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end attribute \src "libresoc.v:198622.3-198641.6" process $proc$libresoc.v:198622$13415 assign { } { } assign { } { } assign { } { } assign $0\dec2_cur_dec$next[63:0]$13416 $2\dec2_cur_dec$next[63:0]$13418 attribute \src "libresoc.v:198623.5-198623.29" switch \initial attribute \src "libresoc.v:198623.9-198623.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\dec2_cur_dec$next[63:0]$13417 \dec2_cur_dec attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec2_cur_dec$next[63:0]$13417 \new_dec case assign $1\dec2_cur_dec$next[63:0]$13417 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dec2_cur_dec$next[63:0]$13418 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $2\dec2_cur_dec$next[63:0]$13418 $1\dec2_cur_dec$next[63:0]$13417 end sync always update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13416 end attribute \src "libresoc.v:198642.3-198664.6" process $proc$libresoc.v:198642$13419 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] attribute \src "libresoc.v:198643.5-198643.29" switch \initial attribute \src "libresoc.v:198643.9-198643.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\new_tb[63:0] \$269 [63:0] case assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_tb $0\new_tb[63:0] end attribute \src "libresoc.v:198665.3-198673.6" process $proc$libresoc.v:198665$13420 assign { } { } assign { } { } assign $0\dbg_dmi_we_i$next[0:0]$13421 $1\dbg_dmi_we_i$next[0:0]$13422 attribute \src "libresoc.v:198666.5-198666.29" switch \initial attribute \src "libresoc.v:198666.9-198666.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_dmi_we_i$next[0:0]$13422 1'0 case assign $1\dbg_dmi_we_i$next[0:0]$13422 \jtag_dmi0__we_i end sync always update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13421 end attribute \src "libresoc.v:198674.3-198682.6" process $proc$libresoc.v:198674$13423 assign { } { } assign { } { } assign $0\pc_ok_delay$next[0:0]$13424 $1\pc_ok_delay$next[0:0]$13425 attribute \src "libresoc.v:198675.5-198675.29" switch \initial attribute \src "libresoc.v:198675.9-198675.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\pc_ok_delay$next[0:0]$13425 1'0 case assign $1\pc_ok_delay$next[0:0]$13425 \$38 end sync always update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13424 end attribute \src "libresoc.v:198683.3-198698.6" process $proc$libresoc.v:198683$13426 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] attribute \src "libresoc.v:198684.5-198684.29" switch \initial attribute \src "libresoc.v:198684.9-198684.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\pc[63:0] \pc_i case assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:73" switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\pc[63:0] \core_cia__data_o case assign $2\pc[63:0] $1\pc[63:0] end sync always update \pc $0\pc[63:0] end attribute \src "libresoc.v:198699.3-198711.6" process $proc$libresoc.v:198699$13427 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] attribute \src "libresoc.v:198700.5-198700.29" switch \initial attribute \src "libresoc.v:198700.9-198700.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $1\core_cia__ren[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\core_cia__ren[2:0] 3'001 end sync always update \core_cia__ren $0\core_cia__ren[2:0] end attribute \src "libresoc.v:198712.3-198720.6" process $proc$libresoc.v:198712$13428 assign { } { } assign { } { } assign $0\svstate_ok_delay$next[0:0]$13429 $1\svstate_ok_delay$next[0:0]$13430 attribute \src "libresoc.v:198713.5-198713.29" switch \initial attribute \src "libresoc.v:198713.9-198713.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\svstate_ok_delay$next[0:0]$13430 1'0 case assign $1\svstate_ok_delay$next[0:0]$13430 \$40 end sync always update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13429 end attribute \src "libresoc.v:198721.3-198736.6" process $proc$libresoc.v:198721$13431 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] attribute \src "libresoc.v:198722.5-198722.29" switch \initial attribute \src "libresoc.v:198722.9-198722.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\svstate[63:0] \$42 case assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:73" switch \svstate_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\svstate[63:0] \core_sv__data_o case assign $2\svstate[63:0] $1\svstate[63:0] end sync always update \svstate $0\svstate[63:0] end attribute \src "libresoc.v:198737.3-198749.6" process $proc$libresoc.v:198737$13432 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] attribute \src "libresoc.v:198738.5-198738.29" switch \initial attribute \src "libresoc.v:198738.9-198738.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $1\core_sv__ren[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\core_sv__ren[2:0] 3'100 end sync always update \core_sv__ren $0\core_sv__ren[2:0] end attribute \src "libresoc.v:198750.3-198837.6" process $proc$libresoc.v:198750$13433 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] attribute \src "libresoc.v:198751.5-198751.29" switch \initial attribute \src "libresoc.v:198751.9-198751.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_wen[2:0] $2\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\core_wen[2:0] $3\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\core_wen[2:0] 3'001 case assign $3\core_wen[2:0] 3'000 end end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\core_wen[2:0] $4\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_wen[2:0] $5\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\core_wen[2:0] 3'001 case assign $5\core_wen[2:0] 3'000 end case assign $4\core_wen[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\core_wen[2:0] $6\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_wen[2:0] $7\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_wen[2:0] $8\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$64 \$60 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $8\core_wen[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $8\core_wen[2:0] 3'001 case assign $8\core_wen[2:0] 3'000 end case assign $7\core_wen[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $6\core_wen[2:0] $9\core_wen[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:712" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\core_wen[2:0] 3'001 case assign $9\core_wen[2:0] 3'000 end end case assign $1\core_wen[2:0] 3'000 end sync always update \core_wen $0\core_wen[2:0] end attribute \src "libresoc.v:198838.3-198925.6" process $proc$libresoc.v:198838$13434 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] attribute \src "libresoc.v:198839.5-198839.29" switch \initial attribute \src "libresoc.v:198839.9-198839.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\core_data_i[63:0] \pc_i case assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\core_data_i[63:0] $4\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\core_data_i[63:0] $5\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" switch \$74 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\core_data_i[63:0] \nia case assign $5\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\core_data_i[63:0] $6\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_data_i[63:0] $7\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_data_i[63:0] $8\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$86 \$82 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $8\core_data_i[63:0] \nia case assign $8\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case assign $7\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $6\core_data_i[63:0] $9\core_data_i[63:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:712" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\core_data_i[63:0] \pc_i case assign $9\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end end case assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \core_data_i $0\core_data_i[63:0] end attribute \src "libresoc.v:198926.3-198941.6" process $proc$libresoc.v:198926$13435 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] attribute \src "libresoc.v:198927.5-198927.29" switch \initial attribute \src "libresoc.v:198927.9-198927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_msr__ren[2:0] 3'010 case assign $2\core_msr__ren[2:0] 3'000 end case assign $1\core_msr__ren[2:0] 3'000 end sync always update \core_msr__ren $0\core_msr__ren[2:0] end attribute \src "libresoc.v:198942.3-198950.6" process $proc$libresoc.v:198942$13436 assign { } { } assign { } { } assign $0\dbg_dmi_din$next[63:0]$13437 $1\dbg_dmi_din$next[63:0]$13438 attribute \src "libresoc.v:198943.5-198943.29" switch \initial attribute \src "libresoc.v:198943.9-198943.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dbg_dmi_din$next[63:0]$13438 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $1\dbg_dmi_din$next[63:0]$13438 \jtag_dmi0__din end sync always update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13437 end attribute \src "libresoc.v:198951.3-198961.6" process $proc$libresoc.v:198951$13439 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] attribute \src "libresoc.v:198952.5-198952.29" switch \initial attribute \src "libresoc.v:198952.9-198952.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\fetch_pc_ready_o[0:0] 1'1 case assign $1\fetch_pc_ready_o[0:0] 1'0 end sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end attribute \src "libresoc.v:198962.3-198977.6" process $proc$libresoc.v:198962$13440 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] attribute \src "libresoc.v:198963.5-198963.29" switch \initial attribute \src "libresoc.v:198963.9-198963.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\imem_a_pc_i[47:0] \pc [47:0] case assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 end case assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 end sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end attribute \src "libresoc.v:198978.3-198986.6" process $proc$libresoc.v:198978$13441 assign { } { } assign { } { } assign $0\jtag_dmi0__ack_o$next[0:0]$13442 $1\jtag_dmi0__ack_o$next[0:0]$13443 attribute \src "libresoc.v:198979.5-198979.29" switch \initial attribute \src "libresoc.v:198979.9-198979.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_dmi0__ack_o$next[0:0]$13443 1'0 case assign $1\jtag_dmi0__ack_o$next[0:0]$13443 \dbg_dmi_ack_o end sync always update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13442 end attribute \src "libresoc.v:198987.3-199020.6" process $proc$libresoc.v:198987$13444 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] attribute \src "libresoc.v:198988.5-198988.29" switch \initial attribute \src "libresoc.v:198988.9-198988.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\imem_a_valid_i[0:0] 1'1 case assign $2\imem_a_valid_i[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\imem_a_valid_i[0:0] 1'1 case assign $3\imem_a_valid_i[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\imem_a_valid_i[0:0] 1'1 case assign $4\imem_a_valid_i[0:0] 1'0 end case assign $1\imem_a_valid_i[0:0] 1'0 end sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end attribute \src "libresoc.v:199021.3-199054.6" process $proc$libresoc.v:199021$13445 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] attribute \src "libresoc.v:199022.5-199022.29" switch \initial attribute \src "libresoc.v:199022.9-199022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\imem_f_valid_i[0:0] 1'1 case assign $2\imem_f_valid_i[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\imem_f_valid_i[0:0] 1'1 case assign $3\imem_f_valid_i[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\imem_f_valid_i[0:0] 1'1 case assign $4\imem_f_valid_i[0:0] 1'0 end case assign $1\imem_f_valid_i[0:0] 1'0 end sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end attribute \src "libresoc.v:199055.3-199075.6" process $proc$libresoc.v:199055$13446 assign { } { } assign { } { } assign { } { } assign $0\dec2_cur_pc$next[63:0]$13447 $3\dec2_cur_pc$next[63:0]$13450 attribute \src "libresoc.v:199056.5-199056.29" switch \initial attribute \src "libresoc.v:199056.9-199056.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dec2_cur_pc$next[63:0]$13448 $2\dec2_cur_pc$next[63:0]$13449 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dec2_cur_pc$next[63:0]$13449 \pc case assign $2\dec2_cur_pc$next[63:0]$13449 \dec2_cur_pc end case assign $1\dec2_cur_pc$next[63:0]$13448 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dec2_cur_pc$next[63:0]$13450 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\dec2_cur_pc$next[63:0]$13450 $1\dec2_cur_pc$next[63:0]$13448 end sync always update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13447 end attribute \src "libresoc.v:199076.3-199114.6" process $proc$libresoc.v:199076$13451 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cur_cur_dststep$next[6:0]$13452 $4\cur_cur_dststep$next[6:0]$13476 assign $0\cur_cur_maxvl$next[6:0]$13453 $4\cur_cur_maxvl$next[6:0]$13477 assign $0\cur_cur_srcstep$next[6:0]$13454 $4\cur_cur_srcstep$next[6:0]$13478 assign $0\cur_cur_subvl$next[1:0]$13455 $4\cur_cur_subvl$next[1:0]$13479 assign $0\cur_cur_svstep$next[1:0]$13456 $4\cur_cur_svstep$next[1:0]$13480 assign $0\cur_cur_vl$next[6:0]$13457 $4\cur_cur_vl$next[6:0]$13481 attribute \src "libresoc.v:199077.5-199077.29" switch \initial attribute \src "libresoc.v:199077.9-199077.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\cur_cur_dststep$next[6:0]$13458 $2\cur_cur_dststep$next[6:0]$13464 assign $1\cur_cur_maxvl$next[6:0]$13459 $2\cur_cur_maxvl$next[6:0]$13465 assign $1\cur_cur_srcstep$next[6:0]$13460 $2\cur_cur_srcstep$next[6:0]$13466 assign $1\cur_cur_subvl$next[1:0]$13461 $2\cur_cur_subvl$next[1:0]$13467 assign $1\cur_cur_svstep$next[1:0]$13462 $2\cur_cur_svstep$next[1:0]$13468 assign $1\cur_cur_vl$next[6:0]$13463 $2\cur_cur_vl$next[6:0]$13469 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $2\cur_cur_maxvl$next[6:0]$13465 $2\cur_cur_vl$next[6:0]$13469 $2\cur_cur_srcstep$next[6:0]$13466 $2\cur_cur_dststep$next[6:0]$13464 $2\cur_cur_subvl$next[1:0]$13467 $2\cur_cur_svstep$next[1:0]$13468 } \svstate [31:0] case assign $2\cur_cur_dststep$next[6:0]$13464 \cur_cur_dststep assign $2\cur_cur_maxvl$next[6:0]$13465 \cur_cur_maxvl assign $2\cur_cur_srcstep$next[6:0]$13466 \cur_cur_srcstep assign $2\cur_cur_subvl$next[1:0]$13467 \cur_cur_subvl assign $2\cur_cur_svstep$next[1:0]$13468 \cur_cur_svstep assign $2\cur_cur_vl$next[6:0]$13469 \cur_cur_vl end case assign $1\cur_cur_dststep$next[6:0]$13458 \cur_cur_dststep assign $1\cur_cur_maxvl$next[6:0]$13459 \cur_cur_maxvl assign $1\cur_cur_srcstep$next[6:0]$13460 \cur_cur_srcstep assign $1\cur_cur_subvl$next[1:0]$13461 \cur_cur_subvl assign $1\cur_cur_svstep$next[1:0]$13462 \cur_cur_svstep assign $1\cur_cur_vl$next[6:0]$13463 \cur_cur_vl end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:722" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $3\cur_cur_maxvl$next[6:0]$13471 $3\cur_cur_vl$next[6:0]$13475 $3\cur_cur_srcstep$next[6:0]$13472 $3\cur_cur_dststep$next[6:0]$13470 $3\cur_cur_subvl$next[1:0]$13473 $3\cur_cur_svstep$next[1:0]$13474 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case assign $3\cur_cur_dststep$next[6:0]$13470 $1\cur_cur_dststep$next[6:0]$13458 assign $3\cur_cur_maxvl$next[6:0]$13471 $1\cur_cur_maxvl$next[6:0]$13459 assign $3\cur_cur_srcstep$next[6:0]$13472 $1\cur_cur_srcstep$next[6:0]$13460 assign $3\cur_cur_subvl$next[1:0]$13473 $1\cur_cur_subvl$next[1:0]$13461 assign $3\cur_cur_svstep$next[1:0]$13474 $1\cur_cur_svstep$next[1:0]$13462 assign $3\cur_cur_vl$next[6:0]$13475 $1\cur_cur_vl$next[6:0]$13463 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $4\cur_cur_svstep$next[1:0]$13480 2'00 assign $4\cur_cur_subvl$next[1:0]$13479 2'00 assign $4\cur_cur_dststep$next[6:0]$13476 7'0000000 assign $4\cur_cur_srcstep$next[6:0]$13478 7'0000000 assign $4\cur_cur_vl$next[6:0]$13481 7'0000000 assign $4\cur_cur_maxvl$next[6:0]$13477 7'0000000 case assign $4\cur_cur_dststep$next[6:0]$13476 $3\cur_cur_dststep$next[6:0]$13470 assign $4\cur_cur_maxvl$next[6:0]$13477 $3\cur_cur_maxvl$next[6:0]$13471 assign $4\cur_cur_srcstep$next[6:0]$13478 $3\cur_cur_srcstep$next[6:0]$13472 assign $4\cur_cur_subvl$next[1:0]$13479 $3\cur_cur_subvl$next[1:0]$13473 assign $4\cur_cur_svstep$next[1:0]$13480 $3\cur_cur_svstep$next[1:0]$13474 assign $4\cur_cur_vl$next[6:0]$13481 $3\cur_cur_vl$next[6:0]$13475 end sync always update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13452 update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13453 update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13454 update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13455 update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13456 update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13457 end attribute \src "libresoc.v:199115.3-199144.6" process $proc$libresoc.v:199115$13482 assign { } { } assign { } { } assign { } { } assign $0\msr_read$next[0:0]$13483 $4\msr_read$next[0:0]$13487 attribute \src "libresoc.v:199116.5-199116.29" switch \initial attribute \src "libresoc.v:199116.9-199116.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\msr_read$next[0:0]$13484 $2\msr_read$next[0:0]$13485 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\msr_read$next[0:0]$13485 1'0 case assign $2\msr_read$next[0:0]$13485 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\msr_read$next[0:0]$13484 $3\msr_read$next[0:0]$13486 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\msr_read$next[0:0]$13486 1'1 case assign $3\msr_read$next[0:0]$13486 \msr_read end case assign $1\msr_read$next[0:0]$13484 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\msr_read$next[0:0]$13487 1'1 case assign $4\msr_read$next[0:0]$13487 $1\msr_read$next[0:0]$13484 end sync always update \msr_read$next $0\msr_read$next[0:0]$13483 end attribute \src "libresoc.v:199145.3-199153.6" process $proc$libresoc.v:199145$13488 assign { } { } assign { } { } assign $0\jtag_dmi0__dout$next[63:0]$13489 $1\jtag_dmi0__dout$next[63:0]$13490 attribute \src "libresoc.v:199146.5-199146.29" switch \initial attribute \src "libresoc.v:199146.9-199146.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\jtag_dmi0__dout$next[63:0]$13490 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $1\jtag_dmi0__dout$next[63:0]$13490 \dbg_dmi_dout end sync always update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13489 end attribute \src "libresoc.v:199154.3-199207.6" process $proc$libresoc.v:199154$13491 assign { } { } assign { } { } assign { } { } assign $0\fetch_fsm_state$next[1:0]$13492 $6\fetch_fsm_state$next[1:0]$13498 attribute \src "libresoc.v:199155.5-199155.29" switch \initial attribute \src "libresoc.v:199155.9-199155.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\fetch_fsm_state$next[1:0]$13493 $2\fetch_fsm_state$next[1:0]$13494 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fetch_fsm_state$next[1:0]$13494 2'01 case assign $2\fetch_fsm_state$next[1:0]$13494 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\fetch_fsm_state$next[1:0]$13493 $3\fetch_fsm_state$next[1:0]$13495 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\fetch_fsm_state$next[1:0]$13495 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\fetch_fsm_state$next[1:0]$13495 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\fetch_fsm_state$next[1:0]$13493 $4\fetch_fsm_state$next[1:0]$13496 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $4\fetch_fsm_state$next[1:0]$13496 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $4\fetch_fsm_state$next[1:0]$13496 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\fetch_fsm_state$next[1:0]$13493 $5\fetch_fsm_state$next[1:0]$13497 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\fetch_fsm_state$next[1:0]$13497 2'00 case assign $5\fetch_fsm_state$next[1:0]$13497 \fetch_fsm_state end case assign $1\fetch_fsm_state$next[1:0]$13493 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\fetch_fsm_state$next[1:0]$13498 2'00 case assign $6\fetch_fsm_state$next[1:0]$13498 $1\fetch_fsm_state$next[1:0]$13493 end sync always update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13492 end attribute \src "libresoc.v:199208.3-199232.6" process $proc$libresoc.v:199208$13499 assign { } { } assign { } { } assign { } { } assign $0\dec2_cur_msr$next[63:0]$13500 $3\dec2_cur_msr$next[63:0]$13503 attribute \src "libresoc.v:199209.5-199209.29" switch \initial attribute \src "libresoc.v:199209.9-199209.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\dec2_cur_msr$next[63:0]$13501 \dec2_cur_msr attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec2_cur_msr$next[63:0]$13501 $2\dec2_cur_msr$next[63:0]$13502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\dec2_cur_msr$next[63:0]$13502 \core_msr__data_o case assign $2\dec2_cur_msr$next[63:0]$13502 \dec2_cur_msr end case assign $1\dec2_cur_msr$next[63:0]$13501 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\dec2_cur_msr$next[63:0]$13503 64'0000000000000000000000000000000000000000000000000000000000000000 case assign $3\dec2_cur_msr$next[63:0]$13503 $1\dec2_cur_msr$next[63:0]$13501 end sync always update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13500 end attribute \src "libresoc.v:199233.3-199255.6" process $proc$libresoc.v:199233$13504 assign { } { } assign { } { } assign $0\nia$next[63:0]$13505 $1\nia$next[63:0]$13506 attribute \src "libresoc.v:199234.5-199234.29" switch \initial attribute \src "libresoc.v:199234.9-199234.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\nia$next[63:0]$13506 \nia attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\nia$next[63:0]$13506 $2\nia$next[63:0]$13507 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\nia$next[63:0]$13507 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\nia$next[63:0]$13507 \$92 [63:0] end case assign $1\nia$next[63:0]$13506 \nia end sync always update \nia$next $0\nia$next[63:0]$13505 end attribute \src "libresoc.v:199256.3-199290.6" process $proc$libresoc.v:199256$13508 assign { } { } assign { } { } assign $0\dec2_raw_opcode_in$next[31:0]$13509 $1\dec2_raw_opcode_in$next[31:0]$13510 attribute \src "libresoc.v:199257.5-199257.29" switch \initial attribute \src "libresoc.v:199257.9-199257.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\dec2_raw_opcode_in$next[31:0]$13510 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\dec2_raw_opcode_in$next[31:0]$13510 $2\dec2_raw_opcode_in$next[31:0]$13511 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\dec2_raw_opcode_in$next[31:0]$13511 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\dec2_raw_opcode_in$next[31:0]$13511 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\dec2_raw_opcode_in$next[31:0]$13510 $3\dec2_raw_opcode_in$next[31:0]$13512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:357" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\dec2_raw_opcode_in$next[31:0]$13512 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\dec2_raw_opcode_in$next[31:0]$13512 \$99 end case assign $1\dec2_raw_opcode_in$next[31:0]$13510 \dec2_raw_opcode_in end sync always update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13509 end attribute \src "libresoc.v:199291.3-199313.6" process $proc$libresoc.v:199291$13513 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] attribute \src "libresoc.v:199292.5-199292.29" switch \initial attribute \src "libresoc.v:199292.9-199292.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign $1\fetch_insn_valid_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\fetch_insn_valid_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign $1\fetch_insn_valid_o[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\fetch_insn_valid_o[0:0] 1'1 case assign $1\fetch_insn_valid_o[0:0] 1'0 end sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end attribute \src "libresoc.v:199314.3-199400.6" process $proc$libresoc.v:199314$13514 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\new_svstate_dststep[6:0] $1\new_svstate_dststep[6:0] assign $0\new_svstate_maxvl[6:0] $1\new_svstate_maxvl[6:0] assign $0\new_svstate_srcstep[6:0] $1\new_svstate_srcstep[6:0] assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] attribute \src "libresoc.v:199315.5-199315.29" switch \initial attribute \src "libresoc.v:199315.9-199315.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\new_svstate_dststep[6:0] $2\new_svstate_dststep[6:0] assign $1\new_svstate_maxvl[6:0] $2\new_svstate_maxvl[6:0] assign $1\new_svstate_srcstep[6:0] $2\new_svstate_srcstep[6:0] assign $1\new_svstate_subvl[1:0] $2\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $2\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $2\new_svstate_vl[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$110 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\new_svstate_dststep[6:0] \cur_cur_dststep assign $2\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $2\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $2\new_svstate_subvl[1:0] \cur_cur_subvl assign $2\new_svstate_svstep[1:0] \cur_cur_svstep assign $2\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\new_svstate_dststep[6:0] $3\new_svstate_dststep[6:0] assign $2\new_svstate_maxvl[6:0] $3\new_svstate_maxvl[6:0] assign $2\new_svstate_srcstep[6:0] $3\new_svstate_srcstep[6:0] assign $2\new_svstate_subvl[1:0] $3\new_svstate_subvl[1:0] assign $2\new_svstate_svstep[1:0] $3\new_svstate_svstep[1:0] assign $2\new_svstate_vl[6:0] $3\new_svstate_vl[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $3\new_svstate_maxvl[6:0] $3\new_svstate_vl[6:0] $3\new_svstate_srcstep[6:0] $3\new_svstate_dststep[6:0] $3\new_svstate_subvl[1:0] $3\new_svstate_svstep[1:0] } \svstate_i case assign $3\new_svstate_dststep[6:0] \cur_cur_dststep assign $3\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $3\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $3\new_svstate_subvl[1:0] \cur_cur_subvl assign $3\new_svstate_svstep[1:0] \cur_cur_svstep assign $3\new_svstate_vl[6:0] \cur_cur_vl end end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $1\new_svstate_subvl[1:0] \cur_cur_subvl assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $1\new_svstate_subvl[1:0] \cur_cur_subvl assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $1\new_svstate_subvl[1:0] \cur_cur_subvl assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $1\new_svstate_subvl[1:0] \cur_cur_subvl assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $1\new_svstate_subvl[1:0] \cur_cur_subvl assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $1\new_svstate_subvl[1:0] \cur_cur_subvl assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\new_svstate_dststep[6:0] $4\new_svstate_dststep[6:0] assign $1\new_svstate_maxvl[6:0] $4\new_svstate_maxvl[6:0] assign $1\new_svstate_srcstep[6:0] $4\new_svstate_srcstep[6:0] assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\new_svstate_maxvl[6:0] \cur_cur_maxvl assign { } { } assign $4\new_svstate_subvl[1:0] \cur_cur_subvl assign $4\new_svstate_svstep[1:0] \cur_cur_svstep assign $4\new_svstate_vl[6:0] \cur_cur_vl assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0] assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$122 \$118 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $6\new_svstate_dststep[6:0] \cur_cur_dststep assign $6\new_svstate_srcstep[6:0] \cur_cur_srcstep attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign $6\new_svstate_srcstep[6:0] 7'0000000 assign $6\new_svstate_dststep[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign $6\new_svstate_srcstep[6:0] \next_srcstep assign $6\new_svstate_dststep[6:0] \next_dststep end case assign $5\new_svstate_dststep[6:0] \cur_cur_dststep assign $5\new_svstate_srcstep[6:0] \cur_cur_srcstep end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $4\new_svstate_dststep[6:0] $7\new_svstate_dststep[6:0] assign $4\new_svstate_maxvl[6:0] $5\new_svstate_maxvl[6:0] assign $4\new_svstate_srcstep[6:0] $7\new_svstate_srcstep[6:0] assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $5\new_svstate_maxvl[6:0] $5\new_svstate_vl[6:0] $7\new_svstate_srcstep[6:0] $7\new_svstate_dststep[6:0] $5\new_svstate_subvl[1:0] $5\new_svstate_svstep[1:0] } \svstate_i case assign $7\new_svstate_dststep[6:0] \cur_cur_dststep assign $5\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $7\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $5\new_svstate_subvl[1:0] \cur_cur_subvl assign $5\new_svstate_svstep[1:0] \cur_cur_svstep assign $5\new_svstate_vl[6:0] \cur_cur_vl end end case assign $1\new_svstate_dststep[6:0] \cur_cur_dststep assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep assign $1\new_svstate_subvl[1:0] \cur_cur_subvl assign $1\new_svstate_svstep[1:0] \cur_cur_svstep assign $1\new_svstate_vl[6:0] \cur_cur_vl end sync always update \new_svstate_dststep $0\new_svstate_dststep[6:0] update \new_svstate_maxvl $0\new_svstate_maxvl[6:0] update \new_svstate_srcstep $0\new_svstate_srcstep[6:0] update \new_svstate_subvl $0\new_svstate_subvl[1:0] update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end attribute \src "libresoc.v:199401.3-199416.6" process $proc$libresoc.v:199401$13515 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] attribute \src "libresoc.v:199402.5-199402.29" switch \initial attribute \src "libresoc.v:199402.9-199402.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\fetch_pc_valid_i[0:0] $2\fetch_pc_valid_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\fetch_pc_valid_i[0:0] 1'1 case assign $2\fetch_pc_valid_i[0:0] 1'0 end case assign $1\fetch_pc_valid_i[0:0] 1'0 end sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end attribute \src "libresoc.v:199417.3-199524.6" process $proc$libresoc.v:199417$13516 assign { } { } assign { } { } assign { } { } assign $0\issue_fsm_state$next[2:0]$13517 $13\issue_fsm_state$next[2:0]$13530 attribute \src "libresoc.v:199418.5-199418.29" switch \initial attribute \src "libresoc.v:199418.9-199418.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 $2\issue_fsm_state$next[2:0]$13519 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$140 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\issue_fsm_state$next[2:0]$13519 $3\issue_fsm_state$next[2:0]$13520 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\issue_fsm_state$next[2:0]$13520 3'001 case assign $3\issue_fsm_state$next[2:0]$13520 \issue_fsm_state end case assign $2\issue_fsm_state$next[2:0]$13519 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 $4\issue_fsm_state$next[2:0]$13521 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\issue_fsm_state$next[2:0]$13521 $5\issue_fsm_state$next[2:0]$13522 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\issue_fsm_state$next[2:0]$13522 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $5\issue_fsm_state$next[2:0]$13522 3'010 end case assign $4\issue_fsm_state$next[2:0]$13521 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 $6\issue_fsm_state$next[2:0]$13523 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:576" switch \pred_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\issue_fsm_state$next[2:0]$13523 3'100 case assign $6\issue_fsm_state$next[2:0]$13523 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 $7\issue_fsm_state$next[2:0]$13524 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:581" switch \pred_mask_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\issue_fsm_state$next[2:0]$13524 3'101 case assign $7\issue_fsm_state$next[2:0]$13524 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 $8\issue_fsm_state$next[2:0]$13525 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" switch \$146 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\issue_fsm_state$next[2:0]$13525 3'010 case assign $8\issue_fsm_state$next[2:0]$13525 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 3'110 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 $9\issue_fsm_state$next[2:0]$13526 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\issue_fsm_state$next[2:0]$13526 3'111 case assign $9\issue_fsm_state$next[2:0]$13526 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\issue_fsm_state$next[2:0]$13518 $10\issue_fsm_state$next[2:0]$13527 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$152 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $10\issue_fsm_state$next[2:0]$13527 $11\issue_fsm_state$next[2:0]$13528 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $11\issue_fsm_state$next[2:0]$13528 $12\issue_fsm_state$next[2:0]$13529 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$158 \$154 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $12\issue_fsm_state$next[2:0]$13529 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $12\issue_fsm_state$next[2:0]$13529 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $12\issue_fsm_state$next[2:0]$13529 3'101 end case assign $11\issue_fsm_state$next[2:0]$13528 \issue_fsm_state end case assign $10\issue_fsm_state$next[2:0]$13527 \issue_fsm_state end case assign $1\issue_fsm_state$next[2:0]$13518 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $13\issue_fsm_state$next[2:0]$13530 3'000 case assign $13\issue_fsm_state$next[2:0]$13530 $1\issue_fsm_state$next[2:0]$13518 end sync always update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13517 end attribute \src "libresoc.v:199525.3-199579.6" process $proc$libresoc.v:199525$13531 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] attribute \src "libresoc.v:199526.5-199526.29" switch \initial attribute \src "libresoc.v:199526.9-199526.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$164 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$170 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\core_stopped_i[0:0] 1'1 end case assign $1\core_stopped_i[0:0] 1'0 end sync always update \core_stopped_i $0\core_stopped_i[0:0] end attribute \src "libresoc.v:199580.3-199634.6" process $proc$libresoc.v:199580$13532 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] attribute \src "libresoc.v:199581.5-199581.29" switch \initial attribute \src "libresoc.v:199581.9-199581.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$176 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\dbg_core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$182 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $3\dbg_core_stopped_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $3\dbg_core_stopped_i[0:0] 1'1 end case assign $1\dbg_core_stopped_i[0:0] 1'0 end sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end attribute \src "libresoc.v:199635.3-199725.6" process $proc$libresoc.v:199635$13533 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\pc_changed$next[0:0]$13534 $9\pc_changed$next[0:0]$13543 attribute \src "libresoc.v:199636.5-199636.29" switch \initial attribute \src "libresoc.v:199636.9-199636.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\pc_changed$next[0:0]$13535 $2\pc_changed$next[0:0]$13536 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$188 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\pc_changed$next[0:0]$13536 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\pc_changed$next[0:0]$13536 $3\pc_changed$next[0:0]$13537 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:543" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\pc_changed$next[0:0]$13537 1'1 case assign $3\pc_changed$next[0:0]$13537 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\pc_changed$next[0:0]$13535 \pc_changed attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\pc_changed$next[0:0]$13535 $4\pc_changed$next[0:0]$13538 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$194 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $4\pc_changed$next[0:0]$13538 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $4\pc_changed$next[0:0]$13538 $5\pc_changed$next[0:0]$13539 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:712" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\pc_changed$next[0:0]$13539 1'1 case assign $5\pc_changed$next[0:0]$13539 \pc_changed end end case assign $1\pc_changed$next[0:0]$13535 \pc_changed end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $6\pc_changed$next[0:0]$13540 $7\pc_changed$next[0:0]$13541 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\pc_changed$next[0:0]$13541 1'0 case assign $7\pc_changed$next[0:0]$13541 $1\pc_changed$next[0:0]$13535 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\pc_changed$next[0:0]$13540 $8\pc_changed$next[0:0]$13542 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" switch \$196 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\pc_changed$next[0:0]$13542 1'1 case assign $8\pc_changed$next[0:0]$13542 $1\pc_changed$next[0:0]$13535 end case assign $6\pc_changed$next[0:0]$13540 $1\pc_changed$next[0:0]$13535 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\pc_changed$next[0:0]$13543 1'0 case assign $9\pc_changed$next[0:0]$13543 $6\pc_changed$next[0:0]$13540 end sync always update \pc_changed$next $0\pc_changed$next[0:0]$13534 end attribute \src "libresoc.v:199726.3-199806.6" process $proc$libresoc.v:199726$13544 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] attribute \src "libresoc.v:199727.5-199727.29" switch \initial attribute \src "libresoc.v:199727.9-199727.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\update_svstate[0:0] $2\update_svstate[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$204 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\update_svstate[0:0] $3\update_svstate[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\update_svstate[0:0] 1'1 case assign $3\update_svstate[0:0] 1'0 end end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\update_svstate[0:0] $4\update_svstate[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$210 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\update_svstate[0:0] $5\update_svstate[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\update_svstate[0:0] $6\update_svstate[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" switch { \$216 \$212 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign $6\update_svstate[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign $6\update_svstate[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $6\update_svstate[0:0] 1'1 end case assign $5\update_svstate[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $4\update_svstate[0:0] $7\update_svstate[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\update_svstate[0:0] 1'1 case assign $7\update_svstate[0:0] 1'0 end end case assign $1\update_svstate[0:0] 1'0 end sync always update \update_svstate $0\update_svstate[0:0] end attribute \src "libresoc.v:199807.3-199897.6" process $proc$libresoc.v:199807$13545 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sv_changed$next[0:0]$13546 $9\sv_changed$next[0:0]$13555 attribute \src "libresoc.v:199808.5-199808.29" switch \initial attribute \src "libresoc.v:199808.9-199808.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } assign $1\sv_changed$next[0:0]$13547 $2\sv_changed$next[0:0]$13548 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" switch \$222 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\sv_changed$next[0:0]$13548 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\sv_changed$next[0:0]$13548 $3\sv_changed$next[0:0]$13549 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\sv_changed$next[0:0]$13549 1'1 case assign $3\sv_changed$next[0:0]$13549 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'010 assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'110 assign $1\sv_changed$next[0:0]$13547 \sv_changed attribute \src "libresoc.v:0.0-0.0" case 3'111 assign { } { } assign $1\sv_changed$next[0:0]$13547 $4\sv_changed$next[0:0]$13550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \$228 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $4\sv_changed$next[0:0]$13550 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $4\sv_changed$next[0:0]$13550 $5\sv_changed$next[0:0]$13551 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\sv_changed$next[0:0]$13551 1'1 case assign $5\sv_changed$next[0:0]$13551 \sv_changed end end case assign $1\sv_changed$next[0:0]$13547 \sv_changed end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $6\sv_changed$next[0:0]$13552 $7\sv_changed$next[0:0]$13553 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\sv_changed$next[0:0]$13553 1'0 case assign $7\sv_changed$next[0:0]$13553 $1\sv_changed$next[0:0]$13547 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\sv_changed$next[0:0]$13552 $8\sv_changed$next[0:0]$13554 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:765" switch \$230 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $8\sv_changed$next[0:0]$13554 1'1 case assign $8\sv_changed$next[0:0]$13554 $1\sv_changed$next[0:0]$13547 end case assign $6\sv_changed$next[0:0]$13552 $1\sv_changed$next[0:0]$13547 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $9\sv_changed$next[0:0]$13555 1'0 case assign $9\sv_changed$next[0:0]$13555 $6\sv_changed$next[0:0]$13552 end sync always update \sv_changed$next $0\sv_changed$next[0:0]$13546 end attribute \src "libresoc.v:199898.3-199912.6" process $proc$libresoc.v:199898$13556 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] attribute \src "libresoc.v:199899.5-199899.29" switch \initial attribute \src "libresoc.v:199899.9-199899.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\fetch_insn_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\fetch_insn_ready_i[0:0] 1'1 case assign $1\fetch_insn_ready_i[0:0] 1'0 end sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end attribute \src "libresoc.v:199913.3-199958.6" process $proc$libresoc.v:199913$13557 assign { } { } assign { } { } assign { } { } assign $0\insn_done[0:0] $4\insn_done[0:0] attribute \src "libresoc.v:199914.5-199914.29" switch \initial attribute \src "libresoc.v:199914.9-199914.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\insn_done[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\insn_done[0:0] $2\insn_done[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:555" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\insn_done[0:0] $3\insn_done[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" switch \$236 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\insn_done[0:0] 1'1 case assign $3\insn_done[0:0] 1'0 end case assign $2\insn_done[0:0] 1'0 end case assign $1\insn_done[0:0] 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign $4\insn_done[0:0] $1\insn_done[0:0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\insn_done[0:0] $5\insn_done[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:769" switch \$238 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\insn_done[0:0] $6\insn_done[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\insn_done[0:0] 1'1 case assign $6\insn_done[0:0] $1\insn_done[0:0] end case assign $5\insn_done[0:0] $1\insn_done[0:0] end case assign $4\insn_done[0:0] $1\insn_done[0:0] end sync always update \insn_done $0\insn_done[0:0] end attribute \src "libresoc.v:199959.3-199977.6" process $proc$libresoc.v:199959$13558 assign { } { } assign { } { } assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] attribute \src "libresoc.v:199960.5-199960.29" switch \initial attribute \src "libresoc.v:199960.9-199960.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\pred_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\pred_insn_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\pred_insn_valid_i[0:0] 1'1 case assign $1\pred_insn_valid_i[0:0] 1'0 end sync always update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] end attribute \src "libresoc.v:199978.3-200000.6" process $proc$libresoc.v:199978$13559 assign { } { } assign { } { } assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] attribute \src "libresoc.v:199979.5-199979.29" switch \initial attribute \src "libresoc.v:199979.9-199979.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\pred_mask_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\pred_mask_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign $1\pred_mask_ready_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\pred_mask_ready_i[0:0] 1'1 case assign $1\pred_mask_ready_i[0:0] 1'0 end sync always update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] end attribute \src "libresoc.v:200001.3-200122.6" process $proc$libresoc.v:200001$13560 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\core_asmcode$next[7:0]$13561 $1\core_asmcode$next[7:0]$13620 assign $0\core_core_core_cia$next[63:0]$13562 $1\core_core_core_cia$next[63:0]$13621 assign $0\core_core_core_cr_rd$next[7:0]$13563 $1\core_core_core_cr_rd$next[7:0]$13622 assign { } { } assign $0\core_core_core_cr_wr$next[7:0]$13565 $1\core_core_core_cr_wr$next[7:0]$13624 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\core_core_core_fn_unit$next[13:0]$13574 $1\core_core_core_fn_unit$next[13:0]$13633 assign $0\core_core_core_input_carry$next[1:0]$13575 $1\core_core_core_input_carry$next[1:0]$13634 assign $0\core_core_core_insn$next[31:0]$13576 $1\core_core_core_insn$next[31:0]$13635 assign $0\core_core_core_insn_type$next[6:0]$13577 $1\core_core_core_insn_type$next[6:0]$13636 assign $0\core_core_core_is_32bit$next[0:0]$13578 $1\core_core_core_is_32bit$next[0:0]$13637 assign $0\core_core_core_msr$next[63:0]$13579 $1\core_core_core_msr$next[63:0]$13638 assign $0\core_core_core_oe$next[0:0]$13580 $1\core_core_core_oe$next[0:0]$13639 assign { } { } assign $0\core_core_core_rc$next[0:0]$13582 $1\core_core_core_rc$next[0:0]$13641 assign { } { } assign $0\core_core_core_trapaddr$next[12:0]$13584 $1\core_core_core_trapaddr$next[12:0]$13643 assign $0\core_core_core_traptype$next[7:0]$13585 $1\core_core_core_traptype$next[7:0]$13644 assign $0\core_core_cr_in1$next[6:0]$13586 $1\core_core_cr_in1$next[6:0]$13645 assign { } { } assign $0\core_core_cr_in2$1$next[6:0]$13588 $1\core_core_cr_in2$1$next[6:0]$13647 assign $0\core_core_cr_in2$next[6:0]$13589 $1\core_core_cr_in2$next[6:0]$13648 assign { } { } assign { } { } assign $0\core_core_cr_out$next[6:0]$13592 $1\core_core_cr_out$next[6:0]$13651 assign { } { } assign $0\core_core_ea$next[6:0]$13594 $1\core_core_ea$next[6:0]$13653 assign $0\core_core_fast1$next[2:0]$13595 $1\core_core_fast1$next[2:0]$13654 assign { } { } assign $0\core_core_fast2$next[2:0]$13597 $1\core_core_fast2$next[2:0]$13656 assign { } { } assign $0\core_core_fasto1$next[2:0]$13599 $1\core_core_fasto1$next[2:0]$13658 assign $0\core_core_fasto2$next[2:0]$13600 $1\core_core_fasto2$next[2:0]$13659 assign $0\core_core_lk$next[0:0]$13601 $1\core_core_lk$next[0:0]$13660 assign $0\core_core_reg1$next[6:0]$13602 $1\core_core_reg1$next[6:0]$13661 assign { } { } assign $0\core_core_reg2$next[6:0]$13604 $1\core_core_reg2$next[6:0]$13663 assign { } { } assign $0\core_core_reg3$next[6:0]$13606 $1\core_core_reg3$next[6:0]$13665 assign { } { } assign $0\core_core_rego$next[6:0]$13608 $1\core_core_rego$next[6:0]$13667 assign $0\core_core_spr1$next[9:0]$13609 $1\core_core_spr1$next[9:0]$13668 assign { } { } assign $0\core_core_spro$next[9:0]$13611 $1\core_core_spro$next[9:0]$13670 assign $0\core_core_xer_in$next[2:0]$13612 $1\core_core_xer_in$next[2:0]$13671 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\core_xer_out$next[0:0]$13619 $1\core_xer_out$next[0:0]$13678 assign $0\core_core_core_cr_rd_ok$next[0:0]$13564 $2\core_core_core_cr_rd_ok$next[0:0]$13679 assign $0\core_core_core_exc_$signal$3$next[0:0]$13566 $2\core_core_core_exc_$signal$3$next[0:0]$13680 assign $0\core_core_core_exc_$signal$4$next[0:0]$13567 $2\core_core_core_exc_$signal$4$next[0:0]$13681 assign $0\core_core_core_exc_$signal$5$next[0:0]$13568 $2\core_core_core_exc_$signal$5$next[0:0]$13682 assign $0\core_core_core_exc_$signal$6$next[0:0]$13569 $2\core_core_core_exc_$signal$6$next[0:0]$13683 assign $0\core_core_core_exc_$signal$7$next[0:0]$13570 $2\core_core_core_exc_$signal$7$next[0:0]$13684 assign $0\core_core_core_exc_$signal$8$next[0:0]$13571 $2\core_core_core_exc_$signal$8$next[0:0]$13685 assign $0\core_core_core_exc_$signal$9$next[0:0]$13572 $2\core_core_core_exc_$signal$9$next[0:0]$13686 assign $0\core_core_core_exc_$signal$next[0:0]$13573 $2\core_core_core_exc_$signal$next[0:0]$13687 assign $0\core_core_core_oe_ok$next[0:0]$13581 $2\core_core_core_oe_ok$next[0:0]$13688 assign $0\core_core_core_rc_ok$next[0:0]$13583 $2\core_core_core_rc_ok$next[0:0]$13689 assign $0\core_core_cr_in1_ok$next[0:0]$13587 $2\core_core_cr_in1_ok$next[0:0]$13690 assign $0\core_core_cr_in2_ok$2$next[0:0]$13590 $2\core_core_cr_in2_ok$2$next[0:0]$13691 assign $0\core_core_cr_in2_ok$next[0:0]$13591 $2\core_core_cr_in2_ok$next[0:0]$13692 assign $0\core_core_cr_wr_ok$next[0:0]$13593 $2\core_core_cr_wr_ok$next[0:0]$13693 assign $0\core_core_fast1_ok$next[0:0]$13596 $2\core_core_fast1_ok$next[0:0]$13694 assign $0\core_core_fast2_ok$next[0:0]$13598 $2\core_core_fast2_ok$next[0:0]$13695 assign $0\core_core_reg1_ok$next[0:0]$13603 $2\core_core_reg1_ok$next[0:0]$13696 assign $0\core_core_reg2_ok$next[0:0]$13605 $2\core_core_reg2_ok$next[0:0]$13697 assign $0\core_core_reg3_ok$next[0:0]$13607 $2\core_core_reg3_ok$next[0:0]$13698 assign $0\core_core_spr1_ok$next[0:0]$13610 $2\core_core_spr1_ok$next[0:0]$13699 assign $0\core_cr_out_ok$next[0:0]$13613 $2\core_cr_out_ok$next[0:0]$13700 assign $0\core_ea_ok$next[0:0]$13614 $2\core_ea_ok$next[0:0]$13701 assign $0\core_fasto1_ok$next[0:0]$13615 $2\core_fasto1_ok$next[0:0]$13702 assign $0\core_fasto2_ok$next[0:0]$13616 $2\core_fasto2_ok$next[0:0]$13703 assign $0\core_rego_ok$next[0:0]$13617 $2\core_rego_ok$next[0:0]$13704 assign $0\core_spro_ok$next[0:0]$13618 $2\core_spro_ok$next[0:0]$13705 attribute \src "libresoc.v:200002.5-200002.29" switch \initial attribute \src "libresoc.v:200002.9-200002.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:526" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" case 3'000 assign $1\core_asmcode$next[7:0]$13620 \core_asmcode assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok assign $1\core_core_ea$next[6:0]$13653 \core_core_ea assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 assign $1\core_core_lk$next[0:0]$13660 \core_core_lk assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok assign $1\core_core_rego$next[6:0]$13667 \core_core_rego assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok assign $1\core_core_spro$next[9:0]$13670 \core_core_spro assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'001 assign $1\core_asmcode$next[7:0]$13620 \core_asmcode assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok assign $1\core_core_ea$next[6:0]$13653 \core_core_ea assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 assign $1\core_core_lk$next[0:0]$13660 \core_core_lk assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok assign $1\core_core_rego$next[6:0]$13667 \core_core_rego assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok assign $1\core_core_spro$next[9:0]$13670 \core_core_spro assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok assign 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\core_core_core_exc_$signal$7 assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok assign $1\core_core_ea$next[6:0]$13653 \core_core_ea assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 assign $1\core_core_lk$next[0:0]$13660 \core_core_lk assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok assign $1\core_core_rego$next[6:0]$13667 \core_core_rego assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok assign $1\core_core_spro$next[9:0]$13670 \core_core_spro assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'100 assign $1\core_asmcode$next[7:0]$13620 \core_asmcode assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok assign $1\core_core_ea$next[6:0]$13653 \core_core_ea assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 assign $1\core_core_lk$next[0:0]$13660 \core_core_lk assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok assign $1\core_core_rego$next[6:0]$13667 \core_core_rego assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok assign $1\core_core_spro$next[9:0]$13670 \core_core_spro assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'101 assign $1\core_asmcode$next[7:0]$13620 \core_asmcode assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok assign $1\core_core_ea$next[6:0]$13653 \core_core_ea assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 assign $1\core_core_lk$next[0:0]$13660 \core_core_lk assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok assign $1\core_core_rego$next[6:0]$13667 \core_core_rego assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok assign $1\core_core_spro$next[9:0]$13670 \core_core_spro assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok assign $1\core_xer_out$next[0:0]$13678 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\core_core_core_is_32bit$next[0:0]$13637 $1\core_core_cr_wr_ok$next[0:0]$13652 $1\core_core_core_cr_wr$next[7:0]$13624 $1\core_core_core_cr_rd_ok$next[0:0]$13623 $1\core_core_core_cr_rd$next[7:0]$13622 $1\core_core_core_trapaddr$next[12:0]$13643 $1\core_core_core_exc_$signal$9$next[0:0]$13631 $1\core_core_core_exc_$signal$8$next[0:0]$13630 $1\core_core_core_exc_$signal$7$next[0:0]$13629 $1\core_core_core_exc_$signal$6$next[0:0]$13628 $1\core_core_core_exc_$signal$5$next[0:0]$13627 $1\core_core_core_exc_$signal$4$next[0:0]$13626 $1\core_core_core_exc_$signal$3$next[0:0]$13625 $1\core_core_core_exc_$signal$next[0:0]$13632 $1\core_core_core_traptype$next[7:0]$13644 $1\core_core_core_input_carry$next[1:0]$13634 $1\core_core_core_oe_ok$next[0:0]$13640 $1\core_core_core_oe$next[0:0]$13639 $1\core_core_core_rc_ok$next[0:0]$13642 $1\core_core_core_rc$next[0:0]$13641 $1\core_core_lk$next[0:0]$13660 $1\core_core_core_fn_unit$next[13:0]$13633 $1\core_core_core_insn_type$next[6:0]$13636 $1\core_core_core_insn$next[31:0]$13635 $1\core_core_core_cia$next[63:0]$13621 $1\core_core_core_msr$next[63:0]$13638 $1\core_cr_out_ok$next[0:0]$13672 $1\core_core_cr_out$next[6:0]$13651 $1\core_core_cr_in2_ok$2$next[0:0]$13649 $1\core_core_cr_in2$1$next[6:0]$13647 $1\core_core_cr_in2_ok$next[0:0]$13650 $1\core_core_cr_in2$next[6:0]$13648 $1\core_core_cr_in1_ok$next[0:0]$13646 $1\core_core_cr_in1$next[6:0]$13645 $1\core_fasto2_ok$next[0:0]$13675 $1\core_core_fasto2$next[2:0]$13659 $1\core_fasto1_ok$next[0:0]$13674 $1\core_core_fasto1$next[2:0]$13658 $1\core_core_fast2_ok$next[0:0]$13657 $1\core_core_fast2$next[2:0]$13656 $1\core_core_fast1_ok$next[0:0]$13655 $1\core_core_fast1$next[2:0]$13654 $1\core_xer_out$next[0:0]$13678 $1\core_core_xer_in$next[2:0]$13671 $1\core_core_spr1_ok$next[0:0]$13669 $1\core_core_spr1$next[9:0]$13668 $1\core_spro_ok$next[0:0]$13677 $1\core_core_spro$next[9:0]$13670 $1\core_core_reg3_ok$next[0:0]$13666 $1\core_core_reg3$next[6:0]$13665 $1\core_core_reg2_ok$next[0:0]$13664 $1\core_core_reg2$next[6:0]$13663 $1\core_core_reg1_ok$next[0:0]$13662 $1\core_core_reg1$next[6:0]$13661 $1\core_ea_ok$next[0:0]$13673 $1\core_core_ea$next[6:0]$13653 $1\core_rego_ok$next[0:0]$13676 $1\core_core_rego$next[6:0]$13667 $1\core_asmcode$next[7:0]$13620 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case assign $1\core_asmcode$next[7:0]$13620 \core_asmcode assign $1\core_core_core_cia$next[63:0]$13621 \core_core_core_cia assign $1\core_core_core_cr_rd$next[7:0]$13622 \core_core_core_cr_rd assign $1\core_core_core_cr_rd_ok$next[0:0]$13623 \core_core_core_cr_rd_ok assign $1\core_core_core_cr_wr$next[7:0]$13624 \core_core_core_cr_wr assign $1\core_core_core_exc_$signal$3$next[0:0]$13625 \core_core_core_exc_$signal$3 assign $1\core_core_core_exc_$signal$4$next[0:0]$13626 \core_core_core_exc_$signal$4 assign $1\core_core_core_exc_$signal$5$next[0:0]$13627 \core_core_core_exc_$signal$5 assign $1\core_core_core_exc_$signal$6$next[0:0]$13628 \core_core_core_exc_$signal$6 assign $1\core_core_core_exc_$signal$7$next[0:0]$13629 \core_core_core_exc_$signal$7 assign $1\core_core_core_exc_$signal$8$next[0:0]$13630 \core_core_core_exc_$signal$8 assign $1\core_core_core_exc_$signal$9$next[0:0]$13631 \core_core_core_exc_$signal$9 assign $1\core_core_core_exc_$signal$next[0:0]$13632 \core_core_core_exc_$signal assign $1\core_core_core_fn_unit$next[13:0]$13633 \core_core_core_fn_unit assign $1\core_core_core_input_carry$next[1:0]$13634 \core_core_core_input_carry assign $1\core_core_core_insn$next[31:0]$13635 \core_core_core_insn assign $1\core_core_core_insn_type$next[6:0]$13636 \core_core_core_insn_type assign $1\core_core_core_is_32bit$next[0:0]$13637 \core_core_core_is_32bit assign $1\core_core_core_msr$next[63:0]$13638 \core_core_core_msr assign $1\core_core_core_oe$next[0:0]$13639 \core_core_core_oe assign $1\core_core_core_oe_ok$next[0:0]$13640 \core_core_core_oe_ok assign $1\core_core_core_rc$next[0:0]$13641 \core_core_core_rc assign $1\core_core_core_rc_ok$next[0:0]$13642 \core_core_core_rc_ok assign $1\core_core_core_trapaddr$next[12:0]$13643 \core_core_core_trapaddr assign $1\core_core_core_traptype$next[7:0]$13644 \core_core_core_traptype assign $1\core_core_cr_in1$next[6:0]$13645 \core_core_cr_in1 assign $1\core_core_cr_in1_ok$next[0:0]$13646 \core_core_cr_in1_ok assign $1\core_core_cr_in2$1$next[6:0]$13647 \core_core_cr_in2$1 assign $1\core_core_cr_in2$next[6:0]$13648 \core_core_cr_in2 assign $1\core_core_cr_in2_ok$2$next[0:0]$13649 \core_core_cr_in2_ok$2 assign $1\core_core_cr_in2_ok$next[0:0]$13650 \core_core_cr_in2_ok assign $1\core_core_cr_out$next[6:0]$13651 \core_core_cr_out assign $1\core_core_cr_wr_ok$next[0:0]$13652 \core_core_cr_wr_ok assign $1\core_core_ea$next[6:0]$13653 \core_core_ea assign $1\core_core_fast1$next[2:0]$13654 \core_core_fast1 assign $1\core_core_fast1_ok$next[0:0]$13655 \core_core_fast1_ok assign $1\core_core_fast2$next[2:0]$13656 \core_core_fast2 assign $1\core_core_fast2_ok$next[0:0]$13657 \core_core_fast2_ok assign $1\core_core_fasto1$next[2:0]$13658 \core_core_fasto1 assign $1\core_core_fasto2$next[2:0]$13659 \core_core_fasto2 assign $1\core_core_lk$next[0:0]$13660 \core_core_lk assign $1\core_core_reg1$next[6:0]$13661 \core_core_reg1 assign $1\core_core_reg1_ok$next[0:0]$13662 \core_core_reg1_ok assign $1\core_core_reg2$next[6:0]$13663 \core_core_reg2 assign $1\core_core_reg2_ok$next[0:0]$13664 \core_core_reg2_ok assign $1\core_core_reg3$next[6:0]$13665 \core_core_reg3 assign $1\core_core_reg3_ok$next[0:0]$13666 \core_core_reg3_ok assign $1\core_core_rego$next[6:0]$13667 \core_core_rego assign $1\core_core_spr1$next[9:0]$13668 \core_core_spr1 assign $1\core_core_spr1_ok$next[0:0]$13669 \core_core_spr1_ok assign $1\core_core_spro$next[9:0]$13670 \core_core_spro assign $1\core_core_xer_in$next[2:0]$13671 \core_core_xer_in assign $1\core_cr_out_ok$next[0:0]$13672 \core_cr_out_ok assign $1\core_ea_ok$next[0:0]$13673 \core_ea_ok assign $1\core_fasto1_ok$next[0:0]$13674 \core_fasto1_ok assign $1\core_fasto2_ok$next[0:0]$13675 \core_fasto2_ok assign $1\core_rego_ok$next[0:0]$13676 \core_rego_ok assign $1\core_spro_ok$next[0:0]$13677 \core_spro_ok assign $1\core_xer_out$next[0:0]$13678 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\core_rego_ok$next[0:0]$13704 1'0 assign $2\core_ea_ok$next[0:0]$13701 1'0 assign $2\core_core_reg1_ok$next[0:0]$13696 1'0 assign $2\core_core_reg2_ok$next[0:0]$13697 1'0 assign $2\core_core_reg3_ok$next[0:0]$13698 1'0 assign $2\core_spro_ok$next[0:0]$13705 1'0 assign $2\core_core_spr1_ok$next[0:0]$13699 1'0 assign $2\core_core_fast1_ok$next[0:0]$13694 1'0 assign $2\core_core_fast2_ok$next[0:0]$13695 1'0 assign $2\core_fasto1_ok$next[0:0]$13702 1'0 assign $2\core_fasto2_ok$next[0:0]$13703 1'0 assign $2\core_core_cr_in1_ok$next[0:0]$13690 1'0 assign $2\core_core_cr_in2_ok$next[0:0]$13692 1'0 assign $2\core_core_cr_in2_ok$2$next[0:0]$13691 1'0 assign $2\core_cr_out_ok$next[0:0]$13700 1'0 assign $2\core_core_core_rc_ok$next[0:0]$13689 1'0 assign $2\core_core_core_oe_ok$next[0:0]$13688 1'0 assign $2\core_core_core_exc_$signal$next[0:0]$13687 1'0 assign $2\core_core_core_exc_$signal$3$next[0:0]$13680 1'0 assign $2\core_core_core_exc_$signal$4$next[0:0]$13681 1'0 assign $2\core_core_core_exc_$signal$5$next[0:0]$13682 1'0 assign $2\core_core_core_exc_$signal$6$next[0:0]$13683 1'0 assign $2\core_core_core_exc_$signal$7$next[0:0]$13684 1'0 assign $2\core_core_core_exc_$signal$8$next[0:0]$13685 1'0 assign $2\core_core_core_exc_$signal$9$next[0:0]$13686 1'0 assign $2\core_core_core_cr_rd_ok$next[0:0]$13679 1'0 assign $2\core_core_cr_wr_ok$next[0:0]$13693 1'0 case assign $2\core_core_core_cr_rd_ok$next[0:0]$13679 $1\core_core_core_cr_rd_ok$next[0:0]$13623 assign $2\core_core_core_exc_$signal$3$next[0:0]$13680 $1\core_core_core_exc_$signal$3$next[0:0]$13625 assign $2\core_core_core_exc_$signal$4$next[0:0]$13681 $1\core_core_core_exc_$signal$4$next[0:0]$13626 assign $2\core_core_core_exc_$signal$5$next[0:0]$13682 $1\core_core_core_exc_$signal$5$next[0:0]$13627 assign $2\core_core_core_exc_$signal$6$next[0:0]$13683 $1\core_core_core_exc_$signal$6$next[0:0]$13628 assign $2\core_core_core_exc_$signal$7$next[0:0]$13684 $1\core_core_core_exc_$signal$7$next[0:0]$13629 assign $2\core_core_core_exc_$signal$8$next[0:0]$13685 $1\core_core_core_exc_$signal$8$next[0:0]$13630 assign $2\core_core_core_exc_$signal$9$next[0:0]$13686 $1\core_core_core_exc_$signal$9$next[0:0]$13631 assign $2\core_core_core_exc_$signal$next[0:0]$13687 $1\core_core_core_exc_$signal$next[0:0]$13632 assign $2\core_core_core_oe_ok$next[0:0]$13688 $1\core_core_core_oe_ok$next[0:0]$13640 assign $2\core_core_core_rc_ok$next[0:0]$13689 $1\core_core_core_rc_ok$next[0:0]$13642 assign $2\core_core_cr_in1_ok$next[0:0]$13690 $1\core_core_cr_in1_ok$next[0:0]$13646 assign $2\core_core_cr_in2_ok$2$next[0:0]$13691 $1\core_core_cr_in2_ok$2$next[0:0]$13649 assign $2\core_core_cr_in2_ok$next[0:0]$13692 $1\core_core_cr_in2_ok$next[0:0]$13650 assign $2\core_core_cr_wr_ok$next[0:0]$13693 $1\core_core_cr_wr_ok$next[0:0]$13652 assign $2\core_core_fast1_ok$next[0:0]$13694 $1\core_core_fast1_ok$next[0:0]$13655 assign $2\core_core_fast2_ok$next[0:0]$13695 $1\core_core_fast2_ok$next[0:0]$13657 assign $2\core_core_reg1_ok$next[0:0]$13696 $1\core_core_reg1_ok$next[0:0]$13662 assign $2\core_core_reg2_ok$next[0:0]$13697 $1\core_core_reg2_ok$next[0:0]$13664 assign $2\core_core_reg3_ok$next[0:0]$13698 $1\core_core_reg3_ok$next[0:0]$13666 assign $2\core_core_spr1_ok$next[0:0]$13699 $1\core_core_spr1_ok$next[0:0]$13669 assign $2\core_cr_out_ok$next[0:0]$13700 $1\core_cr_out_ok$next[0:0]$13672 assign $2\core_ea_ok$next[0:0]$13701 $1\core_ea_ok$next[0:0]$13673 assign $2\core_fasto1_ok$next[0:0]$13702 $1\core_fasto1_ok$next[0:0]$13674 assign $2\core_fasto2_ok$next[0:0]$13703 $1\core_fasto2_ok$next[0:0]$13675 assign $2\core_rego_ok$next[0:0]$13704 $1\core_rego_ok$next[0:0]$13676 assign $2\core_spro_ok$next[0:0]$13705 $1\core_spro_ok$next[0:0]$13677 end sync always update \core_asmcode$next $0\core_asmcode$next[7:0]$13561 update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13562 update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13563 update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13564 update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13565 update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13566 update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13567 update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13568 update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13569 update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13570 update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13571 update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13572 update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13573 update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13574 update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13575 update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13576 update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13577 update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13578 update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13579 update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13580 update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13581 update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13582 update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13583 update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13584 update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13585 update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13586 update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13587 update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13588 update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13589 update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13590 update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13591 update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13592 update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13593 update \core_core_ea$next $0\core_core_ea$next[6:0]$13594 update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13595 update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13596 update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13597 update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13598 update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13599 update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13600 update \core_core_lk$next $0\core_core_lk$next[0:0]$13601 update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13602 update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13603 update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13604 update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13605 update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13606 update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13607 update \core_core_rego$next $0\core_core_rego$next[6:0]$13608 update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13609 update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13610 update \core_core_spro$next $0\core_core_spro$next[9:0]$13611 update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13612 update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13613 update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13614 update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13615 update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13616 update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13617 update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13618 update \core_xer_out$next $0\core_xer_out$next[0:0]$13619 end attribute \src "libresoc.v:200123.3-200131.6" process $proc$libresoc.v:200123$13706 assign { } { } assign { } { } assign $0\dec2_cur_eint$next[0:0]$13707 $1\dec2_cur_eint$next[0:0]$13708 attribute \src "libresoc.v:200124.5-200124.29" switch \initial attribute \src "libresoc.v:200124.9-200124.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dec2_cur_eint$next[0:0]$13708 1'0 case assign $1\dec2_cur_eint$next[0:0]$13708 \xics_icp_core_irq_o end sync always update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13707 end attribute \src "libresoc.v:200132.3-200141.6" process $proc$libresoc.v:200132$13709 assign { } { } assign { } { } assign $0\delay$next[1:0]$13710 $1\delay$next[1:0]$13711 attribute \src "libresoc.v:200133.5-200133.29" switch \initial attribute \src "libresoc.v:200133.9-200133.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:830" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\delay$next[1:0]$13711 \$25 [1:0] case assign $1\delay$next[1:0]$13711 \delay end sync always update \delay$next $0\delay$next[1:0]$13710 end connect \$101 $add$libresoc.v:197050$13081_Y connect \$103 $mul$libresoc.v:197051$13082_Y connect \$99 $shr$libresoc.v:197052$13083_Y [31:0] connect \$106 $not$libresoc.v:197053$13084_Y connect \$108 $not$libresoc.v:197054$13085_Y connect \$110 $and$libresoc.v:197055$13086_Y connect \$112 $not$libresoc.v:197056$13087_Y connect \$114 $not$libresoc.v:197057$13088_Y connect \$116 $and$libresoc.v:197058$13089_Y connect \$118 $or$libresoc.v:197059$13090_Y connect \$120 1'1 connect \$122 $or$libresoc.v:197061$13091_Y connect \$125 $add$libresoc.v:197062$13092_Y connect \$128 $add$libresoc.v:197063$13093_Y connect \$130 $not$libresoc.v:197064$13094_Y connect \$132 $not$libresoc.v:197065$13095_Y connect \$134 $and$libresoc.v:197066$13096_Y connect \$136 $not$libresoc.v:197067$13097_Y connect \$138 $not$libresoc.v:197068$13098_Y connect \$140 $and$libresoc.v:197069$13099_Y connect \$142 $eq$libresoc.v:197070$13100_Y connect \$144 $and$libresoc.v:197071$13101_Y connect \$146 $not$libresoc.v:197072$13102_Y connect \$148 $not$libresoc.v:197073$13103_Y connect \$150 $not$libresoc.v:197074$13104_Y connect \$152 $and$libresoc.v:197075$13105_Y connect \$154 $or$libresoc.v:197076$13106_Y connect \$156 1'1 connect \$158 $or$libresoc.v:197078$13107_Y connect \$160 $not$libresoc.v:197079$13108_Y connect \$162 $not$libresoc.v:197080$13109_Y connect \$164 $and$libresoc.v:197081$13110_Y connect \$166 $not$libresoc.v:197082$13111_Y connect \$168 $not$libresoc.v:197083$13112_Y connect \$170 $and$libresoc.v:197084$13113_Y connect \$172 $not$libresoc.v:197085$13114_Y connect \$174 $not$libresoc.v:197086$13115_Y connect \$176 $and$libresoc.v:197087$13116_Y connect \$178 $not$libresoc.v:197088$13117_Y connect \$180 $not$libresoc.v:197089$13118_Y connect \$182 $and$libresoc.v:197090$13119_Y connect \$184 $not$libresoc.v:197091$13120_Y connect \$186 $not$libresoc.v:197092$13121_Y connect \$188 $and$libresoc.v:197093$13122_Y connect \$190 $not$libresoc.v:197094$13123_Y connect \$192 $not$libresoc.v:197095$13124_Y connect \$194 $and$libresoc.v:197096$13125_Y connect \$197 $and$libresoc.v:197097$13126_Y connect \$196 $reduce_or$libresoc.v:197098$13127_Y connect \$200 $not$libresoc.v:197099$13128_Y connect \$202 $not$libresoc.v:197100$13129_Y connect \$204 $and$libresoc.v:197101$13130_Y connect \$206 $not$libresoc.v:197102$13131_Y connect \$208 $not$libresoc.v:197103$13132_Y connect \$210 $and$libresoc.v:197104$13133_Y connect \$212 $or$libresoc.v:197105$13134_Y connect \$214 1'1 connect \$216 $or$libresoc.v:197107$13135_Y connect \$218 $not$libresoc.v:197108$13136_Y connect \$220 $not$libresoc.v:197109$13137_Y connect \$222 $and$libresoc.v:197110$13138_Y connect \$224 $not$libresoc.v:197111$13139_Y connect \$226 $not$libresoc.v:197112$13140_Y connect \$228 $and$libresoc.v:197113$13141_Y connect \$231 $and$libresoc.v:197114$13142_Y connect \$230 $reduce_or$libresoc.v:197115$13143_Y connect \$234 $eq$libresoc.v:197116$13144_Y connect \$236 $and$libresoc.v:197117$13145_Y connect \$238 $not$libresoc.v:197118$13146_Y connect \$23 $ne$libresoc.v:197119$13147_Y connect \$240 $not$libresoc.v:197120$13148_Y connect \$242 $not$libresoc.v:197121$13149_Y connect \$244 $and$libresoc.v:197122$13150_Y connect \$246 $not$libresoc.v:197123$13151_Y connect \$248 $not$libresoc.v:197124$13152_Y connect \$250 $and$libresoc.v:197125$13153_Y connect \$252 $eq$libresoc.v:197126$13154_Y connect \$254 $pos$libresoc.v:197127$13155_Y connect \$256 $ne$libresoc.v:197128$13156_Y connect \$258 $not$libresoc.v:197129$13157_Y connect \$260 $not$libresoc.v:197130$13158_Y connect \$262 $pos$libresoc.v:197131$13160_Y connect \$264 $pos$libresoc.v:197132$13162_Y connect \$267 $sub$libresoc.v:197133$13163_Y connect \$26 $sub$libresoc.v:197134$13164_Y connect \$270 $add$libresoc.v:197135$13165_Y connect \$28 $or$libresoc.v:197136$13166_Y connect \$30 $or$libresoc.v:197137$13167_Y connect \$32 $ne$libresoc.v:197138$13168_Y connect \$34 $not$libresoc.v:197139$13169_Y connect \$36 $and$libresoc.v:197140$13170_Y connect \$38 $not$libresoc.v:197141$13171_Y connect \$40 $not$libresoc.v:197142$13172_Y connect \$42 $pos$libresoc.v:197143$13174_Y connect \$44 $not$libresoc.v:197144$13175_Y connect \$46 $not$libresoc.v:197145$13176_Y connect \$48 $and$libresoc.v:197146$13177_Y connect \$50 $eq$libresoc.v:197147$13178_Y connect \$52 $and$libresoc.v:197148$13179_Y connect \$54 $not$libresoc.v:197149$13180_Y connect \$56 $not$libresoc.v:197150$13181_Y connect \$58 $and$libresoc.v:197151$13182_Y connect \$60 $or$libresoc.v:197152$13183_Y connect \$62 1'1 connect \$64 $or$libresoc.v:197154$13184_Y connect \$66 $not$libresoc.v:197155$13185_Y connect \$68 $not$libresoc.v:197156$13186_Y connect \$70 $and$libresoc.v:197157$13187_Y connect \$72 $eq$libresoc.v:197158$13188_Y connect \$74 $and$libresoc.v:197159$13189_Y connect \$76 $not$libresoc.v:197160$13190_Y connect \$78 $not$libresoc.v:197161$13191_Y connect \$80 $and$libresoc.v:197162$13192_Y connect \$82 $or$libresoc.v:197163$13193_Y connect \$84 1'1 connect \$86 $or$libresoc.v:197165$13194_Y connect \$88 $not$libresoc.v:197166$13195_Y connect \$90 $not$libresoc.v:197167$13196_Y connect \$93 $add$libresoc.v:197168$13197_Y connect \$96 $mul$libresoc.v:197169$13198_Y connect \$95 $shr$libresoc.v:197170$13199_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 connect \$124 \$125 connect \$127 \$128 connect \$266 \$267 connect \$269 \$270 connect \dec2_sv_a_nz 1'0 connect \svstate_i_ok 1'0 connect \svstate_i 0 connect \is_svp64_mode 1'0 connect \pred_insn_ready_o 1'0 connect \pred_mask_valid_o 1'0 connect \next_dststep \$128 [6:0] connect \next_srcstep \$125 [6:0] connect \dbg_core_dbg_msr \dec2_cur_msr connect { \dbg_core_dbg_core_dbg_maxvl \dbg_core_dbg_core_dbg_vl \dbg_core_dbg_core_dbg_srcstep \dbg_core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_subvl \dbg_core_dbg_core_dbg_svstep } \svstate [31:0] connect \dbg_core_dbg_pc \pc connect \dbg_terminate_i \core_core_terminate_o connect \pc_o \dec2_cur_pc connect \core_cu_st__go_i \cu_st__rel_o_rise connect \core_cu_ad__go_i \core_cu_ad__rel_o connect \cu_st__rel_o_rise \$36 connect \cu_st__rel_o_dly$next \core_cu_st__rel_o connect \dec2_bigendian \core_bigendian_i connect \busy_o \core_corebusy_o connect \core_coresync_rst \ti_rst connect \ti_rst \$32 connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } end attribute \src "libresoc.v:200176.1-201367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 attribute \src "libresoc.v:200912.3-200913.25" wire $0\all_rd_dly[0:0] attribute \src "libresoc.v:200910.3-200911.41" wire $0\alu_done_dly[0:0] attribute \src "libresoc.v:201270.3-201278.6" wire $0\alu_l_r_alu$next[0:0]$14033 attribute \src "libresoc.v:200838.3-200839.39" wire $0\alu_l_r_alu[0:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$13959 attribute \src "libresoc.v:200878.3-200879.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$13960 attribute \src "libresoc.v:200872.3-200873.69" wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$13961 attribute \src "libresoc.v:200874.3-200875.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$13962 attribute \src "libresoc.v:200870.3-200871.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] attribute \src "libresoc.v:201093.3-201110.6" wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$13963 attribute \src "libresoc.v:200880.3-200881.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$13964 attribute \src "libresoc.v:200886.3-200887.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$13965 attribute \src "libresoc.v:200876.3-200877.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$13966 attribute \src "libresoc.v:200884.3-200885.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$13967 attribute \src "libresoc.v:200882.3-200883.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] attribute \src "libresoc.v:201261.3-201269.6" wire $0\alui_l_r_alui$next[0:0]$14030 attribute \src "libresoc.v:200840.3-200841.43" wire $0\alui_l_r_alui[0:0] attribute \src "libresoc.v:201111.3-201132.6" wire width 64 $0\data_r0__o$next[63:0]$13978 attribute \src "libresoc.v:200866.3-200867.37" wire width 64 $0\data_r0__o[63:0] attribute \src "libresoc.v:201111.3-201132.6" wire $0\data_r0__o_ok$next[0:0]$13979 attribute \src "libresoc.v:200868.3-200869.43" wire $0\data_r0__o_ok[0:0] attribute \src "libresoc.v:201133.3-201154.6" wire width 64 $0\data_r1__fast1$next[63:0]$13986 attribute \src "libresoc.v:200862.3-200863.45" wire width 64 $0\data_r1__fast1[63:0] attribute \src "libresoc.v:201133.3-201154.6" wire $0\data_r1__fast1_ok$next[0:0]$13987 attribute \src "libresoc.v:200864.3-200865.51" wire $0\data_r1__fast1_ok[0:0] attribute \src "libresoc.v:201155.3-201176.6" wire width 64 $0\data_r2__fast2$next[63:0]$13994 attribute \src "libresoc.v:200858.3-200859.45" wire width 64 $0\data_r2__fast2[63:0] attribute \src "libresoc.v:201155.3-201176.6" wire $0\data_r2__fast2_ok$next[0:0]$13995 attribute \src "libresoc.v:200860.3-200861.51" wire $0\data_r2__fast2_ok[0:0] attribute \src "libresoc.v:201177.3-201198.6" wire width 64 $0\data_r3__nia$next[63:0]$14002 attribute \src "libresoc.v:200854.3-200855.41" wire width 64 $0\data_r3__nia[63:0] attribute \src "libresoc.v:201177.3-201198.6" wire $0\data_r3__nia_ok$next[0:0]$14003 attribute \src "libresoc.v:200856.3-200857.47" wire $0\data_r3__nia_ok[0:0] attribute \src "libresoc.v:201199.3-201220.6" wire width 64 $0\data_r4__msr$next[63:0]$14010 attribute \src "libresoc.v:200850.3-200851.41" wire width 64 $0\data_r4__msr[63:0] attribute \src "libresoc.v:201199.3-201220.6" wire $0\data_r4__msr_ok$next[0:0]$14011 attribute \src "libresoc.v:200852.3-200853.47" wire $0\data_r4__msr_ok[0:0] attribute \src "libresoc.v:201279.3-201288.6" wire width 64 $0\dest1_o[63:0] attribute \src "libresoc.v:201289.3-201298.6" wire width 64 $0\dest2_o[63:0] attribute \src "libresoc.v:201299.3-201308.6" wire width 64 $0\dest3_o[63:0] attribute \src "libresoc.v:201309.3-201318.6" wire width 64 $0\dest4_o[63:0] attribute \src "libresoc.v:201319.3-201328.6" wire width 64 $0\dest5_o[63:0] attribute \src "libresoc.v:200177.7-200177.20" wire $0\initial[0:0] attribute \src "libresoc.v:201048.3-201056.6" wire $0\opc_l_r_opc$next[0:0]$13944 attribute \src "libresoc.v:200896.3-200897.39" wire $0\opc_l_r_opc[0:0] attribute \src "libresoc.v:201039.3-201047.6" wire $0\opc_l_s_opc$next[0:0]$13941 attribute \src "libresoc.v:200898.3-200899.39" wire $0\opc_l_s_opc[0:0] attribute \src "libresoc.v:201329.3-201337.6" wire width 5 $0\prev_wr_go$next[4:0]$14041 attribute \src "libresoc.v:200908.3-200909.37" wire width 5 $0\prev_wr_go[4:0] attribute \src "libresoc.v:200993.3-201002.6" wire $0\req_done[0:0] attribute \src "libresoc.v:201084.3-201092.6" wire width 5 $0\req_l_r_req$next[4:0]$13956 attribute \src "libresoc.v:200888.3-200889.39" wire width 5 $0\req_l_r_req[4:0] attribute \src "libresoc.v:201075.3-201083.6" wire width 5 $0\req_l_s_req$next[4:0]$13953 attribute \src "libresoc.v:200890.3-200891.39" wire width 5 $0\req_l_s_req[4:0] attribute \src "libresoc.v:201012.3-201020.6" wire $0\rok_l_r_rdok$next[0:0]$13932 attribute \src "libresoc.v:200904.3-200905.41" wire $0\rok_l_r_rdok[0:0] attribute \src "libresoc.v:201003.3-201011.6" wire $0\rok_l_s_rdok$next[0:0]$13929 attribute \src "libresoc.v:200906.3-200907.41" wire $0\rok_l_s_rdok[0:0] attribute \src "libresoc.v:201030.3-201038.6" wire $0\rst_l_r_rst$next[0:0]$13938 attribute \src "libresoc.v:200900.3-200901.39" wire $0\rst_l_r_rst[0:0] attribute \src "libresoc.v:201021.3-201029.6" wire $0\rst_l_s_rst$next[0:0]$13935 attribute \src "libresoc.v:200902.3-200903.39" wire $0\rst_l_s_rst[0:0] attribute \src "libresoc.v:201066.3-201074.6" wire width 4 $0\src_l_r_src$next[3:0]$13950 attribute \src "libresoc.v:200892.3-200893.39" wire width 4 $0\src_l_r_src[3:0] attribute \src "libresoc.v:201057.3-201065.6" wire width 4 $0\src_l_s_src$next[3:0]$13947 attribute \src "libresoc.v:200894.3-200895.39" wire width 4 $0\src_l_s_src[3:0] attribute \src "libresoc.v:201221.3-201230.6" wire width 64 $0\src_r0$next[63:0]$14018 attribute \src "libresoc.v:200848.3-200849.29" wire width 64 $0\src_r0[63:0] attribute \src "libresoc.v:201231.3-201240.6" wire width 64 $0\src_r1$next[63:0]$14021 attribute \src "libresoc.v:200846.3-200847.29" wire width 64 $0\src_r1[63:0] attribute \src "libresoc.v:201241.3-201250.6" wire width 64 $0\src_r2$next[63:0]$14024 attribute \src "libresoc.v:200844.3-200845.29" wire width 64 $0\src_r2[63:0] attribute \src "libresoc.v:201251.3-201260.6" wire width 64 $0\src_r3$next[63:0]$14027 attribute \src "libresoc.v:200842.3-200843.29" wire width 64 $0\src_r3[63:0] attribute \src "libresoc.v:200303.7-200303.24" wire $1\all_rd_dly[0:0] attribute \src "libresoc.v:200313.7-200313.26" wire $1\alu_done_dly[0:0] attribute \src "libresoc.v:201270.3-201278.6" wire $1\alu_l_r_alu$next[0:0]$14034 attribute \src "libresoc.v:200321.7-200321.25" wire $1\alu_l_r_alu[0:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$13968 attribute \src "libresoc.v:200357.14-200357.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 attribute \src "libresoc.v:200376.14-200376.51" wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$13970 attribute \src "libresoc.v:200380.14-200380.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 attribute \src "libresoc.v:200459.13-200459.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] attribute \src "libresoc.v:201093.3-201110.6" wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 attribute \src "libresoc.v:200463.7-200463.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 attribute \src "libresoc.v:200467.13-200467.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$13974 attribute \src "libresoc.v:200471.14-200471.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 attribute \src "libresoc.v:200475.14-200475.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] attribute \src "libresoc.v:201093.3-201110.6" wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$13976 attribute \src "libresoc.v:200479.13-200479.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] attribute \src "libresoc.v:201261.3-201269.6" wire $1\alui_l_r_alui$next[0:0]$14031 attribute \src "libresoc.v:200485.7-200485.27" wire $1\alui_l_r_alui[0:0] attribute \src "libresoc.v:201111.3-201132.6" wire width 64 $1\data_r0__o$next[63:0]$13980 attribute \src "libresoc.v:200517.14-200517.47" wire width 64 $1\data_r0__o[63:0] attribute \src "libresoc.v:201111.3-201132.6" wire $1\data_r0__o_ok$next[0:0]$13981 attribute \src "libresoc.v:200521.7-200521.27" wire $1\data_r0__o_ok[0:0] attribute \src "libresoc.v:201133.3-201154.6" wire width 64 $1\data_r1__fast1$next[63:0]$13988 attribute \src "libresoc.v:200525.14-200525.51" wire width 64 $1\data_r1__fast1[63:0] attribute \src "libresoc.v:201133.3-201154.6" wire $1\data_r1__fast1_ok$next[0:0]$13989 attribute \src "libresoc.v:200529.7-200529.31" wire $1\data_r1__fast1_ok[0:0] attribute \src "libresoc.v:201155.3-201176.6" wire width 64 $1\data_r2__fast2$next[63:0]$13996 attribute \src "libresoc.v:200533.14-200533.51" wire width 64 $1\data_r2__fast2[63:0] attribute \src "libresoc.v:201155.3-201176.6" wire $1\data_r2__fast2_ok$next[0:0]$13997 attribute \src "libresoc.v:200537.7-200537.31" wire $1\data_r2__fast2_ok[0:0] attribute \src "libresoc.v:201177.3-201198.6" wire width 64 $1\data_r3__nia$next[63:0]$14004 attribute \src "libresoc.v:200541.14-200541.49" wire width 64 $1\data_r3__nia[63:0] attribute \src "libresoc.v:201177.3-201198.6" wire $1\data_r3__nia_ok$next[0:0]$14005 attribute \src "libresoc.v:200545.7-200545.29" wire $1\data_r3__nia_ok[0:0] attribute \src "libresoc.v:201199.3-201220.6" wire width 64 $1\data_r4__msr$next[63:0]$14012 attribute \src "libresoc.v:200549.14-200549.49" wire width 64 $1\data_r4__msr[63:0] attribute \src "libresoc.v:201199.3-201220.6" wire $1\data_r4__msr_ok$next[0:0]$14013 attribute \src "libresoc.v:200553.7-200553.29" wire $1\data_r4__msr_ok[0:0] attribute \src "libresoc.v:201279.3-201288.6" wire width 64 $1\dest1_o[63:0] attribute \src "libresoc.v:201289.3-201298.6" wire width 64 $1\dest2_o[63:0] attribute \src "libresoc.v:201299.3-201308.6" wire width 64 $1\dest3_o[63:0] attribute \src "libresoc.v:201309.3-201318.6" wire width 64 $1\dest4_o[63:0] attribute \src "libresoc.v:201319.3-201328.6" wire width 64 $1\dest5_o[63:0] attribute \src "libresoc.v:201048.3-201056.6" wire $1\opc_l_r_opc$next[0:0]$13945 attribute \src "libresoc.v:200584.7-200584.25" wire $1\opc_l_r_opc[0:0] attribute \src "libresoc.v:201039.3-201047.6" wire $1\opc_l_s_opc$next[0:0]$13942 attribute \src "libresoc.v:200588.7-200588.25" wire $1\opc_l_s_opc[0:0] attribute \src "libresoc.v:201329.3-201337.6" wire width 5 $1\prev_wr_go$next[4:0]$14042 attribute \src "libresoc.v:200700.13-200700.31" wire width 5 $1\prev_wr_go[4:0] attribute \src "libresoc.v:200993.3-201002.6" wire $1\req_done[0:0] attribute \src "libresoc.v:201084.3-201092.6" wire width 5 $1\req_l_r_req$next[4:0]$13957 attribute \src "libresoc.v:200708.13-200708.32" wire width 5 $1\req_l_r_req[4:0] attribute \src "libresoc.v:201075.3-201083.6" wire width 5 $1\req_l_s_req$next[4:0]$13954 attribute \src "libresoc.v:200712.13-200712.32" wire width 5 $1\req_l_s_req[4:0] attribute \src "libresoc.v:201012.3-201020.6" wire $1\rok_l_r_rdok$next[0:0]$13933 attribute \src "libresoc.v:200724.7-200724.26" wire $1\rok_l_r_rdok[0:0] attribute \src "libresoc.v:201003.3-201011.6" wire $1\rok_l_s_rdok$next[0:0]$13930 attribute \src "libresoc.v:200728.7-200728.26" wire $1\rok_l_s_rdok[0:0] attribute \src "libresoc.v:201030.3-201038.6" wire $1\rst_l_r_rst$next[0:0]$13939 attribute \src "libresoc.v:200732.7-200732.25" wire $1\rst_l_r_rst[0:0] attribute \src "libresoc.v:201021.3-201029.6" wire $1\rst_l_s_rst$next[0:0]$13936 attribute \src "libresoc.v:200736.7-200736.25" wire $1\rst_l_s_rst[0:0] attribute \src "libresoc.v:201066.3-201074.6" wire width 4 $1\src_l_r_src$next[3:0]$13951 attribute \src "libresoc.v:200752.13-200752.31" wire width 4 $1\src_l_r_src[3:0] attribute \src "libresoc.v:201057.3-201065.6" wire width 4 $1\src_l_s_src$next[3:0]$13948 attribute \src "libresoc.v:200756.13-200756.31" wire width 4 $1\src_l_s_src[3:0] attribute \src "libresoc.v:201221.3-201230.6" wire width 64 $1\src_r0$next[63:0]$14019 attribute \src "libresoc.v:200760.14-200760.43" wire width 64 $1\src_r0[63:0] attribute \src "libresoc.v:201231.3-201240.6" wire width 64 $1\src_r1$next[63:0]$14022 attribute \src "libresoc.v:200764.14-200764.43" wire width 64 $1\src_r1[63:0] attribute \src "libresoc.v:201241.3-201250.6" wire width 64 $1\src_r2$next[63:0]$14025 attribute \src "libresoc.v:200768.14-200768.43" wire width 64 $1\src_r2[63:0] attribute \src "libresoc.v:201251.3-201260.6" wire width 64 $1\src_r3$next[63:0]$14028 attribute \src "libresoc.v:200772.14-200772.43" wire width 64 $1\src_r3[63:0] attribute \src "libresoc.v:201111.3-201132.6" wire width 64 $2\data_r0__o$next[63:0]$13982 attribute \src "libresoc.v:201111.3-201132.6" wire $2\data_r0__o_ok$next[0:0]$13983 attribute \src "libresoc.v:201133.3-201154.6" wire width 64 $2\data_r1__fast1$next[63:0]$13990 attribute \src "libresoc.v:201133.3-201154.6" wire $2\data_r1__fast1_ok$next[0:0]$13991 attribute \src "libresoc.v:201155.3-201176.6" wire width 64 $2\data_r2__fast2$next[63:0]$13998 attribute \src "libresoc.v:201155.3-201176.6" wire $2\data_r2__fast2_ok$next[0:0]$13999 attribute \src "libresoc.v:201177.3-201198.6" wire width 64 $2\data_r3__nia$next[63:0]$14006 attribute \src "libresoc.v:201177.3-201198.6" wire $2\data_r3__nia_ok$next[0:0]$14007 attribute \src "libresoc.v:201199.3-201220.6" wire width 64 $2\data_r4__msr$next[63:0]$14014 attribute \src "libresoc.v:201199.3-201220.6" wire $2\data_r4__msr_ok$next[0:0]$14015 attribute \src "libresoc.v:201111.3-201132.6" wire $3\data_r0__o_ok$next[0:0]$13984 attribute \src "libresoc.v:201133.3-201154.6" wire $3\data_r1__fast1_ok$next[0:0]$13992 attribute \src "libresoc.v:201155.3-201176.6" wire $3\data_r2__fast2_ok$next[0:0]$14000 attribute \src "libresoc.v:201177.3-201198.6" wire $3\data_r3__nia_ok$next[0:0]$14008 attribute \src "libresoc.v:201199.3-201220.6" wire $3\data_r4__msr_ok$next[0:0]$14016 attribute \src "libresoc.v:200778.18-200778.112" wire width 4 $and$libresoc.v:200778$13829_Y attribute \src "libresoc.v:200779.19-200779.125" wire $and$libresoc.v:200779$13830_Y attribute \src "libresoc.v:200780.19-200780.125" wire $and$libresoc.v:200780$13831_Y attribute \src "libresoc.v:200781.19-200781.125" wire $and$libresoc.v:200781$13832_Y attribute \src "libresoc.v:200782.19-200782.125" wire $and$libresoc.v:200782$13833_Y attribute \src "libresoc.v:200783.19-200783.125" wire $and$libresoc.v:200783$13834_Y attribute \src "libresoc.v:200784.19-200784.157" wire width 5 $and$libresoc.v:200784$13835_Y attribute \src "libresoc.v:200785.19-200785.121" wire width 5 $and$libresoc.v:200785$13836_Y attribute \src "libresoc.v:200786.19-200786.127" wire $and$libresoc.v:200786$13837_Y attribute \src "libresoc.v:200787.19-200787.127" wire $and$libresoc.v:200787$13838_Y attribute \src "libresoc.v:200788.18-200788.110" wire $and$libresoc.v:200788$13839_Y attribute \src "libresoc.v:200789.19-200789.127" wire $and$libresoc.v:200789$13840_Y attribute \src "libresoc.v:200790.19-200790.127" wire $and$libresoc.v:200790$13841_Y attribute \src "libresoc.v:200791.19-200791.127" wire $and$libresoc.v:200791$13842_Y attribute \src "libresoc.v:200793.18-200793.98" wire $and$libresoc.v:200793$13844_Y attribute \src "libresoc.v:200795.18-200795.100" wire $and$libresoc.v:200795$13846_Y attribute \src "libresoc.v:200796.18-200796.171" wire width 5 $and$libresoc.v:200796$13847_Y attribute \src "libresoc.v:200798.18-200798.119" wire width 5 $and$libresoc.v:200798$13849_Y attribute \src "libresoc.v:200801.18-200801.116" wire $and$libresoc.v:200801$13852_Y attribute \src "libresoc.v:200805.17-200805.123" wire $and$libresoc.v:200805$13856_Y attribute \src "libresoc.v:200807.18-200807.113" wire $and$libresoc.v:200807$13858_Y attribute \src "libresoc.v:200808.18-200808.125" wire width 5 $and$libresoc.v:200808$13859_Y attribute \src "libresoc.v:200810.18-200810.112" wire $and$libresoc.v:200810$13861_Y attribute \src "libresoc.v:200812.18-200812.127" wire $and$libresoc.v:200812$13863_Y attribute \src "libresoc.v:200813.18-200813.127" wire $and$libresoc.v:200813$13864_Y attribute \src "libresoc.v:200814.18-200814.117" wire $and$libresoc.v:200814$13865_Y attribute \src "libresoc.v:200819.18-200819.131" wire $and$libresoc.v:200819$13870_Y attribute \src "libresoc.v:200820.18-200820.124" wire width 5 $and$libresoc.v:200820$13871_Y attribute \src "libresoc.v:200823.18-200823.116" wire $and$libresoc.v:200823$13874_Y attribute \src "libresoc.v:200824.18-200824.120" wire $and$libresoc.v:200824$13875_Y attribute \src "libresoc.v:200825.18-200825.120" wire $and$libresoc.v:200825$13876_Y attribute \src "libresoc.v:200826.18-200826.118" wire $and$libresoc.v:200826$13877_Y attribute \src "libresoc.v:200827.18-200827.118" wire $and$libresoc.v:200827$13878_Y attribute \src "libresoc.v:200833.18-200833.135" wire $and$libresoc.v:200833$13884_Y attribute \src "libresoc.v:200834.18-200834.133" wire $and$libresoc.v:200834$13885_Y attribute \src "libresoc.v:200835.18-200835.160" wire width 4 $and$libresoc.v:200835$13886_Y attribute \src "libresoc.v:200836.18-200836.112" wire width 4 $and$libresoc.v:200836$13887_Y attribute \src "libresoc.v:200809.18-200809.113" wire $eq$libresoc.v:200809$13860_Y attribute \src "libresoc.v:200811.18-200811.119" wire $eq$libresoc.v:200811$13862_Y attribute \src "libresoc.v:200792.18-200792.97" wire $not$libresoc.v:200792$13843_Y attribute \src "libresoc.v:200794.18-200794.99" wire $not$libresoc.v:200794$13845_Y attribute \src "libresoc.v:200797.18-200797.113" wire width 5 $not$libresoc.v:200797$13848_Y attribute \src "libresoc.v:200800.18-200800.106" wire $not$libresoc.v:200800$13851_Y attribute \src "libresoc.v:200806.18-200806.121" wire $not$libresoc.v:200806$13857_Y attribute \src "libresoc.v:200821.17-200821.113" wire width 4 $not$libresoc.v:200821$13872_Y attribute \src "libresoc.v:200837.18-200837.114" wire width 4 $not$libresoc.v:200837$13888_Y attribute \src "libresoc.v:200804.18-200804.112" wire $or$libresoc.v:200804$13855_Y attribute \src "libresoc.v:200815.18-200815.122" wire $or$libresoc.v:200815$13866_Y attribute \src "libresoc.v:200816.18-200816.124" wire $or$libresoc.v:200816$13867_Y attribute \src "libresoc.v:200817.18-200817.181" wire width 5 $or$libresoc.v:200817$13868_Y attribute \src "libresoc.v:200818.18-200818.168" wire width 4 $or$libresoc.v:200818$13869_Y attribute \src "libresoc.v:200822.18-200822.120" wire width 5 $or$libresoc.v:200822$13873_Y attribute \src "libresoc.v:200832.17-200832.117" wire width 4 $or$libresoc.v:200832$13883_Y attribute \src "libresoc.v:200777.17-200777.104" wire $reduce_and$libresoc.v:200777$13828_Y attribute \src "libresoc.v:200799.18-200799.106" wire $reduce_or$libresoc.v:200799$13850_Y attribute \src "libresoc.v:200802.18-200802.113" wire $reduce_or$libresoc.v:200802$13853_Y attribute \src "libresoc.v:200803.18-200803.112" wire $reduce_or$libresoc.v:200803$13854_Y attribute \src "libresoc.v:200828.18-200828.118" wire width 64 $ternary$libresoc.v:200828$13879_Y attribute \src "libresoc.v:200829.18-200829.118" wire width 64 $ternary$libresoc.v:200829$13880_Y attribute \src "libresoc.v:200830.18-200830.118" wire width 64 $ternary$libresoc.v:200830$13881_Y attribute \src "libresoc.v:200831.18-200831.118" wire width 64 $ternary$libresoc.v:200831$13882_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 5 \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" wire width 5 \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" wire \$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" wire width 5 \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 5 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire width 5 \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire width 5 \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" wire \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" wire \$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" wire \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 4 \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" wire width 5 \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" wire width 4 \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" wire width 5 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" wire width 5 \$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire width 4 \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" wire width 64 \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" wire width 4 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" wire \all_rd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \all_rd_dly$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \all_rd_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire \alu_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \alu_done_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 5 \alu_pulsem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_fast1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_fast2$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" wire \alu_trap0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" wire \alu_trap0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire width 64 \alu_trap0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" wire \alu_trap0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \alu_trap0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__cia$next attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_trap0_trap_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 \alu_trap0_trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_trap0_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \alu_trap0_trap_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_trap0_trap_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_trap0_trap_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_trap0_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_trap0_trap_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \alu_trap0_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \alu_trap0_trap_op__ldst_exc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \alu_trap0_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \alu_trap0_trap_op__trapaddr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \alu_trap0_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \alu_trap0_trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 32 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire input 11 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 input 15 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 output 14 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 input 13 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 input 22 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 output 21 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 5 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r0__o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r1__fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r1__fast1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r2__fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r2__fast2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__fast2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r3__nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r3__nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__nia_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r4__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r4__msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__msr_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 23 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 26 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 27 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 29 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 output 31 \dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 25 \fast2_ok attribute \src "libresoc.v:200177.7-200177.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 30 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 28 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" wire output 20 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 6 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" attribute \enum_value_00000000000010 "ALU" attribute \enum_value_00000000000100 "LDST" attribute \enum_value_00000000001000 "SHIFT_ROT" attribute \enum_value_00000000010000 "LOGICAL" attribute \enum_value_00000000100000 "BRANCH" attribute \enum_value_00000001000000 "CR" attribute \enum_value_00000010000000 "TRAP" attribute \enum_value_00000100000000 "MUL" attribute \enum_value_00001000000000 "DIV" attribute \enum_value_00010000000000 "SPR" attribute \enum_value_00100000000000 "MMU" attribute \enum_value_01000000000000 "SV" attribute \enum_value_10000000000000 "VL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 14 input 3 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 4 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" attribute \enum_value_0000010 "OP_ADD" attribute \enum_value_0000011 "OP_ADDPCIS" attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" attribute \enum_value_0001010 "OP_CMP" attribute \enum_value_0001011 "OP_CMPB" attribute \enum_value_0001100 "OP_CMPEQB" attribute \enum_value_0001101 "OP_CMPRB" attribute \enum_value_0001110 "OP_CNTZ" attribute \enum_value_0001111 "OP_CRAND" attribute \enum_value_0010000 "OP_CRANDC" attribute \enum_value_0010001 "OP_CREQV" attribute \enum_value_0010010 "OP_CRNAND" attribute \enum_value_0010011 "OP_CRNOR" attribute \enum_value_0010100 "OP_CROR" attribute \enum_value_0010101 "OP_CRORC" attribute \enum_value_0010110 "OP_CRXOR" attribute \enum_value_0010111 "OP_DARN" attribute \enum_value_0011000 "OP_DCBF" attribute \enum_value_0011001 "OP_DCBST" attribute \enum_value_0011010 "OP_DCBT" attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" attribute \enum_value_0100000 "OP_EXTSWSLI" attribute \enum_value_0100001 "OP_ICBI" attribute \enum_value_0100010 "OP_ICBT" attribute \enum_value_0100011 "OP_ISEL" attribute \enum_value_0100100 "OP_ISYNC" attribute \enum_value_0100101 "OP_LOAD" attribute \enum_value_0100110 "OP_STORE" attribute \enum_value_0100111 "OP_MADDHD" attribute \enum_value_0101000 "OP_MADDHDU" attribute \enum_value_0101001 "OP_MADDLD" attribute \enum_value_0101010 "OP_MCRF" attribute \enum_value_0101011 "OP_MCRXR" attribute \enum_value_0101100 "OP_MCRXRX" attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" attribute \enum_value_0110000 "OP_MTCRF" attribute \enum_value_0110001 "OP_MTSPR" attribute \enum_value_0110010 "OP_MUL_L64" attribute \enum_value_0110011 "OP_MUL_H64" attribute \enum_value_0110100 "OP_MUL_H32" attribute \enum_value_0110101 "OP_OR" attribute \enum_value_0110110 "OP_POPCNT" attribute \enum_value_0110111 "OP_PRTY" attribute \enum_value_0111000 "OP_RLC" attribute \enum_value_0111001 "OP_RLCL" attribute \enum_value_0111010 "OP_RLCR" attribute \enum_value_0111011 "OP_SETB" attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" attribute \enum_value_1000011 "OP_XOR" attribute \enum_value_1000100 "OP_SIM_CONFIG" attribute \enum_value_1000101 "OP_CROP" attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 input 2 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 10 \oper_i_alu_trap0__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \oper_i_alu_trap0__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 9 \oper_i_alu_trap0__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 input 8 \oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 5 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 5 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire \req_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 5 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \req_l_r_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire \reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 4 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 5 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rok_l_r_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 17 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 16 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 18 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 input 19 \src4_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 4 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:200778$13829 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 connect \Y $and$libresoc.v:200778$13829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:200779$13830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:200779$13830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:200780$13831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:200780$13831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:200781$13832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:200781$13832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:200782$13833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:200782$13833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" cell $and $and$libresoc.v:200783$13834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i connect \Y $and$libresoc.v:200783$13834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:200784$13835 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } connect \Y $and$libresoc.v:200784$13835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" cell $and $and$libresoc.v:200785$13836 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o connect \Y $and$libresoc.v:200785$13836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:200786$13837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o connect \Y $and$libresoc.v:200786$13837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:200787$13838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o connect \Y $and$libresoc.v:200787$13838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $and $and$libresoc.v:200788$13839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 connect \Y $and$libresoc.v:200788$13839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:200789$13840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o connect \Y $and$libresoc.v:200789$13840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:200790$13841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o connect \Y $and$libresoc.v:200790$13841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" cell $and $and$libresoc.v:200791$13842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o connect \Y $and$libresoc.v:200791$13842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:200793$13844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 connect \Y $and$libresoc.v:200793$13844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $and $and$libresoc.v:200795$13846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 connect \Y $and$libresoc.v:200795$13846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" cell $and $and$libresoc.v:200796$13847 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:200796$13847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:200798$13849 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 connect \Y $and$libresoc.v:200798$13849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $and $and$libresoc.v:200801$13852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 connect \Y $and$libresoc.v:200801$13852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" cell $and $and$libresoc.v:200805$13856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok connect \Y $and$libresoc.v:200805$13856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $and $and$libresoc.v:200807$13858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 connect \Y $and$libresoc.v:200807$13858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:200808$13859 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o connect \Y $and$libresoc.v:200808$13859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $and $and$libresoc.v:200810$13861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 connect \Y $and$libresoc.v:200810$13861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:200812$13863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i connect \Y $and$libresoc.v:200812$13863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:200813$13864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o connect \Y $and$libresoc.v:200813$13864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $and$libresoc.v:200814$13865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o connect \Y $and$libresoc.v:200814$13865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" cell $and $and$libresoc.v:200819$13870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o connect \Y $and$libresoc.v:200819$13870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" cell $and $and$libresoc.v:200820$13871 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o connect \Y $and$libresoc.v:200820$13871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:200823$13874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:200823$13874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:200824$13875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:200824$13875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:200825$13876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:200825$13876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:200826$13877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:200826$13877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" cell $and $and$libresoc.v:200827$13878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o connect \Y $and$libresoc.v:200827$13878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" cell $and $and$libresoc.v:200833$13884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui connect \Y $and$libresoc.v:200833$13884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" cell $and $and$libresoc.v:200834$13885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu connect \Y $and$libresoc.v:200834$13885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:200835$13886 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } connect \Y $and$libresoc.v:200835$13886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $and $and$libresoc.v:200836$13887 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 connect \Y $and$libresoc.v:200836$13887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $eq$libresoc.v:200809$13860 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 connect \Y $eq$libresoc.v:200809$13860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $eq $eq$libresoc.v:200811$13862 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 connect \Y $eq$libresoc.v:200811$13862_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:200792$13843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly connect \Y $not$libresoc.v:200792$13843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" cell $not $not$libresoc.v:200794$13845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly connect \Y $not$libresoc.v:200794$13845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:200797$13848 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o connect \Y $not$libresoc.v:200797$13848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $not $not$libresoc.v:200800$13851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:200800$13851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" cell $not $not$libresoc.v:200806$13857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i connect \Y $not$libresoc.v:200806$13857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $not $not$libresoc.v:200821$13872 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o connect \Y $not$libresoc.v:200821$13872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" cell $not $not$libresoc.v:200837$13888 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i connect \Y $not$libresoc.v:200837$13888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $or $or$libresoc.v:200804$13855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 connect \Y $or$libresoc.v:200804$13855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" cell $or $or$libresoc.v:200815$13866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i connect \Y $or$libresoc.v:200815$13866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" cell $or $or$libresoc.v:200816$13867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i connect \Y $or$libresoc.v:200816$13867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" cell $or $or$libresoc.v:200817$13868 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:200817$13868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" cell $or $or$libresoc.v:200818$13869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } connect \Y $or$libresoc.v:200818$13869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" cell $or $or$libresoc.v:200822$13873 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go connect \Y $or$libresoc.v:200822$13873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $or $or$libresoc.v:200832$13883 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i connect \Y $or$libresoc.v:200832$13883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" cell $reduce_and $reduce_and$libresoc.v:200777$13828 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $reduce_and$libresoc.v:200777$13828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" cell $reduce_or $reduce_or$libresoc.v:200799$13850 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 connect \Y $reduce_or$libresoc.v:200799$13850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:200802$13853 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i connect \Y $reduce_or$libresoc.v:200802$13853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" cell $reduce_or $reduce_or$libresoc.v:200803$13854 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $reduce_or$libresoc.v:200803$13854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:200828$13879 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] connect \Y $ternary$libresoc.v:200828$13879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:200829$13880 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] connect \Y $ternary$libresoc.v:200829$13880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:200830$13881 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] connect \Y $ternary$libresoc.v:200830$13881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" cell $mux $ternary$libresoc.v:200831$13882 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] connect \Y $ternary$libresoc.v:200831$13882_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:200914.14-200920.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 attribute \src "libresoc.v:200921.13-200951.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \fast1 \alu_trap0_fast1 connect \fast1$1 \alu_trap0_fast1$1 connect \fast1_ok \fast1_ok connect \fast2 \alu_trap0_fast2 connect \fast2$2 \alu_trap0_fast2$2 connect \fast2_ok \fast2_ok connect \msr \alu_trap0_msr connect \msr_ok \msr_ok connect \n_ready_i \alu_trap0_n_ready_i connect \n_valid_o \alu_trap0_n_valid_o connect \nia \alu_trap0_nia connect \nia_ok \nia_ok connect \o \alu_trap0_o connect \o_ok \o_ok connect \p_ready_o \alu_trap0_p_ready_o connect \p_valid_i \alu_trap0_p_valid_i connect \ra \alu_trap0_ra connect \rb \alu_trap0_rb connect \trap_op__cia \alu_trap0_trap_op__cia connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit connect \trap_op__insn \alu_trap0_trap_op__insn connect \trap_op__insn_type \alu_trap0_trap_op__insn_type connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit connect \trap_op__ldst_exc \alu_trap0_trap_op__ldst_exc connect \trap_op__msr \alu_trap0_trap_op__msr connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 attribute \src "libresoc.v:200952.15-200958.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui connect \r_alui \alui_l_r_alui connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 attribute \src "libresoc.v:200959.14-200965.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc connect \r_opc \opc_l_r_opc connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 attribute \src "libresoc.v:200966.14-200972.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req connect \r_req \req_l_r_req connect \s_req \req_l_s_req end attribute \module_not_derived 1 attribute \src "libresoc.v:200973.14-200979.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok connect \r_rdok \rok_l_r_rdok connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 attribute \src "libresoc.v:200980.14-200985.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 attribute \src "libresoc.v:200986.14-200992.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end attribute \src "libresoc.v:200177.7-200177.20" process $proc$libresoc.v:200177$14043 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:200303.7-200303.24" process $proc$libresoc.v:200303$14044 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end attribute \src "libresoc.v:200313.7-200313.26" process $proc$libresoc.v:200313$14045 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end attribute \src "libresoc.v:200321.7-200321.25" process $proc$libresoc.v:200321$14046 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end attribute \src "libresoc.v:200357.14-200357.59" process $proc$libresoc.v:200357$14047 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end attribute \src "libresoc.v:200376.14-200376.51" process $proc$libresoc.v:200376$14048 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end attribute \src "libresoc.v:200380.14-200380.45" process $proc$libresoc.v:200380$14049 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end attribute \src "libresoc.v:200459.13-200459.49" process $proc$libresoc.v:200459$14050 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end attribute \src "libresoc.v:200463.7-200463.41" process $proc$libresoc.v:200463$14051 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end attribute \src "libresoc.v:200467.13-200467.48" process $proc$libresoc.v:200467$14052 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end attribute \src "libresoc.v:200471.14-200471.59" process $proc$libresoc.v:200471$14053 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end attribute \src "libresoc.v:200475.14-200475.52" process $proc$libresoc.v:200475$14054 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end attribute \src "libresoc.v:200479.13-200479.48" process $proc$libresoc.v:200479$14055 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end attribute \src "libresoc.v:200485.7-200485.27" process $proc$libresoc.v:200485$14056 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end attribute \src "libresoc.v:200517.14-200517.47" process $proc$libresoc.v:200517$14057 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end attribute \src "libresoc.v:200521.7-200521.27" process $proc$libresoc.v:200521$14058 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end attribute \src "libresoc.v:200525.14-200525.51" process $proc$libresoc.v:200525$14059 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end attribute \src "libresoc.v:200529.7-200529.31" process $proc$libresoc.v:200529$14060 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end attribute \src "libresoc.v:200533.14-200533.51" process $proc$libresoc.v:200533$14061 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end attribute \src "libresoc.v:200537.7-200537.31" process $proc$libresoc.v:200537$14062 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end attribute \src "libresoc.v:200541.14-200541.49" process $proc$libresoc.v:200541$14063 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end attribute \src "libresoc.v:200545.7-200545.29" process $proc$libresoc.v:200545$14064 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end attribute \src "libresoc.v:200549.14-200549.49" process $proc$libresoc.v:200549$14065 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end attribute \src "libresoc.v:200553.7-200553.29" process $proc$libresoc.v:200553$14066 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end attribute \src "libresoc.v:200584.7-200584.25" process $proc$libresoc.v:200584$14067 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end attribute \src "libresoc.v:200588.7-200588.25" process $proc$libresoc.v:200588$14068 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end attribute \src "libresoc.v:200700.13-200700.31" process $proc$libresoc.v:200700$14069 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end attribute \src "libresoc.v:200708.13-200708.32" process $proc$libresoc.v:200708$14070 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end attribute \src "libresoc.v:200712.13-200712.32" process $proc$libresoc.v:200712$14071 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end attribute \src "libresoc.v:200724.7-200724.26" process $proc$libresoc.v:200724$14072 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:200728.7-200728.26" process $proc$libresoc.v:200728$14073 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:200732.7-200732.25" process $proc$libresoc.v:200732$14074 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end attribute \src "libresoc.v:200736.7-200736.25" process $proc$libresoc.v:200736$14075 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end attribute \src "libresoc.v:200752.13-200752.31" process $proc$libresoc.v:200752$14076 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end attribute \src "libresoc.v:200756.13-200756.31" process $proc$libresoc.v:200756$14077 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end attribute \src "libresoc.v:200760.14-200760.43" process $proc$libresoc.v:200760$14078 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end attribute \src "libresoc.v:200764.14-200764.43" process $proc$libresoc.v:200764$14079 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end attribute \src "libresoc.v:200768.14-200768.43" process $proc$libresoc.v:200768$14080 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end attribute \src "libresoc.v:200772.14-200772.43" process $proc$libresoc.v:200772$14081 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end attribute \src "libresoc.v:200838.3-200839.39" process $proc$libresoc.v:200838$13889 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end attribute \src "libresoc.v:200840.3-200841.43" process $proc$libresoc.v:200840$13890 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end attribute \src "libresoc.v:200842.3-200843.29" process $proc$libresoc.v:200842$13891 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end attribute \src "libresoc.v:200844.3-200845.29" process $proc$libresoc.v:200844$13892 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end attribute \src "libresoc.v:200846.3-200847.29" process $proc$libresoc.v:200846$13893 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end attribute \src "libresoc.v:200848.3-200849.29" process $proc$libresoc.v:200848$13894 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end attribute \src "libresoc.v:200850.3-200851.41" process $proc$libresoc.v:200850$13895 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end attribute \src "libresoc.v:200852.3-200853.47" process $proc$libresoc.v:200852$13896 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end attribute \src "libresoc.v:200854.3-200855.41" process $proc$libresoc.v:200854$13897 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end attribute \src "libresoc.v:200856.3-200857.47" process $proc$libresoc.v:200856$13898 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end attribute \src "libresoc.v:200858.3-200859.45" process $proc$libresoc.v:200858$13899 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end attribute \src "libresoc.v:200860.3-200861.51" process $proc$libresoc.v:200860$13900 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end attribute \src "libresoc.v:200862.3-200863.45" process $proc$libresoc.v:200862$13901 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end attribute \src "libresoc.v:200864.3-200865.51" process $proc$libresoc.v:200864$13902 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end attribute \src "libresoc.v:200866.3-200867.37" process $proc$libresoc.v:200866$13903 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end attribute \src "libresoc.v:200868.3-200869.43" process $proc$libresoc.v:200868$13904 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end attribute \src "libresoc.v:200870.3-200871.73" process $proc$libresoc.v:200870$13905 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end attribute \src "libresoc.v:200872.3-200873.69" process $proc$libresoc.v:200872$13906 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end attribute \src "libresoc.v:200874.3-200875.63" process $proc$libresoc.v:200874$13907 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end attribute \src "libresoc.v:200876.3-200877.61" process $proc$libresoc.v:200876$13908 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end attribute \src "libresoc.v:200878.3-200879.61" process $proc$libresoc.v:200878$13909 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end attribute \src "libresoc.v:200880.3-200881.71" process $proc$libresoc.v:200880$13910 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end attribute \src "libresoc.v:200882.3-200883.71" process $proc$libresoc.v:200882$13911 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end attribute \src "libresoc.v:200884.3-200885.71" process $proc$libresoc.v:200884$13912 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end attribute \src "libresoc.v:200886.3-200887.71" process $proc$libresoc.v:200886$13913 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end attribute \src "libresoc.v:200888.3-200889.39" process $proc$libresoc.v:200888$13914 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end attribute \src "libresoc.v:200890.3-200891.39" process $proc$libresoc.v:200890$13915 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end attribute \src "libresoc.v:200892.3-200893.39" process $proc$libresoc.v:200892$13916 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end attribute \src "libresoc.v:200894.3-200895.39" process $proc$libresoc.v:200894$13917 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end attribute \src "libresoc.v:200896.3-200897.39" process $proc$libresoc.v:200896$13918 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end attribute \src "libresoc.v:200898.3-200899.39" process $proc$libresoc.v:200898$13919 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end attribute \src "libresoc.v:200900.3-200901.39" process $proc$libresoc.v:200900$13920 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end attribute \src "libresoc.v:200902.3-200903.39" process $proc$libresoc.v:200902$13921 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end attribute \src "libresoc.v:200904.3-200905.41" process $proc$libresoc.v:200904$13922 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end attribute \src "libresoc.v:200906.3-200907.41" process $proc$libresoc.v:200906$13923 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end attribute \src "libresoc.v:200908.3-200909.37" process $proc$libresoc.v:200908$13924 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end attribute \src "libresoc.v:200910.3-200911.41" process $proc$libresoc.v:200910$13925 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end attribute \src "libresoc.v:200912.3-200913.25" process $proc$libresoc.v:200912$13926 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end attribute \src "libresoc.v:200993.3-201002.6" process $proc$libresoc.v:200993$13927 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] attribute \src "libresoc.v:200994.5-200994.29" switch \initial attribute \src "libresoc.v:200994.9-200994.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_done[0:0] 1'1 case assign $1\req_done[0:0] \$47 end sync always update \req_done $0\req_done[0:0] end attribute \src "libresoc.v:201003.3-201011.6" process $proc$libresoc.v:201003$13928 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$13929 $1\rok_l_s_rdok$next[0:0]$13930 attribute \src "libresoc.v:201004.5-201004.29" switch \initial attribute \src "libresoc.v:201004.9-201004.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_s_rdok$next[0:0]$13930 1'0 case assign $1\rok_l_s_rdok$next[0:0]$13930 \cu_issue_i end sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13929 end attribute \src "libresoc.v:201012.3-201020.6" process $proc$libresoc.v:201012$13931 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$13932 $1\rok_l_r_rdok$next[0:0]$13933 attribute \src "libresoc.v:201013.5-201013.29" switch \initial attribute \src "libresoc.v:201013.9-201013.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rok_l_r_rdok$next[0:0]$13933 1'1 case assign $1\rok_l_r_rdok$next[0:0]$13933 \$65 end sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13932 end attribute \src "libresoc.v:201021.3-201029.6" process $proc$libresoc.v:201021$13934 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$13935 $1\rst_l_s_rst$next[0:0]$13936 attribute \src "libresoc.v:201022.5-201022.29" switch \initial attribute \src "libresoc.v:201022.9-201022.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_s_rst$next[0:0]$13936 1'0 case assign $1\rst_l_s_rst$next[0:0]$13936 \all_rd end sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13935 end attribute \src "libresoc.v:201030.3-201038.6" process $proc$libresoc.v:201030$13937 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$13938 $1\rst_l_r_rst$next[0:0]$13939 attribute \src "libresoc.v:201031.5-201031.29" switch \initial attribute \src "libresoc.v:201031.9-201031.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\rst_l_r_rst$next[0:0]$13939 1'1 case assign $1\rst_l_r_rst$next[0:0]$13939 \rst_r end sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13938 end attribute \src "libresoc.v:201039.3-201047.6" process $proc$libresoc.v:201039$13940 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$13941 $1\opc_l_s_opc$next[0:0]$13942 attribute \src "libresoc.v:201040.5-201040.29" switch \initial attribute \src "libresoc.v:201040.9-201040.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_s_opc$next[0:0]$13942 1'0 case assign $1\opc_l_s_opc$next[0:0]$13942 \cu_issue_i end sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13941 end attribute \src "libresoc.v:201048.3-201056.6" process $proc$libresoc.v:201048$13943 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$13944 $1\opc_l_r_opc$next[0:0]$13945 attribute \src "libresoc.v:201049.5-201049.29" switch \initial attribute \src "libresoc.v:201049.9-201049.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\opc_l_r_opc$next[0:0]$13945 1'1 case assign $1\opc_l_r_opc$next[0:0]$13945 \req_done end sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13944 end attribute \src "libresoc.v:201057.3-201065.6" process $proc$libresoc.v:201057$13946 assign { } { } assign { } { } assign $0\src_l_s_src$next[3:0]$13947 $1\src_l_s_src$next[3:0]$13948 attribute \src "libresoc.v:201058.5-201058.29" switch \initial attribute \src "libresoc.v:201058.9-201058.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_s_src$next[3:0]$13948 4'0000 case assign $1\src_l_s_src$next[3:0]$13948 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always update \src_l_s_src$next $0\src_l_s_src$next[3:0]$13947 end attribute \src "libresoc.v:201066.3-201074.6" process $proc$libresoc.v:201066$13949 assign { } { } assign { } { } assign $0\src_l_r_src$next[3:0]$13950 $1\src_l_r_src$next[3:0]$13951 attribute \src "libresoc.v:201067.5-201067.29" switch \initial attribute \src "libresoc.v:201067.9-201067.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_l_r_src$next[3:0]$13951 4'1111 case assign $1\src_l_r_src$next[3:0]$13951 \reset_r end sync always update \src_l_r_src$next $0\src_l_r_src$next[3:0]$13950 end attribute \src "libresoc.v:201075.3-201083.6" process $proc$libresoc.v:201075$13952 assign { } { } assign { } { } assign $0\req_l_s_req$next[4:0]$13953 $1\req_l_s_req$next[4:0]$13954 attribute \src "libresoc.v:201076.5-201076.29" switch \initial attribute \src "libresoc.v:201076.9-201076.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_s_req$next[4:0]$13954 5'00000 case assign $1\req_l_s_req$next[4:0]$13954 \$67 end sync always update \req_l_s_req$next $0\req_l_s_req$next[4:0]$13953 end attribute \src "libresoc.v:201084.3-201092.6" process $proc$libresoc.v:201084$13955 assign { } { } assign { } { } assign $0\req_l_r_req$next[4:0]$13956 $1\req_l_r_req$next[4:0]$13957 attribute \src "libresoc.v:201085.5-201085.29" switch \initial attribute \src "libresoc.v:201085.9-201085.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\req_l_r_req$next[4:0]$13957 5'11111 case assign $1\req_l_r_req$next[4:0]$13957 \$69 end sync always update \req_l_r_req$next $0\req_l_r_req$next[4:0]$13956 end attribute \src "libresoc.v:201093.3-201110.6" process $proc$libresoc.v:201093$13958 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\alu_trap0_trap_op__cia$next[63:0]$13959 $1\alu_trap0_trap_op__cia$next[63:0]$13968 assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$13960 $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 assign $0\alu_trap0_trap_op__insn$next[31:0]$13961 $1\alu_trap0_trap_op__insn$next[31:0]$13970 assign $0\alu_trap0_trap_op__insn_type$next[6:0]$13962 $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$13963 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$13964 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 assign $0\alu_trap0_trap_op__msr$next[63:0]$13965 $1\alu_trap0_trap_op__msr$next[63:0]$13974 assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$13966 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 assign $0\alu_trap0_trap_op__traptype$next[7:0]$13967 $1\alu_trap0_trap_op__traptype$next[7:0]$13976 attribute \src "libresoc.v:201094.5-201094.29" switch \initial attribute \src "libresoc.v:201094.9-201094.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 $1\alu_trap0_trap_op__traptype$next[7:0]$13976 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 $1\alu_trap0_trap_op__cia$next[63:0]$13968 $1\alu_trap0_trap_op__msr$next[63:0]$13974 $1\alu_trap0_trap_op__insn$next[31:0]$13970 $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case assign $1\alu_trap0_trap_op__cia$next[63:0]$13968 \alu_trap0_trap_op__cia assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$13969 \alu_trap0_trap_op__fn_unit assign $1\alu_trap0_trap_op__insn$next[31:0]$13970 \alu_trap0_trap_op__insn assign $1\alu_trap0_trap_op__insn_type$next[6:0]$13971 \alu_trap0_trap_op__insn_type assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$13972 \alu_trap0_trap_op__is_32bit assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$13973 \alu_trap0_trap_op__ldst_exc assign $1\alu_trap0_trap_op__msr$next[63:0]$13974 \alu_trap0_trap_op__msr assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$13975 \alu_trap0_trap_op__trapaddr assign $1\alu_trap0_trap_op__traptype$next[7:0]$13976 \alu_trap0_trap_op__traptype end sync always update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$13959 update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$13960 update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$13961 update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$13962 update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$13963 update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$13964 update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$13965 update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$13966 update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$13967 end attribute \src "libresoc.v:201111.3-201132.6" process $proc$libresoc.v:201111$13977 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r0__o$next[63:0]$13978 $2\data_r0__o$next[63:0]$13982 assign { } { } assign $0\data_r0__o_ok$next[0:0]$13979 $3\data_r0__o_ok$next[0:0]$13984 attribute \src "libresoc.v:201112.5-201112.29" switch \initial attribute \src "libresoc.v:201112.9-201112.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r0__o_ok$next[0:0]$13981 $1\data_r0__o$next[63:0]$13980 } { \o_ok \alu_trap0_o } case assign $1\data_r0__o$next[63:0]$13980 \data_r0__o assign $1\data_r0__o_ok$next[0:0]$13981 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r0__o_ok$next[0:0]$13983 $2\data_r0__o$next[63:0]$13982 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r0__o$next[63:0]$13982 $1\data_r0__o$next[63:0]$13980 assign $2\data_r0__o_ok$next[0:0]$13983 $1\data_r0__o_ok$next[0:0]$13981 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r0__o_ok$next[0:0]$13984 1'0 case assign $3\data_r0__o_ok$next[0:0]$13984 $2\data_r0__o_ok$next[0:0]$13983 end sync always update \data_r0__o$next $0\data_r0__o$next[63:0]$13978 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13979 end attribute \src "libresoc.v:201133.3-201154.6" process $proc$libresoc.v:201133$13985 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r1__fast1$next[63:0]$13986 $2\data_r1__fast1$next[63:0]$13990 assign { } { } assign $0\data_r1__fast1_ok$next[0:0]$13987 $3\data_r1__fast1_ok$next[0:0]$13992 attribute \src "libresoc.v:201134.5-201134.29" switch \initial attribute \src "libresoc.v:201134.9-201134.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r1__fast1_ok$next[0:0]$13989 $1\data_r1__fast1$next[63:0]$13988 } { \fast1_ok \alu_trap0_fast1 } case assign $1\data_r1__fast1$next[63:0]$13988 \data_r1__fast1 assign $1\data_r1__fast1_ok$next[0:0]$13989 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r1__fast1_ok$next[0:0]$13991 $2\data_r1__fast1$next[63:0]$13990 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r1__fast1$next[63:0]$13990 $1\data_r1__fast1$next[63:0]$13988 assign $2\data_r1__fast1_ok$next[0:0]$13991 $1\data_r1__fast1_ok$next[0:0]$13989 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r1__fast1_ok$next[0:0]$13992 1'0 case assign $3\data_r1__fast1_ok$next[0:0]$13992 $2\data_r1__fast1_ok$next[0:0]$13991 end sync always update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$13986 update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$13987 end attribute \src "libresoc.v:201155.3-201176.6" process $proc$libresoc.v:201155$13993 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r2__fast2$next[63:0]$13994 $2\data_r2__fast2$next[63:0]$13998 assign { } { } assign $0\data_r2__fast2_ok$next[0:0]$13995 $3\data_r2__fast2_ok$next[0:0]$14000 attribute \src "libresoc.v:201156.5-201156.29" switch \initial attribute \src "libresoc.v:201156.9-201156.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r2__fast2_ok$next[0:0]$13997 $1\data_r2__fast2$next[63:0]$13996 } { \fast2_ok \alu_trap0_fast2 } case assign $1\data_r2__fast2$next[63:0]$13996 \data_r2__fast2 assign $1\data_r2__fast2_ok$next[0:0]$13997 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r2__fast2_ok$next[0:0]$13999 $2\data_r2__fast2$next[63:0]$13998 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r2__fast2$next[63:0]$13998 $1\data_r2__fast2$next[63:0]$13996 assign $2\data_r2__fast2_ok$next[0:0]$13999 $1\data_r2__fast2_ok$next[0:0]$13997 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r2__fast2_ok$next[0:0]$14000 1'0 case assign $3\data_r2__fast2_ok$next[0:0]$14000 $2\data_r2__fast2_ok$next[0:0]$13999 end sync always update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$13994 update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$13995 end attribute \src "libresoc.v:201177.3-201198.6" process $proc$libresoc.v:201177$14001 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r3__nia$next[63:0]$14002 $2\data_r3__nia$next[63:0]$14006 assign { } { } assign $0\data_r3__nia_ok$next[0:0]$14003 $3\data_r3__nia_ok$next[0:0]$14008 attribute \src "libresoc.v:201178.5-201178.29" switch \initial attribute \src "libresoc.v:201178.9-201178.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r3__nia_ok$next[0:0]$14005 $1\data_r3__nia$next[63:0]$14004 } { \nia_ok \alu_trap0_nia } case assign $1\data_r3__nia$next[63:0]$14004 \data_r3__nia assign $1\data_r3__nia_ok$next[0:0]$14005 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r3__nia_ok$next[0:0]$14007 $2\data_r3__nia$next[63:0]$14006 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r3__nia$next[63:0]$14006 $1\data_r3__nia$next[63:0]$14004 assign $2\data_r3__nia_ok$next[0:0]$14007 $1\data_r3__nia_ok$next[0:0]$14005 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r3__nia_ok$next[0:0]$14008 1'0 case assign $3\data_r3__nia_ok$next[0:0]$14008 $2\data_r3__nia_ok$next[0:0]$14007 end sync always update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14002 update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14003 end attribute \src "libresoc.v:201199.3-201220.6" process $proc$libresoc.v:201199$14009 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\data_r4__msr$next[63:0]$14010 $2\data_r4__msr$next[63:0]$14014 assign { } { } assign $0\data_r4__msr_ok$next[0:0]$14011 $3\data_r4__msr_ok$next[0:0]$14016 attribute \src "libresoc.v:201200.5-201200.29" switch \initial attribute \src "libresoc.v:201200.9-201200.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $1\data_r4__msr_ok$next[0:0]$14013 $1\data_r4__msr$next[63:0]$14012 } { \msr_ok \alu_trap0_msr } case assign $1\data_r4__msr$next[63:0]$14012 \data_r4__msr assign $1\data_r4__msr_ok$next[0:0]$14013 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { $2\data_r4__msr_ok$next[0:0]$14015 $2\data_r4__msr$next[63:0]$14014 } 65'00000000000000000000000000000000000000000000000000000000000000000 case assign $2\data_r4__msr$next[63:0]$14014 $1\data_r4__msr$next[63:0]$14012 assign $2\data_r4__msr_ok$next[0:0]$14015 $1\data_r4__msr_ok$next[0:0]$14013 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\data_r4__msr_ok$next[0:0]$14016 1'0 case assign $3\data_r4__msr_ok$next[0:0]$14016 $2\data_r4__msr_ok$next[0:0]$14015 end sync always update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14010 update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14011 end attribute \src "libresoc.v:201221.3-201230.6" process $proc$libresoc.v:201221$14017 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$14018 $1\src_r0$next[63:0]$14019 attribute \src "libresoc.v:201222.5-201222.29" switch \initial attribute \src "libresoc.v:201222.9-201222.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r0$next[63:0]$14019 \src1_i case assign $1\src_r0$next[63:0]$14019 \src_r0 end sync always update \src_r0$next $0\src_r0$next[63:0]$14018 end attribute \src "libresoc.v:201231.3-201240.6" process $proc$libresoc.v:201231$14020 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$14021 $1\src_r1$next[63:0]$14022 attribute \src "libresoc.v:201232.5-201232.29" switch \initial attribute \src "libresoc.v:201232.9-201232.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r1$next[63:0]$14022 \src2_i case assign $1\src_r1$next[63:0]$14022 \src_r1 end sync always update \src_r1$next $0\src_r1$next[63:0]$14021 end attribute \src "libresoc.v:201241.3-201250.6" process $proc$libresoc.v:201241$14023 assign { } { } assign { } { } assign $0\src_r2$next[63:0]$14024 $1\src_r2$next[63:0]$14025 attribute \src "libresoc.v:201242.5-201242.29" switch \initial attribute \src "libresoc.v:201242.9-201242.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r2$next[63:0]$14025 \src3_i case assign $1\src_r2$next[63:0]$14025 \src_r2 end sync always update \src_r2$next $0\src_r2$next[63:0]$14024 end attribute \src "libresoc.v:201251.3-201260.6" process $proc$libresoc.v:201251$14026 assign { } { } assign { } { } assign $0\src_r3$next[63:0]$14027 $1\src_r3$next[63:0]$14028 attribute \src "libresoc.v:201252.5-201252.29" switch \initial attribute \src "libresoc.v:201252.9-201252.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" switch \src_l_q_src [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src_r3$next[63:0]$14028 \src4_i case assign $1\src_r3$next[63:0]$14028 \src_r3 end sync always update \src_r3$next $0\src_r3$next[63:0]$14027 end attribute \src "libresoc.v:201261.3-201269.6" process $proc$libresoc.v:201261$14029 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$14030 $1\alui_l_r_alui$next[0:0]$14031 attribute \src "libresoc.v:201262.5-201262.29" switch \initial attribute \src "libresoc.v:201262.9-201262.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alui_l_r_alui$next[0:0]$14031 1'1 case assign $1\alui_l_r_alui$next[0:0]$14031 \$89 end sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14030 end attribute \src "libresoc.v:201270.3-201278.6" process $proc$libresoc.v:201270$14032 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$14033 $1\alu_l_r_alu$next[0:0]$14034 attribute \src "libresoc.v:201271.5-201271.29" switch \initial attribute \src "libresoc.v:201271.9-201271.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\alu_l_r_alu$next[0:0]$14034 1'1 case assign $1\alu_l_r_alu$next[0:0]$14034 \$91 end sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14033 end attribute \src "libresoc.v:201279.3-201288.6" process $proc$libresoc.v:201279$14035 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] attribute \src "libresoc.v:201280.5-201280.29" switch \initial attribute \src "libresoc.v:201280.9-201280.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest1_o[63:0] \data_r0__o case assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest1_o $0\dest1_o[63:0] end attribute \src "libresoc.v:201289.3-201298.6" process $proc$libresoc.v:201289$14036 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] attribute \src "libresoc.v:201290.5-201290.29" switch \initial attribute \src "libresoc.v:201290.9-201290.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest2_o[63:0] \data_r1__fast1 case assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest2_o $0\dest2_o[63:0] end attribute \src "libresoc.v:201299.3-201308.6" process $proc$libresoc.v:201299$14037 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] attribute \src "libresoc.v:201300.5-201300.29" switch \initial attribute \src "libresoc.v:201300.9-201300.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest3_o[63:0] \data_r2__fast2 case assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest3_o $0\dest3_o[63:0] end attribute \src "libresoc.v:201309.3-201318.6" process $proc$libresoc.v:201309$14038 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] attribute \src "libresoc.v:201310.5-201310.29" switch \initial attribute \src "libresoc.v:201310.9-201310.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest4_o[63:0] \data_r3__nia case assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest4_o $0\dest4_o[63:0] end attribute \src "libresoc.v:201319.3-201328.6" process $proc$libresoc.v:201319$14039 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] attribute \src "libresoc.v:201320.5-201320.29" switch \initial attribute \src "libresoc.v:201320.9-201320.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" switch \$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\dest5_o[63:0] \data_r4__msr case assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dest5_o $0\dest5_o[63:0] end attribute \src "libresoc.v:201329.3-201337.6" process $proc$libresoc.v:201329$14040 assign { } { } assign { } { } assign $0\prev_wr_go$next[4:0]$14041 $1\prev_wr_go$next[4:0]$14042 attribute \src "libresoc.v:201330.5-201330.29" switch \initial attribute \src "libresoc.v:201330.9-201330.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\prev_wr_go$next[4:0]$14042 5'00000 case assign $1\prev_wr_go$next[4:0]$14042 \$21 end sync always update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14041 end connect \$5 $reduce_and$libresoc.v:200777$13828_Y connect \$99 $and$libresoc.v:200778$13829_Y connect \$101 $and$libresoc.v:200779$13830_Y connect \$103 $and$libresoc.v:200780$13831_Y connect \$105 $and$libresoc.v:200781$13832_Y connect \$107 $and$libresoc.v:200782$13833_Y connect \$109 $and$libresoc.v:200783$13834_Y connect \$111 $and$libresoc.v:200784$13835_Y connect \$113 $and$libresoc.v:200785$13836_Y connect \$115 $and$libresoc.v:200786$13837_Y connect \$117 $and$libresoc.v:200787$13838_Y connect \$11 $and$libresoc.v:200788$13839_Y connect \$119 $and$libresoc.v:200789$13840_Y connect \$121 $and$libresoc.v:200790$13841_Y connect \$123 $and$libresoc.v:200791$13842_Y connect \$13 $not$libresoc.v:200792$13843_Y connect \$15 $and$libresoc.v:200793$13844_Y connect \$17 $not$libresoc.v:200794$13845_Y connect \$19 $and$libresoc.v:200795$13846_Y connect \$21 $and$libresoc.v:200796$13847_Y connect \$25 $not$libresoc.v:200797$13848_Y connect \$27 $and$libresoc.v:200798$13849_Y connect \$24 $reduce_or$libresoc.v:200799$13850_Y connect \$23 $not$libresoc.v:200800$13851_Y connect \$31 $and$libresoc.v:200801$13852_Y connect \$33 $reduce_or$libresoc.v:200802$13853_Y connect \$35 $reduce_or$libresoc.v:200803$13854_Y connect \$37 $or$libresoc.v:200804$13855_Y connect \$3 $and$libresoc.v:200805$13856_Y connect \$39 $not$libresoc.v:200806$13857_Y connect \$41 $and$libresoc.v:200807$13858_Y connect \$43 $and$libresoc.v:200808$13859_Y connect \$45 $eq$libresoc.v:200809$13860_Y connect \$47 $and$libresoc.v:200810$13861_Y connect \$49 $eq$libresoc.v:200811$13862_Y connect \$51 $and$libresoc.v:200812$13863_Y connect \$53 $and$libresoc.v:200813$13864_Y connect \$55 $and$libresoc.v:200814$13865_Y connect \$57 $or$libresoc.v:200815$13866_Y connect \$59 $or$libresoc.v:200816$13867_Y connect \$61 $or$libresoc.v:200817$13868_Y connect \$63 $or$libresoc.v:200818$13869_Y connect \$65 $and$libresoc.v:200819$13870_Y connect \$67 $and$libresoc.v:200820$13871_Y connect \$6 $not$libresoc.v:200821$13872_Y connect \$69 $or$libresoc.v:200822$13873_Y connect \$71 $and$libresoc.v:200823$13874_Y connect \$73 $and$libresoc.v:200824$13875_Y connect \$75 $and$libresoc.v:200825$13876_Y connect \$77 $and$libresoc.v:200826$13877_Y connect \$79 $and$libresoc.v:200827$13878_Y connect \$81 $ternary$libresoc.v:200828$13879_Y connect \$83 $ternary$libresoc.v:200829$13880_Y connect \$85 $ternary$libresoc.v:200830$13881_Y connect \$87 $ternary$libresoc.v:200831$13882_Y connect \$8 $or$libresoc.v:200832$13883_Y connect \$89 $and$libresoc.v:200833$13884_Y connect \$91 $and$libresoc.v:200834$13885_Y connect \$93 $and$libresoc.v:200835$13886_Y connect \$95 $and$libresoc.v:200836$13887_Y connect \$97 $not$libresoc.v:200837$13888_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 connect \cu_rd__rel_o \$99 connect \cu_busy_o \opc_l_q_opc connect \alu_l_s_alu \all_rd_pulse connect \alu_trap0_n_ready_i \alu_l_q_alu connect \alui_l_s_alui \all_rd_pulse connect \alu_trap0_p_valid_i \alui_l_q_alui connect \alu_trap0_fast2$2 \$87 connect \alu_trap0_fast1$1 \$85 connect \alu_trap0_rb \$83 connect \alu_trap0_ra \$81 connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } connect \reset_r \$63 connect \reset_w \$61 connect \rst_r \$59 connect \reset \$57 connect \wr_any \$37 connect \cu_done_o \$31 connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } connect \alu_pulse \alu_done_rise connect \alu_done_rise \$19 connect \alu_done_dly$next \alu_done connect \alu_done \alu_trap0_n_valid_o connect \all_rd_pulse \all_rd_rise connect \all_rd_rise \$15 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end attribute \src "libresoc.v:201371.1-201429.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l attribute \src "libresoc.v:201372.7-201372.20" wire $0\initial[0:0] attribute \src "libresoc.v:201417.3-201425.6" wire $0\q_int$next[0:0]$14092 attribute \src "libresoc.v:201415.3-201416.27" wire $0\q_int[0:0] attribute \src "libresoc.v:201417.3-201425.6" wire $1\q_int$next[0:0]$14093 attribute \src "libresoc.v:201394.7-201394.19" wire $1\q_int[0:0] attribute \src "libresoc.v:201407.17-201407.96" wire $and$libresoc.v:201407$14082_Y attribute \src "libresoc.v:201412.17-201412.96" wire $and$libresoc.v:201412$14087_Y attribute \src "libresoc.v:201409.18-201409.93" wire $not$libresoc.v:201409$14084_Y attribute \src "libresoc.v:201411.17-201411.92" wire $not$libresoc.v:201411$14086_Y attribute \src "libresoc.v:201414.17-201414.92" wire $not$libresoc.v:201414$14089_Y attribute \src "libresoc.v:201408.18-201408.98" wire $or$libresoc.v:201408$14083_Y attribute \src "libresoc.v:201410.18-201410.99" wire $or$libresoc.v:201410$14085_Y attribute \src "libresoc.v:201413.17-201413.97" wire $or$libresoc.v:201413$14088_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:201372.7-201372.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:201407$14082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:201407$14082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:201412$14087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:201412$14087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:201409$14084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd connect \Y $not$libresoc.v:201409$14084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:201411$14086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd connect \Y $not$libresoc.v:201411$14086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:201414$14089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd connect \Y $not$libresoc.v:201414$14089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:201408$14083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd connect \Y $or$libresoc.v:201408$14083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:201410$14085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int connect \Y $or$libresoc.v:201410$14085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:201413$14088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd connect \Y $or$libresoc.v:201413$14088_Y end attribute \src "libresoc.v:201372.7-201372.20" process $proc$libresoc.v:201372$14094 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:201394.7-201394.19" process $proc$libresoc.v:201394$14095 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:201415.3-201416.27" process $proc$libresoc.v:201415$14090 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:201417.3-201425.6" process $proc$libresoc.v:201417$14091 assign { } { } assign { } { } assign $0\q_int$next[0:0]$14092 $1\q_int$next[0:0]$14093 attribute \src "libresoc.v:201418.5-201418.29" switch \initial attribute \src "libresoc.v:201418.9-201418.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$14093 1'0 case assign $1\q_int$next[0:0]$14093 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$14092 end connect \$9 $and$libresoc.v:201407$14082_Y connect \$11 $or$libresoc.v:201408$14083_Y connect \$13 $not$libresoc.v:201409$14084_Y connect \$15 $or$libresoc.v:201410$14085_Y connect \$1 $not$libresoc.v:201411$14086_Y connect \$3 $and$libresoc.v:201412$14087_Y connect \$5 $or$libresoc.v:201413$14088_Y connect \$7 $not$libresoc.v:201414$14089_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end attribute \src "libresoc.v:201433.1-201491.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l attribute \src "libresoc.v:201434.7-201434.20" wire $0\initial[0:0] attribute \src "libresoc.v:201479.3-201487.6" wire $0\q_int$next[0:0]$14106 attribute \src "libresoc.v:201477.3-201478.27" wire $0\q_int[0:0] attribute \src "libresoc.v:201479.3-201487.6" wire $1\q_int$next[0:0]$14107 attribute \src "libresoc.v:201456.7-201456.19" wire $1\q_int[0:0] attribute \src "libresoc.v:201469.17-201469.96" wire $and$libresoc.v:201469$14096_Y attribute \src "libresoc.v:201474.17-201474.96" wire $and$libresoc.v:201474$14101_Y attribute \src "libresoc.v:201471.18-201471.95" wire $not$libresoc.v:201471$14098_Y attribute \src "libresoc.v:201473.17-201473.94" wire $not$libresoc.v:201473$14100_Y attribute \src "libresoc.v:201476.17-201476.94" wire $not$libresoc.v:201476$14103_Y attribute \src "libresoc.v:201470.18-201470.100" wire $or$libresoc.v:201470$14097_Y attribute \src "libresoc.v:201472.18-201472.101" wire $or$libresoc.v:201472$14099_Y attribute \src "libresoc.v:201475.17-201475.99" wire $or$libresoc.v:201475$14102_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:201434.7-201434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 3 \q_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 4 \r_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:201469$14096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:201469$14096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:201474$14101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:201474$14101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:201471$14098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid connect \Y $not$libresoc.v:201471$14098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:201473$14100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid connect \Y $not$libresoc.v:201473$14100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:201476$14103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid connect \Y $not$libresoc.v:201476$14103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:201470$14097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid connect \Y $or$libresoc.v:201470$14097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:201472$14099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int connect \Y $or$libresoc.v:201472$14099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:201475$14102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid connect \Y $or$libresoc.v:201475$14102_Y end attribute \src "libresoc.v:201434.7-201434.20" process $proc$libresoc.v:201434$14108 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:201456.7-201456.19" process $proc$libresoc.v:201456$14109 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:201477.3-201478.27" process $proc$libresoc.v:201477$14104 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:201479.3-201487.6" process $proc$libresoc.v:201479$14105 assign { } { } assign { } { } assign $0\q_int$next[0:0]$14106 $1\q_int$next[0:0]$14107 attribute \src "libresoc.v:201480.5-201480.29" switch \initial attribute \src "libresoc.v:201480.9-201480.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$14107 1'0 case assign $1\q_int$next[0:0]$14107 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$14106 end connect \$9 $and$libresoc.v:201469$14096_Y connect \$11 $or$libresoc.v:201470$14097_Y connect \$13 $not$libresoc.v:201471$14098_Y connect \$15 $or$libresoc.v:201472$14099_Y connect \$1 $not$libresoc.v:201473$14100_Y connect \$3 $and$libresoc.v:201474$14101_Y connect \$5 $or$libresoc.v:201475$14102_Y connect \$7 $not$libresoc.v:201476$14103_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end attribute \src "libresoc.v:201495.1-201553.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l attribute \src "libresoc.v:201496.7-201496.20" wire $0\initial[0:0] attribute \src "libresoc.v:201541.3-201549.6" wire $0\q_int$next[0:0]$14120 attribute \src "libresoc.v:201539.3-201540.27" wire $0\q_int[0:0] attribute \src "libresoc.v:201541.3-201549.6" wire $1\q_int$next[0:0]$14121 attribute \src "libresoc.v:201518.7-201518.19" wire $1\q_int[0:0] attribute \src "libresoc.v:201531.17-201531.96" wire $and$libresoc.v:201531$14110_Y attribute \src "libresoc.v:201536.17-201536.96" wire $and$libresoc.v:201536$14115_Y attribute \src "libresoc.v:201533.18-201533.93" wire $not$libresoc.v:201533$14112_Y attribute \src "libresoc.v:201535.17-201535.92" wire $not$libresoc.v:201535$14114_Y attribute \src "libresoc.v:201538.17-201538.92" wire $not$libresoc.v:201538$14117_Y attribute \src "libresoc.v:201532.18-201532.98" wire $or$libresoc.v:201532$14111_Y attribute \src "libresoc.v:201534.18-201534.99" wire $or$libresoc.v:201534$14113_Y attribute \src "libresoc.v:201537.17-201537.97" wire $or$libresoc.v:201537$14116_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "libresoc.v:201496.7-201496.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" wire \qlq_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \qn_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire input 3 \r_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $and $and$libresoc.v:201531$14110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 connect \Y $and$libresoc.v:201531$14110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $and $and$libresoc.v:201536$14115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 connect \Y $and$libresoc.v:201536$14115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" cell $not $not$libresoc.v:201533$14112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri connect \Y $not$libresoc.v:201533$14112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $not $not$libresoc.v:201535$14114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri connect \Y $not$libresoc.v:201535$14114_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $not $not$libresoc.v:201538$14117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri connect \Y $not$libresoc.v:201538$14117_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" cell $or $or$libresoc.v:201532$14111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri connect \Y $or$libresoc.v:201532$14111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" cell $or $or$libresoc.v:201534$14113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int connect \Y $or$libresoc.v:201534$14113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" cell $or $or$libresoc.v:201537$14116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri connect \Y $or$libresoc.v:201537$14116_Y end attribute \src "libresoc.v:201496.7-201496.20" process $proc$libresoc.v:201496$14122 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:201518.7-201518.19" process $proc$libresoc.v:201518$14123 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end attribute \src "libresoc.v:201539.3-201540.27" process $proc$libresoc.v:201539$14118 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end attribute \src "libresoc.v:201541.3-201549.6" process $proc$libresoc.v:201541$14119 assign { } { } assign { } { } assign $0\q_int$next[0:0]$14120 $1\q_int$next[0:0]$14121 attribute \src "libresoc.v:201542.5-201542.29" switch \initial attribute \src "libresoc.v:201542.9-201542.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\q_int$next[0:0]$14121 1'0 case assign $1\q_int$next[0:0]$14121 \$5 end sync always update \q_int$next $0\q_int$next[0:0]$14120 end connect \$9 $and$libresoc.v:201531$14110_Y connect \$11 $or$libresoc.v:201532$14111_Y connect \$13 $not$libresoc.v:201533$14112_Y connect \$15 $or$libresoc.v:201534$14113_Y connect \$1 $not$libresoc.v:201535$14114_Y connect \$3 $and$libresoc.v:201536$14115_Y connect \$5 $or$libresoc.v:201537$14116_Y connect \$7 $not$libresoc.v:201538$14117_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end attribute \src "libresoc.v:201557.1-201623.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a attribute \src "libresoc.v:201602.17-201602.91" wire $not$libresoc.v:201602$14124_Y attribute \src "libresoc.v:201604.18-201604.93" wire $not$libresoc.v:201604$14126_Y attribute \src "libresoc.v:201606.18-201606.93" wire $not$libresoc.v:201606$14128_Y attribute \src "libresoc.v:201607.17-201607.89" wire width 6 $not$libresoc.v:201607$14129_Y attribute \src "libresoc.v:201609.18-201609.93" wire $not$libresoc.v:201609$14131_Y attribute \src "libresoc.v:201612.17-201612.91" wire $not$libresoc.v:201612$14134_Y attribute \src "libresoc.v:201603.18-201603.106" wire $reduce_or$libresoc.v:201603$14125_Y attribute \src "libresoc.v:201605.18-201605.106" wire $reduce_or$libresoc.v:201605$14127_Y attribute \src "libresoc.v:201608.18-201608.106" wire $reduce_or$libresoc.v:201608$14130_Y attribute \src "libresoc.v:201610.18-201610.90" wire $reduce_or$libresoc.v:201610$14132_Y attribute \src "libresoc.v:201611.17-201611.103" wire $reduce_or$libresoc.v:201611$14133_Y attribute \src "libresoc.v:201613.17-201613.105" wire $reduce_or$libresoc.v:201613$14135_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 6 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 6 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 6 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201602$14124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:201602$14124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201604$14126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:201604$14126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201606$14128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:201606$14128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201607$14129 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i connect \Y $not$libresoc.v:201607$14129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201609$14131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 connect \Y $not$libresoc.v:201609$14131_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201612$14134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:201612$14134_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201603$14125 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:201603$14125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201605$14127 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } connect \Y $reduce_or$libresoc.v:201605$14127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201608$14130 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } connect \Y $reduce_or$libresoc.v:201608$14130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201610$14132 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201610$14132_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201611$14133 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:201611$14133_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201613$14135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:201613$14135_Y end connect \$7 $not$libresoc.v:201602$14124_Y connect \$12 $reduce_or$libresoc.v:201603$14125_Y connect \$11 $not$libresoc.v:201604$14126_Y connect \$16 $reduce_or$libresoc.v:201605$14127_Y connect \$15 $not$libresoc.v:201606$14128_Y connect \$1 $not$libresoc.v:201607$14129_Y connect \$20 $reduce_or$libresoc.v:201608$14130_Y connect \$19 $not$libresoc.v:201609$14131_Y connect \$23 $reduce_or$libresoc.v:201610$14132_Y connect \$4 $reduce_or$libresoc.v:201611$14133_Y connect \$3 $not$libresoc.v:201612$14134_Y connect \$8 $reduce_or$libresoc.v:201613$14135_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:201627.1-201648.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr attribute \src "libresoc.v:201642.17-201642.89" wire $not$libresoc.v:201642$14136_Y attribute \src "libresoc.v:201643.17-201643.89" wire $reduce_or$libresoc.v:201643$14137_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201642$14136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:201642$14136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201643$14137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201643$14137_Y end connect \$1 $not$libresoc.v:201642$14136_Y connect \$3 $reduce_or$libresoc.v:201643$14137_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:201652.1-201709.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 attribute \src "libresoc.v:201691.17-201691.91" wire $not$libresoc.v:201691$14138_Y attribute \src "libresoc.v:201693.18-201693.93" wire $not$libresoc.v:201693$14140_Y attribute \src "libresoc.v:201695.18-201695.93" wire $not$libresoc.v:201695$14142_Y attribute \src "libresoc.v:201696.17-201696.89" wire width 5 $not$libresoc.v:201696$14143_Y attribute \src "libresoc.v:201699.17-201699.91" wire $not$libresoc.v:201699$14146_Y attribute \src "libresoc.v:201692.18-201692.106" wire $reduce_or$libresoc.v:201692$14139_Y attribute \src "libresoc.v:201694.18-201694.106" wire $reduce_or$libresoc.v:201694$14141_Y attribute \src "libresoc.v:201697.18-201697.90" wire $reduce_or$libresoc.v:201697$14144_Y attribute \src "libresoc.v:201698.17-201698.103" wire $reduce_or$libresoc.v:201698$14145_Y attribute \src "libresoc.v:201700.17-201700.105" wire $reduce_or$libresoc.v:201700$14147_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 5 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 5 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 5 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201691$14138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:201691$14138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201693$14140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:201693$14140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201695$14142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:201695$14142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201696$14143 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i connect \Y $not$libresoc.v:201696$14143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201699$14146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:201699$14146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201692$14139 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:201692$14139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201694$14141 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } connect \Y $reduce_or$libresoc.v:201694$14141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201697$14144 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201697$14144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201698$14145 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:201698$14145_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201700$14147 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:201700$14147_Y end connect \$7 $not$libresoc.v:201691$14138_Y connect \$12 $reduce_or$libresoc.v:201692$14139_Y connect \$11 $not$libresoc.v:201693$14140_Y connect \$16 $reduce_or$libresoc.v:201694$14141_Y connect \$15 $not$libresoc.v:201695$14142_Y connect \$1 $not$libresoc.v:201696$14143_Y connect \$19 $reduce_or$libresoc.v:201697$14144_Y connect \$4 $reduce_or$libresoc.v:201698$14145_Y connect \$3 $not$libresoc.v:201699$14146_Y connect \$8 $reduce_or$libresoc.v:201700$14147_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:201713.1-201815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o attribute \src "libresoc.v:201782.17-201782.91" wire $not$libresoc.v:201782$14148_Y attribute \src "libresoc.v:201784.18-201784.93" wire $not$libresoc.v:201784$14150_Y attribute \src "libresoc.v:201786.18-201786.93" wire $not$libresoc.v:201786$14152_Y attribute \src "libresoc.v:201787.17-201787.89" wire width 10 $not$libresoc.v:201787$14153_Y attribute \src "libresoc.v:201789.18-201789.93" wire $not$libresoc.v:201789$14155_Y attribute \src "libresoc.v:201791.18-201791.93" wire $not$libresoc.v:201791$14157_Y attribute \src "libresoc.v:201793.18-201793.93" wire $not$libresoc.v:201793$14159_Y attribute \src "libresoc.v:201795.18-201795.93" wire $not$libresoc.v:201795$14161_Y attribute \src "libresoc.v:201797.18-201797.93" wire $not$libresoc.v:201797$14163_Y attribute \src "libresoc.v:201800.17-201800.91" wire $not$libresoc.v:201800$14166_Y attribute \src "libresoc.v:201783.18-201783.106" wire $reduce_or$libresoc.v:201783$14149_Y attribute \src "libresoc.v:201785.18-201785.106" wire $reduce_or$libresoc.v:201785$14151_Y attribute \src "libresoc.v:201788.18-201788.106" wire $reduce_or$libresoc.v:201788$14154_Y attribute \src "libresoc.v:201790.18-201790.106" wire $reduce_or$libresoc.v:201790$14156_Y attribute \src "libresoc.v:201792.18-201792.106" wire $reduce_or$libresoc.v:201792$14158_Y attribute \src "libresoc.v:201794.18-201794.106" wire $reduce_or$libresoc.v:201794$14160_Y attribute \src "libresoc.v:201796.18-201796.106" wire $reduce_or$libresoc.v:201796$14162_Y attribute \src "libresoc.v:201798.18-201798.90" wire $reduce_or$libresoc.v:201798$14164_Y attribute \src "libresoc.v:201799.17-201799.103" wire $reduce_or$libresoc.v:201799$14165_Y attribute \src "libresoc.v:201801.17-201801.105" wire $reduce_or$libresoc.v:201801$14167_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$35 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 10 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 10 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 10 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201782$14148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:201782$14148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201784$14150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:201784$14150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201786$14152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 connect \Y $not$libresoc.v:201786$14152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201787$14153 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i connect \Y $not$libresoc.v:201787$14153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201789$14155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 connect \Y $not$libresoc.v:201789$14155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201791$14157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 connect \Y $not$libresoc.v:201791$14157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201793$14159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 connect \Y $not$libresoc.v:201793$14159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201795$14161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 connect \Y $not$libresoc.v:201795$14161_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201797$14163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 connect \Y $not$libresoc.v:201797$14163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201800$14166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:201800$14166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201783$14149 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:201783$14149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201785$14151 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } connect \Y $reduce_or$libresoc.v:201785$14151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201788$14154 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } connect \Y $reduce_or$libresoc.v:201788$14154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201790$14156 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } connect \Y $reduce_or$libresoc.v:201790$14156_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201792$14158 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } connect \Y $reduce_or$libresoc.v:201792$14158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201794$14160 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } connect \Y $reduce_or$libresoc.v:201794$14160_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201796$14162 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } connect \Y $reduce_or$libresoc.v:201796$14162_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201798$14164 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201798$14164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201799$14165 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:201799$14165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201801$14167 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:201801$14167_Y end connect \$7 $not$libresoc.v:201782$14148_Y connect \$12 $reduce_or$libresoc.v:201783$14149_Y connect \$11 $not$libresoc.v:201784$14150_Y connect \$16 $reduce_or$libresoc.v:201785$14151_Y connect \$15 $not$libresoc.v:201786$14152_Y connect \$1 $not$libresoc.v:201787$14153_Y connect \$20 $reduce_or$libresoc.v:201788$14154_Y connect \$19 $not$libresoc.v:201789$14155_Y connect \$24 $reduce_or$libresoc.v:201790$14156_Y connect \$23 $not$libresoc.v:201791$14157_Y connect \$28 $reduce_or$libresoc.v:201792$14158_Y connect \$27 $not$libresoc.v:201793$14159_Y connect \$32 $reduce_or$libresoc.v:201794$14160_Y connect \$31 $not$libresoc.v:201795$14161_Y connect \$36 $reduce_or$libresoc.v:201796$14162_Y connect \$35 $not$libresoc.v:201797$14163_Y connect \$39 $reduce_or$libresoc.v:201798$14164_Y connect \$4 $reduce_or$libresoc.v:201799$14165_Y connect \$3 $not$libresoc.v:201800$14166_Y connect \$8 $reduce_or$libresoc.v:201801$14167_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 connect \t8 \$31 connect \t7 \$27 connect \t6 \$23 connect \t5 \$19 connect \t4 \$15 connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:201819.1-201840.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 attribute \src "libresoc.v:201834.17-201834.89" wire $not$libresoc.v:201834$14168_Y attribute \src "libresoc.v:201835.17-201835.89" wire $reduce_or$libresoc.v:201835$14169_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201834$14168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:201834$14168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201835$14169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201835$14169_Y end connect \$1 $not$libresoc.v:201834$14168_Y connect \$3 $reduce_or$libresoc.v:201835$14169_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:201844.1-201865.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr attribute \src "libresoc.v:201859.17-201859.89" wire $not$libresoc.v:201859$14170_Y attribute \src "libresoc.v:201860.17-201860.89" wire $reduce_or$libresoc.v:201860$14171_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201859$14170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i connect \Y $not$libresoc.v:201859$14170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201860$14171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201860$14171_Y end connect \$1 $not$libresoc.v:201859$14170_Y connect \$3 $reduce_or$libresoc.v:201860$14171_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end attribute \src "libresoc.v:201869.1-201899.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia attribute \src "libresoc.v:201890.17-201890.89" wire width 2 $not$libresoc.v:201890$14172_Y attribute \src "libresoc.v:201892.17-201892.91" wire $not$libresoc.v:201892$14174_Y attribute \src "libresoc.v:201891.17-201891.103" wire $reduce_or$libresoc.v:201891$14173_Y attribute \src "libresoc.v:201893.17-201893.89" wire $reduce_or$libresoc.v:201893$14175_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 2 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 2 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 2 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201890$14172 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i connect \Y $not$libresoc.v:201890$14172_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201892$14174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:201892$14174_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201891$14173 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:201891$14173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201893$14175 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201893$14175_Y end connect \$1 $not$libresoc.v:201890$14172_Y connect \$4 $reduce_or$libresoc.v:201891$14173_Y connect \$3 $not$libresoc.v:201892$14174_Y connect \$7 $reduce_or$libresoc.v:201893$14175_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:201903.1-201942.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca attribute \src "libresoc.v:201930.17-201930.91" wire $not$libresoc.v:201930$14176_Y attribute \src "libresoc.v:201932.17-201932.89" wire width 3 $not$libresoc.v:201932$14178_Y attribute \src "libresoc.v:201934.17-201934.91" wire $not$libresoc.v:201934$14180_Y attribute \src "libresoc.v:201931.18-201931.90" wire $reduce_or$libresoc.v:201931$14177_Y attribute \src "libresoc.v:201933.17-201933.103" wire $reduce_or$libresoc.v:201933$14179_Y attribute \src "libresoc.v:201935.17-201935.105" wire $reduce_or$libresoc.v:201935$14181_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 3 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 3 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 3 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201930$14176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:201930$14176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201932$14178 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i connect \Y $not$libresoc.v:201932$14178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201934$14180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:201934$14180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201931$14177 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201931$14177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201933$14179 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:201933$14179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201935$14181 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:201935$14181_Y end connect \$7 $not$libresoc.v:201930$14176_Y connect \$11 $reduce_or$libresoc.v:201931$14177_Y connect \$1 $not$libresoc.v:201932$14178_Y connect \$4 $reduce_or$libresoc.v:201933$14179_Y connect \$3 $not$libresoc.v:201934$14180_Y connect \$8 $reduce_or$libresoc.v:201935$14181_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:201946.1-201994.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov attribute \src "libresoc.v:201979.17-201979.91" wire $not$libresoc.v:201979$14182_Y attribute \src "libresoc.v:201981.18-201981.93" wire $not$libresoc.v:201981$14184_Y attribute \src "libresoc.v:201983.17-201983.89" wire width 4 $not$libresoc.v:201983$14186_Y attribute \src "libresoc.v:201985.17-201985.91" wire $not$libresoc.v:201985$14188_Y attribute \src "libresoc.v:201980.18-201980.106" wire $reduce_or$libresoc.v:201980$14183_Y attribute \src "libresoc.v:201982.18-201982.90" wire $reduce_or$libresoc.v:201982$14185_Y attribute \src "libresoc.v:201984.17-201984.103" wire $reduce_or$libresoc.v:201984$14187_Y attribute \src "libresoc.v:201986.17-201986.105" wire $reduce_or$libresoc.v:201986$14189_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 4 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201979$14182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:201979$14182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201981$14184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:201981$14184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:201983$14186 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i connect \Y $not$libresoc.v:201983$14186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:201985$14188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:201985$14188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201980$14183 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:201980$14183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:201982$14185 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:201982$14185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201984$14187 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:201984$14187_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:201986$14189 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:201986$14189_Y end connect \$7 $not$libresoc.v:201979$14182_Y connect \$12 $reduce_or$libresoc.v:201980$14183_Y connect \$11 $not$libresoc.v:201981$14184_Y connect \$15 $reduce_or$libresoc.v:201982$14185_Y connect \$1 $not$libresoc.v:201983$14186_Y connect \$4 $reduce_or$libresoc.v:201984$14187_Y connect \$3 $not$libresoc.v:201985$14188_Y connect \$8 $reduce_or$libresoc.v:201986$14189_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:201998.1-202046.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so attribute \src "libresoc.v:202031.17-202031.91" wire $not$libresoc.v:202031$14190_Y attribute \src "libresoc.v:202033.18-202033.93" wire $not$libresoc.v:202033$14192_Y attribute \src "libresoc.v:202035.17-202035.89" wire width 4 $not$libresoc.v:202035$14194_Y attribute \src "libresoc.v:202037.17-202037.91" wire $not$libresoc.v:202037$14196_Y attribute \src "libresoc.v:202032.18-202032.106" wire $reduce_or$libresoc.v:202032$14191_Y attribute \src "libresoc.v:202034.18-202034.90" wire $reduce_or$libresoc.v:202034$14193_Y attribute \src "libresoc.v:202036.17-202036.103" wire $reduce_or$libresoc.v:202036$14195_Y attribute \src "libresoc.v:202038.17-202038.105" wire $reduce_or$libresoc.v:202038$14197_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" wire \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" wire \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" wire output 2 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 4 input 3 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" wire width 4 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 4 output 1 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:202031$14190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 connect \Y $not$libresoc.v:202031$14190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:202033$14192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 connect \Y $not$libresoc.v:202033$14192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" cell $not $not$libresoc.v:202035$14194 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i connect \Y $not$libresoc.v:202035$14194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $not $not$libresoc.v:202037$14196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 connect \Y $not$libresoc.v:202037$14196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:202032$14191 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } connect \Y $reduce_or$libresoc.v:202032$14191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" cell $reduce_or $reduce_or$libresoc.v:202034$14193 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o connect \Y $reduce_or$libresoc.v:202034$14193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:202036$14195 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } connect \Y $reduce_or$libresoc.v:202036$14195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" cell $reduce_or $reduce_or$libresoc.v:202038$14197 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } connect \Y $reduce_or$libresoc.v:202038$14197_Y end connect \$7 $not$libresoc.v:202031$14190_Y connect \$12 $reduce_or$libresoc.v:202032$14191_Y connect \$11 $not$libresoc.v:202033$14192_Y connect \$15 $reduce_or$libresoc.v:202034$14193_Y connect \$1 $not$libresoc.v:202035$14194_Y connect \$4 $reduce_or$libresoc.v:202036$14195_Y connect \$3 $not$libresoc.v:202037$14196_Y connect \$8 $reduce_or$libresoc.v:202038$14197_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 connect \t2 \$7 connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end attribute \src "libresoc.v:202050.1-202370.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer attribute \src "libresoc.v:202051.7-202051.20" wire $0\initial[0:0] attribute \src "libresoc.v:202330.3-202338.6" wire width 3 $0\ren_delay$11$next[2:0]$14221 attribute \src "libresoc.v:202228.3-202229.43" wire width 3 $0\ren_delay$11[2:0]$14210 attribute \src "libresoc.v:202187.13-202187.34" wire width 3 $0\ren_delay$11[2:0]$14227 attribute \src "libresoc.v:202292.3-202300.6" wire width 3 $0\ren_delay$18$next[2:0]$14213 attribute \src "libresoc.v:202226.3-202227.43" wire width 3 $0\ren_delay$18[2:0]$14208 attribute \src "libresoc.v:202191.13-202191.34" wire width 3 $0\ren_delay$18[2:0]$14229 attribute \src "libresoc.v:202311.3-202319.6" wire width 3 $0\ren_delay$next[2:0]$14217 attribute \src "libresoc.v:202230.3-202231.35" wire width 3 $0\ren_delay[2:0] attribute \src "libresoc.v:202320.3-202329.6" wire width 2 $0\src1__data_o[1:0] attribute \src "libresoc.v:202339.3-202348.6" wire width 2 $0\src2__data_o[1:0] attribute \src "libresoc.v:202301.3-202310.6" wire width 2 $0\src3__data_o[1:0] attribute \src "libresoc.v:202330.3-202338.6" wire width 3 $1\ren_delay$11$next[2:0]$14222 attribute \src "libresoc.v:202292.3-202300.6" wire width 3 $1\ren_delay$18$next[2:0]$14214 attribute \src "libresoc.v:202311.3-202319.6" wire width 3 $1\ren_delay$next[2:0]$14218 attribute \src "libresoc.v:202185.13-202185.29" wire width 3 $1\ren_delay[2:0] attribute \src "libresoc.v:202320.3-202329.6" wire width 2 $1\src1__data_o[1:0] attribute \src "libresoc.v:202339.3-202348.6" wire width 2 $1\src2__data_o[1:0] attribute \src "libresoc.v:202301.3-202310.6" wire width 2 $1\src3__data_o[1:0] attribute \src "libresoc.v:202217.17-202217.109" wire width 2 $or$libresoc.v:202217$14198_Y attribute \src "libresoc.v:202219.18-202219.126" wire width 2 $or$libresoc.v:202219$14200_Y attribute \src "libresoc.v:202220.18-202220.111" wire width 2 $or$libresoc.v:202220$14201_Y attribute \src "libresoc.v:202222.18-202222.126" wire width 2 $or$libresoc.v:202222$14203_Y attribute \src "libresoc.v:202223.18-202223.111" wire width 2 $or$libresoc.v:202223$14204_Y attribute \src "libresoc.v:202225.17-202225.125" wire width 2 $or$libresoc.v:202225$14206_Y attribute \src "libresoc.v:202218.18-202218.100" wire $reduce_or$libresoc.v:202218$14199_Y attribute \src "libresoc.v:202221.18-202221.100" wire $reduce_or$libresoc.v:202221$14202_Y attribute \src "libresoc.v:202224.17-202224.95" wire $reduce_or$libresoc.v:202224$14205_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$16 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$23 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 16 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:825" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 12 \data_i$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 14 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 6 output 3 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen attribute \src "libresoc.v:202051.7-202051.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest20__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_dest30__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_r0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_r0__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_src10__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_src20__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src20__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_src30__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_src30__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_0_w0__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_dest11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest21__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_dest31__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_r1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_r1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_src11__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src11__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_src21__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src21__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_src31__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_src31__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_1_w1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_dest12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest22__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_dest32__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_r2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_r2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_src12__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src12__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_src22__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src22__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_src32__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_src32__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire \reg_2_w2__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 4 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 5 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 6 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 7 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 8 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 9 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 11 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 13 \wen$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:202217$14198 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 connect \Y $or$libresoc.v:202217$14198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:202219$14200 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o connect \Y $or$libresoc.v:202219$14200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:202220$14201 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 connect \Y $or$libresoc.v:202220$14201_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:202222$14203 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o connect \Y $or$libresoc.v:202222$14203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" cell $or $or$libresoc.v:202223$14204 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 connect \Y $or$libresoc.v:202223$14204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" cell $or $or$libresoc.v:202225$14206 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o connect \Y $or$libresoc.v:202225$14206_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:202218$14199 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 connect \Y $reduce_or$libresoc.v:202218$14199_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:202221$14202 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 connect \Y $reduce_or$libresoc.v:202221$14202_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" cell $reduce_or $reduce_or$libresoc.v:202224$14205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay connect \Y $reduce_or$libresoc.v:202224$14205_Y end attribute \module_not_derived 1 attribute \src "libresoc.v:202232.15-202251.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest10__data_i \reg_0_dest10__data_i connect \dest10__wen \reg_0_dest10__wen connect \dest20__data_i \reg_0_dest20__data_i connect \dest20__wen \reg_0_dest20__wen connect \dest30__data_i \reg_0_dest30__data_i connect \dest30__wen \reg_0_dest30__wen connect \r0__data_o \reg_0_r0__data_o connect \r0__ren \reg_0_r0__ren connect \src10__data_o \reg_0_src10__data_o connect \src10__ren \reg_0_src10__ren connect \src20__data_o \reg_0_src20__data_o connect \src20__ren \reg_0_src20__ren connect \src30__data_o \reg_0_src30__data_o connect \src30__ren \reg_0_src30__ren connect \w0__data_i \reg_0_w0__data_i connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:202252.15-202271.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest11__data_i \reg_1_dest11__data_i connect \dest11__wen \reg_1_dest11__wen connect \dest21__data_i \reg_1_dest21__data_i connect \dest21__wen \reg_1_dest21__wen connect \dest31__data_i \reg_1_dest31__data_i connect \dest31__wen \reg_1_dest31__wen connect \r1__data_o \reg_1_r1__data_o connect \r1__ren \reg_1_r1__ren connect \src11__data_o \reg_1_src11__data_o connect \src11__ren \reg_1_src11__ren connect \src21__data_o \reg_1_src21__data_o connect \src21__ren \reg_1_src21__ren connect \src31__data_o \reg_1_src31__data_o connect \src31__ren \reg_1_src31__ren connect \w1__data_i \reg_1_w1__data_i connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 attribute \src "libresoc.v:202272.15-202291.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest12__data_i \reg_2_dest12__data_i connect \dest12__wen \reg_2_dest12__wen connect \dest22__data_i \reg_2_dest22__data_i connect \dest22__wen \reg_2_dest22__wen connect \dest32__data_i \reg_2_dest32__data_i connect \dest32__wen \reg_2_dest32__wen connect \r2__data_o \reg_2_r2__data_o connect \r2__ren \reg_2_r2__ren connect \src12__data_o \reg_2_src12__data_o connect \src12__ren \reg_2_src12__ren connect \src22__data_o \reg_2_src22__data_o connect \src22__ren \reg_2_src22__ren connect \src32__data_o \reg_2_src32__data_o connect \src32__ren \reg_2_src32__ren connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end attribute \src "libresoc.v:202051.7-202051.20" process $proc$libresoc.v:202051$14224 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:202185.13-202185.29" process $proc$libresoc.v:202185$14225 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end attribute \src "libresoc.v:202187.13-202187.34" process $proc$libresoc.v:202187$14226 assign { } { } assign $0\ren_delay$11[2:0]$14227 3'000 sync always sync init update \ren_delay$11 $0\ren_delay$11[2:0]$14227 end attribute \src "libresoc.v:202191.13-202191.34" process $proc$libresoc.v:202191$14228 assign { } { } assign $0\ren_delay$18[2:0]$14229 3'000 sync always sync init update \ren_delay$18 $0\ren_delay$18[2:0]$14229 end attribute \src "libresoc.v:202226.3-202227.43" process $proc$libresoc.v:202226$14207 assign { } { } assign $0\ren_delay$18[2:0]$14208 \ren_delay$18$next sync posedge \coresync_clk update \ren_delay$18 $0\ren_delay$18[2:0]$14208 end attribute \src "libresoc.v:202228.3-202229.43" process $proc$libresoc.v:202228$14209 assign { } { } assign $0\ren_delay$11[2:0]$14210 \ren_delay$11$next sync posedge \coresync_clk update \ren_delay$11 $0\ren_delay$11[2:0]$14210 end attribute \src "libresoc.v:202230.3-202231.35" process $proc$libresoc.v:202230$14211 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end attribute \src "libresoc.v:202292.3-202300.6" process $proc$libresoc.v:202292$14212 assign { } { } assign { } { } assign $0\ren_delay$18$next[2:0]$14213 $1\ren_delay$18$next[2:0]$14214 attribute \src "libresoc.v:202293.5-202293.29" switch \initial attribute \src "libresoc.v:202293.9-202293.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$18$next[2:0]$14214 3'000 case assign $1\ren_delay$18$next[2:0]$14214 \src3__ren end sync always update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14213 end attribute \src "libresoc.v:202301.3-202310.6" process $proc$libresoc.v:202301$14215 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] attribute \src "libresoc.v:202302.5-202302.29" switch \initial attribute \src "libresoc.v:202302.9-202302.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src3__data_o[1:0] \$23 case assign $1\src3__data_o[1:0] 2'00 end sync always update \src3__data_o $0\src3__data_o[1:0] end attribute \src "libresoc.v:202311.3-202319.6" process $proc$libresoc.v:202311$14216 assign { } { } assign { } { } assign $0\ren_delay$next[2:0]$14217 $1\ren_delay$next[2:0]$14218 attribute \src "libresoc.v:202312.5-202312.29" switch \initial attribute \src "libresoc.v:202312.9-202312.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$next[2:0]$14218 3'000 case assign $1\ren_delay$next[2:0]$14218 \src1__ren end sync always update \ren_delay$next $0\ren_delay$next[2:0]$14217 end attribute \src "libresoc.v:202320.3-202329.6" process $proc$libresoc.v:202320$14219 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] attribute \src "libresoc.v:202321.5-202321.29" switch \initial attribute \src "libresoc.v:202321.9-202321.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src1__data_o[1:0] \$9 case assign $1\src1__data_o[1:0] 2'00 end sync always update \src1__data_o $0\src1__data_o[1:0] end attribute \src "libresoc.v:202330.3-202338.6" process $proc$libresoc.v:202330$14220 assign { } { } assign { } { } assign $0\ren_delay$11$next[2:0]$14221 $1\ren_delay$11$next[2:0]$14222 attribute \src "libresoc.v:202331.5-202331.29" switch \initial attribute \src "libresoc.v:202331.9-202331.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ren_delay$11$next[2:0]$14222 3'000 case assign $1\ren_delay$11$next[2:0]$14222 \src2__ren end sync always update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14221 end attribute \src "libresoc.v:202339.3-202348.6" process $proc$libresoc.v:202339$14223 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] attribute \src "libresoc.v:202340.5-202340.29" switch \initial attribute \src "libresoc.v:202340.9-202340.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\src2__data_o[1:0] \$16 case assign $1\src2__data_o[1:0] 2'00 end sync always update \src2__data_o $0\src2__data_o[1:0] end connect \$9 $or$libresoc.v:202217$14198_Y connect \$12 $reduce_or$libresoc.v:202218$14199_Y connect \$14 $or$libresoc.v:202219$14200_Y connect \$16 $or$libresoc.v:202220$14201_Y connect \$19 $reduce_or$libresoc.v:202221$14202_Y connect \$21 $or$libresoc.v:202222$14203_Y connect \$23 $or$libresoc.v:202223$14204_Y connect \$5 $reduce_or$libresoc.v:202224$14205_Y connect \$7 $or$libresoc.v:202225$14206_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } connect \reg_2_dest32__data_i \data_i$1 connect \reg_1_dest31__data_i \data_i$1 connect \reg_0_dest30__data_i \data_i$1 connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 connect \reg_2_dest22__data_i \data_i connect \reg_1_dest21__data_i \data_i connect \reg_0_dest20__data_i \data_i connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen connect \reg_2_dest12__data_i \data_i$3 connect \reg_1_dest11__data_i \data_i$3 connect \reg_0_dest10__data_i \data_i$3 connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end attribute \src "libresoc.v:202374.1-202691.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $0\be_out[31:0] attribute \src "libresoc.v:202606.3-202614.6" wire $0\core_irq_o$next[0:0]$14265 attribute \src "libresoc.v:202494.3-202495.37" wire $0\core_irq_o[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $0\cppr$10[7:0]$14269 attribute \src "libresoc.v:202508.3-202523.6" wire width 8 $0\cppr$next[7:0]$14248 attribute \src "libresoc.v:202498.3-202499.25" wire width 8 $0\cppr[7:0] attribute \src "libresoc.v:202615.3-202624.6" wire width 32 $0\icp_wb__dat_r[31:0] attribute \src "libresoc.v:202375.7-202375.20" wire $0\initial[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire $0\irq$12[0:0]$14270 attribute \src "libresoc.v:202508.3-202523.6" wire $0\irq$next[0:0]$14249 attribute \src "libresoc.v:202502.3-202503.23" wire $0\irq[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $0\mfrr$11[7:0]$14271 attribute \src "libresoc.v:202508.3-202523.6" wire width 8 $0\mfrr$next[7:0]$14250 attribute \src "libresoc.v:202500.3-202501.25" wire width 8 $0\mfrr[7:0] attribute \src "libresoc.v:202594.3-202605.6" wire width 8 $0\min_pri[7:0] attribute \src "libresoc.v:202584.3-202593.6" wire width 8 $0\pending_priority[7:0] attribute \src "libresoc.v:202625.3-202687.6" wire $0\wb_ack$14[0:0]$14272 attribute \src "libresoc.v:202508.3-202523.6" wire $0\wb_ack$next[0:0]$14251 attribute \src "libresoc.v:202506.3-202507.29" wire $0\wb_ack[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 32 $0\wb_rd_data$13[31:0]$14273 attribute \src "libresoc.v:202508.3-202523.6" wire width 32 $0\wb_rd_data$next[31:0]$14252 attribute \src "libresoc.v:202504.3-202505.37" wire width 32 $0\wb_rd_data[31:0] attribute \src "libresoc.v:202524.3-202554.6" wire $0\xirr_accept_rd[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 24 $0\xisr$9[23:0]$14274 attribute \src "libresoc.v:202508.3-202523.6" wire width 24 $0\xisr$next[23:0]$14253 attribute \src "libresoc.v:202496.3-202497.25" wire width 24 $0\xisr[23:0] attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $1\be_out[31:0] attribute \src "libresoc.v:202606.3-202614.6" wire $1\core_irq_o$next[0:0]$14266 attribute \src "libresoc.v:202404.7-202404.24" wire $1\core_irq_o[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $1\cppr$10[7:0]$14275 attribute \src "libresoc.v:202508.3-202523.6" wire width 8 $1\cppr$next[7:0]$14254 attribute \src "libresoc.v:202408.13-202408.25" wire width 8 $1\cppr[7:0] attribute \src "libresoc.v:202615.3-202624.6" wire width 32 $1\icp_wb__dat_r[31:0] attribute \src "libresoc.v:202625.3-202687.6" wire $1\irq$12[0:0]$14285 attribute \src "libresoc.v:202508.3-202523.6" wire $1\irq$next[0:0]$14255 attribute \src "libresoc.v:202437.7-202437.17" wire $1\irq[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $1\mfrr$11[7:0]$14276 attribute \src "libresoc.v:202508.3-202523.6" wire width 8 $1\mfrr$next[7:0]$14256 attribute \src "libresoc.v:202445.13-202445.25" wire width 8 $1\mfrr[7:0] attribute \src "libresoc.v:202594.3-202605.6" wire width 8 $1\min_pri[7:0] attribute \src "libresoc.v:202584.3-202593.6" wire width 8 $1\pending_priority[7:0] attribute \src "libresoc.v:202625.3-202687.6" wire $1\wb_ack$14[0:0]$14277 attribute \src "libresoc.v:202508.3-202523.6" wire $1\wb_ack$next[0:0]$14257 attribute \src "libresoc.v:202459.7-202459.20" wire $1\wb_ack[0:0] attribute \src "libresoc.v:202508.3-202523.6" wire width 32 $1\wb_rd_data$next[31:0]$14258 attribute \src "libresoc.v:202467.14-202467.32" wire width 32 $1\wb_rd_data[31:0] attribute \src "libresoc.v:202524.3-202554.6" wire $1\xirr_accept_rd[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 24 $1\xisr$9[23:0]$14282 attribute \src "libresoc.v:202508.3-202523.6" wire width 24 $1\xisr$next[23:0]$14259 attribute \src "libresoc.v:202477.14-202477.31" wire width 24 $1\xisr[23:0] attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $2\be_out[31:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $2\cppr$10[7:0]$14278 attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $2\mfrr$11[7:0]$14279 attribute \src "libresoc.v:202524.3-202554.6" wire $2\xirr_accept_rd[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 24 $2\xisr$9[23:0]$14283 attribute \src "libresoc.v:202555.3-202583.6" wire width 32 $3\be_out[31:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $3\cppr$10[7:0]$14280 attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $3\mfrr$11[7:0]$14281 attribute \src "libresoc.v:202524.3-202554.6" wire $3\xirr_accept_rd[0:0] attribute \src "libresoc.v:202625.3-202687.6" wire width 8 $4\cppr$10[7:0]$14284 attribute \src "libresoc.v:202524.3-202554.6" wire $4\xirr_accept_rd[0:0] attribute \src "libresoc.v:202484.18-202484.116" wire $and$libresoc.v:202484$14230_Y attribute \src "libresoc.v:202488.18-202488.116" wire $and$libresoc.v:202488$14234_Y attribute \src "libresoc.v:202490.18-202490.116" wire $and$libresoc.v:202490$14236_Y attribute \src "libresoc.v:202493.17-202493.109" wire $and$libresoc.v:202493$14239_Y attribute \src "libresoc.v:202489.18-202489.110" wire $eq$libresoc.v:202489$14235_Y attribute \src "libresoc.v:202486.18-202486.114" wire $lt$libresoc.v:202486$14232_Y attribute \src "libresoc.v:202487.18-202487.109" wire $lt$libresoc.v:202487$14233_Y attribute \src "libresoc.v:202492.18-202492.114" wire $lt$libresoc.v:202492$14238_Y attribute \src "libresoc.v:202485.18-202485.109" wire $ne$libresoc.v:202485$14231_Y attribute \src "libresoc.v:202491.18-202491.109" wire $ne$libresoc.v:202491$14237_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" wire \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" wire \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 3 \core_irq_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \core_irq_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" wire width 8 \cppr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" wire width 8 \cppr$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" wire width 8 \cppr$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" wire width 8 \cppr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire output 5 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 28 input 11 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 6 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 32 output 7 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 32 input 8 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire width 4 input 12 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 9 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 10 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 input 2 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 1 \ics_i_src attribute \src "libresoc.v:202375.7-202375.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" wire width 8 \mfrr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" wire width 8 \mfrr$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" wire width 8 \mfrr$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" wire width 8 \mfrr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 4 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" wire width 32 \wb_rd_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" wire width 32 \wb_rd_data$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" wire width 32 \wb_rd_data$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" wire width 32 \wb_rd_data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" wire \xirr_accept_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" cell $and $and$libresoc.v:202484$14230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb connect \Y $and$libresoc.v:202484$14230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" cell $and $and$libresoc.v:202488$14234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb connect \Y $and$libresoc.v:202488$14234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" cell $and $and$libresoc.v:202490$14236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb connect \Y $and$libresoc.v:202490$14236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" cell $and $and$libresoc.v:202493$14239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc connect \Y $and$libresoc.v:202493$14239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" cell $eq $eq$libresoc.v:202489$14235 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 connect \Y $eq$libresoc.v:202489$14235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" cell $lt $lt$libresoc.v:202486$14232 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority connect \Y $lt$libresoc.v:202486$14232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" cell $lt $lt$libresoc.v:202487$14233 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 connect \Y $lt$libresoc.v:202487$14233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" cell $lt $lt$libresoc.v:202492$14238 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority connect \Y $lt$libresoc.v:202492$14238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" cell $ne $ne$libresoc.v:202485$14231 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 connect \Y $ne$libresoc.v:202485$14231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" cell $ne $ne$libresoc.v:202491$14237 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 connect \Y $ne$libresoc.v:202491$14237_Y end attribute \src "libresoc.v:202375.7-202375.20" process $proc$libresoc.v:202375$14286 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:202404.7-202404.24" process $proc$libresoc.v:202404$14287 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end attribute \src "libresoc.v:202408.13-202408.25" process $proc$libresoc.v:202408$14288 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end attribute \src "libresoc.v:202437.7-202437.17" process $proc$libresoc.v:202437$14289 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end attribute \src "libresoc.v:202445.13-202445.25" process $proc$libresoc.v:202445$14290 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end attribute \src "libresoc.v:202459.7-202459.20" process $proc$libresoc.v:202459$14291 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end attribute \src "libresoc.v:202467.14-202467.32" process $proc$libresoc.v:202467$14292 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end attribute \src "libresoc.v:202477.14-202477.31" process $proc$libresoc.v:202477$14293 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end attribute \src "libresoc.v:202494.3-202495.37" process $proc$libresoc.v:202494$14240 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end attribute \src "libresoc.v:202496.3-202497.25" process $proc$libresoc.v:202496$14241 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end attribute \src "libresoc.v:202498.3-202499.25" process $proc$libresoc.v:202498$14242 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end attribute \src "libresoc.v:202500.3-202501.25" process $proc$libresoc.v:202500$14243 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end attribute \src "libresoc.v:202502.3-202503.23" process $proc$libresoc.v:202502$14244 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end attribute \src "libresoc.v:202504.3-202505.37" process $proc$libresoc.v:202504$14245 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end attribute \src "libresoc.v:202506.3-202507.29" process $proc$libresoc.v:202506$14246 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end attribute \src "libresoc.v:202508.3-202523.6" process $proc$libresoc.v:202508$14247 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cppr$next[7:0]$14248 $1\cppr$next[7:0]$14254 assign $0\irq$next[0:0]$14249 $1\irq$next[0:0]$14255 assign $0\mfrr$next[7:0]$14250 $1\mfrr$next[7:0]$14256 assign $0\wb_ack$next[0:0]$14251 $1\wb_ack$next[0:0]$14257 assign $0\wb_rd_data$next[31:0]$14252 $1\wb_rd_data$next[31:0]$14258 assign $0\xisr$next[23:0]$14253 $1\xisr$next[23:0]$14259 attribute \src "libresoc.v:202509.5-202509.29" switch \initial attribute \src "libresoc.v:202509.9-202509.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\xisr$next[23:0]$14259 24'000000000000000000000000 assign $1\cppr$next[7:0]$14254 8'00000000 assign $1\mfrr$next[7:0]$14256 8'11111111 assign $1\irq$next[0:0]$14255 1'0 assign $1\wb_rd_data$next[31:0]$14258 0 assign $1\wb_ack$next[0:0]$14257 1'0 case assign $1\cppr$next[7:0]$14254 \cppr$2 assign $1\irq$next[0:0]$14255 \irq$4 assign $1\mfrr$next[7:0]$14256 \mfrr$3 assign $1\wb_ack$next[0:0]$14257 \wb_ack$6 assign $1\wb_rd_data$next[31:0]$14258 \wb_rd_data$5 assign $1\xisr$next[23:0]$14259 \xisr$1 end sync always update \cppr$next $0\cppr$next[7:0]$14248 update \irq$next $0\irq$next[0:0]$14249 update \mfrr$next $0\mfrr$next[7:0]$14250 update \wb_ack$next $0\wb_ack$next[0:0]$14251 update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14252 update \xisr$next $0\xisr$next[23:0]$14253 end attribute \src "libresoc.v:202524.3-202554.6" process $proc$libresoc.v:202524$14260 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] attribute \src "libresoc.v:202525.5-202525.29" switch \initial attribute \src "libresoc.v:202525.9-202525.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\xirr_accept_rd[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign $3\xirr_accept_rd[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\xirr_accept_rd[0:0] 1'1 case assign $4\xirr_accept_rd[0:0] 1'0 end case assign $3\xirr_accept_rd[0:0] 1'0 end end case assign $1\xirr_accept_rd[0:0] 1'0 end sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end attribute \src "libresoc.v:202555.3-202583.6" process $proc$libresoc.v:202555$14261 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] attribute \src "libresoc.v:202556.5-202556.29" switch \initial attribute \src "libresoc.v:202556.9-202556.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\be_out[31:0] $2\be_out[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\be_out[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $2\be_out[31:0] $3\be_out[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } assign $3\be_out[31:0] { \cppr \xisr } attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } assign $3\be_out[31:0] { \cppr \xisr } attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 assign $3\be_out[31:0] [31:24] \mfrr case assign $3\be_out[31:0] 0 end end case assign $1\be_out[31:0] 0 end sync always update \be_out $0\be_out[31:0] end attribute \src "libresoc.v:202584.3-202593.6" process $proc$libresoc.v:202584$14262 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] attribute \src "libresoc.v:202585.5-202585.29" switch \initial attribute \src "libresoc.v:202585.9-202585.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\pending_priority[7:0] \ics_i_pri case assign $1\pending_priority[7:0] 8'11111111 end sync always update \pending_priority $0\pending_priority[7:0] end attribute \src "libresoc.v:202594.3-202605.6" process $proc$libresoc.v:202594$14263 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] attribute \src "libresoc.v:202595.5-202595.29" switch \initial attribute \src "libresoc.v:202595.9-202595.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\min_pri[7:0] \mfrr attribute \src "libresoc.v:0.0-0.0" case assign { } { } assign $1\min_pri[7:0] \pending_priority end sync always update \min_pri $0\min_pri[7:0] end attribute \src "libresoc.v:202606.3-202614.6" process $proc$libresoc.v:202606$14264 assign { } { } assign { } { } assign $0\core_irq_o$next[0:0]$14265 $1\core_irq_o$next[0:0]$14266 attribute \src "libresoc.v:202607.5-202607.29" switch \initial attribute \src "libresoc.v:202607.9-202607.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\core_irq_o$next[0:0]$14266 1'0 case assign $1\core_irq_o$next[0:0]$14266 \irq end sync always update \core_irq_o$next $0\core_irq_o$next[0:0]$14265 end attribute \src "libresoc.v:202615.3-202624.6" process $proc$libresoc.v:202615$14267 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] attribute \src "libresoc.v:202616.5-202616.29" switch \initial attribute \src "libresoc.v:202616.9-202616.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" switch \icp_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\icp_wb__dat_r[31:0] \wb_rd_data case assign $1\icp_wb__dat_r[31:0] 0 end sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end attribute \src "libresoc.v:202625.3-202687.6" process $proc$libresoc.v:202625$14268 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\mfrr$11[7:0]$14271 $1\mfrr$11[7:0]$14276 assign $0\wb_ack$14[0:0]$14272 $1\wb_ack$14[0:0]$14277 assign { } { } assign { } { } assign { } { } assign $0\xisr$9[23:0]$14274 $2\xisr$9[23:0]$14283 assign $0\cppr$10[7:0]$14269 $4\cppr$10[7:0]$14284 assign $0\wb_rd_data$13[31:0]$14273 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } assign $0\irq$12[0:0]$14270 $1\irq$12[0:0]$14285 attribute \src "libresoc.v:202626.5-202626.29" switch \initial attribute \src "libresoc.v:202626.9-202626.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign $1\wb_ack$14[0:0]$14277 1'1 assign $1\cppr$10[7:0]$14275 $2\cppr$10[7:0]$14278 assign $1\mfrr$11[7:0]$14276 $2\mfrr$11[7:0]$14279 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign $2\cppr$10[7:0]$14278 $3\cppr$10[7:0]$14280 assign $2\mfrr$11[7:0]$14279 $3\mfrr$11[7:0]$14281 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } assign $3\mfrr$11[7:0]$14281 \mfrr assign $3\cppr$10[7:0]$14280 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } assign $3\mfrr$11[7:0]$14281 \mfrr assign $3\cppr$10[7:0]$14280 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 assign $3\cppr$10[7:0]$14280 \cppr assign { } { } assign $3\mfrr$11[7:0]$14281 \be_in [31:24] case assign $3\cppr$10[7:0]$14280 \cppr assign $3\mfrr$11[7:0]$14281 \mfrr end case assign $2\cppr$10[7:0]$14278 \cppr assign $2\mfrr$11[7:0]$14279 \mfrr end case assign $1\cppr$10[7:0]$14275 \cppr assign $1\mfrr$11[7:0]$14276 \mfrr assign $1\wb_ack$14[0:0]$14277 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\xisr$9[23:0]$14282 { 20'00000000000000000001 \ics_i_src } case assign $1\xisr$9[23:0]$14282 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\xisr$9[23:0]$14283 24'000000000000000000000010 case assign $2\xisr$9[23:0]$14283 $1\xisr$9[23:0]$14282 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\cppr$10[7:0]$14284 \min_pri case assign $4\cppr$10[7:0]$14284 $1\cppr$10[7:0]$14275 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } assign $1\irq$12[0:0]$14285 1'1 case assign $1\irq$12[0:0]$14285 1'0 end sync always update \cppr$10 $0\cppr$10[7:0]$14269 update \irq$12 $0\irq$12[0:0]$14270 update \mfrr$11 $0\mfrr$11[7:0]$14271 update \wb_ack$14 $0\wb_ack$14[0:0]$14272 update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14273 update \xisr$9 $0\xisr$9[23:0]$14274 end connect \$15 $and$libresoc.v:202484$14230_Y connect \$17 $ne$libresoc.v:202485$14231_Y connect \$19 $lt$libresoc.v:202486$14232_Y connect \$21 $lt$libresoc.v:202487$14233_Y connect \$23 $and$libresoc.v:202488$14234_Y connect \$25 $eq$libresoc.v:202489$14235_Y connect \$27 $and$libresoc.v:202490$14236_Y connect \$29 $ne$libresoc.v:202491$14237_Y connect \$31 $lt$libresoc.v:202492$14238_Y connect \$7 $and$libresoc.v:202493$14239_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end attribute \src "libresoc.v:202695.1-203744.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics attribute \src "libresoc.v:203625.3-203674.6" wire width 32 $0\be_out[31:0] attribute \src "libresoc.v:203336.3-203345.6" wire width 4 $0\cur_idx0[3:0] attribute \src "libresoc.v:203545.3-203554.6" wire width 4 $0\cur_idx10[3:0] attribute \src "libresoc.v:203565.3-203574.6" wire width 4 $0\cur_idx11[3:0] attribute \src "libresoc.v:203585.3-203594.6" wire width 4 $0\cur_idx12[3:0] attribute \src "libresoc.v:203605.3-203614.6" wire width 4 $0\cur_idx13[3:0] attribute \src "libresoc.v:203675.3-203684.6" wire width 4 $0\cur_idx14[3:0] attribute \src "libresoc.v:203695.3-203704.6" wire width 4 $0\cur_idx15[3:0] attribute \src "libresoc.v:203356.3-203365.6" wire width 4 $0\cur_idx1[3:0] attribute \src "libresoc.v:203376.3-203385.6" wire width 4 $0\cur_idx2[3:0] attribute \src "libresoc.v:203396.3-203405.6" wire width 4 $0\cur_idx3[3:0] attribute \src "libresoc.v:203425.3-203434.6" wire width 4 $0\cur_idx4[3:0] attribute \src "libresoc.v:203445.3-203454.6" wire width 4 $0\cur_idx5[3:0] attribute \src "libresoc.v:203465.3-203474.6" wire width 4 $0\cur_idx6[3:0] attribute \src "libresoc.v:203485.3-203494.6" wire width 4 $0\cur_idx7[3:0] attribute \src "libresoc.v:203505.3-203514.6" wire width 4 $0\cur_idx8[3:0] attribute \src "libresoc.v:203525.3-203534.6" wire width 4 $0\cur_idx9[3:0] attribute \src "libresoc.v:203326.3-203335.6" wire width 8 $0\cur_pri0[7:0] attribute \src "libresoc.v:203535.3-203544.6" wire width 8 $0\cur_pri10[7:0] attribute \src "libresoc.v:203555.3-203564.6" wire width 8 $0\cur_pri11[7:0] attribute \src "libresoc.v:203575.3-203584.6" wire width 8 $0\cur_pri12[7:0] attribute \src "libresoc.v:203595.3-203604.6" wire width 8 $0\cur_pri13[7:0] attribute \src "libresoc.v:203615.3-203624.6" wire width 8 $0\cur_pri14[7:0] attribute \src "libresoc.v:203685.3-203694.6" wire width 8 $0\cur_pri15[7:0] attribute \src "libresoc.v:203346.3-203355.6" wire width 8 $0\cur_pri1[7:0] attribute \src "libresoc.v:203366.3-203375.6" wire width 8 $0\cur_pri2[7:0] attribute \src "libresoc.v:203386.3-203395.6" wire width 8 $0\cur_pri3[7:0] attribute \src "libresoc.v:203406.3-203415.6" wire width 8 $0\cur_pri4[7:0] attribute \src "libresoc.v:203435.3-203444.6" wire width 8 $0\cur_pri5[7:0] attribute \src "libresoc.v:203455.3-203464.6" wire width 8 $0\cur_pri6[7:0] attribute \src "libresoc.v:203475.3-203484.6" wire width 8 $0\cur_pri7[7:0] attribute \src "libresoc.v:203495.3-203504.6" wire width 8 $0\cur_pri8[7:0] attribute \src "libresoc.v:203515.3-203524.6" wire width 8 $0\cur_pri9[7:0] attribute \src "libresoc.v:203705.3-203714.6" wire $0\ibit[0:0] attribute \src "libresoc.v:203200.3-203201.25" wire width 8 $0\icp_o_pri[7:0] attribute \src "libresoc.v:203198.3-203199.28" wire width 4 $0\icp_o_src[3:0] attribute \src "libresoc.v:203724.3-203732.6" wire $0\ics_wb__ack$next[0:0]$14540 attribute \src "libresoc.v:203234.3-203235.39" wire $0\ics_wb__ack[0:0] attribute \src "libresoc.v:203715.3-203723.6" wire width 32 $0\ics_wb__dat_r$next[31:0]$14537 attribute \src "libresoc.v:203236.3-203237.43" wire width 32 $0\ics_wb__dat_r[31:0] attribute \src "libresoc.v:202696.7-202696.20" wire $0\initial[0:0] attribute \src "libresoc.v:203416.3-203424.6" wire width 16 $0\int_level_l$next[15:0]$14509 attribute \src "libresoc.v:203238.3-203239.39" wire width 16 $0\int_level_l[15:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive0_pri$next[7:0]$14419 attribute \src "libresoc.v:203202.3-203203.35" wire width 8 $0\xive0_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive10_pri$next[7:0]$14420 attribute \src "libresoc.v:203222.3-203223.37" wire width 8 $0\xive10_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive11_pri$next[7:0]$14421 attribute \src "libresoc.v:203224.3-203225.37" wire width 8 $0\xive11_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive12_pri$next[7:0]$14422 attribute \src "libresoc.v:203226.3-203227.37" wire width 8 $0\xive12_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive13_pri$next[7:0]$14423 attribute \src "libresoc.v:203228.3-203229.37" wire width 8 $0\xive13_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive14_pri$next[7:0]$14424 attribute \src "libresoc.v:203230.3-203231.37" wire width 8 $0\xive14_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive15_pri$next[7:0]$14425 attribute \src "libresoc.v:203232.3-203233.37" wire width 8 $0\xive15_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive1_pri$next[7:0]$14426 attribute \src "libresoc.v:203204.3-203205.35" wire width 8 $0\xive1_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive2_pri$next[7:0]$14427 attribute \src "libresoc.v:203206.3-203207.35" wire width 8 $0\xive2_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive3_pri$next[7:0]$14428 attribute \src "libresoc.v:203208.3-203209.35" wire width 8 $0\xive3_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive4_pri$next[7:0]$14429 attribute \src "libresoc.v:203210.3-203211.35" wire width 8 $0\xive4_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive5_pri$next[7:0]$14430 attribute \src "libresoc.v:203212.3-203213.35" wire width 8 $0\xive5_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive6_pri$next[7:0]$14431 attribute \src "libresoc.v:203214.3-203215.35" wire width 8 $0\xive6_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive7_pri$next[7:0]$14432 attribute \src "libresoc.v:203216.3-203217.35" wire width 8 $0\xive7_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive8_pri$next[7:0]$14433 attribute \src "libresoc.v:203218.3-203219.35" wire width 8 $0\xive8_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $0\xive9_pri$next[7:0]$14434 attribute \src "libresoc.v:203220.3-203221.35" wire width 8 $0\xive9_pri[7:0] attribute \src "libresoc.v:203625.3-203674.6" wire width 32 $1\be_out[31:0] attribute \src "libresoc.v:203336.3-203345.6" wire width 4 $1\cur_idx0[3:0] attribute \src "libresoc.v:203545.3-203554.6" wire width 4 $1\cur_idx10[3:0] attribute \src "libresoc.v:203565.3-203574.6" wire width 4 $1\cur_idx11[3:0] attribute \src "libresoc.v:203585.3-203594.6" wire width 4 $1\cur_idx12[3:0] attribute \src "libresoc.v:203605.3-203614.6" wire width 4 $1\cur_idx13[3:0] attribute \src "libresoc.v:203675.3-203684.6" wire width 4 $1\cur_idx14[3:0] attribute \src "libresoc.v:203695.3-203704.6" wire width 4 $1\cur_idx15[3:0] attribute \src "libresoc.v:203356.3-203365.6" wire width 4 $1\cur_idx1[3:0] attribute \src "libresoc.v:203376.3-203385.6" wire width 4 $1\cur_idx2[3:0] attribute \src "libresoc.v:203396.3-203405.6" wire width 4 $1\cur_idx3[3:0] attribute \src "libresoc.v:203425.3-203434.6" wire width 4 $1\cur_idx4[3:0] attribute \src "libresoc.v:203445.3-203454.6" wire width 4 $1\cur_idx5[3:0] attribute \src "libresoc.v:203465.3-203474.6" wire width 4 $1\cur_idx6[3:0] attribute \src "libresoc.v:203485.3-203494.6" wire width 4 $1\cur_idx7[3:0] attribute \src "libresoc.v:203505.3-203514.6" wire width 4 $1\cur_idx8[3:0] attribute \src "libresoc.v:203525.3-203534.6" wire width 4 $1\cur_idx9[3:0] attribute \src "libresoc.v:203326.3-203335.6" wire width 8 $1\cur_pri0[7:0] attribute \src "libresoc.v:203535.3-203544.6" wire width 8 $1\cur_pri10[7:0] attribute \src "libresoc.v:203555.3-203564.6" wire width 8 $1\cur_pri11[7:0] attribute \src "libresoc.v:203575.3-203584.6" wire width 8 $1\cur_pri12[7:0] attribute \src "libresoc.v:203595.3-203604.6" wire width 8 $1\cur_pri13[7:0] attribute \src "libresoc.v:203615.3-203624.6" wire width 8 $1\cur_pri14[7:0] attribute \src "libresoc.v:203685.3-203694.6" wire width 8 $1\cur_pri15[7:0] attribute \src "libresoc.v:203346.3-203355.6" wire width 8 $1\cur_pri1[7:0] attribute \src "libresoc.v:203366.3-203375.6" wire width 8 $1\cur_pri2[7:0] attribute \src "libresoc.v:203386.3-203395.6" wire width 8 $1\cur_pri3[7:0] attribute \src "libresoc.v:203406.3-203415.6" wire width 8 $1\cur_pri4[7:0] attribute \src "libresoc.v:203435.3-203444.6" wire width 8 $1\cur_pri5[7:0] attribute \src "libresoc.v:203455.3-203464.6" wire width 8 $1\cur_pri6[7:0] attribute \src "libresoc.v:203475.3-203484.6" wire width 8 $1\cur_pri7[7:0] attribute \src "libresoc.v:203495.3-203504.6" wire width 8 $1\cur_pri8[7:0] attribute \src "libresoc.v:203515.3-203524.6" wire width 8 $1\cur_pri9[7:0] attribute \src "libresoc.v:203705.3-203714.6" wire $1\ibit[0:0] attribute \src "libresoc.v:202977.13-202977.30" wire width 8 $1\icp_o_pri[7:0] attribute \src "libresoc.v:202982.13-202982.29" wire width 4 $1\icp_o_src[3:0] attribute \src "libresoc.v:203724.3-203732.6" wire $1\ics_wb__ack$next[0:0]$14541 attribute \src "libresoc.v:202991.7-202991.25" wire $1\ics_wb__ack[0:0] attribute \src "libresoc.v:203715.3-203723.6" wire width 32 $1\ics_wb__dat_r$next[31:0]$14538 attribute \src "libresoc.v:203000.14-203000.35" wire width 32 $1\ics_wb__dat_r[31:0] attribute \src "libresoc.v:203416.3-203424.6" wire width 16 $1\int_level_l$next[15:0]$14510 attribute \src "libresoc.v:203012.14-203012.36" wire width 16 $1\int_level_l[15:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive0_pri$next[7:0]$14435 attribute \src "libresoc.v:203032.13-203032.30" wire width 8 $1\xive0_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive10_pri$next[7:0]$14436 attribute \src "libresoc.v:203036.13-203036.31" wire width 8 $1\xive10_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive11_pri$next[7:0]$14437 attribute \src "libresoc.v:203040.13-203040.31" wire width 8 $1\xive11_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive12_pri$next[7:0]$14438 attribute \src "libresoc.v:203044.13-203044.31" wire width 8 $1\xive12_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive13_pri$next[7:0]$14439 attribute \src "libresoc.v:203048.13-203048.31" wire width 8 $1\xive13_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive14_pri$next[7:0]$14440 attribute \src "libresoc.v:203052.13-203052.31" wire width 8 $1\xive14_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive15_pri$next[7:0]$14441 attribute \src "libresoc.v:203056.13-203056.31" wire width 8 $1\xive15_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive1_pri$next[7:0]$14442 attribute \src "libresoc.v:203060.13-203060.30" wire width 8 $1\xive1_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive2_pri$next[7:0]$14443 attribute \src "libresoc.v:203064.13-203064.30" wire width 8 $1\xive2_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive3_pri$next[7:0]$14444 attribute \src "libresoc.v:203068.13-203068.30" wire width 8 $1\xive3_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive4_pri$next[7:0]$14445 attribute \src "libresoc.v:203072.13-203072.30" wire width 8 $1\xive4_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive5_pri$next[7:0]$14446 attribute \src "libresoc.v:203076.13-203076.30" wire width 8 $1\xive5_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive6_pri$next[7:0]$14447 attribute \src "libresoc.v:203080.13-203080.30" wire width 8 $1\xive6_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive7_pri$next[7:0]$14448 attribute \src "libresoc.v:203084.13-203084.30" wire width 8 $1\xive7_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive8_pri$next[7:0]$14449 attribute \src "libresoc.v:203088.13-203088.30" wire width 8 $1\xive8_pri[7:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $1\xive9_pri$next[7:0]$14450 attribute \src "libresoc.v:203092.13-203092.30" wire width 8 $1\xive9_pri[7:0] attribute \src "libresoc.v:203625.3-203674.6" wire width 32 $2\be_out[31:0] attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive0_pri$next[7:0]$14451 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive10_pri$next[7:0]$14452 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive11_pri$next[7:0]$14453 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive12_pri$next[7:0]$14454 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive13_pri$next[7:0]$14455 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive14_pri$next[7:0]$14456 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive15_pri$next[7:0]$14457 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive1_pri$next[7:0]$14458 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive2_pri$next[7:0]$14459 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive3_pri$next[7:0]$14460 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive4_pri$next[7:0]$14461 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive5_pri$next[7:0]$14462 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive6_pri$next[7:0]$14463 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive7_pri$next[7:0]$14464 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive8_pri$next[7:0]$14465 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $2\xive9_pri$next[7:0]$14466 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive0_pri$next[7:0]$14467 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive10_pri$next[7:0]$14468 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive11_pri$next[7:0]$14469 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive12_pri$next[7:0]$14470 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive13_pri$next[7:0]$14471 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive14_pri$next[7:0]$14472 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive15_pri$next[7:0]$14473 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive1_pri$next[7:0]$14474 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive2_pri$next[7:0]$14475 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive3_pri$next[7:0]$14476 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive4_pri$next[7:0]$14477 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive5_pri$next[7:0]$14478 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive6_pri$next[7:0]$14479 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive7_pri$next[7:0]$14480 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive8_pri$next[7:0]$14481 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $3\xive9_pri$next[7:0]$14482 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive0_pri$next[7:0]$14483 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive10_pri$next[7:0]$14484 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive11_pri$next[7:0]$14485 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive12_pri$next[7:0]$14486 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive13_pri$next[7:0]$14487 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive14_pri$next[7:0]$14488 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive15_pri$next[7:0]$14489 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive1_pri$next[7:0]$14490 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive2_pri$next[7:0]$14491 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive3_pri$next[7:0]$14492 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive4_pri$next[7:0]$14493 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive5_pri$next[7:0]$14494 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive6_pri$next[7:0]$14495 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive7_pri$next[7:0]$14496 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive8_pri$next[7:0]$14497 attribute \src "libresoc.v:203240.3-203325.6" wire width 8 $4\xive9_pri$next[7:0]$14498 attribute \src "libresoc.v:203097.19-203097.113" wire $and$libresoc.v:203097$14296_Y attribute \src "libresoc.v:203099.19-203099.114" wire $and$libresoc.v:203099$14298_Y attribute \src "libresoc.v:203101.19-203101.114" wire $and$libresoc.v:203101$14300_Y attribute \src "libresoc.v:203103.19-203103.114" wire $and$libresoc.v:203103$14302_Y attribute \src "libresoc.v:203105.19-203105.114" wire $and$libresoc.v:203105$14304_Y attribute \src "libresoc.v:203107.19-203107.114" wire $and$libresoc.v:203107$14306_Y attribute \src "libresoc.v:203109.19-203109.114" wire $and$libresoc.v:203109$14308_Y attribute \src "libresoc.v:203112.19-203112.114" wire $and$libresoc.v:203112$14311_Y attribute \src "libresoc.v:203114.19-203114.114" wire $and$libresoc.v:203114$14313_Y attribute \src "libresoc.v:203116.19-203116.114" wire $and$libresoc.v:203116$14315_Y attribute \src "libresoc.v:203119.19-203119.114" wire $and$libresoc.v:203119$14318_Y attribute \src "libresoc.v:203121.19-203121.114" wire $and$libresoc.v:203121$14320_Y attribute \src "libresoc.v:203123.19-203123.114" wire $and$libresoc.v:203123$14322_Y attribute \src "libresoc.v:203125.19-203125.114" wire $and$libresoc.v:203125$14324_Y attribute \src "libresoc.v:203127.19-203127.115" wire $and$libresoc.v:203127$14326_Y attribute \src "libresoc.v:203129.19-203129.115" wire $and$libresoc.v:203129$14328_Y attribute \src "libresoc.v:203131.19-203131.115" wire $and$libresoc.v:203131$14330_Y attribute \src "libresoc.v:203134.19-203134.115" wire $and$libresoc.v:203134$14333_Y attribute \src "libresoc.v:203136.19-203136.115" wire $and$libresoc.v:203136$14335_Y attribute \src "libresoc.v:203138.19-203138.115" wire $and$libresoc.v:203138$14337_Y attribute \src "libresoc.v:203141.19-203141.115" wire $and$libresoc.v:203141$14340_Y attribute \src "libresoc.v:203143.19-203143.115" wire $and$libresoc.v:203143$14342_Y attribute \src "libresoc.v:203145.19-203145.115" wire $and$libresoc.v:203145$14344_Y attribute \src "libresoc.v:203147.19-203147.115" wire $and$libresoc.v:203147$14346_Y attribute \src "libresoc.v:203149.19-203149.115" wire $and$libresoc.v:203149$14348_Y attribute \src "libresoc.v:203152.19-203152.115" wire $and$libresoc.v:203152$14351_Y attribute \src "libresoc.v:203176.17-203176.115" wire $and$libresoc.v:203176$14375_Y attribute \src "libresoc.v:203184.18-203184.112" wire $and$libresoc.v:203184$14383_Y attribute \src "libresoc.v:203186.18-203186.112" wire $and$libresoc.v:203186$14385_Y attribute \src "libresoc.v:203188.18-203188.112" wire $and$libresoc.v:203188$14387_Y attribute \src "libresoc.v:203190.18-203190.112" wire $and$libresoc.v:203190$14389_Y attribute \src "libresoc.v:203193.18-203193.112" wire $and$libresoc.v:203193$14392_Y attribute \src "libresoc.v:203195.18-203195.112" wire $and$libresoc.v:203195$14394_Y attribute \src "libresoc.v:203197.18-203197.112" wire $and$libresoc.v:203197$14396_Y attribute \src "libresoc.v:203111.18-203111.109" wire $eq$libresoc.v:203111$14310_Y attribute \src "libresoc.v:203133.18-203133.109" wire $eq$libresoc.v:203133$14332_Y attribute \src "libresoc.v:203150.17-203150.114" wire $eq$libresoc.v:203150$14349_Y attribute \src "libresoc.v:203153.19-203153.110" wire $eq$libresoc.v:203153$14352_Y attribute \src "libresoc.v:203155.18-203155.109" wire $eq$libresoc.v:203155$14354_Y attribute \src "libresoc.v:203157.18-203157.109" wire $eq$libresoc.v:203157$14356_Y attribute \src "libresoc.v:203159.18-203159.109" wire $eq$libresoc.v:203159$14358_Y attribute \src "libresoc.v:203161.18-203161.109" wire $eq$libresoc.v:203161$14360_Y attribute \src "libresoc.v:203163.18-203163.109" wire $eq$libresoc.v:203163$14362_Y attribute \src "libresoc.v:203165.17-203165.114" wire $eq$libresoc.v:203165$14364_Y attribute \src "libresoc.v:203166.18-203166.109" wire $eq$libresoc.v:203166$14365_Y attribute \src "libresoc.v:203168.18-203168.109" wire $eq$libresoc.v:203168$14367_Y attribute \src "libresoc.v:203170.18-203170.110" wire $eq$libresoc.v:203170$14369_Y attribute \src "libresoc.v:203172.18-203172.110" wire $eq$libresoc.v:203172$14371_Y attribute \src "libresoc.v:203174.18-203174.110" wire $eq$libresoc.v:203174$14373_Y attribute \src "libresoc.v:203177.18-203177.110" wire $eq$libresoc.v:203177$14376_Y attribute \src "libresoc.v:203179.18-203179.110" wire $eq$libresoc.v:203179$14378_Y attribute \src "libresoc.v:203181.18-203181.110" wire $eq$libresoc.v:203181$14380_Y attribute \src "libresoc.v:203192.17-203192.108" wire $eq$libresoc.v:203192$14391_Y attribute \src "libresoc.v:203096.18-203096.111" wire $lt$libresoc.v:203096$14295_Y attribute \src "libresoc.v:203098.19-203098.112" wire $lt$libresoc.v:203098$14297_Y attribute \src "libresoc.v:203100.19-203100.112" wire $lt$libresoc.v:203100$14299_Y attribute \src "libresoc.v:203102.19-203102.112" wire $lt$libresoc.v:203102$14301_Y attribute \src "libresoc.v:203104.19-203104.112" wire $lt$libresoc.v:203104$14303_Y attribute \src "libresoc.v:203106.19-203106.112" wire $lt$libresoc.v:203106$14305_Y attribute \src "libresoc.v:203108.19-203108.112" wire $lt$libresoc.v:203108$14307_Y attribute \src "libresoc.v:203110.19-203110.112" wire $lt$libresoc.v:203110$14309_Y attribute \src "libresoc.v:203113.19-203113.112" wire $lt$libresoc.v:203113$14312_Y attribute \src "libresoc.v:203115.19-203115.112" wire $lt$libresoc.v:203115$14314_Y attribute \src "libresoc.v:203118.19-203118.112" wire $lt$libresoc.v:203118$14317_Y attribute \src "libresoc.v:203120.19-203120.112" wire $lt$libresoc.v:203120$14319_Y attribute \src "libresoc.v:203122.19-203122.112" wire $lt$libresoc.v:203122$14321_Y attribute \src "libresoc.v:203124.19-203124.112" wire $lt$libresoc.v:203124$14323_Y attribute \src "libresoc.v:203126.19-203126.113" wire $lt$libresoc.v:203126$14325_Y attribute \src "libresoc.v:203128.19-203128.113" wire $lt$libresoc.v:203128$14327_Y attribute \src "libresoc.v:203130.19-203130.114" wire $lt$libresoc.v:203130$14329_Y attribute \src "libresoc.v:203132.19-203132.114" wire $lt$libresoc.v:203132$14331_Y attribute \src "libresoc.v:203135.19-203135.114" wire $lt$libresoc.v:203135$14334_Y attribute \src "libresoc.v:203137.19-203137.114" wire $lt$libresoc.v:203137$14336_Y attribute \src "libresoc.v:203140.19-203140.114" wire $lt$libresoc.v:203140$14339_Y attribute \src "libresoc.v:203142.19-203142.114" wire $lt$libresoc.v:203142$14341_Y attribute \src "libresoc.v:203144.19-203144.114" wire $lt$libresoc.v:203144$14343_Y attribute \src "libresoc.v:203146.19-203146.114" wire $lt$libresoc.v:203146$14345_Y attribute \src "libresoc.v:203148.19-203148.114" wire $lt$libresoc.v:203148$14347_Y attribute \src "libresoc.v:203151.19-203151.114" wire $lt$libresoc.v:203151$14350_Y attribute \src "libresoc.v:203185.18-203185.110" wire $lt$libresoc.v:203185$14384_Y attribute \src "libresoc.v:203187.18-203187.110" wire $lt$libresoc.v:203187$14386_Y attribute \src "libresoc.v:203189.18-203189.111" wire $lt$libresoc.v:203189$14388_Y attribute \src "libresoc.v:203191.18-203191.111" wire $lt$libresoc.v:203191$14390_Y attribute \src "libresoc.v:203194.18-203194.111" wire $lt$libresoc.v:203194$14393_Y attribute \src "libresoc.v:203196.18-203196.111" wire $lt$libresoc.v:203196$14395_Y attribute \src "libresoc.v:203183.18-203183.40" wire width 16 $shr$libresoc.v:203183$14382_Y attribute \src "libresoc.v:203095.17-203095.114" wire width 8 $ternary$libresoc.v:203095$14294_Y attribute \src "libresoc.v:203117.18-203117.116" wire width 8 $ternary$libresoc.v:203117$14316_Y attribute \src "libresoc.v:203139.18-203139.116" wire width 8 $ternary$libresoc.v:203139$14338_Y attribute \src "libresoc.v:203154.19-203154.118" wire width 8 $ternary$libresoc.v:203154$14353_Y attribute \src "libresoc.v:203156.18-203156.116" wire width 8 $ternary$libresoc.v:203156$14355_Y attribute \src "libresoc.v:203158.18-203158.116" wire width 8 $ternary$libresoc.v:203158$14357_Y attribute \src "libresoc.v:203160.18-203160.116" wire width 8 $ternary$libresoc.v:203160$14359_Y attribute \src "libresoc.v:203162.18-203162.116" wire width 8 $ternary$libresoc.v:203162$14361_Y attribute \src "libresoc.v:203164.18-203164.116" wire width 8 $ternary$libresoc.v:203164$14363_Y attribute \src "libresoc.v:203167.18-203167.116" wire width 8 $ternary$libresoc.v:203167$14366_Y attribute \src "libresoc.v:203169.18-203169.116" wire width 8 $ternary$libresoc.v:203169$14368_Y attribute \src "libresoc.v:203171.18-203171.117" wire width 8 $ternary$libresoc.v:203171$14370_Y attribute \src "libresoc.v:203173.18-203173.117" wire width 8 $ternary$libresoc.v:203173$14372_Y attribute \src "libresoc.v:203175.18-203175.117" wire width 8 $ternary$libresoc.v:203175$14374_Y attribute \src "libresoc.v:203178.18-203178.117" wire width 8 $ternary$libresoc.v:203178$14377_Y attribute \src "libresoc.v:203180.18-203180.117" wire width 8 $ternary$libresoc.v:203180$14379_Y attribute \src "libresoc.v:203182.18-203182.117" wire width 8 $ternary$libresoc.v:203182$14381_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$159 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$189 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$191 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$199 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$201 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$203 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" wire \$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire width 8 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:315" wire \$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" wire \$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:337" wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" wire width 8 \cur_pri9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" wire \ibit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 output 2 \icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 \icp_o_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 output 1 \icp_o_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \icp_o_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 \icp_r_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \icp_r_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire output 9 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire \ics_wb__ack$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 28 input 4 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 6 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 32 output 8 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 32 \ics_wb__dat_r$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire width 32 input 10 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we attribute \src "libresoc.v:202696.7-202696.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" wire width 16 \int_level_l attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" wire width 16 \int_level_l$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358" wire width 4 \max_idx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359" wire width 8 \max_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:261" wire width 4 \reg_idx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:287" wire \reg_is_config attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:288" wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:824" wire input 3 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive0_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive0_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive10_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive10_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive11_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive11_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive12_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive12_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive13_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive13_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive14_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive14_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive15_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive15_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive1_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive1_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive2_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive2_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive3_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive3_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive4_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive4_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive5_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive5_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive6_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive6_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive7_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive7_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive8_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive8_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203097$14296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 connect \Y $and$libresoc.v:203097$14296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203099$14298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 connect \Y $and$libresoc.v:203099$14298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203101$14300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 connect \Y $and$libresoc.v:203101$14300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203103$14302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 connect \Y $and$libresoc.v:203103$14302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203105$14304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 connect \Y $and$libresoc.v:203105$14304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203107$14306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 connect \Y $and$libresoc.v:203107$14306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203109$14308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 connect \Y $and$libresoc.v:203109$14308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203112$14311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 connect \Y $and$libresoc.v:203112$14311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203114$14313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 connect \Y $and$libresoc.v:203114$14313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203116$14315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 connect \Y $and$libresoc.v:203116$14315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203119$14318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 connect \Y $and$libresoc.v:203119$14318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203121$14320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 connect \Y $and$libresoc.v:203121$14320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203123$14322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 connect \Y $and$libresoc.v:203123$14322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203125$14324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 connect \Y $and$libresoc.v:203125$14324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203127$14326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 connect \Y $and$libresoc.v:203127$14326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203129$14328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 connect \Y $and$libresoc.v:203129$14328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203131$14330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 connect \Y $and$libresoc.v:203131$14330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203134$14333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 connect \Y $and$libresoc.v:203134$14333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203136$14335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 connect \Y $and$libresoc.v:203136$14335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203138$14337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 connect \Y $and$libresoc.v:203138$14337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203141$14340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 connect \Y $and$libresoc.v:203141$14340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203143$14342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 connect \Y $and$libresoc.v:203143$14342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203145$14344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 connect \Y $and$libresoc.v:203145$14344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203147$14346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 connect \Y $and$libresoc.v:203147$14346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203149$14348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 connect \Y $and$libresoc.v:203149$14348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203152$14351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 connect \Y $and$libresoc.v:203152$14351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" cell $and $and$libresoc.v:203176$14375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb connect \Y $and$libresoc.v:203176$14375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" cell $and $and$libresoc.v:203184$14383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we connect \Y $and$libresoc.v:203184$14383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203186$14385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 connect \Y $and$libresoc.v:203186$14385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203188$14387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 connect \Y $and$libresoc.v:203188$14387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203190$14389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 connect \Y $and$libresoc.v:203190$14389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203193$14392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 connect \Y $and$libresoc.v:203193$14392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203195$14394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 connect \Y $and$libresoc.v:203195$14394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" cell $and $and$libresoc.v:203197$14396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 connect \Y $and$libresoc.v:203197$14396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203111$14310 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203111$14310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203133$14332 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203133$14332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" cell $eq $eq$libresoc.v:203150$14349 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 connect \Y $eq$libresoc.v:203150$14349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203153$14352 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 connect \Y $eq$libresoc.v:203153$14352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203155$14354 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203155$14354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203157$14356 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203157$14356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203159$14358 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203159$14358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203161$14360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203161$14360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203163$14362 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203163$14362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" cell $eq $eq$libresoc.v:203165$14364 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 connect \Y $eq$libresoc.v:203165$14364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203166$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203166$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203168$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203168$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203170$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203170$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203172$14371 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203172$14371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203174$14373 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203174$14373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203177$14376 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203177$14376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203179$14378 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203179$14378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203181$14380 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203181$14380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $eq $eq$libresoc.v:203192$14391 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 connect \Y $eq$libresoc.v:203192$14391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203096$14295 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 connect \Y $lt$libresoc.v:203096$14295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203098$14297 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 connect \Y $lt$libresoc.v:203098$14297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203100$14299 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 connect \Y $lt$libresoc.v:203100$14299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203102$14301 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 connect \Y $lt$libresoc.v:203102$14301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203104$14303 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 connect \Y $lt$libresoc.v:203104$14303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203106$14305 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 connect \Y $lt$libresoc.v:203106$14305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203108$14307 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 connect \Y $lt$libresoc.v:203108$14307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203110$14309 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 connect \Y $lt$libresoc.v:203110$14309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203113$14312 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 connect \Y $lt$libresoc.v:203113$14312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203115$14314 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 connect \Y $lt$libresoc.v:203115$14314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203118$14317 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 connect \Y $lt$libresoc.v:203118$14317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203120$14319 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 connect \Y $lt$libresoc.v:203120$14319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203122$14321 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 connect \Y $lt$libresoc.v:203122$14321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203124$14323 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 connect \Y $lt$libresoc.v:203124$14323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203126$14325 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 connect \Y $lt$libresoc.v:203126$14325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203128$14327 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 connect \Y $lt$libresoc.v:203128$14327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203130$14329 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 connect \Y $lt$libresoc.v:203130$14329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203132$14331 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 connect \Y $lt$libresoc.v:203132$14331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203135$14334 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 connect \Y $lt$libresoc.v:203135$14334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203137$14336 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 connect \Y $lt$libresoc.v:203137$14336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203140$14339 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 connect \Y $lt$libresoc.v:203140$14339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203142$14341 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 connect \Y $lt$libresoc.v:203142$14341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203144$14343 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 connect \Y $lt$libresoc.v:203144$14343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203146$14345 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 connect \Y $lt$libresoc.v:203146$14345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203148$14347 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 connect \Y $lt$libresoc.v:203148$14347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203151$14350 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 connect \Y $lt$libresoc.v:203151$14350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203185$14384 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri connect \Y $lt$libresoc.v:203185$14384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203187$14386 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri connect \Y $lt$libresoc.v:203187$14386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203189$14388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 connect \Y $lt$libresoc.v:203189$14388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203191$14390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 connect \Y $lt$libresoc.v:203191$14390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203194$14393 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 connect \Y $lt$libresoc.v:203194$14393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" cell $lt $lt$libresoc.v:203196$14395 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 connect \Y $lt$libresoc.v:203196$14395_Y end attribute \src "libresoc.v:203183.18-203183.40" cell $shr $shr$libresoc.v:203183$14382 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx connect \Y $shr$libresoc.v:203183$14382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203095$14294 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 connect \Y $ternary$libresoc.v:203095$14294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203117$14316 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 connect \Y $ternary$libresoc.v:203117$14316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203139$14338 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 connect \Y $ternary$libresoc.v:203139$14338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203154$14353 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 connect \Y $ternary$libresoc.v:203154$14353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203156$14355 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 connect \Y $ternary$libresoc.v:203156$14355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203158$14357 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 connect \Y $ternary$libresoc.v:203158$14357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203160$14359 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 connect \Y $ternary$libresoc.v:203160$14359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203162$14361 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 connect \Y $ternary$libresoc.v:203162$14361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203164$14363 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 connect \Y $ternary$libresoc.v:203164$14363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203167$14366 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 connect \Y $ternary$libresoc.v:203167$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203169$14368 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 connect \Y $ternary$libresoc.v:203169$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203171$14370 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 connect \Y $ternary$libresoc.v:203171$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203173$14372 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 connect \Y $ternary$libresoc.v:203173$14372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203175$14374 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 connect \Y $ternary$libresoc.v:203175$14374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203178$14377 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 connect \Y $ternary$libresoc.v:203178$14377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203180$14379 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 connect \Y $ternary$libresoc.v:203180$14379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" cell $mux $ternary$libresoc.v:203182$14381 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 connect \Y $ternary$libresoc.v:203182$14381_Y end attribute \src "libresoc.v:202696.7-202696.20" process $proc$libresoc.v:202696$14542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end attribute \src "libresoc.v:202977.13-202977.30" process $proc$libresoc.v:202977$14543 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end attribute \src "libresoc.v:202982.13-202982.29" process $proc$libresoc.v:202982$14544 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end attribute \src "libresoc.v:202991.7-202991.25" process $proc$libresoc.v:202991$14545 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end attribute \src "libresoc.v:203000.14-203000.35" process $proc$libresoc.v:203000$14546 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end attribute \src "libresoc.v:203012.14-203012.36" process $proc$libresoc.v:203012$14547 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end attribute \src "libresoc.v:203032.13-203032.30" process $proc$libresoc.v:203032$14548 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end attribute \src "libresoc.v:203036.13-203036.31" process $proc$libresoc.v:203036$14549 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end attribute \src "libresoc.v:203040.13-203040.31" process $proc$libresoc.v:203040$14550 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end attribute \src "libresoc.v:203044.13-203044.31" process $proc$libresoc.v:203044$14551 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end attribute \src "libresoc.v:203048.13-203048.31" process $proc$libresoc.v:203048$14552 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end attribute \src "libresoc.v:203052.13-203052.31" process $proc$libresoc.v:203052$14553 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end attribute \src "libresoc.v:203056.13-203056.31" process $proc$libresoc.v:203056$14554 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end attribute \src "libresoc.v:203060.13-203060.30" process $proc$libresoc.v:203060$14555 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end attribute \src "libresoc.v:203064.13-203064.30" process $proc$libresoc.v:203064$14556 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end attribute \src "libresoc.v:203068.13-203068.30" process $proc$libresoc.v:203068$14557 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end attribute \src "libresoc.v:203072.13-203072.30" process $proc$libresoc.v:203072$14558 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end attribute \src "libresoc.v:203076.13-203076.30" process $proc$libresoc.v:203076$14559 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end attribute \src "libresoc.v:203080.13-203080.30" process $proc$libresoc.v:203080$14560 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end attribute \src "libresoc.v:203084.13-203084.30" process $proc$libresoc.v:203084$14561 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end attribute \src "libresoc.v:203088.13-203088.30" process $proc$libresoc.v:203088$14562 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end attribute \src "libresoc.v:203092.13-203092.30" process $proc$libresoc.v:203092$14563 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end attribute \src "libresoc.v:203198.3-203199.28" process $proc$libresoc.v:203198$14397 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end attribute \src "libresoc.v:203200.3-203201.25" process $proc$libresoc.v:203200$14398 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end attribute \src "libresoc.v:203202.3-203203.35" process $proc$libresoc.v:203202$14399 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end attribute \src "libresoc.v:203204.3-203205.35" process $proc$libresoc.v:203204$14400 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end attribute \src "libresoc.v:203206.3-203207.35" process $proc$libresoc.v:203206$14401 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end attribute \src "libresoc.v:203208.3-203209.35" process $proc$libresoc.v:203208$14402 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end attribute \src "libresoc.v:203210.3-203211.35" process $proc$libresoc.v:203210$14403 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end attribute \src "libresoc.v:203212.3-203213.35" process $proc$libresoc.v:203212$14404 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end attribute \src "libresoc.v:203214.3-203215.35" process $proc$libresoc.v:203214$14405 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end attribute \src "libresoc.v:203216.3-203217.35" process $proc$libresoc.v:203216$14406 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end attribute \src "libresoc.v:203218.3-203219.35" process $proc$libresoc.v:203218$14407 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end attribute \src "libresoc.v:203220.3-203221.35" process $proc$libresoc.v:203220$14408 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end attribute \src "libresoc.v:203222.3-203223.37" process $proc$libresoc.v:203222$14409 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end attribute \src "libresoc.v:203224.3-203225.37" process $proc$libresoc.v:203224$14410 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end attribute \src "libresoc.v:203226.3-203227.37" process $proc$libresoc.v:203226$14411 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end attribute \src "libresoc.v:203228.3-203229.37" process $proc$libresoc.v:203228$14412 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end attribute \src "libresoc.v:203230.3-203231.37" process $proc$libresoc.v:203230$14413 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end attribute \src "libresoc.v:203232.3-203233.37" process $proc$libresoc.v:203232$14414 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end attribute \src "libresoc.v:203234.3-203235.39" process $proc$libresoc.v:203234$14415 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end attribute \src "libresoc.v:203236.3-203237.43" process $proc$libresoc.v:203236$14416 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end attribute \src "libresoc.v:203238.3-203239.39" process $proc$libresoc.v:203238$14417 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end attribute \src "libresoc.v:203240.3-203325.6" process $proc$libresoc.v:203240$14418 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\xive0_pri$next[7:0]$14419 $4\xive0_pri$next[7:0]$14483 assign $0\xive10_pri$next[7:0]$14420 $4\xive10_pri$next[7:0]$14484 assign $0\xive11_pri$next[7:0]$14421 $4\xive11_pri$next[7:0]$14485 assign $0\xive12_pri$next[7:0]$14422 $4\xive12_pri$next[7:0]$14486 assign $0\xive13_pri$next[7:0]$14423 $4\xive13_pri$next[7:0]$14487 assign $0\xive14_pri$next[7:0]$14424 $4\xive14_pri$next[7:0]$14488 assign $0\xive15_pri$next[7:0]$14425 $4\xive15_pri$next[7:0]$14489 assign $0\xive1_pri$next[7:0]$14426 $4\xive1_pri$next[7:0]$14490 assign $0\xive2_pri$next[7:0]$14427 $4\xive2_pri$next[7:0]$14491 assign $0\xive3_pri$next[7:0]$14428 $4\xive3_pri$next[7:0]$14492 assign $0\xive4_pri$next[7:0]$14429 $4\xive4_pri$next[7:0]$14493 assign $0\xive5_pri$next[7:0]$14430 $4\xive5_pri$next[7:0]$14494 assign $0\xive6_pri$next[7:0]$14431 $4\xive6_pri$next[7:0]$14495 assign $0\xive7_pri$next[7:0]$14432 $4\xive7_pri$next[7:0]$14496 assign $0\xive8_pri$next[7:0]$14433 $4\xive8_pri$next[7:0]$14497 assign $0\xive9_pri$next[7:0]$14434 $4\xive9_pri$next[7:0]$14498 attribute \src "libresoc.v:203241.5-203241.29" switch \initial attribute \src "libresoc.v:203241.9-203241.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $1\xive0_pri$next[7:0]$14435 $2\xive0_pri$next[7:0]$14451 assign $1\xive10_pri$next[7:0]$14436 $2\xive10_pri$next[7:0]$14452 assign $1\xive11_pri$next[7:0]$14437 $2\xive11_pri$next[7:0]$14453 assign $1\xive12_pri$next[7:0]$14438 $2\xive12_pri$next[7:0]$14454 assign $1\xive13_pri$next[7:0]$14439 $2\xive13_pri$next[7:0]$14455 assign $1\xive14_pri$next[7:0]$14440 $2\xive14_pri$next[7:0]$14456 assign $1\xive15_pri$next[7:0]$14441 $2\xive15_pri$next[7:0]$14457 assign $1\xive1_pri$next[7:0]$14442 $2\xive1_pri$next[7:0]$14458 assign $1\xive2_pri$next[7:0]$14443 $2\xive2_pri$next[7:0]$14459 assign $1\xive3_pri$next[7:0]$14444 $2\xive3_pri$next[7:0]$14460 assign $1\xive4_pri$next[7:0]$14445 $2\xive4_pri$next[7:0]$14461 assign $1\xive5_pri$next[7:0]$14446 $2\xive5_pri$next[7:0]$14462 assign $1\xive6_pri$next[7:0]$14447 $2\xive6_pri$next[7:0]$14463 assign $1\xive7_pri$next[7:0]$14448 $2\xive7_pri$next[7:0]$14464 assign $1\xive8_pri$next[7:0]$14449 $2\xive8_pri$next[7:0]$14465 assign $1\xive9_pri$next[7:0]$14450 $2\xive9_pri$next[7:0]$14466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $2\xive0_pri$next[7:0]$14451 $3\xive0_pri$next[7:0]$14467 assign $2\xive10_pri$next[7:0]$14452 $3\xive10_pri$next[7:0]$14468 assign $2\xive11_pri$next[7:0]$14453 $3\xive11_pri$next[7:0]$14469 assign $2\xive12_pri$next[7:0]$14454 $3\xive12_pri$next[7:0]$14470 assign $2\xive13_pri$next[7:0]$14455 $3\xive13_pri$next[7:0]$14471 assign $2\xive14_pri$next[7:0]$14456 $3\xive14_pri$next[7:0]$14472 assign $2\xive15_pri$next[7:0]$14457 $3\xive15_pri$next[7:0]$14473 assign $2\xive1_pri$next[7:0]$14458 $3\xive1_pri$next[7:0]$14474 assign $2\xive2_pri$next[7:0]$14459 $3\xive2_pri$next[7:0]$14475 assign $2\xive3_pri$next[7:0]$14460 $3\xive3_pri$next[7:0]$14476 assign $2\xive4_pri$next[7:0]$14461 $3\xive4_pri$next[7:0]$14477 assign $2\xive5_pri$next[7:0]$14462 $3\xive5_pri$next[7:0]$14478 assign $2\xive6_pri$next[7:0]$14463 $3\xive6_pri$next[7:0]$14479 assign $2\xive7_pri$next[7:0]$14464 $3\xive7_pri$next[7:0]$14480 assign $2\xive8_pri$next[7:0]$14465 $3\xive8_pri$next[7:0]$14481 assign $2\xive9_pri$next[7:0]$14466 $3\xive9_pri$next[7:0]$14482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive0_pri$next[7:0]$14467 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign { } { } assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive1_pri$next[7:0]$14474 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign { } { } assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive2_pri$next[7:0]$14475 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign { } { } assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive3_pri$next[7:0]$14476 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign { } { } assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive4_pri$next[7:0]$14477 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign { } { } assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive5_pri$next[7:0]$14478 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign { } { } assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive6_pri$next[7:0]$14479 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign { } { } assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive7_pri$next[7:0]$14480 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign { } { } assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive8_pri$next[7:0]$14481 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign { } { } assign $3\xive9_pri$next[7:0]$14482 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign { } { } assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive10_pri$next[7:0]$14468 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign { } { } assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive11_pri$next[7:0]$14469 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign { } { } assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive12_pri$next[7:0]$14470 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign { } { } assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive13_pri$next[7:0]$14471 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign { } { } assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive14_pri$next[7:0]$14472 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign { } { } assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri assign $3\xive15_pri$next[7:0]$14473 \be_in [7:0] case assign $3\xive0_pri$next[7:0]$14467 \xive0_pri assign $3\xive10_pri$next[7:0]$14468 \xive10_pri assign $3\xive11_pri$next[7:0]$14469 \xive11_pri assign $3\xive12_pri$next[7:0]$14470 \xive12_pri assign $3\xive13_pri$next[7:0]$14471 \xive13_pri assign $3\xive14_pri$next[7:0]$14472 \xive14_pri assign $3\xive15_pri$next[7:0]$14473 \xive15_pri assign $3\xive1_pri$next[7:0]$14474 \xive1_pri assign $3\xive2_pri$next[7:0]$14475 \xive2_pri assign $3\xive3_pri$next[7:0]$14476 \xive3_pri assign $3\xive4_pri$next[7:0]$14477 \xive4_pri assign $3\xive5_pri$next[7:0]$14478 \xive5_pri assign $3\xive6_pri$next[7:0]$14479 \xive6_pri assign $3\xive7_pri$next[7:0]$14480 \xive7_pri assign $3\xive8_pri$next[7:0]$14481 \xive8_pri assign $3\xive9_pri$next[7:0]$14482 \xive9_pri end case assign $2\xive0_pri$next[7:0]$14451 \xive0_pri assign $2\xive10_pri$next[7:0]$14452 \xive10_pri assign $2\xive11_pri$next[7:0]$14453 \xive11_pri assign $2\xive12_pri$next[7:0]$14454 \xive12_pri assign $2\xive13_pri$next[7:0]$14455 \xive13_pri assign $2\xive14_pri$next[7:0]$14456 \xive14_pri assign $2\xive15_pri$next[7:0]$14457 \xive15_pri assign $2\xive1_pri$next[7:0]$14458 \xive1_pri assign $2\xive2_pri$next[7:0]$14459 \xive2_pri assign $2\xive3_pri$next[7:0]$14460 \xive3_pri assign $2\xive4_pri$next[7:0]$14461 \xive4_pri assign $2\xive5_pri$next[7:0]$14462 \xive5_pri assign $2\xive6_pri$next[7:0]$14463 \xive6_pri assign $2\xive7_pri$next[7:0]$14464 \xive7_pri assign $2\xive8_pri$next[7:0]$14465 \xive8_pri assign $2\xive9_pri$next[7:0]$14466 \xive9_pri end case assign $1\xive0_pri$next[7:0]$14435 \xive0_pri assign $1\xive10_pri$next[7:0]$14436 \xive10_pri assign $1\xive11_pri$next[7:0]$14437 \xive11_pri assign $1\xive12_pri$next[7:0]$14438 \xive12_pri assign $1\xive13_pri$next[7:0]$14439 \xive13_pri assign $1\xive14_pri$next[7:0]$14440 \xive14_pri assign $1\xive15_pri$next[7:0]$14441 \xive15_pri assign $1\xive1_pri$next[7:0]$14442 \xive1_pri assign $1\xive2_pri$next[7:0]$14443 \xive2_pri assign $1\xive3_pri$next[7:0]$14444 \xive3_pri assign $1\xive4_pri$next[7:0]$14445 \xive4_pri assign $1\xive5_pri$next[7:0]$14446 \xive5_pri assign $1\xive6_pri$next[7:0]$14447 \xive6_pri assign $1\xive7_pri$next[7:0]$14448 \xive7_pri assign $1\xive8_pri$next[7:0]$14449 \xive8_pri assign $1\xive9_pri$next[7:0]$14450 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $4\xive0_pri$next[7:0]$14483 8'11111111 assign $4\xive1_pri$next[7:0]$14490 8'11111111 assign $4\xive2_pri$next[7:0]$14491 8'11111111 assign $4\xive3_pri$next[7:0]$14492 8'11111111 assign $4\xive4_pri$next[7:0]$14493 8'11111111 assign $4\xive5_pri$next[7:0]$14494 8'11111111 assign $4\xive6_pri$next[7:0]$14495 8'11111111 assign $4\xive7_pri$next[7:0]$14496 8'11111111 assign $4\xive8_pri$next[7:0]$14497 8'11111111 assign $4\xive9_pri$next[7:0]$14498 8'11111111 assign $4\xive10_pri$next[7:0]$14484 8'11111111 assign $4\xive11_pri$next[7:0]$14485 8'11111111 assign $4\xive12_pri$next[7:0]$14486 8'11111111 assign $4\xive13_pri$next[7:0]$14487 8'11111111 assign $4\xive14_pri$next[7:0]$14488 8'11111111 assign $4\xive15_pri$next[7:0]$14489 8'11111111 case assign $4\xive0_pri$next[7:0]$14483 $1\xive0_pri$next[7:0]$14435 assign $4\xive10_pri$next[7:0]$14484 $1\xive10_pri$next[7:0]$14436 assign $4\xive11_pri$next[7:0]$14485 $1\xive11_pri$next[7:0]$14437 assign $4\xive12_pri$next[7:0]$14486 $1\xive12_pri$next[7:0]$14438 assign $4\xive13_pri$next[7:0]$14487 $1\xive13_pri$next[7:0]$14439 assign $4\xive14_pri$next[7:0]$14488 $1\xive14_pri$next[7:0]$14440 assign $4\xive15_pri$next[7:0]$14489 $1\xive15_pri$next[7:0]$14441 assign $4\xive1_pri$next[7:0]$14490 $1\xive1_pri$next[7:0]$14442 assign $4\xive2_pri$next[7:0]$14491 $1\xive2_pri$next[7:0]$14443 assign $4\xive3_pri$next[7:0]$14492 $1\xive3_pri$next[7:0]$14444 assign $4\xive4_pri$next[7:0]$14493 $1\xive4_pri$next[7:0]$14445 assign $4\xive5_pri$next[7:0]$14494 $1\xive5_pri$next[7:0]$14446 assign $4\xive6_pri$next[7:0]$14495 $1\xive6_pri$next[7:0]$14447 assign $4\xive7_pri$next[7:0]$14496 $1\xive7_pri$next[7:0]$14448 assign $4\xive8_pri$next[7:0]$14497 $1\xive8_pri$next[7:0]$14449 assign $4\xive9_pri$next[7:0]$14498 $1\xive9_pri$next[7:0]$14450 end sync always update \xive0_pri$next $0\xive0_pri$next[7:0]$14419 update \xive10_pri$next $0\xive10_pri$next[7:0]$14420 update \xive11_pri$next $0\xive11_pri$next[7:0]$14421 update \xive12_pri$next $0\xive12_pri$next[7:0]$14422 update \xive13_pri$next $0\xive13_pri$next[7:0]$14423 update \xive14_pri$next $0\xive14_pri$next[7:0]$14424 update \xive15_pri$next $0\xive15_pri$next[7:0]$14425 update \xive1_pri$next $0\xive1_pri$next[7:0]$14426 update \xive2_pri$next $0\xive2_pri$next[7:0]$14427 update \xive3_pri$next $0\xive3_pri$next[7:0]$14428 update \xive4_pri$next $0\xive4_pri$next[7:0]$14429 update \xive5_pri$next $0\xive5_pri$next[7:0]$14430 update \xive6_pri$next $0\xive6_pri$next[7:0]$14431 update \xive7_pri$next $0\xive7_pri$next[7:0]$14432 update \xive8_pri$next $0\xive8_pri$next[7:0]$14433 update \xive9_pri$next $0\xive9_pri$next[7:0]$14434 end attribute \src "libresoc.v:203326.3-203335.6" process $proc$libresoc.v:203326$14499 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] attribute \src "libresoc.v:203327.5-203327.29" switch \initial attribute \src "libresoc.v:203327.9-203327.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri0[7:0] \xive0_pri case assign $1\cur_pri0[7:0] \max_pri end sync always update \cur_pri0 $0\cur_pri0[7:0] end attribute \src "libresoc.v:203336.3-203345.6" process $proc$libresoc.v:203336$14500 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] attribute \src "libresoc.v:203337.5-203337.29" switch \initial attribute \src "libresoc.v:203337.9-203337.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx0[3:0] 4'0000 case assign $1\cur_idx0[3:0] \max_idx end sync always update \cur_idx0 $0\cur_idx0[3:0] end attribute \src "libresoc.v:203346.3-203355.6" process $proc$libresoc.v:203346$14501 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] attribute \src "libresoc.v:203347.5-203347.29" switch \initial attribute \src "libresoc.v:203347.9-203347.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri1[7:0] \xive1_pri case assign $1\cur_pri1[7:0] \cur_pri0 end sync always update \cur_pri1 $0\cur_pri1[7:0] end attribute \src "libresoc.v:203356.3-203365.6" process $proc$libresoc.v:203356$14502 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] attribute \src "libresoc.v:203357.5-203357.29" switch \initial attribute \src "libresoc.v:203357.9-203357.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$89 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx1[3:0] 4'0001 case assign $1\cur_idx1[3:0] \cur_idx0 end sync always update \cur_idx1 $0\cur_idx1[3:0] end attribute \src "libresoc.v:203366.3-203375.6" process $proc$libresoc.v:203366$14503 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] attribute \src "libresoc.v:203367.5-203367.29" switch \initial attribute \src "libresoc.v:203367.9-203367.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri2[7:0] \xive2_pri case assign $1\cur_pri2[7:0] \cur_pri1 end sync always update \cur_pri2 $0\cur_pri2[7:0] end attribute \src "libresoc.v:203376.3-203385.6" process $proc$libresoc.v:203376$14504 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] attribute \src "libresoc.v:203377.5-203377.29" switch \initial attribute \src "libresoc.v:203377.9-203377.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$97 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx2[3:0] 4'0010 case assign $1\cur_idx2[3:0] \cur_idx1 end sync always update \cur_idx2 $0\cur_idx2[3:0] end attribute \src "libresoc.v:203386.3-203395.6" process $proc$libresoc.v:203386$14505 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] attribute \src "libresoc.v:203387.5-203387.29" switch \initial attribute \src "libresoc.v:203387.9-203387.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri3[7:0] \xive3_pri case assign $1\cur_pri3[7:0] \cur_pri2 end sync always update \cur_pri3 $0\cur_pri3[7:0] end attribute \src "libresoc.v:203396.3-203405.6" process $proc$libresoc.v:203396$14506 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] attribute \src "libresoc.v:203397.5-203397.29" switch \initial attribute \src "libresoc.v:203397.9-203397.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx3[3:0] 4'0011 case assign $1\cur_idx3[3:0] \cur_idx2 end sync always update \cur_idx3 $0\cur_idx3[3:0] end attribute \src "libresoc.v:203406.3-203415.6" process $proc$libresoc.v:203406$14507 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] attribute \src "libresoc.v:203407.5-203407.29" switch \initial attribute \src "libresoc.v:203407.9-203407.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri4[7:0] \xive4_pri case assign $1\cur_pri4[7:0] \cur_pri3 end sync always update \cur_pri4 $0\cur_pri4[7:0] end attribute \src "libresoc.v:203416.3-203424.6" process $proc$libresoc.v:203416$14508 assign { } { } assign { } { } assign $0\int_level_l$next[15:0]$14509 $1\int_level_l$next[15:0]$14510 attribute \src "libresoc.v:203417.5-203417.29" switch \initial attribute \src "libresoc.v:203417.9-203417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\int_level_l$next[15:0]$14510 16'0000000000000000 case assign $1\int_level_l$next[15:0]$14510 \int_level_i end sync always update \int_level_l$next $0\int_level_l$next[15:0]$14509 end attribute \src "libresoc.v:203425.3-203434.6" process $proc$libresoc.v:203425$14511 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] attribute \src "libresoc.v:203426.5-203426.29" switch \initial attribute \src "libresoc.v:203426.9-203426.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx4[3:0] 4'0100 case assign $1\cur_idx4[3:0] \cur_idx3 end sync always update \cur_idx4 $0\cur_idx4[3:0] end attribute \src "libresoc.v:203435.3-203444.6" process $proc$libresoc.v:203435$14512 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] attribute \src "libresoc.v:203436.5-203436.29" switch \initial attribute \src "libresoc.v:203436.9-203436.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri5[7:0] \xive5_pri case assign $1\cur_pri5[7:0] \cur_pri4 end sync always update \cur_pri5 $0\cur_pri5[7:0] end attribute \src "libresoc.v:203445.3-203454.6" process $proc$libresoc.v:203445$14513 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] attribute \src "libresoc.v:203446.5-203446.29" switch \initial attribute \src "libresoc.v:203446.9-203446.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx5[3:0] 4'0101 case assign $1\cur_idx5[3:0] \cur_idx4 end sync always update \cur_idx5 $0\cur_idx5[3:0] end attribute \src "libresoc.v:203455.3-203464.6" process $proc$libresoc.v:203455$14514 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] attribute \src "libresoc.v:203456.5-203456.29" switch \initial attribute \src "libresoc.v:203456.9-203456.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$125 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri6[7:0] \xive6_pri case assign $1\cur_pri6[7:0] \cur_pri5 end sync always update \cur_pri6 $0\cur_pri6[7:0] end attribute \src "libresoc.v:203465.3-203474.6" process $proc$libresoc.v:203465$14515 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] attribute \src "libresoc.v:203466.5-203466.29" switch \initial attribute \src "libresoc.v:203466.9-203466.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx6[3:0] 4'0110 case assign $1\cur_idx6[3:0] \cur_idx5 end sync always update \cur_idx6 $0\cur_idx6[3:0] end attribute \src "libresoc.v:203475.3-203484.6" process $proc$libresoc.v:203475$14516 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] attribute \src "libresoc.v:203476.5-203476.29" switch \initial attribute \src "libresoc.v:203476.9-203476.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri7[7:0] \xive7_pri case assign $1\cur_pri7[7:0] \cur_pri6 end sync always update \cur_pri7 $0\cur_pri7[7:0] end attribute \src "libresoc.v:203485.3-203494.6" process $proc$libresoc.v:203485$14517 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] attribute \src "libresoc.v:203486.5-203486.29" switch \initial attribute \src "libresoc.v:203486.9-203486.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx7[3:0] 4'0111 case assign $1\cur_idx7[3:0] \cur_idx6 end sync always update \cur_idx7 $0\cur_idx7[3:0] end attribute \src "libresoc.v:203495.3-203504.6" process $proc$libresoc.v:203495$14518 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] attribute \src "libresoc.v:203496.5-203496.29" switch \initial attribute \src "libresoc.v:203496.9-203496.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$141 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri8[7:0] \xive8_pri case assign $1\cur_pri8[7:0] \cur_pri7 end sync always update \cur_pri8 $0\cur_pri8[7:0] end attribute \src "libresoc.v:203505.3-203514.6" process $proc$libresoc.v:203505$14519 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] attribute \src "libresoc.v:203506.5-203506.29" switch \initial attribute \src "libresoc.v:203506.9-203506.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$145 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx8[3:0] 4'1000 case assign $1\cur_idx8[3:0] \cur_idx7 end sync always update \cur_idx8 $0\cur_idx8[3:0] end attribute \src "libresoc.v:203515.3-203524.6" process $proc$libresoc.v:203515$14520 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] attribute \src "libresoc.v:203516.5-203516.29" switch \initial attribute \src "libresoc.v:203516.9-203516.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$149 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri9[7:0] \xive9_pri case assign $1\cur_pri9[7:0] \cur_pri8 end sync always update \cur_pri9 $0\cur_pri9[7:0] end attribute \src "libresoc.v:203525.3-203534.6" process $proc$libresoc.v:203525$14521 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] attribute \src "libresoc.v:203526.5-203526.29" switch \initial attribute \src "libresoc.v:203526.9-203526.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$153 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx9[3:0] 4'1001 case assign $1\cur_idx9[3:0] \cur_idx8 end sync always update \cur_idx9 $0\cur_idx9[3:0] end attribute \src "libresoc.v:203535.3-203544.6" process $proc$libresoc.v:203535$14522 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] attribute \src "libresoc.v:203536.5-203536.29" switch \initial attribute \src "libresoc.v:203536.9-203536.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$157 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri10[7:0] \xive10_pri case assign $1\cur_pri10[7:0] \cur_pri9 end sync always update \cur_pri10 $0\cur_pri10[7:0] end attribute \src "libresoc.v:203545.3-203554.6" process $proc$libresoc.v:203545$14523 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] attribute \src "libresoc.v:203546.5-203546.29" switch \initial attribute \src "libresoc.v:203546.9-203546.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$161 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx10[3:0] 4'1010 case assign $1\cur_idx10[3:0] \cur_idx9 end sync always update \cur_idx10 $0\cur_idx10[3:0] end attribute \src "libresoc.v:203555.3-203564.6" process $proc$libresoc.v:203555$14524 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] attribute \src "libresoc.v:203556.5-203556.29" switch \initial attribute \src "libresoc.v:203556.9-203556.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$165 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri11[7:0] \xive11_pri case assign $1\cur_pri11[7:0] \cur_pri10 end sync always update \cur_pri11 $0\cur_pri11[7:0] end attribute \src "libresoc.v:203565.3-203574.6" process $proc$libresoc.v:203565$14525 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] attribute \src "libresoc.v:203566.5-203566.29" switch \initial attribute \src "libresoc.v:203566.9-203566.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$169 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx11[3:0] 4'1011 case assign $1\cur_idx11[3:0] \cur_idx10 end sync always update \cur_idx11 $0\cur_idx11[3:0] end attribute \src "libresoc.v:203575.3-203584.6" process $proc$libresoc.v:203575$14526 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] attribute \src "libresoc.v:203576.5-203576.29" switch \initial attribute \src "libresoc.v:203576.9-203576.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$173 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri12[7:0] \xive12_pri case assign $1\cur_pri12[7:0] \cur_pri11 end sync always update \cur_pri12 $0\cur_pri12[7:0] end attribute \src "libresoc.v:203585.3-203594.6" process $proc$libresoc.v:203585$14527 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] attribute \src "libresoc.v:203586.5-203586.29" switch \initial attribute \src "libresoc.v:203586.9-203586.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$177 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx12[3:0] 4'1100 case assign $1\cur_idx12[3:0] \cur_idx11 end sync always update \cur_idx12 $0\cur_idx12[3:0] end attribute \src "libresoc.v:203595.3-203604.6" process $proc$libresoc.v:203595$14528 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] attribute \src "libresoc.v:203596.5-203596.29" switch \initial attribute \src "libresoc.v:203596.9-203596.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$181 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri13[7:0] \xive13_pri case assign $1\cur_pri13[7:0] \cur_pri12 end sync always update \cur_pri13 $0\cur_pri13[7:0] end attribute \src "libresoc.v:203605.3-203614.6" process $proc$libresoc.v:203605$14529 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] attribute \src "libresoc.v:203606.5-203606.29" switch \initial attribute \src "libresoc.v:203606.9-203606.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$185 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx13[3:0] 4'1101 case assign $1\cur_idx13[3:0] \cur_idx12 end sync always update \cur_idx13 $0\cur_idx13[3:0] end attribute \src "libresoc.v:203615.3-203624.6" process $proc$libresoc.v:203615$14530 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] attribute \src "libresoc.v:203616.5-203616.29" switch \initial attribute \src "libresoc.v:203616.9-203616.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$189 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri14[7:0] \xive14_pri case assign $1\cur_pri14[7:0] \cur_pri13 end sync always update \cur_pri14 $0\cur_pri14[7:0] end attribute \src "libresoc.v:203625.3-203674.6" process $proc$libresoc.v:203625$14531 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] attribute \src "libresoc.v:203626.5-203626.29" switch \initial attribute \src "libresoc.v:203626.9-203626.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" switch { \reg_is_debug \reg_is_config \reg_is_xive } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\be_out[31:0] $2\be_out[31:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } attribute \src "libresoc.v:0.0-0.0" case 4'1010 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } attribute \src "libresoc.v:0.0-0.0" case 4'1011 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } attribute \src "libresoc.v:0.0-0.0" case 4'1100 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } attribute \src "libresoc.v:0.0-0.0" case 4'1101 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } attribute \src "libresoc.v:0.0-0.0" case 4'1110 assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } attribute \src "libresoc.v:0.0-0.0" case 4'---- assign { } { } assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } case assign $2\be_out[31:0] 0 end attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } assign $1\be_out[31:0] 134217744 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } case assign $1\be_out[31:0] 0 end sync always update \be_out $0\be_out[31:0] end attribute \src "libresoc.v:203675.3-203684.6" process $proc$libresoc.v:203675$14532 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] attribute \src "libresoc.v:203676.5-203676.29" switch \initial attribute \src "libresoc.v:203676.9-203676.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$193 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx14[3:0] 4'1110 case assign $1\cur_idx14[3:0] \cur_idx13 end sync always update \cur_idx14 $0\cur_idx14[3:0] end attribute \src "libresoc.v:203685.3-203694.6" process $proc$libresoc.v:203685$14533 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] attribute \src "libresoc.v:203686.5-203686.29" switch \initial attribute \src "libresoc.v:203686.9-203686.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$197 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_pri15[7:0] \xive15_pri case assign $1\cur_pri15[7:0] \cur_pri14 end sync always update \cur_pri15 $0\cur_pri15[7:0] end attribute \src "libresoc.v:203695.3-203704.6" process $proc$libresoc.v:203695$14534 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] attribute \src "libresoc.v:203696.5-203696.29" switch \initial attribute \src "libresoc.v:203696.9-203696.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" switch \$201 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\cur_idx15[3:0] 4'1111 case assign $1\cur_idx15[3:0] \cur_idx14 end sync always update \cur_idx15 $0\cur_idx15[3:0] end attribute \src "libresoc.v:203705.3-203714.6" process $proc$libresoc.v:203705$14535 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] attribute \src "libresoc.v:203706.5-203706.29" switch \initial attribute \src "libresoc.v:203706.9-203706.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" switch { \reg_is_debug \reg_is_config \reg_is_xive } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign $1\ibit[0:0] \$71 case assign $1\ibit[0:0] 1'0 end sync always update \ibit $0\ibit[0:0] end attribute \src "libresoc.v:203715.3-203723.6" process $proc$libresoc.v:203715$14536 assign { } { } assign { } { } assign $0\ics_wb__dat_r$next[31:0]$14537 $1\ics_wb__dat_r$next[31:0]$14538 attribute \src "libresoc.v:203716.5-203716.29" switch \initial attribute \src "libresoc.v:203716.9-203716.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ics_wb__dat_r$next[31:0]$14538 0 case assign $1\ics_wb__dat_r$next[31:0]$14538 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14537 end attribute \src "libresoc.v:203724.3-203732.6" process $proc$libresoc.v:203724$14539 assign { } { } assign { } { } assign $0\ics_wb__ack$next[0:0]$14540 $1\ics_wb__ack$next[0:0]$14541 attribute \src "libresoc.v:203725.5-203725.29" switch \initial attribute \src "libresoc.v:203725.9-203725.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ics_wb__ack$next[0:0]$14541 1'0 case assign $1\ics_wb__ack$next[0:0]$14541 \wb_valid end sync always update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14540 end connect \$7 $ternary$libresoc.v:203095$14294_Y connect \$99 $lt$libresoc.v:203096$14295_Y connect \$101 $and$libresoc.v:203097$14296_Y connect \$103 $lt$libresoc.v:203098$14297_Y connect \$105 $and$libresoc.v:203099$14298_Y connect \$107 $lt$libresoc.v:203100$14299_Y connect \$109 $and$libresoc.v:203101$14300_Y connect \$111 $lt$libresoc.v:203102$14301_Y connect \$113 $and$libresoc.v:203103$14302_Y connect \$115 $lt$libresoc.v:203104$14303_Y connect \$117 $and$libresoc.v:203105$14304_Y connect \$119 $lt$libresoc.v:203106$14305_Y connect \$121 $and$libresoc.v:203107$14306_Y connect \$123 $lt$libresoc.v:203108$14307_Y connect \$125 $and$libresoc.v:203109$14308_Y connect \$127 $lt$libresoc.v:203110$14309_Y connect \$12 $eq$libresoc.v:203111$14310_Y connect \$129 $and$libresoc.v:203112$14311_Y connect \$131 $lt$libresoc.v:203113$14312_Y connect \$133 $and$libresoc.v:203114$14313_Y connect \$135 $lt$libresoc.v:203115$14314_Y connect \$137 $and$libresoc.v:203116$14315_Y connect \$11 $ternary$libresoc.v:203117$14316_Y connect \$139 $lt$libresoc.v:203118$14317_Y connect \$141 $and$libresoc.v:203119$14318_Y connect \$143 $lt$libresoc.v:203120$14319_Y connect \$145 $and$libresoc.v:203121$14320_Y connect \$147 $lt$libresoc.v:203122$14321_Y connect \$149 $and$libresoc.v:203123$14322_Y connect \$151 $lt$libresoc.v:203124$14323_Y connect \$153 $and$libresoc.v:203125$14324_Y connect \$155 $lt$libresoc.v:203126$14325_Y connect \$157 $and$libresoc.v:203127$14326_Y connect \$159 $lt$libresoc.v:203128$14327_Y connect \$161 $and$libresoc.v:203129$14328_Y connect \$163 $lt$libresoc.v:203130$14329_Y connect \$165 $and$libresoc.v:203131$14330_Y connect \$167 $lt$libresoc.v:203132$14331_Y connect \$16 $eq$libresoc.v:203133$14332_Y connect \$169 $and$libresoc.v:203134$14333_Y connect \$171 $lt$libresoc.v:203135$14334_Y connect \$173 $and$libresoc.v:203136$14335_Y connect \$175 $lt$libresoc.v:203137$14336_Y connect \$177 $and$libresoc.v:203138$14337_Y connect \$15 $ternary$libresoc.v:203139$14338_Y connect \$179 $lt$libresoc.v:203140$14339_Y connect \$181 $and$libresoc.v:203141$14340_Y connect \$183 $lt$libresoc.v:203142$14341_Y connect \$185 $and$libresoc.v:203143$14342_Y connect \$187 $lt$libresoc.v:203144$14343_Y connect \$189 $and$libresoc.v:203145$14344_Y connect \$191 $lt$libresoc.v:203146$14345_Y connect \$193 $and$libresoc.v:203147$14346_Y connect \$195 $lt$libresoc.v:203148$14347_Y connect \$197 $and$libresoc.v:203149$14348_Y connect \$1 $eq$libresoc.v:203150$14349_Y connect \$199 $lt$libresoc.v:203151$14350_Y connect \$201 $and$libresoc.v:203152$14351_Y connect \$204 $eq$libresoc.v:203153$14352_Y connect \$203 $ternary$libresoc.v:203154$14353_Y connect \$20 $eq$libresoc.v:203155$14354_Y connect \$19 $ternary$libresoc.v:203156$14355_Y connect \$24 $eq$libresoc.v:203157$14356_Y connect \$23 $ternary$libresoc.v:203158$14357_Y connect \$28 $eq$libresoc.v:203159$14358_Y connect \$27 $ternary$libresoc.v:203160$14359_Y connect \$32 $eq$libresoc.v:203161$14360_Y connect \$31 $ternary$libresoc.v:203162$14361_Y connect \$36 $eq$libresoc.v:203163$14362_Y connect \$35 $ternary$libresoc.v:203164$14363_Y connect \$3 $eq$libresoc.v:203165$14364_Y connect \$40 $eq$libresoc.v:203166$14365_Y connect \$39 $ternary$libresoc.v:203167$14366_Y connect \$44 $eq$libresoc.v:203168$14367_Y connect \$43 $ternary$libresoc.v:203169$14368_Y connect \$48 $eq$libresoc.v:203170$14369_Y connect \$47 $ternary$libresoc.v:203171$14370_Y connect \$52 $eq$libresoc.v:203172$14371_Y connect \$51 $ternary$libresoc.v:203173$14372_Y connect \$56 $eq$libresoc.v:203174$14373_Y connect \$55 $ternary$libresoc.v:203175$14374_Y connect \$5 $and$libresoc.v:203176$14375_Y connect \$60 $eq$libresoc.v:203177$14376_Y connect \$59 $ternary$libresoc.v:203178$14377_Y connect \$64 $eq$libresoc.v:203179$14378_Y connect \$63 $ternary$libresoc.v:203180$14379_Y connect \$68 $eq$libresoc.v:203181$14380_Y connect \$67 $ternary$libresoc.v:203182$14381_Y connect \$71 $shr$libresoc.v:203183$14382_Y [0] connect \$73 $and$libresoc.v:203184$14383_Y connect \$75 $lt$libresoc.v:203185$14384_Y connect \$77 $and$libresoc.v:203186$14385_Y connect \$79 $lt$libresoc.v:203187$14386_Y connect \$81 $and$libresoc.v:203188$14387_Y connect \$83 $lt$libresoc.v:203189$14388_Y connect \$85 $and$libresoc.v:203190$14389_Y connect \$87 $lt$libresoc.v:203191$14390_Y connect \$8 $eq$libresoc.v:203192$14391_Y connect \$89 $and$libresoc.v:203193$14392_Y connect \$91 $lt$libresoc.v:203194$14393_Y connect \$93 $and$libresoc.v:203195$14394_Y connect \$95 $lt$libresoc.v:203196$14395_Y connect \$97 $and$libresoc.v:203197$14396_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 connect \max_pri 8'11111111 connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } connect \wb_valid \$5 connect \reg_idx \ics_wb__adr [3:0] connect \reg_is_debug \$3 connect \reg_is_config \$1 connect \reg_is_xive \ics_wb__adr [9] end